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Analog Labs Manual

1. N ZU 1589 Bad dim wU gp nmo HZ EX LL Lx a U a D En D d Bm m aie DL BEGI eee 1 pmeaz am i I 1565n b gm mesi MS anma cadence Analog lab manual cadence Schematic Entry Objective To create a new cell view and build A XOR gate Use the techniques learned in the Lab2 1 to complete the schematic of XOR gate This is a table of components for building the XOR gate schematic nind name Cell Name Properties Comments kasia Pmos Model Name pmos1 pmos2 pmos3 pmos4 gpdk180 Nmos Model Name nmos1 nmos2 nmos3 nmos4 Type the following in the ADD pin form in the exact order leaving space between the pin names Analog lab manual ra cadence Objective To create a symbol for the XOR gate Use the techniques learned in the Lab2 1 to complete the symbol of XOR gate Analog lab manual cadence Building the XOR Gate Test Design Objective To build cmos xor test circuit using your cmos xor Using the component list and Properties Comments in the table build the cs amplifier test schematic as shown below Library name Properties Comments Define pulse specification as analogLib vpulse In lab 2 1 analogLib vdd vss gnd vdd 1 8 vss 1 8 Analog lab manual ra cadence Objective To set up and run simulations on the XOR gate design Use the techniques learned in the Lab2 1 to complete the simulation of XOR gate ADE window an
2. Info Argument mode is not used From IC614 orwards ViVA runs with XL mode Loading viva cxt Loading awx cxt Loading oasis cxt mouse L 2 amp root localhost scratch Log root CDS log 2 s Virtuoso R Visualization amp Analy Analog lab manual cadence o Examine the visulization amp Analysis browser a Select the Append and open the Database cadence analog labs 613 Diff amplifier raw file sse B Applications Actions Tue Feb 28 21 46 v Virtuoso R Visualization amp Analysis XL browser EY 3 File Tools Options Help cadence Replace Select Waveform Database EJ Directory Name cratc h JNTUSOLUTIONS Diff_amplifier raw EE scratch EFS JNTLUSOLLUTIONS L Diff_amplifier raw B inverter raw OK Apply Refresh Cancel S ia 2 Open Results e E amp root amp localhost scratch Log root CDS log 2 a Virtuoso R Visualization amp Analys 8 For transient analysis Click on trans trans vout and vin soe Applications Actions Q9 Vm S GD TueFeb28 21 47 pas Virtuoso R Visualization amp Analysis XL browser l Eal Active Graph Window 3 e rx File Tools Options Help cadence File Edit Fram Grap Axis Trac Marke Zoon Tool Measureme Helradence S 20S ORS E nS R MSE See U Gppend e 3 E Q F Feb 28 2012 Transient Analysis tran time O s gt 4 ms ea Dy Xe EE 7 5tvn FDiff amplifier raw bd E 5 0 EE sc
3. m mouse L 1 Z ES root amp P localhost scratch Log root CDS log 2 P Virtuoso R Visualization amp Analy gt Analog lab manual cadence 7 Examine the visulization amp Analysis browser a Select the Append and open the File Database cadence analog labs 613 inverter raw s 2s E Applications Actions Ve amp LLL TueFeb 28 20 16 N Virtuoso R Visualization amp Analysis XL browser File Tools Options Help c dence Select Waveform Database e Directory Name fscratch JINTUSOLUTIONS sinverter raw EFRO Z Erf scratch Erf JNTUSOLLITIONS Location inverter raw Refresh _ Cancel AL SAT S 2 Open Results lt BS root localhost scratch C Log root CDS log 2 W Virtuoso R Visualization amp Analy 8 For transient analysis Click on trans trans vout and vin E gt as E amp Applications Actions gt e Tue Feb 28 20 19 Virtuoso R Visualization amp Analysis XL browser File Tools Options Help ac ap ae i Active Graph Window 5 RETE File Edit Frame Graph Axis Trace Marker zoom Tools Measurement Help Append MIS File Edi Frame Graph Axis Trace Marker Zoom Tools Measurement Helpadence padence AL Xem mSS P E 5x 4P e E3 ae fl nverter raw Feb 28 2012 Transient E L MIS SERE ee Ua Scc ee AN tran time 0s 100 ns 2 0 Signals 1 75 Er Et scratchz JIN TUSOLUTIONS inverter raw O fi
4. 1 Spice code of PMOS PMO vout vin vdd vdd pmos1 w 2u 1 180n as 1 2p ad 1 2p ps 5 2u pd 5 2u m 1 1 In which ad and as are the areas of source and drain diffusion pd and ps are the value of the perimeter of the source and drain End of lab 4 Analog lab manual DONE cadence Lab 5 1 SPICE Simulation of Basic Analog Circuits Inverter A Inverter 1 Log in to your workstation using the username and password The home directory has a cshrc file with paths to the Cadence installation 2 In a terminal window type csh at the command prompt to invoke the C shell gt csh gt source cshrc 3 Change to the course directory by entering this command gt cd Database cadence_analog labs_613 4 In the same terminal window observe the code of inverter and close gedit inverter scs i Eile Edit View Search Tools Documents Help c LU amp x e E B KS New Open Save Print i Undo Redo Cut Copy Paste Find Replace _inverter scs imulator lang spectre global O include scratch database scratch varal cadence cadence ms labs 613 models spectre gpdk scs section stat NMO Cvout vin O O nmos1i1 w 2u 1 180n as 1 2p ad 1 2p ps 5 2u pd 5 2u m 1 C1 PMO Cvout vin vdd vdd pmosi w 2u 1 180n as 1 2p ad 1 2p ps 5 2u pd 5 2u m 1 7 C 1 V1 C Cvin O vsource type pulse valO O vali1 1 8 period 40n delay in rise in fall in width 20n V3 vdd O vsource dc 1
5. 78 9 step 36 mV 2 95 dc dc 1 44 V 80 9 step 36 mV 2 dc dc 1 476 V 82 step 36 mV 2 96 qc dc L 512 V 84 step 36 mV 2 dc dc 1 548 V 86 step 36 mV 2 90 dc dc 1 584 V 88 9 step 36 mV 2 95 dc dc 1 62 V 90 9 step 36 mV 2 9 dc dc 1 656 V 92 9 step 36 mV 2 95 dc dc 1 692 V 94 step 36 mV 2 dc dc 1 728 V 96 95 step 36 mV 2 95 dc dc 1 764 V 98 9 step 36 mV 2 95 dc dc 1 8 V 100 step 36 mV 2 95 Total time required for dc analysis dc CPU 17 998 ms elapsed 396 262 ms Time accumulated CPU 398 938 ms elapsed 1 42737 s Peak resident memory used 24 2 Mbytes Aggregate audit 8 13 12 PM Tue Feb 28 2012 Time used CPU 424 ms elapsed 1 48 s util 28 5 Time spent in licensing elapsed 128 ms percentage of total 8 63 Peak memory used 24 2 Mbytes spectre completes with O errors O warnings and O notices 20 13 12 cdslmd IN Virtuoso Spectre root localhost localdomain root localhost JNTUSOLUTIONS T lt E rote localhost scratch um 4 Open Virtuoso visulization amp Analysis browser gt viva Diff amplifier scs s x E Applications Actions V GD Tue Feb 28 21 46 Virtuoso R Visualization amp Analysis XL browser x Eile Tools Options Help c dence Signals Search Log root C D S log 2 File Tools Options Help
6. 86 step 36 mV 2 dc dc 1 584 V 88 step 36 mV 2 95 dc dc 1 62 V 90 9 step 36 mV 2 95 dc dc 1 656 V 92 step 36 mV 2 96 dc dc 1 692 V 94 step 36 mV 2 96 dc dc 1 728 V 96 9 step 36 mV 2 95 dc dc 1 764 V 98 step 36 mV 2 dc dc 1 8 V 100 step 36 mV 2 95 Total time required for dc analysis dc CPU 17 998 ms elapsed 396 262 ms Time accumulated CPU 398 938 ms elapsed 1 42737 s Peak resident memory used 24 2 Mbytes Aggregate audit 8 13 12 PM Tue Feb 28 2012 Time used CPU 424 ms elapsed 1 48 s util 28 5 Time spent in licensing elapsed 128 ms percentage of total 8 65 Peak memory used 24 2 Mbytes spectre completes with O errors O warnings and O notices 20 13 12 cdslmd IN Virtuoso Spectre root localhost localdomain root localhost JNTUSOLUTIONS T Bl root localhost scratch 6 Open Virtuoso visulization amp Analysis browser gt viva inverter scs S x E Applications Actions G 5 Tue Feb 28 20 21 Virtuoso KR Visualization amp Analysis XL browser File Replace B ESL sd F lL i Tools Options Help at Signals Search HH Log rooyCDs log 2 File Tools Options Help xInEo Argument mode is not used From IC614d onwards ViVA runs with XL mode Loading viva cxt Loading awv cxt Loading oasis cxt
7. 5 00e 06 Brin dvp 6 00e 06 hd 2 0 1 75 1 5 1 25 Eg I A 25 n n ET RRR U 50 0 100 150 200 eat Ne m ms L E TEE qn DB de TT fey es 756682mv 142633y t C gt Note Change the wp value of pmos device back to 2u and save the schematic before proceeding to the next section of the lab To do this use edit property option L Analog lab manual E cadence Creating Layout View of Inverter 1 From the Inverter schematic window menu execute Launch Layout XL A Startup Option form appears 2 Select Create New option This gives a New Cell View Form 3 Check the Cellname Inverter Viewname layout 4 Click OK from the New Cellview form LSW and a blank layout window appear along with schematic window Adding Components to Layout 1 Execute Connectivity Generate All from Source or click the icon in the layout editor window Generate Layout form appears Click OK which imports the schematic components in to the Layout window automatically 2 Re arrange the components with in PR Boundary as shown in the next page 3 To rotate a component Select the component and execute Edit Properties Now select the degree of rotation from the property edit form lo elt 6mxogJjBesas44 S5 Analog lab manual 36 cadence 4 To Move a component Select the component and execute Edit Move command Making interconnection 1 Execute Connectivity Nets Show Hide selected Incomplete Nets or click L the icon in th
8. as SchematicSymbol Cellview From Cellview Library Mame mylilesignLih Browse Call Mame Inverter From View Name schematic B To view Name symbol Tool Data Type chematicsymbol Display Cellview Edit Options OK Cancel Defaults Apply Help 3 Click OK in the Cellview From Cellview form The Symbol Generation Form appears Analog lab manual EE cadence 4 Modify the Pin Specifications as follows ___ Symbol Generation Options _ Library Mame Cell Mame View Name nylesignLib Inverter symbol Fin Specifications Attributes Left Fins A i ee ee Right Pins Y bist Tap Pins dd List Bottom Fins wss List Exclude Inherited Connection Pins S fone ww All Only these Load Save Edit Attributes Edit Labels Edit Properties ar Cancel J Apply J Help 5 Click OK in the Symbol Generation Options form 6 A new window displays an automatically created Inverter symbol as shown here Analog lab manual rm cadence Editing a Symbol In this section we will modify the inverter symbol to look like a Inverter gate symbol IR x 668 da 1 Move the cursor over the automatically generated symbol until the green rectangle is highlighted click left to select it 2 Click Delete icon in the symbol window similarly select the red rectangle and delete that 3 Execute Create Shape polygon and draw a shape similar to triangle 4 After creating the triangle press ESC key
9. basics by concentrating on designing an Inverter through automatic layout generation Then you will go ahead with completing the other layouts After that you will run DRC LVS checks on the layout Extract parasitics and back annotate them to the simulation environment After completing the parasitic back annotation flow design is ready for generating GDSII Analog lab manual EE cadence Table of Contents Gerieral DOES nudam E u edDpI Mb E 5 Lap T Layour TC Si se S ssaseeisidumusvrenete nM um PPSO IRI M ME EPPRSUPIP MM EndupRUU EIU PdseTU DRGEN 9 IET RAN AN INVERTER NE 11 S eLa 6 8 D a FG RRPT M eee 12 By FT RT AiO Eo TE EEEE E MM MM E MEAE IUE 18 Balane MEIN er TOESE DE necne E E 2 Analog Sin Ula Or WIG SPC CLC sure nEpx ue au tre teo ede pU QOIS SEU T 24 PPM SUB SESu qune dme IEIUNII UEM M MESE MEMINI DENEN EIE 33 Creato LSvotb VIew oE Invert E oec pab RIO EI E 36 Dovstcal NNT r dex e OIM ISI INIM MEAM anes EE 39 Creating the Configuration View see 45 OS Bo aha ENE D ur NR 51 BaD Z A NAND B AEG dena e 1 02382833 E EE E R EEEE 55 TO eL e E S e E E EA E E N EN E 55 ERT eT n e e E AEE EA E E AEAEE eee 56 Building the NAND Test Design sss 57 Amalosg Simulation WA OPECI Cesis iie Tesi t tu pea E dte Apa PEDEM INESSE PEU dius 58 Creanga layout view or BUSINTIDOEATOL tac vcctor iarr qund med UM MN IULII 59 Lab2 3 A XOR aU EUN RR r ennn EEr AES EREEREER E EEEN E 61 oelemadc
10. cy a WG anne nner Ee meee E enon ne NIMIUM MM EINE MM 61 OVI ee C ROSEIOEL S esos teras ont EUR tee tr Ma me MEM DR nM I MM M 62 Building the NAND Gate Test Design sss 63 LKS eR EIR TO a WiN DOG D Ouissecesdoni assai E sad MEDIE M DEI 64 Creatine a layout View Of XOR Gale ss utenti ntt bea Meet epit Ier bere eta en DEUS 65 laD2 4 A BUELOXDIDER GC SIBI e condo ino budito t WETREFAE HR mde CH DA Tar BURN o TR MEET 57 eL L E a tun ECCE A 67 VERT RT DOPO ener enema a UM MEME MM REIN MM E ene eee 68 B ildine the Full Adder Test DOSIBEE e oermerieeue buen ptt tns aae mU Una E tos Er E 69 eos SAO Se DOO seit remit eicit Ip teni eB thu 70 Creating a layout view of FULL ADDER gate 1 esee nennen nnns 7 Lap2no ALARN a o doesceeeivor dos oed sinebat au eS eee ree er ener 73 Cema EY a E R EEE EA MIR A EE E 73 DOL CEA O e N E E E E T AN 74 B ilding thelateh Test DESIT scenerna EE E Ei 75 Analog Simulation Wita 35 DO CU Ge sapone bI USUS PHIF EU UIT FMSPINM ENIM uM M DUM 76 Creatine a layout View OF LATCH amati e S E by etre eH EP ph E EE 71 Analog lab manual E cadence LID C RUE T ee ne en ne ena eee ne pM FUE EVI 79 Doberalie BE EE Va osos tcc soe teenie EMEN ME CU MEM URN UN Eq 79 VEL DOLC eT er odisse PET E EHE miM UdeMM UEM EM MUS 80 Creating a layout view of SRAM gate uu cccccsssscceceeeessseeeeeesesseeeecessesseeeeeseseeeees 8l Lab3 A GREY TO BINARY CODE CONVERTER design ccc cece eee ne ene eee eees 83 eG 00594 9
11. gt RIAA Danone aan Analog lab manual cadence Schematic Entry Objective To create a library and build a schematic of an Inverter Below steps explain the creation of new library myDesignLib and we will use the same throughout this course for building various cells that we going to create in the next labs Execute Tools Library Manager in the CIW or Virtuoso window to open Library Manager Creating a New library 1 In the Library Manager execute File New Library The new library form appears 2 In the New Library form type myDesignLib in the Name section New Library Library Mame my DesiqnLibl Directory qshan cadence_analog_labs_613 CE B B a EJ neockt 1 arelog 1 displawv drf 23 DRC FU Ea pev 1 ade viva lag leBindKeys il Eg Ls Eg spectre runi1 ade wavescan lag lib defs La dig source C spice run 1 assura_tech lib 1 libhAanager Ic 3 docs 73 stre am 1 casLag 1 tibhtanager lc zug libs oazz 3techFiles 1 eds lib nevlog log Ea models CS work cds lib oazz d arcdog 23 neacsll Ci Inverter sp 1 casLibEuitor Iag 1 schBindKeys File type Directories Design Manager Use NONE Use MHo OM Analog lab manual R cadence 3 In the field of Directory section verify that the path to the library is set to Database cadence analog labs 613 and click OK Note A technology file is not required if you are not interested to do t
12. in Ims attan User defined ConnRules ov full muyconmectL b connect Built in Llser definsd ncvlog ncelsp ncsim User detned ncverilog e Click OK 6 Execute Simulation Netlist and Run or click on the Netlist and Run icon to start the simulation You may close the netlist and log files when the simulation is finished Examining the Results 1 When the simulation completes ViVA will appear displaying the overlaid traces PLL lib PLI 1 config Jan 6 14 23 13 2006 7 File Edit Frame Graph Axis Trace Marker Zoom Tools Help S amp S HSHE ee eS BME s OES 7 Label Transient Response hi cc in EN Eldon Eup Sr rer 10 time Qus Analog lab manual ao cadence The waveforms need to be formatted to see what is happening in the loop as it locks to the input frequency 2 Change the analog traces to Strip mode by clicking on the Strip mode icon If all four analog strips are not displayed select one of them execute Trace Edit and change Strip Chart Visible Rows to a higher number This form also allows you to change trace colors and style After changing colors for better printing the ViVA display looks something like this PLL_lib PLL config Jan amp 14 23 13 2008 7 E File Edit Frame COH gal Asis Trace Marker Z unrr Tools Help Spm HS Lj cel E ee Wer TO EE oo pb Ga Ea j tabed Transient Response 10 time Cus a Note how the vco_in v
13. setup forms with the proper values for this simulation including a transient simulation of 20us Analog lab manual ao cadence Virtuoso Analog Design Environment 1 PLI lib PLET config Sohon Sotup Analyoce Variabat Outputs Simulation Beosultte Toox Hol cadence 5 Statut Ready TaZ C o Simulator amcispertre Mode baich Stare stated Design Saari bers Analyses Type Ense FPuagurents 1 ran v 3 20 moderal amp ne ignal Esgr IVase Pot Save Save Opilons ves Plotting mede b emacs 6 Plot Quiputs a Verify the MOSFET models are set to models basicMos scs under Setup Model Libraries b Select Setup Connect Rules and select User defined Connect Rules Note If a pop up display reports an error that you cannot select the built in rules because the cds lib file does not include a reference to connectLib you can ignore the message because you will be using locally defined connect rules Close the error window c In the Select Connect Rules form in the User defined rules section browse to find ConnRules 5V full in the myconnectLib library Close the browser window after highlighting ConnRules 5V full which will copy it to the Select Connect Rules form d Click on the Add button to add the ConnRules 5V full Connect Rules to the simulation The form should look like this Analog lab manual m cadence armis Select Connect Rules List of Connect Rules Used
14. window in the new myDesignLib library and build the inverter schematic as shown in the figure at the start of this lab 1 In the CIW or Library manager execute File New Cellview 2 Set up the New file form as follows New Elle File Library nM Desin nL Ib Cell Inverter M LB schematic Type schematic S Application Mpen with schematics L IMS S Use this application for this type of file Library path file wer darshan cadence analog labs 613 cds 1ib Cancel Help Analog lab manual m cadence Do not edit the Library path file and the one above might be different from the path shown in your form 3 Click OK when done the above settings A blank schematic window for the Inverter design appears Adding Components to schematic 1 In the Inverter schematic window click the Instance fixed menu icon to display the 5 Add Instance form Tip You can also execute Create Instance or press i 2 Click on the Browse button This opens up a Library browser from which you can select components and the symbol view You will update the Library Name Cell Name and the property values given in the table on the next page as you place each component 3 After you complete the Add Instance form move your cursor to the schematic window and click left to place a component This is a table of components for building the Inverter schematic name Cell Name Prope
15. y WT S lp MIL be E suhSinqleselectPt E schdomeFit l 0 9 x Analog lab manual ao cadence Compiling the Connect Rules and Modules 1 Change to the ADElab directory If the directory in which the AMS Designer directory is located is not your login directory then replace the with the correct path cd AMSDesigner ADElab The contents of this directory are the design contained in the PLL lib directory a model file in the models directory a cds lib file a directory containing Connect Modules and rules and an artist states file which can be used to load the ADE form to save time 2 Compile the Connect Rules and Modules by running the compileConnect script The Connect Rules and Modules will be used to do the level translation between analog ports and digital ports compileConnect Starting the Software 1 Start virtuoso virtuoso amp Note The ampersand amp places the command into a background task so the window can be reused The Command Interpreter Window CIW appears You may close the What s New window if it appears File Close 2 Open the Library Manager from the CIW Tools Library Manager Setting Up and Running the Simulation 1 From the PLL lib library select the config view of the PLL1 cell and double click on it The config view is a specific configuration of the design that binds selected views to the cells and reflects the settings in the Hierarchy Editor Select
16. 021 6m coins ORE c 83 BO A ON use NIMM NEIFEM EMEN E NINE M 84 Creating a layout view of GREY TO BINARY CODE CONVERTER 85 Lab4 Introduction to SPICE Simulation and coding of NMOS PMOS Circuits 608 86 Lab 5 1 SPICE Simulation of basic Analog Circuits InYere r see e 88 Lab 5 2 SPICE Simulation of Basic Analog circuits Differential amplifier 92 Lab 6 COMMON SOURCE AMPLIFIER siescstuccsssecncsussanrevecne cases E E EE 97 Schematic Entry see 98 S AO EERE 1610 NN E RD m 99 Building the Common Source Amplifier Test Design sss sese 99 Analog Simulation with Spectre eee 101 Creating a layout view of Common Source Amper sese 102 I Ee p oi P te EIEEE EN 104 DCC MIAUIC MERC T n 105 Compiling the Connect Rules and modules 105 Diario OS DONNI Oene eens UTCU RES tet EA ENG rt LSU tU LEA END RUND CHE ENdA 105 setting Up and Running the simulation ccc cece cece cece cece e cece eene 107 E caminino the JS CSS terete cesarean Ea arene esas ey Vete DIE etu PIN DUM MN ET EUN 108 Analog lab manual LEN cadence General Notes There are a number of things to consider before beginning these lab exercises Please read through this section completely and perform any needed steps in order to ensure a successful workshop These labs were designed for use with Incisive Unified Simulator82 IC613 and Assura32 Before r
17. 2 5 n 2 5 5 0 i26 6mv 7 i12mw de D z Open Results a Z ES root localhost scratch E Log root C D5 log 2 a Virtuoso R Visualization f Active Graph Window 4 10 For AC analysis Click on ac ac and vout 59 Tue Feb 28 21 48 o S I amp Applications Actions i Virtuoso R Visualization amp Analysis XL browser TEE E Active Graph Window 5 E 2 mI File Tools Options Help cadence Fil Ed Fram Grap Axi Trat Mark Zool Too Measuren Hela dence Ebes R i E H H T Feb 28 2012 AC Analysis ac freq 1 Hz gt 500 GHz b Default Ed egnitude X NR 05 E 9 eDi _ amplifier raw Ea T 125 0 z scratch x z dm rESoLLFTICOrPmSz 7Diff amplifier ra Signals Search Er Eg EE E tran tran Ga finalTimedcF infa Pin 23g deOp udc 100 0 H 2g dc Opinto into E Ba dc dc E FE modelParameter into GI 23g elementinto GI 23g outputParameterinta 75 0 Gl 23 designParam als info E Gl ig primitives into primitives 5x00 25 0 O 25 0 T T T T T T T T T T T oF 10 1067 108 10 10130110 9z 8523kHz 1o1 94297w red tHe e Open Results TE a EE root amp P localhost scratch Log root C DS log 2 j Virtuoso R Visualizatior f Active Graph Window 5 ml Analog lab manual cadence 11 To Calculate the gain of Differential pair select calculator from ac output wave form then select t
18. 5 Execute Create Shape Circle to make a circle at the end of triangle 6 You can move the pin names according to the location 7 Execute Create Selection Box In the Add Selection Box form click Automatic A new red selection box is automatically added 8 After creating symbol click on the save icon in the symbol editor window to save the symbol In the symbol editor execute File Close to close the symbol view window Analog lab manual 20 cadence Building the Inverter Test Design Objective To build an Inverter Test circuit using your Inverter Creating the Inverter Test Cellview You will create the Inverter Test cellview that will contain an instance of the Inverter cellview In the next section you will run simulation on this design 1 In the CIW or Library Manager execute File New Cellview 2 Set up the New File form as follows Library Cell Inverter x LP schematic Type schematic Application Gpen with schematics L Ea IMS S Use this application for this type of file Library path file wr darshan cadence analog labs 6bilarcda Lib CELI cancel 696 3 Click OK when done A blank schematic window for the Inverter Test design appears Analog lab manual DEN cadence Building the Inverter Test Circuit 1 Using the component list and Properties Comments in this table build the Inverter Test schematic Library name Cellview name Properties Comments myDesignL
19. 8 type dc tran tran stop 100n write spectre ic writefinal spectre fc annotate status maxiters 5 dc dc dev V1 param dc start O stop 1 8 oppoint rawfile maxiters 150 maxsteps 10000 annotate status save vout vin Ln 1 Col 1 INS 4B Screenshot png B root amp localhost scratch scratch JNTUSOLUTION S inver mE Analog lab manual 3mm cadence 5 Compile the inverter scs code gt spectre inverter scs e a amp Applications Actions e 9 Tue Feb 28 20 13 root localhost scratch File Edit View Terminal Tabs Help de de 864 mV 48 step 36 mV 2 dc de 900 mV 50 step 36 mV 2 9 dc dc 936 mV 52 step 36 mV 2 95 dc dc 972 mV 54 step 36 mV 2 965 dc dc 1 008 V 56 9 step 36 mV 2 dc dc 1 044 V 58 step 36 mV 2 95 dc dc 1 08 V 60 step 36 mV 2 90 dc dc 1 116 V 62 9 step 36 mV 2 dc de 1 152 WV 64 step 36 mV 2 9 dc dc 1 188 V 66 9 step 36 mV 2 95 dc dc 1 224 V 68 step 36 mV 2 9 dc dc 1 26 V 70 step 36 mV 2 96 dc dc 1 2868 V 72 step 36 mV 2 dc dc 1 332 V 74 9 step 36 mV 2 95 dc dc 1 368 V 76 9 step 36 mV 2 90 dc dc 1 404 V 78 9 step 36 mV 2 96 dc dc 1 44 V 80 9 step 36 mV 2 95 dc dc 1 476 V 82 9 step 36 mV 2 qc dc L 312 V 84 95 step 36 mV 2 95 dc dc 1 548 V
20. ADDER vdd instanceNamelcarry sum Analog lab manual cadence Building the Full Adder Test Design Objective To build full adder test circuit using your full adder Using the component list and Properties Comments in the table build the Full adder test schematic as shown below Library name Cellview name Properties Comments myDesignLib cmos FULL ADDER Symbol Define pulse specification as analogLib vpulse In lab 2 1 analogLib vdd vss gnd vdd 1 8 vss 1 8 Virtuoso Analog Design Environment 3 Hsolutions full adder schematic Session setup Analyses Variables Outputs Simulation Results Tools Help cadence idi Mii Twpe Enable Arguments jt 7 tran ra 0 160n moderate me S me Trans WamesSignalvExpr Value Plot Save Save Options La wt ally eh E ally h y mc Ll all 4 sum Cd ally g Carry w allv Plot after simulation Auto Plotting mode Replace i mmause Ls MA Ri tatzo Save State Status Ready T 27 Simulator spectre Analog lab manual rau cadence Analog Simulation with Spectre Objective To set up and run simulations on the FULL ADDER design Use the techniques learned in the Lab2 1 to complete the simulation of FULL ADDER ADE window and waveform should look like below Active Hsolutions full adder schematic Feb 28 21 33 03 2012 26 File Edit Frame Graph Axis Trace Marker Zoom Tools Measurement
21. Ectit Aper Piogins Help cade in ce I Ns RI n NIRE TT ce Lek Sen Lm es Global Bindings _ FERRE TET Merr Configuration Library Cel XV ben Library myOesiqnLibl Ea Cel Inverter Test k OPE d E ien L Table Global Bindings Cel Gi Library List o d wes List Stop List lmonstraint List Description m Hane SCT ID o Cus Analog lab manual ES cadence 4 Click Use template at the bottom of the New Configuration form and select Spectre in the cyclic field and click OK The Global Bindings lists are loaded from the template Use Tem plate Template Pd ame Other gt slthers From File Kl SUL ws hspicerp spectreverilog system erilog erilag xs ndlinteg 5 Change the Top Cell View to schematic and remove the default entry from the Library List field 6 Click OK in the New Configuration form TT E Se New Configuration 2 ES Top Cell Library jprmyOesiqnLlib Ea lel jInverter Test schematic Shobha Bindings v em Library List view List spectre cmas_ sch crmos sch schematic veriloga ahdl stop List spectre lonstraint List P Description rate Please remember to replace Top cell Library Cell and Tes fields with the actual names used by your design 0 Cancel Use Template levee The hierarchy editor displays the hierarchy for this design using
22. Made qnd Mult Factor 1 0 Extraction Type Analog lab manual ram cadence 4 In the Filtering tab of the form Enter Power Nets as vdd vss and Enter Ground Nets as gnd Enter Power Mets From File aelFramasch Enter Ground Mets From File SelFromach 5 Click OK in the Assura parasitic extraction form when done The RCX progress form appears in the progress form click Watch log file to see the output log file o When RCX completes a dialog box appears informs you that Assura RCX run Completed successfully 6 You can open the av extracted view from the library manager and view the parasitic Analog lab manual ru cadence Creating the Configuration View In this section we will create a config view and with this config view we will run the simulation with and without parasitic 1 In the CIW or Library Manager execute File New Cellview 2 In the Create New file form set the following T x T Tq HE AE tirare imyDesignLbib Ea E Inverter Test M LGV config Type config Application n Open with Hierarchy Editar Always use this application far this type of file Library path Tile rerdarshanr cadence e analog labs 613 cds Lib TID ce H 3 Click OK in create New File form The Hierarchy Editor form opens and a New Configuration form opens in front of it Hw Prt w Hierarchy E ditor m File
23. ab and click OK 4 In the Virtuoso XStream Out form click Translate button to start the stream translator 5 The stream file Inverter gds is stored in the specified location Streaming In the Design 1 Select File Import Stream from the CIW menu and change the following in the form iv Virtuoso R XStream In Stream File lexportihomedarshanicadence analog labs B13 Inverter ads Destination Library DDS LIB Y Attach Technology Library pak T 80 Top Cell Inverter T Load ASCII Tech File lexportihomeJdarshanicadence analog labs 61 sitechFilesigpdk 180 oa22 tt Options Load File Translate Cancel tar pj e haaa Load Template Save Template F lia y Help Reset Options Analog lab manual Rw cadence You need to specify the gpdk180 oa22 tf file This is the entire technology file that has been dumped from the design library 2 Click on the Options button 3 In the StreamOut Options form select Use Automatic Mapping under Layers tab and click OK 4 In the Virtuoso XStream Out form click Translate button to start the stream translator o From the Library Manager open the Inverter cellview from the GDS LIB library and notice the design 6 Close all the windows except CIW window which is needed for the next lab END OF LAB 2 1 Analog lab manual Em cadence Schematic Capture vdd a pmos J PME WM pmo
24. ab manual FEN cadence S Iw Virtuoso 6 1 3 Log home darshan CDS log 8 fx File Tools Options Help cadence COPYRIGHT 1992 2009 CADENCE DESIGN SYSTEMS INC ALL RIGHTS RESERVED 1992 2009 UNIX SYSTEMS Laboratories INC Reproduced with permission This Cadence Design Systems program and online documentation are proprietary confidential information and may be disclosed used only m m 1 F TH R ddsOnLineHelpimait mouse L awvhiousesingleselectFIC Bi hd 1 gt 3 If the What s New window appears close it with the File Close command What s New in 6 1 3 500 File Edit Help cadence The information in this window is current for the IC 6 1 release and contains these sections l VIRTUOSO DESIGN ENVIRONMENT ON OPENACCESS 2 VIEWING IC 6 1 PLATFORM DOCUMENTATION 3 STARTING USER DOCUMENTATION FROM THE cdsinit FILE 4 Keep opened CIW window for the labs End of General Notes Analog lab manual e cadence Lab 1 Layout Design Rules The physical mask layout of any circuit to be manufactured using a particular process must conform to a set of geometric constraints or rules which are generally called layout design rules These rules usually specify the minimum allowable line widths for physical objects on chip such as metal and polysilicon interconnects or diffusion areas minimum feature dimensions and minimum all
25. arameterz are set view avicompareRules _ Modify avCompareRules 1ToavCompare rule is set View Additional Functions MHo additional functions are set ok P Cancel J Apply J Defaults J Load State J Save State J view RSF J Help 3 The LVS begins and a Progress form appears Analog lab manual ram cadence 4 If the schematic and layout matches completely you will get the form displaying Schematic and Layout Match 5 If the schematic and layout do not matches a form informs that the LVS completed successfully and asks if you want to see the results of this run 6 Click Yes in the form LVS debug form appears and you are directed into LVS debug environment 7 In the LVS debug form you can find the details of mismatches and you need to correct all those mismatches and Re run the LVS till you will be able to match the schematic with layout Assura RCX In this section we will extract the RC values from the layout and perform analog circuit simulation on the designs extracted with RCX Before using RCX to extract parasitic devices for simulation the layout should match with schematic completely to ensure that all parasites will be backannoted to the correct schematic nets Running RCX 1 From the layout window execute Assura Run RCX 2 Change the following in the Assura parasitic extraction form Select output type under Setup tab of the form Analog lab manual ru cad
26. cadence Analog Labs Manual Revision 1 0 IC614 ASSURA410 MMSIM 101 Developed By University Support Team Cadence Design Systems Bangalore Analog lab manual DE cadence Objective Objective of this lab is to learn the Virtuoso tool as well learn the flow of the Full Custom IC design cycle You will finish the lab by running DRC LVS and Parasitic Extraction on the various designs In the process you will create various components like inverter NAND gate XOR gate Full adder Latch SRAM register cell grey to binary code converter and PLL differential amplifier we won t be designing every cell as the time will not be sufficient instead we will be using some ready made cells in the process You will start the lab by creating a library called myDesignLib and you will attach the library to a technology library called gpdk180 Attaching a technology library will ensure that you can do front to back design You will create a new cell called Inverter with schematic view and hence build the inverter schematic by instantiating various components Once inverter schematic is done symbol for Inverter is generated Now you will create a new cell view called Inverter Test where you will instantiate Inverter symbol This circuit is verified by doing various simulations using spectre In the process you will learn to use spectre waveform window options waveform calculator etc You will learn the Layout Editor
27. compute the hierarchy icon the configuration is now updated from schematic to av extracted view 6 From the Analog Design Environment window click Netlist and Run to start the simulation again 7 When simulation completes note the Circuit inventory conditions this time the list shows all nets designed devices sources and parasitic devices as well 8 Calculate the delay again and match with the previous one Now you can conclude how much delay is introduced by these parasites now our main aim should to minimize the delay due to these parasites so number of iteration takes place for making an optimize layout Generating Stream Data Streaming Out the Design 1 Select File Export Stream from the CIW menu and Virtuoso Xstream out form appears change the following in the form EM Virtuoso R XStream Out atream File fexporthomendarshanicadence analog labs B13 lnverter gds Technology Library gpdk 150 Library Toplevel Celis Inverter Wiew layout Options Load Hierarchy Translate v Cancel Load Template Save Template Help Reset Options OE RAPE aT Po Sa Pa k ll h Pe a Analog lab manual cadence 2 Click on the Options button 3 In the StreamOut Options form select Z Use Automatic Mapping under Layers t
28. d waveform should look like below Applications Actions ASA AS AED s Tue Feb 28 21 16 Q Active Hsolutions cmos_xor_test schematic Feb 28 21 15 48 2012 17 File Edit Frame Graph Axis Trace Marker Zoom Tools Measurements Help cadence Sme NRI SP E 2C 4 c ES x label Feb 28 2012 Transient Response 2 0 LS 0 50 0 100 150 200 70 105ns 1 71189V time ns Analog lab manual cadence Use the techniques learned in the Lab1 and Lab2 to complete the layout of XOR gate Complete the DRC LVS check using the assura tool Extract RC parasites for back annotation and Re simulation I I Analog lab manual cadence Lab 2 4 A FULL ADDER Schematic Capture PMIDE iliius nenga HH hino n m D E Analog lab manual cadence Schematic Entry Objective To create a new cell view and build A FULL ADDER gate Use the techniques learned in the Lab2 1 to complete the schematic of FULL ADDER gate This is a table of components for building the FULL ADDER gate schematic jr name Cell Name Properties Comments bni Pmos Model Name pmos1 pmos2 pmos3 pmos4 gpdk180 Nmos Model Name nmos1 nmos2 nmos3 nmos4 Type the following in the ADD pin form in the exact order leaving space between the pin names Analog lab manual ru cadence Objective To create a symbol for the FULL ADDER Use the techniques learned in the Lab2 1 to complete the symbol of FULL
29. dc dc VIE 15 ARD oO 0 2 0 1 75 1 5 1 25 1 0 OES m 25 a ps 25 0 50 0 41 465ns 886 905mv time ns graphi label 1 amp Open Results BE root amp localhost scratch Log root C D5S log 2 M Virtuoso R Visualization Active Graph Window 5 EL J Analog lab manual cadence 9 For DC analysis Click on dc dc vout Lm as E amp Applications Actions S H Tue Feb 28 20 18 ka Virtuoso R Visualization amp Analysis XL browser ie File Tools Options Help cadence m fa Active Graph Window4 lt TB T 5 LE L uw d File Edit Frame Grapl Axis Trace Marke Zoorr Tool Measuremei Helrad ence A xIt e messem ur 264 EA Zabel Jinverter raw Feb 28 2012 DCc Analhsis dc vI dc 0v gt 1 8 wv E EF amp scratch JNTLISOLLITIORNS inverter rav Bout H 5g tran tran ES SB Da de de n LEES vin 1 75 1 5 1 25 1 0 fo e o 0 25 e 749 203mv 860 107mVv A gt Z Open Results E root localhost scratch c Log root CD5S log 2 Virtuoso R Visualization Active Graph Window 4 ELJI End of lab 5 1 Analog lab manual ra cadence Lab 5 2 SPICE Simulation of Basic Analog Circuits Differential amplifier 1 Change to the course directory by entering this command gt cd Database cadence analog labs 613 2 In the same terminal window observe the spice code of differential amplifier and close gedit Diff am
30. e Circuit with Parasites In this exercise we will change the configuration to direct simulation of the av extracted view which contains the parasites 1 Open the same Hierarchy Editor form which is already set for Inverter Test config 2 Select the Tree View icon this will show the design hierarchy in the tree format 3 Click right mouse on the Inverter schematic A pull down menu appears Select av extracted view from the Set Instance view menu the View to use column now shows av extracted view EU Hierarchy E ditor myDesignLib Inverter_Test contig File Edit View Plugins Help cadence lee she ees uvm Global Bindings Library myDesignLib B Library List miyDesigqnLib Cell Inverter Test Set Instance rex nanmne irm EHOW Expand instance av extracted Expand By Instance Group layout Explain schematic pen lt a Open symbol ai HIE ig Source File Add Stop Point le Reference Verilog Remove Stop Point Table view Tree View Target Instance Inherited View List Instance li EI E imyDesignLib Inverter Test schematic ee me 10 mM DesTmanL TR Inverter schematic Add Bind To Open Remove Bind To Open MECE Cres sch cmos sch L ST VO fanaloglib vpulse spectre spectre cmas sch cmos sch H 59 VT fanaloglib vde spectre spectre cmos sch cmos sch m Mamespace COBS Filters OFF ams Analog lab manual 50 cadence 4 Click on the Re
31. e Layout Menu 2 Move the mouse pointer over the device and click LMB to get the connectivity information which shows the guide lines or flight lines for the inter connections of the components 3 From the layout window execute Create Shape Path Create wire or Create Shape Rectangle for vdd and gnd bar and select the appropriate Layers from the LSW window and Vias for making the inter connections Creating Contacts Vias You will use the contacts or vias to make connections between two different layers 1 Execute Create Via or select command to place different Contacts as given in below table Connection Contact Type For Metall Poly Metal1 Poly Connection For Metall Metall1 Psub Psubstrate Analog lab manual ao cadence Connection For Metall Nwell Metal1 Nwell Connection Saving the design ii 1 Save your design by selecting File Save or click to save the layout and layout should appear as below Analog lab manual EXE cadence Physical Verification Assura DRC Running a DRC 1 Open the Inverter layout form the CIW or library manger if you have closed that Press shift f in the layout window to display all the levels 2 Select Assura Run DRC from layout window The DRC form appears The Library and Cellname are taken from the current design window but rule file may be missing select the Technology as gpdk180 This automatically loads the rule file Your DRC form
32. e directory by entering this command gt cd Database cadence analog labs 613 Analog lab manual m cadence You will start the Cadence Design Framework II environment from this directory because it contains cds lib which is the local initialization file The library search paths are defined in this file The Cadence Analog labs 613 directory contains Solutions folder and also Work folder Inside Work folder you can create new cell modifications of the cell locally without affecting your Source cell present inside Solutions directory Directory Solutions libs cdb models stream pV techfiles dig source cds lib hdl var docs Directory Contains a local copy of all the lab experiments including test circuit for simulation Contains a technology library for the design gpdk180nm Contains spectre models of components for simulation in gpdk180nm technology Contains layer map file for GDSII format Containing the Assura and Diva verification files Contains ASCII versions of the oa22 techfiles Contains verilog codes for SAR register and clock File containing pointer to the Cadence OA22 initialization file File defines the work library for AMS simulation Reference manual and user manual for gpdk180nm technology 2 In the same terminal window enter gt virtuoso amp The virtuoso or Command Interpreter Window CIW appears at the bottom of the screen Analog l
33. e enable button and then click Apply Analog lab manual am cadence Analysis tran dc Mc AES hose ww c Serres GC m at r Sth pz 8p e Brvip pes Pac psth praise we Por psp _ pss eu Opac Opnoise PET Opsp c hk Khas hbnoize De Analysis Save pe operating Point Hysteresis MTG G D Sweep vwvarialhie Component Parme wo Temperature Design NP arable c Select Component m X ompanent Parameter Parameter Mame oc Podel Parameter Sweep Range tet Eee Start nu Stop 1 8 co lenterspan Sweep Type amp WTO ree tic Add Specific Points L3 Enabled xw O cpttans Cancel J Defaults Apply Help 4 Click OK in the Choosing Analyses Form Setting Design Variables Set the values of any design variables in the circuit before simulating Otherwise the simulation will not run 1 In the Simulation window click the Edit Variables icon The Editing Design Variables form appears 2 Click Copy From at the bottom of the form The design is scanned and all variables found in the design are listed In a few moments the wp variable appears in the Table of Design variables section 3 Set the value of the wp variable With the wp variable highlighted in the Table of Design Variables click on the variable name wp and enter the following Analog lab manual DOE cadence Value Expr Click Change and notice the update i
34. egrated Circuits Emphasis A SPICE input file called source file consists of three parts 1 Data statements description of the components and the interconnections Ex Voltage source statement Vname N1 N2 Value Type V1 2 O vsource dc 10 type dc N1 is the positive terminal node N2 is the negative terminal node Type can be DC AC or TRAN depending on the type of analysis Value gives the value of the source 2 Control statements Tells SPICE what type of analysis to perform on the circuit Ex DC Statement This statement allows you to increment sweep an independent source over a Certain range with a specified step The format is as follows DC oRCname SIART STOP SIEP dc dc dev V1 param dc start O stop 1 8 oppoint rawfile maxiters 150 maxsteps 10000 annotate status In which SRC name is the name of the source you want to vary START and STOP are the starting And ending value respectively and STEP is the size of the increment Analog lab manual ra cadence 3 Output statements specifies what outputs are to be printed or plotted Ex Save vout vin Coding of MOS The MOS transistor name Nname has to start with a M ND NG NS and NB are the node numbers of the Drain Gate Source and Bulk terminals respectively ModName is the name of the transistor model L and W are the length and width of the gate Spice code of NMOS NMO vout vin O 0 nmosl1 w 2u 1 180n as 1 2p ad 1 2p ps 5 2u pd 5 2u m 1
35. ence ORC Assura Parasitic Extraction Run Form Setup Extraction Filtering Metlishg RunDetais Substrate Technology pakian RuleSet default r3 pelvsset NOME E l UseMutRuleSets setup Dir fhome darshan cadencse analog labs 61l3 pv assura rcx RSF Inelude Oo e Wiew Edit Rule RSF Include ey ieg Edit Tech Cmd File Default E aa de Ea utput Extracted View Lib DesignLib Cel Inverter View av extracted able CellView Check kad rasitic Res Component presistor Prop Id r rasitic Cap Component peapacitor i it tS Prop Id S rasitic Ind Component pinductor Prop Id L rasitic hd Component gmind Prop Id k ductance L1 Prop Id indl Inductance Le Prop Ia ind2 ll Procedure hstrate Extract kad Extract MOS Diffusion Res L ract MOS Difusion AF v Add LYS MOS Diffusion Res i hstrate Profile None M Extract MOS Diffusion High None P brary Prefix Doo brary Directory be gay m Ba Cancel J Defaults Apply J Load State Save State J ViewRSF J Help ail 3 In the Extraction tab of the form choose Extraction type Cap Coupling Mode and specify the Reference node for extraction P ORC Assura Parasitic Extraction Run Form Setup Extraction Filtering Netlisting Run Details Substrate RE Mame Space Layout Names Max fracture length infinite microns Temperature 25 0 G Cap Coupling Mode Coupled Ref
36. esponse I Jun 25 2009 DC Response 2 Eo Evin mee Vout Sain 2 0 1 75 1 5 1 25 Sa 75 5 25 i zb LE ace T A 0 0 50 0 100 150 200 0 0 25 5 5 1 0 1 25 1 5 1 75 2 0 100 23n 88r 235mw Mens 1i 58832v i 50s32y 06 gt graphi selected double click to bring Up attribute dialog Analog lab manual cadence Saving the Simulator State We can save the simulator state which stores information such as model library file outputs analysis variable etc This information restores the simulation environment without having to type in all of setting again 1 In the Simulation window execute Session Save State The Saving State form appears 2 Set the Save as field to statel inv and make sure all options are selected under what to save field 3 Click OK in the saving state form The Simulator state is saved Loading the Simulator State 1 From the ADE window execute Session Load State 2 In the Loading State window set the State name to statel inv as shown Analog lab manual Em cadence Loading State Virtuoso Analog Design Environment 1 State Load Directory e actist states Browse Library mybesiqnLib Zell Inverter Test EE Simulator jspectre State Mame Delete State eviews Options Library im DesignLib Cell Ireverter Test Simulator u State i ST GE E L L Staic l n M Description What to Loiad Se
37. he ac wave form and DB20 File Tools In Context Results DB SC rafc hr JNTUSOLUTIONS Diff amplifier raw Replace l M MEW 9 Applications Actions D Options Constants Help Virtuoso R Visualization amp Analysis XL calculator dBe2Otve vaut resulteDir DiN amplifier raw result ac ac y LA B Pee Be ga bandwidth clip compare compression compressioan vRl conjugate convolye delay deriv dft dftbb dnl duty Cycle gym evmcpsk exp eyebiagram fallTime flip fourEval freq freq jitter frequency ga gac freq qac gain gainBvwPrad gainhdargin get amp sciiWave gmax gmin successful evaluation lm Z Bll root amp localhost scratch Log root CD5 log 2 l Virtuoso R Visualizatior gpc gain qroupDelay gt gum harmonic harmanicFreg histo iinteg imag int integ intersect ipn ipn Rl kf In loadpull logi0 Ish Ishift mag nce_frey nc gain nf nfimin overshoot peak peakToPeak period jitter phase phaseDeg phaseDegUnwrapped phasehtargin phaseMnise phaseRad phaseRadUnwrapped pow psd psdbb pzbode pefilter real riseTime rms rmsMoise m foot rshift 11 s12 sz1 sez sample settlingTime cadence Ex Ne M ME E EE z FRIES 1 ug oO o user 1 usar ET MI X V OB b Tue Feb 28 21 50 Active Graph Window 5 File Edit Frame Graph Axis Trace Marker Zoom Tools Measurement He
38. he layouts for the design 4 In the next Technology File for New library form select option Attach to an existing techfile and click OK Technology File for library myLDiesigqnLib You can Compile an ASCI technology file Reference existing technology libraries Attach to an existing technology library w OO not need process information Cancel Help 5 In the Attach Design Library to Technology File form select gpdk180 from the cyclic field and click OK or Attach Library to Technology Library E Mew Library myDesignLib Technology Library analogLib avTech hasic EUR Apply hele 6 After creating a new library you can verify it from the library manager 7 If you right click on the myDesignLib and select properties you will find that gpdk180 library is attached as techlib to myDesignLib Analog lab manual PERSE cadence Library Manager Directory _arshanfcadence _analog_ Eterm H m EJ Eile Edit Miew Design Mianager Help cadence show Categories show Files Library ell Q0 MER EUR mywDesignLib lf cos assertions cds inhcarnnmn d cos spirelib ranmnegrcti ib l gpdki arn eaae l PGZ mO del Z rc utilz zuilit Messages na p rary a Pec pa ai BEL EEE The directory Vserversztfa clc softwares amp SSLUHAS3Z G Sto ots nd x Creating a Schematic Cellview In this section we will learn how to open new schematic
39. ib Inverter Symbol analogLib vpulse vl 0 v2 1 8 td 0 tr tf l1ns ton 10n T 20n analogLib vdc gnd vdc 1 8 Note Remember to set the values for VDD and VSS Otherwise your circuit will have no power 2 Add the above components using Create Instance or by pressing I 4 3 Click the Wire narrow icon and wire your schematic Tip You can also press the w key or execute Create Wire narrow 4 Click Create Wire Name or press L to name the input Vin and output Vout abg JL wires as in the below schematic T 5 Click on the Check and Save icon to save the design Analog lab manual Em cadence 6 The schematic should look like this 7 Leave your Inverter_Test schematic window open for the next section Analog lab manual cadence Analog Simulation with Spectre Objective To set up and run simulations on the Inverter Test design In this section we will run the simulation for Inverter and plot the transient DC characteristics and we will do Parametric Analysis after the initial simulation Starting the Simulation Environment Start the Simulation Environment to run a simulation 1 In the Inverter Test schematic window execute Launch ADE L The Virtuoso Analog Design Environment ADE simulation window appears Choosing a Simulator Set the environment to use the Spectree tool a high speed highly accurate analog simulator Use this simulator with the Inverter Test des
40. ign which is made up of analog components 1 In the simulation window ADE execute Setup Simulator Directory Host Analog lab manual PE cadence 2 In the Choosing Simulator form set the Simulator field to spectre Not spectreS and click OK Setting the Model Libraries The Model Library file contains the model files that describe the nmos and pmos devices during simulation 1 In the simulation window ADE Execute Setup Model Libraries The Model Library Setup form appears Click the browse button o to add gpdk scs if not added by default as shown in the Model Library Setup form Remember to select the section type as stat in front of the gpdk scs file Your Model Library Setup window should now looks like the below figure spectre Model Library Setup Model File Section Er Glabal Model Files He R shan cadence analog labs BIa models spectre gps scs stat Pe ick here to add model fe OK Cancel Apply J Help To view the model file highlight the expression in the Model Library File field and Click Edit File Analog lab manual Em cadence E lk pu 2 To complete the Model Library Setup move the cursor and click OK The Model Library Setup allows you to include multiple model files It also allows you to use the Edit button to view the model file Choosing Analyses This section demonstrates how to view and select the different types of analyses to complete the circuit whe
41. in the Design Variables section of the Simulation window 3 In the selection window double click left on wp The Variable Name field for Sweep 1 in the Parametric Analysis form is set to wp Analog lab manual Fa cadence 4 Change the Range Type and Step Control fields in the Parametric Analysis form as shown below Range Type From To From lu To 10u Step Control Auto Total Steps 10 These numbers vary the value of the wp of the pmos between lum and 10um at ten evenly spaced intervals G oweBB 1 Variable Name wp Range Type FromTo From iu Step Control Auto M uu Steps 10l T l Sweep 1 o Execute Analysis Start The Parametric Analysis window displays the number of runs remaining in the analysis and the current value of the swept variable s Look in the upper right corner of the window Once the runs are completed the wavescan window comes up with the plots for different runs Analog lab manual 64 cadence RA Active myDesignLib Inverter_Test schematic Jun 24 00 48 52 2009 15 HLT File Edit Frame Graph Axis Trace Marker Zoom Tools Measurements Help cadence Pa t rt EE erst E FT S D 88 m II SIS EE El dK eng lx Label Jun 24 2009 Transient Response 1 lun 24 2009 DC Response E Bin dep 1 00e 06 Vin ip 22 00 06 o gyvniep i00e 06 Vin opo2 00e 06 A Edin up 3 00s 05 Ein pup d 004 5 _ Sin b p 3008 06 Ein ipa uns 06 Li EmPiniwp 5 00e 06 Brin epe 00 06 Evin tvp
42. l view and build A GREY TO BINARY CODE CONVERTER Use the techniques learned in the Lab2 1 to complete the schematic of GREY TO BINARY CODE CONVERTER This is a table of components for building the GREY TO BINARY CODE CONVERTER schematic Cell Name Properties Comments gpdk180 Pmos Model Name pmos1 pmos2 pmos3 pmos4 gpdk180 Nmos Model Name nmosl nmos2 nmos3 nmos4 Type the following in the ADD pin form in the exact order leaving space between the pin names vout Output Analog lab manual 89 l cadence Objective To create a symbol for the GREY TO BINARY CODE CONVERTER Use the techniques learned in the Lab2 1 to complete the symbol of GREY TO BINARY CODE CONVERTER gate Nel Analog lab manual cadence Use the techniques learned in the Lab1 and Lab2 to complete the layout of GREY TO BINARY CODE CONVERTER Complete the DRC LVS check using the assura tool Extract RC parasites for back annotation and Re simulation Analog lab manual cadence 4 Introduction to SPICE Simulation and coding of NMOS PMOS Circuits SPICE is a powerful general purpose analog circuit simulator that is used to verify circuit designs and to predict the circuit behavior This is of particular importance for integrated circuits It was for this reason that SPICE was originally developed at the Electronics Research Laboratory of the University of California Berkeley 1975 as its name implies Simulation Program for Int
43. ld the cs amplifier test schematic as shown below Analog lab manual ra cadence Define pulse specification as analogLib AC Magnitude 1 DC Voltage 0 Offset Voltage 0 Amplitude 5m Frequency 1K analogLib vdd vss gnd vdd 2 5 vss 2 5 vbias 2 5 Analog lab manual cadence Analog Simulation with Spectre Objective To set up and run simulations on the cs amplifier test design Use the techniques learned in the Lab1 and Lab2 to complete the simulation of cs amplifier ADE window and waveform should look like below session gem mem Variables r QUE simulation Results Tools Hel cadence status Ready Te27 C oimulator spectre Design variables Analyses z Type Enable Arguments j t 1 dc w t 5 5 Automatic star stop M3 e AC E ac w 150 100M1 20 Logarithmic Points Per Decad R _ be a tran w 5m moderate Trans ili Ex lt Outputs my 1 4alur Plot Save Save Options E ao v ally re BU v aly S a iit Ka Mag Hl 7 me Plot After Simulation Auto M Plotting made Replace Q gt Results itr me darshan simulation cs amplifier test spectre schematic 36 Plot Outputs h Transient Response 1 AC Response E DC Response s Eo HE 1 9205 1 92 1 9195 1 919 1 3185 1 318 1 3175 1 0 2 0 3 0 40 5 0 102103 10 10 105 107 108 Ru EE 4 819ms 4 515mv ims 69 366MHz 1 91902 4826W ST giw Analog lab ma
44. learned in the Lab1 and Lab2 to complete the layout of LATCH Complete the DRC LVS check using the assura tool Extract RC parasites for back annotation and Re simulation END OF LAB 2 5 Analog lab manual LONE cadence PT DS on Fu i d E g es La P r C 18 z Amos ob By HMG m l m I 1868 HLA 1 An eo nmeoal T Analog lab manual cadence Schematic Entry Objective To create a new cell view and build A SRAM Use the techniques learned in the Lab2 1 to complete the schematic of SRAM This is a table of components for building the SRAM schematic nind name Cell Name Properties Comments kasia Pmos Model Name pmos1 pmos2 pmos3 pmos4 gpdk180 Nmos Model Name nmos1 nmos2 nmos3 nmos4 Type the following in the ADD pin form in the exact order leaving space between the pin names Analog lab manual LE cadence Objective To create a symbol for the SRAM Use the techniques learned in the Lab2 1 to complete the symbol of SRAM vdd instanceNamelcarry sum Analog lab manual cadence Creating a layout view of SRAM Use the techniques learned in the Lab1 and Lab2 to complete the layout of SRAM gate Complete the DRC LVS check using the assura tool Extract RC parasites for back annotation and Re simulation END OF LAB 2 6 Analog lab manual Hm cadence Analog lab manual cadence Schematic Entry Objective To create a new cel
45. lect Allo Clear All E Analyses a variables S Outputs Model Setup S Simulation Files Environment options aw Simulator options a Convergence Setup Waveform Setup Graphical Stimuli Conditions Setup Results Display Setup Device Checking Setup Cosimulation Options Turbo and Parasitic Reduction En ESL cance 4 pply Help 3 Click OK in the Loading State window Analog lab manual cadence Parametric Analysis Parametric Analysis yields information similar to that provided by the Spectree sweep feature except the data is for a full range of sweeps for each parametric step The Spectre sweep feature provides sweep data at only one specified condition You will run a parametric DC analysis on the wp variable of the PMOS device of the Inverter design by sweeping the value of wp Run a simulation before starting the parametric tool You will start by loading the state from the previous simulation run Run the simulation and check for errors When the simulation ends a single waveform in the waveform window displays the DC Response at the Vout node Starting the Parametric Analysis Tool 1 In the Simulation window execute Tools Parametric Analysis The Parametric Analysis form appears 2 In the Parametric Analysis form execute Setup Pick Name For Variable Sweep 1 A selection window appears with a list of all variables in the design that you can sweep This list includes the variables that appear
46. lp a e 8 8 50888 8 Feb 28 2012 C dk Ed pane O 0B ZU GM yout resultsDir Diff am plifier raw rezult ac ac n 20 0 25 0 25 0 50 0 75 0 109 gol 102 Sf Active Graph Window 5 End of lab 5 2 103 10 10 10 107 109 109 1010 fred Hz W Virtuoso R Visualizatior B i Analog lab manual ra cadence Schematic Capture Proce au ATE 2 d M LAM L L 1 L l rn nmes d NMG amaosi Ww TAH a eu l 1u m 1 Analog lab manual cadence Schematic Entry Objective To create a new cell view and build Common Source Amplifier Use the techniques learned in the Lab1 and Lab2 to complete the schematic of Common Source Amplifier This is a table of components for building the Common Source Amplifier schematic Cell Name Properties Comments gpdk180 Model Name pmos1 W 50u L 1u gpdk180 Model Name nmos1 W 10u L lu Type the following in the ADD pin form in the exact order leaving space between the pin names vin vbias Input vout Output Analog lab manual ra cadence Symbol Creation Objective To create a symbol for the Common Source Amplifier Use the techniques learned in the Lab1 and Lab2 to complete the symbol of cs amplifier Building the Common Source Amplifier Test Design Objective To build cs amplifier test circuit using your cs amplifier Using the component list and Properties Comments in the table bui
47. n correct all the DRC errors and Re run the DRC 9 If there are no errors in the layout then a dialog box appears with No DRC errors found written in it click on close to terminate the DRC run Analog lab manual rau cadence ASSURA LVS In this section we will perform the LVS check that will compare the schematic netlist and the layout netlist Running LVS 1 Select Assura Run LVS from the layout window The Assura Run LVS form appears It will automatically load both the schematic and layout view of the cell 2 Change the following in the form and click OK Run Assura LVS x Schematic Design Source OFII Use Existing Metlist pd Metlisting Options J Library myDesignLib ell Inverter Whew schematic Browse j Layout Design Source DFI Use Existing Extracted Metlist acd Library mylLIezsignLib Cell Irvzerter Vieux layout Browse J Fun Location local view Rules Files Technology lgpdk180 lt Rule Set detfault Extract Rules ane e analog labs 51I3 pwv assura ezxtract rul Whew Relead Compare Rules asn cadence analog labs 613 pv assura compare rul V penu J Run Mame Run Directors l L S Switch names Set Switches Binding Filets View i RSF Include wig Warlahle value Default Description Mone Rd View avParameters boy Modify avParameters 7 awvP
48. n running the simulation 1 In the Simulation window ADE click the Choose Analyses icon You can also execute Analyses Choose The Choosing Analysis form appears This is a dynamic form the bottom of the form changes based on the selection above 2 To setup for transient analysis a In the Analysis section select tran b Set the stop time as 200n c Click at the moderate or Enabled button at the bottom and then click Apply Analog lab manual 26 cadence Ba Choosing Analyses Virtuoso Analog Design Environn Em Analysis tran aw Lit wed LES Nose uud T Sens e dcmatch wy sth pz c Sf envip eu Pos wo HaC psth Pnoise ww PIT Pop pss a Wpac w Opnoise wu Ct Cpsp WX hb wa Hees hbnaise Transient Analysis Stop Time ZD Ue Seccwracy Defaults CeTrrpre gt eT Conservative w moderate liberal Transient POI Z Enabled m C 3ptions EIA cance Deteuits Apply Help 3 To set up for DC Analyses a In the Analyses section select de b In the DC Analyses section turn on Save DC Operating Point c Turn on the Component Parameter d Double click the Select Component Which takes you to the schematic window e Select input signal vpulse source in the test schematic window f Select DC Voltage in the Select Component Parameter form and click OK f In the analysis form type start and stop voltages as O to 1 8 respectively g Check th
49. n the Circuit without Parasites 1 From the Library Manager open Inverter Test Config view Open Configuration or Top cellview form appears v ES Open Configuration or Top CellView Open for editing Configuration mybesignLib Inverter Test config s yes Tap Cell View myDesignLib Inverter Test schematic a ves 2 In the form turn on the both cyclic buttons to Yes and click OK The Inverter Test schematic and Inverter Test config window appears Notice the window banner of schematic also states Config myDesignLib Inverter Test config 3 Execute Launch ADE L from the schematic window 4 Now you need to follow the same procedure for running the simulation Executing Session Load state the Analog Design Environment window loads the previous state e 5 Click Netlist and Run icon to start the simulation The simulation takes a few seconds and then waveform window appears 6 In the CIW note the netlisting statistics in the Circuit inventory section This list includes all nets designed devices source and loads There are no Analog lab manual rag cadence parasitic components Also note down the circuit inventory section Measuring the Propagation Delay 1 In the waveform window execute Tools Calculator The calculator window appears Virtuoso R Visualization amp Analysis L Calculator File Tools Wiew Options Constants Help cadence Results Gir fexportfhomerdarshanssimulationsn
50. n the Table of Design Variables 3 Click OK or Cancel in the Editing Design Variables window Selecting Outputs for Plotting Execute Outputs To be plotted Select on Schematic in the simulation window 2 Follow the prompt at the bottom of the schematic window Click on output net Vout input net Vin of the Inverter Press ESC with the cursor in the schematic after selecting it Does the simulation window look like this Session Setup Analyses Variables Outputs simulation Results Tools Help cadence i Status Ready T zyr c simulator spectre Design Variables Analyses Types Enable Arguments B dc wt t 1 8 Automatic Start Stop vo tran wt 0 200n moderate E value Plot Save Save Options wt ally 2 vin S ally Plot After Simulation Auta Plotting mode Replace ONE 2 Choose Design Analog lab manual CE cadence Running the Simulation 1 Execute Simulation Netlist and Run in the simulation window to start the Simulation or the icon this will create the netlist as well as run the simulation 2 When simulation finishes the Transient DC plots automatically will be popped up along with log file e le Ha Active work Inverter_Test schematic Jun 25 13 12 51 200913 File Edit Frame Graph Axis Trace Marker Zoom Tools Measurements Help cadence amp n H SOG 2S of vii OMB ox dk EJES Label 0 0 0 0 0 0 Jun 25 20049 Transient R
51. nual mam cadence Use the techniques learned in the Lab1 and Lab2 to complete the layout of cs amplifier Complete the DRC LVS check using the assura tool Extract RC parasites for back annotation and Re simulation Tenens a N NU ma RU pan ERI a R nan ANN 1 H w L 1 xes i U sest l l m IB co den c dee Hel c den Nen c G des m p m LA ISI IE B ET L i ant uu d MW Na i M ll V Analog lab manual cadence Lab7 Design of PLL A phase locked loop PLL generates a clock that is in sync with an input signal If the input signal changes the phase detector PD detects the difference in frequency and phase between the input and the output and sends a filtered voltage to a voltage controlled oscillator VCO to either raise or lower the output clock frequency as necessary to bring it back into sync with the input signal PLLs are used widely in data recovery and frequency generation The PLL in this lab was designed as a schematic with both schematic and Verilog views of the phase detector and the schematic and Verilog AMS views of the VCO A configuration is used to tell the simulator to use Verilog views for the phase detector and the schematic view of the VCO Control of the simulation is done using the Virtuoso Analog Design Environment ADE which may be familiar to analog designers Schematic Ermi Bet n Tenis Design Window Edit Add Check Sheet Options A e Iq T ba i
52. oltage changes in response to pump down pulses the positive going pulses and pump up pulses the negative going pulses and finally settles out after 10 us when the pump down and pump up pulse areas are approximately equal That indicates that syncing to the input signal in ref has been achieved End of lab 7 Analog lab manual 105
53. operties Comments in the table build the latch test schematic as shown below myDesignLib cmos LATCH Symbol Define pulse specification as analogLib vpulse In lab 2 1 analogLib vdd vss gnd vdd 1 8 vss 1 8 Virtuoso Analog Design Environment 3 Hsolutions full adder schematic HB if Session setup Analyses Variables Outputs simulation Results Tools Help cadence G aan _ Tvpe Enable lt Arguments jm T iran w 0160n moderate ET we Pd 5x R Mame Signal Espr Value Plot Save Save Options 1a nd ally 2b ally Wi ac Ld ally EE Sum t ally 5 carry w Lad ally Plot after simulation Auto Ea Fioting mode Replace M mouse L hel R 13620 Save State Status Ready T 27 Simulator spectre Analog lab manual Im cadence Analog Simulation with Spectre Objective To set up and run simulations on the LATCH design Use the techniques learned in the Lab2 1 to complete the simulation of LATCH ADE window and waveform should look like below Active Hsolutions full adder schematic Feb 28 21 33 03 2012 26 m EH Ga File Edit Frame Graph Axis Trace Marker Zoom Tools Measurements Help em ce Bone Bul El oP ES Label Feb 28 2012 Transient o M BS RS 9S 2 0 U 25 0 50 0 P50 100 0 125 0 150 0 175 0 time insi 150ns 0 0 e gt graphl Analog lab manual LEN cadence Creating a layout view of LATCH Use the techniques
54. ost of the submicron CMOS process design rules do not lend themselves to straightforward linear scaling The use of lambda based design rules must therefore be handled with caution in sub micron Analog lab manual 9 cadence geometries In the following we present a sample set of the lambda based layout design rules devised for the MOSIS CMOS process MOSIS Layout Design Rules sample set Rule number Description L Rule Rl Minimum active area width 3L R2 Minimum active area spacing 3L R3 Minimum poly width AL R4 Minimum poly spacing AL R5 Minimum gate extension of poly over active 2L RO Minimum poly active edge spacing 1L poly outside active area R7 Minimum poly active edge spacing 3L poly inside active area R8 Minimum metal width 3L R9 Minimum metal spacing 3L R10 Poly contact size 2L R11 Minimum poly contact spacing 2L R12 Minimum poly contact to poly edge spacing IL R13 Minimum poly contact to metal edge spacing IL R14 Minimum poly contact to active edge spacing 3L R15 Active contact size 2L R16 Minimum active contact spacing 2L on the same active region R17 Minimum active contact to active edge spacing IL R18 Minimum active contact to metal edge spacing IL R19 Minimum active contact to poly edge spacing 3L R20 Minimum active contact spacing 6L on different active regions Analog lab manual rmm cadence Schematic Capture C a gt pmos MD omos T fo T our MI al bale Ge n 8a d ined O
55. owable separations between two such features The main objective of design rules is to achieve a high overall yield and reliability while using the smallest possible silicon area for any circuit to be manufactured with a particular process The layout design rules which are specified for a particular fabrication process normally represent a reasonable optimum point in terms of yield and density gt A layout which violates some of the specified design rules may still result in an operational circuit with reasonable yield whereas another layout observing all specified design rules may result in a circuit which is not functional and or has very low yield To summarize we can say in general that observing the layout design rules significantly increases the probability of fabricating a successful product with high yield The design rules are usually described in two ways Y Micron rules in which the layout constraints such as minimum feature sizes and minimum allowable feature separations are stated in terms of absolute dimensions in micrometers or v Lambda rules which specify the layout constraints in terms of a single parameter and thus allow linear proportional scaling of all geometrical constraints Lambda based layout design rules were originally devised to simplify the industry standard micron based design rules and to allow scaling capability for various processes It must be emphasized however that m
56. plifier scs a as B Applications Actions ge 9 4 Tue Feb 28 21 44 root localhost scratch File Edit View Terminal Tabs Help simulator lang spectre global 0 include scratch database scratch varal cadence cadence ms labs 613 models spectre gpdk scs section stat NMO vout O net net06 nmosl w 3u l lu as 1 8p ad 1 8p ps 2u pd 2u m 1 1 NM2 net8 idc vss vss nmosl w 4 5u l 1u as 2 p ad 2 p ps 10 2u pd 10 2u m 1 1 NMI net vin net net 06 nmosl w 3u l lu as 1 8p ad 1 8p ps 2u pd 2u m 1 1 NM3 idc idc vss vss nmosl w 4 5u l 1u as 2 7p ad 2 7p ps 10 2u pd 10 2u m 1 1 PM1 vout net vdd vdd pmosl w 15u l 1u as 9p ad 9p ps 31 2u pd 31 2u m 1 1 PMO net net vdd vdd pmosl w 15u l 1u as 9p ad 9p ps 31 2u pd 31 2u m 1 1 V2 net06 0 vsource dc 2 5 type dc V1 vss 0 vsource dc 2 5 type dc VO vdd 0 vsource dc 2 5 type dc Ti vdd idc isource de 30u type dc V3 vin 0 vsource mag 1 type sine sinedc ampl 5m freg 1k simulator ptions options reltol le 3 vabstol le 6 iabstol le l2 temp 27 tnom 27 scalem 1 0 scale 1 0 gmin 1e 1 rforce 1 maxnotes 5 maxwarns 5 X digits 5 cols 80 pivrel le 3 sensfile psf sens output checklimitdest psf tran tran stop 4m write spectre ic writefinal spectre fc annotate status maxiters 5 finalTimeOP info what oppoint where rawfile ac ac start 1l stop 5006 annotate status dcOp dc write spectre dc maxiters 150 maxsteps 10000 annotate stat
57. ratch JNTLISOLLITIONSZDiff amplifier raw ES tran tran signals Search E Eg finalTimeOP info 2 5 E i ac ac E Eg dcOp dc E gg dcOpilnfo info o H Gi dc dc 5 E 2g modelParameter info 22 5 E 5g element info E i39 outputParameter infa E 25g designParam als info 5 0 E 23 primitives info primitives 7 5 2 44 vout 22 2 0 1 8 gt 1 6 1 4 1 2 o IO 2 0 3 0 4 0 i977ms 1 806 time m5 2 l Open Results gt Can t delete last graph to close window use File gt Close i es E E root Iocalhost scratch Log root CDS log 2 Virtuoso R Visualizatior Active Graph Window 3 Analog lab manual cadence 9 For DC analysis Click on dc dc vout Virtuoso R Visualization amp Analysis XL browser Jm i if Active Graph Window 4 ZS E E 4 Applications Actions V ID Tue Feb 28 21 48 Fil Ec Frar Gra Ax Tra Mar Zoc Tot Measure Headence File Tools Options Help cadence S4HQ HE 08S Co nw D OR nS E ES Bo Nel vout Diff amplifier raw M UE a EFE fscratch JNTLISOLLITIONS Diff amplifier raw signals search E33 tran tran i finalTimaeFP infa T E ac ac EF 5 ig dcoOp dc E dcOplnfo infa REL lr n i8 dc dc modelParameter into elementinta l outputFarameter info l Tele Lee HERR H designParam als info primitives infa primitives nS 0 9 509 SUT IS oN lt Y D HP rJ 3 5 0
58. rties Comments nd pmos For MO Model name pmos1 W wp L 180n gpdk180 nmos For M1 Model name nmos1 W 2u L 180n Analog lab manual DONE cadence If you place a component with the wrong parameter values use the Edit Properties Objects command to change the parameters Use the Edit Move command if you place components in the wrong location IE D md Xx Q Ee e You can rotate components at the time you place them or use the Edit Rotate command after they are placed 4 After entering components click Cancel in the Add Instance form or press Esc with your cursor in the schematic window Adding pins to Schematic 1 Click the Pin fixed menu icon in the schematic window You can also execute create Pin or press p e The Add pin form appears 2 Type the following in the Add pin form in the exact order leaving space between the pin names Make sure that the direction field is set to input output inputOutput when placing the input output inout pins respectively and the Usage field is set to schematic 3 Select Cancel from the Add pin form after placing the pins In the schematic g window execute Window Fit or press the f bindkey C Fa a mL L Analog lab manual rmm cadence Adding Wires to a Schematic Add wires to connect components and pins in the design 1 Click the Wire narrow icon in the schematic window You can also press the w key or e
59. s S pro i Pmnpsl uu Pc c Wie 188n LTR mit om B WoL E nmos MM amos 1 it LI I 185m mil MTL nmos FF rnd G 1 pp B HT E ladn m 1 Analog lab manual cadence Schematic Entry Objective To create a new cell view and build A NAND gate Use the techniques learned in the Lab2 1 to complete the schematic of NAND gate This is a table of components for building the nand gate schematic Cell Name Properties Comments gpdk180 Model Name pmos1 pmos2 gpdk180 Model Name nmos1 nmos2 Type the following in the ADD pin form in the exact order leaving space between the pin names vout Output Analog lab manual Em cadence Objective To create a symbol for the nand gate Use the techniques learned in the Lab2 1 to complete the symbol of NAND gate Analog lab manual cadence Objective To build NAND test circuit using your NAND gate Using the component list and Properties Comments in the table build the cs amplifier test schematic as shown below Library name Cellview name Properties Comments Define pulse specification as analogLib vpulse In lab 2 1 analogLib vdd vss gnd vdd 1 8 vss 1 8 Analog lab manual cadence Analog Simulation with Spectre Objective To set up and run simulations on the NAND gate design Use the techniques learned in the Lab2 1 to complete the simulation of NAND eate ADE window and waveform should look like below
60. s Help Dye a 323 BI Biel El x5 db oes uz Label Feb 28 2012 Transient Fen gu HZ 1 1 Tramsentnespooec 2 0 U 25 0 60 0 75 0 100 0 125 0 150 0 175 0 time ins 160ns D mw e gt graphl Analog lab manual 70 cadence Creating a layout view of FULL ADDER Use the techniques learned in the Lab1 and Lab2 to complete the layout of FULL ADDER Complete the DRC LVS check using the assura tool Extract RC parasites for back annotation and Re simulation 11 1 1 meum H E a m i 1 x y Y E z z x x 7 11 19 END OF LAB 2 2 Analog lab manual UNE cadence Analog lab manual cadence Schematic Entry Objective To create a new cell view and build A LATCH Use the techniques learned in the Lab2 1 to complete the schematic of LATCH This is a table of components for building the LATCH schematic nind name Cell Name Properties Comments kasia Pmos Model Name pmos1 pmos2 pmos3 pmos4 gpdk180 Nmos Model Name nmos1 nmos2 nmos3 nmos4 Type the following in the ADD pin form in the exact order leaving space between the pin names Analog lab manual Om cadence Objective To create a symbol for the LATCH Use the techniques learned in the Lab2 1 to complete the symbol of LATCH nstanceName Analog lab manual cadence Building the latch Test Design Objective To build latch test circuit using your latch Using the component list and Pr
61. should appear like this Run Assura DRC Layout Design Source DE Compare two layouts baal Generate viz Compare Rules Library CeDesignLib Cell Inverter VIEW layout Browse cave Extracted View View Mame dro extracted amp rea To Be Checked Full B Run Mame Run Directory DRCrun Run Location local View Rules Files La Technology igpadktau M Rule Ser default M Rules File cadence analog labs 613 pv assura drce rul Wie Reload Switch Names set Switches RSF Include Vip j variable Value Default Description Mone View avParameters hiodity avParameters Mo avParameters are set View Adgditianal Functions pad Mo additional functions are set a gt Cancel Ji Apply I Defaults J Load State J Save State J View RSF Help J Analog lab manual D cadence 3 Click OK to start DRC 4 A Progress form will appears You can click on the watch log file to see the log file 5 When DRC finishes a dialog box appears asking you if you want to view your DRC results and then click Yes to view the results of this run 6 If there any DRC error exists in the design View Layer Window VLW and Error Layer Window ELW appears Also the errors highlight in the design itself 7 Click View Summary in the ELW to find the details of errors 8 You can refer to rule file also for more informatio
62. table format Analog lab manual 46 cadence Virtuoso Hierarchy Editor myDesignlib Inverter Test config He gt File Edit iew Plugins Help caden ce lla K Pear Es m cedi Gioball Bindings Library myDesignLib Library List Call Inverter Test lt View List sz sch schematic verilaga andl MV peste schematic Stop List spectre Constraint List Open Table View Tree View Cell Bindings Library Mies Found view To Use Inherited view List analagLib v dc spectre spectre cmos_sch cmos s analogLik w pulze spectre spectre cmoas_sch cmos s qpdk1 ao nO Z spectre spectre cmos zch cmops s gpdki 60 D mO S spectre spectre cmos_sch cmos s myOesiqnlib Inverter schematic spectre cmos_sch cmos s myOesiqnlib Inverter_Test schematic spectre cmos_sch cmos s 7 Click the Tree View tab The design hierarchy changes to tree format The form should look like th s Table View Tree Yjew Target Occurrence Instance wiew To Use Inherited View List EF S myDesignLib Inverter Test schematic H ID myDesignLib Inverter schematic spectre cmas sch cmos L 9 YO fanaloglib vpulse spectre spectre cmas sch cmos w C V1 fanalogLlib vde spectre spectre cmas sch cmos 8 Save the current configuration 9 Close the Hierarchy Editor window Execute File Close Window Analog lab manual ao cadence To ru
63. the radio buttons to open both the Configuration Hierarch Editor and the Top Cell View schematic of the PLL1 cell and click OK Analog lab manual 104 cadence 2 In the Hierarchy Editor note that the PD phase detector is set to use the verilog view and the VCO1 voltage controlled oscillator is set to use the schematic view In this lab the Hierarchy Editor will only be used to view the configuration not to control the simulation 3 In the Virtuoso Schematic Editor which displays the PLL1 configured schematic Config PLL lib PLL1 config execute Launch ADE L to open the Virtuoso Analog Design Environment ADE You may close the What s New in Analog Mixed Signal window File Close Window 4 In the ADE window execute Setup Simulator Directory Host and for Simulator verify that ams is selected Click OK Choosing Simulator Directory Host Virtuoso Analog aln ulatci Project Directory J simulation Host Mencia local w romolo w detribuled Note The simulator was set to ams by a line in the cdsinit file 22 cc 2 envSetVal asimenv startup simulator string ams Note also that this form allows you to change the output directory name and to set up distributed hosts if you have them available For this lab leave it set to a local host o In the ADE window execute Session Load State In the Loading State form select statel and click OK This will pre load the ADE
64. unning any of these labs ensure that you ve set up IUS92 IC614 MMSIM101 and Assura41 correctly 90 setenv CDSHOME lt IC614 installation home gt 90 setenv MMSIMHOME lt MMSIM101 installation home gt gt setenv PVHOME lt Assura41 installation home gt gt setenv AMSHOME lt IUS92 installation home gt You will also need to ensure that the IUS92 is setup correctly for lab 5 To setup the lab environment please perform the following steps 1 Ensure the software mentioned above is correctly setup 2 Source the C Shell related commands file i e cshrc file These labs were designed to be run using Cadence Virtuoso tool and Assura tool Analog lab manual E cadence Lab Getting Started 1 Log in to your workstation using the username and password The home directory has a eshrc file with paths to the Cadence installation 2 In a terminal window type csh at the command prompt to invoke the C shell gt csh gt source cshrc 3 To verify that the path to the software is properly set in the cshrc file type the below command in the terminal window and enter gt which virtuoso It gives the complete path of IC614 tool Installation gt which spectre It gives the complete path of MMSIM101 tool Installation gt which assura It gives the complete path of Assura410 tool Installation Starting the Cadence Software Use the installed database to do your work and the steps are as follows 1 Change to the cours
65. us dc pInfo info what oppoint where rawfile dc dc dev V3 param dc start 5 stop 5 oppoint rawfile maxiters 150 maxsteps 10000 annotate status modelParameter info what models where rawfile element info what inst where rawfile outputParameter info what output where rawfile designParamVals info what parameters where rawfile primitives info what primitives where rawfile save vout vin save ptions options save allpub Diff amplifier scs 37L 1750C af 0 1 All Z E root localhost scratc h Bl oot localhost simulation dif Analog lab manual ra cadence 3 Compile the inverter scs code gt spectre Diff amplifier scs Xs B Applications Actions amp GSD Tue Feb 28 20 13 root localhost scratch e File Edit View Terminal Tabs Help dc de 864 mV 48 step 36 mV 2 dc de 900 mV 50 step 36 mV 2 95 dc dc 936 mV 52 step 36 mV 2 95 dc de 972 mV 54 step 36 mV 2 9 dc dc 1 008 V 56 step 36 mV 2 90 dc dc 1 044 V 58 9 step 36 mV 2 9 dc dc 1 08 V 60 step 36 mV 2 9 dc dc 1 116 V 62 9 step 36 mV 2 95 dc dc 1 152 V 64 step 36 mV 2 dc dc 1 188 V 66 step 36 mV 2 95 dc dc 1 224 V 68 9 step 36 mV 2 95 dc dc 1 26 V 70 9 5 step 36 mV 2 96 dc dc 1 296 V 72 9 step 36 mV 2 95 dc dc 1 332 V 74 step 36 mV 2 96 dc dc 1 368 V 76 9 step 36 mV 2 9 dc dc 1 404 V
66. veter_Test spectrercontigr pst ew TE aag MS l OU ag vn wt Sp oW Sr wu Dp wm e iL ex df vu Idec e ES Opi x mp c Vr us ZD wu wp cs nd x data Of Family Wave Clip E Append i l Pae Bas Pop E gis Hee WS mie me average dftbn i argi Ishirt rmsroise bandwidth dnl 7 overshoot root clip duty y che peak sample compare By ma A m1 harmonic period jitter settingTime compression GJ Hn LA D gt K harmonicFrewN phasehliardin slewRate compressions HI ewepiagram histo phaserloise spectralPower a Special Functions a Z Huser sere conyolye flip iinteg spectrum user 3 usert fourEval integ stddev fred intersect D tangent Tren jitter ipn the Trequency ipn Fl i i unity GainF reg Gain rod loadpull status area 14 2 From the functions select delay this will open the delay data panel 3 Place the cursor in the text box for Signall select the wave button and select the input waveform from the waveform window 4 Repeat the same for Signal2 and select the output waveform 5 Set the Threshold value 1 and Threshold value 2 to 0 9 this directs the calculator to calculate delay at 50 i e at 0 9 volts 6 Execute OK and observe the expression created in the calculator buffer Analog lab manual 40 cadence 7 Click on Evaluate the buffer icon N to perform the calculation note down the value returned after execution 8 Close the calculator window To run th
67. wWEFELICHECKE Analog Design Environment 1 HH solutions cmos nmand test schematic Session Setup Analyses Variables Outputs Simulation Results Tools Help cadence Analyses LM BS Enable u 1 tran a agn moderate Design variables Arguments Hame salue Hames Signalvespr Malte Plot save cave Options 71 nets nat all 2 netsh all AAT Ss vout all Flot after simulation auto B Plotting mode Replace Ed mouse L I E R arg Metlist and Run Status Ready Fear um simulator spectre State state1 EE EEM Jj Applications Actions B amp 5 Swe 3 1 C e rue Feb 28 2111 Q Active H solutions cmos_nand_test schematic Feb 28 21 10 54 2012 10 File Edit Frame Graph Axis Trace Marker Zoom Tools Measurements Help cadence Feb 28 2012 Transient Response RI 233 S qm l2 1 0 Peaks EE pe ss Oo DS 2 0 1 75 qus 1 25 1 0 gt we O 20 40 60 20 0 0s O O time ns Analog lab manual Em cadence Use the techniques learned in the Lab2 1 to complete the layout of NAND gate Complete the DRC LVS check using the assura tool Extract RC parasites for back annotation and Re simulation END OF LAB 2 2 Analog lab manual Schematic Capture prism T Bu vtl pros 2 LE E S 154r m 1 iuo NM Anmos Wig Libary Tiel pmosg FMi p a aa e 1 1 N ZU MIB c Pns nmos HHA Tnmaal
68. xecute Create Wire narrow 2 In the schematic window click on a pin of one of your components as the first point for your wiring A diamond shape appears over the starting point of this wire 3 Follow the prompts at the bottom of the design window and click left on the destination point for your wire A wire is routed between the source and destination points 4 Complete the wiring as shown in figure and when done wiring press ESC key in the schematic window to cancel wiring Saving the Design 1 Click the Check and Save icon in the schematic editor window 2 Observe the CIW output area for any errors Analog lab manual Em cadence Symbol Creation Objective To create a symbol for the Inverter In this section you will create a symbol for your inverter design so you can place it in a test circuit for simulation A symbol view is extremelyimportant step in the design process The symbol view must exist for the schematic to be used in a hierarchy In addition the symbol has attached properties cdsParam that facilitate the simulation and the design of the circuit 1 In the Inverter schematic window execute Create Cellview From Cellview The Cellview From Cellview form appears With the Edit Options function active you can control the appearance of the symbol to generate 2 Verify that the From View Name field is set to schematic and the To View Name field is set to symbol with the Tool Data Type set

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