PWRficient Debugger
Contents
1. 18 20 20 21 22 23 24 26 26 26 26 27 27 Er 28 29 29 29 30 31 31 31 32 32 33 34 35 36 36 36 38 39 40 40 40 PWRficient Debugger Version 06 Nov 2015 General Note This documentation describes the processor specific settings and features for TRACE32 ICD for the following members of the PA Semi PWRficient PA6T CPU family e DA Semi PWRficient PA6T 1682M e DA Semi PWRficient PA6T 1672M e DA Semi PWRficient PAGT 1352E Support for other PWRficient family members will be available as soon as they are officially released Pre release support is also available but only with explicit permission from P A Semi If some of the described functions options signals or connections in this Processor Architecture Manual are only valid for a single CPU or for specific families the name s of the family ies is added in brackets Brief Overview of Documents for New Users Architecture independent information Debugger Basics Training training debugger pdf Get familiar with the basic features of a TRACE32 debugger e T32Start app t32start pdf T32Start assists you in starting TRACE32 PowerView instances for different configurations of the debugger T32Start is only available for Windows e General Commands general ref x pdf Alphabetic list of debug commands Architecture specific information Processor Architecture Manuals These manuals describe comman2. PWRficient Debugger 1989 2015 Lauterbach GmbH 39 Support Products Product Information OrderNo Code Text LA 3754 JTAG Debugger for PWRficient ICD DEBUG PWRFICIENT supports PA6T 1682M supports 1 8V 5 0V Concurrent debugging of both cores in dual core chip requires a License for Multicore Debugging LA 7960X includes software for Windows Linux and MacOSX requires Power Debug Module debug cable with 16 pin connector Order Information Order No Code Text LA 3754 DEBUG PWRFICIENT JTAG Debugger for PWRficient ICD Additional Options LA 7960X MULTICORE LICENSE License for Multicore Debugging 1989 2015 Lauterbach GmbH PWhficient Debugger 40 Products
3. and will restore MSE EE 1989 2015 Lauterbach GmbH PWhficient Debugger 27 CPU specific SYStem Commands SYStem Option MMUSPACES Enable multiple address spaces support Format SYStem Option MMUSPACES ON OFF SYStem Option MMU ON OFF deprecated Default OFF Enables the usage of the MMU to support multiple address spaces The command should not be used if only one translation table is used Enabling the option will extend the address scheme of the debugger by a 16 bit memory space identifier The option can only be enabled when there are no symbols loaded 1989 2015 Lauterbach GmbH PWhficient Debugger 28 CPU specific SYStem Commands CPU specific MMU Commands MMU TLB Display MMU TLB entries Format MMU TLB Displays a table of all MMU TLB entries of the selected TLB table If the selected CPU only supports one TLB table it can be displayed by just typing MMU TLB Note This functionality is currently in development MMU TLB SCAN Loads MMU TLB entries Format MMU TLB SCAN Loads the TLB table entries from the CPU to the debugger internal MMU table This commands makes the TLBs information available for the TRACE32 debugger even when the program execution is running and the TRACE32 debugger has no access to the TLBs This is required for the real time memory access See also SYStem MemAccess Use the command TRANSIation ON to enable the debugger internal MMU table Note Thi
4. consistent debug display model with embedded Book III E systems the debugger will display Valid Locked and Dirty flags State translation table Display Flag MOESI State Valid NOT I invalid Locked O owned OR E exclusive Dirty M modified internal shared flag S shared Please note that the valid flag is independent of the other state flags 1989 2015 Lauterbach GmbH PWhficient Debugger PWhficient PA6T Specific Implementations Debugging Information Debugging through Reset The core will reset all on chip breakpoints and debug registers upon RESET so it is not possible to debug through a reset If RESET is visible in the JTAG_HReset pin the debugger will report the reset and change the system mode to down 1989 2015 Lauterbach GmbH PWhficient Debugger PWhficient PA6T Specific Implementations Programming the On chip FLASH Note This functionality is currently in development 1989 2015 Lauterbach GmbH PWhficient Debugger PWRficient PA6T Specific Implementations On chip Trace Processors of the PA6T series have a built in trace system The on chip trace can be configured and accessed via the Onchip window The on chip trace can also be accessed via the Trace window if the trace method is set to Onchip Note This functionality is currently in development Processors of the PA6T series have a built in trace buffer with 256 entries It can be used to trace transactio
5. is permanently in reset or checkstop Please check on your target reset and chkstp signals power supply bootstrap configuration pins system clocks and PLL TAP IR problem Even without causing physical damage electrostatic discharges in the vicinity of the debug setup can affect communication between debugger and target E g with Electra systems ESD can cause invalid JTAG instruction IR and data register DR values to be read out If an inconsistent IR state is detected by the debugger a TAP IR problem error message will be issued 1989 2015 Lauterbach GmbH PWhficient Debugger 9 Troubleshooting FAQ No information available 1989 2015 Lauterbach GmbH PWRficient Debugger 10 FAQ Configuration System Overview Debug Cable POWER DEBUG INTERFACE USB 2 q AC DC Adapter 1989 2015 Lauterbach GmbH PWhficient Debugger 11 Configuration PWhficient PA6T Specific Implementations Breakpoints There are two types of breakpoints available Software breakpoints and on chip breakpoints Software Breakpoints To set a software breakpoint before resuming the CPU the debugger replaces the instruction at the breakpoint address with a trap instruction If it is necessary to use the trap interrupt in the target program on the PAGT architecture it is possible to use another instruction for this functionality Please contact us if you need this option On chip Breakpoints To set breakp
6. 2015 Lauterbach GmbH PWhficient Debugger 26 CPU specific SYStem Commands SYStem Option ICREAD Read from instruction cache Format SYStem Option ICREAD ON OFF Default OFF If enabled Data List window and Data dump window for memory class P program memory display the memory values from the instruction cache or L2 cache if valid If the data is not available in cache the physical memory will be displayed SYStem Option IMASKASM Disable interrupts while single stepping Format SYStem Option IMASKASM ON I OFF Default OFF If enabled the interrupt mask bits of the CPU will be set during assembler single step operations The interrupt routine is not executed during single step operations After single step the interrupt mask bits are restored to the value before the step SYStem Option IMASKHLL Disable interrupts while HLL single stepping Format SYStem Option IMASKHLL ON OFF Default OFF If enabled the interrupt mask bits of the cpu will be set during HLL single step operations The interrupt routine is not executed during single step operations After single step the interrupt mask bits are restored to the value before the step NOTE Don t enable this option for code that disables MSR_EE The debugger will disable MSR EE while the CPU is running and restore it after the CPU stopped If a part of the application is executed that disables MSE EE the debugger can not detect this change
7. 4 Switch off the target power Disconnect the debug cable from the target Close the TRACE32 software Power OFF the TRACE32 hardware PWRficient Debugger 1989 2015 Lauterbach GmbH 5 Warning Target Design Requirement Recommendations General e Locate the BDM JTAG COP connector as close as possible to the processor to minimize the capacitive influence of the trace length and cross coupling of noise onto the JTAG signals Don t put any capacitors or RC combinations on the JTAG lines Connect TDI TDO TMS and TCK directly to the CPU Buffers on the JTAG lines will add delays and will reduce the maximum possible JTAG frequency If you need to use buffers select ones with little delay Most CPUs will support JTAG above 30 MHz and you might want to use high frequencies for optimized download performance Ensure that JTAG HRESET is connected directly to the HRESET of the processor This will provide the ability for the debugger to drive and sense the status of HRESET The target design should only drive HRESET with open collector open drain e For optimal operation the debugger should be able to reset the target board completely processor external peripherals e g memory controllers with HRESET e In order to start debugging right from reset the debugger must be able to control CPU HRESET and CPU TRST independently There are board design recommendations to tie CPU TRST to CPU HRESET but this recommendation is not
8. AP controller position in the JTAG chain if there is more than one core in the JTAG chain The information is required before the debugger can be activated e g by a SYStem Up See example below On some CPU selections SYStem CPU with known system configuration the above setting might be set automatically TriState has to be used if more than one debugger are connected to the common JTAG port at the same time TAPState and TCKLevel define the TAP state and TCK level which is selected when the debugger switches to tristate mode NOTE nTRST must have a pull up resistor on the target EDBGRQ must have a pull down resistor 1989 2015 Lauterbach GmbH PWhficient Debugger 23 General SYStem Commands DRPRE DRPOST IRPRE IRPOST TAPState TCKLevel TriState Slave state Example default 0 number of TAPs in the JTAG chain between the core of interest and the TDO signal of the debugger If each core in the system contributes only one TAP to the JTAG chain DRPRE is the number of cores between the core of interest and the TDO signal of the debugger default 0 number of TAPs in the JTAG chain between the TDI signal of the debugger and the core of interest If each core in the system contributes only one TAP to the JTAG chain DRPOST is the number of cores between the TDI signal of the debugger and the core of interest default 0 number of instruction register bits in the JTAG chain between the c
9. C Wind River Systems ELF STABS C C CODEWARRIOR Freescale ELF DWARF Semiconductor Inc GCC GCC Free Software ELF DWARF Foundation Inc JAVA FASTJ Wind River Systems ELF DWARF PWhficient Debugger 1989 2015 Lauterbach GmbH 37 Support Realtime Operation Systems Name Company Comment AMX KadakProducts Ltd ChorusOS Oracle Corporation CMX RTX CMX Systems Inc DEOS DDC I Inc implemented by DDC I ECOS eCosCentric Limited 1 3 2 0 and 3 0 Elektrobit tresos Elektrobit Automotive GmbH via ORTI ERCOSEK ETAS GmbH via ORTI Erika Evidence via ORTI FreeRTOS Freeware v7 Linux Kernel Version 2 4 and 2 6 3 x 4 x Linux MontaVista Software LLC 3 0 3 1 4 0 5 0 LynxOS LynuxWorks Inc 3 1 0 3 1 0a 4 0 MQX Freescale Semiconductor Inc 3 x and 4 x MQX Synopsys Inc 2 40 and 2 50 NetBSD NORTi MISPO Co Ltd Nucleus PLUS Mentor Graphics Corporation OS 9 Radisys Inc OSE Delta Enea OSE Systems 4 x and 5 x OSEK via ORTI OSEKturbo Freescale Semiconductor Inc via ORTI former MetrowerksOSEK PikeOS Sysgo AG ProOSEK Elektrobit Automotive GimbH via ORTI pSOS Wind River Systems 2 1 to 2 5 3 0 with TRACE32 QNX QNX Software Systems 6 0 to 6 5 0 RTEMS RTEMS 4 10 RTXC 3 2 Quadros Systems Inc RTXC Quadros Quadros Systems Inc Sciopta Sciopta SMX Micro Digital Inc 3 4 to 4 0 ThreadX Express Lo
10. P 1989 2015 Lauterbach GmbH PWRficient Debugger 35 Signal QACK TRST JTAG VREF PRESENT N C GND N C KEY PIN GND JTAGConnector Support Available Tools HE o o w amp P S CG 5 Oo HI ot 5 B w e laBla a Z 9E O 9 jf 1RoIRSIRtIG I o PA6T 1352E YES YES PA6T 1672M YES YES PA6T 1682M YES YES Compilers Language Compiler Company Option Comment ADA GNAT Free Software ELF DWARF Foundation Inc C CXPPC Cosmic Software ELF DWARF C CC Freescale XCOFF Semiconductor Inc C XCC V GAIO Technology Co SAUF Ltd C GREEN HILLS C Greenhills Software Inc ELF DWARF C GCC HighTec EDV Systeme ELF DWARF GmbH C MCCPPC Mentor Graphics ELF DWARF Corporation C ULTRA C Radisys Inc ROF C HIGH C Synopsys Inc ELF DWARF C DCPPC TASKING ELF DWARF C D CC Wind River Systems IEEE C D CC Wind River Systems COFF C D CC Wind River Systems ELF DWARF C GCC Free Software ELF DWARF Foundation Inc C GREEN HILLS Greenhills Software Inc ELF DWARF C C CCCPPC Mentor Graphics ELF DWARF Corporation 1989 2015 Lauterbach GmbH PWRficient Debugger 36 Support Language Compiler Company Option Comment C MSVC Microsoft Corporation EXE CV5 WindowsCE C HIGH C Synopsys Inc ELF DWARF C D C Wind River Systems ELF DWARF C GCCPP
11. PWRficient Debugger TRACE32 Online Help TRACE32 Directory TRACE32 Index TRAGES2 DOCUMGONIS DR Es PCB e E j Processor Architecture Manuals aasnssnnneennunnennnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn nnmnnn nannan nnmnnn nnn 7 illud e 7 PWhficient Debugger eeeecee erre eeeenen ene ee nennen nennen nnne nennen an nnnn nenas nennen annnm 1 cal cg Mee EELER 3 Brief Overview of Documents for New Users seeeeeeeeeeeeeennn nennen nennen 3 bine s 5 Target Design Requirement Recommendations eese enne 6 General 6 ej d r e 7 Lire mee ein eae Be 8 SYStem Up Errors 8 PG 10 Be Le LL E 11 System Overview 11 PWhficient PA6T Specific Implementations eeeeeeeeeeeeeeenn nennen nnns 12 Breakpoints 12 Software Breakpoints 12 On chip Breakpoints 12 Breakpoints on Data Addresses 13 Memory Classes 14 Cache 15 Memory Coherency 15 MOESI States 15 Debugging Information 16 Debugging through Reset 16 Programming the On chip FLASH 17 On chip Trace 18 General SY Stet Commands 4i decer bare ccepit cdudL EX aea EDU Kcu DES ME Enel ORE dp 19 SYStem BdmClock Set BDM clock frequency 19 1989 2015 Lauterbach GmbH PWhficient Debugger 1 SYStem CPU SYStem CpuAccess SY
12. Stem LOCK SYStem MemAccess SYStem Mode SYStem CONFIG Example CPU specific SYStem Commands SYStem Option DCREAD SYStem Option FREEZE SYStem Option ICFLUSH SYStem Option ICREAD SYStem Option IMASKASM SYStem Option IMASKHLL SYStem Option MMUSPACES CPU specific MMU Commands MMU TLB MMU TLB SCAN MMU TLB Set CPU specific TrOnchip Commands TrOnchip CONVert TrOnchip EVTEN TrOnchip RESet TrOnchip Set TrOnchip VarCONVert TrOnchip view JTAG Connector RNN TT e GE Available Tools Compilers Realtime Operation Systems 3rd Party Tool Integrations PFOQUEIS est Product Information Order Information Select the CPU type Run time CPU access intrusive Lock and tristate the debug port Run time memory access non intrusive Select operation mode Configure debugger according to target topology Read from data cache Freeze system timers on debug events Invalidate instruction cache before go step Read from instruction cache Disable interrupts while single stepping Disable interrupts while HLL single stepping Enable multiple address spaces support Display MMU TLB entries Loads MMU TLB entries Set an MMU TLB entry Adjust range breakpoint in on chip resource Enable EVTI and EVTO pins Reset on chip trigger settings Enable on chip trigger facilities Adjust hll breakpoint in on chip resource View on chip trigger setup window 1989 2015 Lauterbach GmbH PWhficient Debugger 2
13. breakpoint is still listed as a range breakpoint in the Break List window Use the Data View command to verify the set data address breakpoints OFF An error message is displayed when the user wants to set a new data address breakpoint after all on chip breakpoints are spent by a data address breakpoint to an address range TrOnchip CONVert ON Break Ger 0x6020 0x1f Break Ger 0x7400 0x3f Data View 0x6020 Data View 0x7400 TrOnchip EVTEN Enable EVTI and EVTO pins Format TrOnchip EVTEN ON I OFF Default ON When enabled the processor is configured to enable the EVTI EVTO pins If disabled that pins can be used for GPIO NOTE 1 This options reflect the EVT EN bit in the PCR register of the NPC It is not available on all processor derivates Please check the reference manual for availability 1989 2015 Lauterbach GmbH PWhficient Debugger CPU specific TrOnchip Commands NOTE 2 If the EVTx pins are used for GPIO they should not be connected to the debug trace connector to avoid additional load and other possible errors TrOnchip RESet Reset on chip trigger settings Format TrOnchip RESet Resets the on chip trigger system to the default state TrOnchip Set Enable on chip trigger facilities Format TrOnchip Set source ON OFF lt source gt eXception BRANCH Enables the specified on chip trigger facility to stop the CPU on several events The debugger sets the corr
14. cient Debugger Exit2 DR Exit1 DR Shift DR Pause DR Select IR Scan Update DR Capture DR Select DR Scan Exit2 IR Exit1 IR Shift IR Pause IR Run Test Idle Update IR Capture IR Test Logic Reset IR Core Rene Orme DRE Cone DRC Ome 1989 2015 Lauterbach GmbH 25 General SYStem Commands CPU specific SYStem Commands SYStem Option DCREAD Read from data cache Format SYStem Option DCREAD ON I OFF Default ON If enabled Data dump windows for memory class D data and variable windows display the memory values from the data caches L1D or L2 if valid If no cached data is available physical memory will be read SYStem Option FREEZE Freeze system timers on debug events Format SYStem Option FREEZE ON OFF Default ON Enabling this option will lead the debugger to set the upper half of the TBCTL register to 0 freezing all system timers when a debug event is detected Note This functionality is currently in development SYStem Option ICFLUSH Invalidate instruction cache before go step Format SYStem Option ICFLUSH ON OFF Default ON Invalidates the instruction cache before starting the target program Step or Go If this option is disabled the debugger will update data and instruction cache for program memory downloads modifications and breakpoints Disabling this option might cause performance decrease on memory accesses 1989
15. ds that are specific for the processor architecture supported by your debug cable To access the manual for your processor architecture proceed as follows 1989 2015 Lauterbach GmbH PWhficient Debugger 3 General Note Choose Help menu Processor Architecture Manual e RTOS Debugger rtos x pdf TRACE32 PowerView can be extended for operating system aware debugging The appropriate RTOS manual informs you how to enable the OS aware debugging 1989 2015 Lauterbach GmbH PWhficient Debugger Brief Overview of Documents for New Users Warning Signal Level NOTE The debugger drives the output pins of the BDM JTAG COP connector with the same level as detected on the VCCS pin If the IO pins of the processor are 3 3 V compatible then the VCCS should be connected to 3 3 V See also System Up Errors ESD Protection NOTE To prevent debugger and target from damage it is recommended to connect or disconnect the debug cable only while the target power is OFF Recommendation for the software start f owns w Disconnect the debug cable from the target while the target power is off Connect the host system the TRACE32 hardware and the debug cable Power ON the TRACE32 hardware Start the TRACE32 software to load the debugger firmware Connect the debug cable to the target Switch the target power ON Configure your debugger e g via a start up script Power down 1 2 3
16. e and click through the hotkeys 1989 2015 Lauterbach GmbH PWhficient Debugger 19 General SYStem Commands SYStem CpuAccess Run time CPU access intrusive Format SYStem CpuAccess lt mode gt mode Enable Denied Nonstop This option declares if an intrusive memory access can take place while the CPU is executing code To perform this access the debugger stops the CPU shortly performs the access and then restarts the CPU The run time memory access has to be activated for each window by using the memory class E e g Data dump E 0x100 or by using the format option E e g Var View E var1 Enable In order to perform a memory read or write while the CPU is executing the program the debugger stops the program execution shortly Each short stop takes 1 100 ms depending on the speed of the debug interface and on the size of the read write accesses required Denied No intrusive memory read or write is possible while the CPU is executing the program Nonstop Nonstop ensures that the program execution can not be stopped and that the debugger doesn t affect the real time behavior of the CPU Nonstop reduces the functionality of the debugger to run time access to memory and variables trace display The debugger inhibits the following to stop the program execution all features of the debugger that are intrusive e g spot breakpoints per formance analysis via StopAndGo conditional breakpoint
17. es Breakpoints on data addresses are bound to several conditions 1 The source of the data access read and or write must be the CPU as the data address breakpoints are part of the CPU Any other accesses from on chip or off chip peripherals DMA etc will not be recognized by the data address breakpoints 2 The data being targeted must be qualified by an address in memory It is not possible to set a data address breakpoint to GPR SPR etc 1989 2015 Lauterbach GmbH PWhficient Debugger PWhficient PA6T Specific Implementations Memory Classes To specify which and how target memory is accessed there are memory classes A memory class consists of one or more letters followed by a colon Memory classes can be applied almost everywhere an address has to be specified Here are some examples Command Effect DATA LIST P 0x1000 Opens a List window displaying program memory DATA SET SPR 256 Long 0x00223344 Write value 0x00223344 to SPR VRSAVE The following memory classes are available Memory Class Description P Program D Data SPR Special Purpose Register IC Instruction Cache DC Data Cache NC No Cache only physical memory In addition to the memory classes there are memory class attributes Examples Command Effect DATA LIST SP 0x1000 Opens a List window displaying supervisor program memory DATA SET ED 0x3330 Ox4F Write Ox4F to addre
18. esponding bit in the DBCRO register before resuming the CPU 1989 2015 Lauterbach GmbH PWhficient Debugger 32 CPU specific TrOnchip Commands TrOnchip VarCONVert Adjust hll breakpoint in on chip resource Format TrOnchip VarCONVert ON OFF ON default After a data address breakpoint is set to an hll variable all on chip breakpoints are spent As soon as a new data address breakpoint is set the data address breakpoint to the hll variable is converted to a single data address breakpoint Please be aware that the breakpoint is still listed as a range breakpoint in the Break List window Use the Data View command to verify the set data address breakpoints OFF An error message is displayed when the user wants to set a new data address breakpoint after all on chip breakpoints are spent by a data address breakpoint to an hll variable TrOnchip CONVert ON Var Break Set flags Var Break Set ast Data View flags Data View ast 1989 2015 Lauterbach GmbH PWhficient Debugger 33 CPU specific TrOnchip Commands TrOnchip view View on chip trigger setup window Format TrOnchip view Display the trigger setup dialog window Ss B TrOnchip DER CONVert VarCONVert EVTI BusTtiggerDE Set OBRT C IRPT C CIRPT CRET CI CRET 1989 2015 Lauterbach GmbH PWhficient Debugger CPU specific TrOnchip Commands JTAG Connector Signal TDO TDI QREQ TCK TMS SRESET HRESET CKSTO
19. ftware version are usually not supported Please download and install the latest software from our homepage or contact technical support to get a newer software Please also check if the processor or the software update is covered by your current licence A JTAG communication error prevented correct determination of the connected processor Please check if the debugger is properly connected to the target Target Reset Fail On SYStem Up the debugger will assert HReset in order to stop the CPU at the reset address A target reset fail means that an unexpected reset behavior caused an error The reset is asserted longer than 500ms and is not visible on the JTAG connector Please check the signal level of the JTAG HRESET pin The target reset is permanently asserted Check target reset circuitry and reset pull up A chip external watchdog caused a reset after the debugger asserted reset Disable the watchdog and try again 1989 2015 Lauterbach GmbH PWhficient Debugger 8 Troubleshooting Emulation Debug Port Fail An emulation debug port fail can have a variety of reasons Please check the AREA window for a detailed error message Here is a collection of frequently seen issues e JTAG communication error Please check the signals on the debug connector e Problems related with Reset can not always be detected as those Please check Target Reset Fail e AREA window error message Error reading BPTR This error usually occurs if the CPU
20. gic Inc 3 0 4 0 5 0 uC OS II Micrium Inc 2 0 to 2 92 ulTRON HI7000 RX4000 NORTi PrKernel VRTXsa Mentor Graphics Corporation VxWorks Wind River Systems 5 x to 7 x PWRficient Debugger 1989 2015 Lauterbach GmbH 38 Support 3rd Party Tool Integrations CPU Tool Company Host ALL ADENEO Adeneo Embedded ALL X TOOLS X32 blue river software GmbH Windows ALL CODEWRIGHT Borland Software Windows Corporation ALL CODE CONFIDENCE Code Confidence Ltd Windows TOOLS ALL CODE CONFIDENCE Code Confidence Ltd Linux TOOLS ALL EASYCODE EASYCODE GmbH Windows ALL ECLIPSE Eclipse Foundation Inc Windows ALL RHAPSODY IN MICROC IBM Corp Windows ALL RHAPSODY IN C IBM Corp Windows ALL CHRONVIEW Inchron GmbH Windows ALL LDRA TOOL SUITE LDRA Technology Inc Windows ALL UML DEBUGGER LieberLieber Software Windows GmbH ALL ATTOL TOOLS MicroMax Inc Windows ALL VISUAL BASIC Microsoft Corporation Windows INTERFACE ALL LABVIEW NATIONAL Windows INSTRUMENTS Corporation ALL CODE BLOCKS Open Source ALL C TEST Parasoft Windows ALL RAPITIME Rapita Systems Ltd Windows ALL DA C RistanCASE Windows ALL TRACEANALYZER Symtavision GmbH Windows ALL SIMULINK The MathWorks Inc Windows ALL TA INSPECTOR Timing Architects GmbH Windows ALL UNDODB Undo Software Linux ALL VECTORCAST Vector Software Windows ALL WINDOWS CE PLATF Windows Windows BUILDER
21. ns that occur on the internal memory bus if the selected inferface The trace buffer holds information about transaction address transaction type source and target ID and the byte count The interface can be selected with the command Onchip Mode IFSel All other configurations can be done directly via the peripheral view in the section Debug Features and Watchpoint Facility Here is an example on how to set up the on chip trace buffer to trace the data accesses of the PowerPC core Please note that only uncached accesses will be recorded in the trace buffer Select interface ECM Onchip Mode IFSEL ECM configure onchip trace TBCRO address match disable 0x40000000 8 transaction match disable 0x20000000 3 source ID enable 0x04000000 8 method trace events 0x00020000 Data Set iobase address 0x000E2040 LONG 0x64020000 TBCR1 src ID d fetch 0x00110000 Data Set iobase address 0x000E2044 LONG 0x00110000 enable automatically when CPU is started Onchip AutoArm ON initialize trace buffer Onchip Init Start program until some func is reached Go some func display trace buffer Onchip List Regarding instruction fetch traces please note that the trace buffer is connected outside the caches so instruction fetches on cached addresses will not appear in the trace As the core will always fetch a full instruction cache way 32 bytes at once the program trace can not be reconstructed using this on chip trace For mo
22. oints on code in read only memory only the on chip instruction address breakpoints are available With the command MAP BOnchip range it is possible to declare memory address ranges for use with on chip breakpoints to the debugger The number of breakpoints is then limited by the number of available on chip instruction address breakpoints On chip breakpoints Total amount of available on chip breakpoints Instruction address breakpoints Number of on chip breakpoints that can be used to set Program breakpoints into ROM FLASH EEPROM Data address breakpoints Number of on chip breakpoints that can be used as Read or Write breakpoints Data value breakpoint Number of on chip data value breakpoints that can be used to stop the program when a specific data value is written to an address or when a specific data value is read from an address CPU Family PA6T On chip Breakpoints 2 Instruction 2 Read Write Instruction Address Breakpoints 2 single breakpoints or 1 breakpoint ranges Data Address Breakpoints 2 single breakpoints or 1 breakpoint range Data Value Breakpoints You can check your currently set breakpoints with the command Break List If no more on chip breakpoints are available you will get an error message on trying to set a new on chip breakpoint PWRficient Debugger 1989 2015 Lauterbach GmbH PWhficient PA6T Specific Implementations Breakpoints on Data Address
23. ommands SYStem Mode Select operation mode Format SYStem Mode mode mode Down NoDebug Go Attach StandBy Up Select target reset mode Down Disables the debugger The state of the CPU remains unchanged NoDebug Resets the target with debug mode disabled In this mode no debugging is possible The CPU state keeps in the state of NoDebug Go Resets the target with debug mode enabled and prepares the CPU for debug mode entry After this command the CPU is in the SYStem Up mode and running Now the processor can be stopped with the break command or any break condition Attach This command works similar to the Up command The difference is that the target CPU is not reset The BDM JTAG COP interface will be synchronized and the CPU state will be read out After this command the CPU is in the SYStem Up mode and can be stopped for debugging Up Resets the target and sets the CPU to debug mode After execution of this command the CPU is stopped and prepared for debugging All register are set to the default value 1989 2015 Lauterbach GmbH PWhficient Debugger 22 General SYStem Commands SYStem CONFIG Configure debugger according to target topology Format SYStem CONFIG parameter number or address parameter DRPRE JTAG DRPOST IRPRE IRPOST TAPState TCKLevel TriState Slave state The four parameter IRPRE IRPOST DRPRE DRPOST are required to inform the debugger about the T
24. ore of interest and the TDO signal of the debugger This is the sum of the instruction register length of all TAPs between the core of interest and the TDO signal of the debugger default 0 number of instruction register bits in the JTAG chain between the TDI signal and the core of interest This is the sum of the instruction register lengths of all TAPs between the TDI signal of the debugger and the core of interest default 7 2 Select DR Scan This is the state of the TAP controller when the debugger switches to tristate mode All states of the JTAG TAP controller are selectable default O Level of TCK signal when all debuggers are tristated default OFF If more than one debugger share the same JTAG port this option is required The debugger switches to tristate mode after each JTAG access Then other debuggers can access the port default OFF If more than one debugger share the same JTAG port all except one must have this option active Only one debugger the master is allowed to control the signals nNTRST and nSRST nRESET Show state TDI gt Core A gt Core B gt PA6T gt Core C gt TDO PWhficient Debugger 1989 2015 Lauterbach GmbH 24 General SYStem Commands Instruction register length of Core A 3 bit Core B 5 bit Core C 6 bit SYStem CONFIG IRPRE 6 SYStem CONFIG IRPOST 8 SYStem CONFIG DRPRE 1 SYStem CONFIG DRPOST 2 SYStem Up TapStates PWRfi
25. p Break Load the program Data LOAD ELf demo elf ELF specifies the format demo elf is the file name The option of the Data LOAD command depends on the file format generated by the compiler For information on the compiler options refer to the section Compiler A detailed description of the Data LOAD command is given in the General Commands Reference 1989 2015 Lauterbach GmbH PWhRficient Debugger 7 Quick Start Troubleshooting SYStem Up Errors The SYStem Up or SYStem Attach command is the first command of a debug session where communication with the target is required If you receive error messages while executing this command there can be several reasons The next sections list possible errors and explains how to fix them Target Power Fail The Target has no power the debug cable is not connected or not connected properly Check if the JTAG VCC pin is driven by the target The voltage of the pin must be identical to the debug voltage of the JTAG signals It is recommended to connect VCC directly to the pin or via a resistor lt 5 KO Emulation Pod Configuration Error The debugger was not able to determine the connected processor There are two possible reasons for this error In both cases please check the AREA window for more information The connected processor is not supported by the used software Please check if the processor is supported by the debugger Processors that appeared later than the debugger so
26. re information about general trace commands see Trace in General Commands Reference Guide T and Onchip Trace Commands in General Commands Reference Guide O 1989 2015 Lauterbach GmbH PWhficient Debugger PWhficient PA6T Specific Implementations General SYStem Commands SYStem BdmClock Set BDM clock frequency Format SYStem BdmClock lt rate gt lt rate gt 100000 50000000 100kHz 50MHz Selects the frequency for the debug interface For multicore debugging it is recommended to set the same JTAG frequency for all cores SYStem CPU Select the CPU type Format SYStem CPU lt cpu gt lt cpu gt PA6T1682 PAGT1672 PA6T1352 Selects the CPU type If the needed CPU type is not available in the CPU selection of the SYStem window or if the command results in an error check if the licence of the debug cable includes the desired CPU type You will find the information in the VERSION window if the debugger software is up to date Please check the VERSION window to see which version is installed CPUs that appeared later than the software release are usually not supported Please check www lauterbach com for updates If the needed CPU appeared after the release date of the debugger software please contact technical support and request a software update e if the CPU name matches one the names in the CPU selection Search for the CPU name in the SYStem window or type SYStem CPU to the command lin
27. s etc SYStem LOCK Lock and tristate the debug port Format SYStem LOCK ON OFF Default OFF If the system is locked no access to the debug port will be performed by the debugger While locked the debug connector of the debugger is tristated The main intention of the lock command is to give debug access to another tool The command has no effect for the simulator 1989 2015 Lauterbach GmbH PWhficient Debugger 20 General SYStem Commands SYStem MemAccess Run time memory access non intrusive Format SYStem MemAccess mode mode Denied CPU This option declares if and how a non intrusive memory access can take place while the CPU is executing code Although the CPU is not halted run time memory access creates an additional load on the processors internal data bus The run time memory access has to be activated for each window by using the memory class E e g Data dump E 0x100 or by using the format option E e g Var View E var It is also possible to activate this non intrusive memory access for all memory ranges displayed on the TRACE32 screen by setting SYStem Option DUALPORT ON Denied Memory access is disabled while the CPU is executing code CPU The debugger performs memory accesses via a dedicated CPU interface This memory access will snoop data cache and L2 cache if a memory class for data D is used 1989 2015 Lauterbach GmbH PWhficient Debugger 21 General SYStem C
28. s functionality is currently in development 1989 2015 Lauterbach GmbH PWhficient Debugger 29 CPU specific MMU Commands MMU TLB Set Set an MMU TLB entry Format MMU TLB Set index lt mas1 gt mas2 lt mas3 gt mas index TLB entry index From 0 to number of TLB entries 1 of the specified TLB table lt mas1 gt Values corresponding to the values that would be written to the MAS1 2 3 lt mas2 gt registers in order to set a TLB entry See chip user s manual for details on MAS lt mas3 gt registers Sets the specified MMU TLB table entry in the CPU The parameter lt tlb gt is not available for CPUs with only one TLB table MMU TLB Set 0x1 0x80000300 0x00000000 0x4000003f Note This functionality is currently in development 1989 2015 Lauterbach GmbH PWhRficient Debugger 30 CPU specific MMU Commands CPU specific TrOnchip Commands Note This functionality is currently in development TrOnchip CONVert Adjust range breakpoint in on chip resource Format TrOnchip CONVert ON OFF There are 2 data address breakpoints These breakpoints can be used to mark two single data addresses or one data address range ON default After a data address breakpoint is set to an address range all on chip breakpoints are spent As soon as a new data address breakpoint is set the data address breakpoint to the address range is converted to a single data address breakpoint Please be aware that the
29. ss 0x3330 using real time memory access The following memory class attributes are available Memory Class Description E Use real time memory access A Given address is physical bypass MMU U User memory S Supervisor memory Memory class attributes can also be used without a memory class but U and S are usually combined with D and P UD user data SD supervisor data UP user program UD user data 1989 2015 Lauterbach GmbH PWhficient Debugger PWhficient PA6T Specific Implementations Cache Memory Coherency The following table describes which memory will be updated depending on the selected memory class memory class D Cache I Cache L2 Cache Memory uncached DC updated not updated not updated not updated IC not updated updated not updated not updated L2 not updated not updated updated not updated NC not updated not updated not updated updated D updated not updated updated updated P not updated updated updated updated Depending on the debugger configuration the coherency of the instruction cache will not be achieved by updating the instruction cache but by invalidating the instruction cache See SYStem Option ICFLUSH Invalidate instruction cache before go step debugger_pwr pdf for details MOESI States The cache logic of PWRficient PowerPC cores behaves according to the MOESI state model PowerlSA Book III S To maintain a
30. suitable for JTAG debuggers Debug cable The T32 internal buffer level shifter will be supplied via the VCCS pin with blue Therefore it is necessary to reduce the VCCS pull up on the target board ribbon cable to a value smaller 10 1989 2015 Lauterbach GmbH PWhficient Debugger 6 Target Design Requirement Recommendations Quick Start Starting up the Debugger is done as follows 1 Select the device prompt B for the ICD Debugger only necessary if the device prompt is not active after the TRACE32 software was started Jazz Select the CPU type to load the CPU specific settings If your CPU is not listed you can use one of the generic CPU types MPC85XX MPX55XX SYStem CPU PA6T1682 Specify that on chip breakpoints should be used by the debugger if a program breakpoint is set to the boot page read only memory MAP BOnchip OxFFFFF000 OxFFFFFFFF For simplicity we now use CFE for the complex SoC initialisation and let the target run until the CFE prompt is displayed in the terminal window SYStem Mode Attach The default state after selecting the CPU type SYStem Mode Down holds the CPU in reset HRESET SYStem Mode Attach releases reset and lets the CPU run but uses active JTAG lines to poll the current system state When the CFE command prompt is displayed in the terminal any terminal of your liking or you can use our built in terminal using the TERM command break into the CFE command loo
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