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S1D13705 TECHNICAL MANUAL

1. g 9 S y y E L r p P 6661 yO Menuer AepuoN Sd o 8 ne Jequiny jwawnoog azi ddns Jemod Q97 PIB08 uoa O L ABH SNE VSI DOOASOLELNSS 9u juewdojarag yoeasay vosd3 vOLOHbZ vOLOHYL vOLOHbL vOLOHYL A dl Z A Z 4 A aro ore Hir Bos 6 Se y vr v a aen gen L aen 1 o6n DOA ODA 99A 29A aNosd Taou ON9Sd a DONSd OBA ODN el E 30d 1001 HSI MOT ASE ANS bey ezo lo z YOSELANN zo AgWANLy aon CANE Xo ont lt DOASd 001 lo EURO jalo fo alt ozy a S a S 3 8 8883 22 5 88 6lu 8lu eA Cy er O O A zz P E Z gt 2 DAS le MOL TOONS 906 LAWN LN w N vate ho o aaaol la aNosd AbL S oy E YMd001 lt POLOHPL Ie 7 t FEMAITOT yO Al nda Ea yl Wd M00Z lt aen Sla NOS 3NZY nosing l lt aosan o 020 619 Joo ngt indy o 819 95A ASLy HL viu Haga GOW SE DOASd 4 FS Yo Halooo lo fro lt 000000 g M 8 O 5 ZEZE f O 1 Cc o0o000co a oa Q z EN Q 33 m 2 20 09 on g 9 S E y E L Figure 8 4 SID1I3705BO0C Schematic Diagram 4 of 4 1D13705 X27A G 005 03 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 Page 24 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 S5U13705B00C Rev
2. AK Vancouver Design Center Copyright c Seiko Epson Corp 1998 All rights reserved kk el ifndef HAL REGS_H defin HAL REGS_H PER 13705 register names 7 define REG_REVISION_CODE 0x00 define REG_MODE_REGISTER_0 0x01 define REG_MODE_REGISTER_1 0x02 define REG_MODE_REGISTER_2 0x03 define REG_HORZ_PANEL_SIZE 0x04 define REG_VERT_PANEL_SIZE_LSB 0x05 define REG_VERT_PANEL_SIZE_MSB 0x06 define REG_FPLINE_START_POS 0x07 define REG_HORZ_NONDISP_PERIOD 0x08 define REG_FPFRAME_START_POS 0x09 define REG_VERT_NONDISP_PERIOD Ox0A define REG_MOD_RATE Ox0B define REG_SCRN1_START_ADDR_LSB Ox0C define REG_SCRN1_START_ADDR_MSB Ox0D define REG_SCRN2_START_ADDR_LSB Ox0E define REG_SCRN2_START_ADDR_MSB Ox0F define REG_SCRN_START_ADDR_OVERFLOW 0x10 define REG_MEMORY_ADDR_OFFSET 0x11 define REG_SCRN1_VERT_SIZE_LSB 0x12 define REG_SCRN1_VERT_SIZE_MSB 0x13 define REG_LUT_ADDR 0x15 define REG_LUT_BANK_SELECT 0x16 define REG_LUT_DATA 0x17 define REG_GPIO_CONFIG 0x18 define REG_GPIO_STATUS 0x19 define REG_SCRATCHPAD Ox1A define REG_PORTRAIT_MODE Ox1B define REG_LINE BYTE _COUNT 0x1C define REG_NOT_PRESENT_1 Ox1D WARNING MAX_REG must be the last available register ty defin AX_REG Ox1D ndif ess HAL _REGS_H 1D13705 Programming Notes and Example
3. TBcLK Sot INN E L A A 16 0 VALID CS ff tl t2 1 gt t gt WE0 WE1 RDO RD1 B y t5 D 15 0 Hi Z write Ee Y t4 t6 t7 gt D 15 0 Hi Z VALID Hi Z read Hi Z Hi Z WAIT be t11 z Figure 7 5 Generic 1 Timing Table 7 5 Generic 1 Timing Symbol Parameter Min Max Units fecik Bus Clock frequency 50 MHz Tecik Bus Clock period 1 fBCLK MHz u A 16 0 CS valid to WEO WE14 low write cycle or RDO RD1 0 He low read cycle 12 WEO WE1 high write cycle or RDO RD1 high read cycle to 0 fie A 16 0 CS invalid t3 WEO WE1 low to D 15 0 valid write cycle TBcLk t4 RDO RD1 low to D 15 0 driven read cycle 17 ns t5 WEO WE1 high to D 15 0 invalid write cycle 0 ns t6 D 15 0 valid to WAIT high read cycle 0 ns t7 RDO RD1 high to D 15 0 high impedance read cycle 10 ns 18 WE0 WE1 low write cycle or RDO RD1 low read cycle to 16 n WAIT driven low t9 BCLK to WAIT high 16 ns HO WEO WE1 high write cycle or RDO RD1 high read cycle to 16 AG WAIT high impedance t11 WAIT high to WE0 WE1 RDO RD1 high 1TecLk Note BCLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 84 S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 33 Vanc
4. Epson Research and Development Page 43 Vancouver Design Center tl 2 Sync Timing iy Es Frame Pulse p t4 a t3 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t8 t9 t7 t14 t11 t10 lt 4 Pit gt lt gt Shift Pulse ez t12 t13 FPDAT 7 4 a x Figure 7 16 Single Color 4 Bit Panel A C Timing Table 7 13 Single Color 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 0 5 Ts t9 Shift Pulse period 1 Ts t10 Shift Pulse pulse width low 0 5 Ts t11 Shift Pulse pulse width high 0 5 Ts t12 FPDAT 7 4 setup to Shift Pulse falling edge 0 5 Ts t13 FPDAT 7 4 hold to Shift Pulse falling edge 0 5 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 24 Ts 1 Ts pixel clock period 2 timin t8min 9Ts 3 tBmin REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 1 5 Ts 5 t min REG O8h bits 4 0 x 8 10 Ts Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 44
5. 0 5 0 1 k 0 18 0 05 20 0 1 gt te S1D13705 X27A A 001 10 Figure 14 1 Mechanical Drawing OFP14 Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 87 Vancouver Design Center 15 Sales and Technical Support Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http Awww epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192
6. E bes 4 bit Gray Data pe A 10 411 04 L FC FD FE FF 2 bit per pixel data from Display Buffer unused Look Up Table entries Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 72 4 Bit per pixel Monochrome Mode Epson Research and Development Vancouver Design Center from Display Buffer Green Look Up Table 256x4 4 bit per pixel data 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 4 bit Gray Data unused Look Up Table entries S1D13705 X27A A 001 10 Figure 11 3 4 Bit per pixel Monochrome Mode Data Output Path Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center 11 2 Color Modes 1 Bit per pixel Color Mode Page 73 Red Look Up Table 256x4 00 01 4 bit Red Data 02 Green Look Up Table 256x4 00 4 bit Green Data 01 02 Blue Look Up Table 256x4 a rt 00 01 4 bit Blue Data 02 1 bit per pixel da
7. Epson Research and Development Page 61 Vancouver Design Center REG 07h FPLINE Start Position Address 1FFE7h Read Write Ala AS wa FPLINE Start FPLINE Start FPLINE Start FPLINE Start FPLINE Start Position Bit 4 Position Bit 3 Position Bit 2 Position Bit 1 Position Bit O bits 4 0 FPLINE Start Position These bits are used in TFT D TFD mode to specify the position of the FPLINE pulse These bits specify the delay in 8 pixel resolution from the end of a line of display data FPDAT to the leading edge of FPLINE This register is effective in TFT D TFD mode only REG 01h bit 7 1 This register is programmed as follows FPLINEposition pixels REG 07h 2 x 8 The following constraint must be satisfied REG 07h lt REG 08h REG 08h Horizontal Non Display Period Address 1FFE8h Read Write Horizontal Horizontal Horizontal Horizontal Horizontal n a n a n a Non Display Non Display Non Display Non Display Non Display Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bits 4 0 Horizontal Non Display Period These bits specify the horizontal non display period in 8 pixel resolution HorizontalNonDisplayPeriod pixels REG 08h 4 x 8 REG 09h FPFRAME Start Position Address 1FFE9h Read Write FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME n a n a Start Position Start Position Start Position
8. Vi VIL 10 tp A K gt ty 1 TeLKI Figure 7 7 Clock Input Requirements for CLKI Table 7 7 Clock Input Requirements for CLKI Symbol Parameter Min Max Units Fx Input Clock Frequency CLKI 50 MHz Toki Input Clock period CLKI Wok ns town Input Clock Pulse Width High CLKI 8 ns bowl Input Clock Pulse Width Low CLKI 8 ns t Input Clock Fall Time 10 90 ns t Input Clock Rise Time 10 90 ns Note When CLKI is gt 25MHz the Input Clock Divide bit REG 02h bit 4 must be set to 1 S1D13705 X27A A 001 10 Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 35 Vancouver Design Center Clock Input Waveform PWH mil PWL 90 Vin VIL 10 tp t gt t 4 TBCLK Figure 7 8 Clock Input Requirements for BCLK Table 7 8 Clock Input Requirements for BCLK Symbol Parameter Min Max Units fBCLK Input Clock Frequency BCLK 50 MHz Tack Input Clock period BCLK Wer town Input Clock Pulse Width High BCLK 8 ns tow Input Clock Pulse Width Low BCLK 8 ns t Input Clock Fall Time 10 90 5 ns t Input Clock Rise Time 10 90 5 ns Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 36 Epson Research and Development Vancouver Design Center 7 3 Display Interface 7 3 1 Power On Reset Timing
9. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 REG 0Dh Screen 1 Start Word Address MSB bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 REG OEh Screen 1 Start Word Address MSB n a n a n a n a n a n a n a bit 16 The Screen 1 Start Address registers must be set correctly for portrait mode In portrait mode the Start Address registers form a byte offset as opposed to a word offset into display memory The initial required offset is the portrait mode stride in bytes less one REG 1Ch Line Byte Count Register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 The line byte count register informs the S1D13705 of the stride in bytes between two consecutive lines of display in portrait mode The Line Byte Count register only affects portrait mode operation and are ignored when the S1D13705 is in landscape display mode REG 1Bh Portrait Mode Register Portrait Mode Portrait Mode Portrait Mode Portrait Mode Portrait Mode Enable Select n a n a n a Memory Pixel Clock Pixel Clock Clock Select Select Bit 1 Select Bit 0 The portrait mode register contains several items for portrait mode support The first is the Portrait Mode Enable bit When this bit is 0 the S1D13705 is in landscape mode and the remainder of the settings in this register as well as the Line Byte Count in REG 1Ch are ignored Set this bit to
10. 65 1 2 4 8 Bit Per Pixel Display Data Memory Organization 70 1 Bit per pixel Monochrome Mode Data Output Path 71 S1D13705 X27A A 001 10 Page 8 Epson Research and Development Vancouver Design Center Figure 11 2 2 Bit per pixel Monochrome Mode Data Output Path 71 Figure 11 3 4 Bit per pixel Monochrome Mode Data Output Path 72 Figure 11 4 1 Bit per pixel Color Mode Data Output Path 2 2 ee ee 73 Figure 11 5 2 Bit per pixel Color Mode Data Output Path ee ee 74 Figure 11 6 4 Bit per pixel Color Mode Data Output Path 2 2 ee ee 75 Figure 11 7 8 Bit per pixel Color Mode Data Output Path o o 76 Figure 12 1 Relationship Between The Screen Image and the Image Refreshed by S1D13703 in Default Mode e 77 Figure 12 2 Relationship Between The Screen Image and the Image Refreshed by S1D13703 in Alternate Mode 2 2 e 79 Figure 13 1 Panel On Off Sequence 2 ee 84 Figure 14 1 Mechanical Drawing QFP14 0 e e 86 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 9 Vancouver Design Center 1 Introduction 1 1 Scope This is the Hardware Functional Specification for the S1D13705 Embedded Memory LCD Controller Chip Included in this document are timing diagrams AC and DC character istics re
11. _ RESET Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 3 1 Typical Implementation of MC68EZ328 to SIDI3705 Interface Generic 1 Interfacing to the Motorola Dragonball Family of Microprocessors 1D13705 Issue Date 01 02 13 X27A G 007 04 Page 20 Epson Research and Development Vancouver Design Center 3 4 2 S1D13705 Hardware Configuration The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the 1D 3705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show those configuration settings important to the Generic 1 host bus interface Table 3 2 Summary of Power On Reset Options S1D1370 value on this pin at the rising edge of RESET is used to configure 1 0 5 Pin Name 0 a CNFO CNF1 See Table 2 3 Host Bus Interface Selection CNF2 CER COE y configuration for MC68EZ328 support Table 3 3 Host Bus Interface Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 X reserved 0 1 1 X MC68K 1 16 bit 1 0 0 X reserved 1 0 1 X MC68K 2 16
12. e 8 2 2 Register Values suela es a ad a A y na ad E 8 2 3 Frame Rate Calculation 3 Memory Models eis wae eee eB ee la a a ee E e ee ee a ile 12 3 1 1 Bit Per Pixel 2 Colors Gray Shades 2 2 12 3 2 2 Bit Per Pixel 4 Colors Gray Shades 13 3 3 4Bit Per Pixel 16 Colors Gray Shades 2 ee 13 3 4 Eight Bit Per Pixel 256 Colors a a ee ee ee ee ee 14 4 Look Up Table LUT 20 20 40 ee 15 4 1 Look Up Table Registers 2 2 ee 16 4 2 Look Up Table Organization 2 2 2 ee eee ee 17 4 21 Color Modes 3 2 4 5 4c 3 Sede AS Eee hy BAR Re eh ae oe Bg de a 17 4 2 2 Gray Shade Modes 2 6 2b ee ee ee ee ee ee ye ee 22 5 Advanced Techniques lt lt ee ee es 25 5 1 Virtual Display o seus aa Gk dee ae a Ge a ee Re A ed bd DRESiSters s o Sep ag A Ser tee nn Fores oh ats aie Sy Reeth A ea i D 26 OA Examples moree ten ane a al da Goes ke an ane a a Be 26 5 2 Panningand Scrolling 2 2 a a ee 27 S2 CREgISTErS hai Eee bh PS ae ad a 28 liz TE XaMples ir EA eg a ae ee A eed DS A Bde et 29 9 3 SplitScreen aios ao A Wek te eg a a aa A ae BS A TRESIStErS lt ae ue as Rea ae ecard Sia Sern at aE Ae iva dun Sy a eet oe 32 O32 Examples merr p ace ee ae Bal a E A An ea irae Baek gh ay BO 34 6 LCD Power Sequencing and Power Save Modes 35 6 1 LCD Power
13. The data in this file was generated using 13705CFG EXE The configureation parameters chosen were 320x240 Single Color 4 bit STN 4 bpp 100 Hz Frame Rate 12 MHz CLKi High Performance enabled E AA 13705 HAL HDR do not remove HAL STRUCT Information generated by 13705CFG EX Copyright c 1998 Epson Research and Development Inc All rights reserved El Ei Include this file ONCE in your primary source file E AA HAL_STRUCT HaliInfo y 13705 HAL EXE ID string ay 0x1234 Detect Endian sizeof HAL STRUCT Size 0x00 0x20 0xC0 0x03 0x27 OxEF 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 OxFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 6000 C1kI kHz 0xF00000 Display Address 70 Panel Frame Rate Hz Programming Notes and Examples Issue Date 02 01 22 0x00 0x00 0x00 0x00 nl E S1D13705 X27A G 002 03 Page 82 Epson Research and Development Vancouver Design Center HAL REGS H Created 1998 Epson Research amp Development
14. 4 3 3 MC68K 1 Interface Mode 4 4 MC68VZ328 To S1D13705 Interface 4 4 1 Hardware Description s ooa e 4 4 2 S1D13705 Hardware Configuration 4 4 3 MC68VZ328 Chip Select and Pin Configuration Dl SOWANG ikoe a a e d e ee A a id Referentes tiara a a ele aa A ee ds E 6 1 Documents Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Page 3 1D13705 X27A G 007 04 Page 4 Epson Research and Development Vancouver Design Center 62 Document Sources o ZO 7 Technical Support sas sos onno m ea E A AAA wes 30 7 1 EPSON LCD Controllers S1D13705 a a a aaa 30 7 2 Motorola Dragonball Processors 2 a a ee ee ee ee ee 80 1D13705 Interfacing to the Motorola Dragonball Family of Microprocessors X27A G 007 04 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 Host Bus Interface Pin Mapping 2 000000 ee eee 9 Table 2 2 Summary of Power On Reset Options o e 14 Table 2 3 Host Bus Interface Selection o e 14 Table 3 1 Host Bus Interface Pin Mapping 0000000020000 48 16 Table 3 2 Summary of Power On Reset Options o o e 19 Table 3 3 Host Bus Interface Selection o e 19 Table 4 1 Host Bus Interface Pin Mapping e 21 Table 4 2 Summary of Power
15. Register 08h Horizontal Non Display Period Reg 08 4 8 E 0 4 8 32 pels a HNDP and VNDP are calculated to achieve the ES desired frame rate according to kk aX PCLK EK Frame Rat ER HDP HNDP VDP VNDP ee SET_REG 0x08 0x00 Register 09h FPFRAME Start Position not used by SIN E SET_REG 0x09 0x00 Register OAh Vertical Non Display Register 3 lines ER Calculated in conjunction with register 08h HNDP to EK achieve the desired frame rate SET_REG Ox0A 0x03 Register OBh MOD Rate not used by this panel EY SET_REG 0x0B 0x00 j gt Register OCh Screen 1 Start Word Address LSB Register ODh Screen 1 Start Word Address MSB EK Start address should be set to 0 SET_REG 0x0C 0x00 SET_REG 0x0D 0x00 Register OEh Screen 2 Start Word Address LSB Register OFh Screen 2 Start Word Address MSB aX Set this start address to 0 too sy SET_REG 0x0E 0x00 SET_REG 0x0F 0x00 SET_REG 0x10 0x00 Screenl Screen2 Start Address High bits Register 11h Memory Address Offset ER Used for setting memory to a width greater than the aX display size Usually set to 0 during initialization ER and programmed to desired value later 3 Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Epson Research and Development Vancouver Design Center SET_REG 0x11 0x00 Register 12h Screen
16. sg 04 HOM HIM YMW 0Y siaa vlad erga gtaa 1180 olga 68d 8ga 80 980 sga vad ega grav sigay lav elay clay Law orgy sav sav gav sav egy zav ogy L gt _z fe GdAOl o L sal gt 2 xde ZL 09 OF 02 ede Edf anto anro any 9T eS Z or anto _ anto anto anto ie ngop sa 3 uid amod Jad sioyoedeg ssed Ag gt UYM tS lt W9 tz bosna lt lt 99 lt lt as3y sa 04 0JM IM Sp 9VSs S STVS eS PIS SS ES 9S MEN 86 ols 6S Y LEN 4 HMH lt sr olas lt Terolvs ler olvs GGAOI AEE EZ GGAOI AD S Zt 30V3SH ODA o lt L qa tdr Figure 8 1 SIDI3705B00C Schematic Diagram 1 of 4 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13705 Issue Date 01 02 13 X27A G 005 03 Page 21 Epson Research and Development Vancouver Design Center S1D13705 X27A G 005 03 Figure 8 2 SIDI3705B00C Schematic Diagram 2 of 4 01 02 13 g 9 S y y E L
17. 1 12 bit TFT D TFD panel 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 57 Vancouver Design Center REG 02h Mode Register 1 Address 1FFE2h Read Write Bit Per Pixel Bit Per Pixel High aprit clock Frame aroware Software Bit 1 Bit O TA D aioe Display Blank Repeat Video Invert Video Invert CLKI 2 P Enable bits 7 6 Bit Per Pixel Bits 1 0 These bits select the color or gray scale depth Display Mode Table 8 2 Gray Scale Color Mode Selection Color Mono Bit Per Pixel Bit 1 Bit Per Pixel Bit 0 A Display Mode REG 01h bit 5 REG 02h bit 7 REG 02h bit 6 0 0 2 Gray scale 1 bit per pixel 0 1 4 Gray scale 2 bit per pixel 0 16 Gray scale 4 bit per pixel 1 reserved 0 0 2 Colors 1 bit per pixel 1 4 Colors 2 bit per pixel 0 16 Colors 4 bit per pixel 1 256 Colors 8 bit per pixel bit 5 High Performance Landscape Modes Only When this bit 0 the internal Memory Clock MCLK is a divided down version of the Pixel Clock PCLK The denominator is dependent on the bit per pixel mode see the table below Table 8 3 High Performance Selection High Performance BPP Bit 1 BPP Bit 0 Display Modes 0 MCIk PCIk 8 1 bit per pixel i 1 MCIk PCIk 4 2 bit per pixel 3 i 0 MCIk PCIK 2 4 bit per pixel 1 MCIk PClk 8 bit per pixel 1 X X MCIk
18. 1D13705 X27A G 002 03 These functions deal with altering the color values in the Look Up Table int seSetLut BYTE pLut int Count Description Parameters This routine writes one or more LUT entries The writes always start with Look Up Table index 0 and continue for Count entries A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four most significant bits of each byte pLut pointer to an array of BYTE lut 16 3 lut x 0 RED component lut x 1 GREEN component lut x 2 BLUE component Count the number of LUT entries to write Return Value ERR_OK operation completed with no problems int seGetLut BYTE pLUT int Count Description Parameters This routine reads one or more LUT entries and puts the result in the byte array pointed to by pLUT A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four most significant bits of each byte pLUT pointer to an array of BYTE lut 16 3 pLUT must point to enough memory to hold Count x 3 bytes of data Count the number of LUT elements to read Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 63 Vancouver Design Center int seSetLutEntry int Index BYTE pEntry Description This routine writes one L
19. For example writing a value 03h into the LUT Address Register sets the pointer to R 3 A subsequent access to the LUT Data Register accesses R 3 and moves the pointer onto G 3 Subsequent accesses to the LUT Data Register move the pointer onto B 3 R 4 G 4 B 4 R 5 etc Note The RGB data is inserted into the LUT after the Blue data is written i e all three colors must be written before the LUT is updated Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 66 Epson Research and Development Vancouver Design Center REG 17h Look Up Table Data Register Address 1FFF7h Read Write LUT Data LUT Data LUT Data LUT Data n a na Wla na Bit 3 Bit 2 Bit 1 Bit 0 bits 7 4 LUT Data Bits 3 0 This register is used to read write the RGB Look Up Tables This register accesses the entry at the pointer controlled by the Look Up Table Address Register REG 15h Accesses to the Look Up Table Data Register automatically increment the pointer Note The RGB data is inserted into the LUT after the Blue data is written 1 e all three colors must be written before the LUT is updated REG 18h GPIO Configuration Control Register Address 1FFF8h Read Write n a n a n a GPIO4 Pin lO Configuration GPIO3 Pin IO Configuration GPIO2 Pin lO Configuration GPIO1 Pin lO Configuration GPIOO Pin IO Configuration bits
20. SA gt gt 16 amp OXFF In this example code the notation REG refers to whatever mechanism is employed to read write the registers Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 30 S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center Example 4 Scrolling Up and Down To scroll down increase the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line To scroll up decrease the value in the Screen 1 Display Start Address Register by the number of words in one virtual scan line A virtual scan line includes both the number of bytes required by the physical display and any extra bytes that may be being used for creating a virtual width on the display The previous dimensions are still in effect for this example i e 320w x 240h virtual size 256h x 64w physical size at 4 bpp Step 1 Determine the number of words in one virtual scanline bytes_per_line pixels_per_line pixels_per_byte 320 2 160 words_per_line bytes_per_line 2 160 2 80 Step 2 Scroll up or down To scroll up StartWord GetStartAddress StartWord words_per_line EE StartWord lt 0 StartWord 0 SetStartAddress StartWord To scroll down StartWord GetStartAddress StartWord words_per_line SetStartAddress StartWord Programming Notes and Examples Issue Date 02 01 22 Epson Researc
21. The file MODEO H located in x wince300 platform cepc drivers display S 1D13705 contains the register values required to set the screen resolution color depth bpp display type display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the console driver If the default does not match the configura tion you are building for then MODEO H will have to be regenerated with the correct information Use the program 13705CFG to generate the header file For information on how to use 13705CFG refer to the 13705CFG Configuration Program User Manual document number X27A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13705 WinCE Drivers Save the new configuration as MODEO H in the wince300 platform cepc drivers display replacing the original configuration file From the Platform window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WINCE300 tree and click on Hardware Specific Files then double click on PLATFORM REG Edit the file PLATFORM REG to match the screen resolution color depth and rotation information in MODE H For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp and a SwivelView mode
22. e Drag the icon X86 DEMO1 onto the desktop using the right mouse button f Click on Copy Here g Rename the icon X86 DEMO1 on the desktop to X86 DEMO by right click ing on the icon and choosing rename h Right click on the icon X86 DEMO7 and click on Properties to bring up the X86 DEMO7 Properties window i Click on Shortcut and replace the string DEMO1 under the entry Target with DEMO7 j Click on OK to finish 5 Create a sub directory named 1D13705 under x wince platform cepc drivers dis play 6 Copy the source code to the 1D13705 subdirectory Windows CE 2 x Display Drivers Issue Date 01 06 07 Epson Research and Development Page 5 Vancouver Design Center 7 Edit the file x wince platform cepc drivers display dirs and add S1D13705 into the list of directories 8 Edit the file PLATFORM BIB located in x wince platform cepc files to set the de fault display driver to the file EPSON DLL EPSON DLL will be created during the build in step 13 Replace or comment out the following lines in PLATFORM BIB IF CEPC_DDI_VGA2BPP ddi dll _FLATRELEASEDIR ddi_vga2 dll NK SH ENDIF IF CEPC_DDI_VGA8BPP ddi dll _FLATRELEASEDIR ddi_vga8 dll NK SH ENDIF IF CEPC_DDI_VGA2BPP IF CEPC_DDI_VGASBPP ddi dll _FLATRELEASEDIR ddi_s364 dll NK SH ENDIF ENDIF with this line ddi dll FLATRELEASEDIRANEPSON dll NK SH 9 The file M
23. 2 3 Frame Rate Calculation Frame rate specifies the number of complete frame which are drawn on the display in one second Configuring a frame rate that is too high or too low adversely effects the quality of the displayed image System configuration imposes certain non variable limitations For instance the width and height of the display panel are fixed as is typically the input clock to the 1D13705 From the following formula it is evident that the two variables the programmer can use to adjust frame rate are horizontal and vertical non display periods Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 10 S1D13705 Epson Research and Development Vancouver Design Center The following are the formulae for determining the frame rate of a panel The formula for a single passive or TFT panel is calculated as follows PCLK FrameRate DP ANDP x VDP VNDP for a dual passive panel the formula is FrameRate RELE 2x HDP HNDP x VNDP where PCLK Pixel clock in Hz HDP Horizontal Display Period in pixels HNDP Horizontal Non Display Period in pixels VDP Vertical Display Period in lines VNDP Vertical Non Display Period in lines In addition to varying the HNDP and VNDP times we can also select divider values which will reduce CLKi to one half one quarter up to one eight of the CLKi value The example below is a portion of a C routine to calculate HNDP an
24. 3 TMPR3912 22U and S1D13704 5 Interface 3 1 Hardware Connections 3 2 Memory Mapping and Aliasing 6 3 3 S1D13704 5 Configuration and Pin Mapping 4 CPU Module Description lt lt 4 1 Clock Signals AYA BUSCEK ecto gk ri id SS A A Eo eae ANZ CER ts Soi ec 2 Speech Sed BA oe ha He ee E 4 2 LCD Connectors 42 1 50 pin LCD Module Connector J3 o 42 2 Standard Epson LCD Comnector J4 ooo 4 3 LCD Controller 4 3 1 SID13704 vs SIDISTOS 200000 babe sesh ee ie E 4 3 2 LEDPWR Polarity om E a ees 43 3 S1D13704V75 Chip Select o o S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 Page 3 X00A G 004 02 Page 4 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 S1D13704 5 Configuration for Generic 2 Bus Interface o 11 Table 3 2 1D13704 5 Generic 2 Interface Pin Mapping e 11 List of Figures Figure 3 1 S1D13704 to TMPR3912 22U Interface o a 10 S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 6 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704 5 TMPR3912 22U CPU Module X0
25. EPSON PCI Bridge Card will appear in the list Click NEXT Windows will install the driver Click FINISH Windows will ask you to restart the system Windows will re detect the card and ask you to restart the system S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 Epson Research and Development Page 7 Vancouver Design Center All ISA Bus Evaluation Cards Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HARDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES and click NEXT Click Have Disk Specify the location of the driver files and click OK Click Next Click Finish Previous Versions of Windows 95 All PCI Bus Evaluation Cards 1 Ze Install the evaluation board in the computer and boot the computer Windows will detect the card Select DRIVER FROM DISK PROVIDED BY MANUFACTURER Click OK Specify a path to the location of the driver files Click OK Windows will find the S1D13XXX INF file Click OK Click OK and Windows will install the driver S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 8 Epson Research and Development Vancouver Design Center All ISA Bus Evaluation Cards X00A E 003 04 10 11 12 13 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD NEW HA
26. For example when building HELLOAPP EXE for the Intel 16 bit platform you need the HELLOAPP source files the 13705HAL library and its include files and some Standard C library functions which in this case would be supplied by the compiler as part of its run time library As this is a DOS EXE application you do not need to supply start up code that sets up the chip selects or interrupts etc What if you wanted to build the application for an SH 3 target one not running DOS Before you can build that application to load onto the target you need to build a C library for the target that contains enough of the Standard C functions like sprintf and strcpy to let you build the application Epson Research and Development supplies the LIBSE for this purpose but your compiler may come with one included You also need to build the 13705HAL library for the target This library is the graphics chip dependent portion of the code Finally you need to build the final application linked together with the libraries described earlier The following examples assume that you have a copy of the complete source code for the S1D13705 utilities including the nmake makefiles as well as a copy of the GNU Compiler v2 7 96q3a for Hitachi SH3 These are available on the World Wide Web at http www erd epson com Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 65 Vancouver Design Center 9 5 1 Bui
27. Page 18 Epson Research and Development Vancouver Design Center 5 4 S1D13705 Configuration The S1D13705 is configured at power up by latching the state of the CNF 3 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx The table below shows those configuration settings relevant to this specific interface Table 5 2 SIDI3705 Configuration Using the IT8368E S1D13705 Value hard wired on this pin is used to configure Configuration Pin 1 10 Vpp 0 Vss BS Generic 2 CNF3 CNF 2 0 Big Endian E configuration for connection using ITE IT8368E S1D13705 X27A G 012 02 Interfacing to the Philips MIPS PR31500 PR31 700 Processor Issue Date 01 02 13 Epson Research and Development Page 19 Vancouver Design Center 6 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1357CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13705 test utilities and Windows CE v2 0 display drivers are available from your sal
28. 0 0 Not Configured or 0 1 1 X reserved Not Configured or 0 Normal Operation X fo 0 Configured and 1 Hardware Power Save Mode 13 1 Software Power Save Mode Software Power Save Mode saves power by powering down the panel and stopping display refresh accesses to the display buffer Table 13 2 Software Power Save Mode Summary e Registers read write accessible e Memory read write accessible e Look Up Table registers not accessible LCD outputs are forced low 13 2 Hardware Power Save Mode Hardware Power Save Mode saves power by powering down the panel stopping accesses to the display buffer and registers and disabling the Host Bus Interface Table 13 3 Hardware Power Save Mode Summary Host Interface not accessible e Memory read write not accessible Look Up Table registers not accessible LCD outputs are forced low 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 83 Vancouver Design Center 13 3 Power Save Mode Function Summary Table 13 4 Power Save Mode Function Summary Hardware Software Normal Power Save Power Save IO Access Possible No Yes Yes Memory Access Possible No Yes Yes Look Up Table Registers Access Possible No No Yes Sequence Controller Running No No Yes Display Active No No Yes LCDPWR Inactive Inactive Acti
29. 2 Type the following command at the root of the Project source tree gddk_v1 00 direc tory services graphics tests bench nto x86 0 bench dlhardware devg S1D13705 nto x86 dll devg S1D13705 so mW H C F d0x0 0x0 Where W is the configured width of the display H is the configured height of the display C is the color depth in bpp i e 8 F is the configured frame rate This command starts the bench utility which will initialize the driver as the secondary display and exercise the drivers main functions If the display appears satisfactory restart QNX Photon and the restart will result in the S1D13705 display driver becoming the primary display device Comments e To restore the display driver to the default comment out changes made to the trap file graphics trapfile 1D13705 QNX Photon v2 0 Display Driver X27A E 005 01 Issue Date 01 09 10 EPSON S1D13XXX 32 Bit Windows Device Driver Installation Guide Document No X00A E 003 04 Copyright O 1999 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected u
30. Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the 1D13705 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update 1t is possible that contention may occur in accessing the S1D13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the 1D13705 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola Dragonball Family of Microprocesso
31. Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 13 EPSON 1D13704 5 Embedded Memory Color LCD Controller S5U13704 5 TMPR3912 22U CPU Module Document Number X00A G 004 02 Copyright O 1998 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON Research and Development Vancouver Design Center Table of Contents 1 INtTOdUCHION sa oaae a Sh eo Bet ik Ee es Bee ey ees Ble de S 1 1 General Description 2 1D13704 5 Bus Interface 0 0 00 ee ee ee 2 1 Bus Interface Modes 2 2 Generic 2 Interface Mode
32. Mapping for connection details Note When using a 3 3V host bus interface IO Vpp must be set to 3 3V by setting jumper JP1 to the 2 3 position Refer to Table 2 3 Jumper Settings on page 9 6 4 Decoding Logic All the required decode logic is provided through a PLD of type 22V 10 15 U7 socketed This PAL contains the following equations es Address gt hC0000 amp Address lt hDFFFF ADDR REFRESH ENAB Addressl gt hF00000 amp Addressl lt hF1FFFF amp ADDR amp REFRESH amp ENAB IMEMCS16 Addressl gt h0C0000 Addressl lt hODFFFF amp ADDR CS Addressl gt hF00000 Addressl lt hFIFFFF amp ADDR amp CS IWEO CS amp ADDR SMEMW CS amp ADDR MEMW RD CS amp ADDR SMEMR ICS amp ADDR MEMR Note ADDR Switch S1 5 see Table 2 1 Configuration DIP Switch Settings on page 8 6 5 Clock Input Support The input clock CLKI frequency can be up to SOMHz for the 1D13705 if the internal clock divide by 2 mode is set If the clock divider is not used the maximum CLKI frequency is 25MHz There is no minimum input clock frequency A 25 0MHz oscillator U2 socketed is provided as the input clock source However depending on the LCD resolution desired frame rate and power consumtion budget a lower frequency clock
33. Start Position Start Position Start Position Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 bits 5 0 FPFRAME Start Position These bits are used in TFT D TFD mode to specify the position of the FPFRAME pulse These bits specify the number of lines between the last line of display data FPDAT and the leading edge of FPFRAME This register is effective in TFT D TFD mode only REG 01h bit 7 1 This register is programmed as follows FPFRAMEposition lines REG 09h The contents of this register must be greater than zero and less than or equal to the Vertical Non Display Period Register i e 1 lt REG 09h lt REG OAh Bits 5 0 S1D13705 X27A A 001 10 Hardware Functional Specification Issue Date 02 02 01 Page 62 Epson Research and Development Vancouver Design Center REG OAh Vertical Non Display Period Address 1FFEAh Read Write Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Vertical Non Display n a Display Display Display Display Display Display Status Period Bit 5 Period Bit 4 Period Bit 3 Period Bit 2 Period Bit 1 Period Bit 0 bit 7 Vertical Non Display Status This bit 1 during the Vertical Non Display period bits 5 0 Vertical Non Display Period These bits specify the vertical non display period This register is programmed as follows VerticalNonDisplayPeriod lines REG OAh bits 5 0 Note This register should be set only once on powe
34. is specified otherwise the register is read XA Reads all registers L index datal data2 data3 Reads writes Look Up Table LUT values Writes data to the LUT index when data is specified otherwise the LUT index is read Data must consist of 3 bytes 1 red 1 green 1 blue and range in value from 0x00 to OxOF LA Reads all LUT values F W addrl addr2 data Fills bytes or words from address 1 to address 2 with data Data can be multiple values e g F 0 20 1 2 3 4 fills address 0 to 0x20 with a repeating pattern of 1 2 3 4 13705PLAY Diagnostic Utility Issue Date 01 07 04 Epson Research and Development Page 5 Vancouver Design Center R W addr count Reads count of bytes or words from the address specified by addr If count is not specified then 16 bytes words are read W W addr data Writes bytes or words of data to address specified by addr Data can be multiple values eg W 0 1 2 3 4 writes the byte values 123 4 starting at address 0 I Initializes the chip with user specified configuration M bpp Returns information about the current mode If bpp is specified then set the requested color depth P 0 1 2 Sets software power save mode 0 2 Power save mode 0 is normal operation H lines Halts after specified lines of display This feature halts the display during long read operations to prevent data from scrolling off the display Set 0 to disable Q Quit
35. signal is not used in the bus interface for Generic 1 mode However BS is used to configure the 1D13705 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Page 19 Vancouver Design Center 3 4 MC683EZ28 To S1D13705 Interface 3 4 1 Hardware Description The interface between the MC68328 and the 1D13705 can be implemented using the Generic 1 host bus interface of the S1D13705 The DTACK signal must be made available for the S1D13705 since it inserts a variable number of wait states depending upon CPU LCD synchronization and the LCD panel display mode WAIT must be inverted using an inverter enabled by CS to make it an active high signal and thus compatible with the MC68EZ328 architecture A single resistor is used to pull up WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68EZ328 to S1D13705 using the Generic 1 host bus interface For further information on the Generic 1 host bus interface and AC Timing refer to the 1D13705 Hardware Functional Specification document number X27A A 001 xx MC68EZ328 S1D13705 A 16 0 gt AB 16 0 D 15 0 DB 15 0 CSBO CS vad iE BS DTACK 4 o2 WAIT UWE WE1 IWE WEO OE gt RD WR gt RD CLKO BUSCLK System RESET
36. 1 0 ISA Bus Evaluation Board User Manual X27A G 005 03 Issue Date 01 02 13 EPSON 1D13705 Embedded Memory LCD Controller Windows CE 3 x Display Drivers Document Number X27A E 006 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Windows CE 3 x Display Drivers X27A E 006 01 Issue Date 01 05 25 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 3 x DISPLAY DRIVERS The Windows CE 3 x display driver is designed to support the S1D13705 Embedded Memory LCD Controller running the Microsoft Windows CE operating system version 3 0 The driver is capable of 4 and 8 bit per pixel landscape modes no rotation and 4 and 8 bit p
37. 2 mode However BS is used to configure the S1D13705 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to the Toshiba MIPS TMPR3912 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 004 02 Page 12 Epson Research and Development Vancouver Design Center 4 Direct Connection to the Toshiba TMPR3912 4 1 General Description In this example implementation the 1D13705 occupies the TMPR3912 PC Card slot 1 The S1D13705 is easily interfaced to the TMPR3912 with minimal additional logic The address bus of the TMPR3912 PC Card interface is multiplexed and must be demultiplexed using an advanced CMOS latch e g 74AHC373 The direct connection approach makes use of the S1D13705 in its Generic Interface 2 configuration The following diagram demonstrates a typical implementation of the interface S1D13705 3 3V TMPR3912 t__ IO Vpp CORE Vpp CARDIORD gt RD CARDIOWR gt WEO CARD1CSL CARD1CSH WE1 3 3V E BS 3 3V z RD WR m ENDIAN System RESET gt RESET y Latch E ALE PC GSH A 12 0 gt AB 16 13 gt AB 12 0 D 31 24 e gt DB 7 0 D 23 16 gt DB 15 8 VoD pull up CARD1WAIT 4 WAIT DCLKOUT See text CLKI 1 Glock divider 9f Oscillator BCLK Note When connecting the S1D13705 RESET pin the s
38. 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Santa Clara California Tel 800 366 9782 Fax 800 729 9288 http A www nec com Interfacing to the NEC VR4181A Microprocessor Issue Date 01 02 13 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Page 17 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13705 X27A G 013 02 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 EPSON S1D13705 Embedded Memory Color LCD Controller Interfacing to an 8 bit Processor Document Number X27A G 015 01 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson
39. Future S1D1370x products will support the HAL allowing OEMs the ability to upgrade to future chips with relative ease Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 8 Epson Research and Development Vancouver Design Center 2 Initialization Prior to doing anything else with the S1D13705 the controller must be initialized Initial ization is the process of setting up the control registers to a known state in order to generate proper display signals 2 1 Display Buffer Location Before we can perform the initialization we have to know where to find the S1D13705 display memory and control registers The S1D13705 contains 80 kilobytes of internal display memory External support logic must be employed to decode the starting address for this display memory in CPU address space On the S5U13705B00x PC platform evaluation boards the address is usually fixed at FOOOOOh Alternatively the address can be set to DOOOOh The control registers are located by adding 1FFEOh 128 Kb less 32 bytes to the base memory address Thus on the typical PC platform we access control register 0 at address F1FFEOh Control register 5 would be located at address FIFFES etc 2 2 Register Values This section describes the register settings and sequence of setting the registers In addition to these setting the Look Up Table must be programmed with appropriate colors Look Up Table setup is not covered here See Section 4
40. If your hardware implementation differs from the addresses used select the User Defined option and enter the correct addresses for Register address and Display buffer address The physical address of the start of register decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected The physical address of the start of display buffer decode space in hexadecimal This field is automatically set according to the Decode Address unless the User Defined decode address is selected When Epson S5U13705B00C Rev 2 Evaluation Board is selected the register and display buffer addresses are blanked because the evaluation board uses the PCI interface and the decode addresses are determined by the system BIOS during boot up If using the S1D13705 Evaluation Board on a PCI based platform both Windows and the S1ID13XXX device driver must be installed For further information on the S1D13XXX device driver see the SIDI13XXX Windows 32 bit Windows Device Driver Installation Guide document number XOOA E 003 xx 13705CFG Configuration Program Issue Date 02 03 11 Epson Research and Development Vancouver Design Center Preferences Tab 705 51D13705 Configuration Utility Color Depth E El Allematve Mode Page 9 The Preference tab contains settings pertaining to the initial display state During runtime th
41. Linux 6 1 kernel version 2 2 17 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13705 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D137053 archive to a temporary directory e g tmp When completed the files s1d13xxxfb c s1d13705 h Config in fbmem c fbcon cfb4 c and Makefile should be located in the temporary directory 3 Copy the console driver files to the build directory Copy the files tmp s1d13xxxfb c and tmp s1d13705 h to the directory usr src linux drivers video Copy the remaining source files tmp Config in tmp fbmem c tmp fbcon cfb4 c and tmp Makefile into the directory usr src linux drivers video replacing the files of the same name Linux Console Driver Issue Date 01 09 19 Epson Research and Development Page 5 Vancouver Design Center If your kernel version is not 2 2 17 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding files of the same names 4 Modify s1d13705 h The file s1d13705 h contains the register values required to set the screen resolution color depth bpp display type display rotation etc Before building the console driver refer t
42. RESET if REG 03h bits 1 0 00 11 LCDPWR Ie FPLINE FPSHIFT ACTIVE FPDAT FPFRAME tl t2 DRDY MA ais Figure 7 9 LCD Panel Power On Reset Timing Table 7 9 LCD Panel Power On Reset Timing Symbol Parameter Min Typ Max Units REG 03h to FPLINE FPFRAME FPSHIFT FPDAT DRDY active TFPFRAME ns 2 FPLINE FPFRAME FPSHIFT FPDAT DRDY active to 0 Eram LCDPWR Ames Note Where Tfpprrame is the period of FPFRAME and Tpcrx is the period of the pixel clock S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 37 Vancouver Design Center 7 3 2 Power Down Up Timing LCDPWR Override REG 03h bit 3 HW Power Save or Software Power Save REG O3h bits 1 0 11 00 11 00 11 t1 t2 Inactive Active Inactive 14 lt 15 gt 16 t7 FP Signals Active Active Rea t3 LCDPWR Figure 7 10 Power Down Up Timing Table 7 10 Power Down Up Timing Symbol Parameter Min Typ Max Units u HW Power Save active to FPLINE FPFRAME FPSHIFT FPDAT DRDY 1 Frama inactive LCDPWR Override 1 2 HW Power Save inactive to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 Fr me active LCDPWR Override 1 3 HW Power Save active to FPLINE FPFRAME FPSHIFT FPDAT DRDY 4 Fram inactive LCDPWR Override 0 amg
43. Read Only bit set to 0 its BSW Bus Data Width set to 1 for a 16 bit bus and the WS Wait states bit should be set to 111b to allow the S1D13705 to terminate bus cycles externally with DTACK Enable DTACK pin function with Register FFFFF433 Port G Select Register bit 0 Additional registers must be configured if the M68K 1 host bus interface is used LDS UDS and R W must be enabled by setting register FFFFFF443h bits 1 2 and 3 to zero to enable the internal 68000 pin functions Interfacing to the Motorola Dragonball Family of Microprocessors 1D13705 Issue Date 01 02 13 X27A G 007 04 Page 30 Epson Research and Development Vancouver Design Center 5 Software S1D13705 Test utilities and Windows CE display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13705CFG or by directly modifying the source The Windows CE display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13705 test utilities and Windows CE display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the Motorola Dragonball Family of Microprocessors X27A G 007 04 Issue Date 01 02 13 Epson Research and Development Page 31 Vancouver Design
44. S1D13705 The following instructions produce a bootable disk that automatically starts the UGL demo software These instructions assume that the Wind River Tornado platform is correctly installed Note For the example steps where the drive letter is given as x Substitute x with the drive letter that your development environment is on 1 Create a working directory and unzip the UGL display driver into it Using a command prompt or GUI interface create a new directory e g x 13705 Unzip the file 13705ugl zip to the newly created working directory The files will be unzipped to the directory x 13705 8bpp 2 Configure for the target execution model This example build creates a VxWorks image that fits onto and boots from a single floppy diskette In order for the VxWorks image to fit on the disk certain modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13705 8bpp File config h The new config h file removes networking compo nents and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the Tornado tool bar select Build gt Build Boot ROM Select pcPentium as the BSP and bootrom_uncmp as the image 4 Create a bootable disk in drive A From a command prompt
45. S1D13705 is aliased 512 times at 128K byte intervals over the 64M byte PC Card slot 1 memory space Note If aliasing is undesirable additional decoding circuitry must be added 4 3 S1D13705 Configuration The S1D13705 is configured at power up by latching the state of the CNF 3 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the 1D13705 Hardware Functional Specification document number X27A A 001 xx The table below shows those configuration settings relevant to the direct connection approach Table 4 1 SIDI3705 Configuration for Direct Connection S1D13705 Value hard wired on this pin is used to configure Configuration Pin 1 IO Von 0 Vss Generic 1 Big Endian CNF 2 0 configuration for Toshiba TMPR3912 host bus interface Interfacing to the Toshiba MIPS TMPR3912 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 004 02 Page 14 Epson Research and Development Vancouver Design Center 5 Using the ITE IT8368E PC Card Buffer If the system designer uses the ITE IT8368E PC Card and multiple function I O buffer the S1D13705 can be interfaced so that 1t shares a PC Card slot The S1D13705 is mapped to a rarely used 16M byte portion of the PC Card slot buffered by the IT8368E making the S1D13705 virtually transparent to PC Card devices that use the same slot 5 1 Hardware Description The ITE8368E has been specially design
46. Scratch bit 4 Scratch bit 3 Scratch bit 2 Scratch bit 1 Scratch bit 0 bits 7 0 Scratch Pad Register This register contains general use read write bits These bits have no effect on hardware REG 1Bh SwivelView Mode Register Address 1FFFBh Read Write SwivelView SwivelView SwivelView SwivelView Ma a reseed Mode Pixel Mode Pixel Mode Enable Mode Select Clock Select Clock Select Bit 1 Bit 0 bit 7 SwivelView Mode Enable When this bit 1 Swivel View Mode is enabled When this bit 0 Landscape Mode is enabled bit 6 SwivelView Mode Select Hardware Functional Specification When this bit 0 Default Swivel View Mode is selected When this bit 1 Alternate SwivelView Mode is selected See Section 12 Swivel View on page 77 for further information on Swivel View Mode The following table shows the selection of Swivel View Mode Issue Date 02 02 01 Table 8 7 Selection of Swivel View Mode SwivelView SwivelView Mode Enable Mode Select Mode REG 1Bh bit 7 REG 1Bh bit 6 0 X Landscape 1 0 Default SwivelView 4 1 Alternate SwivelView S1D13705 X27A A 001 10 Page 68 Epson Research and Development Vancouver Design Center bit 2 reserved reserved bits must be set to 0 bits 1 0 SwivelView Mode Pixel Clock Select Bits 1 0 These two bits select the Pixel Clock PCLK source in Swivel View Mode th
47. Vancouver Design Center Building a WindML v2 0 Display Driver S1D13705 X27A E 002 03 The following instructions produce a bootable disk that automatically starts the UGL demo program These instructions assume that Wind River s Tornado platform is already installed Note For the example steps where the drive letter is given as x Substitute x with the drive letter that your development environment is on 1 Create a working directory and unzip the WindML display driver into it From a command prompt or GUI interface create a new directory e g x113705 Unzip the file 13705windml zip to the newly created working directory The files will be unzipped to the directory x 13705 8bpp 2 Configure for the target execution model This example build creates a VxWorks image that fits onto and boots from a single floppy diskette In order for the VxWorks image to fit on the disk certain modifica tions are required Replace the file x Tornado target config pcPentium config h with the file x 13705 8bpp File config h The new config h file removes networking compo nents and configures the build image for booting from a floppy disk Note Rather than simply replacing the original config h file rename it so the file can be kept for reference purposes 3 Build a boot ROM image From the Tornado tool bar select Build gt Build Boot ROM Select pcPentium as the BSP and bootrom_uncmp as t
48. WE1 BHE CS External Decode External Decode BCLK BCLK BCLK BS connect to Vgg connect to lO Vpp RD WR RD1 connect to lO Vpp RD RDO RD WEO WEO WE WAIT WAIT WAIT RESET RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx Interfacing to the Philips MIPS PR31500 PR31700 Processor S1D13705 Issue Date 01 02 13 X27A G 012 02 Page 10 Epson Research and Development Vancouver Design Center 3 2 Generic 1 Interface Mode 1D13705 X27A G 012 02 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13705 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13705 host interface It is sepa rate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB 16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding t
49. Wind River UGL v1 2 Display Drivers The Wind River UGL v1 2 display drivers for the S1D13705 Embedded Memory LCD Controller are intended as reference source code for OEMs developing for Wind River s UGL v1 2 The drivers provide support for 8 bit per pixel color depth The source code is written for portability and contains functionality for most features of the S1D13705 Source code modification is required to provide a smaller more efficient driver for mass production The UGL display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13705CFG This design allows for easy customization of display type clocks addresses rotation etc by OEMs For further information on 13705CKG see the 13705CFG Configuration Program User Manual document number X27A B 001 xx This document and the source code for the UGL display drivers are updated as appropriate Please check the Epson Electronics America website at http www eea epson com or the Epson Research and Development website at http www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com Wind River UGL v1 2 Display Drivers 1D13705 Issue Date 01 02 13 X27A E 003 02 Page 4 Epson Research and Development Vancouver Design Center Building a UGL v1 2 Display Driver
50. mode Default for EPSON Display Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D13705 Width dword 140 Height dword FO Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 11 Delete all the files in the x wince release directory and delete x wince plat form cepc bif 12 Generate the proper building environment by double clicking on the sample project icon i e X86 DEMO7 13 Type BLDDEMO lt ENTER gt at the command prompt of the X86 DEMO7 window to generate a Windows CE image file NK BIN Build for CEPC X86 on Windows CE Platform Builder 2 1x using a Command Line Interface 1D13705 X27A E 001 03 Throughout this section 2 1x refers to either 2 11 or 2 12 as appropriate 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Install Platform Builder 2 1x by running SETUP EXE from compact disk 1 4 Follow the steps below to create a Build Epson for x86 shortcut which uses the current Minshell project icon shortcut on the Windows desktop a Right click on the Start menu on the taskbar b Click on the item Explore and Exploring Start Menu window will come up c Under x winnt profiles all users start menu programs microsoft windows ce platform builder x86 tools find
51. modulated image pattern is repeated every 1 hour when the frame rate is 72Hz When this bit 0 the modulated image pattern is never repeated Hardware Video Invert Enable In passive panel modes REG O1h bit 7 0 FPDAT11 is available as either GPIO4 or hardware video invert When this bit 1 Hardware Video Invert is enabled via the FPDAT11 pin When this bit 0 FPDAT11 operates as GPIO4 See Table 8 4 Inverse Video Mode Select Options below Note Video data is inverted after the Look Up Table Software Video Invert When this bit 1 Inverse Video Mode is selected When this bit 0 Standard Video Mode is selected See Table 8 4 Inverse Video Mode Select Options below Note Video data is inverted after the Look Up Table Table 8 4 Inverse Video Mode Select Options Hardware Video Ware Video Invert FPDAT11 Passive and Active Video Data Invert Enable Passive Panels Only Panels 0 0 x Normal 0 1 x Inverse 1 X 0 Normal 1 X 1 Inverse Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 59 Vancouver Design Center REG 03h Mode Register 2 Address 1FFE3h Read Write Hardware Software Software n a n a n a n a ei Power Save Power Save Power Save Enable Bit 1 Bit O bit 3 LCDPWR Override This bit is used to override the panel on off sequencing logic When this bit 0 LCDPWR and the panel
52. s on chip LCD controller The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Interfacing to the Motorola Dragonball Family of Microprocessors 1D13705 Issue Date 01 02 13 X27A G 007 04 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MC68328 2 1 The MC68328 System Bus The MC68328 is the first generation of Motorola s Dragonball microprocessors The MC68328 is an integrated controller for handheld products based upon the MC68EC000 microprocessor core It implements a 16 bit data bus and a 32 bit address bus The bus interface consists of all the standard MC68EC000 bus interface signals plus some new signals intended to simplify the task of interfacing to typical memory and peripheral devices The MC68EC00O0 bus control signals are well documented in Motorola s user manuals and will not be described here A brief summary of the new signals appears below Output Enable OE is asserted when a read cycle is in process it is intended to connect to the output enable control of a typical static RAM EPROM o
53. stride n bytes REG 1Eh and REG 1Fh REG 1Eh and REG 1Fh are reserved for factory 1D13705 testing and should not be written Any value written to these registers may result in damage to the S1D13705 and or any panel connected to the S1D13705 S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 69 Vancouver Design Center 9 Frame Rate Calculation The following formulae are used to calculate the display frame rate TFT D TFD and Passive Single Panel modes fPcLK FrameRate HDP HNDP x VDP VNDP Where fperk PCIk frequency Hz HDP Horizontal Display Period REG 04h bits 6 0 1 x 8 Pixels HNDP Horizontal Non Display Period REG 08h bits 4 0 4 x 8 Pixels VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines Passive Dual Panel mode fPcLK VDP FrameRate lt 2 x HDP HNDP x amp VNDP Where frerk PCIKk frequency Hz HDP Horizontal Display Period REG 04h bits 6 0 1 x 8 Pixels HNDP Horizontal Non Display Period REG 08h bits 4 0 4 x 8 Pixels VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 70 Epson Research an
54. t12 FPDATT 7 0 setup to Shift Pulse falling edge 1 Ts t13 FPDATT 7 0 hold to Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 timin t8min 9TS 3 t8min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 1 Ts 5 t min REG O8h bits 4 0 x 8 10 Ts Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 48 Epson Research and Development Vancouver Design Center 7 3 8 Dual Monochrome 8 Bit Panel Timing FPFRAME FPLINE DRDY MOD FPDAT 7 0 FPLINE DRDY MOD FPSHIFT FPDAT7 FPDAT6 FPDAT5 FPDAT4 FPDAT3 FPDAT2 FPDAT1 FPDATO VDP VNDP LINE 1 241 X LINE 2 242 X LINE 3 243 X LINE 4 244 LINE 239 479XLINE 240 480 Pi LINE 1 241 X LINE 2 242 X X le HDP lt HNDP gt po os Ata Xis x Y X 1 637 X ANNA X_X ON X VEDED ON QUE x ao a on a X A 241 1 X 241 5 X X SK Y X Yes 1 637 X 241 2 241 6 X X x Y X e41 638 X aa 241 7 Y eN X X e41 639 X A 241 4 241 8 X gt Y X 241 640 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 21 Dual Monochrom
55. t4 LCDPWR low to FPLINE FPFRAME FPSHIFT FPDAT DRDY inactive 127 Frame LCDPWR Override 0 5 HW Power Save inactive to FPLINE FRFRAME FPSHIFT FPDAT DRDY 0 Frame LCDPWR active LCDPWR Override 0 t6 LCDPWR Override active 1 to LCDPWR inactive 1 Frame t7 LCDPWR Override inactive 1 to LCDPWR active 1 Frame Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 38 Epson Research and Development Vancouver Design Center 7 3 3 Single Monochrome 4 Bit Panel Timing VDP VNDP FPFRAME Pp m FPLINE j ll I IL tl I j j I DRDY MOD y y FPDAT 7 4 LINE1 X LINE2 X LINES X LINE4 XLINE239XLINE240 LINE1 X LINE2 FPLINE il E DRDY MOD X 7 HDP HNDP gt ane Sri ia HU ne M FPDAT7 aXX yX AS X87 X FPDAT6 12 X16 X X y SUD ET X FPDAT5 13 X17 X E X Xaa FPDAT4 14 18 X A YX 1 320 Y Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 11 Single Monochrome 4 Bit Panel Timing VDP Vertical Display Period REG O6h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts S1D13705 H
56. virtual image size lt 80K bytes as it consumes less power than the Alternate SwivelView Mode For example the panel size is 320x240 and the display mode is 8 bit per pixel The virtual image size is 320x256 which can be contained within the 80K Byte display buffer Default Swivel View Mode also requires Memory Clock MCLK gt Pixel Clock PCLK The following figure shows how the programmer sees a 240x320 image and how the image is displayed The application image is written to the S1D13705 in the following sense A B C D The display is refreshed by the S1D13705 in the following sense B D A C physical memory start N a 299 gt address A Ta B E i m QO g pea A gt 8 ne display gt Q start oe q address Ss lt 9 o y y E z 320 240 image seen by programmer image refreshed by S1D13705 image in display buffer Figure 12 1 Relationship Between The Screen Image and the Image Refreshed by SIDI13705 in Default Mode Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Page 78 Epson Research and Development Vancouver Design Center 12 1 1 How to Set Up Default SwivelView Mode The following describes the register settings needed to set up Default Swivel View Mode for a 240x320x8 bpp image e Select Default SwivelView Mode REG 1Bh bit 7 1 and bit6 0 e The display refresh circuitry starts at pixel B therefore the
57. 00 00 05 AO 00 AO 06 AO AO 00 07 AO AO AO 08 00 00 00 09 00 00 FO OA 00 FO 00 0B 00 FO FO oC FO 00 00 0D FO 00 FO OE FO FO 00 OF FO FO FO 10 00 00 00 ae 00 00 00 FF 00 00 00 indicates unused entries Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 20 8 bpp color When the 1D13705 is configured for 8 bpp color mode the entire Look Up Table is used to display images Each of the LUT entries may be set to any of the 4096 possible colors Each byte in the display buffer represents one pixels The byte value is used directly as an Epson Research and Development Vancouver Design Center index into one of the 256 LUT entries A display memory byte with a value of 00h will display the color contained in the first Look Up Table entry while a display memory byte of FFh will display a color formed byte the two hundred and fifty sixth Look Up Table entry The following table depicts LUT values which approximate the VGA default 256 color palette Table 4 4 Suggested LUT Values to Simulate VGA Default 256 Color Palette Index R G B index R G B index R G B index R G B 00 00 00 00 40 FO 70 70 80 30 30 70 co 00 40 00 01 00 00 AO 41 FO 90 70 81 40 30 70 C1 00 40 10 02 00 AO 00 42 FO BO 70 82 50 30 70 C2 00 40 20 03 00 AO AO 43 FO DO 70 83 60 30 70 C3 00
58. 00 00 00 indicates unused entries Programming Notes and Examples Issue Date 02 01 22 1D13705 X27A G 002 03 Page 24 S1D13705 X27A G 002 03 4 bpp gray shade Epson Research and Development Vancouver Design Center When the S1D13705 is configured for 4 bpp gray shade mode the displayed colors are selected from the green values of the first sixteen entries of the Look Up Table Each of the sixteen entries can be set to any of the sixteen possible intensity levels Each byte in the display buffer contains two adjacent pixels If a nibble pattern is 0000 then the green intensity of LUT index 0 is displayed A nibble value of 0001 results in the green intensity in LUT index 1 being displayed The pattern continues to the nibble pattern of 1111 which results in the sixteenth intensity of Look Up Table being displayed The following table shows the example values for 4 bit per pixel display mode Table 4 7 Suggested LUT Values for 4 Bpp Gray Shade Index Red Green Blue 00 00 00 00 01 00 10 00 02 00 20 00 03 00 30 00 04 00 40 00 05 00 50 00 06 00 60 00 07 00 70 00 08 00 80 00 09 00 90 00 OA 00 AO 00 0B 00 BO 00 0C 00 CO 00 oD 00 DO 00 OE 00 E0 00 OF 00 FO 00 10 00 00 00 00 00 00 FF 00 00 00 indicates unused entries Programming Notes and Examples Issue Date 02 01 22 Epson Research a
59. 0000 00 0000 0000 1110 1111 1 239 1 240 lines 07 0000 0000 00 FPLINE start position only required for TFT configuration o8 00000000 oo Horizontal non display period Reg 08 4 8 Frame Rate Calculation 4 8 32 pixels 09 0000 0000 00 FPFRAME start position only required for TFT configuration 0A 0000 0011 03 Vertical non display period REG OA 3 lines Frame Rate Calculation 0B 0000 0000 00 MOD rate is only required by some monochrome panels 0C 0000 0000 00 OA TA Screen 1 Start Address set to 0 for initialization Split Screen on page 31 0D 0000 0000 00 0E 0000 0000 00 bre Ae Screen 2 Start Address set to 0 for initialization Split Screen on page 31 OF 0000 0000 00 10 0000 0000 00 Screen 1 Screen 2 Start Address MSB set to 0 11 0000 0000 00 Memory Address offset not virtual setup so set to 0 Virtual Display on page 25 12 1111 1111 FF Set the vertical size to the maximum value Split Screen on page 31 13 0000 0011 03 15 z 15 Leave the LUT alone for now poop rable heh gn 17 page 15 18 0000 0000 00 GPIO control and status registers set to 0 19 0000 0000 00 1A 0000 0000 00 Set the scratch pad bits to 0 1B 0000 0000 00 This is not portrait mode so set this register to 0 Introduction To Hardware 1C 0000 0000 00 Line Byte Count is only required for portrait mode Rotation on page 37
60. 01 22 Epson Research and Development Page 59 Vancouver Design Center int seReadDisplayDword DWORD Offset DWORD pDword Description Reads a dword from the display buffer at the specified offset and returns the value in pDword Parameters Offset offset from start of the display buffer to read from pDword pointer to a DWORD to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater than 80 kb int seWriteDisplayBytes DWORD Offset BYTE Value DWORD Count Description This routine writes one or more bytes to the display buffer at the offset specified by Offset If a count greater than one is specified all bytes will have the same value Parameters Offset offset from start of the display buffer to start writing at Value BYTE value to write Count number of bytes to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or the value of Addr plus Count is greater than 80 kb Note There are slight functionality differences between the S1D1370x and the S1D1350x HAL int seWriteDisplayWords DWORD Offset WORD Value DWORD Count Description Writes one or more WORDS to the display buffer at the offset specified by Addr If a count greater than one is specified all WORDS will have the same value Parameters Offset offset from start of the display buffer Value WORD value to write Count num
61. 01 22 X27A G 002 03 Page 32 5 3 1 Registers Epson Research and Development Vancouver Design Center Split screen operation is performed primarily by manipulating three register sets Screen 1 Start Address and Screen 2 Start Address determine from where in display memory the first and second images will be taken from The Vertical Size registers determine how many lines Screen 1 will use The following is a description of the registers used to do split screen REG 12 Screen 1 Vertical Size LSB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 13 Screen 1 Vertical Size MSB n a n a n a n a n a n a Bit 9 Bit 8 S1D13705 X27A G 002 03 Screen 1 Vertical Size These two registers form a ten bit value which determines the size of screen 1 When the vertical size is equal to or greater than the physical number of lines being displayed there is no visible effect on the display When the vertical size value is less than the number of physical display lines operation is like this 1 From the beginning of a frame to the number of lines indicated by vertical size the dis play data will come from the memory area pointed to by the Screen 1 Display Start Address 2 After vertical size lines have been displayed the system will begin displaying data from the memory area pointed to by Screen 2 Display Start Address On thing that must be pointed out here is that Screen 1 memo
62. 1 to enable portrait mode 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 41 Vancouver Design Center The portrait mode select bit selects between the Default Mode and the Alternate Mode Setting this bit to 0 selects the default portrait mode while setting this bit to 1 enables the alternate portrait mode Portrait Mode Memory Clock Select is another power saving measure which can be enabled if the final MCLK value is less than or equal to 25 MHz Memory Clock Select results in the 1D13705 temporarily increasing the memory clock circuitry on CPU access and resuming the slower speed when the access is complete This results in better performance while using the least power In portrait display mode the CLKI input clock is routed to the portrait section of the S1D13705 as CLK From the CLK signal the MCLK value can be determined from table 8 8 of the Hardware Functional Specification document number X27A A 001 xx If MCLK is determined to be less than or equal to 25 MHz then Portrait Mode Memory Clock Select may be enabled Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 42 7 5 Limitations S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center The only limitation to using portrait mode on the S1D13705 is that split screen operation is not supported A comparison
63. 1 ABO AO DB 15 0 D 15 0 WE1 WE1 CS External Decode BCLK BCLK BS connect to Vss RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13705 Issue Date 01 02 13 X27A G 01 1 02 Page 12 Epson Research and Development Vancouver Design Center 3 2 Generic 1 Interface Mode 1D13705 X27A G 011 02 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13705 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13705 host interface It is sepa rate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB 16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order
64. 1 Vertical Size LSB Register 13h Screen 1 Vertical Size MSB KR Set to maximum i e 0x3FF This register is used AIK for split screen operation Normally it is set to a maximum value ad SET_REG 0x12 OxFF SET_REG 0x13 0x03 Look Up Table registers The LUT is programmed at the end of the initialization sequence Ef Register 18h GPIO Configuration set to 0 x O configures the GPIO pins for input power on default ay SET_REG 0x18 0x00 Register 19h GPIO Status set to O TE This step has no real purpose It sets the GPIO EK pins low should GPIO be set as outputs Kf SET_REG 0x19 0x00 Register 1Ah Scratch Pad set to 0 ER Use this register to store whatever state data your aes system may require El SET_REG 0x1A 0x00 Register 1Bh Portrait Mode set to 0 disable portrait mode EN SET_REG 0x1B 0x00 jx Register 1Ch Line Byte Count set to 0 used only by portrait mode SET_REG 0x0C 0x00 Look Up Table In this example we only set the first sixteen LUT entries In typical use all 256 entries would be setup E Register 15h Look Up Table Address ae Set to 0 to start RGB sequencing at the first LUT entry Er SET_REG 0x15 0x00 Programming Notes and Examples X27A G 002 03 I
65. 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13705 host interface It is sepa rate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB 16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the 1D13705 that indicates the host CPU must wait unti
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68. 2 Configuration Settings Signal Low High CNFO CNF2 CNF1 See Host Bus Selection table below CNF3 Little Endian See Host Bus Selection table below Po f5 configuration for MPC821 host bus interface Table 4 3 Host Bus Selection CNF2 CNF1 CNFO BSH Host Bus Interface A configuration for MPC821 host bus interface S1D13705 X27A G 010 02 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 13 Epson Research and Development Page 19 Vancouver Design Center 4 4 MPC821 Chip Select Configuration The DRAM on the MPC821 ADS board extends from address 0 through 3F FFFFh so the S1D13705 is addressed starting at 40 0000h The S1D13705 uses a 128K byte segment of memory starting at this address with the first 80K bytes used for the display buffer and the upper 32 bytes of this memory block used for the 1D13705 internal registers Chip select 4 is used to control the S1D13705 The following options are selected in the base address register BR4 BA 0 16 0000 0000 0100 0000 0 set starting address of S1D13705 to 40 0000h AT 0 2 0 ignore address type bits PS 0 1 1 0 memory port size is 16 bits PARE 0 disable parity checking WP 0 disable write protect MS 0 1 0 0 select General Purpose Chip Select module to control this chip select V 1 set valid bit to enable chip select The following options we
69. 22 2 2 12 4 2 S1D13705 Hardware Configuration 2 2 ee ee eee ee 13 4 3 Register Memory Mapping 2 13 5 Software na e mara GS ie Se Se ee a a ee ee 14 ReierenCe S istics eo ale a ae ea a el ea ead aes da 15 61 DOCUMENTS sie eaat se oa is ee A ay os kar aa ee Re a eae US 6 2 Document Sources o 15 Technical S pport lt a a A Sk a id eed 16 7 1 EPSON LCD Controllers 1D13705 0 2 2 2 2 2 2 2 16 12 PC Catd Standard tesi e e Ge Gee ae eed ac ote 16 Interfacing to the PC Card Bus 1D13705 Issue Date 01 02 13 X27A G 009 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the PC Card Bus X27A G 009 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 0 0 00000 eee 10 Table 4 1 Summary of Power On Reset Options oaoa 00 0000 0022 13 Table 4 2 Host Bus Interface Selection 2 0 2 ee 13 List of Figures Figure 2 1s PCCard Read Cycles su deni Bag ee he ae A A Re 9 Figure 2 2 PC Card Write Cycle 2 ee 9 Figure 4 1 Typical Implementation of PC Card to S1D13705 Interface 12 Interfacing to the PC Card Bus 1D13705 Issue Date 01 02 13 X27A G 009 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfaci
70. 38min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 4 Ts 5 t7min REG O8h bits 4 0 x 8 13 Ts Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 42 Epson Research and Development Vancouver Design Center 7 3 5 Single Color 4 Bit Panel Timing VDP VNDP FPFRAME gt FPLINE fl l l L l I l DRDY MOD X S X FPDAT 7 4 LINE1 X LINE2 X LINES X LINE4 XLINE239XLINE240 LINE1 X LINE2 Pa FPLINE p DRDY MOD X W HDP HNDP 4 r EESPIEr fe Ela LI L Ll US AAA c all Cine FPDAT7 o 1 R1 X 1 G2 X 1 B3 Y Y e 1 B319 X FPDAT6 no 1 G1X 1 82 X 1 R4 X X oo YX 1 R320 X FPDAT5 o ABI 1 R3 X 1 G4 Wo X S Y 1 G820 xX FPDAT4 24 1 R2 X_1 G3X_1 B4 XxX Z x 1 B320 0 X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 320x240 panel Figure 7 15 Single Color 4 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01
71. 4 0 GPIO 4 0 Pin IO Configuration These bits determine the direction of the GPIO 4 0 pins When the GPIOn Pin IO Configuration bit 0 the corresponding GPIOn pin is configured as an input The input can be read at the GPIOn Status Control Register bit See REG 19h GPIO Status Control Register When the GPIOn Pin IO Configuration bit 1 the corresponding GPIOn pin is configured as an output The output can be controlled by writing the GPIOn Status Control Register bit Note These bits have no effect when the GPIOn pin is configured for a specific function i e as FPDAT 11 8 for TFT D TFD operation When configured as IO all unused pins must be tied to IO Vpp 1D13705 X27A A 001 10 Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 67 Vancouver Design Center REG 19h GPIO Status Control Register Address 1FFF9h Read Write nia ma GPIO4 Pin IO GPIO3 Pin IO GPIO2 Pin IO GPIO1 Pin IO GPIOO Pin lO Status Status Status Status Status bits 4 0 GPIO 4 0 Status When the GPIOn pin is configured as an input the corresponding GPIO Status bit is used to read the pin input See REG 18h above When the GPIOn pin is configured as an output the corresponding GPIO Status bit is used to control the pin output REG 1 Ah Scratch Pad Register Address 1FFFAh Read Write Scratch bit 7 Scratch bit 6 Scratch bit 5
72. 4 4 Suggested LUT Values to Simulate VGA Default 256 Color Palette Continued Index R G B Index R G B index R G B index R G B 1C BO BO BO 5C FO FO BO 9C 70 50 70 DC 20 40 40 1D CO CO co 5D EO FO BO 9D 70 50 60 DD 20 30 40 1E EO EO EO 5E DO FO BO 9E 70 50 60 DE 20 30 40 1F FO FO FO 5F CO FO BO 9F 70 50 50 DF 20 20 40 20 00 00 FO 60 BO FO BO AO 70 50 50 E0 20 20 40 21 40 00 FO 61 BO FO co A1 70 50 50 E1 30 20 40 22 70 00 FO 62 BO FO DO A2 70 60 50 E2 30 20 40 23 BO 00 FO 63 BO FO E0 A3 70 60 50 E3 30 20 40 24 FO 00 FO 64 BO FO FO A4 70 70 50 E4 40 20 40 25 FO 00 BO 65 BO E0 FO A5 60 70 50 E5 40 20 30 26 FO 00 70 66 BO DO FO A6 60 70 50 E6 40 20 30 27 FO 00 40 67 BO co FO A7 50 70 50 E7 40 20 30 28 FO 00 00 68 00 00 70 A8 50 70 50 E8 40 20 20 29 FO 40 00 69 10 00 70 A9 50 70 50 E9 40 30 20 2A FO 70 00 6A 30 00 70 AA 50 70 60 EA 40 30 20 2B FO BO 00 6B 50 00 70 AB 50 70 60 EB 40 30 20 2C FO FO 00 6C 70 00 70 AC 50 70 70 EC 40 40 20 2D BO FO 00 6D 70 00 50 AD 50 60 70 ED 30 40 20 2E 70 FO 00 6E 70 00 30 AE 50 60 70 EE 30 40 20 2F 40 FO 00 6F 70 00 10 AF 50 50 70 EF 30 40 20 30 00 FO 00 70 70 00 00 BO 00 00 40 FO 20 40 20 31 00 FO 40 71 70 10 00 B1 10 00 40 F1 20 40 30 32 00 FO 70 72 70 30 00 B2 20 00 40 F2 20 40 30 33 00 FO BO 73 70 50 00 B3 30 00 40 F3 20 40 30 34 00 FO FO 74 70 70 00 B4 40 00 40 F4 20 40 40 35 00 BO FO 75 50 70 00 B5 40 00 30 F5 20 30 40 36 00 70 FO 76 30 70 00 B6 40 00 20 F6 20 30 40 37 00 40 FO 77 10 70 00 B7 40 00 1
73. 7 1 Relationship Between the Default Mode Screen Image and the Image Refreshed by S1D13705 From the programmers perspective the memory is laid out as shown on the left The programmer accesses memory exactly as for a panel of with the dimensions of 240x320 setup to have a 256 pixel horizontal stride The programmer sees memory addresses increasing from A gt B and from B gt C From a hardware perspective the S1D13705 always refreshes the LCD panel in the order B gt D and down to do A gt C S1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Vancouver Design Center Page 39 7 3 Alternate Portrait Mode Alternate portrait mode does not impose the power of two line width To rotated the image on 240 line panel requires a portrait stride of 240 pixels Alternate portrait mode is capable of scrolling by one line at a time in response to changes to the Start Address Registers However to achieve the same frame rate requires a 2 x faster input clock therefore using more power The following figure depicts the ways to envision memory layouts for the S1D137053 in alternate portrait mode This example also uses a 320x240 panel Notice that in alternate portrait mode the stride may be as little as 240 pixels physical memory start address Ps A 480 A B portrait m a window display 35 o start E S address a 3 lt x O C D 480 320 b image seen by programm
74. 7 3 10 9 12 Bit TFT D TFD Panel Timing Epson Research and Development Vancouver Design Center Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center List of Tables Table 5 1 Summary of Power On Reset Options o Table 5 2 Host Bus Interface Pin Mapping o e Table 5 3 LCD Interface Pin Mapping e Table 6 1 Absolute Maximum Ratings o e e e Table 6 2 Recommended Operating Conditions for Core VDD 3 3V 10 Table 6 3 Input Specifications o o e e Table 6 4 Output Specifications o e e Table 7 1 SH 4 Timing Table 7 2 SH 3 Bus Timing Table 7 3 MC68K 1 Bus Timing MC68000 02 Table 7 4 MC68K 2 Timing MC68030 o o o o Table 7 5 Generic 1 Timing e Table 7 6 Generic 2 TiMidgB e Table 7 7 Clock Input Requirements for CLKI o Table 7 8 Clock Input Requirements for BCLK o o Table 7 9 LCD Panel Power On Reset TiMiN8 o e Table 7 10 Power Down Up TiMing e Table 7 11 Single Monochrome 4 Bit Panel A C Timin8 Table 7 12 Single Monochrome 8 Bit Panel A C Timin8 Table 7 13 Single Color 4 Bit Panel A C TiMin8 Table 7 14 Single
75. A Seiten A ote a cake age Hh tied Neck Hie ytd te ed 19 Configure Multiple 24 42 wo a Rae et ae aw Ba Et o eae ae es 20 EXPORTA LA ae a Bienes fora hn Bah ere Chee Fa oat he 21 Enable Tooltips 00 dit bij ie ee ok ai See di he dd 22 ERD on the Web 2 vei ti irk Se ite Be we oar ba he ar a ess 22 About T3705CEG ee iu cede ss ie he ee he E EE ee ee ee ee a 22 Comments 2 5 a AS a he os ee he nd te Bee ee ete Be Sn Se te a Se 2 13705CFG Configuration Program 1D13705 Issue Date 02 03 11 X27A B 001 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705CFG Configuration Program X27A B 001 03 Issue Date 02 03 11 Epson Research and Development Page 5 Vancouver Design Center 13705CFG 13705CFG is an interactive Windows program that calculates register values for a user defined S1D13705 configuration The configuration information can be used to directly alter the operating characteristics of the S1D13705 utilities or any program built with the Hardware Abstraction Layer HAL library Alternatively the configuration information can be saved in a variety of text file formats for use in other applications Note This program is a Windows desktop application suitable for configuring software for a given implementation of an Epson LCD controller However it is not a display driver for any Windows desktop operating system Epson does not provide display drivers for any of the Windows
76. America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 http Awww epson electronics de Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 http www epson com tw Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 http www epson com sg Interfacing to an 8 bit Processor Issue Date 01 12 20 S1D13705 X27A G 015 01 Page 16 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to an 8 bit Processor X27A G 015 01 Issue Date 01 12 20
77. B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13705 WinCE Drivers Save the new configuration as MODEO H in the wince300 platform cepc drivers display replacing the original configuration file Edit the file PLATFORM REG to match the screen resolution color depth and rota tion information in MODE H PLATFORM REG is located in x wince300 plat form cepc files For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp and a Swivel View mode of 0 landscape Default for EPSON Display Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x 1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D 13705 Width dword 140 Height dword FO Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 9 Vancouver Design Center 10 Delete all the files in the x wince300 release directory and delete the file x wince300 platform cepc bif 11 Type BLDDEMO lt ENTER gt at the command prompt to generate a Windows CE image file The file generated will be x wince300 release nk bin Windows CE 3 x Display Drivers 1D13705 Issue Date 01 05 25 X27A E 006 01 Page 10 Epson Research and
78. CLKI 2 X27A A 001 xx Note S1D13705 X27A B 001 03 13705CFG Configuration Program Issue Date 02 03 11 Epson Research and Development Vancouver Design Center Page 11 The S1D13705 uses one clock input known as CLKI The pixel clock PCLK and the memory clock MCLK are both derived from CLKI CLKI CLKI 2 PCLK Source Divide Timing MCLK Source Divide Timing 13705CFG Configuration Program Issue Date 02 03 11 This setting determines the frequency of CLKI CLKI is the source for both PCLK and MCLK The CLKI frequency must be selected from the drop down list or by entering the desired frequency in MHz The actual CLKI frequency used for configuration is displayed in blue in the Actual section Selecting this box divides the input clock CLKL in half for internal S1D13705 operations These settings confirm the signal source and input clock divisor for the pixel clock PCLK The PCLK source is CLKI The divide ratio for the clock source signal is 1 1 This field shows the actual PCLK used by the configu ration process These settings confirm the signal source and input clock divisor for the memory clock MCLK The MCLK source is CLKI The divide ratio for the clock source signal is 1 1 This field shows the actual MCLK frequency used by the configuration process 1D13705 X27A B 001 03 Page 12 Epson Research and Development Vancouver Design Center Panel Tab Format 2 Panel
79. CSB1 gt CS Ly BS Vcc 1k DTACK ii WAIT UDS gt WE1 LDS ABO R W gt RD WR Vcc RD Vcc WEO CLKO gt BUSCLK System RESET RESET Note ue Ea When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states S1D13705 X27A G 007 04 Figure 4 1 Typical Implementation of MC68VZ328 to SIDI3705 Interface MC68K 1 Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Vancouver Design Center Using The Generic 1 Host Bus Interface Page 27 The DTACK signal must be made available for the S1D13705 since it inserts a variable number of wait states depending upon CPU LCD synchronization and the LCD panel display mode WAIT must be inverted using an inverter enabled by CS to make it an active high signal and thus compatible with the MC68VZ328 architecture A single resistor is used to pull up the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68VZ328 to S1D13705 using the Generic 1 host bus interface For further information on the Generic 1 host bus interface and AC Timing refer to the 1D13705 Hardware Functional Specification document numb
80. Center 6 References 6 1 Documents Motorola Inc MC68328 DragonBall Integrated Microprocessor User s Manual Motorola Publication no MC68328UM available on the Internet at http www mot com SPS WIRELESS products MC68328 html Motorola Inc MC68EZ328 DragonBall EZ Integrated Processor User s Manual Motorola Publication no MC68EZ328UMl available on the Internet at http www mot com SPS WIRELESS products MC68EZ328 html Motorola Inc MC68VZ328 DragonBall VZ Integrated Processor User s Manual Motorola Publication no MC683VZ28UM available on the Internet at http www mot com SPS WIRELESS products MC68VZ328 html Epson Research and Development Inc S1D13705 Hardware Functional Specification Document Number X27A A 001 xx Epson Research and Development Inc S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X27A G 005 xx Epson Research and Development Inc 7D13705 Programming Notes and Examples Document Number X27A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola Website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola Dragonball Family of Microprocessors 1D13705 Issue Date 01 02 13 X27A G 007 04 Page 32 7 Technical Support 7 1 EPSON LCD Controllers S1D13705 Japan Seiko Epson Corporation Electronic Devices Marketing Divisi
81. Clear the display Do this by writing 81920 bytes ty seWriteDisplayBytes 0 0 EIGHTY_K Setup portrait mode seSetHWRotate PORTRAIT Draw a solid blue 100x100 rectangle in center of the display This starting co ordinates assuming a 320x240 display is 320 100 2 240 100 2 110 70 ay seDrawRect 110 70 210 170 2 TRUE Done Ry exit 0 Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 68 Epson Research and Development Vancouver Design Center 10 2 Sample code without using the S1D13705 HAL API This second sample demonstrates exactly the same sequence as the first however the HAL is not used all manipulation is done by directly accessing the registers SAMPLE2 C Sample code demonstrating a direct access of the S1D13705 Created 1998 Vancouver Design Centre Copyright c 1998 1999 Epson Research and Development Inc All Rights Reserved The sample code using direct S1D13705 access will configure for the following 320x240 Single Color 4 bit SIN 8 bpp color depth 70 Hz Frame Rate 6 MHz CLKi kk Notes 1 This code is written to be compiled for use under 32 bit pi Windows In order to function the vxd file S1D13X0X VXD must FA be in the WINDOWS SYSTEM directory 2 Register setup is done with discreet writes rather than being tab
82. D5 UD1 D1 D5 D5 UD1 GO G1 FPDAT6 D2 D6 UD2 D2 D6 D6 UD2 B2 B3 FPDAT7 D3 D7 UD3 D3 D7 D7 UD3 B1 B2 FPDAT8 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 BO B1 FPDAT9 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 RO FPDAT10 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GO GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 Hardware Hardware Hardware Hardware Hardware Hardware Hardware PRDATII Video Video Video Video Video Video Video SSA B9 Invert Invert Invert Invert Invert Invert Invert Note 1 Unused GPIO pins must be connected to IO Vpp 2 Hardware Video Invert is enabled on FPDAT11 by REG 02h bit 1 Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 24 Epson Research and Development Vancouver Design Center 6 D C Characteristics Table 6 1 Absolute Maximum Ratings Symbol Parameter Rating Units Core Vpp Supply Voltage Vss 0 3 to 4 0 V IO Vpp Supply Voltage Core Vpp to 7 0 V Vin Input Voltage Vss 0 3 to IO Vpp 0 5 V Vout Output Voltage Vss 0 3 to lO Vpp 0 5 V TsTG Storage Temperature 65 to 150 C TsoL Solder Temperature Time 260 for 10 sec max at lead C Table 6 2 Recommended Operating Conditions for Core VDD 3 3V 10 Symbol Parameter Condition Min Typ Max Units Core Vpp Supply Voltage Vss 0 V 2 7 3 0 3 3 3 6 V IO Vop Supply Voltag
83. Data Width Panel Color A ELNE EPERAME Mask FPSHIFT Mono te Single Panel Type MN Frame Repeat Tie El FPSHIFT E Dual Non display Periods asas E Color Pixel Clock Predefined Panels The S1D13705 supports many panel types This tab allows configuration of most panel settings such as panel dimensions type and timings Panel Type Selects between passive STN and active TFT D TED panel types The Epson D TFD panels are supported only in TFT compatible mode Several options may change or become unavailable when the STN TFT setting is switched Therefore confirm all settings on this tab after the Panel Type is changed 1D13705 13705CFG Configuration Program X27A B 001 03 Issue Date 02 03 11 Epson Research and Development Vancouver Design Center Format 2 Frame Repeat Data Width Panel Color Mask FPSHIFT Dual Panel Polarity FPLINE Polarity FPFRAME Polarity 13705CFG Configuration Program Issue Date 02 03 11 Page 13 Selects color STN panel format 2 This option is specif ically for configuring 8 bit color STN panels See the S1D13705 Hardware Functional Specification document number X27A A 001 xx for description of format 1 format 2 data formats Most new panels use the format 2 data format Selects Frame Repeat feature for use with EL panels See the S1D13705 Hardware Functional Specification document number X27A A 001 xx for description of Frame Repeat Selects the panel data wi
84. Device Driver Installation Guide document number XOOA E 003 XX ERROR An IOCTL error occurred This message indicates an error at the IO control layer occurred The usual cause for this is an incorrect hardware configuration ERROR The HAL returned an unknown error This message should never be displayed it indicates that 13705SOLT is unable to determine the cause of an error returned from the HAL Not enough memory for www x hhh x bpp This message is displayed if there is insufficient display memory to contain two complete images with a width of www pixels a height of hhh pixels and a color depth of bpp bit per pixel In this case the mode is skipped and the next display mode is attempted 13705SPLT Display Utility 1D13705 Issue Date 01 02 12 X27A B 003 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705SPLT Display Utility X27A B 003 02 Issue Date 01 02 12 EPSON 1D13705 Embedded Memory LCD Controller 13705VIRT Display Utility Document No X27A B 004 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current Th
85. Epson Research and Development Vancouver Design Center 7 3 6 Single Color 8 Bit Panel Timing Format 1 r VDP ne VNDP FPFRAME E C FPLINE l f j f fl fl j fl Nl FPDAT 7 0 LINE1 LINE2 X LINES LINE4 X XLINE479XLINE480 XA LINE X LINE2 X a FPLINE l FPSHIFT o ASA A E EES HDP HNDP pa gt lt gt FPSHIFT 2 RA MA E IS FPDAT7 Mm R1 X 1 G1 Y 1 G6 X 1 B6 X1 B11 X 1R12 X1 R630 X FPDAT6 a XK 181 YX 1 22 YX 1 87 X 1 67 X 1 G12X 1 B124 Y Y 1 B638 g YX FPDAT5 a 1 42 X 1 82 X 1 B7 X 1 R8 X1 R13 1 13 Y X 1 663 X FPDAT4 o R3 X 1 63 1 68 X 1 B8 X 1 B13X TRIE Y1 R638 Y FPDAT3 a B3 Y 1 R4 Y 1 P9 X 1 69 X1 G14X 1B14 X X8 X FPDAT2 z 64 Y 1 4 Y 1B9 X T RI0XT RI5XT GI5 X1 G639 X FPDAT1 o R5 X 1 5 Y 1 G10X 18101815 X TRI6 1 R640 Y FPDATO o 85 X 1 R6 X 1 R11X 1 G11X1 G16X 1B16 X Bo E X Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 17 Single Color 8 Bit Panel Timing Format 1 VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period R
86. Figure 7 19 Single Color 8 Bit Panel Timing Format 2 VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Horizontal Non Display Period REG 08h 4 x 8Ts 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 47 Vancouver Design Center ae tl Sync Timing ie Frame Pulse p t4 a t3 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 82 ice t7 t14 t11 410 gt gt Shift Pulse t12 t13 FPDAT 7 0 X Figure 7 20 Single Color 8 Bit Panel A C Timing Format 2 Table 7 15 Single Color 8 Bit Panel A C Timing Format 2 Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 2 Ts t10 Shift Pulse pulse width low 1 Ts t11 Shift Pulse pulse width high 1 Ts
87. For the following examples we base our calculations on a 4 bit per pixel image displayed on a 256w x 64h panel We have set up a virtual size of 320w x 240h Width is greater than height so we are in landscape display mode Refer to Section 2 Initialization on page 8 and Section 5 1 Virtual Display on page 25 for assistance with these settings These examples are shown using a C like syntax Example 3 Panning Right and Left To pan to the right increase the start address value by one To pan to the left decrease the start address value Keep in mind that with the exception of 8 bit per pixel portrait display mode the display will jump by more than one pixel as a result of changing the start address registers Panning to the right StartWord GetStartAddress StartWord SetStartAddress StartWord Panning to the left StartWord GetStartAddress StartWord if StartWord lt 0 StartWord 0 SetStartAddress StartWord The routine GetStartAddress is one which will read the start address registers and return the start address as a long value It would be written similar to long GetStartAddress return REG 10 1 65536 REG OD 256 REG OC The routine SetStartAddress break up its long integer argument into three register values and store the values void SetStartAddress long SA REG OC SA amp OXFF REG 0D SA gt gt 8 amp OxFF Reg 10
88. Kong Tel 2585 4600 Fax 2827 4346 7 2 Toshiba MIPS TMPR3912 Processor http www toshiba com taec nonflash indexproducts html 7 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com Interfacing to the Toshiba MIPS TMPR3912 Microprocessor Issue Date 01 02 13 Page 19 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13705 X27A G 004 02 Page 20 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 EPSON 1D13705 Embedded Memory LCD Controller 1D13705 Power Consumption Document Number X27A G 006 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or
89. NEC VR4102 VR4111 Microprocessor Issue Date 01 02 13 Page 3 S1D13705 X27A G 008 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4102 VR4111 Microprocessor X27A G 008 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping 0 2 00 0 00002 eee 12 Table 4 1 Summary of Power On Reset Options ooa e e 15 Table 4 2 Host Bus Selection 0 ag dl a a ee 15 List of Figures Figure 2 1 NEC VR4102 VR4111 Read Write Cycles o o o 11 Figure 4 1 Typical Implementation of VR4102 VR4111 to S1D13705 Interface 14 Interfacing to the NEC VR4102 VR4111 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 008 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4102 VR4111 Microprocessor X27A G 008 02 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to interface the S1D13705 Embedded Memory LCD Controller and the NEC VR4102 VR4111 Microprocessor uPD30102 The NEC VR4102 VR4111 Microprocessor is specifically designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive d
90. On Reset Options e 26 Table 4 3 Host Bus Interface Selection o e 26 List of Figures Figure 2 1 Typical Implementation of MC68328 to S1D13705 Interface MC68K 1 12 Figure 2 2 Typical Implementation of MC68328 to S1D137053 Interface Generic 1 13 Figure 3 1 Typical Implementation of MC68EZ328 to S1D13705 Interface Generic 1 18 Figure 4 1 Typical Implementation of MC68VZ328 to S1D13705 Interface MC68K 1 24 Figure 4 2 Typical Implementation of MC68VZ328 to S1D13705 Interface Generic 1 25 Interfacing to the Motorola Dragonball Family of Microprocessors 1D13705 Issue Date 01 02 13 X27A G 007 04 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Motorola Dragonball Family of Microprocessors X27A G 007 04 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to interface the S1D13705 Embedded Memory LCD Controller and the Motorola Dragonball family of micropro cessors Each Dragonball microprocessor the MC68328 the MC68EZ328 and the MC68VZ328 will be described in their own sections By implementing an embedded display refresh buffer the S1D13705 can reduce system power consumption improve image quality and increase system performance as compared to the Dragonball
91. Open Workspace gt Existing gt Browse and select the file x 13705 8bpp 13705 wsp 8 Add support for single line comments The WindML v2 0 display driver source code uses single line comment notation rather than the ANSI conventional comments P To add support for single line comments follow these steps a In the Tornado Workspace Views window click on the Builds tab b Expand the 8bpp Builds view by clicking on the next to it The ex panded view will contain the item default Right click on default and select Properties A Properties window will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that contains g mpen tium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details 9 Compile the VxWorks image Select the Builds tab in the Tornado Workspace Views window Right click on 8bpp files and select Dependencies Click on OK to regenerate project file dependencies for All Project files Right click on Sbpp files and select ReBuild All vxWorks to build VxWorks 10 Copy the VxWorks file to the diskette From a command prompt or through the Windows interface copy the file x 13705 8bpp default vxWorks to the bootable disk created in step 4 11 Start t
92. Program 1D13705 Issue Date 02 03 11 X27A B 001 03 Page 18 Epson Research and Development Vancouver Design Center Note Manual changes to the registers may have unpredictable results if incorrect values are entered 13705CFG Menus Open S1D13705 X27A B 001 03 The following sections describe each of the options in the File and Help menus From the Menu Bar select File then Open to display the Open File Dialog Box Look in sw yl El Ea ex 13705bmp exe 13705cfg exe 13705play exe 13705show exe 13705splt exe 13705virt exe File name Files of type All Configurable Files exe s9 idp elf lvb p Y Cancel h The Open option allows 13705CFG to open files containing HAL configuration infor mation When 13705CFG opens a file it scans the file for an identification string and if found reads the configuration information This may be used to quickly arrive at a starting point for register configuration The only requirement is that the file being opened must contain a valid S1D13705 HAL library information block 13705CFG supports a variety of executable file formats Select the file type s 13705CFG should display in the Files of Type drop down list and then select the filename from the list and click on the Open button Note 13705CFG is designed to work with utilities programmed using a given version of the HAL If the configuration structure contained in the executable fil
93. Research and Development Page 3 Vancouver Design Center Table of Contents T Introductions a 514 era ias A AAA ada a 7 2 Interfacing to the NEC VR4181A 8 2 1 The NEC VR4181A System Bus 2 2 8 DIZE COVEVIEW sid eos dd Bed abo E Bop aca ta o kode ans Boe be 8 2 1 2 LCD Memory Access Signals 2 aa ee 9 3 1D13705 Host Bus Interface 2 0c pe 1 10 3 1 Host Bus PinConnection 1 2 ee ee LO 3 2 Generic 2 Interface Mode 2 0 2 22 2 11 4 VR4181A to S1D13705 Interface 2 2 ee es 12 4 1 Hardware Description o G ioan etatas mn yad ee 1 4 2 S1D13705 Hardware Configuration a a a a a a a a eee eee ee 13 4 3 NEC VR4181A Configuration a a a a a eo 14 5 DONWAare q a eee RA EA ARS a A E ees 15 References ao a a daa ls aa didas de da 16 GL DOCUMENS ua a ee e a a a A a A ha te EG 6 2 DocumentSources aoia a E i a a a a a 16 Technical S pport 00000 ios a E we a ele a a Se ees 17 7 1 Epson LCD Controllers S1D13705 a a a a a ee ee 17 7 2 NEC Electronics Ce cm e E ae a A aa ss A Interfacing to the NEC VR4181A Microprocessor 1D13705 Issue Date 01 02 13 X27A G 013 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design
94. S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 4 1 Figure 5 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 Figure 7 6 Figure 7 7 Figure 7 8 Figure 7 9 Figure 7 10 Figure 7 11 Figure 7 12 Figure 7 13 Figure 7 14 Figure 7 15 Figure 7 16 Figure 7 17 Figure 7 18 Figure 7 19 Figure 7 20 Figure 7 21 Figure 7 22 Figure 7 23 Figure 7 24 Figure 7 25 Figure 7 26 Figure 8 1 Figure 10 1 Figure 11 1 Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 7 List of Figures Typical System Diagram SH 4 Bus 2 o o e e 12 Typical System Diagram SH 3 Bus 2 o o e e ee 12 Typical System Diagram M68K 1 BUS o e 13 Typical System Diagram M68K 2 BUS o e e 13 Typical System Diagram Generic 1 Bus o o e 14 Typical System Diagram Generic 2 Bus e g ISA BUS o 14 System Block Diagram Showing Data Paths o o 15 Pinout Diagram ciclo oc a Oe eS Pe Se eae eee SS 17 SHA MIOS o aes AR eases ate doe haan fe eee ea tee Goes ine ae eG 26 SH 3 Bus Timing x ot e a a A eh Bok dl a ao Be ad a 28 MC68K 1 Bus Timing MC68000 0 20002 002022 2 30 MC68K 2
95. SH 4 MC68K 1 MC68K 2 Generic 1 Generic 2 AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 31 16 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO CLK CLK BCLK BCLK BS BS BS AS AS connect to Vgg connect to lO Vpp RD WR RD WR RD WR R W R W RD1 connect to lO Vpp RD RD RD connect to lO Vpp SIZ1 RDO RD WEO WE0 WE0 connect to IO Vpp SIZO WE0 WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 23 Vancouver Design Center 5 5 LCD Interface Pin Mapping Table 5 3 LCD Interface Pin Mapping Monochrome Passive Panel Color Passive Panel Color TFT D TFD S1D13705 3 4 8 bit 8 bit Pin Name ae nas 8 bit Dual al Single Single 8 bit Dual 9 bit 12 bit g g g Format 1 Format 2 FPFRAME FPFRAME FPLINE FPLINE FPSHIFT FPSHIFT DRDY MOD MOD MOD MOD FPSHIFT2 MOD MOD DRDY FPDATO driven 0 DO LDO driven 0 DO DO LDO R2 R3 FPDAT1 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2 FPDAT2 driven 0 D2 LD2 driven 0 D2 D2 LD2 RO R1 FPDAT3 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3 FPDAT4 DO D4 UDO DO D4 D4 UDO G1 G2 FPDAT5 D1
96. Screen 1 Start Address register must be programmed with the address of pixel B i e REG 10h REG ODh REG OCh AddressOfPixelB AddressOfPixelA ByteOffset 240pixels x Sver L 8bpb AddressOfPixelA AddressOfPixelA EFh Where bpp is bits per pixel and bpb is bits per byte e The Line Byte Count Register for Swivel View Mode must be set to the virtual image width in bytes i e 230 me 256 00h see REG 1Ch for explanation REG 1Ch 2 8bpb 8bpp 1 Where bpb is bits per byte and bpp is bits per pixel e Panning is achieved by changing the Screen 1 Start Address register e Increment the register by 1 to pan horizontally by one byte e g one pixel in 8 bpp mode e Increment the register by twice the effective value of the Line Byte Count register to pan vertically by two lines e g add 200h to pan by two lines in the example above Note Vertical panning by a single line is not supported in Default Swivel View Mode 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 79 12 2 Alternate SwivelView Mode Alternate Swivel View Mode may be used when the virtual image size of Default Swivel View Mode cannot be contained in the 80K byte integrated frame buffer For example the panel size is 480x320 and the display mode is 4 bit per pixel The minimum virtual image size for Default Swivel
97. TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 12 EPSON Research and Development Vancouver Design Center 4 CPU Module Description 4 1 Clock Signals 4 1 1 BUSCLK 4 1 2 CLKI This section will describe the various parts of the CPU module that pertain to the S1D13704 5 LCD Controller Because the bus clock for the S1D13704 5 does not need to be synchronous with the bus interface control signals a lot of flexibility is available in the choice for BUSCLK In this CPU module BUSCLK is a divided by two version of the SDRAM clock signal DCLKOUT Since DCLKOUT equals 73 728MHz BUSCLK 36 864MHz The pixel clock for the S1D13704 5 CLKI is also asynchronous with respect to the interface control signals This clock is selected based upon panel frame rates power vs performance budget and maximum input frequencies The maximum CLKI input is 25MHz if the internal CLKI 2 isn t used and if it is used the maximum input is 50MHz On the CPU module CLKI s default input is a divided by four version of DCLKOUT which gives a CLKI 18 432MHZ This frequency gives good performance for 320x240 resolution panels for both portrait and landscape modes If power saving is desired the CLKI can be reduced by using the internal CLKI 2 and the various PCLK and MCLK dividers for portrait mode A socket for an external oscillator is also provided if a different frequency is required This option is selected by positioning jumper J
98. Ts 5 t7min REG 08h bits 4 0 x 8 11 Ts Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 40 Epson Research and Development Vancouver Design Center 7 3 4 Single Monochrome 8 Bit Panel Timing VDP VNDP FPFRAME FPLINE l fl l l l f DRDY MOD ae X FPDAT 7 0 XLINE1 XLINE2 X LINES X LINE4 X XLINE479XLINE480 LINE1 LINE2 7 FPLINE l DRDY MOD X k HDP HNDP gt gt FPSHIFT e e e e EIA fi FPDAT7 o 1X19 xX XX 1638 FPDAT6 Ss 2 1 10 X X X X 1 634 X FPDAT5 o 3 X 11X X a X X 1 635 X FPDAT4 4X 2X X X_ EA X Xie KX FPDAT3 o 5 X 113 X Y ei aX X X 1 637 FPDAT2 a 6X 114 X X Y X y 1 638 Y FPDAT1 o 7 Y 1 15 X ES X Y X_1 639 X FPDATO o 8 X 1 16 X X X X 1 640 A Y Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 13 Single Monochrome 8 Bit Panel Timing VDP Vertical Display Period REG 06h bits 1 0 REG O5h bits 7 0 1 Lines VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period REG 04h bits 6 0 1 x 8Ts HNDP Hori
99. U10 RD 0412 Xentek RD 0412 positive PS 33 1 U11 EPNOO1 Xentek EPNOO1 negative PS S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 S1D13705 X27A G 005 03 Epson Research and Development Page 20 Vancouver Design Center 8 Schematic Diagrams P r pag L 6661 p0 Menuer ABPuoA ed ot noy a J8quinN jueun9og ezis diud WOOSSOZEL p1eog uo neag OSH SNG WS1 DO008S0ZELNSS ou juawidojanag yoseesay vosd3 lerolano lt 1 aNadsns S yaa T v00350 101S YIOVIH YJOVIH GAO amp YM CH ON3ASNS ferolano gt LLIWdd4 lt Te OlaNO oe EN VN zr Y TANS ETA ObiWdds lt 6lvdd4 lt 81v0d34 lt z Olivad4 lt IZ 0l1Y0dd3 Y 9IVdds IE Fa SIvddJ3 ZE Y tlvdds_ve 2Ivdd3_S va LIvddW_9 oOlvddt Ze Agua lt 4LdIHSd4 ANMd4 AWVY4d4 lt YMdd91 lt _ f EJNO ZINO TINO eo oleo ONO ASL su 14 XSL o XSL o ASL su vu ee cu tay pA A aanoi 0Old9 JNO Z4N9 14NO OJNO vOIdD LLIVOd4 OIdD 0L 1WOdW ZOldD61Wdd4 101dD 81W0Od3 Z1WOd3 0 1WOdW Agua 1W1HSdW4 ANMd4 AWVH4d4 YMdd01 agro gaol anol ddAayOo ddgAaYyOo GGA3ZYHOO ddgAay Oo NaLSSL HLIVM W9 108 890 13838
100. Vpp when unused See Table 5 3 LCD Interface Pin Mapping on page 23 for summary FPDAT11 23 CN3 Input This pin has multiple functions Panel Data bit 11 for TFT D TFD panels General Purpose Input Output pin GPIO4 e Inverse Video select pin This pin should be connected to lO Vpp when unused See Table 5 3 LCD Interface Pin Mapping on page 23 for summary FPFRAME 39 CN3 Frame Pulse S1D13705 X27A A 001 10 Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 21 3 RESET so Pin Name Type Pin Cell State Description FPLINE O 38 CN3 0 Line Pulse FPSHIFT O 28 CN3 0 Shift Clock LCDPWR O 43 CO1 0 Active high LCD Power Control This pin has multiple functions TFT D TFD Display Enable DRDY DRDY o 42 CN3 0 LCD Backpiane Bias MOD Second Shift Clock FPSHIFT2 See Table 5 3 LCD Interface Pin Mapping on page 23 for summary 5 2 3 Clock Input Pin Name Type Pin Driver Description CLKI l 51 C Input Clock 5 2 4 Miscellaneous RESET EE Pin Name Type Pin Cell State Description These inputs are used to configure the S1D13705 see Table CNF 3 0 46 47 C As set by 5 1 Summary of Power On Reset Options on page 22 48 49 hardware Must be connected dire
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102. a 62 9 5 Porting LIBSE to a new target platform eR Be A a 0d 9 5 1 Building the LIBSE library for SH3 target ee REA A 65 9 5 2 Building the HAL library for the target example o 65 10 Sample Code i se iria a a a a A be 66 10 1 Sample code using the S1D13705 HAL API 2 2 66 10 2 Sample code without using the S1D13705 HAL API 68 10 3 Header Files me ua al a o Be A a ar pte A iy a er ee Ae dd S1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Vancouver Design Center Table 2 1 Table 4 1 Table 4 2 Table 4 3 Table 4 4 Table 4 5 Table 4 6 Table 4 7 Table 5 1 Table 7 1 Table 9 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 5 1 Figure 5 2 Figure 7 1 Figure 7 2 List of Tables 1D13705 Initialization Sequence o o e e Recommended LUT Values for 1 Bpp Color Mode Example LUT Values for 2 Bpp Color Mode Suggested LUT Values to Simulate VGA Default 16 Color Palette Suggested LUT Values to Simulate VGA Default 256 Color Palette Recommended LUT Values for 1 Bpp Gray Shade Suggested Values for 2 Bpp Gray Shade o Suggested LUT Values for 4 Bpp Gray Shade Number of Pixels Panned Using Start Address o Default and Alternate Portrait Mode Compa
103. about the Drivers Development Kit contact QNX directly 2 Once the ddk package is installed copy the directory tree usr src gddk_v1 0 into the Project directory 3 Change directory to Project gddk_1 0 devg 4 Unpack the display driver files using the commands gunzip S1D13705 tar gz tar xvf S1D13705 tar This unpacks the files into the directory Project gddk_1 0 devg S1D13705 Configure the Driver The file s1d13705_8 h contains register values required to set the screen resolution color depth bpp display type etc The s1d13705 h file included with the drivers may not contain applicable values and must be regenerated The configuration program 13705CFG can be used to build new s1d13705_8 h files Note S1d13705 h should be created using the configuration utility 13705CFG For more in formation on 13705CFG see the 13705CFG Configuration Program User Manual document number X27A B 001 xx available at www erd epson com Build the Driver The first time the driver is built the following command ensures that all drivers and required libraries are built At the root of the Project source tree type make Note To build drivers for X86 NTO type OSLIST nto CPULIST x86 make Further builds do not require all libraries to be re built To build only the 1D13705 display driver change to the directory gddk_1 0 devg S1D13705 and type make QNX Photon v2 0 Display Driver Issue Date 01 09 10 Epson Research and Development P
104. debugging support register initialization values and memory allocation Each of these issues is discussed in the following sections Compile Switches There are several switches specific to the S1D13705 display driver which affect the display driver The switches are added or removed from the compile options in the file SOURCES WINCEVER This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable WINCEOSVER is not defined then WINCEVER will default 2 11 The S1D display driver may test against this option to support different WinCE version specific features EnablePreferVvmem This option enables the use of off screen video memory When this option is enabled WinCE can optimize some BLT operations by using off screen video memory to store images You may need to disable this option for systems with limited off screen memory EpsonMessages This debugging option enables the display of EPSON specific debug messages These debug message are sent to the serial debugging port This option should be disabled unless you are debugging the display driver as they will significantly impact the performance of the display driver DEBUG_MONITOR This option enables the use of the debug monitor The debug monitor can be invoked when the display driver is first loaded and can be used to view registers and perform a few debugging tasks The debug monitor is still under development a
105. desktop operating systems 1D13705 Supported Evaluation Platforms 13705CFG runs on PC system running Windows 9x ME XP NT 2000 and can modify Win32 exe files 13705CFG Configuration Program 1D13705 Issue Date 02 03 11 X27A B 001 03 Page 6 Installation Usage S1D13705 X27A B 001 03 Epson Research and Development Vancouver Design Center Create a directory for 13705cfg exe and the S1D13705 utilities Copy the files 13705cfg exe and panels def to that directory Panels def contains configuration infor mation for a number of panels and must reside in the same directory as 13705cfg exe To start 13705CFG from the Windows desktop double click on the My Computer icon and run the program 13705cfg exe from the installed directory To start 13705CFG from a Windows command prompt change to the directory 13705cfg exe was installed to and type the command 13705cfg The basic procedure for using 13705CFG is 1 2 Start 13705CFG as described above Open an existing file to serve as a starting reference point this step is optional Modify the configuration For specific information on editing the configuration see 13705CFG Configuration Tabs on page 7 Save the new configuration The configuration information can be saved in two ways as an ASCII text file or by modifying an executable image on disk Several ASCII text file formats are supported Most are formatted C header files used to build display drivers or
106. document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 3 Vancouver Design Center Table of Contents AL introduction y ansa DA AA O BEAR CA vw de 9 Vel ES COPS se acl a as a AEs BS Be ae ea ee wt ae ated r 1 2 Overview Description een A es Se ar ea Ay he ar ee A a he ee SD 2 POGUES i ised GM a ee Se A Be Sai Ew Glee Re ask ce ie Se AAA 10 2 1 Integrated Frame Buffer 2 2 ee eee 10 2 2 CPU Interfaces o sok aig ae es a a A ee ot et Ge LO 2430 Display Supports cauto fo esc tah Ge Po ea ed ae edo Buh ped ak ae amp go ae LO 2 4 Display Modes o s aoc aoa A woa ek eee Ae ek Bae eg dee 23 ClOCK SoOurees eee ok e a ee ee a A 2 6 Miscellaneous lt i 2 aid Wok Bet ah e oa E OP ae a eR a eM 2 7 Package 4 sos kouenn AI AAA Be oo we ae AL Typical System Implementation Diagrams 0 2 00 000 eee 12 Functional Block Diagram 2 2 ee 15 4 1 Functional Block Descriptions 2 1 ee eee ee ee 15 4 1 1 Host Interface imc e Be ee RP ae Ee a ee eed e 15 4 1 2 Memory Controller isco phone gee nl o
107. enabled k k ey include lt conio h gt include lt stdio h gt include lt stdlib h gt include lt string h gt include hal h Structures constants and prototypes include appcfg h HAL configuration information as si void main void int Chipld Initialize the HAL The call to seRegisterDevice actually prepares the HAL library for use The S1D13705 is not accessed except to read the revision code register ET if ERR_OK seRegisterDevice amp HalInfo printf AnERROR Could not register S1D13705 device exit 1 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 67 Vancouver Design Center Get the product code to verify this is an S1D13705 xf seGetId amp ChiplIid if ID_S1D13705_Rev1l Chipld printf nERROR Did not detect an S1D13705 exit 1 Initialize the S1D13705 This step programs the registers with values taken from the HalInfo struct in appcfg h if ERR_OK seSetInit printf nERROR Could not initialize device exit 1 The default initialization cleared the display Draw a 100x100 red color 1 rectangle in the upper left corner 0 0 of the display seDrawRect 0 0 100 100 1 TRUE jx Pause here EL getch
108. failed to initialize the S1D13705 Failed to open BMP file 13705BMP was unable to open the BMP file specified on the command line 2 is not a valid bitmap file While performing validity checks it was determined that the file is either not a valid BMP file or is of an unsupported format ERROR Unable to set a suitable display mode 13705BMP was unable to set a display mode to view the image with ERROR Currently unable to process images greater than 8 bpp 13705BMP can decode images of 8BPP or less color depth Try reducing the color depth of your image ERROR Image larger than display memory size The amount of memory required by this image is more than the amount of memory available to the S1D13705 Try choosing a smaller image ERROR Unable to allocate enough memory to decode the image In order to decode a BMP image 13705BMP needs to allocate some additional system memory This message is seen if the call to allocate additional memory fails 13705BMP Demonstration Program Issue Date 01 02 12 EPSON 1D13705 Embedded Memory LCD Controller 13705PWR Power Save Utility Document No X27A B 007 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson R
109. host CPU is reading data from the 1D13704 5 RD must be generated by external decode hard ware based upon the control outputs from the host CPU WAIT is a signal which is output from the S1D13704 5 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13704 5 may occur asynchronously to the display update it is possible that contention may occur in accessing the 13704 5 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the 1D13704 5 for Generic 2 mode and must be tied high connected to IOVDD 3 3V RD WR must also be tied high S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 10 EPSON Research and Development 3 TMPR3912 22U and S1D13704 5 Interface 3 1 Hardware Connections Vancouver Design Center The S1D13704 5 occupies the TMPR3912 22U s PC Card slot 1 Therefore this slot cannot be used for other devices on the main board The Generic 2 bus mode of the S1D13704 5 is used to interface to this PC Card slot 1 The S1D13704 5 is interfaced to the TMPR3912 2
110. how to access the timers was not always available however we do know frame rate and can use that for timing calculations The S1D13705 registers must be initialized for this function to work correctly On the PC platform this is simply a call to the C timing functions and is therefore independent of the register settings MilliSeconds time to delay in seconds ERR_OK operation completed with no problems ERR_FAILED returned on non PC platforms when the S1D13705 registers have not bee initialized int seGetLastUsableByte long plLastByte Description Parameters Return Value This functions returns a pointer as a long integer to the last byte of usable display memory The returned value never changes for the 1D13705 plLastByte pointer to a long integer to receive the offset to the last byte of display memory ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 55 Vancouver Design Center int seSetHighPerformance BOOL OnOff Description This function call enables or disable the high performance bit of the S1D13705 When high performance is enabled then MCIk equals PCIk for all video display resolutions In the high performance state CPU to video memory performance is improved at the cost of higher power consumption When high performance is disabled then MCIKk ranges from PCIKk 1 at 8 bit per pixel to PCIK 8 at 1 bit per pixel W
111. is socketed so that it can be interchanged between the S1D13704 and the S1D13705 These controllers are very similar with the main differences being the amount of embedded display memory and the lookup table architecture LUT The S1D13704 has 40K bytes of display memory and the S1D13705 has 80K bytes The Toshiba TMPR3912 22U processor supports two PC Card PCMCIA slots on the TX RISC Reference Platform The S1D13704 or S1D13705 LCD controller uses the PC Card slot 1 to interface to the TMPR3912 22U therefore this slot is unavailable for use on the TX RISC Reference Platform S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 8 EPSON Research and Development Vancouver Design Center 2 S1D13704 5 Bus Interface This section is summary of the bus interface modes available on the S1D13704 and S1D13705 LCDCs and offers some detail on the Generic 2 bus mode used to implement the interface to the TMPR3912 22U 2 1 Bus Interface Modes The 1D13704 5 implements a general purpose 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families Bus interface mode selections are made during reset by sampling the state of the configu ration pins CNF 2 0 and the BS line Table 5 1 in the S1D13704 or S1D13705 Hardware Functional Specification details the values needed for the configuration pins and BS to select the desired
112. is two bus clocks Figure 2 1 Power PC Memory Read Cycle illustrates a typical memory read cycle on the Power PC system bus sw Tl Le eel TS TA A 0 31 XK RDWR XX AS TSIZ 0 1 AT O 3 x Dro 31 XXMAXKAXMAXMAMKXMAXMAXMAX XXX Sampled when TA low Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 1 Power PC Memory Read Cycle Interfacing to the Motorola MPC821 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 010 02 Page 10 Epson Research and Development Vancouver Design Center Figure 2 2 Power PC Memory Write Cycle illustrates a typical memory write cycle on the Power PC system bus Us ll ae al fe e lA EA TS TA AJO 31 X X TSIZ 0 1 AT O 3 A x pfo 31 0000004 Valid Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 Power PC Memory Write Cycle If an error occurs TEA Transfer Error Acknowledge is asserted and the bus cycle is aborted For example a peripheral device may assert TEA if a parity error is detected or the MPC821 bus controller may assert TEA if no peripheral device responds at the addressed memory location within a bus time out period For 32 bit transfers all data lines D 0 31 are used and the two low order address lines A30 and A31 are ignored For 16 bit transfers data
113. landscape panel modes allows two different images to be simultaneously displayed Virtual display support displays images larger than the panel size through the use of panning Maximum operating clock CLK frequency of 25MHz Operating clock CLK is derived from CLKI input CLK CLKI or CLK CLKI 2 Pixel Clock PCLK and Memory Clock MCLK are derived from CLK 2 6 Miscellaneous 2 7 Package Hardware Software Video Invert Software Power Save mode Hardware Power Save mode LCD power down sequencing 5 General Purpose Input Output pins are available e GPIOO is available if Hardware Power Save is not required e GPIO 4 1 are available if upper LCD data pins FPDAT 11 8 are not required for TFT D TFD support or hardware inverse video Core operates from 2 7 volts to 3 6 volts IO Operates from the core voltage up to 5 5 volts 80 pin QFP14 package Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 12 3 Typical System Implementation Epson Research and Development Vancouver Design Center Diagrams Oscillator x SH 4 3 BUS CSnit p CSH A 16 0 gt AB 16 0 DHS 0 gt DB 15 0 FPDAT 7 0 p 7 0 L pl FPSHIFT WE gt WE1 A eee BSE S1D13705 FPFRAME __ FPFRAME cai PENRI PEDRE FPLI
114. lines DO through D15 are used and address line A30 is ignored For 8 bit transfers data lines DO through D7 are used and all address lines A 0 31 are used Note This assumes that the Power PC core is operating in big endian mode typically the case for embedded systems 2 2 2 Burst Cycles 1D13705 X27A G 010 02 Burst memory cycles are used to fill on chip cache memory and to carry out certain on chip DMA operations They are very similar to normal bus cycles with the following exceptions e Always 32 bit e Always attempt to transfer four 32 bit words sequentially e Always address longword aligned memory i e A30 and A31 are always 0 0 Do not increment address bits A28 and A29 between successive transfers the addressed device must increment these address bits internally Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 13 Epson Research and Development Page 11 Vancouver Design Center If a peripheral is not capable of supporting burst cycles it can assert Burst Inhibit BI simultaneously with TA and the processor will revert to normal bus cycles for the remaining data transfers Burst cycles are mainly intended to facilitate cache line fills from program or data memory They are normally not used for transfers to from IO peripheral devices such as the S1D13705 therefore the interfaces described in this document do not attempt to support burst cycles However the example interfaces include circu
115. may be required 1D13705 X27A G 005 03 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 Epson Research and Development Page 17 Vancouver Design Center 6 6 LCD Panel Voltage Setting The S5U13705B00C board supports both 3 3V and 5V LCD panels through the LCD connector J5 The voltage level is selected by setting jumper J4 to the appropriate position Refer to Table 2 3 Jumper Settings on page 9 for setting this jumper Although not necessary for signal buffering buffers have been implemented in the board design to provide flexibility in handling 3 and 5 volt panels 6 7 Monochrome LCD Panel Support The S1D13705 directly supports 4 and 8 bit dual and single monochrome passive LCD panels All necessary signals are provided on the 40 pin ribbon cable header J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for specific connection information 6 8 Color Passive LCD Panel Support The S1D13705 directly supports 4 and 8 bit dual and single color passive LCD panels All the necessary signals are provided on the 40 pin ribbon cable header J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for specific connection information 6 9 Color TFT D TFD LCD Panel Su
116. no effect in landscape display modes The Intel 32 bit version of 13705SHOW is designed to work under either Windows 9x or Windows NT To install the 32 bit Windows device driver S1D13X0X vxd see the S1D13X0X 32 Bit Windows Device Driver Installation Guide document number XO0A E 003 xx The 16 bit version of the program runs under DOS with no DOS extenders The lack of a DOS extender means that the 16 bit program can only be used on a hardware platform where the S1D13705 is addressed below 1MB Program Messages ERROR Did not find a 13705 device The HAL was unable to read the revision code register on the S1D 13705 Ensure that the S1D13705 hardware is installed and that the hardware platform has been configured correctly Also check that the display memory address has been configured correctly ERROR Unable to locate load S1D13XXX VXD 13705PLAY was unable to load a required driver The file S1D13XXX VXD should be located in x WINDOWS SYSTEM or in xNWINNTAS Y STEM If the file is not there install it as described in the S1D13XXX 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 XX ERROR An IOCTL error occurred This message indicates an error at the IO control layer occurred The usual cause for this is an incorrect hardware configuration ERROR The HAL returned an unknown error This message should never be displayed it indicates that 13705SHOW is unable to determine the cause of an error return
117. note 3 t9 Frame Pulse pulse width low 2t6 t10 horizontal display period note 4 t11 Line Pulse setup to Shift Pulse falling edge 0 5 Ts H2 Frame Pulse falling edge to Line Pulse falling 16 18Ts edge phase difference t13 DRDY to Shift Pulse falling edge setup time 0 5 Ts t14 DRDY pulse width note 5 t15 DRDY falling edge to Line Pulse falling edge note 6 t16 DRDY hold from Shift Pulse falling edge 0 5 Ts t17 Line Pulse Falling edge to DRDY active note 7 250 1 Ts pixel clock period 2 t6min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 3 t8 min REG O6h bits 1 0 REG O5h bits 7 0 1 REG OAh bits 6 0 Lines 4 t10min REG 04h bits 6 0 1 x 8 Ts 5 ti4min REG O4h bits 6 0 1 x 8 Ts 6 ti5min REG O7h bits 4 0 x 8 16 Ts 7 17min REG 08h bits 4 0 REG O7 x 8 16 Ts 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 55 Vancouver Design Center 8 Registers 8 1 Register Mapping The S1D13705 registers are located in the upper 32 bytes of the 128K byte S1D13705 address range The registers are accessible when CS 0 and AB 16 0 are in the range 1FFEOh through 1 FFFFh 8 2 Register Descriptions Unless specified otherwise all register bits are reset to 0 during power up All bits marked n a should be programmed 0 REG 00h Revisi
118. occurs ae pMem p13705 for tmp 0 tmp lt MEM_SIZE tmp pMem 0 pMem y We will use the default portrait mode scheme so we have to adjust the ROTATED width to be a power of 2 NOTE current height will become the rotated width Es tmp 1 Height gt 1 lt lt tmp while tmp Height 1 lt lt tmp OffsetBytes Height BitsPerPixel 8 aX Sets 1 Line Byte Count to size of the ROTATED width i e current height 2 Start Address to the offset of the width of the ROTATED display ial in portrait mode the start address registers point to bytes 7 SET_REG 0x1C BYTE OffsetBytes OffsetBytes SET_REG 0x0C LOBYT SET_REG 0x0D HIBYT Set Portrait mode OffsetBytes OffsetBytes 150 A ra Use the non X2 default scheme so we don t have to re calc the frame rate MCLK will be lt 25 MHz so we can leave auto switch enabled SET_REG 0x1B 0x80 Draw a solid blue 100x100 rectangle centered on the display Starting co ordinates assuming a 320x240 display are AK 320 100 2 240 100 2 110 70 for y 70 y lt 180 y Set the memory pointer at the start of each line FK Pointer MEM_OFFSET Y Line_Width BPP 8 X BPP 8 NOTICE as this is default portrait mode the width is a power KK of two In this ca
119. of 0 landscape Default for EPSON Display Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D 13705 Width dword 140 Height dword FO Bpp dword 8 Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 7 Vancouver Design Center ActiveDisp dword 1 Rotation dword 0 13 From the Build menu select Rebuild Platform to generate a Windows CE image file NK BIN in the project directory x myproject myplatform reldir x86_release nk bin Build for CEPC X86 on Windows CE Platform Builder 3 00 using the Command Line Interface 1 Windows CE 3 x Display Drivers Issue Date 01 05 25 Install Microsoft Windows 2000 Professional or Windows NT Workstation version 4 0 with Service Pack 5 or later Install Windows CE Platform Builder 3 00 Create a batch file called x wince300 cepath bat Put the following in cepath bat x cd wince300 public common oak misc call wince x86 i486 CE MINSHELL CEPC set IMGNODEBUGGER 1 set WINCEREL 1 set CEPC_DDI_S1D13X0X 1 Generate the build environment by calling cepath bat Create a new folder called S1D13705 under x wince300 platform cepc drivers dis play and copy the S1D13705 driver source code into x wince300 platform cepc driv ers display S 1D13705 Edit the file x win
120. of RESET Refer to the 1D 3705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show those configuration settings important to the MC68K 1 and Generic 1 host bus interfaces Table 2 2 Summary of Power On Reset Options S1D1370 value on this pin at the rising edge of RESET is used to configure 1 0 5 Pin Name 0 CNFO CNF1 See Table 2 3 Host Bus Interface Selection CNF2 CNF3 titi Enda Banda configuration for MC68328 support Table 2 3 Host Bus Interface Selection CNF2 CNF1 CNFO BS Host Bus Interface 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 X reserved a a o a a ESS Eee 1 0 0 X reserved 1 0 1 X MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved Generic 2 16 bit configuration for MC68328 using Generic 1 host bus interface configuration for MC68328 using MC68K 1 host bus interface 2 4 3 MC68328 Chip Select Configuration 1D13705 X27A G 007 04 The S1D13705 requires a 128K byte address space for the display buffer and its internal registers To accommodate this block size it is preferable but not required to use one of the chip selects from groups A or B Virtually any chip select other than CSAO or CSD3 would be suitable for the S1D13705 interface In the example interface chip select CSB3 is used to control the S1D13705 A 128K byte address space is us
121. of generating a vertical non display period of up to sixty three lines This amount of VNDP is far too great a non display period and will likely degrade display quality Similarly setting a large HNDP value may cause a degrade in image quality If possible the system should be designed such that VNDP values of 7 or less lines and HNDP values of 20 or less characters can be selected Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 12 Epson Research and Development Vancouver Design Center 3 Memory Models The S1D13705 is capable of operating at four different color depths For each color depth the data format is packed pixel S1D13705 packed pixel modes can range from one byte containing eight adjacent pixels 1 bpp to one byte containing just one pixel 8 bpp Packed pixel data may be envisioned as a stream of pixels In this stream pixels are packed in adjacent to each other If a pixel requires four bits then it will be located in the four most significant bits of a byte The pixel to the immediate right on the display will occupy the lower four bits of the same byte The next two pixels to the immediate right are located in the following byte etc 3 1 1 Bit Per Pixel 2 Colors Gray Shades 1 bit pixels support two color gray shades In this memory format each byte of display buffer contains eight adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out appropr
122. on the S1D13705 that would be used to interface to the TMPR3912 The S1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The interface modes used for the TMPR3912 are e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte e Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping lA Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 ABO AO AO DB 15 0 D 15 0 D 15 0 WE1 WE1 BHE CS External Decode External Decode BCLK BCLK BCLK BS connect to Vgg connect to lO Vpp RD WR RD1 connect to lO Vpp RD RDO RD WEO WEO WE WAIT WAIT WAIT RESET RESET RESET For configuration details refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx Interfacing to the Toshiba MIPS TMPR3912 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 004 02 Page 10 Epson Research and Development Vancouver Design Center 3 2 Generic 1 Interface Mode 1D13705 X27A G 004 02 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13705 The Generic
123. only will display only files that can be configured using 13705CFG The configuration values can be saved only to specific files The file must have been compiled using the 13705 HAL library Checking Preserve Physical Addresses instructs 13705CFG to use the register and display buffer address values the files were previously configured with Addresses specified in the General Tab are discarded This is useful when configuring several programs for various hardware platforms at the same time For example if configuring PCI MPC and IDP based programs at the same time for a new panel type the physical addresses for each are retained This feature is primarily intended for the test lab where multiple hardware configurations exist and are being tested 13705CFG Configuration Program X27A B 001 03 Issue Date 02 03 11 Epson Research and Development Page 21 Vancouver Design Center Export After determining the desired configuration Export permits the user to save the register information as a variety of ASCU text file formats The following is a list and description of the currently supported output formats a C header file for use in writing HAL library based applications a C header file which lists each register and the value it should be set to a C header file for use in developing Window CE display drivers a C header file for use in developing display drivers for other operating systems such as Linux QNX and VxW
124. ras 9 S LL 39 s b y ep dv eb Ev Y ld E zq TV 7 t Dv TO qe tF od 2H IH P F sued COINAGE Z I T sued GOTAO S Z ASZ ANOL anro 219 3 LLO Ea h FAOT 99A0 LOA NIA He 099A EEWO A PYZOHYYZ 7 en mo LA NEO 010 or jane 22 Esr eugavaH NS DOA DI H Ri 0 i var x IPAS pve KE fexz eve 1 ne ave gE LAZ vz zi At Wt Hanyag veda 9091 E F HEN ev Na HUMO yMdd01 El ZAL AAS lt Agua VAL ivi KUT IHS er e asa A dde ae veZOHWrL Eu a anro 69 zano 92 er 8590 ore Xe taz tvz Ly geaz evz Hi gia VOYNOO om aye ve Ter 6 TE maw avesa ZAI wl e mwaa S bhHyddd ee Le EAL ev OLIVad3 F 70808 3NMd38 PE Fo owd e HaGA O se se ZAL O mi lt 6lY d4 s oF y blvd gt anro zyno sz nelt ve 8 VAL ivi lt Blvad4 I3AS438 er Fe smda veo HS a E SE En zano ino Dno amo o e ango ori xez gZ 2 A DA ON HX 92 g vbZOHWeL ve ez Trivddse l ee orvagaa No x oz 6L DON rk a aS 61V0d38 0 91 si Sivads8 raz we 1vdd38 E yl el EAZ eve Sivadsa El zi il zaz ave Sivadsa Z OL 6 1vd439 6 LAZ LYZ 8 Zr PAL vv 9 S EAL ev y 199938 TAL vi lv E e 1Iv dJg EINA iy 01V0d38 er Sr en BOLO3NNOO 097 ONOW HOTOD A0 S Ag TIBVLOITIAS ovas olvada E yz 9 S E y L Figure 8 3 SIDI3705B00C Schematic Diagram 3 of 4 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13705 Issue Date 01 02 13 X27A G 005 03 Page 23 Epson Research and Development Vancouver Design Center
125. save mode The following settings are recommended when using the S3U13705B00C with the ISA S1D13705 X27A G 005 03 bus Table 2 1 Configuration DIP Switch Settings Switch Signal Closed 0 or low Open 1 or high S1 1 CNFO 1 2 CNF1 See Host Bus Selection table below See Host Bus Selection table below 1 3 CNF2 S1 4 CNF3 Little Endian Big Endian S1 5 ADDR Memory Register Start Address COOOOh Memory Register Start Address F00000h S1 6 GPIOO Hardware Suspend Disable Hardware Suspend Enable recommended settings configured for ISA bus support Table 2 2 Host Bus Selection S1 3 1 2 S1 1 BS Host Bus Interface 0 0 0 X SH 4 bus interface 0 0 1 X SH 3 bus interface 0 1 0 X reserved 0 1 1 X MC68K bus interface 1 16 bit 1 0 0 X reserved 1 0 1 Xx MC68K bus interface 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 0 Generic 1 16 bit 1 1 1 1 Generic 2 16 bit recommended settings configured for ISA bus support S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 Epson Research and Development Vancouver Design Center Table 2 3 Jumper Settings Page 9 Description 1 2 2 3 JP1 IOVDD Selection 5 0V lOVDD 3 3V lOVDD JP2 RD WR Signal Selection Pulled up to IOVDD No Connection JP3 BS Signal Selection Pulled up to IOVDD No Connection
126. square wave reference clock called MCLK Master Clock This clock runs at the machine cycle speed of the CPU core typically 25 to 50 MHz Most outputs from the processor change state on the rising edge of this clock Similarly most inputs to the processor are sampled on the rising edge Note The external bus can run at one half the CPU core speed using the clock control register This is typically used when the CPU core is operated above 50 MHz The MPC821 can generate up to eight independent chip select outputs each of which may be controlled by one of two types of timing generators the General Purpose Chip Select Module GPCM or the User Programmable Machine UPM Examples are given using the GPCM It should be noted that all Power PC microprocessors including the MPC8xx family use bit notation opposite from the convention used by most other microprocessor systems Bit numbering for the MPC8xx always starts with zero as the most significant bit and incre ments in value to the least significant bit For example the most significant bits of the address bus and data bus are AO and DO while the least significant bits are A31 and D31 The MPC8xx uses both a 32 bit address and data bus A parity bit is supported for each of the four byte lanes on the data bus Parity checking is done when data is read from external memory or peripherals and generated by the MPC8xx bus controller on write cycles All IO accesses are memory mapped meaning
127. standalone applications Utility files based on the Hardware Abstraction Layer HAL can be modified directly by 13705CFG 13705CFG Configuration Program Issue Date 02 03 11 Epson Research and Development Page 7 Vancouver Design Center 13705CFG Configuration Tabs 13705CFG provides a series of tabs which can be selected at the top of the main window Each tab allows the configuration of a specific aspect of S1D13705 operation The tabs are labeled General Preference Clocks Panel Panel Power and Registers The following sections describe the purpose and use of each of the tabs General Tab 705 51D13705 Configuration Utility The General tab contains S1D13705 evaluation board specific information The values presented are used for configuring HAL based executable utilities The settings on this tab specify where in CPU address space the registers and display buffer are located 13705CFG Configuration Program S1D13705 Issue Date 02 03 11 X27A B 001 03 Page 8 S1D13705 X27A B 001 03 Decode Addresses Register Address Display Buffer Address Note Epson Research and Development Vancouver Design Center Selecting one of the listed evaluation platforms changes the values for the Register address and Display buffer address fields The values used for each evalu ation platform are examples of possible implementa tions as used by the Epson S1D13705 evaluation board
128. the MCF5307 lt lt 8 2 1 The MCF5307 System Bus 2 e 2 ee ee ee 8 Dal SOVERVICW oil dl Buel eh aa cate eo hate ee ans Bee amp Gos 8 2 1 2 Normal Non Burst Bus Transactions e ee 8 2 37 BUSE CYESS ova te Betis A ei EA nds DA ts ede eat Do 9 2 2 Chip Select Modul s accurate 10 3 1D13705 Bus Interface 2 0222 curs Oe ad POE Eee 11 3 1 Host Bus Pin Connection 0 0 0 11 3 2 Generic 1 Interface Mode 02020202 2202020200200282 2 12 4 MCF5307 To S1D13705 Interface 2 2 ee es 13 4 1 Hardware Description 2 eee 13 4 2 S1D13705 Hardware Configuration 2 2 2 ee ee A 4 3 MCF5307 Chip Select Configuration 15 SOMWANG SA be Bend Sy Bena eer eae ae ada 16 References us ke see ts at are Ad SR ed A ato a ee ee Berm cat wa 17 Os DOCUMENTS i 4 il se be MB oP eo ok we PA pt Be A Ae te odie ae ee A 6 2 Document Sources o 17 7 Technical Support 200003 a a iS ae Sei ee Ee ae ee da 18 7 1 EPSON LCD Controllers S1D13705 2 0 2 2 2 18 7 2 Motorola MCF5307 Processor 2 2 2 ee ee ee ee 18 Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13705 Issue Date 01 02 13 X27A G 01 1 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X27A G 01
129. the following interfaces Hitachi SH 3 Hitachi SH 4 Motorola M68K MPU bus interface using WAIT signal Direct memory mapping of internal registers Single level CPU write buffer Registers are mapped into upper 32 bytes of 128K byte address space The complete 80K byte display buffer is directly and contiguously available through the 17 bit address bus 2 3 Display Support 1D13705 X27A A 001 10 4 8 bit monochrome LCD interface 4 8 bit color LCD interface Single panel single drive passive displays Dual panel dual drive passive displays Active Matrix TFT D TFD interface Register level support for EL panels Example resolutions 640x480 at a color depth of 2 bpp 640x240 at a color depth of 4 bpp 320x240 at a color depth of 8 bpp Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 11 Vancouver Design Center 2 4 Display Modes 2 5 Clock Source SwivelView direct 90 hardware rotation of display image for portrait mode display 1 2 4 bit per pixel bpp 2 4 16 level grayscale display 1 2 4 8 bit per pixel 2 4 16 256 level color display Up to 16 shades of gray by FRM on monochrome passive LCD panels a 256x4 Look Up Table is used to map 1 2 4 bpp modes into these shades 256 simultaneous of 4096 colors on color passive and active matrix LCD panels three 256x4 Look Up Tables are used to map 1 2 4 8 bpp modes into these colors Split screen display for all
130. the word address of the start of Screen 1 in Landscape modes or the byte address of the start of Screen 1 in SwivelView modes Note For SwivelView mode the most significant bit bit 16 is located in REG 10h REG 0Eh Screen 2 Start Address Register LSB Address 1FFEEh Read Write Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 0OFh Screen 2 Start Address Register MSB Address 1FFEFh Read Write Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Screen 2 Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG OFh bits 7 0 REG OEh bits 7 0 Screen 2 Start Address Bits 15 0 These bits determine the word address of the start of Screen 2 in Landscape modes only and has no effect in SwivelView modes REG 10h Screen Start Address Overflow Register Address 1FFFOh Read Write Screen 1 Start n a n a n a n a n a n a n a Address Bit 16 bit 0 Screen Start Address Bit 16 This bit is the most significant bit of Screen 1 Start Address for Swivel View mode This bit has no effect in Landscape mod
131. use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S 1D13705 Width dword 140 Height dword FO Bpp dword 8 Rotation dword 0 RefreshRate dword 3C Flags dword 1 Note that all dword values are in hexadecimal therefore 140h 320 FOh 240 and 3Ch 60 The value for Flags should be 1 LCD When the display driver starts it will read these values in the registry and attempt to match a mode table against them All values must be present and valid for a match to occur otherwise the display driver will default to the first mode table in your list A WinCE desktop application or control panel applet can change these registry values and the display driver will select a different mode upon warmboot This allows the display driver to support different display configurations and or orientations An example appli cation that controls these registry values will be made available upon the next release of the display driver preliminary alpha code is available by special request Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 13 Vancouver Design Center Resource Management Issues The Windows CE 3 0 OEM must deal with certain display driver issues relevant to Windows CE 3 0 These issues require the OEM balance factors such as system vs display memory utilization video performance and power off capabilit
132. was built using Red Hat Linux 6 1 kernel version 2 4 5 For information on building the kernel refer to the readme file at ftp ftp linuxberg com pub linux kernel README Note Before continuing with modifications for the S1D13705 you should ensure that you can build and start the Linux operating system 2 Unzip the console driver files Using a zip file utility unzip the S1D13705 archive to a temporary directory e g tmp When completed the files Config in fbmem c fbcon cfb4 c Makefile should be located in the temporary directory tmp and the files Makefile s1d13xxxfb c s1d13705 h should be located in a sub directory called epson within the temporary directory tmp epson 3 Copy the console driver files to the build directory Make the directory usr src linux drivers video epson Copy the files tmp epson s1d13xxxfb c tmp epson s1d13705 h tmp epson Makefile to the directory usr src linux drivers video epson 1D13705 X27A E 004 02 Page 8 S1D13705 X27A E 004 02 Epson Research and Development Vancouver Design Center Copy the remaining source files Itmp Config in tmp fbmem c Itmp fbcon cfb4 c tmp Makefile into the directory usr src linux drivers video replacing the files of the same name If your kernel version is not 2 4 5 or you want to retain greater control of the build process then use a text editor and cut and paste the sections dealing with the Epson driver in the corresponding f
133. 0 F7 20 30 40 38 70 70 FO 78 00 70 00 B8 40 00 00 F8 00 00 00 39 90 70 FO 79 00 70 10 B9 40 10 00 F9 00 00 00 3A BO 70 FO 7A 00 70 30 BA 40 20 00 FA 00 00 00 3B DO 70 FO 7B 00 70 50 BB 40 30 00 FB 00 00 00 3C FO 70 FO 7C 00 70 70 BC 40 40 00 FC 00 00 00 3D FO 70 DO 7D 00 50 70 BD 30 40 00 FD 00 00 00 3E FO 70 BO 7E 00 30 70 BE 20 40 00 FE 00 00 00 3F FO 70 90 7F 00 10 70 BF 10 40 00 FF 00 00 00 Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 22 Epson Research and Development Vancouver Design Center 4 2 2 Gray Shade Modes S1D13705 X27A G 002 03 Gray shade modes are monochrome display modes Monochrome display modes use the Look Up Table in a very similar fashion to the color modes This most significant difference is that the monochrome display modes use only the intensity of the green element of the Look Up Table to form the gray level One side effect of using only green for intensity selection is that in gray shade modes there are only sixteen possible intensities 8 bit per pixel is not supported for gray shade modes 1 bpp gray shade When the S1D137053 is configured for 1 bpp gray shade mode the LUT is limited to selecting colors from the first two green entries The two LUT entries can be set to any of sixteen possible intensities Typically they would be set to Oh black and Fh white Each byte in the display buffer contains eight adjacent pixels If a bit has a value of 0 then th
134. 0322002020 be eee ee de ed we Fe ee ee 15 7 1 Epson LCD CRT Controllers S1D13705 2 2 2 2 eee ee 15 Interfacing to an 8 bit Processor 1D13705 Issue Date 01 12 20 X27A G 015 01 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to an 8 bit Processor X27A G 015 01 Issue Date 01 12 20 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping a 9 Table 4 1 Configuration Settings ee 12 Table 4 2 Host Bus Selection ypu an doe e i aa ds o 12 List of Figures Figure 4 1 Typical Implementation of an 8 bit Processor to the S1D13705 Generic 2 Interface 11 Interfacing to an 8 bit Processor S1D13705 Issue Date 01 12 20 X27A G 015 01 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to an 8 bit Processor X27A G 015 01 Issue Date 01 12 20 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware environment required to provide an interface between the S1D13705 Embedded Memory LCD Controller and a generic 8 bit micropro cessor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Research and Development Website
135. 05 Issue Date 01 02 13 X27A G 013 02 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4181A Configuration The NEC VR4181A must be configured through its internal registers in order to map the S1D13705 to the external LCD controller space The following register values must be set Register LCDGPMD at address 0B00 032Eh must be set as follows Bit 7 must be set to 1 to disable the internal LCD controller and enable the external LCD controller interface This also maps pin SHCLK to LCDCS and pin LOCLK to FMEMCS 16 e Bits 1 0 must be set to 01b to reserve 128Kbytes of memory address range 133E 0000h to 133F FFFFh for the external LCD controller Register GPMD2REG at address 0B00 0304h must be set as follows e Bits 9 8 GP20MD 1 0 must be set to 11b to map pin GPIO20 to UBE e Bits 5 4 GP18MD 1 0 must be set to 01b to map pin GPIO18 to IORDY S1D13705 Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13705CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types re
136. 05 Source code modification is required to provide a smaller more efficient driver for mass production e g Swivel View support may be removed for products not requiring display rotation The WindML display drivers are designed around a common configuration include file called mode0 h which is generated by the configuration utility 13705CFG This design allows for easy customization of clocks decode addresses rotation etc by OEMs For further information on 13705CFG see the 13705CFG Configuration Program User Manual document number X27A B 001 xx Note The WindML display drivers are provided as reference source code only They are in tended to provide a basis for OEMs to develop their own drivers for WindML v2 0 These drivers are not backwards compatible with UGL v1 2 For information on the UGL v1 2 display drivers see Wind River UGL v1 2 Display Drivers document number X27A E 003 xx This document and the source code for the WindML display drivers is updated as appro priate Please check the Epson Electronics America website at http www eea epson com or the Epson Research and Development website at http www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation erd epson com Wind River WindML v2 0 Display Drivers 1D13705 Issue Date 01 04 06 X27A E 002 03 Page 4 Epson Research and Development
137. 0A G 004 02 Issue Date 01 03 07 EPSON Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the interface between the S1D13704 5 LCD Controller LCDC and the TMPR3912 22U microprocessor as implemented on the Toshiba 3912 22 and S1D13704 5 CPU Module This module is used in conjunction with the Toshiba TX RISC Reference Platform For more information regarding the S1D13704 or S1D13705 refer to their respective Hardware Functional Specification document number X26A A 001 xx and X27A A 001 xx respectively For more information regarding the TMPR3912 22U refer to the TMPR3912 22U 32 Bit MIPS RISC Processor User s Manual See the Toshiba website under semiconductors at http toshiba com taec nonflash indexproducts html 1 1 General Description The Toshiba TX RISC Reference Kit consists of 6 boards which include a main board a CPU board a EPROM board a FMEM board a debug board and an analog board The main board acts as the motherboard for all the other add on boards In addition to these boards there is an LCD module that connects to the CPU board In order to support the add on LCD panel that connects to the LCD module the CPU board microprocessor must have an internal LCD controller or the CPU board must have an LCD controller on it that interfaces to the microprocessor For the TMPR3912 22U microprocessor the S1D13704 or S1D13705 LCDC is used to provide support for LCD panels The LCDC
138. 1 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Blue Look Up Table 256x4 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 from Display Buffer 4 bit Red Data 4 bit Green Data 4 bit Blue Data unused Look Up Table entries Figure 11 6 4 Bit per pixel Color Mode Data Output Path Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Page 76 8 Bit per pixel Color Mode Epson Research and Development Vancouver Design Center 8 bit per pixel data Red Look Up Table 256x4 t 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 t 0000 0101 0000 0110 0000 0111 1111 1000 1111 1001 1111 1010 1111 1011 1111 1100 1111 1101 1111 1110 1111 1111 Green Look Up Table 256
139. 1 S1D13705 Embedded Memory LCD Controller The S1D13705 is a color monochrome LCD graphics controller with an embedded 80K Byte SRAM display buffer The high integration of the S1D13705 provides a low cost low power single chip solution to meet the requirements of embedded markets such as Office Automation equipment Mobile Commu nications devices and Palm size PCs where board size and battery life are major concerns Products requiring a Portrait display can take advantage of the Hardware Portrait Mode feature of the 1D13705 Virtual and Split Screen are just some of the display modes supported While focusing on devices targeted by the Microsoft Windows CE Operating System the S1D13705 s impartiality to CPU type or operating system makes it an ideal display solution for a wide variety of applications MW FEATURES e Embedded 80K byte SRAM display buffer Up to 256 simultaneous colors from a possible e Direct support for the following CPU s 4096 colors on passive LCD panels and active Hitachi SH 3 matrix TFT D TFD LCD panels Hitachi SH 4 e Register level support for EL panels Motorola M68xxx noe Forirar Mode MPU bus interface with programmable Spill lil pena READY e Virtual Display Support Resolutions up to e LCD power down sequencing 640x480 at a color depth of 2 bpp 640x240 at a color depth of 4 bpp 320x240 at a color depth of 8 bpp E SYSTEM BLOCK DIAGRAM Data and Digital Out CPU A di Control Sign
140. 1 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 11 Table 4 1 Summary of Power On Reset Options o e e 14 Table 4 2 Host Bus Interface Selection o e 14 List of Figures Figure 2 1 MCF5307 Memory Read Cycle o o e ee 9 Figure 2 2 MCF5307 Memory Write Cycle 2 2 00 0000000002 2 ee 9 Figure 4 1 Typical Implementation of MCF5307 to S1D13705 Interface 13 Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13705 Issue Date 01 02 13 X27A G 011 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X27A G 011 02 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to interface the S1D13705 Embedded Memory LCD Controller and the Motorola MCF5307 Processor The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea ep
141. 1 SAO Connected to ABO of the S1D13705 2 SA1 Connected to AB1 of the S1D13705 3 SA2 Connected to AB2 of the S1D13705 4 SA3 Connected to AB3 of the S1D13705 5 SA4 Connected to AB4 of the S1D13705 6 SA5 Connected to AB5 of the S1D13705 7 SA6 Connected to AB6 of the S1D13705 8 SA7 Connected to AB7 of the S1D13705 9 GND Ground 10 GND Ground 11 SA8 Connected to AB8 of the S1D13705 12 SA9 Connected to AB9 of the S1D13705 13 SA10 Connected to AB10 of the S1D13705 14 SA11 Connected to AB11 of the S1D13705 15 SA12 Connected to AB12 of the S1D13705 16 SA13 Connected to AB13 of the S1D13705 17 GND Ground 18 GND Ground 19 SA14 Connected to AB14 of the S1D13705 20 SA15 Connected to AB14 of the S1D13705 21 SA16 Connected to AB16 of the S1D13705 22 SA17 Connected to SA17 of the ISA bus connector 23 SA18 Connected to SA18 of the ISA bus connector 24 SA19 Connected to SA19 of the ISA bus connector 25 GND Ground 26 GND Ground 27 VCC 5 volt supply 28 VCC 5 volt supply 29 RD WR Connected to the R W signal of the S1D13705 30 BS Connected to the BS signal of the S1D13705 31 BUSCLK Connected to the BCLK signal of the S1D13705 32 RD Connected to the RD signal of the S1D13705 33 NC Not connected 34 CLKI Connected to the CLKI signal of the S1D13705 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center 5 Host Bus Interface Pin Mapping Table 5 1
142. 13 X27A G 010 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Motorola MPC821 Microprocessor X27A G 010 02 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13705 Embedded Memory LCD Controller and the Motorola MPC821 Processor The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MPC821 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 010 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MPC821 2 1 The MPC8xx System Bus The MPC8xx family of processors feature a high speed synchronous system bus typical of modern RISC microprocessors This section provides an overview of the operation of the CPU bus in order to establish interface requirements 2 2 MPC821 Bus Overview The MPC8xx microprocessor family uses a synchronous address and data bus All IO is synchronous to a
143. 13705 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MCF5307 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor S1D13705 X27A G 011 02 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 13 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the Philips MIPS PR31500 PR31700 Processor Document Number X27A G 012 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document
144. 13705 4 SD3 Connected to DB3 of the S1D13705 5 GND Ground 6 GND Ground 7 SD4 Connected to DB4 of the S1D13705 8 SD5 Connected to DB5 of the S1D13705 9 SD6 Connected to DB6 of the S1D13705 10 SD7 Connected to DB7 of the S1D13705 11 GND Ground 12 GND Ground 13 SD8 Connected to DB8 of the S1D13705 14 SD9 Connected to DB9 of the S1D13705 15 SD10 Connected to DB10 of the S1D13705 16 SD11 Connected to DB11 of the S1D13705 17 GND Ground 18 GND Ground 19 SD12 Connected to DB12 of the S1D13705 20 SD13 Connected to DB13 of the S1D13705 21 SD14 Connected to DB14 of the S1D13705 22 SD15 Connected to DB15 of the S1D13705 23 RESET Connected to the RESET signal of the S1D13705 24 GND Ground 25 GND Ground 26 GND Ground 27 12V 12 volt supply 28 12V 12 volt supply 29 WEO Connected to the WEO signal of the S1D13705 30 WAIT Connected to the WAIT signal of the S1D13705 31 CS Connected to the CS signal of the S1D13705 32 NC Not connected 33 WE1 Connected to the WE1 signal of the S1D13705 34 IOVDD Connected to the IOVDD supply of the S1D13705 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13705 Issue Date 01 02 13 X27A G 005 03 Page 12 S1D13705 X27A G 005 03 Epson Research and Development Table 4 2 CPU BUS Connector H2 Pinout Vancouver Design Center Connector CPU BUS Comments Pin No Pin Name
145. 1D13705 Support Advanced low level driver options xbpp packed pixels support where x is the color depth being compile for Once you have configured the kernel options save and exit the configuration utility Linux Console Driver Issue Date 01 09 19 Epson Research and Development Page 9 Vancouver Design Center 6 Compile and install the kernel Build the kernel with the following sequence of commands make dep make clean make bzImage sbin lilo if running lilo 7 Boot to the Linux operating system If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13705 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the necessary files and in structions on this process is on the Internet at www xfree86 org Linux Console Driver S1D13705 Issue Date 01 09 19 X27A E 004 02 Page 10 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Linux Console Driver X27A E 004 02 Issue Date 01 09 19 EPSON 1D13705 Embedded Memory LCD Controller QNX Photon v2 0 Display Driver Document Number X27A E 005 01 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is
146. 2 03 Page 16 4 1 Look Up Table Registers Epson Research and Development Vancouver Design Center REG 15h Look Up Table Address Register Read Write LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O LUT Address The LUT address register selects which of the 256 LUT entries will be accessed After three successive reads writes to the data register this register is automatically incremented to point to the next address REG 17h Look Up Table Data Register Read Write LUT Data Bit 3 LUT Data Bit 2 LUT Data Bit 1 LUT Data Bit O n a n a n a S1D13705 X27A G 002 03 LUT Data This register is where the 4 bit red green blue data value is written read Immediately after setting the LUT index with register 15h this register accesses the red element of the Look Up Table With each successive write read the internal bank select is incremented Thus the second access is from the green element and the third is from the blue element After the third access the LUT Address is incremented by one then next access to this register will be the red element of the next Look Up Table index Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Vancouver Design Center 4 2 Look Up Table Organization 4 2 1 Color
147. 241 G8 XO EA XOX FPDATO 241 R2X241 G3X241 B4X241 R6X241 G7 241 B8 EIO EA Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel Figure 7 23 Dual Color 8 Bit Panel Timing VDP Vertical Display Period VNDP Vertical Non Display Period REG OAh bits 5 0 Lines HDP Horizontal Display Period HNDP Horizontal Non Display Period S1D13705 X27A A 001 10 REG 04h bits 6 0 1 x 8Ts REG 08h 4 x 8Ts REG 06h bits 1 0 REG O5h bits 7 0 1 Lines Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 51 Vancouver Design Center tl t2 Sync Timing p AA Frame Pulse gt 14 13 R Line Pulse t5 DRDY MOD X Data Timing Line Pulse t6 t8 t9 t7 t14 t11 t10 gt gt Shift Pulse a t12 t13 FPDAT 7 0 x l e a Figure 7 24 Dual Color 8 Bit Panel A C Timing Table 7 17 Dual Color 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse falling edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Line Pulse falling edge note 6 t8 Line Pul
148. 2U with minimal glue logic Since the address bus of the TMPR3912 22U is multiplexed it is demultiplexed using an advanced CMOS latch 74ACT373 to obtain the higher address bits needed for the S1D13704 5 The following diagram demonstrates the implementation of the interface 1D13704 3 3V TMPR3912 22U Po RD gt WE 4 CARD1CSL CARD1CSH rl 3 3V7 33V ENDIAN System RESET gt Latch DE gt ALE gt a LJ A 12 0 Y gt D 31 24 4 D 23 16 4 gt 3 3V 40K pull up CARD1WAIT la DCLKOUT Clock divider L gt or Oscillator L gt Clock divider IO Vpp CORE Vpp RD WE10 WE1 BS RD WR RESET CS AB 15 13 AB 12 0 DBI7 0 DB 15 8 WAIT CLKI BUSCLK X00A G 004 02 Figure 3 1 SID13704 to TMPR3912 22U Interface 5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 EPSON Research and Development Page 11 Vancouver Design Center 3 2 Memory Mapping and Aliasing The S1D13704 requires an addressing space of 64K bytes while the S1D13705 requires 128K The on chip display memory occupies the range O through 9FFFh The registers occupy the range FFEOh through FFFFh The TMPR3912 22U demultiplexed address lines A16 and above are ignored if the S1D13704 is used thus it is aliased 1024 times at 64K byte intervals over the 64M byte
149. 3 GPIO3 GPIO3 GPIO3 GPIO3 GPIO3 GO GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 GPIO4 BFPDAT11 23 Inverse Inverse Inverse Inverse Inverse Inverse Inverse GPIO4 BO Video Video Video Video Video Video Video BFPSHIFT 33 FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT FPSHIFT BFPSHIFT2 35 FPSHIFT2 BFPLINE 37 FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE FPLINE BFPFRAME 39 FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME FPFRAME 2 26 GND Even GND GND GND GND GND GND GND GND GND Pins N C 28 VLCD 30 LCD panel negative bias voltage 24V to 14V LCDVCC 32 3 3V or 5V selectable with JP4 12V 34 12V 12V 12V 12V 12V 12V 12V 12V 12V VDDH 36 LCD panel positive bias voltage 23V to 40V BDRDY 38 MOD MOD MOD MOD MOD MOD DRDY DRDY BLCDPWR 40 LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR LCDPWR Note S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 Epson Research and Development Page 11 Vancouver Design Center 4 CPU Bus Interface Connector Pinouts Table 4 1 CPU BUS Connector H1 Pinout Connector CPU BUS Comment Pin No Pin Name 1 SDO Connected to DBO of the S1D13705 2 SD1 Connected to DB1 of the S1D13705 3 SD2 Connected to DB2 of the S1D
150. 3 XX ERROR An IOCTL error occurred This message indicates an error at the IO control layer occurred The usual cause for this is an incorrect hardware configuration ERROR The HAL returned an unknown error This message should never be displayed it indicates that 13705SHOW is unable to determine the cause of an error returned from the HAL 1D13705 X27A B 005 04 Page 8 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705PLAY Diagnostic Utility X27A B 005 04 Issue Date 01 07 04 EPSON 1D13705 Embedded Memory LCD Controller 13705BMP Demonstration Program Document No X27A B 006 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705BMP Demonstration Program X27A B 006 03 Iss
151. 3 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D137053 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS signal indicates that the address on the address bus is valid The WEO and RD signals is not used in the bus interface for MC68K 1 and must be tied high tied to IO Vpp Interfacing to the Motorola Dragonball Family of Microprocessors S1D13705 Issue Date 01 02 13 X27A G 007 04 Page 12 Epson Research and Development Vancouver Design Center 2 4 MC68328 To S1D13705 Interface 2 4 1 Hardware Description The interface between the MC68328 and the S1D13705 can be implemented using either the MC68K 1 or Generic 1 host bus interface of the 1D13705 Using The MC68K 1 Host Bus Interface The MC68328 multiplexes dual functions on some of its bus control pins specifically UDS LDS and DTACK In implementations where all of these pins are available for use as bus control pins then the S1D13705 interface is a straightforward implementation of the MC68K 1 host bus interface The following diagram shows a typical implementation of the MC68328 to S1D13705 using the MC68K 1 host bus inte
152. 4 V VoH High Level Output Voltage l loH IO Vpp 0 4 V Vop MAX loz Output Leakage Current Vou Vpp 1 1 uA VoL Vss Court Output Pin Capacitance 10 pF Cpip Bidirectional Pin Capacitance 10 pF Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 26 Epson Research and Development Vancouver Design Center 7 A C Characteristics Conditions IO Vpp 2 7 V to 5 0 V Ta 40 C to 85 C Tise and Ts for all inputs must be lt 5 nsec 10 90 C 60pF Bus MPU Interface C 60pF LCD Panel Interface 7 1 Bus Interface Timing 7 1 1 SH 4 Interface Timing Tckio t2 13 gt CKIO HY t4 t5 gt A 16 0 M R RD WR A t6 t7 gt BS t8 gt CSn WEn i i RD cal t2 MEL N t14 gt RDY ss a 4 t15 He D 15 0 Hi Z E a Hi Z write t18 a hime D 15 0 Hi Z Hi Z read VALID Figure 7 1 SH 4 Timing Note The SH 4 Wait State Control Register for the area in which the S1D13705 resides must be set to a non zero value The SH 4 read to write cycle transition must be set to a non zero value with reference to BUSCLK 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 27 Vancouver Design Center Table 7 1 SH 4 Timing Symbol Parameter Min Max Units f
153. 40 30 04 AO 00 00 44 FO FO 70 84 70 30 70 C4 00 40 40 05 AO 00 AO 45 DO FO 70 85 70 30 60 C5 00 30 40 06 AO 50 00 46 BO FO 70 86 70 30 50 C6 00 20 40 07 AO AO AO 47 90 FO 70 87 70 30 40 C7 00 10 40 08 50 50 50 48 70 FO 70 88 70 30 30 C8 20 20 40 09 50 50 FO 49 70 FO 90 89 70 40 30 C9 20 20 40 OA 50 FO 50 4A 70 FO BO 8A 70 50 30 CA 30 20 40 0B 50 FO FO 4B 70 FO DO 8B 70 60 30 CB 30 20 40 0C FO 50 50 4C 70 FO FO 8C 70 70 30 CC 40 20 40 oD FO 50 FO 4D 70 DO FO 8D 60 70 30 CD 40 20 30 0E FO FO 50 4E 70 BO FO 8E 50 70 30 CE 40 20 30 OF FO FO FO 4F 70 90 FO 8F 40 70 30 CF 40 20 20 10 00 00 00 50 BO BO FO 90 30 70 30 DO 40 20 20 11 10 10 10 51 CO BO FO 91 30 70 40 D1 40 20 20 12 20 20 20 52 DO BO FO 92 30 70 50 D2 40 30 20 13 20 20 20 53 EO BO FO 93 30 70 60 D3 40 30 20 14 30 30 30 54 FO BO FO 94 30 70 70 D4 40 40 20 15 40 40 40 55 FO BO EO 95 30 60 70 D5 30 40 20 16 50 50 50 56 FO BO DO 96 30 50 70 D6 30 40 20 17 60 60 60 57 FO BO Co 97 30 40 70 D7 20 40 20 18 70 70 70 58 FO BO BO 98 50 50 70 D8 20 40 20 19 80 80 80 59 FO Co BO 99 50 50 70 D9 20 40 20 1A 90 90 90 5A FO DO BO 9A 60 50 70 DA 20 40 30 1B AO AO AO 5B FO EO BO 9B 60 50 70 DB 20 40 30 S1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 21 Vancouver Design Center Table
154. 5 Chip Select Minimal glue logic is used on the CPU module to provide the chip select signal CS for the LCDC A simple AND gate activates the S1D13704 5 whenever the PC Card slot 1 is accessed whether it be memory space or attribute space S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 X00A G 004 02 Page 14 EPSON Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the NEC VR4181A Microprocessor Document Number X27A G 013 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 Epson
155. 5mW 256 Colors 8 65mW 1 52mW 10 16mW Input Clock 25MHz 3 LCD Panel 640x480 8 bit Single Black and White 13 97mW 1 10mW 15 07mW 1 2 4 Gray Shades 16 75mw 2 08mw 18 83mw mw 232mW Monochrome Input Clock 25MHz 2 Colors 15 53mW 2 64mW 18 17mW 4 2 4 LCD Panel 640x480 8 bit Single Color 4 Colors 18 30mW 7 16mWw 25 47mw 2589MW 2 32mW Input Clock 25MHz 7 re Black and White 13 84mW 1 08mW 14 93mW 1 2 5 LCD Panel 640x480 8 bit Dual 4 Grey Shades 20 38mW 2 07mW 22 45mW 2 53mwW 2 32mW Monochrome Input Clock 25MHz 7 ae 2 Colors 15 82mW 2 62mW 18 44mW 4 2 6 LCD Panel 640x480 8 bit Dual Color 4 Colors 23 31mW 7 01mW 30 32mW 2 53mW 2 32mwW Input Clock 25MHz 7 hi 2 Colors 11 42mW 7 40mW 18 82mW 1 2 7 LCD Panel 640x480 9 bit TFT 4 Colors 19 74mw 20 96mW 40 70mW 2 53mW 2 32mW Note 1 Conditions for Software Power Save e CPU interface active signals toggling e CLKI active 2 Conditions for Hardware Power Save e CPU interface inactive high impedance e CLKI active 1D13705 Power Consumption X27A G 006 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center 2 Summary Power Consumption Issue Date 01 02 13 The system design variables in Section 1 S1D13705 Power Consumption and in Table 1 1 S1D13705 Total Power Consumption show that S1D13705 power consum
156. 7 m h Xo FORO 08 yeas o Po AS Se a8 Asi 4 ou sas oi t sas lv A 908 Fe 30S 13s3u lt E 1asa8 as HE ONO HOO Ex is er Hr aaaol tero gt si olas ASZ anOL elo F 99A g 9 ba y E L S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date Epson Research and Development Page 22 Vancouver Design Center ye Pg 566190 Ender Repu AE ob a nou sequiny wewnoog ezis SI0peoH 3 JO eUUOD GOT PuBBPEN eAg 0 494 SNg YSI DODESOLELNSS ou juawidojenag Y yoreesey uosd3 5 Ms sy teros Let dvs Ny roas stolas a ZXLLU3OVIH gt ZXLL U3OV3H W19 ve ee x aanolot dre ee pb 13M 408 Ze le nosna dze kep 89 sg og 6z p 4M 0H LIVM qoe 62 gt HOM gon Tp 3 BRT Son amo Pe ai dre teh vi 1 dre teh 1as3y Noz ee ey A ads mao p a A svS NI LS as pp 48 St po Tetas 91 St dot Sib eet SS wE p NA zl LL oe qzl LL fo A o 6 za fot 6f yT LS g8 R WS sos 1398 PJ
157. 705 Issue Date 01 06 07 X27A E 001 03 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for 1 Windows CE 2 0 using a command line interface 2 Windows CE Platform Builder 2 1x using a command line interface In all examples x refers to the drive letter where Platform Builder is installed Build for CEPC X86 on Windows CE 2 0 using a Command Line Interface S1D13705 X27A E 001 03 To build a Windows CE v2 0 display driver for the CEPC X86 platform using a S5U13705B00C evaluation board follow the instructions below 1 Install Microsoft Windows NT v4 0 or 2000 2 Install Microsoft Visual C C version 5 0 or 6 0 3 Install the Microsoft Windows CE Embedded Toolkit ETK by running SETUP EXE from the ETK compact disc 1 4 Create a new project by following the procedure documented in Creating a New Project Directory from the Windows CE ETK v2 0 Alternately use the current DEMO project included with the ETK v2 0 Follow the steps below to create a X86 DEMO7 shortcut on the Windows NT v4 0 desktop which uses the current DEMO project a Right click on the Start menu on the taskbar b Click on the item Open All Users and the Start Menu window will come up c Click on the icon Programs d Click on the icon Windows CE Embedded Development Kit
158. 705 Interfacing to the Motorola Dragonball Family of Microprocessors X27A G 007 04 Issue Date 01 02 13 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction 40200330 ca a a a al e 2 interfacing to the MC68328 2 1 The MC68328 System Bus 2 2 Chip Select Module 2 3 S1D13705 Host Bus Interface 2 3 1 Host Bus Pin Connection 2 3 2 Generic 1 Interface Mode 2 3 3 MC68K 1 Interface Mode 2 4 MC68328 To S1D13705 Interface 2 4 1 Hardware Description o o e 2 4 2 S1D13705 Hardware Configuration 2 4 3 MC68328 Chip Select Configuration 3 Interfacing to the MC68EZ328 3 1 The MC68EZ328 System Bus 3 2 Chip Select Module 3 3 S1D13705 Host Bus Interface 3 3 1 Host Bus Pin Connection 3 3 2 Generic 1 Interface Mode 3 4 MC683EZ28 To S1D13705 Interface 3 4 1 Hardware Description o o e 3 4 2 S1D13705 Hardware Configuration 3 4 3 MC68EZ328 Chip Select Configuration 4 Interfacing to the MC68VZ328 lt 4 1 The MC68VZ328 System Bus 4 2 Chip Select Module 4 3 S1D13705 Host Bus Interface 4 3 1 Host Bus Pin Connection 4 3 2 Generic 1 Interface Mode
159. 705 for Generic 2 mode and should be tied high connected to IOVpp RD WR should also be tied high Interfacing to the NEC VR4181A Microprocessor 1D13705 Issue Date 01 02 13 X27A G 013 02 Page 12 Epson Research and Development Vancouver Design Center 4 VR4181A to S1D13705 Interface 4 1 Hardware Description The NEC VR4181A microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 interface a glueless interface is achieved The diagram below shows a typical implementation of the VR4181A to S1D13705 interface NEC VR4181A S1D13705 MEMWR WEO UBE gt WE1 MEMRD gt RDA LCDCS Pulbup gt CS WAIT ry IORDY MEMCS16 System RESET RESET A 16 0 gt AB 15 0 D 15 0 DB 15 0 Oscillator gt BCLK Vec t _ BSH Vcc t _ RD WR Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states 1D13705 X27A G 013 02 Figure 4 1 Typical Implementation of VR4181A to SIDI3705 Interface Interfacing to the NEC VR4181A Microprocessor Issue Date 01 02 13 Epson Research and Development Vancouver Desig
160. A A 001 10 Page 56 Epson Research and Development Vancouver Design Center bit 4 FPLINE Polarity This bit controls the polarity of FPLINE in TFT D TFD mode no effect in passive panel mode When this bit 0 FPLINE is active low When this bit 1 FPLINE is active high bit 3 FPFRAME Polarity This bit controls the polarity of FPFRAME in TFT D TFD mode no effect in passive panel mode When this bit 0 FPFRAME is active low When this bit 1 FPFRAME is active high bit 2 Mask FPSHIFT FPSHIFT is masked during non display periods if either of the following two criteria is met 1 Color passive panel is selected REG 01h bit 5 1 2 This bit REG O1h bit 2 1 bits 1 0 Data Width Bits 1 0 These bits select the display data format See Table 8 1 Panel Data Format below for a comprehensive description of panel selection Table 8 1 Panel Data Format Data Width Data Width Bee faerie neem CO een Function REG 01h bit 1 REG 01h bit 0 6 0 Mono Single 4 bit passive LCD 1 Mono Single 8 bit passive LCD E i 0 reserved 1 reserved 0 reserved f 9 1 Mono Dual 8 bit passive LCD E 0 reserved 1 reserved il 0 0 Color Single 4 bit passive LCD 1 Color Single 8 bit passive LCD format 1 y 0 reserved 1 Color Single 8 bit passive LCD format 2 0 reserved i g 1 Color Dual 8 bit passive LCD 0 reserved 1 reserved 0 9 bit TFT D TFD panel 1 X don t care
161. BUSCLK Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 13 Epson Research and Development Page 17 Vancouver Design Center Table 4 1 List of Connections from MPC821ADS to SIDI3705 Continued MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13705 Signal Name CS4 P6 D13 CS TA P6 B6 to inverter enabled by CS WAIT WEO P6 B15 WE1 WE1 P6 A14 WEO0H OE P6 B16 RD WR RDA P12 A1 P12 B1 P12 A2 P12 B2 P12 A3 P12 B3 P12 A4 P12 B4 P12 A5 P12 B5 P12 A6 P12 B6 P12 A7 GND Vss Note The bit numbering of the Power PC bus signals is reversed from the normal convention e g the most significant address bit is AO the next is Al A2 etc Interfacing to the Motorola MPC821 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 010 02 Page 18 4 3 S1D13705 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show only those configuration settings important to the MPC821 interface The settings are very similar to the ISA bus with the following exceptions e the WAIT signal is active high rather than active low e the Power PC is big endian rather than little endian Table 4
162. Bit 2 Bit 1 Bit 0 Red bit 2 Red bit 1 Red bit 0 Green bit 2 Green bit 1 Green bit 0 Blue bit 1 Blue bit 0 Figure 3 4 Pixel Storage for 8 Bpp 256 Colors in One Byte of Display Buffer 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 15 Vancouver Design Center 4 Look Up Table LUT This section is supplemental to the description of the Look Up Table architecture found in the S1D13705 Hardware Functional Specification Covered here is a review of the LUT registers recommendations for the color and gray shade LUT values and additional programming considerations for the LUT Refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx for more detail The S1D13705 Look Up Table consists of 256 indexed red green blue entries Each entry 1s 4 bits wide Two registers REG 15h and REG 17h control access to the LUT Each Look Up Table entry consists of a red green and blue component Each component consisting of four bits or sixteen intensity levels Any Look Up Table element can be selected from a palette of 4096 16x16x16 colors In color display modes pixel values are used as an index to an RGB value stored in the Look Up Table In monochrome modes pixel values still index into the LUT but only the green component is used to determine display intensity The selected color depth determines how many index positions are used for image display
163. CNF3 ite Endan poron gt configuration for MC68VZ328 support Table 4 3 Host Bus Interface Selection CNF2 CNF1 CNFO BSH Host Bus Interface 0 0 0 X SH 4 interface 0 0 1 X SH 3 interface 0 1 0 X reserved 1 0 0 X reserved 1 0 1 X MC68K 2 16 bit 1 1 0 0 reserved 1 1 0 1 reserved Generic 2 16 bit 1D13705 X27A G 007 04 configuration for MC68VZ328 using Generic 1 host bus interface configuration for MC68VZ328 using MC68K 1 host bus interface Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Page 29 Vancouver Design Center 4 4 3 MC68VZ328 Chip Select and Pin Configuration The S1D13705 requires a 128K byte address space for the display buffer and its internal registers To accommodate this block size it is preferable but not required to use one of the chip selects from groups A or B Groups A and B can have a size range of 128K bytes to 16M bytes and groups C and D have a size range of 32K bytes to 16M bytes Therefore any chip select other than CSAO would be suitable for the S1D137053 interface In the example interface chip select CSB1 is used to control the S1D13705 A 128K byte address space is used with the S1D13705 control registers mapped into the top 32 bytes of the 128K byte block and the 80K bytes of display buffer mapped to the starting address of the block The chip select should have its RO
164. Center 7 6 Examples Example 6 Enable default portrait mode for a 320x240 panel at 4 bpp Before switching to portrait mode from landscape mode display memory should be cleared to make the user perceived transition smoother Images in display memory are not rotated automatically by hardware and a garbled image would be visible for a short period of time 1f video memory is not cleared If alternate portrait is used then the CLK signal is divided in half to get the PCLK signal If the Input Clock Divide bit in register 02 is set we can simply reset the divider The result of this is a PCLK of exactly the same frequency as we used for landscape mode and we can use the current horizontal and vertical non display periods If the Input Clock Divide bit is not set then we must recalculate the frame rate based on the a PCLK value In this example we will bypass recalculation of the horizontal and vertical non display times frame rate by selecting the default portrait mode scheme 1 Calculate and set the Screen 1 Start Word Address register OffsetBytes Width x BitsPerPixel 8 1 256 x 4 8 1 127 007Fh Width is the width of the portrait mode display in this case the next power of two greater than 240 pixels or 256 Set Screenl Display Start Word Address LSB REG 0Ch to 7Fh and Screen1 Dis play Start Word Address MSB REG ODh to 00h 2 Calculate the Line Byte Count The Line Byte Count also must be based on the
165. Center List of Tables Table 3 1 Host Bus Interface Pin Mapping a 10 Table 4 1 Summary of Power On Reset Options ooa 000000000 eee 13 Table 4 2 Host Bus SelectiOO 0 0 ocre an a a 13 List of Figures Figure 4 1 Typical Implementation of VR4181A to S1D13703 Interface 12 Interfacing to the NEC VR4181A Microprocessor 1D13705 Issue Date 01 02 13 X27A G 013 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to interface the S1D13705 Embedded Memory LCD Controller and the NEC VR4181A microprocessor The NEC VR4181A microprocessor is specifically designed to support an external LCD controller and the pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O
166. Color 8 Bit Panel A C Timing Format l Table 7 15 Single Color 8 Bit Panel A C Timing Format 2 Table 7 16 Dual Monochrome 8 Bit Panel A C Timing Table 7 17 Dual Color 8 Bit Panel A C TiMin8 o o Table 7 18 TFI D TFD A C Timing e Table 8 1 Panel Data Format 00 00 0000 00000 Table 8 2 Gray Scale Color Mode Selection o o o Table 8 3 High Performance Selection o o e Table 8 4 Inverse Video Mode Select Options o o Table 8 5 Hardware Power Save GPIOO Operation Table 8 6 Software Power Save Mode Selection o oo Table 8 7 Selection of SwivelView Mode o o Table 8 8 Selection of PCLK and MCLK in SwivelView Mode Table 12 1 Default and Alternate SwivelView Mode Comparison Table 13 1 Power Save Mode Selection 2 o o o 00000 Table 13 2 Software Power Save Mode Summary Table 13 3 Hardware Power Save Mode Summary Table 13 4 Power Save Mode Function Summary Table 13 5 S1D13705 Internal Clock Requirements Hardware Functional Specification Issue Date 02 02 01 Page 5 1D13705 X27A A 001 10 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK
167. D controller chip select signal is programmed to a window of that size the S1D13705 must reside in the VR4181A physical address range of 133E 0000h to 133F FFFFh which 1s part of the external ISA memory space The signals required for external LCD controller access are listed below and obey ISA signalling rules e A 16 0 Address bus FUBE High byte enable active low e LCDCS LCD controller S1D13705 chip select active low e D 15 0 Data bus KMEMRD Read command active low e MEMWR Write command active low e MEMCS16 Sixteen bit peripheral capability acknowledge active low e IORDY Ready signal from S1D13705 e SYSCLK Optional prescalable bus clock Once an address in the LCD block of memory is accessed the LCD chip select LCDCS is driven low The read or write enable signals MEMRD or MEMWR are driven low for the appropriate cycle and IORDY is driven low by the 1D13705 to insert wait states into the cycle The high byte enable is driven low for 16 bit transfers and high for 8 bit transfers Interfacing to the NEC VR4181A Microprocessor 1D13705 Issue Date 01 02 13 X27A G 013 02 Page 10 Epson Research and Development Vancouver Design Center 3 S1D13705 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13705 that would be used to interface to the VR4181A The 1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several m
168. D13705 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the 13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the S1D13705 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13705 Issue Date 01 02 13 X27A G 012 02 Page 12 Epson Research and Development Vancouver Design Center 4 Direct Connection to the Philips PR31500 PR31700 4 1 General Description In this example implementation the S1D13705 occupies the PR31500 PR31700 PC Card slot 1 The S1D13705 is easily interfaced to the PR31500 PR31700 with minimal additional logic The address bus of the PR31500 PR31700 PC Card interface is multiplexed and must be demultiplexed using an advanced CMOS latch e g 74AHC373 The direct connection approach makes use of the S1D13705 in its Generic 2 interface configuration Th
169. DB 15 0 D 15 0 D 15 0 WE1 UDS WE1 CS External Decode External Decode BCLK CLK BCLK BS AS connect to Vss RD WR R W RD1 RD connect to lO Vpp RDO WEO connect to lO Vpp WEO WAIT DTACK WAIT RESET RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 1D13705 X27A G 007 04 Page 10 Epson Research and Development Vancouver Design Center 2 3 2 Generic 1 Interface Mode S1D13705 X27A G 007 04 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13705 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13705 host interface It is sepa rate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset
170. Development Vancouver Design Center Installation for CEPC Environment Once the NK BIN file is built the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system The two methods are described below 1 To start CEPC after booting from a floppy drive a Create a bootable floppy disk b Edit CONFIG SYS on the floppy disk to contain only the following line device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to CA Search for the loadCEPC utility in your Windows CE directories b Edit CONFIG SYS on the hard drive to contain only the following line device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy NK BIN and HIMEM SYS to c e Boot the system 1D13705 Windows CE 3 x Display Drivers X27A E 006 01 Issue Date 01 05 25 Epson Research and Development Page 11 Vancouver Design Center Configuration There are several issues to consider when configuring the display driver The issues cover
171. Diagram Generic 2 Bus e g ISA Bus S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 15 Vancouver Design Center 4 Functional Block Diagram 40k x 16 bit SRAM i Memory Power Save Register Controller Clocks LCD Generic MPU MC68K gt SH 3 SH 4 Look Up Table Sequence Controller Bus Clock Memory Clock Pixel Clock Figure 4 1 System Block Diagram Showing Data Paths 4 1 Functional Block Descriptions 4 1 1 Host Interface The Host Interface provides the means for the CPU MPU to communicate with the display buffer and internal registers 4 1 2 Memory Controller The Memory Controller arbitrates between CPU accesses and display refresh accesses It also generates the necessary signals to control the SRAM frame buffer 4 1 3 Sequence Controller The Sequence Controller controls data flow from the Memory Controller through the Look Up Table and to the LCD Interface It also generates memory addresses for display refresh accesses Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 16 Epson Research and Development Vancouver Design Center 4 1 4 Look Up Table The Look Up Table contains three 256x4 Look Up Tables or palettes one for each primary color In monochrome mode only the green Look Up Tabl
172. EG 04h 1 Pixels REG 11h Words Where Virtual Image REG ODh REG OCh is the Screen 1 Start Word Address BPP is Bits per Pixel as set by REG 02h bits 7 6 REG 11h is the Address Pitch Adjustment in Words REG OFh REG OEh is the Screen 2 Start Word Address REG 13h REG 12h is the Screen 1 Vertical Size REG 06h REG O5h is the Vertical Panel Size Figure 8 1 Screen Register Relationship Split Screen Consider an example where REG 13h REG 12 OCEh for a 320x240 display system The upper 207 lines CEh 1 of the panel show an image from the Screen 1 Start Word Address The remaining 33 lines show an image from the Screen 2 Start Word Address REG 15h Look Up Table Address Register Address 1FFF5h Read Write LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address LUT Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O bits 7 0 LUT Address Bits 7 0 These 8 bits control a pointer into the Look Up Tables LUT The S1D137053 has three 256 position 4 bit wide LUTs one for each of red green and blue refer to Section 11 Look Up Table Architecture on page 71 for details This register selects which LUT entry is read write accessible through the LUT Data Reg ister REG 17h Writing the LUT Address Register automatically sets the pointer to the Red LUT Accesses to the LUT Data Register automatically increment the pointer
173. EG 08h 4 x 8Ts 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 45 Vancouver Design Center Sync Timing ti 2 Frame Pulse t4 4 t3 si Line Pulse pete timing Line Pulse t6a t6b opa t8 t9 t7a t14 t11 t10 gt 4 gt tt Shift Pulse 2 t7b Shift Pulse A t12 t13 t12 t13 Do th to FPDAT 7 0 Y X X Figure 7 18 Single Color 8 Bit Panel A C Timing Format 1 Table 7 14 Single Color 8 Bit Panel A C Timing Format 1 Symbol Parameter Min Typ Max Units ti Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t6a Shift Pulse falling edge to Line Pulse rising edge note 4 t6b Shift Pulse 2 falling edge to Line Pulse rising edge note 5 t a Shift Pulse 2 falling edge to Line Pulse falling edge note 6 t7b Shift Pulse falling edge to Line Pulse falling edge note 7 t8 Line Pulse falling edge to Shift Pulse rising Shift Pulse 2 falling edge t14 2 Ts t9 Shift Pulse 2 Shift Pulse period 4 Ts t10 Shift Pulse 2 Shift Pulse pulse width low 2 Ts t11 Shift Pulse 2 Shift Pulse pulse width high 2 Ts t12 FPDAT 7 0 setup to Shift Pulse 2 Shift Pulse falling edge 1 Ts t13 FPDAT 7 0 hold from Shift Pul
174. EO H in x wince platform cepc drivers display S 1D13705 replacing the original configura tion file Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display LCD CRT TV and rotation information in MODE H PLAT FORM REG is located in x wince platform cepc files For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp in Swivel View 0 landscape mode Default for EPSON Display Driver 320x240 at 8 bits pixel LCD display no rotation Useful Hex Values 1024 0x400 768 0x300 640 0x280 480 0x1E0 320 140 240 0xF0 HKEY_LOCAL_MACHINE Drivers Display S 1D13705 Width dword 140 Height dword FO Bpp dword 8 ActiveDisp dword 1 Rotation dword 0 Delete all the files in wince release directory and delete x wince platform cepc bif Windows6 CE 2 x Display Drivers Issue Date 01 06 07 Epson Research and Development Page 9 Vancouver Design Center 12 Generate the proper building environment by double clicking on the Epson project icon Build Epson for x86 13 Type BLDDEMO lt ENTER gt at the command prompt of the Build Epson for x86 window to generate a Windows CE image file NK BIN Windows CE 2 x Display Drivers 1D13705 Issue Date 01 06 07 X27A E 001 03 Page 10 Epson Research and Development Vancouver Design Center Installation for CEPC Environment Once th
175. EPSON S1D13705 Embedded Memory LCD Controller S1D13705 TECHNICAL MANUAL Document No X27A Q 001 04 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 TECHNICAL MANUAL X27A Q 001 04 Issue Date 01 04 18 Epson Research and Development Page 3 Vancouver Design Center Customer Support Information Comprehensive Support Tools Seiko Epson Corp provides to the system designer and computer OEM manufacturer a complete set of resources and tools for the development of graphics systems Evaluation Demonstration Board e Assembled and fully tested graphics evaluation board with installation guide and sche matics e To borrow an evaluation board please contact your local Seiko Epson Corp sales repre sentative Chip Documentation
176. FEO address of Revision Code Register mfspr rl IMMR get base address of internal registers andis ly PLENOS EFE clear lower 16 bits to 0 andis r2 r0 0 clear r2 oris r2 r2 MemStart write base address ori r2 r2 0801 port size 16 bits select GPCM enable stw r2 BR4 r1 write value to base register andis r2 r0 0 clear r2 oris r2 r2 ffc0 address mask use upper 10 bits ori r2 r2 0708 normal CS negation delay CS clock inhibit burst stw r2 OR4 r1 write to option register andis ELY 0 10 clear rl oris r1 r1 MemStart point rl to start of S1D13705 mem space lbz r0 RevCodeReg r1 read revision code into rl b Loop 7 branch forever Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 13 Epson Research and Development Page 21 Vancouver Design Center This code was entered into the memory of the MPC821ADS using the line by line assembler in MPC8BUG the debugger provided with the ADS board It was executed on the ADS and a logic analyzer was used to verify operation of the interface hardware Note MPC8BUG does not support comments or symbolic equates these have been added for clarity It is important to note that when the MPC821 comes out of reset its on chip caches and MMU are disabled If the data cache is enabled then the MMU must be set up so that the S1D13705 memory block is tagged as non cacheable to ensure that accesses to the S1D13705 will occur in proper order and
177. For example at one bit per pixel bpp only index positions O and 1 of the Look Up Table are used At 4 bpp the first 16 index positions of the Look Up Table are used and at 8 bpp all 256 Look Up Table index positions are used The Look Up Table mechanism itself consists of an index register and a data register The index or address register determines which element of the Look Up Table will be accessed After setting the index the LUT may be read or written through the data register The first data element read or written is the red component of the entry Subsequent read write operations access the green and then the blue elements of the Look Up Table The S1D13705 LUT architecture is designed to provide a high degree of similarity in operation to a standard VGA RAMDAC However there are two considerations which must be kept in mind e The S1D13705 Look Up Table has four bits 16 levels of intensity per primary color The standard VGA RAMDAC has six bits 64 levels This four to one difference must be taken into consideration when converting from a VGA palette to a LUT palette One suggestion is to divide the VGA intensity level by four to arrive at the LUT intensity However most applications specify the red green and blue components as eight bit intensities To determine the appropriate S1D13705 Look Up Table value we recom mend using the four most significant bits Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 00
178. Host Bus Interface Pin Mapping ei SH 3 SH 4 MC68K 1 MC68K 2 Generic Bus 1 Generic Bus 2 AB 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 A 16 1 ABO AO AO LDS AO AO AO DB 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 D 15 0 WE1 WE1 WE1 UDS DS WE1 BHE CS CSn CSn External Decode External Decode External Decode External Decode BCLK CKIO CKIO BCLK BCLK BCLK BCLK BS BS BS AS AS Connect to Vgs Connect to IO Vpp RD WR RD WR RD WR R W R W RD1 Connect to IO Vpp RD RD RD Connect to lO Vpp SIZ1 RDO RD WEO WEO WEO Connect to IO Vpp SIZO WEO WE WAIT WAIT RDY DTACK DSACK1 WAIT WAIT RESET RESET RESET RESET RESET RESET RESET S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual 1D13705 Issue Date 01 02 13 X27A G 005 03 Page 14 Epson Research and Development Vancouver Design Center 6 Technical Description 6 1 Embedded Memory Support S1D13705 X27A G 005 03 The S1D13705 contains 80K bytes of embedded 16 bit SRAM used for the display buffer and a 32 byte internal register set Since the S1D13705 does not distinguish between memory and register accesses both the 80K byte display buffer and the 32 byte register set must be memory mapped into the host s memory space When using the S3U13705B00C board on an ISA bus system the board can be configured to map the S1D137053 to one of two memory blocks The SRAM
179. Host Bus Interface Selection CNF2 CNF1 CNFO BS Host Bus Interface configuration for PC Card host bus interface 4 3 Register Memory Mapping The S1D13705 is a memory mapped device The S1D13705 memory may be addressed starting at 0000h or on consecutive 128K byte blocks and its internal registers are located in the upper 32 bytes of the 128K byte block i e REG O 1 FFEOh While the PC Card socket provides 64M bytes of memory address space the S1D13705 only needs a 128K byte block of memory to accommodate its 80K byte display buffer and its 32 byte register set For this reason only address bits A 16 0 are used while A 25 17 are ignored Because the entire 64M bytes of memory is available the S1D13705 s memory and registers will be aliased every 128K bytes for a total of 512 times Note If aliasing is not desirable the upper addresses must be fully decoded Interfacing to the PC Card Bus 1D13705 Issue Date 01 02 13 X27A G 009 02 Page 14 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13705CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and c
180. ISP_Y 2 define MAX _NON_DISP_Y 64 enum RED GREEN BLUE A NEEE IE AETA EN ee E typedef struct tagHalStruct char szIdString 16 WORD wDetectEndian WORD wSize BYTE Reg MAX_REG 1 DWORD dwC1kI Input Clock Frequency in kHz DWORD dwDispMem WORD wFrameRate HAL STRUCT typedef HAL STRUCT PHAL STRUCT ifdef INTEL_16BIT typedef HAL STRUCT far LPHAL STRUCT else typedef HAL STRUCT LPHAL STRUCT Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 80 Epson Research and Development Vancouver Design Center ndif JE RA FUNCTION PROTO TYPE el Initialization int seRegisterDevice const LPHAL STRUCT lpHalInfo int seSetInit void int seInitHal void Miscellaneous int seGetId int pld void seGetHalVersion const char pVersion const char pStatus const char pStatusRevision int seSetBitsPerPixel int nBitsPerPixel int seGetBitsPerPixel int pBitsPerPixel int seGetBytesPerScanline int pBytes int seGetScreenSize int width int height void seDelay int nMilliSeconds int seGetLastUsableByte long LastByte int seSetHighPerformance BOOL OnOff Advanced i int seSetHWRotate int nMode int seSplitInit W
181. IT8368E 16 Interfacing to the Philips MIPS PR31500 PR31700 Processor S1D13705 Issue Date 01 02 13 X27A G 012 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Philips MIPS PR31500 PR31700 Processor X27A G 012 02 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to interface the S1D13705 Embedded Memory LCD Controller and the Philips MIPS PR31500 PR31700 Processor The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor S1D13705 Issue Date 01 02 13 X27A G 012 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PR31500 PR31700 S1D13705 X27A G 012 02 The Philips MIPS PR31500 PR31700 processor supports up to two PC Card PCMCIA slots It is thro
182. JP4 LCD Panel Voltage Selection 5V LCD Panel 3 3V LCD Panel JP6 LCDPWR polarity Active low LCDPWR Active high LCDPWR S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 recommended settings JP1 through JP3 configured for ISA bus support S1D13705 X27A G 005 03 Page 10 3 LCD Interface Pin Mapping Table 3 1 LCD Signal Connector J5 Pinout Epson Research and Development Vancouver Design Center S1D13705 X27A G 005 03 1 Un used GPIO pins must be connected to IO Vpp 2 Inverse Video is enabled on FPDAT11 by REG 02h bit 1 Connector Single Passive Panel Dual Passive Panel Color TET D TFD Color Mono Color Mono Pin Name Pin i ob f i i 4 bit 8 bit Alternate 4 bit 8 bit 8 bit 8 bit 9 bit 12 bit Format BFPDATO 1 driven 0 DO LDO driven 0 DO DO LDO R2 R3 BFPDAT1 3 driven 0 D1 LD1 driven 0 D1 D1 LD1 R1 R2 BFPDAT2 5 driven 0 D2 LD2 driven 0 D2 D2 LD2 RO R1 BFPDAT3 7 driven 0 D3 LD3 driven 0 D3 D3 LD3 G2 G3 BFPDAT4 9 DO D4 UDO DO D4 D4 UDO G1 G2 BFPDAT5 11 D1 D5 UD1 D1 D5 D5 UD1 GO G1 BFPDAT6 13 D2 D6 UD2 D2 D6 D6 UD2 B2 B3 BFPDAT7 15 D3 D7 UD3 D3 D7 D7 UD3 B1 B2 BFPDAT8 17 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 GPIO1 BO B1 BFPDAT9 19 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 GPIO2 RO BFPDAT10 21 GPIO3 GPIO3 GPIO
183. KDJ and is typically driven by the host CPU system clock The address inputs ABO through AB 16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper IO or memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13705 RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13705 WAIT is a signal output from the 1D13705 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait s
184. Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 13 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the Motorola MCF5307 ColdFire Microprocessor Document Number X27A G 011 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X27A G 011 02 Issue Date 01 02 13 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 INTOUCHON s sa a a AR A A A A 7 2 Interfacing to
185. Modes 1 bpp color Page 17 When the 1D13705 is configured for 1 bpp color mode the LUT is limited to selecting colors from the first two entries The two LUT entries can be any two RGB values but are typically set to black and white Each byte in the display buffer contains eight adjacent pixels If a bit has a value of 0 then the color in LUT 0 index is displayed A bit value of 1 results in the color in LUT 1 index being displayed The following table shows the recommended values for obtaining a black and white mode while in 1 bpp on a color panel Table 4 1 Recommended LUT Values for 1 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 FO FO FO 02 00 00 00 ats 00 00 00 RE 00 00 00 unused entries Programming Notes and Examples Issue Date 02 01 22 S1D13705 X27A G 002 03 Page 18 S1D13705 X27A G 002 03 2 bpp color Epson Research and Development Vancouver Design Center When the 1D13705 is configured for 2 bpp color mode the displayed colors are selected from the first four entries of the Look Up Table The LUT entries may be set to any of the 4096 possible colors Each byte in the display buffer contains four adjacent pixels If a bit combination has a value of 00 then the color in LUT index 0 is displayed A bit value of 01 results in the color in LUT index 1 being displayed Likewise the bit combination of 10 displays from the
186. NE gt FPLINE be RD RD aay GB Display WEo gt WEO RDY WAIT LCDPWR ckIO gt BCLK RESET Pi RESET Figure 3 1 Typical System Diagram SH 4 Bus Oscillator x SH 3 d BUS CSn cs A 16 0 gt AB 16 0 D 15 0 DB 15 0 conan as LY FPSHIFT WE gt WE1 E i P SSE S1D13705 FPFRAME __ FPFRAME on PONY ad FPLINE gt FPLINE LOD RD P RD DAY uon Display WEO gt WEO WAIT WAIT h LCDPWR CkIO gt BCLK RESET Pi RESET 1D13705 X27A A 001 10 Figure 3 2 Typical System Diagram SH 3 Bus Hardware Functional Specification Issue Date 02 02 01 Issue Date 02 02 01 Epson Research and Development Page 13 Vancouver Design Center Oscillator MC68000 BUS A 23 17 lt FCO FC1 FC2 D Decoder C _ gt CS a A 16 1 AB 16 1 D 15 0 4 P DB 15 0 ona s FPSHIFT _ FPSHIFT LDS gt ABO 4 bit UDS p WEI S1 D1 3705 FPFRAME gt FPFRAME LCD Asy gt ase FPLINE _ FPLINE Display RH gt RDIWRE DRDY MOD DTACK lq WAITH LCDPWR CLK gt BCLK RESET P RESET Figure 3 3 Typical System Diagram M68K 1 Bus Oscillator MC68030 BUS FCO foes Decoder o CS x A 16 0 P AB 16 0 D 31 16 4 P DB 15 0 FPDAT 7 0 ott bee pl W
187. ODEO H located in x wince platform cepc drivers display S 1D 13705 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the driver If the default does not match the configuration you are building for then MODEO H will have to be regenerated with the correct informa tion Use the program 13705CFG to generate the header file For information on how to use 13705CFG refer to the 13705CFG Configuration Program User Manual document number X27A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13705 WinCE Drivers Save the new configuration as MODEO H in x wince platform cepc drivers display S 1D 13705 replacing the original configura tion file 10 Edit the file PLATFORM REG to match the screen resolution color depth bpp ac tive display LCD CRT TV and rotation information in MODE H PLAT FORM REG is located in x wince platform cepc files Windows CE 2 x Display Drivers 1D13705 Issue Date 01 06 07 X27A E 001 03 Page 6 Epson Research and Development Vancouver Design Center For example the display driver section of PLATFORM REG should be as follows when using a 320x240 LCD panel with a color depth of 8 bpp in SwivelView 0 landscape
188. ORD ScrnilAddr WORD Scrn2Addr int seSplitScreen int WhichScreen int VisibleScanlines int seVirtInit int xVirt long yVirt int seVirtMove int nWhichScreen int x int y Es Register Memory Access int seGetReg int index BYTE pValue int seSetReg int index BYTE value int seReadDisplayByte DWORD offset BYTE pByte int seReadDisplayWord DWORD offset WORD pWord int seReadDisplayDword DWORD offset DWORD pDword int seWriteDisplayBytes DWORD addr BYTE val DWORD count int seWriteDisplayWords DWORD addr WORD val DWORD count int seWriteDisplayDwords DWORD addr DWORD val DWORD count Power Sav int seHWSuspend int nDevID BOOL val int seSetPowerSaveMode int nDevID int PowerSaveMode Drawing int seDrawLine int xl int yl int x2 int y2 DWORD color int seDrawRect int xl int yl int x2 int y2 DWORD color BOOL Solidfill Color int seSetLut BYTE pLut int seGetLut BYTE pLut int seSetLutEntry int index BYTE pEntry int seGetLutEntry int index BYTE pEntry ndif HAL H_ 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Vancouver Design Center xk x k FA Page 81 APPCFG H Application configuration information Created 1998 Vancouver Design Centre Copyright c 1998 1999 Epson Research and Development All Rights Reserved Inc
189. P1 Horizontal Non Display Period 1 HNDP2 Horizontal Non Display Period 2 1D13705 X27A A 001 pan 0 REG O6h bits 1 0 REG O5h bits 7 0 1 Lines VNDP1 VNDP2 REG OAh bits 5 0 Lines REG 09h bits 5 0 Lines REG OAh bits 5 0 REG O9AN bits 5 0 Lines REG 04h bits 6 0 1 x 8Ts HNDP1 HNDP2 REG O8h 4 x 8Ts REG 07h bits4 0 x 8 16Ts REG 08h bits4 0 REG 07h bits 4 0 x 8 16Ts Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 53 Vancouver Design Center t9 4 gt Frame Pulse gt t12 Line Pulse W ti k t l aso DRDY i i me A NANNI at JE Note DRDY is used to indicate the first pixel Figure 7 26 TFT D TFD A C Timing Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 54 Epson Research and Development Vancouver Design Center Table 7 18 TFT D TFD A C Timing Symbol Parameter Min Typ Max Units t1 Shift Pulse period 1 note 1 t2 Shift Pulse pulse width high 0 5 Ts t3 Shift Pulse pulse width low 0 5 Ts t4 data setup to Shift Pulse falling edge 0 5 Ts t5 data hold from Shift Pulse falling edge 0 5 Ts t6 Line Pulse cycle time note 2 t7 Line Pulse pulse width low 9 Ts t8 Frame Pulse cycle time
190. P8 in the 2 3 position and adding a standard 14 DIP type oscillator in the socket U10 4 2 LCD Connectors 4 2 1 50 pin LCD Module Connector J3 X00A G 004 02 The standard connector used on Toshiba s CPU Modules to connect to the LCD module is included in this CPU module All twelve LCD data lines FPDAT 11 0 from the S1D13704 5 as well as the five video control signals FPFRAME FPSHIFT FPLINE DRDY LCDPWR are passed through this connector Through this connector the 1D13704 5 supports monochrome and color STN panels up to a resolution of 640x480 as well as color TFT D TFT up to a resolution of 640x480 All touch panel signals from the main board have also been routed through this connector S5U13704 5 TMPR3912 22U CPU Module Issue Date 01 03 07 EPSON Research and Development Page 13 Vancouver Design Center 4 2 2 Standard Epson LCD Connector J4 A shrouded 40 pin header J4 is also added to the CPU module to connect to LCD panels This header is the standard LCD connector used on Epson Research and Development evaluation boards and can be used to directly connect LCD panels to the S1D13704 5 controller All LCD signals are buffered to allow 3 3V or 5 0V logic LCD panels to be connected Jumper JP9 selects between these two types of panels A positive power supply for panels requiring a positive bias voltage is supplied to header J4 by the LCD module through the 50 pin LCD module connector J3 No negative power suppl
191. PC Card slot 1 memory space If the S1D13705 is used address lines A17 and above are ignored therefore the S1D13705 is aliased 512 times at 128K byte intervals The TMPR3912 22U control signal CARDREG is ignored therefore the S1D13704 also takes up the entire PC Card slot 1 configuration space Note If aliasing is undesirable additional decoding circuitry must be added 3 3 S1D13704 5 Configuration and Pin Mapping The S1D13704 5 host bus interface is configured at power up by latching the state of the CNF 3 0 pins Pin BS also plays a role in host bus interface configuration One additional configuration pin for the S1D13704 CNF4 is also used to set the polarity of the LCDPWR signal The table below shows the configuration pin connections to configure the S1D13704 5 for use with the TMPR3912 22U microprocessor Table 3 1 SID13704 5 Configuration for Generic 2 Bus Interface S1D13704 Value hard wired on this pin is used to configure Configuration Pin 1 10 Von 0 Vss Generic 1 Big Endian CNF 2 0 E configuration for Toshiba TMPR3912 22U host bus interface When the S1D13704 5 is configured for Generic 2 bus interface mode the host interface pins are mapped as in the table below Table 3 2 S1D13704 5 Generic 2 Interface Pin Mapping Pin Name Pin Function WE1 BHE BS Connect to lO Vpp RD WR Connect to lO Vpp RD RD WEO WE S5U13704 5
192. PC821 Chip Select Configuration 19 A Ter SObWware a GE Ay A ee AP Oe ee te eed See e 220 De DOnWAle a A Meee ek ee A 22 PIGIGIGNCES ara Sy AS ap al eed Symes ey aac ay whch at one Ba Aah a a Mac de Weds We E 23 6 1 DoechMents ar ecw a Se er ce A A A a at A a ie a QS 6 2 Document Sources tar Aea ee 23 T Technical SUDPOR i sis daa Se a ae AA ee E e Pal A Si ee 24 7 1 EPSON LCD CRT Controllers S1D13705 2 2 2 eee 24 7 2 Motorola MPC821 Processor 1 1 1 e A Interfacing to the Motorola MPC821 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 010 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Motorola MPC821 Microprocessor X27A G 010 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 13 Table 4 1 List of Connections from MPC821ADS to 1D13705 16 Table 4 2 Configuration Settings ee ee 18 Table 4 3 Host Bus Selection lt e e sae s aea 00 22 ee E a a e ale 18 List of Figures Figure 2 1 Power PC Memory Read Cycle nonoa a 9 Figure 2 2 Power PC Memory Write Cycle 0 002000000000 0008 10 Figure 4 1 Typical Implementation of MPC821 to S1D13705 Interface 15 Interfacing to the Motorola MPC821 Microprocessor S1D13705 Issue Date 01 02
193. PCIk When this bit 1 MCLK is fixed to the same frequency as PCLK for all bit per pixel modes This provides a faster screen update performance in 1 2 4 bit per pixel modes but also increases power consumption This bit can be set to 1 just before a major screen update then set back to O to save power after the update This bit has no effect in Swivel View mode Refer to REG 1Bh SwivelView Mode Register on page 67 for SwivelView mode clock selection S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Page 58 bit 4 bit 3 bit 2 bit 1 bit 0 S1D13705 X27A A 001 10 Epson Research and Development Vancouver Design Center Input Clock Divide When this bit 0 the Operating Clock CLK is the same as the Input Clock CLKI When this bit 1 CLK CLKI 2 In landscape mode PCLK CLK and MCLK is selected as per Table 8 3 High Perfor mance Selection In Swivel View mode MCLK and PCLK are derived from CLK as shown in Table 8 8 Selection of PCLK and MCLK in Swivel View Mode on page 68 Display Blank This bit blanks the display image When this bit 1 the display is blanked FPDAT lines to the panel are driven low When this bit 0 the display is enabled Frame Repeat EL support This feature is used to improve Frame Rate Modulation of EL panels When this bit 1 an internal frame counter runs from 0 to 3FFFFh When the frame counter rolls over the
194. RDWARE Click NEXT Select NO and click NEXT Select OTHER DEVICES from the HARDWARE TYPES list Click HAVE DISK Specify the location of the driver files and click OK Select the file SID13XXX INF and click OK Click OK The EPSON PCI Bridge Card should be selected in the list window Click NEXT Click NEXT Click Finish S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 EPSON 1D13705 Embedded Memory LCD Controller S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X27A G 005 03 Copyright 1999 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual X27A G 005 03 Issue Date 01 02 13 Epson Research and Development Vancouv
195. Repeat steps 1 and 2 for the remaining color depths 4 and 8 bit per pixel 4 Press lt ESC gt to exit the program 13705VIRT Display Utility S1D13705 Issue Date 01 02 12 X27A B 004 02 Page 6 Epson Research and Development Vancouver Design Center Program Messages S1D13705 X27A B 004 02 ERROR Did not find a 13705 device The HAL was unable to read the revision code register on the S1D13705 Ensure that the S1D13705 hardware is installed and that the hardware platform has been configured correctly Also check that the display memory address has been configured correctly ERROR Unable to locate load S1D13XXX VXD 13705PLAY was unable to load a required driver The file S1D13XXX VXD should be located in x WINDOWS SYSTEM or in x WINNT SYSTEM If the file is not there install it as described in the S1D13XXX 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 Xx ERROR An IOCTL error occurred This message indicates an error at the IO control layer occurred The usual cause for this is an incorrect hardware configuration ERROR The HAL returned an unknown error This message should never be displayed it indicates that 13705 VIRT is unable to determine the cause of an error returned from the HAL Unable to use virtual mode at xx BPP This message is displayed if there is insufficient display memory to show a complete virtual image Specifically the maximum number of lines for the image is ca
196. Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the PC Card Bus X27A G 009 02 Issue Date 01 02 13 Epson Research and Development Page 3 Vancouver Design Center Table of Contents T Introductions a 64 nar ELA AA AIDA AN AA A 7 2 Interfacing to the PC CardBus 8 2 1 The PC Card System Bus e 8 ZEE PC Card Overview se seu da sa e as Aye ia Gon 2 8 2 1 2 Memory Access Cycles o e 8 3 51D13705 Bus interface ica do ia ae wR ae d ace awa 10 3 1 Host Bus Pin Connection 2 2 10 3 2 Generic 2 Interface Mode 20 2 11 4 PC Card to S1D13705 Interface 0 00 eee 12 4 1 Hardware Connections 0 00
197. Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to an 8 bit Processor X27A G 015 01 Issue Date 01 12 20 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction alar TA a ara a Aa ada aa wn ar 7 2 Interfacing to an 8 bit Processor 8 2 1 The Generic 8 bit Processor System Bus 2 8 3 1D13705 Bus Interface 2 dad aa ee ae iw en ae E 9 3 1 Host Bus Pin Connection 2 2 0 O 3 2 Generic 2 Interface Mode e 10 4 8 Bit Processor to S1D13705 Interface lt lt eee 11 4 1 Hardware Description a aaa 11 4 2 S1D13705 Hardware Configuration 2 12 4 3 Register Memory Mapping a 05622 12 SoftWare 0 ot Sea aca A es bs hes emanates 13 Reterences 55 4 5 is bl io de dy o A ec es ee 14 6s Documents ia A ee Rk che bee a sw ce Sb a te a VA 62 Document Sources 0 00 2 2 eee ee ew ew ww 14 T Technical Support sera
198. SIZE VERSION is the size of the version string eg 1 00 SIZE STATUS is the size of the status string eg b for beta SIZE REVISION is the size of the status revision string eg 00 ies define SIZE_VERSION5 define SIZE_STATUS 2 define SIZE_REVISION3 ifdef ENABLE DPE Debug_printf define DPF exp printf exp n define DPFl exp printf exp d n exp define DPF2 expl exp2 printf expl d exp2 Sd n expl exp2 define DPFL exp printf exp x n exp ls define DPF exp void 0 define DPF1 exp void 0 define DPFL exp void 0 ndif Ai Ey enum S1D13705 X27A G 002 03 No error call was successful Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 79 Vancouver Design Center ERR_FAILED General purpose failure ERR_UNKNOWN_DEVICE LESS ERR_INVALID_PARAME ERR_HAL_BAD_ARG ERR_TOOMANY_DEVS y Akk kkk k kkk kk kkk kkk kk kkk RRA RARA RARA RRA k k k k H ER Function was called with invalid parameter Definitions for seGetId E A define PRODUCT_ID 0x24 enum ID_UNKNOWN ID_S1D13705_Revl y define MAX_MEM_ADDR81920 1 define EIGHTY_K81920 define MAX DEVICE 10 define SE _RSVD 0 KOK KKK KK KK RK I RR I I k k Definitions for Internal calculations ORR I A define MIN_NON_DISP_X 32 define MAX _NON_DISP_X 256 define MIN_NON_D
199. Sequencing 2 4 ye ee a a a Re we i a Be a oA a BD 6 2 Registers 5 e rt A AO eae a BD 6 3 LCD Enable Disable 2 2 2 2 36 7 Hardware Rotation 2 0 A eee ae een A da A a en 37 7 1 Introduction To Hardware Rotation 2 ee ee ee ee 37 7 2 Default Portrait Mode 2 a E ee 37 7 3 Alternate Portrait Mode 2 2 a a ee ee 39 TA SROSISUEES a lt gt aq He ck a shi A Gh AO et oS a et es e AO dude ammtationss a aopo pas GS Gee a a ae A a ow a ew ee 42 1 6 Exampless 2242 fb ithe A ae pd ee a A ab S Balog ae AS Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 4 Epson Research and Development Vancouver Design Center 8 Identifying the S1D13705 lt lt 47 9 Hardware Abstraction Layer HAL 48 9 1 Introduction SS a A te ote A AS 9 2 Contents of the HAL_STRUCT 48 9 3 Using the HAL library 2 2 2 o o AD 0 4 APT for IS 7OSHALD 0 ii Sc ae a AP ee we Bo e A ee AO 94 1 Inttralization dada a ted asa 51 9 42 General HAL Support 0 000 ee ee 52 9 4 3 Advanced HAL Functions e 55 9 44 Register Memory Access ee ee 58 OS Power Save 4 ase a a A aa a tas da Pea ks a 2 60 94 6 Drawn 3 2s ey ae a ee A ee ee tere BR es 61 9 48 LUT Manipulation see 0 6 acy a A FB A a
200. Size BYTE Regs MAX_REG 1 DWORD dwClkI Input Clock Frequency in kHz DWORD dwDispMem Starting address of display buffer memory WORD wFrameRate Desired panel frame rate HAL _STRUCT Within the Regs array ia a structure which defines all the registers described in the S1D13705 Hardware Functional Specification document number X27A A 001 xx Using the 13705CFG EXE utility you can adjust the content of the registers contained in HAL_STRUCT to allow for different LCD panel timing values and other default settings used by the HAL In the simplest case the program only calls a few basic HAL functions and the contents of the HAL_STRUCT are used to setup the S1D13705 for operation S1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 49 Vancouver Design Center 9 3 Using the HAL library To utilize the HAL library the programmer must include two h files in their code Hal h contains the HAL library function prototypes and structure definitions and appcfg h contains the instance of the HAL_STRUCT that is defined in Hal h and configured by 13705CFG EXE For a more thorough example of using the HAL see Section 10 1 Sample code using the S1D13705 HAL APT on page 66 Note Many of the HAL library functions have pointers as parameters The programmer should be aware that little validation of these pointers is performed so i
201. T divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13705 clock frequencies The S1D13705 also has internal clock dividers providing additional flexibility 4 2 Memory Mapping and Aliasing The S1D13705 requires an addressing space of 128K bytes The on chip display memory occupies the range O through 13FFFh The registers occupy the range 1FFEOh through 1FFFFh The PR31500 PR31700 demultiplexed address lines A17 and above are ignored thus the 1D13705 is aliased 512 times at 128K byte intervals over the 64M byte PC Card slot 1 memory space In this example implementation the PR31500 PR31700 control signal CARDREG is ignored therefore the S1D13705 also takes up the entire PC Card slot 1 configuration space Note If aliasing is undesirable additional decoding circuitry must be added Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13705 Issue Date 01 02 13 X27A G 012 02 Page 14 Epson Research and Development Vancouver Design Center 4 3 S1D13705 Configuration and Pin Mapping The S1D13705 is configured at power up by latching the state of the CNF 3 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx The table below shows those configuration settings relevant to the direct connection approach T
202. T8368E on page 15 For further information on the IT8368E refer to the IT8368E PC Card GPIO Buffer Chip Specification Note When a second IT8368E is used that circuit should not be set in VGA mode 5 3 Memory Mapping and Aliasing When the TMPR3912 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table 5 1 TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E Note Bit CARDIIOEN or CARD2IOEN depending on which card slot is used must to be set to 0 in the TMPR3912 Memory Configuration Register 3 When the TMPR3912 accesses the PC Card slots buffered through the ITE IT8368E bits CARD IIOEN and CARD2IOEN are ignored and the attribute IO space of the TMPR3912 is divided into Attribute I O and S1D13705 access Details of the Attribute IO address reallocation by the IT8368E are found in Table 5 1 TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E Table 5 1 TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E PC Card TMPR3912 F s Direct Connection Direct Connection Slot Address 9 Usingthe ITE ITS368E CARDnIOEN 0 CARDnIOEN 1 0800 0000h 16M byte Card 1 IO 1D13705 aliased 128 1D13705 0900 0000h 16M byte times aliased 512 times Card 1 lO 1 at 128K byte intervals at 128K byte intervals 0A00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory S1D13705 aliased 512 times
203. TMPR3912 Processor aa ee 19 dd TVEATS83608E gt ua oa sab da Go A oh es tak aus de Ge as Ge a Md ae ee od We or 19 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 004 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 9 Table 4 1 S1D13705 Configuration for Direct Connection o o 13 Table 5 1 TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E 16 Table 5 2 S1D13705 Configuration Using the IT8368E o o 17 List of Figures Figure 4 1 1D13705 to TMPR3912 Direct Connection o o 12 Figure 5 1 S1D13705 to TMPR3912 Connection Using an IT8368E 15 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 004 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware required to interfac
204. Tel 337 7911 Fax 334 2716 http www epson com sg Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Page 88 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 EPSON 1D13705 Embedded Memory LCD Controller Programming Notes and Examples Document Number X27A G 002 03 Copyright 2001 2002 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 Introduction dara cane a RA aa a a 7 2 InItdlizaliOn 0 A E A A AAA ALADO A 8 2 1 Display Buffer Location
205. Timing MC68030 a 31 Genere 1 Timing o oa aos a a Se Ee eS OS a Re a BO 32 Generic 2 Timing oe cs ek a e et be ee ea 33 Clock Input Requirements for CLKT o o e 34 Clock Input Requirements for BCEK o o e e 35 LCD Panel Power On Reset Timing e 36 Power Down Up Timing 37 Single Monochrome 4 Bit Panel Timing o 38 Single Monochrome 4 Bit Panel A C Timing 0 39 Single Monochrome 8 Bit Panel Timing o e 40 Single Monochrome 8 Bit Panel A C TiMid8 41 Single Color 4 Bit Panel Timing 2 2 e 42 Single Color 4 Bit Panel A C Timing 2 0 0 0 002 000 0000 43 Single Color 8 Bit Panel Timing Format l 44 Single Color 8 Bit Panel A C Timing Format1 45 Single Color 8 Bit Panel Timing Format 2 0000 46 Single Color 8 Bit Panel A C Timing Format2 47 Dual Monochrome 8 Bit Panel Timing o o 48 Dual Monochrome 8 Bit Panel A C TiMid8 o 49 Dual Color 8 Bit Panel TiMid8 e 50 Dual Color 8 Bit Panel A C TiMinB8 e 51 12 Bit TFI D TFD Panel Timing e 52 TET D TED AC Timings ce 4 nae ck Wid ao A A ROR a SS 53 Screen Register Relationship Split Screen oo o
206. Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 VDC Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft Windows and the Windows CE Logo are registered trademarks of Microsoft Corporation MEN X27A C 001 04 04 EPSON 1D13705 Embedded Memory LCD Controller Hardware Functional Specification Document Number X27A A 001 10 Copyright 1999 2002 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this
207. UT entry Unlike seSetLut the LUT entry indicated by Tndex can be any value from 0 to 255 A Look Up Table entry consists of three bytes one each for Red Green and Blue The color infor mation is stored in the four most significant bits of each byte Parameters Index index to LUT entry 0 to 255 pLUT pointer to an array of three bytes Return Value ERR_OK operation completed with no problems int seGetLutEntry int index BYTE pEntry Description This routine reads one LUT entry from any index A Look Up Table entry consists of three bytes one each for Red Green and Blue The color information is stored in the four most significant bits of each byte Parameters Index index to LUT entry 0 to 255 pEntry pointer to an array of three bytes Return Value ERR_OK operation completed with no problems Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 64 Epson Research and Development Vancouver Design Center 9 5 Porting LIBSE to a new target platform S1D13705 Building Epson Research and Development applications like a simple HelloApp for a new target platform requires 3 things the HelloApp code the 13705HAL library and a some standard C functions portable ones are encapsulated in our mini C library LIBSE HelloApp Source code HelloApp lt q C Library Functions LIBSE for embedded platforms 13705HAL Library Components needed to build 13705 HAL application
208. Vancouver Design Center 5 2 Pin Description Key CS COx TSx CNx TEST Input Output Bi Directional Input Output Power pin CMOS level input CMOS level Schmitt input CMOS output driver x denotes driver type see lo loy in Table 6 4 Output Specifications on page 25 Tri state CMOS output driver x denotes driver type see lo loy in Table 6 4 Output Specifications on page 25 CMOS low noise output driver x denotes driver type see lo loy in Table 6 4 Output Specifications on page 25 CMOS level test input with pull down resistor 5 2 1 Host Interface Pin Names Type Pin 4 Cell actly Description This pin has multiple functions a mode this pin inputs system address bit O For MC68K 1 this pin inputs the lower data strobe LDS ABO l 70 CS Input For MC68K 2 this pin inputs system address bit 0 AO For Generic 1 this pin inputs system address bit 0 AO For Generic 2 this pin inputs system address bit 0 AO See Table 5 2 Host Bus Interface Pin Mapping on page 22 for summary 45 53 54 55 56 57 AB 16 1 a a E C Input These pins input the system address bits 16 through 1 A 16 1 66 67 68 69 These pins have multiple functions e For SH 3 SH 4 mode these pins are connected to D15 0 34567 e For MC68K 1 these pins are connected to D 15 0 6 9 11 12 SS aor COU or Do a eon dos DB 15 0 IO 13 14 15 C TS2 H
209. View Mode would be 480x512 which requires 122 880 bytes Alternate Swivel View Mode requires a panel size of only 480x320 which needs only 76 800 bytes Alternate Swivel View Mode requires the Memory Clock MCLK to be at least twice the frequency of the Pixel Clock PCLK i e MCLK gt 2 x PCLK This makes the power consumption in Alternate Swivel View Mode higher than in Default Swivel View Mode while increasing performance The following figure shows how the programmer sees a 480x320 image and how the image is being displayed The application image is written to the S1D13705 in the following sense A B C D The display is refreshed by the S1D13705 in the following sense B D A C physical memory start ao dd address 4 A B E SwivelView a o window display gt 4 A start o E S address 5 3 lt O C D y 480 320 image seen by programmer image refreshed by S1D13705 image in display buffer Figure 12 2 Relationship Between The Screen Image and the Image Refreshed by S1D13705 in Alternate Mode Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Page 80 Epson Research and Development Vancouver Design Center 12 2 1 How to Set Up Alternate SwivelView Mode S1D13705 X27A A 001 10 The following describes the register settings needed to set up Alternate Swivel View Mode for a 320x480x4 bpp image Select Alternate Swivel View Mode REG 1B
210. a MC68K 2 Interface Timing Telk cik SE NA A NE A 16 0 CS VALID SIZO SIZ1 R W tl t2 AS DS A t3 lt 4 t5 gt t7 gt t4 t6 AR e j DSACK1 Hi J BLA 18 t9 D 31 16 Hi Z Hi Z write VALID t10 t11 D 31 16 Hi Z A Hi Z read VALID Figure 7 4 MC68K 2 Timing MC68030 Table 7 4 MC68K 2 Timing MC68030 Symbol Parameter Min Max Units folk Bus Clock frequency 33 MHz ToLk Bus Clock period ek t1 A 16 0 CS SIZO SIZ1 valid before ASH falling edge 0 ns t2 A 16 0 CS SIZO SIZ1 hold from AS DS rising edge 0 ns t3 AS low to DSACK1 driven high 22 ns t4 CLK to DSACK1 low 18 ns t5 CLK to AS DS high 1ToLk ns t6 AS high to DSACK1 high 20 ns t7 AS high to DSACK1 high impedance Tok t8 DS falling edge to D 31 16 valid write cycle TeiK 2 t9 AS DS rising edge to D 31 16 invalid write cycle 0 ns t10 D 31 16 valid to DSACK1 low read cycle 0 ns t11 ASH DS rising edge to D 31 16 high impedance 20 ns Note CLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 84 Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 32 Epson Research and Development Vancouver Design Center 7 1 5 Generic 1 Interface Timing
211. a power save mode is set the S1D13705 disables LCD power and the LCD logic signals continue for one hundred and twenty seven frames allowing the LCD power supply to completely discharge For most applications the internal power sequencing is the appropriate choice There may be situations where the internal time delay is insufficient to discharge the LCD power supply before the LCD signals are shut down or the delay is too long and the designer wishes to shorten it This section details the sequences to manually power up and power down the LCD interface REG 03h Mode Register 2 LCDPWR Hardware Software Software Override Power Save Power Save Power Save Enable bit 1 bit O Programming Notes and Examples Issue Date 02 01 22 The LCD Power LCDPWR Override bit forces LCD power inactive one frame after being toggled As long as this bit is 1 LCD power will be disabled The Hardware Power Save Enable bit must be set in order to activate hardware power save through GPIOO The Software Power Save bits set and reset the software power save mode These bits are set to 11 for normal operation and set to 00 for power save mode LCD logic signals to the display panel are active for 128 frames after setting either hardware or software power save modes Power sequencing override is performed by setting the LCDPWR Override bit some time before setting a power save mode for power off sequenc
212. a to the system memory on suspend This mode is used if display memory power is going to be turned off when the system is suspended and there is enough system memory to save the image Any off screen data in display memory is LOST when suspended Therefore off screen memory usage must either be disabled in the display driver i e EnablePreferVmem not defined in SOURCES file or new OEM specific code must be added to the display driver to save off screen data to system memory when the system is suspended and restored when resumed If off screen data is used provided that the OEM has provided code to save off screen data when the system suspends additional code must be added to the display driver s surface allocation routine to prevent the display driver from allocating the main memory save region in display memory When WinCE OS attempts to allocate a buffer to save the main display data WinCE OS marks the allocation request as preferring display memory We believe this is incorrect Code must be added to prevent this specific allocation from being allocated in display memory it MUST be allocated from system mem ory Since the main display data is copied to system memory on suspend and then simply copied back on resume this mode is FAST but not as fast as mode 0 PORepaint 2 This mode tells WinCE to not save the main display data on suspend and causes WinCE to REPAINT the main display on resume This mode is used if d
213. able 4 1 SIDI3705 Configuration for Direct Connection S1D13705 Value hard wired on this pin is used to configure Configuration Pin 1 10 Vpp 0 Vss Generic 1 Big Endian CNF 2 0 ESA configuration for Philips PR31500 PR31700 host bus interface S1D13705 Interfacing to the Philips MIPS PR31500 PR31700 Processor X27A G 012 02 Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center 5 Using the ITE IT8368E PC Card Buffer If the system designer uses the ITE IT8368E PC Card and multiple function I O buffer the S1D13705 can be interfaced so that it shares a PC Card slot The S1D13705 is mapped to ararely used 16M byte portion of the PC Card slot buffered by the IT8368E This makes the S1D13705 virtually transparent to PC Card devices that use the same slot 5 1 Hardware Description The ITE8368E has been specially designed to support EPSON LCD controllers The ITE IT8368E provides eleven Multi Function IO pins MFIO Configuration registers may be used to allow these MFIO pins to provide the control signals required to implement the S1D13705 CPU interface The PR31500 PR31700 processor only provides addresses A 12 0 therefore devices requiring more address space must use an external device to latch A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13705 Issue Dat
214. aced to the S1D13705 Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Generic 8 bit Bus 1D13705 A 0 _ e gt ABIO A 16 1 gt AB 16 1 D 7 0 1 DB 7 0 gt DB 15 8 Decoder _______ qs WAIT e WAIT WE gt WEO RD gt RD o gt BHE WE1 IO Vop RD WR BS BUSCLK BUSCLK System RESET gt RESET Figure 4 1 Typical Implementation of an 8 bit Processor to the SIDI3705 Generic 2 Interface Interfacing to an 8 bit Processor 1D13705 Issue Date 01 12 20 X27A G 015 01 Page 12 4 2 S1D13705 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13705 uses CNF4 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the 1D 3705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show only those configuration settings important to the 8 bit processor interface The endian must be selected based on the 8 bit processor used Table 4 1 Configuration Settings Signal Low High CNFO CNF1 See Host Bus Selection table belo
215. address lines to select the proper register and memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13705 RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13705 WAIT is a signal output from the 1D13705 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the 1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the 1D13705 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center 4 MCF5307 To S1D13705 Interface 4 1 Hardware Description The S1D13705 is interfaced to the MCF5307 with a minimal amount of glue logic One inverter is required to chang
216. age 5 Vancouver Design Center Installing the Driver The build step produces two library images e lib disputil nto x86 so libdisputil so e lib ffb nto x86 so libffb so For the loader to locate them the files need to be renamed and copied to the lib directory 1 Rename libdisputil so to libdisputil so 1 and libffb so to libffb so 1 2 Copy the files new files libdisputil so 1 and libffb so 1 to the directory usr lib 3 Copy the file devg S1D13705 so to the lib dll directory Note To locate the file devg S1D13705 so watch the output of the true command during the makefile build 4 Modify the trap file graphics modes in the etc system config directory by inserting the following lines at the top of the file io graphics dldevg S 1D 13705 so g320x240x8 I0 d0x0 0x0 320 240 8 Epson Run the Driver Note For the remaining steps the S5U13705B00C evaluation board must be installed on the test platform Note Because this is an ISA board a memory hole must be created in the 15 megabyte range This is done in the BIOS settings It is recommended that the driver be verified before starting QNX with the S1D13705 as the primary display To verify the driver 1 Copy the data file from the services graphics tests bench directory to the current di rectory Use test8 raw for 8 bpp QNX Photon v2 0 Display Driver 1D13705 Issue Date 01 09 10 X27A E 005 01 Page 6 Epson Research and Development Vancouver Design Center
217. age would normally require only 76 800 bytes possible within the 80K byte address space but the virtual image is 512x480x4bpp which needs 122 880 bytes not possible Does not require a virtual image Clock Requirements CLK need only be as fast as the required PCLK MCLK and hence CLK need to be 2x PCLK For example if the panel requires a 3MHz PCLK then CLK must be 6MHz Note that 25MHz is the maximum CLK so PCLK cannot be higher than 12 5MHz in this mode Power Consumption Lowest power consumption Higher than Default Mode Panning Vertical panning in 2 line increments Vertical panning in 1 line increments Performance Nominal performance Higher performance than Default Mode 12 4 SwivelView Mode Limitations The only limitation to using SwivelView mode on the S1D137095 is that split screen operation is not supported Hardware Functional Specification Issue Date 02 02 01 1D13705 X27A A 001 10 Page 82 Epson Research and Development Vancouver Design Center 13 Power Save Modes Two Power Save Modes have been incorporated into the S1D13705 to accommodate the need for power reduction in the hand held devices market These modes are enabled as follows Table 13 1 Power Save Mode Selection Hardware Power Software Power Software Power Save Save Bit 1 Save Bit 0 Not Configured or 0 Mode Software Power Save Mode Not Configured or 0 reserved
218. al RD e For MC68K 1 this pin must be tied to lO Vpp For MC68K 2 this pin inputs the bus size bit 1 SIZ1 For Generic 1 this pin inputs the read command for the lower data byte RDO e For Generic 2 this pin inputs the read command RD See Table 5 2 Host Bus Interface Pin Mapping on page 22 for summary WAIT TS2 Hi Z This pin has multiple functions For SH 3 mode this pin outputs the wait request signal WAIT For SH 4 mode this pin outputs the device ready signal RDY For MC68K 1 this pin outputs the data transfer acknowledge signal DTACK e For MC68K 2 this pin outputs the data transfer and size acknowledge bit 1 DSACK1 For Generic 1 this pin outputs the wait signal WAIT For Generic 2 this pin outputs the wait signal WAIT See Table 5 2 Host Bus Interface Pin Mapping on page 22 for summary RESET 73 CS Active low input to set all internal registers to the default state and to force all signals to their inactive states 5 2 2 LCD Interface Pin Name Type Pin Cell RESET State Description FPDATI7 0 O 30 31 32 33 34 35 36 37 CN3 Panel Data FPDAT 10 8 24 25 26 CN3 Input These pins have multiple functions Panel Data bits 10 8 for TFT D TFD panels e General Purpose Input Output pins GPIO 3 1 These pins should be connected to lO
219. als S1D1370 Flat Panel X27A C 001 04 MW DESCRIPTION Memory Interface Embedded 80K byte SRAM display buffer CPU Interface e Direct support for Hitachi SH 3 Hitachi SH 4 Motorola M68xxx MPU bus interface with programmable READY CPU write buffer Display Support 4 8 bit monochrome LCD interface 4 8 bit color LCD interface Single panel single drive passive displays Dual panel dual drive passive displays e Active matrix TFT D TFD interface Example resolutions 640x480 at a color depth of 2 bpp 640x240 at a color depth of 4 bpp 320x240 at a color depth of 8 bpp Clock Source Single clock input for both pixel and memory clocks e The S1D13705 clock source can be internally divided down for a higher frequency clock input Dynamic switching of memory clocks in portrait mode CONTACT YOUR SALES REPRESENTATIVE FOR THESE COMPREHENSIVE DESIGN TOOLS e S1D13705 Technical Manual e S5U13705 Evaluation Boards e Windows CE Display Driver e CPU Independent Software Utilities Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp North America Hong Kong Europe Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 Riesstrasse 15 Copyright 2001 Epson Researc
220. also to ensure that the MPC821 does not attempt to cache any data read from or written to the S1D13705 or its display buffer Interfacing to the Motorola MPC821 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 010 02 Page 22 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13705CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13705 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com S1D13705 Interfacing to the Motorola MPC821 Microprocessor X27A G 010 02 Issue Date 01 02 13 Epson Research and Development Page 23 Vancouver Design Center 6 References 6 1 Documents Motorola Inc Power PC MPC821 Portable Systems Microprocessor User s Manual Motorola Publication no MPC821UM AD available on the Internet at http www mot com SPS ADC pps _subpgs _documentation 821 821UM html Epson Research and Development Inc S1D 3705 Embedded Memory LCD Controller Hardware Functional Specification Document Number X27A A 002 xx Eps
221. anel types resolutions and color depths only by modifying the source The S1D13705 test utilities and display drivers are available from your sales support contact or on the internet at http www erd epson com Interfacing to an 8 bit Processor S1D13705 Issue Date 01 12 20 X27A G 015 01 Page 14 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents e Epson Research and Development Inc S D13705 Embedded Memory LCD Controller Hardware Functional Specification Document Number X27A A 002 xx e Epson Research and Development Inc S5UI13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X26A G 005 xx Epson Research and Development Inc S1D13705 Programming Notes and Examples Document Number X26A G 002 xx 6 2 Document Sources e Epson Reasearch and Development Website http www eea epson com S1D13705 Interfacing to an 8 bit Processor X27A G 015 01 Issue Date 01 12 20 Epson Research and Development Page 15 Vancouver Design Center 7 Technical Support 7 1 Epson LCD CRT Controllers S1D13705 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http www epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 http www epson com hk North America Epson Electronics
222. ardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 39 Vancouver Design Center tl t2 Sync Timing gt Frame Pulse 4 a t3 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t7 4 Shift Pulse FPDAT 7 4 Note For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 12 Single Monochrome 4 Bit Panel A C Timing Table 7 11 Single Monochrome 4 Bit Panel A C Timing Symbol Parameter Min Typ Max Units tl Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 4 Ts t10 Shift Pulse pulse width low 2 Ts t11 Shift Pulse pulse width high 2 Ts t12 FPDATT 7 4 setup to Shift Pulse falling edge 2 Ts t13 FPDATT 7 4 hold to Shift Pulse falling edge 2 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 tlmin t3min 9Ts 3 t3min REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t6min REG O8h bits 4 0 x 8 2
223. arting at index O seGetLut Read from the LUT starting at index 0 seSetLutEntry Write one LUT entry red green blue at the specified index seGetLutEntry Read one LUT entry red green blue from the specified index seSetBitsPerPixel Set the color depth seGetBitsPerPixel Determine the current color depth seSetPowerSaveMode seSetPixel Draw a pixel at x y in the specified color seGetPixel Read pixel s color at x y seDrawLine Draw a line from x1 y1 to x2 y2 in specified color seDrawRect Draw a rectangle from x1 y1 to x2 y2 in specified color Control S1D13705 SW power save mode enable disable S1D13705 X27A G 002 03 Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 51 Vancouver Design Center 9 4 1 Initialization The following section describes the HAL functions dealing with S1D13705 initialization Typically a programmer has only to concern themselves with calls to seRegisterDevice and seSetInit int seRegisterDevice const LPHAL_STRUC IpHallnfo Description This function registers the S1D13705 device parameters with the HAL library The device parameters include address range register values desired frame rate etc and are stored in the HAL_STRUCT structure pointed to by IpHalInfo Additionally this routine allocates system memory as address space for accessing registers and the display buffer Parameters IpHalInfo pointer to HAL_STRUCT info
224. at 128K byte intervals 1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Page 17 Vancouver Design Center Table 5 1 TMPR3912 to PC Card Slots Address Mapping With and Without the IT8368E PC Card TMPR3912 Direct Connection Direct Connection Slot Address 57 ming the tie Tiadesr CARDnIOEN 0 CARDnIOEN 1 0C00 0000h 16M byte Card 2 lO S1D13705 aliased 128 S1D13705 0D00 0000h 16M byte times aliased 512 times Card 2 lO 2 at 128K byte intervals at 128K byte intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory S1D13705 aliased 512 times at 128K byte intervals 5 4 S1D13705 Configuration The S1D13705 is configured at power up by latching the state of the CNF 3 0 pins Pin BS also plays a role in host bus interface configuration For details on configuration refer to the 1D13705 Hardware Functional Specification document number X26A A 001 xx The table below shows those configuration settings relevant to this specific interface Table 5 2 SIDI3705 Configuration Using the ITS368E CNF 2 0 S1D13705 Value hard wired on this pin is used to configure Configuration Pin 1 10 Vpp 0 Vss BS Generic 2 CNF3 Big Endian SS sz configuration for connection using ITE IT8368E Interfacing to the Toshiba MIPS TMPR3912 Microp
225. at http www erd epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at documentation Oerd epson com Interfacing to an 8 bit Processor S1D13705 Issue Date 01 12 20 X27A G 015 01 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to an 8 bit Processor 2 1 The Generic 8 bit Processor System Bus S1D13705 X27A G 015 01 Although the 1D13705 does not directly support an 8 bit CPU with minimal external logic an 8 bit interface can be achieved Typically the bus of an 8 bit microprocessor is straight forward with minimal CPU and system control signals To connect a memory mapped device such as the 1D13705 only the write read and wait control signals as well as the data and address lines need to be interfaced Since the 1D13705 is a 16 bit device some external logic is required Interfacing to an 8 bit Processor Issue Date 01 12 20 Epson Research and Development Page 9 Vancouver Design Center 3 S1D13705 Bus Interface This section is a summary of the host bus interface modes available on the S1D13705 and offers some detail on the Generic 2 Host Bus Interface used to implement the interface to an 8 bit processor The S1D13705 provides a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microproc
226. aying a series of images 1 override default configuration settings and set landscape display mode p override default configuration settings and set portrait display mode noinit bypass the register initialization and use the current setup use this option to override changes that take place to the timing registers displays the Help screen e 13705BMP currently views only Windows BMP format images 13705BMP Demonstration Program 1D13705 Issue Date 01 02 12 X27A B 006 03 Page 4 Epson Research and Development Vancouver Design Center Program Messages S1D13705 X27A B 006 03 ERROR Did not find an S1D13705 device The HAL was unable to locate an 1D13705 at the configured address Check that the correct physical address was configured into 13705BMP EXE ERROR Unable to locate load S1D13XXX VXD The file S1D13XXX VXD is required by the 32 bit version of the 13705BMP Check that the VXD file is in c WINDOWS SYSTEM If the file is not there install it as described in the SID13XXX 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 xx ERROR An IOCTL error occurred The device driver SIDI3XXX VXD was unable to assign memory Check that the PC hardware is configured correctly and that 13705BMP has been configured with the correct memory location ERROR The HAL returned an unknown error This error message should never bee seen Contact ERD ERROR Could not initialize device The HAL
227. ber of words to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or if Addr plus Count is greater than 80 kb Note There are slight functionality differences between the S1D1370x and the S1D1350x HAL Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 60 9 4 5 Power Save S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center int seWriteDisplayDwords DWORD Offset DWORD Value DWORD Count Description Writes one or more DWORDS to the display buffer at the offset specified by Addr If a count greater than one is specified all DWORDSs will have the same value Parameters Offset offset from start of the display buffer Value DWORD value to write Count number of dwords to write Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr or if Addr plus Count is greater than 80 kb Note There are slight functionality differences between the S1D1370x and the S1D1350x HAL This section covers the HAL functions dealing with the Power Save features of the S1D13705 int seSetPowerSaveMode int PwrSaveMode Description This function sets on the S1D13705 s software selectable power save modes Parameters PwrSaveMode integer value specifying the desired power save mode Acceptable values for PwrSaveMode are 0 software power save mode in this mode registers and memo
228. bit 1 1 0 0 reserved 1 1 0 1 reserved 1 1 1 Generic 2 16 bit a configuration for MC68EZ328 using Generic 1 host bus interface 3 4 3 MC68EZ328 Chip Select Configuration 1D13705 X27A G 007 04 The S1D13705 requires a 128K byte address space for the display buffer and its internal registers To accommodate this block size it is preferable but not required to use one of the chip selects from groups A or B Groups A and B can have a size range of 128K bytes to 16M bytes and groups C and D have a size range of 32K bytes to 16M bytes Therefore any chip select other than CSAO would be suitable for the S1D13705 interface In the example interface chip select CSBO is used to control the S1D13705 A 128K byte address space is used with the S1D13705 control registers mapped into the top 32 bytes of the 128K byte block and the 80K bytes of display buffer mapped to the starting address of the block The chip select should have its RO Read Only bit set to 0 its BSW Bus Data Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Page 21 Vancouver Design Center Width set to 1 for a 16 bit bus and the WS Wait states bit should be set to 111b to allow the S1D13705 to terminate bus cycles externally with DTACK Enable DTACK pin function with Register FFFFF433 Port G Select Register bit 0 Interfacing to the Motorola Dragonball Family of Microp
229. cant bits form the product revision From reset power on the steps to identifying the S1D13705 are as follows 1 Read REG OOh Mask off the lower two bits the revision code to obtain the product code 2 The product code for the S1D137053 is 024h Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 48 Epson Research and Development Vancouver Design Center 9 Hardware Abstraction Layer HAL 9 1 Introduction The HAL is a processor independent programming library provided by Epson The HAL was developed to aid the implementation of internal test programs and provides an easy consistent method of programming the S1D13705 on different processor platforms The HAL also allows for easier porting of programs between S1D1370X products Integral to the HAL is an information structure HAL_STRUCT that contains configuration data on clocks display modes and default register values This structure combined with the utility 13705CFG EXE allows quick customization of a program for a new target display or environment Using the HAL keeps sample code simpler although some programmers may find the HAL functions to be limited in their scope and may wish to program the S1D13705 without using the HAL 9 2 Contents of the HAL_STRUCT The HAL_STRUCT below is contained in the file hal h and is required to use the HAL library typedef struct tagHalStruct char szIdString 16 WORD wDetectEndian WORD w
230. ce300 platform cepc drivers display dirs and add S1D13705 into the list of directories Edit the file x wince300 platform cepc files platform bib and make the following two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13X0X ddi dil _FLATRELEASEDIR S1D13X0X dll NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_FLAT IF CEPC_DDI_S1D13X0X Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGA8BPP IF CEPC_DDI_S3TRIO64 IF CEPC_DDI_ATI ddi dil _FLATRELEASEDIR ddi_flat dll NK SH 1D13705 X27A E 006 01 Page 8 S1D13705 X27A E 006 01 Epson Research and Development Vancouver Design Center ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF Insert this line ENDIF Modify MODE0 H The file MODEO H located in x wince300 platform cepc drivers display S 1D13705 contains the register values required to set the screen resolution color depth bpp display type display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the display driver If the default does not match the configura tion you are building for then MODEO H will have to be regenerated with the correct information Use the program 13705CFG to generate the header file For information on how to use 13705CFG refer to the 13705CFG Configuration Program User Manual document number X27A
231. ch is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13705 Supported Evaluation Platforms 13705VIRT has been tested with the following S1D13705 supported evaluation platforms e PC system with an x86 processor e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13705 Programming Notes and Examples manual document number X26A G 002 xx 13705VIRT Display Utility S1D13705 Issue Date 01 02 12 X27A B 004 02 Page 4 Epson Research and Development Vancouver Design Center Installation Usage S1D13705 PC Intel Platform For 16 Bit Program Version copy the file 13705 VIRT EXE to a directory that is in the DOS path on your hard drive For 32 Bit Program Version install the 32 bit Windows device driver S1D13X0X VXD as described in the S1ID13X0X 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 xx Copy the file 13705 VIRT EXE to a directory that is in the DOS path on your hard drive Embedded Platform Download the program 13705VIRT to the system PC platform at the prompt type 13705virt a 11 p alt w Embedded platform execute 13705virt and at the prompt type the comma
232. ckio Bus Clock frequency 50 MHz Tokio Bus Clock period Yckio t2 Bus Clock pulse width low 8 ns t3 Bus Clock pulse width high 8 ns t4 A 16 0 RD WR setup to CKIO 0 ns t5 A 16 0 RD WR hold from CS 0 ns t6 BS setup 5 ns t7 BS hold 5 ns 18 CSn setup 0 ns t9 Falling edge RD to DB 15 0 driven 25 ns t10 CKIO to WE RD high 1 5Tckio t11 Rising edge CSn to RDY high impedance Tokio t12 Falling edge CSn to RDY driven 20 ns t13 CKIO to RDY low 20 ns t14 Rising edge CSn to RDY high 16 ns t15 DB 15 0 setup to 2 CKIO after BS write cycle ns t16 DB 15 0 hold write cycle ns t17 RDY falling edge to DB 15 0 valid read cycle ns t18 Rising edge RD to DB 15 0 high impedance read cycle 10 ns Note CKIO may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 84 Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Page 28 Epson Research and Development Vancouver Design Center 7 1 2 SH 3 Interface Timing Tokio t2 13 a CKIO E t4 t5 gt gt A 16 0 M R RD WR A t6 t7 gt gt gt BS t8 gt CSn t9 p t10 o S a WEn RD t12 t13 e gt WAIT Hi Z Hi Z t14 t15 gt gt D 15 0 Hi Z Hi Z write t16 t17 D 15 0 E Hi Z Hi Z read VALID Figure 7 2 SH 3 Bus Timing Note Th
233. claims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705CFG Configuration Program X27A B 001 03 Issue Date 02 03 11 Epson Research and Development Page 3 Vancouver Design Center Table of Contents WSTOSGRG z n Shinde a A A A A A A sy aes 5 S1D13705 Supported Evaluation Platforms z5 Installation 6 Usage te iy SP wat Ves eed 6 13705CFG Configuration Tabs Bh i E oa ee ee ae eR de tok ee General Tap cok maa ee eth e GE cae Ae alae Putas e bee eaters MS 7 Preferences Tabi a urea Baa die are A bare Sate bar A ek 9 Clocks Labs coa e ices a eee ca sh ee ee Pac E fete ae Beata a aaa 10 Panel Tabs sehen tee ree hee denen Beg es ah shite ee act Sek es Gece opt aos ed elt ted ects a a it 12 Panel Power Tabi sandu tie tl As eed Se Ba o 16 Registers Tabia m 8 be Pb be Qa hee be A a AAS ES 17 13705CFG Menus de 22 ue en A Mh ee ok eee eh ee Ae oe re en Weed te ee de ES OPC ear A eh tae GS os ak Coot ee aia a Se Mie da 18 DAVES hace een cose eee eed A ee agen tise es ta A a a 19 DAVE
234. configured and or compiled to work with your hardware platform The program 13705CFG EXE can be used to configure 13705SHOW Consult the 13705CFG users guide document number X27A B 001 xx for more infor mation on configuring S1D13705 utilities This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications The PC uses a terminal program to send control commands and infor mation to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13705 Supported Evaluation Platforms 13705SHOW has been tested with the following S1D13705 supported evaluation platforms e PC system with an x86 processor Both 16 bit and 32 bit code is supported e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13705 Programming Notes and Examples manual document number X26A G 002 xx 13705SHOW Demonstration Program 1D13705 Issue Date 01 02 12 X27A B 002 02 Page 4 Installat
235. connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MPC821 to S1D13705 Interface Interfacing to the Motorola MPC821 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 010 02 Page 16 4 2 MPC821ADS Evaluation Board Hardware Connections S1D13705 X27A G 010 02 Epson Research and Development Vancouver Design Center The following table details the connections between the pins and signals of the MPC821 and the S1D137095 Table 4 1 List of Connections from MPC821ADS to SIDI3705 MPC821 Signal Name MPC821ADS Connector and Pin Name 1D13705 Signal Name Vcc P6 A1 P6 B1 Vcc A15 P6 D20 A16 A16 P6 B24 A15 A17 P6 C24 A14 A18 P6 D23 A13 A19 P6 D22 A12 A20 P6 D19 A11 A21 P6 A19 A10 A22 P6 D28 A9 A23 P6 A28 A8 A24 P6 C27 A7 A25 P6 A26 A6 A26 P6 C26 A5 A27 P6 A25 A4 A28 P6 D26 A3 A29 P6 B25 A2 A30 P6 B19 Al A31 P6 D17 AO DO P12 A9 D15 D1 P12 C9 D14 D2 P12 D9 D13 D3 P12 A8 D12 D4 P12 B8 D11 D5 P12 D8 D10 D6 P12 B7 D9 D7 P12 C7 D8 D8 P12 A15 D7 D9 P12 C15 D6 D10 P12 D15 D5 D11 P12 A14 D4 D12 P12 B14 D3 D13 P12 D14 D2 D14 P12 B13 D1 D15 P12 C13 DO SRESET P9 D15 RESET SYSCLK P9 C2
236. creen 2 will not be shown In landscape mode these registers form the word offset to the first byte in display memory to be displayed Changing these registers by one will shift the display image 2 to 16 pixels depending on the current color depth The S1D13705 does not support split screen operation in portrait mode Screen 2 will never be used if portrait mode is selected Refer to Table 5 1 Number of Pixels Panned Using Start Address to see the minimum number of pixels affected by a change of one to these registers Screen 1 Start Address registers REG OC REG OD and REG 10 are discussed in Section 5 2 1 on page 28 1D13705 X27A G 002 03 Page 34 5 3 2 Examples S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center Example 5 Display 200 scanlines of image 1 and 40 scanlines of image 2 Image 2 is located first offset 0 in the display buffer followed immediately by im age 1 Assume a 320x240 display and a color depth of 4 bpp 1 Calculate the Screen 1Vertical Size register values vertical_size 200 C8h Write the Vertical Size LSB REG 12h with C8h and Vertical Size MSB REG 13h with a 00h 2 Calculate the Screen 1 Start Word Address register values Screen 2 is located first in display memory therefore we must calculate the number of bytes taken up by the screen 2 data bytes_per_line pixels_per_line pixels_per_byte 320 2 160 total bytes bytes_per_line x li
237. cted then an exact duplicate of the file as opened by the Open option is created containing the new configuration information 13705CFG Configuration Program 1D13705 Issue Date 02 03 11 X27A B 001 03 Page 20 Epson Research and Development Vancouver Design Center Configure Multiple S1D13705 After determining the desired configuration Configure Multiple allows the information to be saved into one or more executable files built with the HAL library From the Menu Bar select File then Configure Multiple to display the Configure Multiple Dialog Box This dialog box is also displayed when a file s is dragged onto the 13705CFG window Configure Multiple Ed Select files to configure Selected files 13705bmp exe i Add gt 13705cfg exe 13705play exe Add All gt gt 1370Sshow exe lt Remove 13705splt exe 13705virt exe lt lt Remove All l a Show all files C Show cont D i files only yy i jii l C 4 1D13705 Close IT Preserve physical addresses The left pane lists files available for configuration the right pane lists files that have been selected for configuration Files can be selected by clicking the Add or Add All buttons double clicking any file in the left pane or by dragging the file s from Windows Explorer Selecting Show all files displays all files in the selected directory whereas selecting Show conf files
238. ctly to IO Vpp or Vss 10 es This pin has multiple functions see REG 0O3h bit 2 GPIOO i 22 181 Input General Purpose Input Output pin Hardware Power Save TESTEN 44 TEST pulled low Test Enable input This input must be connected to Vss 5 2 5 Power Supply Pin Name Type Pin Driver Description COREVDD P 1 a ats P Core Vpp IOVDD P 10 29 52 P IO Vop 20 27 40 VSS P 50 60 72 P Common Vss 80 Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Page 22 5 3 Summary of Configuration Options Epson Research and Development Vancouver Design Center Table 5 1 Summary of Power On Reset Options Configuration Pin Power On Reset State CNF 3 0 Select host bus interface as follows CNF3 CNF2 2d ld dd dd dl ss 4 COODOOOOOO CNF1 CNFO BS 222222000 0000 2222001201 x0u1 x00 X X X X X X X X X X 0 1 0 0 1 1 Host Bus SH 4 interface Big Endian SH 4 interface Little Endian SH 3 interface Big Endian SH 3 interface Little Endian reserved MC68K 1 16 bit Big Endian reserved reserved MC68K 2 16 bit Big Endian reserved reserved reserved Generic 1 16 bit Big Endian Generic 1 16 bit Little Endian reserved Generic 2 16 bit Little Endian 5 4 Host Bus Interface Pin Mapping Table 5 2 Host Bus Interface Pin Mapping Ae e SH 3
239. current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Power Consumption X27A G 006 02 Issue Date 01 02 13 Epson Research and Development Page 3 Vancouver Design Center 1 S1D13705 Power Consumption Power Consumption Issue Date 01 02 13 S1D13705 power consumption is affected by many system design variables Input clock frequency CLKTI the CLKI frequency and the internal clock divide register deter mine the operating clock CLK frequency of the 1D13705 The higher CLK is the higher the frame fate performance and power consumption CPU interface the S1D13705 current consumption depends on the BUSCLK frequency data width number of toggling pins and other factors the higher the BUSCLK the higher the CPU performance and power consumption Vpp Voltage levels Core and IO the voltage level of the Core and IO sections in the S1D13705 affects power consumption the higher the voltage the higher the consumption Display mode the resolution panel type and color depth affect power consumption The higher the resolution color depth and number of LCD panel signals the higher the power consumption Note If the Hig
240. d Buffer 2 0000 2 eee eee 15 5 1 Hardware Description 2 2 ee eee LS 5 2 TT8368E Contiguration cos eo aS To an ea es OE ee es ee a ee ae VT 5 3 Memory Mapping and Aliasing 17 5 4 1D13705 Configuration 2 2 eee 18 Software s a aa 5 dr oti Aaa eh Se a Sar ated 19 Technical Support eile ck Sole Oe SS ee ele he Ee ew ed GS 20 7 1 EPSON LCD Controllers S1D13705 2 2 2 ee ee 20 7 2 Philips MIPS PR31500 PR31700 Processor 2 ee ee 20 dad TTEATS8368E o 23 a6 6 8 a go Gp te a ay a Go es ge ae ae Me ds eee a ee Bo a S20 Interfacing to the Philips MIPS PR31500 PR31700 Processor 1D13705 Issue Date 01 02 13 X27A G 012 02 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Philips MIPS PR31500 PR31700 Processor X27A G 012 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 3 1 Host Bus Interface Pin Mapping e 9 Table 4 1 S1D13705 Configuration for Direct Connection o o 14 Table 5 1 PR31500 PR31700 to PC Card Slots Address Mapping With and Without the IT8368E 17 Table 5 2 S1D13705 Configuration Using the IT8368E oo o 18 List of Figures Figure 4 1 S1D13705 to PR31500 PR31700 Direct Connection o a 12 Figure 5 1 S1D13705 to PR31500 PR31700 Connection Using an
241. d Development Vancouver Design Center 10 Display Data Formats 1 bpp bit 7 bit O PoP4P2P3P4P5 Pe P7 Panel Display Host Address Display Memory 2 bpp bit 7 bit O PoP P2P3P4Ps P6 P7 Panel Display Host Address Display Memory PoP4 P2 P3P4P5 Pe P7 Ph An Br Cr Dn Panel Display Host Address Display Memory PoP4 P2 P3P4P5Pe P7 Ph An Br Cr Dr En Fm Gn Hn Panel Display Host Address Display Memory Figure 10 1 1 2 4 8 Bit Per Pixel Display Data Memory Organization S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 71 Vancouver Design Center 11 Look Up Table Architecture The following figures are intended to show the display data output path only Note When Video Data Invert is enabled the video data is inverted after the Look Up Table 11 1 Monochrome Modes The green Look Up Table LUT is used for all monochrome modes 1 Bit per pixel Monochrome mode Green Look Up Table 256x4 00 lo 4 bit Gray Data 01 02 de eee 1 bit per pixel data from Display Buffer unused Look Up Table entries Figure 11 1 1 Bit per pixel Monochrome Mode Data Output Path 2 Bit per pixel Monochrome Mode Green Look Up Table 256x4
242. d VNDP from a desired frame rate for int loop 0 loop lt 2 loop for VNDP 2 VNDP lt 0x3F VNDP 3 Solve for HNDP HNDP PCLK FrameRate VDP VNDP HDP if HNDP gt 32 amp amp HNDP lt 280 Solve for VNDP VNDP PCLK FrameRate HDP HNDP VDP If we have satisfied VNDP then we re don if VNDP gt 0 amp amp VNDP lt 0x3F goto DoneCalc Divide C1k1 and try again Reg 02 allows us to dived CLKI by 2 PCLK 2 If we still can t hit the frame rat throw an error if VNDP lt 0 VNDP gt 0x3F HNDP lt 32 HNDP gt 280 sprintf ERROR Unable to set the desired frame rate n exit 1 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 11 Vancouver Design Center This routine first performs a formula rearrangement so that HNDP or VNDP can be solved Start with VNDP set to a small value Loop increasing VNDP and solving the equation for HNDP until satisfactory HNDP and VNDP values are found If no satisfactory values are found then divide CLKI and repeat the process If a satisfactory frame rate still can t be reached return an error Note Most passive STN panels are tolerant of nearly any combination of HNDP and VNDP values however panel specifications generally specify only a few lines of vertical non display period The 1D13705 is capable
243. d ee Ge ed tual een e amp 15 4 1 3 Sequence Controller s s se o YG Se Bd Be ek eee te ek 15 ATA Look Up Table ccoo cd he ere ye ee a eB Be Be OS 16 AAS ECD untertace hos dd ee aah ok ate hee eb a ee ate ted a ean ns choo ah een a 16 416 SPOWEF SAVE Cu Bote eR DM ected Deiat ei iat de at ee eh wae 16 54 PINS a ae Grit oe ee A ARA AO A RR BO AA Bee Ree Sky A 17 5 1 Pmout Diagram oi Ae ae a e a a oh ee ee eo a 17 5 2 Pim Description Babe fee ea a ee A ed a ae ee A oe Ea te TB Dize de HOSt Int rface ina he ah ee RAY SA hae WA Rk oie et 18 52 2 LCD Interface eae a Bae BA OR A eh RA had eae ea 20 9 23 Clock Input ici oe eure Soeur Seine be eae Bees fed ale oe eS 21 S24 sMascellaneous oca laa heen a hye as ok a a Se a ee 21 5 2 9 POWER Supply to AA pears Bae aad A Bebe BOA 21 5 3 Summary of Configuration Options 2 2 2 ee ee ee 22 5 4 Host Bus Interface Pin Mapping 22 5 5 LCD Interface Pin Mapping o 23 DG Characteristics iiss ise a AAS ae SGA ee as Ta 24 AC Characteristhe ss sii a we E A ea ar a a 26 7 1 Bus Interface Timing 2 2 0 26 TAD SHA Interface Timing asso us og ak a eA Ae Be ee dee 26 1 1 2 SH 3 Interface Timing eses a RA ee ela 28 7 1 3 Motorola MC68K 1 Interface Timing 30 7 1 4 Motorola MC68K 2 Interface Timing e 31 Hardware Functional Specification S1D13705 Issue Dat
244. def DWORD far LPDWORD else typedef BYTE LPBYTE typedef WORD LPWORD typedef UINT LPUINT typedef DWORD LPDWORD endif ifndef LOBYTE define LOBYTE w BYTE w endif ifndef HIBYTE define HIBYTE w BYTE UINT w gt gt 8 amp OXFF endif ifndef LOWORD define LOWORD 1 WORD DWORD 1 endif ifndef HIWORD define HIWORD 1 WORD DWORD 1 gt gt 16 amp OXFFFF endif ifndef MAKEWORD define MAKEWORD lo hi WORD WORD 10 WORD hi lt lt 8 endif ifndef MAKELONG Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 78 Epson Research and Development Vancouver Design Center define MAKELONG lo hi long WORD lo DWORD WORD hi lt lt 16 ndif ifndef TRUE defin RUE 1 ndif ifndef FALSE define FALSE 0 ndif define OFF 0 define ON 1 define SCREEN1 1 define SCREEN22 Constants for HW rotate support E defin DEFAULTO define LANDSCAPE 1 define PORTRAIT2 ifndef NULL ifdef _ cplusplus define NULL 0 ls define NULL void 0 ndif ndif T3 y
245. dify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Windows6 CE 2 x Display Drivers X27A E 001 03 Issue Date 01 06 07 Epson Research and Development Page 3 Vancouver Design Center WINDOWS CE 2 x DISPLAY DRIVERS The Windows CE display driver is designed to support the S1D13705 Embedded Memory LCD Controller running under the Microsoft Windows CE 2 x operating system The driver 1s capable of 4 and 8 bit per pixel landscape modes no rotation and 4 and 8 bit per pixel SwivelView 270 degree mode This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Windows CE 2 x Display Drivers 1D13
246. difying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13705 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com S1D13705 Interfacing to the Motorola MCF5307 ColdFire Microprocessor X27A G 011 02 Issue Date 01 02 13 Epson Research and Development Page 17 Vancouver Design Center 6 References 6 1 Documents Motorola Inc MCF5307 ColdFire Integrated Microprocessor User s Manual Motorola Publication no MCF5307UM AD available on the Internet at http www mot com SPS HPESD prod coldfire 5307UM html Epson Research and Development Inc S1D13705 Hardware Functional Specification Document Number X27A A 002 xx Epson Research and Development Inc S5UI3705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X27A G 005 xx Epson Research and Development Inc 1D13705 Programming Notes and Examples Document Number X27A G 002 xx 6 2 Document Sources e Motorola Inc Motorola Literature Distribution Center 800 441 2447 e Motorola website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13705 Issue Date 01 02 13 X27A G 01 1 02 Page 18 7 Technical Support 7 1 EPSON LCD Controllers S1D
247. dr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG 10h Screen 1 Display Start Address 2 MSB Start Addr n a n a n a n a n a n a n a Bit 16 Screen 1 Start Address Registers These three registers form the seventeen bit screen 1 start address Screen 1 is displayed starting at the top left corner of the display In landscape mode these registers form the word offset to the first byte in display memory to be displayed in the upper left corner of the screen Changing these registers by one will shift the display image 2 to 16 pixels depending on the current color depth In portrait mode these registers form the offset to the display memory byte where screen 1 will start displaying Changing these registers in portrait mode will result in a shift of 1 to 8 pixels depending on the color depth Refer to Table 5 1 Number of Pixels Panned Using Start Address to see the minimum number of pixels affected by a change of one to these registers Table 5 1 Number of Pixels Panned Using Start Address Color Depth BPP Pixelsiper Word PE Psigpecded Pixels Per Byte te de ane 1 16 16 8 8 2 8 8 4 4 4 4 4 2 2 8 2 2 1 1 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 29 Vancouver Design Center 5 2 2 Examples
248. dress mask register to activate the chip select for a subset of the group s address block Finally each chip select may be individually programmed to control an 8 or 16 bit device and each may be individually programmed to generate from 0 through 6 wait states internally or allow the memory or allow the memory or peripheral device to terminate the cycle externally through use of the standard MC68000 DTACK signal Groups A and B are used to control ROM SRAM and Flash memory devices and have a block size of 128K bytes to 16M bytes Chip select AO is active immediately after reset and is a global chip select so it is typically used to control a boot EPROM device This chip Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Page 17 Vancouver Design Center select ceases to decode globally once this chip select s registers are programmed Groups C and D are special in that they can also control DRAM interfaces These last two groups have block size of 32K bytes to 4M bytes 3 3 S1D13705 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13705 that may be used to interface to the MC68EZ328 The 1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The interface mode that may be used for the MC68EZ328
249. driven by the host CPU system clock If the host CPU bus does not provide this clock an asynchronous clock can be provided e The address inputs ABO through AB 16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively Note In an 8 bit environment D 7 0 must also be connected to DB 15 8 respectively i e D7 connects to both DB15 and DB7 D6 connects to both DB14 and DB6 D5 connects to both DB13 and DBS etc See Figure 4 1 Typical Implementation of an 8 bit Proces sor to the S1D13705 Generic 2 Interface Chip Select CS is driven by decoding the high order address lines to select the proper memory address space BHE WE1 is the high byte enable for both read and write cycles Note In an 8 bit environment this signal is driven by inverting address line AO thus indicating that odd addresses are to be R W on the high byte of the data bus WEO is the enable signal for a write access to be driven low when the host CPU is writing the 1375 memory or registers RD is the read enable for the S1D13705 to be driven low when the host CPU is reading data from the 1D 13705 WAIT is a signal which is output from the S1D13705 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13703 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1375 int
250. dth Panel data width is the number of bits of data transferred to the LCD panel on each clock cycle and shouldn t be confused with color depth which determines the number of displayed colors When the panel type is STN the available options are 4 and 8 bit When an active panel type is selected the available options are 9 and 12 bit Selects between a monochrome or color panel When selected causes the signal FPSHIFT to be masked When color or TFT panel is selected this option is disabled Selects between single or dual panel When the panel type is TFT Single is automatically selected and the Dual option is greyed out These settings define the polarity of the FPLINE and FPFRAME pulses Selects the polarity of the FPLINE pulse Refer to the panel specification for the correct polarity of the FPLINE pulse Selects the polarity of the FPFRAME pulse Refer to the panel specification for the correct polarity of the FPFRAME pulse 1D13705 X27A B 001 03 Page 14 Panel Dimensions Non Display Periods Timings Frame Rate Pixel Clock TFT FPLINE Start Pos S1D13705 X27A B 001 03 Epson Research and Development Vancouver Design Center These fields specify the panel width and height A number of common widths and height are available in the selection boxes If the width height of your panel is not listed enter the actual panel dimensions into the edit field Manually entered pixel widths mu
251. e Hardware Functional Specification Issue Date 02 02 01 1D13705 X27A A 001 10 Page 64 Epson Research and Development Vancouver Design Center REG 11h Memory Address Offset Register Address 1FFF1h Read Write Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Bit 7 Offset Bit 6 Offset Bit 5 Offset Bit 4 Offset Bit 3 Offset Bit 2 Offset Bit 1 Offset Bit 0 bits 7 0 Memory Address Offset Bits 7 0 Landscape Modes Only This register is used to create a virtual image by setting a word offset between the last address of one line and the first address of the following line If this register is not equal to zero then a virtual image is formed The displayed image is a window into the larger vir tual image See Figure 8 1 Screen Register Relationship Split Screen on page 65 This register has no effect in SwivelView modes See REG 1Ch Line Byte Count Regis ter for Swivel View Mode on page 68 REG 12h Screen 1 Vertical Size Register LSB Address 1FFF2h Read Write Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Screen 1 Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Vertical Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 13h Screen 1 Vertical Size Register MSB Add
252. e 01 02 13 X27A G 012 02 Page 16 Epson Research and Development Vancouver Design Center S1D13705 3 3V PR31500 PR31700 IO Vpp CORE Vpp HA 12 0 gt AB 12 0 ENDIAN 1 AB 16 13 HD 31 24 gt DB 7 0 HD 23 16 l gt DB 15 8 System RESET gt RESET Voo pull up CARDXWAIT 4 4 WAIT DCLKOUT See text ob gt CLKI IT8368E gt Clock divider P Oscillator gt BCLK LHA 23 MFIO 10 gt WE1 LHA 22 MFIO 9 WEO LHA 21 MFIO 8 gt RD WR LHA 20 MFIO 7 gt RDA LHA 19 MFIO 6 gt CS LHA 16 13 MFIO 3 0 pSt Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 5 1 S1ID13705 to PR31500 PR31700 Connection Using an IT8368E Note See Section 3 1 on page 9 and Section 3 2 on page 10 for Generic 1 pin descriptions The Generic 1 host interface control signals of the S1D13705 are asynchronous with respect to the S1D13705 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and fram
253. e 02 02 01 X27A A 001 10 Page 4 10 11 12 13 14 15 7 1 5 7 1 6 Generic 2 Interface TiMiNg 7 2 Clock Input Requirements 7 3 Display Interface 7 3 1 R32 7 3 3 7 3 4 7 3 5 7 3 6 7 3 7 7 3 8 7 3 9 Power Down Up Timing Single Monochrome 4 Bit Panel Timing Single Monochrome 8 Bit Panel Timing Single Color 4 Bit Panel Timing Single Color 8 Bit Panel Timing Format 1 Single Color 8 Bit Panel Timing Format 2 Dual Color 8 Bit Panel Timing Registers 8 1 Register Mapping 8 2 Register Descriptions Frame Rate Calculation Display Data Formats Look Up Table Architecture 11 1 Monochrome Modes 11 2 Color Modes SwivelView 12 1 Default Swivel View Mode 12 1 1 How to Set Up Default SwivelView Mode 12 2 Alternate SwivelView Mode 12 2 1 How to Set Up Alternate SwivelView Mode 12 3 Comparison Between Default and Alternate Swivel View Modes 12 4 SwivelView Mode Limitations Power Save Modes 00 00 ee eee eee nee 13 1 Software Power Save Mode 13 2 Hardware Power Save Mode 13 3 Power Save Mode Function Summary 13 4 Panel Power Up Down Sequence 13 5 Turning Off BCLK Between Accesses 13 6 Clock Requirements Mechanical Data Sales and Technical Support S1D13705 X27A A 001 10 Generic 1 Interface Timing Power On Reset Timing Dual Monochrome 8 Bit Panel Timing
254. e 1D13705 internal register set The S1D13705 registers are mapped into the upper 32 bytes of the 128K byte segment 1 FFEOh to 1FFFFh When using the S5U13705BO0C board on a non ISA bus system system or external decode logic must map the S1D13705 into an appropriate memory space S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center 6 2 ISA Bus Support The S5U13705B00C board has been designed to directly support the 16 bit ISA bus environment and can be used in conjunction with either a VGA or a monochrome display adapter card There are 4 configuration inputs associated with the Host Interface CNF 2 0 and BS Refer to Table 2 3 Jumper Settings on page 9 and Table 5 1 Host Bus Interface Pin Mapping on page 13 for complete details 6 2 1 Display Adapter Card Support When using the S5U13705BO0C in conjunction with another primary Display Adapter VGA or Monochrome the following applies VGA Display Adapter All VGA display adapters can be used with the S5U13705B00C board if the S1D13705 is mapped to the upper 1M Byte of ISA bus memory address F00000 F1FFFF If the S1D13705 is mapped to the address range 0CO000 0D0000 then no VGA or VGA compatible display adapters can be used with the S5U13705B00C board See Embedded Memory Support on page 14 Monochrome Display Adapter The S5U13705BO0C board can be used with monochr
255. e it is possible that contention may occur in accessing the 13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the S1D13705 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to the NEC VR4102 VR4111 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 008 02 Page 12 Epson Research and Development Vancouver Design Center 4 VR4102 VR4111 to S1D13705 Interface 4 1 Hardware Description The NEC VR4102 VR4111 Microprocessor is specifically designed to support an external LCD controller by providing the internal address decoding and control signals necessary By using the Generic 2 interface no glue logic is required to interface the S1D13705 and the NEC VR4102 VR4111 A pull up resistor is attached to WAIT to speed up its rise time when terminating a cycle The following diagram shows a typical implementation of the VR4102 VR4111 to S1D13705 interface NEC VR4102 VR4111 S1D13705 WR WEOH SHB gt WE1 RD gt RD LCDCS CS Pull up To LCDRDY WAIT S
256. e 8 Bit Panel Timing VDP Vertical Display Period VNDP Vertical Non Display Period HDP Horizontal Display Period HNDP Horizontal Non Display Period S1D13705 X27A A 001 10 REG 06h bits 1 0 REG O5h bits 7 0 1 Lines REG OAh bits 5 0 Lines REG 04h bits 6 0 1 x 8Ts REG 08h 4 x 8Ts Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 49 Vancouver Design Center Sync Timing u 2 a Frame Pulse 4 13 ss Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 4 t8 gt 4 t9 gt t7 t14 t11 t10 4 gt gt lt __ gt _ gt Shift Pulse t2 t13 2 x FPDAT 7 0 Note For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 22 Dual Monochrome 8 Bit Panel A C Timing Table 7 16 Dual Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse falling edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 5 t7 Shift Pulse falling edge to Line Pulse falling edge note 6 t8 Line Pulse falling edge to Shift Pulse falling edge t14 2 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse pu
257. e NK BIN file is built the CEPC environment can be started by booting either from a floppy or hard drive configured with a Windows 9x operating system The two methods are described below 1 To start CEPC after booting from a floppy drive a Create a bootable floppy disk b Edit CONFIG SYS on the floppy disk to contain only the following line device a himem sys c Edit AUTOEXEC BAT on the floppy disk to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy LOADCEPC EXE and HIMEM SYS to the bootable floppy disk Search for the loadCEPC utility in your Windows CE directories e Copy NK BIN to c f Boot the system from the bootable floppy disk 2 To start CEPC after booting from a hard drive a Copy LOADCEPC EXE to CA Search for the loadCEPC utility in your Windows CE directories b Edit CONFIG SYS on the hard drive to contain only the following line device c himem sys c Edit AUTOEXEC BAT on the hard drive to contain the following lines mode com1 9600 n 8 1 loadcepc B 9600 C 1 c nk bin d Copy NK BIN and HIMEM SYS to c e Boot the system S1D13705 Windows CE 2 x Display Drivers X27A E 001 03 Issue Date 01 06 07 Epson Research and Development Page 11 Vancouver Design Center Configuration There are several issues to consider when configuring the display driver The issues cover debugging support register initialization values and memory allocation Each of th
258. e Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705VIRT Display Utility X27A B 004 02 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center 13705VIRT 13705VIRT demonstrates the virtual display capability of the S1D13705 A virtual display is where the image to be displayed is larger than the physical display device The display surface is used a viewing window The entire image can be seen only by panning and scrolling The 13705VIRT display utility must be configured and or compiled to work with your hardware platform The program 13705CFG EXE can be used to configure 13705VIRT Consult the 13705CFG users guide document number X27A B 001 xx for more infor mation on configuring S1D13705 utilities This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications The PC uses a terminal program to send control commands and infor mation to the target processor Alternatively the PC can program an EPROM whi
259. e SH 3 Wait State Control Register for the area in which the S1D13705 resides must be set to a non zero value 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Table 7 2 SH 3 Bus Timing Page 29 Symbol Parameter Min Max Units fcxio Bus Clock frequency 50 MHz Tokio Bus Clock period 1 fckio t2 Bus Clock pulse width low 8 ns t3 Bus Clock pulse width high 8 ns t4 A 16 0 RD WR setup to CKIO 0 ns t5 A 16 0 RD WR hold from CS 0 ns t6 BS setup 5 ns t7 BS hold 5 ns 18 CSn setup 0 ns t9 Falling edge RD to DB 15 0 driven 25 ns t10 CKIO to WEn RD high 1 5Tckio t11 Rising edge CSn to WAIT high impedance 10 ns t12 Falling edge CSn to WAIT driven 15 ns t13 CKIO to WAIT delay 20 ns t14 DB 15 0 setup to 2 CKIO after BS write cycle ns t15 DB 15 0 hold from rising edge of WEn write cycle ns t16 WAIT rising edge to DB 15 0 valid read cycle 6 ns t17 Rising edge RD to DB 15 0 high impedance read cycle 10 ns 2 One Software WAIT State Required Note CKIO may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 84 Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Epson Research and Development Page 30 Vancouver Design Center 7 1 3 Motorola MC68K 1 Inter
260. e Technical manual includes Data Sheet Application Notes and Programmer s Refer ence Software OEM Utilities e User Utilities e Evaluation Software e To obtain these programs contact Application Engineering Support Application Engineering Support Engineering and Sales Support is provided by Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 TECHNICAL MANUAL Issue Date 01 04 18 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13705 X27A Q 001 04 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 TECHNICAL MANUAL X27A Q 001 04 Issue Date 01 04 18 EPSON amp GRAPHICS February 200
261. e Vss 0 V IO Vpp gt Core Vpp 2 7 3 0 3 3 5 0 5 5 V Vin Input Voltage Vss IO Vpp V Topr Operating Temperature 40 25 85 C Table 6 3 Input Specifications Symbol Parameter Condition Min Typ Max Units Low Level Input Voltage IO Vog 3 0 08 Vi CMOS inputs oe 0 8 y 5 0 1 0 High Level Input Voltage OMpp 20 19 Vil CMOS inputs 2 AN 5 0 3 5 Positive going Threshold Dado ee ae Vr CMOS Schmitt inputs oS 1 Ad y p 5 0 2 0 4 0 Negative going Threshold SM 0 9 Ka VT CMOS Schmitt inputs ae oe ha y 5 0 0 8 3 1 Vop Max liz Input Leakage Current Vin Vop 1 1 uA Vil Vss Cin Input Pin Capacitance 10 pF S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 25 Vancouver Design Center Table 6 4 Output Specifications Symbol Parameter Condition Min Typ Max Units IO Vpp 3 0V lo 3 0V Low Level Output Current Vo 0 4V Type A ES mA 3 10 IO Vpp 3 3V lol 3 3V Low Level Output Current Vo 0 4V Type a E mA 3 12 IO Vpp 5 0V lo 5 0V Low Level Output Current Vo 0 4V Type z E mA 3 12 IO Vpp 3 0V lon 3 0V High Level Output Current Vo IO Vpp 0 4V Type A Me mA 3 10 IO Vop 3 3V lop 3 3V High Level Output Current Vo IO Vpp 0 4V Type A i mA 3 12 IO Vop 5 0V lop 5 0V High Level Output Current Vo IO Vpp 0 4V Type 5 is mA 3 12 VoL Low Level Output Voltage l loL 0
262. e cae brite 9 MY U83341 Sseuppe OJ Y3LS1934 31v8 GOW usolo34 9 4q zoloay 4 ua zolo3u s uq Loloay apon erdsig 018 9XId 19d 1E L UE lexldved wa OUOMA IOJOD voyesedo euon L L oud ena vua sia eju sn s dsiq RET o 7 uog99 S PON 10 00 PLYS LI poua d ejds g uoy eoma A UON HOA Kow aw ejds p jo Bujuuj6eq y 0 enpejes ese sassalppe Ol Z MY UV3331 SSSIppe O Y31SIO3H 0OIW3d AVIASIO NON 14911834 yvOJO38 panasal L 0 Jasa UO Jamod Je GOZELGLS ay nuep 0 pasn ase sq aseyl FORO SAPS 48M Od 0 0 SSN eug vig gua it Ai PON 0 Hg anes 1 MOd L 18 SAS JIMO4 og Lua zua ena y 18 sua 918 48g UO ISOJ HEJS SPA HS UONDIJ9S PON SARS 1 MOd 9 junog ag aun MY U63441 SSSIPpe O NOLLISOd L8VIS 3NV84d4 460 93H ME Y04441 SSSIPpe Ol HaLSIO3H LNNOD ILAG ANIT 4911938 Jld JION x x l Lug zug eug exid 18d 1q 8 ADA MON L oud Lua eg SPON uy SPoWN p 934 8 Poney Ae dsiq UON ejuozuoH L 19942 Id MAIAJOAIMS ponasa eN EM da MOIAJ9AIMS MOJAJSAIMS My 483444 SS9JPpe O doldad AV1dSIG NON IVINOZIHOH yg0 93H lexiduedug y ZMIDA MON 0 18S HT WAIN 0 YygW331 ssauppe O Y31SI93H 3GOW M3IATSAIMS ua pay exid 19d 1q Z plod MON L o Mu lia Zu ell y 18 1 d i eju lexiduedid 8ANOd NOM o 018 hug zug eug vug gug 918 Zug 2 luzoJo38 e uon sod Wels aud guqtzoloay ua zoloau JoysiBay Ped yole1os MY 423444 SSOJPPE O NOILISOd LUVIS aNITd4 uz0193Y sepoyy ejdsig oud Lua suewop d YBIH 7 9XId
263. e color in the green LUT 0 index is displayed A bit value of 1 results in the color in green LUT 1 index being displayed The following table shows the recommended values 1 bpp gray shade display mode Table 4 5 Recommended LUT Values for 1 Bpp Gray Shade Address Red Green Blue 00 00 00 00 01 00 FO 00 02 00 00 00 wi 00 00 00 EP 00 00 00 unused entries 2 bpp gray shade When the S1D13705 is configured for 2 bpp gray shade the displayed colors are selected from the first four green entries in the Look Up Table The remaining entries of the LUT are unused Each of the four entries can be set to any of the sixteen possible colors Each byte in the display buffer contains four adjacent pixels If a bit combination has a value of 00 then the intensity in the green LUT index 0 is displayed A bit value of 01 results in the intensity represented by the green in LUT index 1 being displayed Likewise the bit combination of 10 displays from the third LUT entry and 11 displays a from the fourth LUT entry Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Vancouver Design Center Page 23 The following table shows the example values for 2 bit per pixel display mode Table 4 6 Suggested Values for 2 Bpp Gray Shade Index Red Green Blue 0 00 00 00 1 00 50 00 2 00 AO 00 3 00 FO 00 4 00 00 00 ae 00 00 00 FF
264. e cycle externally through use of the standard MC68000 DTACK signal Groups A and B can have a minimum block size of 64K bytes so these are typically used to control memory devices Chip select AO is active immediately after reset so it is typically used to control a boot EPROM device Groups C and D have a minimum block size of 4K bytes so they are well suited to controlling peripheral devices Chip select D3 is associated with the MC68328 on chip PCMCIA control logic Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Vancouver Design Center 2 3 S1D13705 Host Bus Interface Page 9 This section is a summary of the host bus interface modes available on the S1D13705 that may be used to interface to the MC68328 The S 1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The two interface modes that may be used for the MC68328 are e Motorola MC68K 1 using Upper Data Strobe Lower Data Strobe e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte 2 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 2 1 Host Bus Interface Pin Mapping eli MC68K 1 Generic 1 AB 15 1 A 15 1 A 15 1 ABO LDS AO
265. e differs from the ver sion 13705CFG expects the Open will fail and an error message is displayed This may happen if the version of 13705CFG is substantially older or newer than the file being opened 13705CFG Configuration Program Issue Date 02 03 11 Epson Research and Development Page 19 Vancouver Design Center Save From the Menu Bar select File then Save to initiate the save action The Save menu option allows a fast save of the configuration information to a file that was opened with the Open menu option Note This option is only available once a file has been opened Note 13705cfg exe can be configured by making a copy of the file 13705cfg exe and config uring the copy It is not possible to configure the original while it is running Save As From the Menu Bar select File then Save As to display the Save As Dialog Box Save s RES Save in Y 51013705 z e gal ex 13705bmp exe 13705cfg exe 13705play exe 13705show exe 13705splt exe 13705virt exe File name 13705ctg exe Save as type EXE Files y Cancel Z Save as is very similar to Save except a dialog box is displayed allowing the user to name the file before saving Using this technique a tester can configure a number of files differing only in configuration information and name e g BMP60Hz EXE BMP72Hz EXE BMP75Hz EXE where only the frame rate changes in each of these files Note When Save As is sele
266. e exe in your path run nmake fmakesh3 mk 9 5 2 Building the HAL library for the target example Building the HAL for the target example is less complex because the code is written in C and requires little platform specific adjustment The nmake makefile for our example is makesh3 mk This makefile contains the rules for building sh3 objects the files list for the library and the library creation rules The Gnu compiler tools are pointed to by TOOLDIR With nmake in your path run nmake fmakesh3 mk Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 66 Epson Research and Development Vancouver Design Center 10 Sample Code Included in the sample code section are two examples of programing the S1D13705 The first sample uses the HAL to draw a red square wait for user input then rotates to portrait mode and draws a blue square The second sample code performs the same procedures but directly accesses the registers of the S1D13705 These code samples are for example purposes only 10 1 Sample code using the S1D13705 HAL API Kk SAMPLE1 C Sample code demonstrating a program using the S1D13705 HAL Created 1998 Vancouver Design Centre Copyright c 1998 1999 Epson Research and Development Inc All Rights Reserved The HAL API code is configured for the following 320x240 Single Color 4 bit STN 8 bpp 70 Hz Frame Rate 6 MHz CLKi High Performance
267. e following diagram demonstrates a typical implementation of the interface S1D13705 3 3V PR31500 PR31700 t_ IO Vpp CORE Vpp CARDIOREAD gt RD CARDIOWR gt WEO CARD1CSL CARD1CSH WE1 3 3V BS 3 3V ___ RD WR ENDIAN System RESET RESET Latch ALE gt CS A 12 0 gt AB 16 13 AB 12 0 D 31 24 4 gt DB 7 0 D 23 16 gt DB 15 8 VoD pull up CARD1WAIT WAIT DCLKOUT See text gt CLKI gt Glock divider gt 9f Oscillator BCLK Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states 1D13705 X27A G 012 02 Figure 4 1 S1D13705 to PR31500 PR31700 Direct Connection Note See Section 3 1 on page 9 and Section 3 3 on page 11 for Generic 2 pin descriptions Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center The Generic 2 host interface control signals of the S1D13705 are asynchronous with respect to the S1D13705 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOU
268. e is used 4 1 5 LCD Interface The LCD Interface performs frame rate modulation for passive LCD panels It also generates the correct data format and timing control signals for various LCD and TFT D TFD panels 4 1 6 Power Save Power Save contains the power save mode circuitry 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Vancouver Design Center 5 Pins 5 1 Pinout Diagram Page 17 6d 59 58 57 56l 59 54 53 52 51 50 49 49 a7 49 45 44 49 42 41 lt Z DDDDODDOSOS ro OoO lt 0Q0Q0Q0Q0 RFP 327 00 ELE 2222 NODO o o n praes 3 do4328 iw m lt x 0 61 O 40 COREVDD vss Ea 2 ABs FPFRAME 683 7 FPLINE 28 e FPDATO 5 aps FPDAT1 has 86 apy FPDAT2 gt A AB3 FPDAT3 ape FPDAT4 lt 69 32 Fo AB1 FPDAT5 ETE ABO FPDAT6 Fan 7 71 30 77 BCLK S1D13705 FPDAT7 gt o Epa PVDD og 74 RESET FPSHIFT 5 CS VSS EN 5 Bs FPDAT8 gt 8 aoe FPDAT9 2 7 WEO FPDATIO 24 wet FPDATI1 23_ 2 epwre aPioo 22 80 21 VSS og COREVDD Og mg lt PROURRIRROUZDUUUUUUUOS 073222234 20YU17000000000 Oo 0OND4A0DDNDND 0000J3O0O0_RA0Vv 0O0 E E la E e 7 E E hofia 12 1 14 15 16 17 14 19 20 Figure 5 1 Pinout Diagram Note Package type 80 pin surface mount QFP14 Hardware Functional Specification Issue Date 02 02 01 1D13705 X27A A 001 10 Page 18 Epson Research and Development
269. e last access before shutting BCLK off Allow one BCLK pulse after starting up BCLK before the next access Required Look Up Table Register Read Write Is required during LUT register accesses BCLK can be shut down between accesses allow eight BCLK pulses plus 12 MCLK pulses 8TecLk 12 Tuck after the last access before shutting BCLK off Allow one BCLK pulse after starting up BCLK before the next access Not Required Software Power Save Required Can be stopped after 128 frames from entering Software Power Save i e after REG 03h bits 1 0 11 Hardware Power Save Not Required Can be stopped after 128 frames from entering Hardware Power Save Hardware Functional Specification Issue Date 02 02 01 1D13705 X27A A 001 10 Page 86 14 Mechanical Data Epson Research and Development Vancouver Design Center QFP14 80 pin 61 80 0 05 0 025 0 125 posta 14 0 04 Unit mm 12020 60 41 Index 40 12 0 01 14 0 04 21
270. e rate when setting portrait mode Other factors which can cause a failure include having a 0 Hz frame rate or specifying a value other than LANDSCAPE or PORTRAIT for the rotation scheme Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 56 S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center int seSplitInit WORD Scrn1Addr WORD Scrn2Addr Description Parameters Return Value Note This function prepares the system for split screen operation In order for split screen to function the starting address in the display buffer for the upper portion screen 1 and the lower portion screen 2 must be specified Screen 1 is always displayed above screen 2 on the display regardless of the location of their start addresses ScrnlAddr offset in bytes to the start of screen 1 Sern2Addr offset in bytes to the start of screen 2 ERR_OK operation completed with no problems It is assumed that the system has been initialized prior to calling seSplitInitO int seSplitScreen int Screen int VisibleScanlines Description Parameters Return Value Note Changes the relevant registers to adjust the split screen according to the number of visible lines requested WhichScreen determines which screen 1 or 2 to base the changes on The smallest surface screen can display is one line This is due to the way the 1D13705 operates Setting Screen 1 Vertical S
271. e rates e power budget e part count e maximum S1D13705 clock frequencies The S1D13705 also has internal clock dividers providing additional flexibility S1D13705 Interfacing to the Philips MIPS PR31500 PR31700 Processor X27A G 012 02 Issue Date 01 02 13 Epson Research and Development Page 17 Vancouver Design Center 5 2 IT8368E Configuration The IT8368E provides eleven multi function IO pins MFIO The IT8368E must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the S1D13705 host bus interface and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13705 When accessing the S1D13705 the associated card side signals are disabled in order to avoid any conflicts For mapping details refer to section 3 3 Memory Mapping and Aliasing For connection details see Figure 5 1 S1D13705 to PR31500 PR31700 Connection Using an IT8368E on page 16 For further information on the IT8368E refer to the JT8368E PC Card GPIO Buffer Chip Specification Note When a second IT8368E is used that circuit should not be set in VGA mode 5 3 Memory Mapping and Aliasing When the PR31500 PR31700 accesses the PC Card slots without the ITE IT8368E its system memory is mapped as in Table 5 1 PR31500 PR31700 to PC Card Slots Address Mapping With and Without the IT8368E Note Bit CARDIIOEN or CARD2IOEN dep
272. e the S1D13705 Embedded Memory LCD Controller and the Toshiba MIPS TMPR3912 Processor The pairing of these two devices results in an embedded system offering impressive display capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Toshiba MIPS TMPR3912 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 004 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the TMPR3912 The Toshiba MIPS TMPR3912 processor supports up to two PC Card PCMCIA slots It 1s through this host bus interface that the S1D13705 connects to the TMPR3912 processor The S1D13705 can be successfully interfaced using one of two configurations e Direct connection to TMPR3912 e System design using one ITE IT8368E PC Card GPIO buffer chip S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Page 9 Vancouver Design Center 3 S1D13705 Host Bus Interface This section is a summary of the host bus interface modes available
273. e the polarity of the WAIT signal which is an active low signal to insert wait states in the bus cycle while the MCF5307 s Transfer Acknowledge signal TA is an active low signal to end the current bus cycle The inverter is enabled by CS so that TA is not driven by the S1D13705 during non S1D13705 bus cycles A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle The following diagram shows a typical implementation of the MCF5307 to S1D13705 interface MCF5307 S1D13705 A 16 0 gt AB 16 0 D 31 16 A gt DB 15 0 CS4 gt CS Vcc BS 470 TA l WAIT BWE1 gt WE1 BWEO gt WEO OE RD WR Ll RDA BCLKO BUSCLK System RESET gt RESETH Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of MCF3307 to S1D13705 Interface Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13705 Issue Date 01 02 13 X27A G 011 02 Page 14 Epson Research and Development Vancouver Design Center 4 2 S1D13705 Hardware Configuration The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Table 4 1 Su
274. ed from the HAL ERROR Could not initialize device The call to initialize the 1D13705 registers failed Not enough memory for www x hhh x bpp This message is printed if there is insufficient display memory to show a complete image with a width of www pixels a height of hhh pixels and a color depth of bpp bit per pixel In this case the mode is skipped and the next display mode is attempted 13705SHOW Demonstration Program 1D13705 Issue Date 01 02 12 X27A B 002 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705SHOW Demonstration Program X27A B 002 02 Issue Date 01 02 12 EPSON 1D13705 Embedded Memory LCD Controller 13705SPLT Display Utility Document No X27A B 003 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouv
275. ed to support EPSON LCD controllers and provides eleven Multi Function IO pins MFIO Configuration registers may be used to allow these MFIO pins to provide the control signals required to implement the S1D13705 CPU interface The TMPR3912 processor only provides addresses A 12 0 therefore devices requiring more address space must use an external device to latch A 25 13 The IT8368E s MFIO pins can be configured to provide this latched address S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center S1D13705 3 3V TMPR3912 T lO Vpp CORE Vpp A 12 0 gt AB 12 0 ENDIAN 7 gt AB 16 13 D 31 24 le DB 7 0 D 23 16 gt DB 16 8 System RESET gt RESET VoD pull up CARDxWAIT le ji WAIT DCLKOUT See text gt CLKI IT8368E gt Clock divider gt Oscillator gt BCLK LHA 23 MFIO 1 0 gt WE1 LHA 22 MFIO 9 WEO LHA 21 MFIO 8 RD WR LHA 20 MFIO 7 gt RD LHA 19 MFIO 6 gt CS LHA 16 13 MFIO 3 0 BSH Note k When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 5 1 S1D13705 to TMPR3912 Co
276. ed with the S1D13705 control registers mapped into the top 32 bytes of the 128K byte block and the 80K bytes of display buffer mapped to the starting address of the block The chip select should have its RO Read Only bit set to 0 its BSW Bus Data Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center Width set to 1 for a 16 bit bus and the WS Wait states bit should be set to 111b to allow the S1D13705 to terminate bus cycles externally Enable DTACK pin function with Register FFFFF433 Port G Select Register bit 0 Interfacing to the Motorola Dragonball Family of Microprocessors S1D13705 Issue Date 01 02 13 X27A G 007 04 Page 16 Epson Research and Development Vancouver Design Center 3 Interfacing to the MC68EZ328 3 1 The MC68EZ328 System Bus The MC68EZ328 is Motorola s second generation Dragonball microprocessor The DragonballEZ is an integrated controller for handheld products based upon the MC68EC000 microprocessor core The DragonballEZ differs from its predecessor mainly in that it has increased speed a DRAM controller infrared communication and an in circuit emulator The bus interface has also been simplified 1t implements a 16 bit data bus and a 24 bit address bus The bus interface is based on the standard MC68EC000 bus interface signals although the data bus byte lane control signals of the MC68EC000 bus
277. ed with the following S1D13705 supported evaluation platforms e PC system with an x86 processor Both 16 bit and 32 bit code is supported e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13705 Programming Notes and Examples manual document number X26A G 002 xx S1D13705 X27A B 005 04 Page 4 Installation Usage S1D13705 X27A B 005 04 Epson Research and Development Vancouver Design Center PC Intel Platform For 16 Bit Program Version copy the file 13705PLA Y EXE to a directory that is in the DOS path on your hard drive For 32 Bit Program Version install the 32 bit Windows device driver SID13XXX VXD as described in the S1D13XXX 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 xx Copy the file 13705PLA Y EXE to a directory that is in the DOS path on your hard drive Embedded Platform Download the program 13705PLAY to the system PC platform at the prompt type 13705play Embedded platform execute 13705play and at the prompt type the command line argument Where displays program revision information The following commands are valid within the 13705PLAY program X index data Reads writes the registers Writes data to the register specified by the index when data
278. eis FPSHIFT gt gt FPSHIFT aa ASH gt BS S1D13705 pit RWE gt RDWR FPFRAME DD FPFRAME LCD SIZ1 gt RDH FPLINE FPLINE Display SIZO gt WEO DADY gt gt MOD DSACK1 4 WAIT LCDPWR CLK gt BCLK RESET Pi RESET Figure 3 4 Typical System Diagram M68K 2 Bus Hardware Functional Specification S1D13705 X27A A 001 10 Page 14 Epson Research and Development Vancouver Design Center Oscillator CLK _ GENERIC 1 Se BUS CSn Pp CS A 16 0 P AB 16 0 D 15 0 le DB 15 0 FPDAT 11 0 gt 11 0 FPSHIFT FPSHIFT WEO 1D13705 12 bit WEO FPFRAME FPFRAME TFT NEU P FPLINE Hl FPLINE RDO gt RD Display DRDY _ DRDY RD1 P RD WR WAIT lq WAIT LCDPWR BCLK BCLK RESET Vv RESET Figure 3 5 Typical System Diagram Generic 1 Bus Oscillator CLK BS ISA REFRESH __ BUS sapo 17 __ Decoder O cst SA 16 0 gt AB 16 0 SD 15 0 4 gt DB 15 0 ern Aes SMEMW P WEO FPSHIFT gt FPSHIFT SMEMR gt RD S1D13705 9 bit FPFRAME gt FPFRAME TFT FPLINE A FPLINE SBHE WE1 DRDY P DRDY IOCHRDY WAIT LCDPWR BCLK gt BCLK RESET Do gt RESET Display y Figure 3 6 Typical System
279. els the start address needs to be advanced 1 Calculate the number of bytes to change start address by Bytes Pixels x BitsPerPixel 8 4 x 4 8 2 bytes Increment the start address registers by the just calculated value In this case the value write to the start address register will be 81h 7Fh 2 81h To scroll by 4 lines we have to change the start address by the offset of four lines of display 1 Calculate the number of bytes to change start address by BytesPerLine LineByteCount 128 Bytes Lines x BytesPerLine 4 x 128 512 200h Increment the start address registers by the just calculated value In this case 281h 81h 200h will be written to the Screen 1 Start Address register set Set Screen Display Start Word Address LSB REG OCh to 81h and Screen1 Dis play Start Word Address MSB REG ODh to 02h Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 47 Vancouver Design Center 8 Identifying the S1D13705 There are several similar products in the 135X and 137X LCD controller families Products which can share significant portions of a generic code base It may be important for a program to identify between products at run time Identification of the S1D13705 can be performed any time after the system has been powered up by reading REG 00h the Revision Code register The six most significant bits form the product identification code and the two least signifi
280. ending on which card slot is used must to be set to 0 in the PR31500 PR31700 Memory Configuration Register 3 When the PR31500 PR31700 accesses the PC Card slots buffered through the ITE IT8368E bits CARDIIOEN and CARD2IOEN are ignored and the attribute IO space of the PR31500 PR31700 is divided into Attribute I O and S1D13705 access Table 5 1 PR31500 PR31700 to PC Card Slots Address Mapping With and Without the IT8368E provides all details of the Attribute IO address reallocation by the IT8368E Table 5 1 PR31500 PR31700 to PC Card Slots Address Mapping With and Without the IT8368E PC Card TX3912 Direct Connection Direct Connection Slot Address 57 peng eter eee CARDnIOEN 0 CARDnIOEN 1 0800 0000h 16M byte Card 1 IO 1D13705 aliased 128 times 31013709 0900 0000h 16M byte a aliased 512 times Card 1 IO 1 at 128K byte intervals at 128K byte intervals OA00 0000h 32M byte Card 1 Attribute 6400 0000h 64M byte Card 1 Memory S1D13705 aliased 512 times at 128K byte intervals 0C00 0000h 16M byte Card 2 IO 1D13705 aliased 128 times Ste 0D00 0000h 16M byte aliased 512 times Card 2 IO 2 at 128K byte intervals at 128K byte intervals 0E00 0000h 32M byte Card 2 Attribute 6800 0000h 64M byte Card 2 Memory S1D13705 aliased 512 times at 128K byte intervals Interfacing to the Philips MIPS PR31500 PR31700 Processor S1D13705 Issue Date 01 02 13 X27A G 012 02
281. enter Page 53 int seSetBitsPerPixel int BitsPerPixel Description Parameter Return Value This routine sets the display color depth After performing validity checks to ensure the requested video mode can be set the appropriate registers are changed and the Look Up Table is set its default values appropriate to the color depth This call is similar to a mode set call on a standard VGA BitsPerPixel desired color depth in bits per pixel Valid arguments are 1 2 4 and 8 ERR_OK operation completed with no problems ERR_FAILED possible causes for this error include 1 the desired frame rate may not be attainable with the specified input clock 2 the combination of width height and color depth may require more memory than is available on the S1D13705 int seGetBitsPerPixel int pBitsPerPixel Description Parameters Return Value This function reads the S1D13705 registers to determine the current color depth and returns the result in pBitsPerPixel pBitsPerPixel pointer to an integer to receive current color depth return values will be 1 2 4 or 8 ERR_OK operation completed with no problems int seGetBytesPerScanline int pBytes Description Parameters Return Value Programming Notes and Examples Issue Date 02 01 22 Determines the number of bytes per scan line of current display mode It is assumed that the registers have already been correctly initialized before seGetByt
282. er Design Center O a BON 7 8 Table of Contents Introduction lt lt a 1 1 Features Installation and Configuration lt lt lt eee LCD Interface Pin Mapping lt lt CPU Bus Interface Connector Pinouts Host Bus Interface Pin Mapping Technical Description lt lt lt lt 6 1 Embedded Memory Support 6 2 ISA Bus Support 6 2 1 Display Adapter Card Support o o o 6 2 2 Expanded Memory Manager Support 6 3 Non ISA Bus Support 6 4 Decoding Logic 6 5 Clock Input Support 6 6 LCD Panel Voltage Setting 6 7 Monochrome LCD Panel Support 6 8 Color Passive LCD Panel Support 6 9 Color TFT D TFD LCD Panel Support 6 10 Power Save Modes NA 6 11 Adjustable LCD Panel Negative Power Supply 6 12 Adjustable LCD Panel Positive Power Supply 6 13 CPU Bus Interface Header Strips Paris List e a Si eet arg a wat et a Ser de a Schematic Diagrams o es S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Issue Date 01 02 13 Page 3 1D13705 X27A G 005 03 Page 4 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual X27A G 005 03 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center List of Tables Table 2 1 Confi
283. er Design Center THIS PAGE LEFT BLANK S1D13705 13705SPLT Display Utility X27A B 003 02 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center 13705SPLT 13705SPLT demonstrates S1D13705 split screen capability by showing two different areas of display memory on the screen simultaneously Screen 1 memory is located at the start of the display buffer and is filled with horizontal bars Screen 2 memory is located immediately after Screen 1 in the display buffer and is filled with vertical bars On either user input or elapsed time the line compare register value is changed to adjust the amount of display area taken up by each screen The 13705SPLT display utility must be configured and or compiled to work with your hardware platform The program 13705CFG EXE can be used to configure 13705SPLT Consult the 13705CFG users guide document number X27A B 001 xx for more infor mation on configuring S1D13705 utilities This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications The PC uses a terminal program to send control commands and infor mation to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate w
284. er X27A A 001 xx MC68VZ328 A 16 0 CSB1 CLKO D 15 0 Vcc a la S1D13705 Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up i gt System RESET gt AB 16 0 DB 15 0 CS BS WAIT WE1 WEO RD WR RD BUSCLK RESET from power down modes or during debug states Figure 4 2 Typical Implementation of MC68VZ328 to SIDI3705 Interface Generic 1 Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 1D13705 X27A G 007 04 Page 28 4 4 2 S1D13705 Hardware Configuration Epson Research and Development Vancouver Design Center The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the 1D 3705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show those configuration settings important to the MC68K 1 and Generic 1 host bus interfaces Table 4 2 Summary of Power On Reset Options S1D1370 value on this pin at the rising edge of RESET is used to configure 1 0 a 0 1 Pin Name CNFO CNF1 See Table 2 3 Host Bus Interface Selection CNF2
285. er image refreshed by S1D13705 image in display buffer Figure 7 2 Relationship Between the Alternate Mode Screen Image and the Image Refreshed by SID13705 Programming Notes and Examples Issue Date 02 01 22 From the programmers perspective the memory is laid out as shown on the left The programmer accesses memory exactly as for a panel of with the dimensions of 240x320 The programmer sees memory addresses increasing from A gt B and from B gt C From a hardware perspective the S1D13705 always refreshes the LCD panel in the order B gt D and down to do A gt C The greatest factor in selecting alternate portrait mode over default portrait mode would be for the ability to obtain an area of contiguous off screen memory For example A 640x480 panel in default portrait mode at two bit per pixel requires 81920 bytes 80 Kb There is unused memory but it is not contiguous The same situation using alternate portrait mode requires 76800 bytes leaving 5120 bytes of contiguous memory available to the application In fact the change in memory usage may make the difference between being able to run certain panels in portrait mode or not being able to do so S1D13705 X27A G 002 03 Page 40 Epson Research and Development Vancouver Design Center 7 4 Registers This section describes the registers used to set portrait mode operation REG 0Ch Screen 1 Start Word Address LSB
286. er pixel Swivel View 270 degree mode This document and the source code for the Windows CE drivers are updated as appropriate Before beginning any development please check the Epson Electronics America Website at www eea epson com or the Epson Research and Development Website at www erd epson com for the latest revisions We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Windows CE 3 x Display Drivers 1D13705 Issue Date 01 05 25 X27A E 006 01 Page 4 Epson Research and Development Vancouver Design Center Example Driver Builds The following sections describe how to build the Windows CE display driver for 1 Windows CE Platform Builder 3 00 using the GUI interface 2 Windows CE Platform Builder 3 00 using the command line interface In all examples x refers to the drive letter where Platform Builder is installed Build for CEPC X86 on Windows CE Platform Builder 3 00 using the GUI Interface S1D13705 X27A E 006 01 1 Install Microsoft Windows 2000 Professional or Windows NT Workstation version 4 0 with Service Pack 5 or later Install Windows CE Platform Builder 3 00 Start Platform Builder by double clicking on the Microsoft Windows CE Platform Builder icon Create a new project a Select File New b In the dialog box select the Platforms tab c In the platforms dialog box select WCE Platform set a location for the p
287. erd epson com Interfacing to the NEC VR4181A Microprocessor 1D13705 Issue Date 01 02 13 X27A G 013 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4181A 2 1 The NEC VR4181A System Bus 2 1 1 Overview S1D13705 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4181A offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR4181A is designed around the RISC architecture developed by MIPS This microprocessor is designed around the 100MHz VR4110 CPU core which supports the MIPS III and MIPS16 instruction sets The CPU communicates with external devices via an ISA interface The NEC VR4181A has direct support for an external LCD controller A 64 to 512 kilobyte block of memory is assigned to the LCD controller with a dedicated chip select signal Word or byte accesses are controlled by the system high byte signal UBE Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Signals The S1D13705 requires an addressing range of 128Kbytes When the VR4181A s external LC
288. ernal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the S1D13705 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high Interfacing to an 8 bit Processor Issue Date 01 12 20 Epson Research and Development Page 11 Vancouver Design Center 4 8 Bit Processor to S1D13705 Interface 4 1 Hardware Description The interface between the S1D13705 and an 8 bit processor requires minimal glue logic A decoder is used to generate the chip select for the S1D13705 based on where the S1D13705 is mapped into memory Alternatively if the processor supports a chip select module it can be programmed to generate a chip select for the S1D13705 without the need of an address decoder An inverter inverts AO to generate the Byte High Enable signal for the S1D13705 If the 8 bit host interface has an active high WAIT signal it must be inverted as well In order to support an 8 bit microprocessor with a 16 bit peripheral the low and high order bytes of the data bus must be connected together The following diagram shows a typical implementation of an 8 bit processor interf
289. es During power on sequences the power save mode is reset some time before the LCDPWR Override is reset resulting in the LCD logic signals being active before power is applied to the panel 1D13705 X27A G 002 03 Page 36 Epson Research and Development Vancouver Design Center 6 3 LCD Enable Disable The descriptions below cover manually powering the LCD panel up and down Use the sequences described in this section if the power supply connected to the panel requires more than 127 frames to discharge on power down or if the panel requires starting the LCD logic well in advance of enabling LCD power Currently there are no known circumstances where the LCD logic must be active well in advance of LCD power Note If 127 frame period is to long blank the display then reprogram the Horizontal and Ver tical sizes to produce a shorter frame period before using these methods Power On Enable Sequence The following is a sequence for manually powering up an LCD panel if LCD power had to be applied later than LCD logic 1 Set REG 03h bit 3 LCDPWR Override to 1 This ensures that LCD power will be held disabled 2 Enable LCD logic This is done by either setting the GPIOO pin low to disable hard ware power save mode and or by setting REG 03h bits 1 0 to 11 to disable soft ware power save 3 Count x Vertical Non Display Periods OPTIONAL x corresponds the length of time LCD logic must be enabled before LCD p
290. es support contact or www eea epson com Interfacing to the Philips MIPS PR31500 PR31700 Processor S1D13705 Issue Date 01 02 13 X27A G 012 02 Epson Research and Development Page 20 Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers S1D13705 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Philips Semiconductors Handheld Computing Group 4811 E Arques Avenue M S 42 P O Box 3409 Sunnyvale CA 94088 3409 Tel 408 991 2313 http www philips com 7 3 ITE IT8368E Integrated Technology Express Inc Sales amp Marketing Division 2710 Walsh Avenue Santa Clara CA 95051 USA Tel 408 980 8168 Fax 408 980 9232 http www iteusa com 1D13705 X27A G 012 02 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 Philips MIPS PR31500 PR31700 Processor Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore
291. es the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs AB1 through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space AO and WElf are the enables for the low order and high order bytes respectively to be driven low when the host CPU is reading or writing data to the S1D137053 RD WRz is the read write signal that is driven low when the CPU writes to the S1D13705 and is driven high when the CPU is doing a read from the S1D13705 WAIT is a signal which is output from the S1D13705 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13703 internal registers and or refresh memory The WAIT line re
292. esPer Scanline is called i e after initializing the HAL setting the Display mode and adjusting the bits per pixel or other values The number of bytes per scanline will include non displayed bytes if the screen width is greater the display width or in Default Portrait Mode pBytes pointer to an integer to receive the number of bytes per scan line ERR_OK operation completed with no problems 1D13705 X27A G 002 03 Page 54 S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center int seGetScreenSize int Width int Height Description Retrieves the width and height in pixels of the display surface The width and height are derived by reading the horizontal and vertical size registers and calculating the dimensions Virtual dimensions are not taken into account for this calculation When the display is in portrait mode the dimensions will be swapped i e a 640x480 display in portrait mode will return a width of 480 and height of 640 Parameters Width pointer to an integer to receive the display width Height pointer to an integer to receive the display height Return value ERR_OK the operation completed successfully int seDelay int MilliSeconds Description Parameters Return Value This function will delay for the length of time specified in MilliSeconds before returning to the caller This function was originally intended for non PC platforms Information about
293. ese issues is discussed in the following sections Compile Switches There are several switches specific to the S1D13705 display driver which affect the display driver The switches are added or removed from the compile options in the file SOURCES WINCEVER This option is automatically set to the numerical version of WinCE for version 2 12 or later If the environment variable WINCEOSVER is not defined then WINCEVER will default 2 11 The display driver may test against this option to support different WinCE version specific features DEBUG_MONITOR This option enables the use of the debug monitor The debug monitor can be invoked when the display driver is first loaded and can be used to view registers and perform a few debugging tasks The debug monitor is still under development and is untested This option should remain disabled unless you are performing specific debugging tasks that require the debug monitor TEST_BITMAP This option allows the debug monitor to display a test bitmap This bitmap is big and will make the display driver considerably larger The flag DEBUG_MONITOR must also be enabled for this option to work This option should be disabled unless the image is required for debugging Windows CE 2 x Display Drivers 1D13705 Issue Date 01 06 07 X27A E 001 03 Page 12 Mode File S1D13705 X27A E 001 03 Epson Research and Development Vancouver Design Center A second variable which will affect the
294. ese bits have no effect in Landscape Mode The following table shows the selection of PCLK and MCLK in SwivelView Mode see Section 12 SwivelView on page 77 for details Table 8 8 Selection of PCLK and MCLK in SwivelView Mode SwivelView SwivelView _ Pixel Clock PCLK Select Mode Enable Mode Select REG 1Bh bits 1 0 PCLK MCLK REG 1Bh bit 7 REG 1Bh bit 6 Bit 1 Bit 0 0 X X X CLK See Reg 02h bit 5 1 0 0 0 CLK CLK 1 0 0 1 CLK 2 CLK 2 1 0 1 0 CLK 4 CLK 4 1 0 1 1 CLK 8 CLK 8 1 1 0 0 CLK 2 CLK 1 1 0 1 CLK 2 CLK 1 1 1 0 CLK 4 CLK 2 1 1 1 CLK 8 CLK 4 REG 02h bit 4 0 or CLKI 2 REG O2h bit 4 1 la Where CLK is CLKI REG 1Ch Line Byte Count Register for SwivelView Mode Address 1FFFCh Read Write Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Line Byte Count bit 7 Count bit 6 Count bit 5 Count bit 4 Count bit 3 Count bit 2 Count bit 1 Count bit 0 bits 7 0 Line Byte Count Bits 7 0 This register is the byte count from the beginning of one line to the beginning of the next consecutive line commonly called stride by programmers This register may be used to create a virtual image in Swivel View mode When this register 00 the stride 256 bytes This value is used for 240x320 8 bpp default Swivel View mode When the Line Byte Count Register n where 1 lt n lt FFh the
295. ese settings may be changed Color Depth Panel SwivelView Enable 13705CFG Configuration Program Issue Date 02 03 11 Sets the initial color depth on the LCD panel The S1D13705 SwivelView feature is capable of rotating the image displayed on an LCD panel 90 in a counter clockwise direction This sets the initial orien tation of the panel The SwivelView feature can be run in two different modes Default mode requires a virtual display which requires more memory but uses less power When this box is checked SwivelView is enabled and the LCD display is rotated 90 in a counter clockwise direction S1D13705 X27A B 001 03 Page 10 Alternative Mode Epson Research and Development Vancouver Design Center When alternate mode is selected Swivel View requires no virtual display but consumes more power For details see the S1D13705 Hardware Functional Specification document number X27A A 001 xx The Clocks tab is intended to simplify the selection of input clock frequencies and the source of internal clocking signals For further information regarding clocking and clock sources refer to the D13705 Hardware Functional Specification document number Options for LCD frame rates are limited to ranges determined by the clock values Changing clock values may modify or invalidate Panel settings Confirm all settings on the Panel tab after modifying any clock settings Clocks Tab 70 51D13705 Configuration Utility CLKI
296. esearch and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705PWR Power Save Utility X27A B 007 03 Issue Date 01 07 04 Epson Research and Development Page 3 Vancouver Design Center 13705PWR The 13705PWR Power Save Utility is a tool to assist in the testing of the software and hardware power save modes Refer to the section titled Power Save Modes in the S1D13705 Programming Notes and Examples manual document number X27A G 002 xx and the S1D13705 Functional Hardware Specification document number X27A A 001 xx for further information The 13705PWR utility must be configured and or compiled to work with your hardware platform Consult documentation for the program 13705CFG EXE which can be used to configure 13705PWR This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications where the PC uses a terminal program t
297. essing the 13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the S1D13705 for Generic 2 mode and should be tied high connected to IO Vpp RD WR should also be tied high 1D13705 X27A G 009 02 Page 12 Epson Research and Development Vancouver Design Center 4 PC Card to S1D13705 Interface 4 1 Hardware Connections The S1D13705 is interfaced to the PC Card bus with a minimal amount of glue logic In this implementation the address inputs AB 16 0 and data bus DB 15 0 connect directly to the CPU address A 16 0 and data bus D 15 0 The PC Card interface does not provide a bus clock so one must be supplied for the S1D13705 Since the bus clock frequency is not critical nor does it have to be synchronous to the bus signals it may be the same as CLKI BS bus start is not used by Generic 2 mode but is used to configure the 1D13705 for either Generic 1 or Generic 2 bus and should be tied high connected to IO V pp RD WR is also not used by Generic 2 bus and should be tied high connected to IO Vpp The following diagram shows a typical implementation of t
298. essor families The bus interface mode used in this example is e Generic 2 this bus interface is ISA like and can easily be modified to support an 8 bit CPU 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping EOS Generic 2 Description AB 16 1 A 16 1 Address 16 1 ABO AO Address AO DB 15 0 D 15 0 Data WE1 BHE Byte High Enable CS External Decode Chip Select BCLK BCLK Bus Clock BS n c Must be tied to lO Vpp RD WR n c Must be tied to lO Vpp RD RD Read WEO WE Write WAIT WAIT RESET RESET Note If the CPU does not have address A16 all 80K Bytes of embedded memory will not be accessible For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx Interfacing to an 8 bit Processor Issue Date 01 12 20 1D13705 X27A G 015 01 Page 10 Epson Research and Development Vancouver Design Center 3 2 Generic 2 Interface Mode S1D13705 X27A G 015 01 Generic 2 Host Bus Interface is a general non processor specific interface mode on the S1D13705 that is ideally suited to interface to an 8 bit processor bus The interface requires the following signals e BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKD and is typically
299. face Timing Telk ax EEE E E AR A 16 1 CS VALID R WH tl t2 AS UDS LDS INVALID t5 4 gt t3 t4 gt E t6 DTACK ali a gt e Hi Z 18 Ll D 15 0 o lt A write pes VALID wes t10 t11 tle _ gt D 15 0 i i read ne y VALID Hee Figure 7 3 MC68K 1 Bus Timing MC68000 Table 7 3 MC68K 1 Bus Timing MC68000 Symbol Parameter Min Max Units folk Bus Clock Frequency 33 MHz ToLk Bus Clock period ek ti A 16 1 CS valid before AS falling edge 0 ns t2 A 16 1 CS hold from AS rising edge 0 ns 13 ASH low to DTACK driven high 16 ns t4 CLK to DTACK low 15 ns t5 CLK to AS UDS LDS high Te t6 AS high to DTACK high 20 ns t7 AS high to DTACK high impedance Tok t8 UDS LDS falling edge to D 15 0 valid write cycle TeLk t9 D 15 0 hold from AS rising edge write cycle 0 ns t10 UDS LDS falling edge to D 15 0 driven read cycle 15 ns t11 D 15 0 valid to DTACK falling edge read cycle 0 ns t12 UDS LDS rising edge to D 15 0 high impedance 10 ns Note CLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 84 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Page 31 Vancouver Design Center 7 1 4 Motorol
300. finished display driver is the register configurations contained in the mode file The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13705CFG EXE The display driver comes with example MODE tables By default only MODEO H is used by the display driver New mode tables can be created using the 13705CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode you do not need to add any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should use upon boot add the following lines to your PLATFORM REG file HKEY_LOCAL_MACHINE Drivers Display S 1D13705 Width dword 140 Height dword FO Bpp dword 8 Rotation dword 0 RefreshRate dword 3C Flags dword 1 Note that all dword values are in hexadecimal therefore 140h 320 FOh 240 and 3Ch 60 The value for Flags should be 1 LCD When the display driver starts 1t will read these values in the registry and at
301. following two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13705 ddi dll FLATRELEASEDIR epson dil NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_S1D13705 Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGASBPP Windows CE 2 x Display Drivers 1D13705 Issue Date 01 06 07 X27A E 001 03 Page 8 10 11 S1D13705 X27A E 001 03 Epson Research and Development Vancouver Design Center ddi dll FLATRELEASEDIRNMddi_s364 dll NK SH ENDIF ENDIF ENDIF ENDIF Insert this line The file MODEO H located in xAWwincelplatformicepcidriversidisplayiS1D13705 contains the register values required to set the screen resolution color depth bpp display type active display LCD CRT TV display rotation etc Before building the display driver refer to the descriptions in the file MODEO H for the default settings of the driver If the default does not match the configuration you are building for then MODEO H will have to be regenerated with the correct informa tion Use the program 13705CFG to generate the header file For information on how to use 13705CFG refer to the 13705CFG Configuration Program User Manual document number X27A B 001 xx available at www erd epson com After selecting the desired configuration export the file as a C Header File for S1D13705 WinCE Drivers Save the new configuration as MOD
302. for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4102 VR4111 Microprocessor X27A G 008 02 Issue Date 01 02 13 Epson Research and Development Vancouver Design Center Table of Contents 1 Introduction lt lt 2 Interfacing to the NEC VR4102 VR4111 2 1 The NEC VR4102 VR4111 System Bus DAL COVEIVISW cise ares ead Reo seh a a E a 2 1 2 LCD Memory Access Cycles 3 S1D13705 Host Bus Interface 3 1 Host Bus Pin Connection 3 2 Generic 2 Interface Mode 4 VR4102 VR4111 to S1D13705 Interface 4 1 Hardware Description 4 2 S1D13705 Hardware Configuration 4 3 NEC VR4102 VR4111 Configuration 5 SOWIE oie A a e Ra ee ee References taa Ce Be ee OU ee es 6 1 Documents 6 2 Document Sources 7 Technical Support 7 1 Epson LCD Controllers S1D13705 7 2 NEC Electronics Inc Interfacing to the
303. get File dialog box select browse and then select the path and the file name of sources 9 Delete the component ddi_flat a In the Workspace window select the ComponentView tab b Show the tree for MYPLATFORM components by clicking on the sign at the root of the tree c Right click on the ddi_flat component d Select Delete e From the File menu select Save Workspace 10 From the Workspace window click on ParameterView Tab Show the tree for MY PLATFORM Parameters by clicking on the sign at the root of the tree Expand the the WINCE300 tree and then click on Hardware Specific Files and then double click on PLATFORM BIB Edit the file the PLATFORM BIB file and make the fol lowing two changes a Insert the following text after the line IF ODO_NODISPLAY IF CEPC_DDI_S1D13X0X ddi dll FLATRELEASEDIRAS1D13X0X d1l NK SH ENDIF b Find the section shown below and insert the lines as marked IF CEPC_DDI_FLAT IF CEPC_DDI_S1D13X0X Insert this line IF CEPC_DDI_S3VIRGE IF CEPC_DDI_CT655X IF CEPC_DDI_VGA8BPP IF CEPC_DDI_S3TRIO64 IF CEPC_DDI_ATI Windows CE 3 x Display Drivers 1D13705 Issue Date 01 05 25 X27A E 006 01 Page 6 S1D13705 X27A E 006 01 11 12 Epson Research and Development Vancouver Design Center ddi dll FLATRELEASEDIRNddi_flat dl NK SH ENDIF ENDIF ENDIF ENDIF ENDIF ENDIF Insert this line ENDIF Modify MODEO H
304. gister descriptions and power management descriptions This document is intended for two audiences Video Subsystem Designers and Software Developers This document is updated as appropriate Please check for the latest revision of this document before beginning any development The latest revision can be downloaded at www erd epson com We appreciate your comments on our documentation Please contact us via email at documentation erd epson com 1 2 Overview Description The S1D13705 is a color monochrome LCD graphics controller with an embedded 80K byte SRAM display buffer The high integration of the S1D13705 provides a low cost low power single chip solution to meet the requirements of embedded markets such as Office Automation equipment Mobile Communications devices and Hand Held PCs where board size and battery life are major concerns Products requiring a Portrait display can take advantage of the Swivel View Mode feature of the 1D13705 Virtual and Split Screen are just some of the display modes supported The above features combined with the Operating System independence of the S1D13705 make it the ideal solution for a wide variety of applications Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 10 2 Features Epson Research and Development Vancouver Design Center 2 1 Integrated Frame Buffer Embedded 80K byte SRAM display buffer 2 2 CPU Interface Direct support of
305. guration DIP Switch Settings o e ea 8 Tabl 2 2 Host Bus Selection nh ai a a A 8 Table 2 3 Jumper Settings ec ts Poe dd a e 9 Table 3 1 LCD Signal Connector J5 Pinout o o ee 10 Table 4 1 CPU BUS Connector H1 Pinout e 11 Table 4 2 CPU BUS Connector H2 Pinout e 12 Table 5 1 Host Bus Interface Pin Mapping 2 2 0 0 000 eee 13 List of Figures Figure 8 1 S1D13705B00C Schematic Diagram 1 of 4 o ooo 20 Figure 8 2 S1D13705B00C Schematic Diagram 2 of 4 o o ooo e 21 Figure 8 3 S1D13705B00C Schematic Diagram 3 of 4 o oo o e 22 Figure 8 4 S1D13705B00C Schematic Diagram 404 o ooo 23 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13705 Issue Date 01 02 13 X27A G 005 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual X27A G 005 03 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This manual describes the setup and operation of the S5U13705B00C Rev 1 0 Evaluation Board Implemented using the S1D13705 Embedded Memory Color LCD Controller the S5U13705B00C board is designed for the 16 bit ISA bus environment To accommodate other bus architectures the SSU13705BO0C board also provides CPU Bus i
306. h bit 7 1 and bit 6 1 The display refresh circuitry starts at pixel B therefore the Screen 1 Start Address register must be programmed with the address of pixel B or REG 10h REG ODh REG OCh AddressOfPixelB AddressOfPixelA ByteOffset 320pixels x ACEP L 8bpb AddressOfPixelA AddressOfPixelA 9Fh Where bpp is bits per pixel and bpb is bits per byte The Line Byte Count Register for Swivel View Mode must be set to the image width in bytes i e A 320 3220 ien REGUICh am D7 A0h Where bpb is bits per byte and bpp is bits per pixel Panning is achieved by changing the Screen 1 Start Address register e Increment the register by 1 to pan horizontally by one byte e g two pixels in 4 bpp mode e Increment the register by the value in the Line Byte Count register to pan vertically by one line e g add AOh to pan by one line in the example above Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 81 12 3 Comparison Between Default and Alternate SwivelView Modes Table 12 1 Default and Alternate SwivelView Mode Comparison Item Default SwivelView Mode Alternate SwivelView Mode Memory Requirements The width of the rotated image must be a power of 2 In most cases a virtual image is required where the right hand side of the virtual image is unused and memory is wasted For example a 320x480x4bpp im
307. h Performance option is turned on the power consumption increases to that of 8 bit per pixel mode for all color depths There are two power save modes in the S1D13705 Software and Hardware Power Save The power consumption of these modes is affected by various system design variables e CPU bus state during Power Save the state of the CPU bus signals during Power Save has a substantial effect on power consumption An inactive bus e g BUSCLK low Addr low etc reduces overall system power consumption e CLKI state during Power Save disabling the CLKI during Power Save has substantial power savings 1D13705 X27A G 006 02 Page 4 Epson Research and Development Vancouver Design Center 1 1 Conditions Table 1 1 S1D13705 Total Power Consumption below gives an example of a specific environment and its effects on power consumption Table 1 1 SIDI3705 Total Power Consumption Test Condition Power Consumption Core Vpp 3 3V IO Vpp 3 3V eis ality f Active Power Save Mode BUSOLK a SOM Core 10 Total Software Hardware Input Clock 6MHz Black and White 4 29mW 0 52mW 4 81mW 1 LCD Panel 320x240 4 bit Single 4 Gray Shades 4 99mW 0 76mW 5 75mW 1 44mw 1 21mWw Monochrome 16 Gray Shades 6 13mW 0 75mW 6 88mW 2 Colors 4 64mW 0 73mW 5 37mW 4 Colors 5 30mW 1 51mW 6 81mW 2 Input Clock 6MHz 1 44mW 1 22mw LCD Panel 320x240 4 bit Single Color 16 Colors 6 58mW 1 57mW 8 1
308. h and Development Inc All rights reserved Display e Modes 1 2 4 8 bit per pixel bpp support on LCD Up to 16 shades of gray using FRM on monochrome passive LCD panels Up to 256 simultaneous colors from a possible 4096 colors on passive STN and active matrix TFT D TFD LCD panels Split Screen Display allows two different images to be simultaneously viewed on the same display Virtual Display Support displays images larger than the display size through the use of panning Double Buffering multi pages provides smooth animation and instantaneous screen update Hardware Portrait Mode direct hardware 90 rotation of display image for portrait mode display Power Down Modes e e Software Suspend mode LCD power down sequencing Operating Voltage e COREypp 2 7 to 3 6 volts lOypp 2 7 to 5 5 volts Package e Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Epson Europe Electronics GmbH 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 80 pin QFP14 FOR SYSTEM INTEGRATION SERVICES FOR WINDOWS CE CONTACT Epson Research amp Development Inc Suite 320 11120 Horseshoe Way Richmond B C Canada V7A 5H7 Tel 604 275 5151 Ero Fax 604 275 2167 J Email wince erd epson com Microsoft http www erd epson com Windows CE r er Taiwan Epson Taiwan Technology 8
309. h and Development Page 31 Vancouver Design Center 5 3 Split Screen Occasionally the need arises to display two different but related images Take for example a game where the main play area requires rapid updates and game status displayed at the bottom of the screen requires infrequent updates The Split Screen feature of the S1D13705 allows a programmer to setup a display in such a manor When correctly configured the programmer has only to update the main area on a regular basis Occasionally as the need arises the secondary area is updated The figure below illustrates how a 320x240 panel may be configured to have one image displaying from scan line 0 to scan line 199 and image 2 displaying from scan line 200 to scan line 239 Although this example picks specific values the split between image 1 and image 2 may occur at any line of the display Scan Line 0 Image 1 Scan Line 199 Scan Line 200 Image 2 Scan Line 239 Figure 5 2 320x240 Single Panel For Split Screen In split screen operation Image 1 is taken from the display memory location pointed to by the Screen 1 Start Address registers and is always located at the top of the screen Image 2 is taken from the display memory location pointed to by the Screen 2 Start Address registers The line where Image 1 end and Image 2 begins is determined by the Screen 1 Vertical Size register Programming Notes and Examples 1D13705 Issue Date 02
310. he 8bpp Builds view by clicking on the next to it The expanded view will contain the item default Right click on de fault and select Properties A properties window will appear c Select the C C compiler tab to display the command switches used in the build Remove the ansi switch from the line that con tains g mpentium ansi nostdinc DRW_MULTI_THREAD Refer to GNU ToolKit user s guide for details 8 Compile the VxWorks image Select the Files tab in the Tornado Workspace window Right click on 8bpp files and select Dependencies Click on OK to regenerate project file dependencies for All Project files Right click on 8bpp files and select ReBuild All vxWorks to build VxWorks 9 Copy the VxWorks file to the diskette From a command prompt or through the Windows interface copy the file x 13705 8bpp default vxWorks to the bootable disk created in step 4 10 Start the VxWorks demo Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO auto matically Wind River UGL v1 2 Display Drivers 1D13705 Issue Date 01 02 13 X27A E 003 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Wind River UGL v1 2 Display Drivers X27A E 003 02 Issue Date 01 02 13 EPSON 1D13705 Embedded Memory LCD Controller Linux Console Driver Document N
311. he cause of an error returned from the HAL Software Power Save Mode set This message is a confirmation that the register setting to enable software power save mode has been set Software Power Save Mode reset This message is a confirmation that the register setting to disable software power save mode has been set Hardware Power Save Mode is now Enabled This message confirms that hardware initiated power save mode has been enabled The S1D13705 will enter a hardware power save mode upon application of the appropriate logic level to the hardware power save mode input pin Hardware Power Save Mode is now Disabled This message confirms that the register setting to disable hardware initiated power save mode has been set In this state the 1D13705 should ignore the state of the hardware power save mode input pin 13705PWR Power Save Utility S1D13705 Issue Date 01 07 04 X27A B 007 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705PWR Power Save Utility X27A B 007 03 Issue Date 01 07 04 EPSON 1D13705 Embedded Memory LCD Controller Windows CE 2 x Display Drivers Document Number X27A E 001 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not mo
312. he PC Card bus control signals The interface requires the following signals Interfacing to the PC Card Bus Issue Date 01 02 13 BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WE1F is the high byte enable for both read and write cycles WEO is the write enable for the S1D13705 to be driven low when the host CPU is writing data to the S1D13705 RD is the read enable for the S1D13705 to be driven low when the host CPU is reading data from the S1D13705 WAIT is a signal which is output from the S1D13705 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in acc
313. he PC Card to S1D13705 interface PC Card socket S1D13705 OE gt RD WE gt WEO CE1 CE2 WE1 RESET gt o gt RESET IO V OVo Rom CS A 16 0 gt AB 16 0 D 15 0 gt DB 15 0 15K pull up WAIT WAIT BUSCLK Oscillator CLKI Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states S1D13705 X27A G 009 02 Figure 4 1 Typical Implementation of PC Card to S1D13705 Interface Interfacing to the PC Card Bus Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13705 Hardware Configuration The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the 1D13705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show only those configuration settings important to the PC Card host bus interface Table 4 1 Summary of Power On Reset Options Signal Low High CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Big Endian eS configuration for PC Card host bus interface Table 4 2
314. he VxWorks demo Boot the target PC with the VxWorks bootable diskette to run the UGLDEMO auto matically Wind River WindML v2 0 Display Drivers 1D13705 Issue Date 01 04 06 X27A E 002 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Wind River WindML v2 0 Display Drivers X27A E 002 03 Issue Date 01 04 06 EPSON 1D13705 Embedded Memory LCD Controller Wind River UGL v1 2 Display Drivers Document Number X27A E 003 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Microsoft and Windows are registered trademarks of Microsoft Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Wind River UGL v1 2 Display Drivers X27A E 003 02 Issue Date 01 02 13 Epson Research and Development Page 3 Vancouver Design Center
315. he high order address lines to select the proper register and memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the 1D13705 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the 1D13705 for Generic 1 mode and should be tied low connected to GND Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 13 Epson Research and Developmen
316. he image 4 Create a bootable disk in drive A From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get config pcPentium and type mkboot a bootrom_uncmp 5 Ifnecessary generate a new mode0 h configuration file The file mode0 h contains the register values required to set the screen resolution col or depth bpp display type passive or active matrix rotation etc The mode0 h file included with the drivers may not contain applicable values and must be regenerated The configuration program 13705CFG can be used to build a new mode0 h file If building for 8 bpp place the new mode0 h file in the directory x 13705 8bpp File Wind River WindML v2 0 Display Drivers Issue Date 01 04 06 Epson Research and Development Page 5 Vancouver Design Center Note Mode0 h should be created using the configuration utility 13705CFG For more infor mation on 13705CFG see the 13705CFG Configuration Program User Manual docu ment number X27A B 001 xx available at www erd epson com 6 Build the WindML v2 0 library From a command prompt change to the directory x Tornado host x86 win32 bin and run the batch file torvars bat Next change to the directory x Tornado tar get src ugl and type the command make CPU PENTIUM ugl 7 Open the S1D13705 workspace From the Tornado tool bar select File gt
317. hich is compatible with most 68K peripherals Chip selects O and 1 can be programmed independently to respond to any base address and block size Chip select 0 can be active immediately after reset and is typically used to control a boot ROM Chip select 1 is likewise typically used to control a large static or dynamic RAM block Chip selects 2 through 7 have fixed block sizes of 2M bytes each Each has a unique fixed offset from a common programmable starting address These chip selects are well suited to typical IO addressing requirements Each chip select may be individually programmed for port size 8 16 32 bits 0 to 15 wait states or external acknowledge address space type burst or non burst cycle support and write protect Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 13 Epson Research and Development Page 11 Vancouver Design Center 3 S1D13705 Bus Interface This section is a summary of the host bus interface mode used on the S1D13705 to interface to the MCF5307 The S1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The interface mode used for the MCF5307 is e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte 3 1 Host Bus Pin Connection Table 3 1 Host Bus Interface Pin Mapping elaine Generic 1 AB 15 1 A 15
318. i Z e g MC68340 i 1 19 e For Generic 1 these pins are connected to D 15 0 For Generic 2 these pins are connected to D 15 0 See Table 5 2 Host Bus Interface Pin Mapping on page 22 for summary S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 19 Pin Names Type Pin Cell RESET State Description WE0 l 77 CS Input This pin has multiple functions e For SH 3 SH 4 mode this pin inputs the write enable signal for the lower data byte WEO e For MC68K 1 this pin must be tied to lO Vpp e For MC68K 2 this pin inputs the bus size bit 0 SIZO For Generic 1 this pin inputs the write enable signal for the lower data byte WEO For Generic 2 this pin inputs the write enable signal WE See Table 5 2 Host Bus Interface Pin Mapping on page 22 for summary WE1 l 78 CS Input This pin has multiple functions For SH 3 SH 4 mode this pin inputs the write enable signal for the upper data byte WE1 For MC68K 1 this pin inputs the upper data strobe UDS For MC68K 2 this pin inputs the data strobe DS For Generic 1 this pin inputs the write enable signal for the upper data byte WE1 For Generic 2 this pin inputs the byte enable signal for the high data byte BHE See Table 5 2 Host Bus Interface Pin Mapping o
319. iate bits and if necessary setting bits to 1 When using a color panel the two colors are derived by indexing into positions O and 1 of the Look Up Table If the first two LUT elements are set to black RGB 0 0 0 and white RGB FF F then each 0 bit of display memory will display as a black pixel and each 1 bit will display as a white pixel The two LUT entries can be set to any desired colors for instance red and green or cyan and yellow For monochrome panels the two displayed gray shades are generated by indexing into the first two elements of the green component of the Look Up Table LUT Thus by manip ulating the green LUT components we can set either of the two gray shades to any of sixteen possible levels Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Figure 3 1 Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 13 Vancouver Design Center 3 2 2 Bit Per Pixel 4 Colors Gray Shades 2 bit pixels support four color gray shades In this memory format each byte of display buffer contains four adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the appropriate bits and if necessary setting bits to 1 Color panels derive
320. ies The section Simple Display Driver Configuration on page 15 provides a configuration which should work with most Windows CE platforms This section is only intended as a means of getting started Once the developer has a functional system it is recommended to optimize the display driver configuration as described below in Description of Windows CE Display Driver Issues Description of Windows CE Display Driver Issues The following are some issues to consider when configuring the display driver to work with Windows CE 1 When Windows CE enters the Suspend state power off the LCD controller and dis play memory may lose power depending on how the OEM sets up the system If dis play memory loses power all images stored in display memory are lost If power off power on features are required the OEM has several options e If display memory power is turned off add code to the display driver to save any images in display memory to system memory before power off and add code to restore these images after power on e If display memory power is turned off instruct Windows CE to redraw all images upon power on Unfortunately it is not possible to instruct Windows CE to redraw any off screen images such as icons slider bars etc so in this case the OEM must also configure the display driver to never use off screen memory e Ensure that display memory never loses power 2 Using off screen display memory significantly
321. iles of the same names Modify s1d13705 h The file s1d13705 h contains the register values required to set the screen resolution color depth bpp display type display rotation etc Before building the console driver refer to the descriptions in the file s1d13705 h for the default settings of the console driver If the default does not match the configura tion you are building for then s1d13705 h will have to be regenerated with the correct information Use the program 13705CFG to generate the required header file For information on how to use 13705CFG refer to the 13705CFG Configuration Program User Manual document number X27A B 001 xx available at www erd epson com After selecting the desired configuration choose File gt Export and select the C Header File for S1D13705 Generic Drivers option Save the new configuration as s1d13705 h in the usr src linux drivers video replacing the original configuration file Configure the video options From the command prompt in the directory usr src linux run the command make menuconfig This command will start a text based interface which allows the selection of build time parameters From the options presented select Code maturity level options Prompt for development and or incomplete drivers Console drivers options Frame buffer support Support for frame buffer devices EXPERIMENTAL EPSON LCD CRT TV controller support EPSON S
322. ilities are configurable for different panel types using a program called 13705CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13705 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the NEC VR4102 VR4111 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 008 02 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents NEC VR4102 VR4111 64 32 bit Microprocessor Preliminary User s Manual e Epson Research and Development Inc D13705 Embedded Memory Color LCD Controller Hardware Functional Specification Document Number X27A A 001 xx e Epson Research and Development Inc S5UI13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X27A G 005 xx Epson Research and Development Inc S1D13705 Programming Notes and Examples Document Number X27A G 002 xx 6 2 Document Sources e NEC website http www nec com e Epson Electronics America website http www eea epson com S1D13705 Interfacing to the NEC VR4102 VR4111 Microprocessor X27A G 008 02 Issue Date 01 02 13 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD Controllers S1D13705 Japan Seiko Epson Corporat
323. improves display performance For ex ample slider bars appear more smooth when using off screen memory To enable or disable the use of off screen memory edit the file x wince300 platform cepc driv ers display S 1D13705 sources In SOURCES there is a line which when uncom mented will instruct Windows CE to use off screen display memory if sufficient display memory is available CDEFINES CDEFINES DEnablePreferVmem 3 In the file PROJECT REG under CE 3 0 there is a key called PORepaint search the Windows CE directories for PROJECT REG PORepaint is relevant when the Sus pend state is entered or exited PORepaint can be set to 0 1 or 2 as described below a PORepaint 0 e This mode tells Windows CE not to save or restore display memory on sus pend or resume Windows CE 3 x Display Drivers 1D13705 Issue Date 01 05 25 X27A E 006 01 Page 14 S1D13705 X27A E 006 01 Epson Research and Development Vancouver Design Center Since display data is not saved and not repainted this is the FASTEST mode Main display data in display memory must NOT be corrupted or lost on sus pend The memory clock must remain running Off screen data in display memory must NOT be corrupted or lost on sus pend The memory clock must remain running This mode cannot be used if power to the display memory is turned off PORepaint 1 This is the default mode for Windows CE This mode tells Windows CE to save the main display dat
324. in lilo if running lilo Linux Console Driver S1D13705 Issue Date 01 09 19 X27A E 004 02 Page 6 Epson Research and Development Vancouver Design Center 7 Boot to the Linux operating system If you are using lilo Linux Loader modify the lilo configuration file as discussed in the kernel build README file If there were no errors during the build from the com mand prompt run lilo and reboot your system Note In order to use the S1D13705 console driver with X server you need to configure the X server to use the FBDEV device A good place to look for the necessary files and in structions on this process is on the Internet at www xfree86 org S1D13705 Linux Console Driver X27A E 004 02 Issue Date 01 09 19 Epson Research and Development Page 7 Vancouver Design Center Building the Console Driver for Linux Kernel 2 4 x Linux Console Driver Issue Date 01 09 19 Follow the steps below to construct a copy of the Linux operating system using the S1D13705 as the console display device These instructions assume that the GNU devel opment environment is installed and the user is familiar with GNU and the Linux operating system 1 Acquire the Linux kernel source code You can obtain the Linux kernel source code from your Linux supplier or download the source from ftp ftp kernel org The S1D13705 reference driver requires Linux kernel 2 4 x or greater The example S1D13705 reference driver available on www erd epson com
325. in the directory x Tornado target config pcPentium type mkboot a bootrom_uncmp 5 Ifnecessary generate a new mode0 h configuration file The file mode0 h contains the register values required to set the screen resolution col or depth bpp display type rotation etc The mode0 h included with the drivers sets the display for 256x64 190 Hz output to an LCD display If this setting is inappropriate then mode0 h must be regenerated The configuration program 13705CFG can be used to build a new mode0 h file Place the new mode0 h file in x 13705 8bpp File Wind River UGL v1 2 Display Drivers X27A E 003 02 Issue Date 01 02 13 Epson Research and Development Page 5 Vancouver Design Center Note Mode0 h should be created using the configuration utility 13705CFG For more infor mation on 13705CFG see the 13705CFG Configuration Program User Manual docu ment number X27A B 001 xx available at www erd epson com 6 Open the 1D13705 workspace From the Tornado tool bar select File gt Open Workspace gt Existing gt Browse and select the file x 13705 8bpp 13705 wsp 7 Add support for single line comments The UGL v1 2 display driver source code uses single line comment notation rather than the ANSI conventional comments P To add support for single line comments follow these steps a In the Tornado Workspace window click on the Builds tab b Expand t
326. in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Motorola MPC821 Microprocessor X27A G 010 02 Issue Date 01 02 13 Epson Research and Development Page 3 Vancouver Design Center Table of Contents ft introd ction a oar e a AR AA AR A A 7 2 Interfacing to the MPC621 00000 2 a E a aS 8 2 1 The MPC8xx System Bus e eaa a a a a e 8 2 2 MPC821 Bus Overview oos is soa s 1 1 ee 8 2 2 1 Normal Non Burst Bus Transactions 1 0 0 0 0 eee ee es 9 2 22 Burst yc iii al A rg A Ae ade oD ae te eat 10 2 3 Memory Controller Module e a A leo Yo 2 3 1 General Purpose Chip Select Module le GPCM O eerie se 11 2 3 2 User Programmable Machine UPM o o 002 5005 12 3 S1D13705 Host Bus Interface lt 13 3 1 Host Bus Interface Modes rta ee ee 13 3 2 Generic 1 Host Bus Interface Mode 2 2 2 2 2 22 2 22 242 242 14 4 MPC821 to S1D13705 Interface lt es 15 4 1 Hardware Description LS Bc ds ems he Ae E AS 4 2 MPC821ADS Evaluation Board Hardware Connections 16 4 3 S1D13705 Hardware Configuration 2 2 2 2 2 2 18 4 4 M
327. ing Notes and Examples X27A G 002 03 Issue Date 02 01 22 ET ZO TO 1 93tg 91 18 91 4g Ppy eS ppy Hels UsaJos z Uaelos MY 404431 SSSIPppe Ol 4a1si93y M0744340 SSIY0AY LEVIS N3349S y0L1938 618 orug hua zbug erua plug SL 18 SSAJPPY PIOM URIS Z Uaalos MY 443444 Ssesppe Ol ASW U3LSIO3Y SS3UAUIY GHOM LYvLS Z N3349S 440 93H bug S 18 9118 gt 19 0 H934 luqolo3u 30 934 sseuppy p10m HEIS Z U39195 My 433441 Sselppe Ol S7 431SI93Y SS3YADY GHOM LEVIS Z N3349S 430 938H gua 618 0118 LL 18 zl 18 elu plug Siua SSOIPPY PIOM HEJS USaJos panesal L E l ME 43444 Sseuppe OI ASIN 431S1934 SSIUAUY AYOM Luvs N3auos YqO DaY 9XId 194 119 v apeys e19 9L 0 i 9XI 194 18 Z apeys eID y a oud Lug zug eug vig gua 918 ug 9XId 19d 18 L apeys elo z 0 1 a ology Tucolo3u luoolO34 sseuppy PioM HeIS uaalos 9XId 19d 18 8 S10 0D 99Z i MY 493444 Sseuppe O S7 8a1SI03Y Ss34ady GHOM LUVLS N3389S 490 93H t 9XId 194 119 y S10 0D 9 0 9XIg 19 4 1 siojo L oud Lua cua e 18 vid sua eu e l Xid d 49 Z 109 y Ib 7 Pudo Pe
328. interface UDS and LDS upper and lower data strobes have been replaced by some new signals intended to simplify the task of interfacing to typical memory and peripheral devices The MC68EC00O0 bus control signals are well documented in Motorola s user manuals and will not be described here A brief summary of the new signals appears below Output Enable OE is asserted when a read cycle is in process it is intended to connect to the output enable control of a typical static RAM EPROM or Flash EPROM device e Upper Write Enable and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus they may be directly connected to the write enable inputs of a typical memory device The S1D13705 implements the MC68000 bus interface using its MC68K 1 mode but this mode requires the MC68EC000 control signals UDS and LDS so this mode cannot be used to connect the MC68EZ328 directly to the S1D13705 However the Generic 1 interface mode on the 1D13705 is well suited to interface to the MC68EZ328 3 2 Chip Select Module S1D13705 X27A G 007 04 The MC68EZ328 can generate up to 8 chip select outputs organized into four groups A through D Each chip select group has a common base address register and address mask register to set the base address and block size of the entire group In addition each chip select within a group has its own address compare and ad
329. interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the VR4102 VR4111 control signals The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WE1F is the high byte enable for both read and write cycles WEO is the write enable for the S1D13705 to be driven low when the host CPU is writing data to the S1D13705 RD is the read enable for the S1D13705 to be driven low when the host CPU is reading data from the S1D13705 WAIT is a signal which is output from the S1D13705 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display updat
330. interface signals are controlled by the sequencing logic When this bit 1 LCDPWR is forced to off and the panel interface signals are forced low immediately upon entering power save mode See Section 7 3 2 Power Down Up Timing on page 37 for further information bit 2 Hardware Power Save Enable When this bit 1 GPIOO is used as the Hardware Power Save input pin When this bit 0 GPIOO operates normally Table 8 5 Hardware Power Save GPIOO Operation Hardware Power GPIOO RESET Save Enable aRIOg Contig Status Control GPIOO Operation State REG 18h bit 0 REG 03h bit 2 REG 19h bit 0 0 X Xx Xx a GPIOO Input 1 0 0 reads pin status high impedance 1 0 1 0 GPIOO Output 0 1 0 1 1 GPIOO Output 1 Hardware Power Save i ds s Input active high bits 1 0 Software Power Save Bits 1 0 These bits select the Power Save Mode as shown in the following table Table 8 6 Software Power Save Mode Selection Bit 1 Bit 0 Mode 0 0 Software Power Save 0 1 reserved 1 0 reserved 1 1 Normal Operation Refer to Section 13 Power Save Modes on page 82 for a complete description of the power save modes Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 60 Epson Research and Development Vancouver Design Center REG 04h Horizontal Panel Size Register Address 1FFE4h Read Write Hori
331. inverted using an inverter enabled by CS to make it an active high signal and thus compatible with the MC68328 architecture A single resistor is used to pull up the WAIT DTACK signal when terminating the bus cycle The following diagram shows a typical implementation of the MC68328 to S1D13705 using the Generic 1 host bus interface For further information on the Generic 1 host bus interface and AC Timing refer to the 1D13705 Hardware Functional Specification document number X27A A 001 xx Note MC68328 1D13705 A 16 0 gt AB 16 0 D 15 0 p DB 15 0 CSB3 CSH Voc Na BS 1K DTACK WAIT UWE gt WE1 LWE WEO OE gt RD WR MERA RD CLKO gt BUSCLK System RESET gt RESET When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 2 2 Typical Implementation of MC68328 to SID13705 Interface Generic 1 Interfacing to the Motorola Dragonball Family of Microprocessors 1D13705 Issue Date 01 02 13 X27A G 007 04 Page 14 Epson Research and Development Vancouver Design Center 2 4 2 S1D13705 Hardware Configuration The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge
332. ion Usage S1D13705 X27A B 002 02 Epson Research and Development Vancouver Design Center PC Intel Platform For 16 Bit Program Version copy the file 13705SHOW EXE to a directory that is in the DOS path on your hard drive For 32 Bit Program Version install the 32 bit Windows device driver S1D13X0X VXD as described in the S1D13X0X 32 Bit Windows Device Driver Installation Guide document number X00A E 003 xx Copy the file 13705SHOW EXE to a directory that is in the DOS path on your hard drive Embedded Platform Download the program 13705SHOW to the system PC platform at the prompt type 13705show a b n 1 p alt vertical noinit Embedded platform execute 13705show and at the prompt type the command line argument s Where a automatically cycle through all video modes b starts 13705SHOW at a user specified bit per pixel bpp level where can be 1 2 4 or 8 1 set landscape mode p set portrait mode alt use alternate portrait mode vertical displays vertical line pattern update continuously update display memory noinit bypass register initialization and use values which are currently in the registers displays the help screen 13705SHOW Demonstration Program Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center Comments e The alt command line switch can only be used with the p portrait mode switch This switch will have
333. ion Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 NEC Electronics Inc NEC Electronics Inc U S A Santa Clara California Tel 800 366 9782 Fax 800 729 9288 http A www nec com North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Interfacing to the NEC VR4102 VR4111 Microprocessor Issue Date 01 02 13 Page 17 Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 1D13705 X27A G 008 02 Page 18 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the NEC VR4102 VR4111 Microprocessor X27A G 008 02 Issue Date 01 02 13 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the PC Card Bus Document Number X27A G 009 02 Copyright O 2001 Epson
334. is e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte 3 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping cel Generic 1 AB 15 1 A 15 1 ABO AO DB 15 0 D 15 0 WE1 WE1 CS External Decode BCLK BCLK BS connect to Vss RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx 1D13705 X27A G 007 04 Page 18 Epson Research and Development Vancouver Design Center 3 3 2 Generic 1 Interface Mode S1D13705 X27A G 007 04 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13705 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13705 host interface It is sepa rate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC
335. is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Philips MIPS PR31500 PR31700 Processor X27A G 012 02 Issue Date 01 02 13 Epson Research and Development Page 3 Vancouver Design Center Table of Contents 1 introduction s e sao A AR A AR a A A 7 Interfacing to the PR31500 PR31700 8 S1D13705 Host Bus Interface 9 3 1 Host Bus Pin Connection 9 3 2 Generic Hl Interface Mode 2 0 2 8 6 4 6 24 10 3 3 Generic 2 Interface Mode 2 2 2 26 26 11 4 Direct Connection to the Philips PR31500 PR31700 12 4 1 General Description a a a ee ee LA 4 2 Memory Mapping and Aliasing 2 13 4 3 1D13705 Configuration and Pin Mapping 2 2 2 2 2 2 2 2 14 5 Using the ITE IT8368E PC Car
336. isplay capability with very low power consumption The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the NEC VR4102 VR4111 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 008 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the NEC VR4102 VR4111 2 1 The NEC VR4102 VR4111 System Bus 2 1 1 Overview S1D13705 X27A G 008 02 The VR Series family of microprocessors features a high speed synchronous system bus typical of modern microprocessors Designed with external LCD controller support and Windows CE based embedded consumer applications in mind the VR4102 VR4111 offers a highly integrated solution for portable systems This section is an overview of the operation of the CPU bus to establish interface requirements The NEC VR4102 VR4111 is designed around the RISC architecture developed by MIPS This microprocessor is designed around the 66MHz VR4100 CPU core which supports 64 bit processing The CPU communicates with the Bus Control Unit BCU with its internal SysAD bus The BCU in turn communicates w
337. isplay memory power is going to be turned off when the system is suspended and there is not enough system memory to save the im age Any off screen data in display memory is LOST and since there is insuffi cient system memory to save display data off screen memory usage MUST be disabled When the system is resumed WinCE instructs all running applications to re paint themselves This is the SLOWEST of the three modes Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 15 Vancouver Design Center Simple Display Driver Configuration The following display driver configuration should work with most platforms running Windows CE This configuration disables the use of off screen display memory and forces the system to redraw the main display upon power on 1 This step disables the use of off screen display memory Edit the file x wince300 platform cepc drivers display S 1D13705 sources and change the line CDEFINES CDEFINES DEnablePreferVmem to CDEFINES CDEFINES DEnablePreferVmem 2 This step causes the system to redraw the main display upon power on This step is only required if display memory loses power when Windows CE is shut down If dis play memory is kept powered up set the S1D13705 in powersave mode then the dis play data will be maintained and this step can be skipped Search for the file PROJECT REG in your Windows CE directories and inside PROJECT REG find the ke
338. ist Select NO I WANT TO SELECT THE HARDWARE FROM A LIST and click NEXT 5 From the list select OTHER DEVICES and click NEXT 6 Click HAVE DISK and type the path to the driver files or select browse to find the driver 7 Click OK 8 The driver will be identified as EPSON PCI Bridge Card Click NEXT 9 Click FINISH S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 6 Windows 95 OSR2 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Windows will detect the card as a new PCI Device and launch the UPDATE DEVICE DRIVER wizard If The Driver is on Floppy Disk 3 4 5 6 Place the disk into drive A and click NEXT Windows will find the EPSON PCI Bridge Card Click FINISH to install the driver Windows will ask you to restart the system If The Driver is not on Floppy Disk 3 4 10 11 12 13 14 15 16 17 Click NEXT Windows will search the floppy drive and fail Windows will attempt to load the new hardware as a Standard VGA Card Click CANCEL The Driver must be loaded from the CONTROL PANEL under ADD NEW HARDWARE Select NO for Windows to DETECT NEW HARDWARE Click NEXT Select OTHER DEVICES from HARDWARE TYPE and Click NEXT Click HAVE DISK Specify the location of the driver and click OK Click OK
339. ith external devices with its ADD and DAT buses that can be dynamically sized to 16 or 32 bit operation The NEC VR4102 VR4111 has direct support for an external LCD controller Specific control signals are assigned for an external LCD controller that provide an easy interface to the CPU A 16M byte block of memory is assigned for the LCD controller with its own chip select and ready signals available Word or byte accesses are controlled by the system high byte signal SHB Interfacing to the NEC VR4102 VR4111 Microprocessor Issue Date 01 02 13 Epson Research and Development Page 9 Vancouver Design Center 2 1 2 LCD Memory Access Cycles Once an address in the LCD block of memory is placed on the external address bus ADD 25 0 the LCD chip select LCDCS is driven low The read or write enable signals RD and WR are driven low for the appropriate cycle LCDRDY is driven low by the S1D13705 to insert wait states into the cycle The high byte enable is driven low for 16 bit transfers and high for 8 bit transfers Figure 2 1 NEC VR4102 VR4111 Read Write Cycles on page 9 shows the read and write cycles to the LCD Controller Interface TCLK f AUS RM 2 UU RN ADD 25 0 VALID SHB x LCDCS WR RD D 15 0 write VALID a Hi Z O y LCDRDY Figure 2 1 NEC VR4102 VR4111 Read Write Cycles Interfacing to the NEC VR4102 VR4111 Microprocessor 1D13705 I
340. ith the PC via a parallel port connection or an Ethernet connection 1D13705 Supported Evaluation Platforms 13705SPLT Display Utility Issue Date 01 02 12 13705SPLT has been tested with the following S1D13705 supported evaluation platforms e PC system with an x86 processor Both 16 bit and 32 bit code is supported e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13705 Programming Notes and Examples manual document number X26A G 002 xx S1D13705 X27A B 003 02 Page 4 Installation Usage S1D13705 X27A B 003 02 Epson Research and Development Vancouver Design Center PC Intel Platform For 16 Bit Program Version copy the file 13705SPLT EXE to a directory that is in the DOS path on your hard drive For 32 Bit Program Version install the 32 bit Windows device driver S1D13X0X VXD as described in the S1ID13X0X 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 xx Copy the file 13705SPLT EXE to a directory that is in the DOS path on your hard drive Embedded Platform Download the program 13705SPLT to the system PC platform at the prompt type 13705SPLT a Embedded platform execute 13705spl1t and at the prompt type the command line argument Where no argument enables man
341. ithout high performance CPU to video memory speeds are slower and the S1D13705 uses less power Parameters OnOff a boolean value defined in HAL H to indicate whether to enable of disable high performance Return Value ERR_OK operation completed with no problems 9 4 3 Advanced HAL Functions Advanced HAL functions include the functions to support split virtual and rotated displays While the concept for using these features is advanced the HAL makes actually using them easy int seSetPortraitMethod int Style Description This selects the portrait mode method to be used when seSetHWRotate is called to put the 1D13705 into portrait mode Parameters Style call with style set to DEFAULT 1 to select Default Portrait Mode call with style set to any other value to select Alternate Portrait Mode Return Value ERR_OK operation completed with no problems ERR_FAILED the operation failed int seSetHWRotate int Rotate Description This function sets the rotation scheme according to the value of Rotate When portrait mode is selected as the display rotation the scheme selected is the non X2 scheme Parameters Rotate the direction to rotate the display Valid arguments for Rotate are LANDSCAPE and PORTRAIT Return Value ERR_OK operation completed with no problems ERR_FAILED the operation failed to complete The most likely reason for failing to set a rotate mode is an inability to set the desired fram
342. itry to detect the assertion of BDIP and respond with BI if caching is accidently enabled for the S1D13705 address space 2 3 Memory Controller Module 2 3 1 General Purpose Chip Select Module GPCM The General Purpose Chip Select Module GPCM is used to control memory and peripheral devices which do not require special timing or address multiplexing In addition to the chip select output it can generate active low Output Enable OE and Write Enable WE signals compatible with most memory and x86 style peripherals The MPC821 bus controller also provides a Read Write RD WR signal which is compatible with most 68K peripherals The GPCM is controlled by the values programmed into the Base Register BR and Option Register OR of the respective chip select The Option Register sets the base address the block size of the chip select and controls the following timing parameters The ACS bit field allows the chip select assertion to be delayed with respect to the address bus valid by 0 4 or Y clock cycle The CSNT bit causes chip select and WE to be negated clock cycle earlier than normal The TRLX relaxed timing bit will insert an additional one clock delay between asser tion of the address bus and chip select This accommodates memory and peripherals with long setup times The EHTR Extended hold time bit will insert an additional 1 clock delay on the first access to a chip select Up to 15 wait states may be inserted
343. ize to zero results in one line of screen 1 being displayed The remainder of the display will be screen 2 image Screen must be set to 1 or 2 or use the constants SCREEN or SCREEN2 VisibleScanlines number of lines to display for the selected screen ERR_OK operation completed with no problems ERR_HAL_BAD_ARG argument VisibleScanlines is negative or is greater than vertical panel size or WhichScreen is not SCREEN1 or SCREEN 2 Changing the number of lines for one screen will also change the number of lines for the other screen seSplitInit must be called before calling seSplitScreen Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 57 Vancouver Design Center int seVirtInit DWORD VirtX DWORD VirtY Description This function prepares the system for virtual screen operation The programmer passes the desired virtual width in pixels When the routine returns VirtY will contain the maximum number of line that can be displayed at the requested virtual width Parameter VirtX horizontal size of virtual display in pixels Must be greater or equal to physical size of display VirtY pointer to an integer to receive the maximum number of displayable lines of VirtX width Return Value ERR_OK operation completed with no problems ERR _HAL_BAD_ARG returned in three situations 1 the virtual width VirtX is greater than the largest possible width VirtX varies with color depth a
344. l data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the S1D13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the 1D13705 for Generic 1 mode and should be tied low connected to GND Interfacing to the Toshiba MIPS TMPR3912 Microprocessor Issue Date 01 02 13 Epson Research and Development Page 11 Vancouver Design Center 3 3 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13705 The Generic 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the TMPR3912 control signals The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respec
345. lay Figure 5 1 Viewport Inside a Virtual Display Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 26 5 1 1 Registers Epson Research and Development Vancouver Design Center REG 11h Memory Address Offset Register Memory Memory Memory Memory Memory Memory Memory Memory Address Address Address Address Address Address Address Address Offset Offset Offset Offset Offset Offset Offset Offset Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O 5 1 2 Examples S1D13705 X27A G 002 03 Memory Address Offset Register REG 11h forms an 8 bit value called the Memory Address Offset This offset is the number of additional words on each line of the display If the offset is set to zero there is no virtual width Note This value does not represent the number of words to be shown on the display The dis play width is set in the Horizontal Display Width register Example 1 In this example we go through the calculations to display a 640x480 im age on a 320x240 panel at 2 bpp Step 1 Calculate the number of pixels per word for this color depth At 2 bpp each byte is comprised of 4 pixels therefore each word contains 8 pixels pixels_per_word 16 bpp 16 2 8 Step 2 Calculate the Memory Address Offset register value We require a total of 640 pixels The horizontal display register will account for 320 pixels this leaves 320 pixels for the Memory Address Offset
346. lculated using the current virtual width If the number of possible lines is less than the physical display size this message is displayed Try restarting the program and manually specify a smaller virtual width 13705VIRT Display Utility Issue Date 01 02 12 EPSON 1D13705 Embedded Memory LCD Controller 13705PLAY Diagnostic Utility Document No X27A B 005 04 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705PLAY Diagnostic Utility X27A B 005 04 Issue Date 01 07 04 Epson Research and Development Page 3 Vancouver Design Center 13705PLAY 13705PLAY is a utility which allows the user to easily read write the S1D13705 registers Look Up Table and display memory The user interface for 13705PLA Y is similar to the DOS DEBUG p
347. lding the LIBSE library for SH3 target example In the LIBSE files there are three main types of files e C files that contain the library functions e assembler files that contain the target specific code e makefiles that describe the build process to construct the library The C files are generic to all platforms although there are some customizations for targets in the form of ifdef LCEVBSH3 code the ifdef used for the example SH3 target Low Cost Eval Board SH3 The majority of this code remains constant whichever target you build for The assembler files contain some platform setup code stacks chip selects and jumps into the main entry point of the C code that is contained in the C file entry c For our example the assembler file is STARTSH3 S and it performs only some stack setup and a jump into the code at _mainEntry entry c In the embedded targets printf in file rprintf c putchar putchar c and getch kb c resolve to serial character input output For SH3 much of the detail of handling serial IO 1s hidden in the monitor of the evaluation board but in general the primitives are fairly straight forward providing the ability to get characters to from the serial port For our target example the nmake makefile is makesh3 mk This makefile calls the Gnu compiler at a specific location TOOLDIR enumerates the list of files that go into the target and builds a a library file as the output of the build process With nmak
348. le Ek driven This allows for clear commenting It is more efficient to RG loop through the array writing each element to a control register 3 The array of register values as produced by 13705CFG EXE is included EN here I write the registers directly rather than refer to the register ae array in the sample code kk kk include lt conio h gt include lt windows h gt include lt winioctl h gt include ioctl h Look Up Table 16 of 256 elements For this sample only the first sixteen LUT elements are set af unsigned char LUT 16 3 0x00 0x00 Ox00 BLACK 0x00 0x00 OxA0 BLUE Ko 0x00 OxAO 0x00 GREEN 0x00 OxAO 0xA0 CYAN R P 0xA0 0x00 0x00 7 0xA0 0x00 OxA0 El D RP LI el S1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 69 Vancouver Design Center OxA0 0xA0 0x00 YELLOW OxA0 OxA0 OxAO WHITE 0x00 0x00 0x00 BLACK 0x00 0x00 OxFO LT BLUE 0x00 OxFO 0x00 LT GREEN 0x00 OxFO OxF0O LT CYAN OxFO 0x00 Ox00 LT RED OxFO 0x00 OxFO LT PURPLE OxFO OxFO 0x00 LT YELLOW OxFO OxFO OxFO LT WHITE y Register data These values were generated using 13705CFG EXE The sample code
349. les Issue Date 02 01 22 Epson Research and Development Page 45 Vancouver Design Center FrameRate A me HDP HNDP x VDP VNDP 16 000 000 2 FrameRate 320 88 x 240 3 80 69 For this example the Horizontal Non Display register REG 08h needs to be set to 07h and the Vertical Non Display register REG OAh needs to be set to 03h The 16 000 000 2 in the formula above represents the input clock being divided by two when this alternate portrait mode is selected With the values given for this example we must ensure the Input Clock Divide bit REG 02h b4 is reset with the given values it was likely set as a result of the frame rate calculations for landscape display mode No other registers need to be altered The display is now configured for portrait mode use Offset zero of display memory corre sponds to the upper left corner of the display Display memory is accessed exactly as it was for landscape mode As this is the alternate portrait mode the power of two stride issue encountered with the default portrait mode is no longer an issue The stride is the same as the portrait mode width In this case 120 bytes Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 46 S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center Example 8 Pan the above portrait mode image to the right by 4 pixels then scroll it up by 6 pixels To pan by four pix
350. low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the 1D13705 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update 1t is possible that contention may occur in accessing the S1D13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the 1D13705 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Vancouver Design Center Page 25 4 3 3 MC68K 1 Interface Mode Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 The MC68K 1 Interface Mode can be used to interface to the MC68VZ328 micropro cessor if the previously mentioned multiplexed bus signals will not be used for other purposes The interface requir
351. lse width low 4 Ts t11 Shift Pulse pulse width high 4 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 4 Ts t13 FPDATT 7 0 hold to Shift Pulse falling edge 4 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts 1 Ts pixel clock period 2 Umin t8min 9Ts 3 18min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 x 2 Ts 5 t6min REG 08h bits 4 0 x 2 x 8 20 Ts 6 t min REG 08h bits 4 0 x 2 x 8 29 Ts Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 50 7 3 9 Dual Color 8 Bit Panel Timing Epson Research and Development Vancouver Design Center VDP VNDP la rie gt FPFRAME FPLINE l f f l l l l f l l l DRDY MOD Y y FPDAT 7 0 LINE 1 241 Xune 2 242 X LINE 239 479XLINE 240 480 A LINE 1 241 X FPLINE DRDY MOD la HDP gt j HNDP gt ene a A E A e a FPDAT7 1 R1 X 1 2 X 1 83 X 1 R5 X 1 G6 Y 1 87 Eeg 1 8639 L X FPDAT6 aX 1 B2 X 1 R4 X as X 1 86 X 1 R8 E X 1 R640 X FPDAT5 1181 X 1R3 X 1 44 X 1B5 X ar Y 168 A y 1 G640 k FPDAT4 JA 1 R2 X 163 X 1284 X_1 R6 X 1 67 X 1 B8 HU Y 1 B640 X FPDAT3 241 r1X241 62241 B3X241 R5N241 G0 241 B7L A Y EA KX FPDAT2 Aeat G1X241 B2X241 R4 241 G5X241 B6 241 R8 A X FPDAT1 241 B1X241 R3X241 G4 241 B5 241 R7X
352. mmary of Power On Reset Options and Table 4 2 Host Bus Interface Selection shows the settings used for the S1D13705 in this interface Table 4 1 Summary of Power On Reset Options value on this pin at the rising edge of RESET is used to configure 0 1 S1D1370 5 Pin Name 0 l CNFO CNF1 See Host Bus Selection table below CNF2 CNF3 Little Endian a configuration for MFC5307 support See Host Bus Selection table below Table 4 2 Host Bus Interface Selection CNFO BS Host Bus Interface CNF2 CNF1 configuration for MFC5307 support S1D13705 Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 13 X27A G 011 02 Epson Research and Development Page 15 Vancouver Design Center 4 3 MCF5307 Chip Select Configuration Chip Selects O and 1 have programmable block sizes from 64K bytes through 2G bytes However these chip selects would normally be needed to control system RAM and ROM Therefore one of the IO chip selects CS2 through CS7 is required to address the entire address space of the S1D13705 These IO chip selects have a fixed 2M byte block size In the example interface chip select 4 is used to control the S1D13705 The S1D13705 only uses a 128K byte block with its 80K byte display buffer residing at the start of this 128K byte block and its internal registers occupying the last 32 bytes of this block This block of memory will be shad
353. mode 5U13704 5 TMPR3912 22U CPU Module X00A G 004 02 Issue Date 01 03 07 EPSON Research and Development Page 9 Vancouver Design Center 2 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13704 5 The Generic 2 interface mode was chosen for this interface due to its compatibility with the PC Card interface The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13704 5 BUSCLK is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB15 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper memory address space WE1F is the high byte enable for both read and write cycles and WEO is the enable signal for a write access These must be generated by external decode hardware based upon the control outputs from the host CPU RD is the read enable for the S1D13704 5 to be driven low when the
354. modes less than 8 bpp to toggle the high performance bit on or off AAA ee A seSplitInit Initialize split screen variables and setup start addresses seSplitScreen Set the size of either the top or bottom screen seVirtInit Initialize virtual screen mode setting x and y sizes seVirtMove pan scroll the virtual screen surface s AAA eee seSetHWRotate Set the hardware rotation to either Portrait or Landscape seSetPortraitMethod Call before setting hardware portrait mode to set either Default or Alternate Portrait Mode Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 50 Epson Research and Development Vancouver Design Center Table 9 1 HAL Functions Continued Function Description seSetReg Write a Byte value to the specified S1D13705 register seGetReg Read a Byte value from the specified S1D13705 register seWriteDisplayBytes Write one or more bytes to the display buffer at the specified offset seWriteDisplayWords Write one or more words to the display buffer at the specified offset seWriteDisplayDwords Write one or more dwords to the display buffer at the specified offset seReadDisplayByte Read a byte from the display buffer from the specified offset seReadDisplayWord Read a word from the display buffer from the specified offset seReadDisplayDword Read a dword from the display buffer from the specified offset seSetLut Write to the Look Up Table LUT entries st
355. n Center Page 13 The host interface control signals of the S1D13705 are asynchronous with respect to the S1D13705 bus clock This gives the system designer full flexibility to choose the appro priate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether an external or internal clock divider is needed should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13705 clock frequencies The S1D13705 also has internal clock dividers providing additional flexibility 4 2 S1D13705 Hardware Configuration The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the 1D13705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show those configuration settings important to the Generic 2 host bus interface Table 4 1 Summary of Power On Reset Options Signal value on this pin at the rising edge of RESET is used to configure 0 1 0 1 CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 CNF3 Big Endian configuration for NEC VR4181A support Table 4 2 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus Interface E configuration for NEC VR4181A support Interfacing to the NEC VR4181A Microprocessor 1D137
356. n page 22 for summary CS 74 Input This pin inputs the chip select signal BCLK l 71 Input This pin inputs the system bus clock BS l 75 CS Input This pin has multiple functions For SH 3 SH 4 mode this pin inputs the bus start signal BS For MC68K 1 this pin inputs the address strobe AS For MC68K 2 this pin inputs the address strobe AS e For Generic 1 this pin must be tied to Vss e For Generic 2 this pin must be tied to lO Vpp See Table 5 2 Host Bus Interface Pin Mapping on page 22 for summary RD WR 79 CS Input This pin has multiple functions e For SH 3 SH 4 mode this pin inputs the RD WR4 signal The S1D13705 needs this signal for early decode of the bus cycle For MC68K 1 this pin inputs the R W signal For MC68K 2 this pin inputs the R W signal For Generic 1 this pin inputs the read command for the upper data byte RD1 For Generic 2 this pin must be tied to lO Vpp See Table 5 2 Host Bus Interface Pin Mapping on page 22 for summary Hardware Functional Specification Issue Date 02 02 01 S1D13705 X27A A 001 10 Page 20 Epson Research and Development Vancouver Design Center Pin Names Type Pin Cell RESET State Description RD 76 CS Input This pin has multiple functions e For SH 3 SH 4 mode this pin inputs the read sign
357. n programs REG 03h bits 1 0 to 11b This starts the power up sequence as shown The power up power down sequence delay is 127 frames The Look Up Table registers may be programmed any time after REG 03h bits 1 0 11b The power up power down sequence also occurs when exiting entering Software Power Save Mode BCLK may be turned off held low between accesses if the following rules are observed 1 BCLK must be turned off on in a glitch free manner 2 BCLK must continue for a period equal to 8Tpc_K 12Tuc1 kx after the end of the access RD Y asserted or WAIT deasserted 3 BCLK must be present for at least one Tc k before the start of an access Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center 13 6 Clock Requirements Page 85 The following table shows what clock is required for which function in the S1D13705 Table 13 5 S1D13705 Internal Clock Requirements Function BCLK CLKI Register Read Write Is required during register accesses BCLK can be shut down between accesses allow eight BCLK pulses plus 12 MCLK pulses 8TgcLk 12 Tuck after the last access before shutting BCLK off Allow one BCLK pulse after starting up BCLK before the next access Not Required Memory Read Write Is required during memory accesses BCLK can be shut down between accesses allow eight BCLK pulses plus 12 MCLK pulses 8Tgcik 12 Tuck after th
358. nd display buffer through the HAL int seGetReg int Index BYTE pValue Description Reads the value in the register specified by index Parameters Index register index to read pValue pointer to a BYTE to receive the register value Return Value ERR_OK operation completed with no problems int seSetReg int Index BYTE Value Description Writes value specified in Value to the register specified by Index Parameters Index register index to set Value value to write to the register Return Value ERR_OK operation completed with no problems int seReadDisplayByte DWORD Offset BYTE pByte Description Reads a byte from the display buffer at the specified offset and returns the value in pByte Parameters Offset offset in bytes from start of the display buffer to read from pByte pointer to a BYTE to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater 80 kb int seReadDisplayWord DWORD Offset WORD pWord Description Reads a word from the display buffer at the specified offset and returns the value in pWord Parameters Offset offset in bytes from start of the display buffer to read from pWord pointer to a WORD to return the value in Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG if the value for Addr is greater than 80 kb 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02
359. nd Development Page 25 Vancouver Design Center 5 Advanced Techniques This section contains programming suggestions for the following e virtual display e panning and scrolling e split screen display 5 1 Virtual Display Virtual display refers to the situation where the image to be viewed is larger than the physical display The difference can be in the horizontal vertical or both dimensions To view the image the display is used as a window into the display buffer At any given time only a portion of the image is visible Panning and scrolling are used to view the full image The Memory Address Offset register determines the number of horizontal pixels in the virtual image The offset register can be used to specify from 0 to 255 additional words for each scan line At 1 bpp 255 words span an additional 4 080 pixels At 8 bpp 255 words span an additional 510 pixels The maximum vertical size of the virtual image is the result of dividing 81920 bytes of display memory by the number of bytes on each line i e at 1 bpp with a 320x240 panel set for a virtual width of 640x480 there is enough memory for 1024 lines Figure 5 1 Viewport Inside a Virtual Display depicts a typical use of a virtual display The display panel is 320x240 pixels an image of 640x480 pixels can be viewed by navigating a 320x240 pixel viewport around the image using panning and scrolling 320x240 gt Viewport 640x480 Virtual Disp
360. nd is UNTESTED This option should remain disabled unless you are performing specific debugging tasks that require the debug monitor Windows CE 3 x Display Drivers 1D13705 Issue Date 01 05 25 X27A E 006 01 Page 12 GrayPalette Mode File S1D13705 X27A E 006 01 Epson Research and Development Vancouver Design Center This option is intended for the support of monochrome panels only The option causes palette colors to be grayscaled for correct display on a mono panel For use with color panels this option should not be enabled The MODE tables contained in files MODE0 H MODE1 H MODE2 H contain register information to control the desired display mode The MODE tables must be generated by the configuration program 13705CFG EXE The display driver comes with example MODE tables By default only MODEO H is used by the display driver New mode tables can be created using the 13705CFG program Edit the include section of MODE H to add the new mode table If you only support a single display mode you do not need to add any information to the WinCE registry If however you support more that one display mode you should create registry values see below that will establish the initial display mode If your display driver contains multiple mode tables and if you do not add any registry values the display driver will default to the first mode table in your list To select which display mode the display driver should
361. nd line argument Where no argument panning and scrolling is performed manually defaults to virtual width physical width x 2 and maximum virtual height a panning and scrolling is performed automatically 1 Force landscape display mode to be set p Force portrait display mode to be set alt Enable alternate portrait mode Selecting this option implies p W specifies the virtual display width which includes both on screen and off screen size the maximum virtual width not including display area for each display mode is 1 bpp 4096 pixels 2 bpp 2048 pixels 4 bpp 1024 pixels 8 bpp 512 pixels 13705VIRT Display Utility X27A B 004 02 Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center The following keyboard commands are for navigation within the program Manual mode T scrolls up y scrolls down pans to the left gt pans to the right HOME moves the display screen so that the upper right of the virtual screen shows in the upper right of the display END moves the display screen so that the lower left of the virtual screen shows in the lower left of the display Automatic mode any key changes the direction of screen Both modes b changes the color depth bits per pixel ESC exits 13705VIRT 13705VIRT Example 1 Type 13705virt a to automatically pan and scroll 2 Press b to change the bits per pixel from 1 bit per pixel to 2 bits per pixel 3
362. nd ranges from 4096 pixels wider than the panel at 1 bit per pixel down to 512 pixels wider than the panel at 8 bit per pixel 2 the virtual width is less than the physical width or 3 the maximum number of lines becomes less than the physical number of lines Note The system must have been initialized prior to calling seVirtInit int seVirtMove int Screen int x int y Description This routine pans and scrolls the display In the case where split screen operation is being used the Screen argument specifies which screen to move The x and y param eters specify in pixels the starting location in the virtual image for the top left corner of the applicable display Parameter Screen must be set to 1 or 2 or use the constants SCREEN1 or SCREENZ to identify which screen to base calculations on xX new starting X position in pixels y new starting Y position in pixels Return Value ERR_OK operation completed with no problems ERR_HAL_BAD_ARG there are several reasons for this return value 1 WhichScreen is not SCREEN1 or SCREEN2 2 the y argument is greater than the last available line less the screen height Note seVirtInitO must be been called before calling seVirtMove Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 58 Epson Research and Development Vancouver Design Center 9 4 4 Register Memory Access The Register Memory Access functions provide access to the S1D13705 registers a
363. nder U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13XXX 32 Bit Windows Device Driver Installation Guide X00A E 003 04 Issue Date 01 04 17 Epson Research and Development Page 3 Vancouver Design Center S1D13XXX 32 Bit Windows Device Driver Installation Guide This manual describes the installation of the Windows 9x ME NT 4 0 2000 device drivers for the S5U13xxxB00x series of Epson Evaluation Boards The file S1D13XXX VXD is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows 9x ME The file SIDI3XXX SYS is required for using the Epson supplied Intel32 evaluation and test programs for the S1D13xxx family of LCD controllers with Windows NT 4 0 2000 The file S1D13XXX INF is the install script For updated drivers ask your Sales Representative or visit Epson Electronics America on the World Wide Web at www eea epson com Driver Requirements Video Controller S1D13xxx Display Type N A BIOS N A DOS Program No Dos Version N A Windows Program Yes Windows 9x ME NT 4 0 2000 device driver Windows DOS Box N A Windows Full Screen N A 0S 2 N A Installation Windows NT Version 4 0 All evaluation boards require the driver to be ins
364. nels requiring a positive power supply to provide between 23V and 40V 1 45mA a power supply has been provided as an integral part of this design The VDDH power supply can be adjusted by R15 to provide an output voltage from 23V to 40V and is enabled and disabled by the active high 1D13705 control signal LCDPWR inverted externally Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 6 13 CPU Bus Interface Header Strips All of the CPU Bus interface pins of the S1D13705 are connected to the header strips H1 and H2 for easy interface to a CPU Bus other than ISA Refer to Table 4 1 CPU BUS Connector H1 Pinout on page 11 and Table 4 2 CPU BUS Connector H2 Pinout on page 12 for specific settings Note These headers only provide the CPU bus interface signals from the S1D13705 When another host bus interface is selected by CNF 3 0 and BS appropriate external decod ing logic MUST be used to access the S1D13705 Refer to Table 5 1 Host Bus Inter face Pin Mapping on page 13 for connection details S1D13705 S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual X27A G 005 03 Issue Date 01 02 13 Epson Research and Development Vancouver Design Center 7 Parts List Page 19 Item Qty board Designation Part Value Descri
365. nes 160 x 40 6400 Screen 2 requires 6400 bytes 0 to 6399 therefore the start address offset for screen 1 must be 6400 bytes 6400 bytes 3200 words C80h words Set the Screen 1 Start Word Address MSB REG ODh to OCh and the Screen 1 Start Word Address LSB REG OCh to 80h 3 Calculate the Screen 2 Start Word Address register values Screen 2 display data is coming from the very beginning of the display buffer All there is to do here is ensure that both the LSB and MSB of the Screen 2 Start Word Address registers are set to zero Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Vancouver Design Center Page 35 6 LCD Power Sequencing and Power Save Modes 6 1 LCD Power Sequencing 6 2 Registers Correct power sequencing is required to prevent long term damage to LCD panels and to avoid unsightly lines during power up and power down Power Sequencing allows the LCD power supply to discharge prior to shutting down the LCD logic signals Proper LCD power sequencing dictates there must be a time delay between the LCD power being disabled and the LCD signals being shut down During power up the LCD signals must be active prior to or when power is applied to the LCD The time intervals vary depending on the power supply design The S1D13705 performs automatic power sequencing in response to both software power save REG 03h or in response to a hardware power save One frame after
366. ng to the PC Card Bus X27A G 009 02 Issue Date 01 02 13 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This application note describes the hardware and software environment required to interface the S1D13705 Embedded Memory LCD Controller and the PC Card PCMCIA bus The designs described in this document are presented only as examples of how such interfaces might be implemented This application note will be updated as appropriate Please check the Epson Electronics America website at http www eea epson com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the PC Card Bus S1D13705 Issue Date 01 02 13 X27A G 009 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the PC Card Bus 2 1 The PC Card System Bus PC Card technology has gained wide acceptance in the mobile computing field as well as in other markets due to its portability and ruggedness This section is an overview of the operation of the 16 bit PC Card interface conforming to the PCMCIA 2 0 JEIDA 4 1 Standard or later 2 1 1 PC Card Overview The 16 bit PC Card provides a 26 bit address bus and additional control lines which allow access to three 64M byte address ranges These ranges are used for common memory space IO space and attribute memory
367. nnection Using an IT8368E Note See Section 3 1 on page 9 and Section 3 2 on page 10 for Generic 1 pin descriptions The Generic 1 host interface control signals of the S1D13705 are asynchronous with respect to the S1D13705 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on pixel and frame rates power budget part count and maximum S1D13705 respective clock frequencies Also internal S1D13705 clock dividers provide additional flexibility Interfacing to the Toshiba MIPS TMPR3912 Microprocessor S1D13705 Issue Date 01 02 13 X27A G 004 02 Page 16 Epson Research and Development Vancouver Design Center 5 2 IT8368E Configuration The IT8368E provides eleven multi function IO pins MFIO The IT8368E must have both Fix Attribute IO and VGA modes on When both these modes are enabled the MFIO pins provide control signals needed by the 1D13705 host bus interface and a 16M byte portion of the system PC Card attribute and IO space is allocated to address the S1D13705 When accessing the S1D13705 the associated card side signals are disabled in order to avoid any conflicts For mapping details refer to section 3 3 Memory Mapping and Aliasing For connection details see Figure 5 1 S1D13705 to TMPR3912 Connection Using an I
368. now on the code is common for Win95 amp WinNT if physaddr 0 Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 76 S1D13705 Epson Research and Development Vancouver Design Center return 1 Arr 0 physaddr Arr 1 4 1024 1024 re DeviceloControl hDriver IOCTL_SED_MAP_PHYSICAL MEMORY gArr 0 2 sizeof ULONG amp retVal sizeof ULONG amp cbReturned NULL 1 re linaddr retVal xx Close the handle This will dynamically UNLOAD the Virtual Device for Win95 xf CloseHandle hDriver if rc return 0 return 1 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Vancouver Design Center 10 3 Header Files Page 77 The header files included here are the required for the HAL sample to compile correctly HAL H Header fil for use with programs written to use the S1D13705 HAL Created 1998 Vanc Copyright c 1998 All Rights Reserve ouver Design Centre 1999 Epson Research and Development Inc d xk El ifndef _HAL H_ define _HAL H_ include hal_regs h i typedef unsigned char BYTE typedef unsigned short WORD typedef unsigned long DWORD typedef unsigned int UINT typedef int BOOL ifdef INTEL typedef BYTE far LPBYTE typedef WORD far LPWORD typedef UINT far LPUINT type
369. nterface connectors For more information regarding the S1D13705 refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx 1 1 Features 80 pin QFP14 package SMT technology for all appropriate devices 4 8 bit monochrome and color passive LCD panel support 9 12 bit LCD TFT D TFD panel support Selectable 3 3V or 5V LCD panel support Oscillator support for CLKI up to 50MHz with internal clock divider or 25MHz with no internal clock divider Embedded 80K byte SRAM display buffer for 1 2 4 bit per pixel bpp 2 4 16 level gray shade display and 1 2 4 8 bpp 2 4 16 256 level color display Support for software and hardware power save modes On board adjustable LCD bias positive power supply 23V to 40V On board adjustable LCD bias negative power supply 23V to 14V 16 bit ISA bus support CPU Bus interface header strips for non ISA bus support S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13705 Issue Date 01 02 13 X27A G 005 03 Page 8 2 Installation and Configuration The S1D13705 has four configuration inputs CNF 3 0 which are read on the rising edge Epson Research and Development Vancouver Design Center of RESET and are fully configurable on this evaluation board One six position DIP switch is provided on the board to configure the four configuration inputs select the S3U13705B00C memory register start address and enable disable hardware power
370. o send control commands and information to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection 1D13705 Supported Evaluation Platforms 13705PWR has been designed to work with the following S1D13705 supported evaluation platforms e PC system with an x86 processor Both 16 bit and 32 bit code is supported e M68ECOOOIDP Integrated Development Platform board revision 3 0 with a Motorola M68EC000 processor e SH3 LCEVB board revision B with an Hitachi SH 3 HD6417780 processor If the platform you are using is different from the above please see the S1D13705 Programming Notes and Examples manual document number X27A G 002 xx 13705PWR Power Save Utility S1D13705 Issue Date 01 07 04 X27A B 007 03 Page 4 Installation Usage S1D13705 X27A B 007 03 Epson Research and Development Vancouver Design Center PC Platform For 16 Bit Program Version copy the file 13705PWR EXE to a directory that is in the DOS path on your hard drive For 32 Bit Program Version install the 32 bit Windows device driver SID13XXX VXD as described in the S1D13XXX 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 xx Copy the file 13705PWR EXE to a directory that is in the DOS path on your hard drive Embedded Platform Download the prog
371. o the descriptions in the file s1d13705 h for the default settings of the console driver If the default does not match the configura tion you are building for then s1d13705 h will have to be regenerated with the correct information Use the program 13705CFG to generate the required header file For information on how to use 13705CFG refer to the 13705CFG Configuration Program User Manual document number X27A B 001 xx available at www erd epson com After selecting the desired configuration choose File gt Export and select the C Header File for S1D13705 Generic Drivers option Save the new configuration as s1d13705 h in the usr src linux drivers video replacing the original configuration file 5 Configure the video options From the command prompt in the directory usr src linux run the command make menuconfig This command will start a text based interface which allows the selection of build time parameters From the text interface under Console drivers options select Support for frame buffer devices Epson LCD CRT controllers support S1D13705 support Advanced low level driver options xBpp packed pixels support where x is the color depth being compile for Once you have configured the kernel options save and exit the configuration utility 6 Compile and install the kernel Build the kernel with the following sequence of commands make dep make clean make bzImage sb
372. odes compatible with most of the popular embedded microprocessor families The interface mode used for the VR4181A is e Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte 3 1 Host Bus Pin Connection Table 3 1 Host Bus Interface Pin Mapping ol A Generic 2 AB 16 1 A 16 1 ABO AO DB 15 0 D 15 0 WE1 BHE CS External Decode BCLK BCLK BS Connect to IO Vpp RD WR Connect to IO Vpp RD RD WEO WE WAIT WAIT RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx 1D13705 Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 Epson Research and Development Page 11 Vancouver Design Center 3 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13705 The Generic 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the VR4181A control signals The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU add
373. of the two portrait modes is as follows Table 7 1 Default and Alternate Portrait Mode Comparison Item Default Portrait Mode Alternate Portrait Mode Memory Requirements The width of the rotated image must be a power of 2 In most cases a virtual image is required where the right hand side of the virtual image is unused and memory is wasted For example a 320x480x4bpp image would normally require only 76 800 bytes possible within the 80K byte address space but the virtual image is 512x480x4bpp which needs 122 880 bytes not possible Does not require a virtual image Clock Requirements CLK need only be as fast as the required PCLK MCLK and hence CLK need to be 2x PCLK For example if the panel requires a 3MHz PCLK then CLK must be 6MHz Note that 25MHz is the maximum CLK so PCLK cannot be higher than 12 5MHz in this mode Power Consumption Lowest power consumption Higher than Default Mode Panning Vertical panning in 2 line increments Vertical panning in 1 line increments Nominal performance Note that Higher performance than Default Mode performance can be increased by Note that performance can be increased by Performance increasing CLK and setting MCLK CLK REG 1Bh bit 2 1 increasing CLK and setting MCLK CLK REG 1Bh bit 2 1 Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 43 Vancouver Design
374. ogram the first eight green LUT entries to be 0 and the second green LUT entries to be FFh This would result in nibble values of 0 through 7 displaying as black and nibble values 8 through OFh displaying as white Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 1 Pixel 1 Bit 3 Bit 2 Bit 1 Bit 0 Bit 3 Bit 2 Bit 1 Bit 0 Figure 3 3 Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 14 Epson Research and Development Vancouver Design Center 3 4 Eight Bit Per Pixel 256 Colors In eight bit per pixel mode one byte of display buffer represents one pixel on the display At this color depth the read modify write cycles required by the lessor pixel depths are eliminated When using a color panel each byte of display memory acts as and index to one element of the LUT The displayed color is arrived at by taking the display memory value as an index into the LUT Eight bit per pixel is not supported for monochrome display modes The reason is that each element of the LUT supports a 4 bit sixteen value level for red green and blue In monochrome display modes on the green value is used to set the gray intensity Thus we have sixteen possible grey values but because of the color Bit 7 Bit 6 Bit 5 Bit 4 Bit 3
375. olor depths only by modifying the source The S1D13705 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com S1D13705 Interfacing to the PC Card Bus X27A G 009 02 Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center 6 References 6 1 Documents e PC Card PCMCIA Standard March 1997 e Epson Research and Development Inc D13705 Embedded Memory Color LCD Controller Hardware Functional Specification Document Number X27A A 001 xx Epson Research and Development Inc SSUI3705BO0C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X27A G 005 xx e Epson Research and Development Inc 1D13705 Programming Notes and Examples Document Number X27A G 002 xx 6 2 Document Sources e PC Card website http www pc card com e Epson Electronics America website http www eea epson com Interfacing to the PC Card Bus S1D13705 Issue Date 01 02 13 X27A G 009 02 Page 16 7 Technical Support 7 1 EPSON LCD Controllers S1D13705 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 7 2 PC Card Standard PCMCIA North America Epson Elect
376. ome display adapters at both memory addresses 6 2 2 Expanded Memory Manager Support If a memory manager is being used for system memory the address range selected for the SRAM start address must be excluded from use or memory conflicts will arise 6 3 Non ISA Bus Support The S5U13703B00C board is specifically designed to support the standard 16 bit ISA bus However the S1D13705 directly supports many other host bus interfaces Header strips H1 and H2 are provided and contain all the necessary IO pins to interface to these host buses See CPU Bus Interface Connector Pinouts on page 11 Table 2 1 Configuration DIP Switch Settings on page 8 and Table 2 3 Jumper Settings on page 9 for details S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13705 Issue Date 01 02 13 X27A G 005 03 Page 16 Epson Research and Development Vancouver Design Center When using the header strips to provide the bus interface observe the following All signals on the ISA bus card edge must be isolated from the ISA bus do not plug the card into a computer Power must be provided through the headers U7 a PLD of type 22V 10 15 is used to provide the S1D13705 CS pin 74 and other decoding logic signals for ISA bus mode For non ISA applications this functionality must be provided externally Remove the PAL from its socket to eliminate conflicts driving S1D13705 control signals Refer to Table 5 1 Host Bus Interface Pin
377. on 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola Dragonball Processors e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor S1D13705 X27A G 007 04 Epson Research and Development Vancouver Design Center Taiwan Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the NEC VR4102 VR4111 Microprocessor Document Number X27A G 008 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only
378. on Code Register Address 1FFEOh Read Only Product Code Product Code Product Code Product Code Product Code Product Code Revision Revision Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Code Bit 1 Code Bit 0 bits 7 2 Product Code This is a read only register that indicates the product code of the chip The product code is 001001 bits 1 0 Revision Code This is a read only register that indicates the revision code of the chip The revision code is 00 REG 01h Mode Register 0 Address 1FFE1h Read Write FPLine FPFrame Mask Data Width Data Width PERSIA lt Buaksingle lr GolornMono Polarity Polarity FPSHIFT Bit 1 Bit O bit 7 TFT STN When this bit 0 STN passive panel mode is selected When this bit 1 TFT D TFD panel mode is selected If TFI D TFD panel mode is selected Dual Single REG 01h bit 6 and Color Mono REG 01h bit5 are ignored See Table 8 1 Panel Data Format for a comprehensive description of panel selection bit 6 Dual Single When this bit 0 Single LCD panel drive is selected When this bit 1 Dual LCD panel drive is selected See Table 8 1 Panel Data Format for a comprehensive description of panel selection bit 5 Color Mono When this bit 0 Monochrome LCD panel drive is selected When this bit 1 Color LCD panel drive is selected See Table 8 1 Panel Data Format for a comprehensive description of panel selection Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27
379. on Research and Development Inc S5UI3705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X27A G 005 xx Epson Research and Development Inc Programming Notes and Examples Document Number X27A G 002 xx 6 2 Document Sources e Motorola Inc Literature Distribution Center 800 441 2447 e Motorola Inc Website http www mot com e Epson Electronics America website http www eea epson com Interfacing to the Motorola MPC821 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 010 02 Page 24 7 Technical Support 7 1 EPSON LCD CRT Controllers S1D13705 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Lid 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax 2827 4346 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 7 2 Motorola MPC821 Processor e Motorola Design Line 800 521 6274 Local Motorola sales office or authorized distributor 1D13705 X27A G 010 02 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading
380. on page 15 of this manual for Look Up Table programming details The following initialization presented in table form shows the sequences and values to set the registers The notes column comments the reason for the particular value being written This example writes to all the necessary registers Initially when the S1D13705 is powered up all registers unless noted otherwise in the specification are set to zero This example programs these registers to zero to establish a known state In practice it may be possible to write to only a subset of the registers The example initializes a S1D13705 to control a panel with the following specifications e 320x240 color single passive LCD panel at 70Hz e Color Format 2 8 bit data interface e 8 bit per pixel 256 colors e 6 MHz input clock CLKI 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 9 Vancouver Design Center Table 2 1 S1D13705 Initialization Sequence Register Value hex Notes See Also 01 0010 0011 23 Select a passive Single Color panel with an 8 bit data width 02 1100 0000 CO Select 8 bit per pixel color depth 03 0000 0011 03 Select normal power operation 04 0010 0111 27 Horizontal display size Reg 04 1 8 39 1 8 320 pixels 05 1110 1111 EF Vertical display size Reg 06 05 1 06 0000
381. on the configuration tabs Placing the mouse pointer over nearly any item on any tab generates a popup window containing helpful advice and hints To enable disable tooltips check uncheck the Tooltips option form the Help menu Note Tooltips are enabled by default This Help menu item is actually a hotlink to the Epson Research and Development website Selecting Help then ERD on the Web starts the default web browser and points it to the ERD product web site The latest software drivers and documentation for the 1D13705 is available at this website Selecting the About 13705CFG option from the Help menu displays the about dialog box for 13705CFG The about dialog box contains version information and the copyright notice for 13705CFG e On any tab particular options may be grayed out if selecting them would violate the operational specification of the S1D13705 i e Selecting TFT or STN on the Panel tab enables disables options specific to the panel type e The file panels def is a text file containing operational specifications for several supported and tested panels This file can be edited with any text editor e 13705CFG allows manually altering register values The manual changes may violate memory and LCD timings as specified in the 1D 3705 Hardware Functional Specifi cation document number X27A A 001 xx If this is done unpredictable results may occur Epson Research and Developmen
382. onal Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Page 3 Vancouver Design Center Table of Contents TY INTO UCON s e WS eee as AR A ARA A A 7 Interfacing to the TMPR3912 lt lt o 8 S1D13705 Host Bus Interface ee 9 3 1 Host Bus Pin Connection 9 3 2 Generic Hl Interface Mode 2 2 2 2 2 4 6 2 4 10 3 3 Generic 2 Interface Mode 2 2 00 2 4 11 4 Direct Connection to the Toshiba TMPR3912 12 4 1 General Description 2 a ee LA 4 2 Memory Mapping and Aliasing 13 43 S1D13705 Configuration a a a 2 ee 13 5 Using the ITE IT8368E PC Card Buffer lt 14 5 1 Hardware Description a eo A 5 2 IT8368E Configuration 2 ee ee ee 16 5 3 Memory Mapping and Aliasing 2 2 2 2 2 2242 2 2 16 5 4 S1D13705 Configuration a a a a ee ee 17 Software s a frogs 5 drat Aaa a Sar ate 18 Technical Support hdi Sle Oe SS ee ele se Ee ew ead 19 7 1 EPSON LCD Controllers S1D13705 2 2 19 7 2 Toshiba MIPS
383. or the peripheral can terminate the bus cycle itself by asserting TA Transfer Acknowledge Any chip select may be programmed to assert BI Burst Inhibit automatically when its memory space is addressed by the processor core Interfacing to the Motorola MPC821 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 010 02 Page 12 Epson Research and Development Vancouver Design Center 2 3 2 User Programmable Machine UPM The UPM is typically used to control memory types such as Dynamic RAMs which have complex control or address multiplexing requirements The UPM is a general purpose RAM based pattern generator which can control address multiplexing wait state gener ation and five general purpose output lines on the MPC821 Up to 64 pattern locations are available each 32 bits wide Separate patterns may be programmed for normal accesses burst accesses refresh timer events and exception conditions This flexibility allows almost any type of memory or peripheral device to be accommodated by the MPC821 In this application note the GPCM is used instead of the UPM since the GPCM has enough flexibility to accommodate the 1D13705 and it is desirable to leave the UPM free to handle other interfacing duties such as EDO DRAM 1D13705 Interfacing to the Motorola MPC821 Microprocessor X27A G 010 02 Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center 3 S1D13705 Host Bus Interface This section is a s
384. orks UGL or WindML a comma delimited text file containing an offset a value and a description for each S1D13705 register C Header File for 51013705 HAL Based Applications appcfg h Export As pct C Header File Defining a Map of 51013705 Registers C Header File for 51013705 WinCE Drivers nodel Close C Header File for 51013705 Generic Drivers s1d13705 h Comma Delimited File Containing Current Configuration s1d13705 cs 1D13705 Register Quick Reference s1d13705 html After selecting the file format click the Export As button to display the file dialog box which allows the user to enter a filename before saving Before saving the configuration file clicking the Preview button starts Notepad with a copy of the configuration file about to be saved When the C Header File for S1D13705 WinCE Drivers option is selected as the export type additional options are available and can be selected by clicking on the Options button The options dialog appears as WinCE Header File Export Options E3 Mode Number gt al selects the mode number for Mode number 0 rer Cancel use in the header file 13705CFG Configuration Program S1D13705 Issue Date 02 03 11 X27A B 001 03 Page 22 Enable Tooltips ERD on the Web About 13705CFG Comments S1D13705 X27A B 001 03 Epson Research and Development Vancouver Design Center Tooltips provide useful information about many of the items
385. ouver Design Center 7 1 6 Generic 2 Interface Timing OESTE SES INNATA A 16 0 VALID BHE CS WE RD gt Hi Z D 15 0 VAGID t7 Hi Z write t5 t6 Hiz VALID D 15 0 read t8 9 je MoS a WAIT Hz he 4 gt Figure 7 6 Generic 2 Timing Table 7 6 Generic 2 Timing Symbol Parameter Min Max Units fecLk Bus Clock frequency 50 MHz TBCLK Bus Clock period 1 fBcLK t1 A 16 0 BHE CS valid to WE RD low 0 ns t2 WE RD high to A 16 0 BHE CS invalid 0 ns 13 WE low to D 15 0 valid write cycle TBcLK t4 WE high to D 15 0 invalid write cycle 0 ns t5 RD low to D 15 0 driven read cycle 16 ns t6 D 15 0 valid to WAIT high read cycle 0 ns t7 RD high to D 15 0 high impedance read cycle 10 ns t8 WE RD low to WAIT driven low 14 ns t9 BCLK to WAIT high 10 ns t10 WE RDA high to WAIT high impedance 11 ns t11 WAIT high to WE RD high 1Tecik Note BCLK may be turned off held low between accesses see Section 13 5 Turning Off BCLK Between Accesses on page 84 Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 34 7 2 Clock Input Requirements Epson Research and Development Vancouver Design Center Clock Input Waveform PWH 90 PWL
386. owed over the entire 2M byte space The CSBAR register should be set to the upper 8 bits of the desired base address The following options should be selected in the chip select mask registers CSMR4 5 e WP 0 disable write protect e AM 0 enable alternate bus master access to the S1D13705 e C I 1 disable CPU space access to the S1D13705 e SC 1 disable Supervisor Code space access to the S1D13705 e SD 0 enable Supervisor Data space access to the S1D13705 e UC 1 disable User Code space access to the S1D13705 e UD 0 enable User Data space access to the S1D13705 e V 1 global enable Valid for the chip select The following options should be selected in the chip select control registers CSCR4 5 e WS0 3 0 no internal wait state setting e AA 0 no automatic acknowledgment e PS 1 0 1 0 memory port size is 16 bits e BEM 0 Byte enable write enable active on writes only e BSTR 0 disable burst reads e BSTW 0 disable burst writes Interfacing to the Motorola MCF5307 ColdFire Microprocessor 1D13705 Issue Date 01 02 13 X27A G 011 02 Page 16 Epson Research and Development Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13705CFG or by directly mo
387. ower up converted to the equivalent vertical non display periods For example at 72 HZ count ing 36 non display periods results in a one half second delay 4 Set REG 03h bit 3 to 0 to enable LCD Power Power Off Disable Sequence The following is a sequence for manually powering down an LCD panel These steps would be used if the power supply discharge requirements are larger than the default 127 frames 1 Set REG 03h bit 3 LCDPWR Override to 1 which will disable LCD Power 2 Count x Vertical Non Display Periods x corresponds to the power supply discharge time converted to the equivalent verti cal non display periods see the previous example 3 Disable the LCD logic by setting the software power save in REG 03h or setting hardware power save via GPIOO Keep in mind that after setting the power save mode there will be 127 frames before the LCD logic signals are disabled 1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 37 Vancouver Design Center 7 Hardware Rotation 7 1 Introduction To Hardware Rotation Many of todays applications use the LCD panel in a portrait orientation typically LCD panels are landscape oriented In this case it becomes necessary to rotate the displayed image This rotation can be done by software at the expense of performance or as with the S1D13705 it can be done by hardware with no performance penal
388. ows 2000 will attempt to detect any new plug and play device and fail The CHOOSE HARDWARE DEVICE dialog box appears Select ADD NEW HARDWARE and click NEXT Select NO I WANT TO SELECT FROM A LIST and click NEXT Select OTHER DEVICE from the list and click NEXT Click HAVE DISK Specify the location of the driver files select the SID13XXX INF file and click OPEN Click OK S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 Epson Research and Development Page 5 Vancouver Design Center Windows 98 ME All PCI Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Windows will detect the new hardware as a new PCI Device and bring up the ADD NEW HARDWARE dialog box 3 Click NEXT 4 Windows will look for the driver When Windows does not find the driver it will al low you to specify the location of it Type the driver location or select BROWSE to find it 5 Click NEXT 6 Windows will open the installation file and show the option EPSON PCI Bridge Card 7 Click FINISH All ISA Bus Evaluation Cards 1 Install the evaluation board in the computer and boot the computer 2 Goto the CONTROL PANEL and double click on ADD NEW HARDWARE to launch the ADD NEW HARDWARE WIZARD Click NEXT 3 Windows will attempt to detect any new plug and play device and fail Click NEXT 4 Windows will ask you to let it detect the hardware or allow you to select from a l
389. power of two width LineB yteCount Width x BitsPerPixel 8 256 x 4 8 128 80h Set the Line Byte Count REG 1C to 80h 3 Enable portrait mode This example uses the default portrait mode scheme If we do not change the Portrait Mode Pixel Clock Select bits then we will not have to recalculate the non display tim ings to correct the frame rate Write 80h to the Portrait Mode Register REG 1Bh The display is now configured for portrait mode use Offset zero into display memory will corresponds to the upper left corner of the display The only item to keep in mind is that the count from the first pixel of one line to the first pixel of the next line referred to as the stride is 128 bytes Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 44 S1D13705 X27A G 002 03 Epson Research and Development Vancouver Design Center Example 7 Enable alternate portrait mode for a 320x240 panel at 4 bpp Note As we have to perform a frame rate calculation for this mode we need to know the fol lowing panel characteristics 320x240 8 bit color to be run at 80 Hz with a 16 MHz in put clock As in the previous example before switching to portrait mode display memory should be cleared Images in display memory are not rotated automatically by hardware and the garbled image would be visible for a short period of time if video memory is not cleared 1 Calculate and set the Screen 1 Start Wo
390. pport The S1D13705 directly supports 9 and 12 bit active matrix color TFT D TFD panels All the necessary signals can also be found on the 40 pin LCD connector J5 The interface signals on the cable are alternated with grounds to reduce crosstalk and noise Refer to Table 3 1 LCD Signal Connector J5 Pinout on page 10 for connection infor mation 6 10 Power Save Modes The S1D13705 supports hardware and software power save modes These modes are controlled by the utility 13705PWR The hardware power save mode needs to be enabled by 13705PWR and then activated by DIP switch S1 6 See Table 2 1 Configuration DIP Switch Settings on page 8 for details on setting this switch S5U13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual S1D13705 Issue Date 01 02 13 X27A G 005 03 Page 18 Epson Research and Development Vancouver Design Center 6 11 Adjustable LCD Panel Negative Power Supply For those LCD panels requiring a negative power supply to provide between 23V and 14V oyt 25mA a power supply has been provided as an integral part of this design The VLCD power supply can be adjusted by R21 to give an output voltage from 23V to 14V and is enabled and disabled by the active high S1D13705 control signal LCDPWR inverted externally Determine the panel s specific power requirements and set the potentiometer accordingly before connecting the panel 6 12 Adjustable LCD Panel Positive Power Supply For those LCD pa
391. ps have block size of 32K bytes to 4M bytes Interfacing to the Motorola Dragonball Family of Microprocessors Issue Date 01 02 13 Epson Research and Development Vancouver Design Center 4 3 S1D13705 Host Bus Interface Page 23 This section is a summary of the host bus interface modes available on the S1D13705 that may be used to interface to the MC68VZ328 The S1D137053 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The two interface modes that may be used for the MC68VZ328 are e Motorola MC68K 1 using Upper Data Strobe Lower Data Strobe e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte 4 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 4 1 Host Bus Interface Pin Mapping elles MC68K 1 Generic 1 AB 15 1 A 15 1 A 15 1 ABO LDS AO DB 15 0 D 15 0 D 15 0 WE1 UDS WE1 CS External Decode External Decode BCLK CLK BCLK BS AS connect to Vss RD WR R W RD1 RD connect to lO Vpp RDO WEO connect to lO Vpp WEO WAIT DTACK WAIT RESET RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx Interfacing to the Motorola Dragonball Family of Microprocessor
392. pt file dumpregs scr to be interpreted and the results to be sent to the file results Example 1 The script file dumpregs scr can be created with and text editor and will look like the following This file initializes the S1D13705 and reads the registers i i Initialize the registers Xa Dump all the registers la And the LUT q Exit e All numeric values are considered to be hexadecimal unless identified otherwise For example 10 10h 16 decimal 10t 10 decimal 010b 2 decimal e Redirecting commands from a script file PC platform allows those commands to be executed as though they were typed 13705PLAY Diagnostic Utility Issue Date 01 07 04 Epson Research and Development Page 7 Vancouver Design Center Program Messages 13705PLAY Diagnostic Utility Issue Date 01 07 04 gt gt gt WARNING DID NOT DETECT S1D13705 lt lt lt The HAL was unable to read the revision code register on the S1D13705 Ensure that the S1D13705 hardware is installed and that the hardware platform has been configured correctly Also check that the display memory address has been configured correctly ERROR Unable to locate load S1D13XXX VXD 13705PLAY was unable to load a required driver The file S1D13XXX VXD should be located in x WINDOWS SYSTEM or in xNWINNTAS Y STEM If the file is not there install it as described in the S1D13XXX 32 Bit Windows Device Driver Installation Guide document number XOOA E 00
393. ption 1 15 C1 C11 C15 17 C24 0 1uF 20 50V 0805 ceramic capacitor 2 3 C12 14 10uF 10 25V Tantalum capacitor size D 3 2 C18 C22 47uF 10 16V Tantalum capacitor size D 4 3 C19 C21 4 7UuF 10 50V Tantalum capacitor size D 5 1 C23 56uF 20 63V Electrolytic radial low ESR 6 2 H1 H2 CON34A Header 0 1 17x2 header PTH 7 5 JP1 JP4 JP6 HEADER 3 0 1 1x3 header PTH 8 1 J1 AT CON A ISA Bus gold fingers 9 1 J2 AT CON B ISA Bus gold fingers 10 1 J3 AT CON C ISA Bus gold fingers 11 1 J4 AT CON D ISA Bus gold fingers 12 1 J5 CON40A Shrouded header 2x20 PTH center key 13 1 L1 1pH MCI 1812 inductor 14 2 L3 L4 Ferrite bead Philips BDS3 3 8 9 4S2 15 1 Q1 2N3906 PNP signal transistor SOT23 16 1 Q2 2N3904 NPN signal transistor SOT23 17 6 R1 R6 15K 5 0805 resistor 18 9 R7 R13 R17 R18 10K 5 0805 resistor 19 1 R14 475K 1 0805 resistor 20 1 R15 200K Pot 200K Trim POT Spectrol 635204T607 or equivalent 21 1 R16 14K 1 0805 resistor 22 3 R19 R20 R22 100K 5 0805 resistor 23 1 R21 100K Pot 100K Trim POT Spectrol 635104T607 or equivalent 24 1 S1 SW DIP 6 6 position DIP switch 25 1 U1 S1D13705F00A QFP14 80 80 pin SMT 26 1 U2 25 0 MHz oscillator FOX 25MHZz oscillator or equiv 14 pin DIP socketed 27 3 U3 U5 74AHC244 SO 22 TI74AHC244 28 1 U6 LT1117CM 3 3 Linear Technology 5V to 3 3V regulator 8300mA 29 1 U7 PLD22V 10 15 PLD type 22V10 15 20 Pin DIP socketed 30 1 U8 74ALS125 SO 14 74ALS125 31 1 U9 74HCT04 SO 14 74HCT04 32 1
394. ption depends on the specific implementation Active Mode power consumption depends on the desired CPU perfor mance and LCD frame rate whereas Power Save Mode consumption depends on the CPU Interface and Input Clock state In a typical design environment the S1D13705 can be configured to be an extremely power efficient LCD Controller with high performance and flexibility S1D13705 X27A G 006 02 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Power Consumption X27A G 006 02 Issue Date 01 02 13 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the Motorola Dragonball Family of Microprocessors Document Number X27A G 007 04 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13
395. r Flash EPROM device e Upper Write Enable and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus they may be directly connected to the write enable inputs of a typical memory device The S1D13705 implements the MC68EC00O0 bus interface using its MC68K 1 mode so this mode may be used to connect the MC68328 directly to the S1D13705 with no glue logic However several of the MC68EC000 bus control signals are multiplexed with IO and interrupt signals on the MC68328 and in many applications it may be desirable to make these pins available for these alternate functions This requirement may be accommo dated through the use of the Generic 1 interface mode on the S1D13705 2 2 Chip Select Module 1D13705 X27A G 007 04 The MC68328 can generate up to 16 chip select outputs organized into four groups A through D Each chip select group has a common base address register and address mask register to set the base address and block size of the entire group In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s address block Finally each chip select may be individually programmed to control an 8 or 16 bit device and each may be individually programmed to generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate th
396. r up during initialization REG OBh MOD Rate Register Address 1FFEBh Read Write ie nla MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate MOD Rate Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O bits 5 0 MOD Rate Bits 5 0 When the value of this register is O the MOD output signal toggles every FPFRAME For a non zero value the value in this register 1 specifies the number of FPLINEs between toggles of the MOD output signal These bits are for passive LCD panels only 1D13705 X27A A 001 10 Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 63 REG 0Ch Screen 1 Start Address Register LSB Address 1FFECh Read Write Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Address Address Address Address Address Address Address Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 0Dh Screen 1 Start Address Register MSB Address 1FFEDh Read Write Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Screen 1 Start Address Address Address Address Address Address Address Address Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 REG ODh bits 7 0 REG 0Ch bits 7 0 Screen 1 Start Address Bits 15 0 These bits determine
397. rAddress pRegs p13705 Ox1FFEO Check the revision code Exit if we don t find an S1D13705 if 0x24 pRegs printf Didn t find an S1D13705 return Initialize the chip after initialization the display will be setup for landscape use Normally a loop would be used to write the register array near the top of this file to the registers For purposes of documenting the sample code each register write is performed individually ay Register Olh Mode Register 0 Color 8 bit format 2 SET_REG 0x01 0x20 Register 02h Mode Register 1 8BPP ey SET_REG 0x02 0xC0 Register 03h Mode Register 2 Normal power mode ay SET_REG 0x03 0x03 Register 04h Horizontal Panel Size 320 pixels 320 8 1 39 27h S SET_REG 0x04 0x27 Register 05h Vertical Panel Size LSB 240 pixels Register 06h Vertical Panel Size MSB 240 1 239 EFh R SET_REG 0x05 OXEF SET_REG 0x06 0x00 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 71 Vancouver Design Center Register 07h FPLINE Start Position not used by STN SET_REG 0x07 0x00
398. ram 13705PWR to the system PC platform at the prompt type 13705pwr s0 s1 h0 h1 Embedded platform execute 13705pwr and at the prompt type the command line argument Where s0 resets software power save mode sl sets software power save mode hO resets disables hardware power save mode REG 03h bit 2 h1 sets enables hardware power save mode REG 03h bit 2 displays this usage message 13705PWR Power Save Utility Issue Date 01 07 04 Epson Research and Development Page 5 Vancouver Design Center Program Messages ERROR Did not find a 13705 device The HAL was unable to read the revision code register on the S1D13705 Ensure that the S1D13705 hardware is installed and that the hardware platform has been configured correctly Also check that the display memory address has been configured correctly ERROR Unable to locate load S1D13XXX VXD 13705PLAY was unable to load a required driver The file S1D13XXX VXD should be located in x WINDOWS SYSTEM or in xNWINNTAS Y STEM If the file is not there install it as described in the S1D13XXX 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 XX ERROR An IOCTL error occurred This message indicates an error at the IO control layer occurred The usual cause for this is an incorrect hardware configuration ERROR The HAL returned an unknown error This message should never be displayed it indicates that 13705SHOW is unable to determine t
399. rated by the configuration utility 13705CFG This design allows for easy customization of display type clocks decode addresses etc by OEMs For further information on 13705CFG see the 13705CFG Configuration Program User Manual document number X27A B 001 xx Note The QNX display drivers are provided as reference source code only They are intend ed to provide a basis for OEMs to develop their own drivers for QNX Photon v2 0 This document and the source code for the QNX display drivers are updated as appropriate Please check the Epson Electronics America website at http www eea epson com or the Epson Research and Development website at http www erd epson com for the latest revisions before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation Oerd epson com QNX Photon v2 0 Display Driver S1D13705 Issue Date 01 09 10 X27A E 005 01 Page 4 Epson Research and Development Vancouver Design Center Building the Photon v2 0 Display Driver S1D13705 X27A E 005 01 The following steps build the Photon v2 0 display driver and integrate it into the QNX operating system These instructions assume the ONX developer environment is correctly installed and the developer is familiar with building for the QNX operating system Unpack the Graphics Driver Development Kit Archive 1 Install the QNX ddk package using the Package Manager utility For information
400. rd Address register OffsetBytes Width x BitsPerPixel 8 1 240 x 4 8 1 119 0077h Set Screen Display Start Word Address LSB REG 0Ch to 77h and Screen1 Dis play Start Word Address MSB REG ODh to 00h 2 Calculate the Line Byte Count LineByteCount Width x BitsPerPixel 8 240 x 4 8 120 78h Set the Line Byte Count REG 1C to 78h 3 Enable portrait mode This example uses the alternate portrait mode scheme We will not change the MCLK Autoswitch or Pixel Clock Select settings Write COh to the Portrait Mode register REG 1Bh 4 Recalculate the frame rate dependents This example assumes the alternate portrait mode scheme In this scheme without touching the Pixel Clock Select bits the PCLK value will be equal to CLK 2 These examples don t use the Pixel Clock Select bits The ability to divide the PCLK value down further than the default values was added to the S1D13705 to support hardware portrait mode on very small panels The Pixel Clock value has changed so we must calculate horizontal and vertical non display times to reach the desired frame rate Rather than perform the frame rate calculations here I will refer the reader to the frame rate calculations in Frame Rate Calculation on page 9 and simply arrive at the following Horizontal Non Display Period 88h Vertical Non Display Period 03h Plugging the values into the frame rate calculations yields Programming Notes and Examp
401. re selected in the option register OR4 AM 0 16 1111 1111 1100 0000 0 mask all but upper 10 address bits S1D13705 consumes 4M byte of address space ATM 0 2 0 ignore address type bits CSNT 0 normal CS WE negation ACS 0 1 1 1 delay CS assertion by Y clock cycle from address lines BI 1 assert Burst Inhibit SCY 0 3 0 wait state selection this field is ignored since external transfer acknowledge is used see SETA below SETA 1 the S1D13705 generates an external transfer acknowledge using the WAIT line TRLX 0 normal timing EHTR 0 normal timing Interfacing to the Motorola MPC821 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 010 02 Page 20 Epson Research and Development Vancouver Design Center 4 5 Test Software BR4 OR4 MemStart The test software to exercise this interface is very simple It configures chip select 4 on the MPC821 to map the S1D13705 to an unused 128k byte block of address space and loads the appropriate values into the option register for CS4 At that point the software runs in a tight loop reading the 13705 Revision Code Register REG 00h which allows monitoring of the bus timing on a logic analyzer The source code for this test routine is as follows RevCodeReg Start Loop end S1D13705 X27A G 010 02 equ 120 CS4 base register equ 124 CS4 option register equ 40 upper word of S1D13705 start address qu 1F
402. register to account for offset pixels pixels_per_word 320 8 40 28h The Memory Address Offset register REG 11h will have to be set to 28h to satisfy the above condition Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 27 Vancouver Design Center Example 2 From the above what is the maximum number of lines our image can contain Step 1 Calculate the number of bytes on each line bytes_per_line pixels_per_line pixels_per_byte 640 4 160 Each line of the display requires 160 bytes Step 2 Calculate the number of lines the S1D13705 is capable of total_lines memory bytes_per_line 81920 160 512 We can display a maximum of 512 lines Our example image requires 480 lines so this example can be done 5 2 Panning and Scrolling Panning and scrolling describe the operation of moving a physical display viewport about a virtual image in order to view the entire image a portion at time For example after setting up the previous example virtual display and drawing an image into it we would only be able to view one quarter of the image Panning and scrolling are used to reveal the rest of the image Panning describes the horizontal side to side motion of the viewport When panning to the right the image in the viewport appears to slide to the left When panning to the left the image to appears to slide to the right Scrolling describes the vertical up and down mo
403. ress 1FFF3h Read Write Screen 1 Screen 1 n a n a n a n a n a n a Vertical Size Vertical Size Bit 9 Bit 8 REG 13h bits 1 0 REG 12h bits 7 0 S1D13705 X27A A 001 10 Screen 1 Vertical Size Bits 9 0 This register is used to implement the Split Screen feature of the S1D13705 These bits determine the height in lines of Screen 1 In landscape modes if this register is programmed with a value n where n is less than the Vertical Panel Size REG 06h REG O5h then lines 0 to n of the panel contain Screen 1 and lines n 1 to REG 06h REG O5h of the panel contain Screen 2 See Figure 8 1 Screen Register Relationship Split Screen on page 65 If Split Screen is not desired this register must be programmed greater than or equal to the Vertical Panel Size REG 06h and REG O5h In Swivel View modes this register must be programmed greater than or equal to the Verti cal Panel Size REG O6h and REG O5h See Swivel View on page 77 Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Page 65 Vancouver Design Center REG ODh REG OCh Words Line 0 Last Pixel Address REG ODh REG OCh Line O Last Pixel Address REG 11h Words 8 REG 04h 1 X BPP 16 Words x Line 0 y x Line 1 Image 1 REG 06h REG 05 1 Lines Line REG 13h REG 12h k Image 2 REG OFh REG OEh Words 8 R
404. ress and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WE1F is the high byte enable for both read and write cycles WEO is the write enable signal for the S1D13705 to be driven low when the host CPU is writing data from the S1D13705 RD is the read enable for the S1D13705 to be driven low when the host CPU is reading data from the S1D13705 WAIT is a signal which is output from the S1D137053 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the 1D13705 internal registers or memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic 2 mode However BS is used to configure the S1D13
405. rface For further information on the MC68K 1 host bus interface and AC Timing refer to the 1D13705 Hardware Functional Specification document number X27A A 001 xx Note gt When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states MC68328 S1D13705 A 16 0 gt AB 16 1 D 15 0 gt DB 15 0 CSB3 gt CS Vcc DTACK WAITH AS gt BS UDS gt WE1 LDS ABO R W gt RD WR Vcc RDA Vcc WEO CLKO BUSCLK Y System RESET gt RESET me S1D13705 Figure 2 1 Typical Implementation of MC68328 to SID13705 Interface MC68K 1 Interfacing to the Motorola Dragonball Family of Microprocessors X27A G 007 04 Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center Using The Generic 1 Host Bus Interface If UDS and or LDS are required for their alternate IO functions then the MC68328 to S1D13705 interface may be implemented using the S1D13705 Generic 1 host bus interface Note that in either case the DTACK signal must be made available for the S1D13705 since it inserts a variable number of wait states depending upon CPU LCD synchronization and the LCD panel display mode WAIT must be
406. rison HAL Functions oia a e A A a a List of Figures Pixel Storage for 1 Bpp 2 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 4 Bpp 16 Colors Gray Shades in One Byte of Display Buffer Pixel Storage for 8 Bpp 256 Colors in One Byte of Display Buffer Viewport Inside a Virtual Display ooa o o 320x240 Single Panel For Split Screen oaoa oo Relationship Between the Default Mode Screen Image and the Image Refreshed by S1D13705 Relationship Between the Alternate Mode Screen Image and the Image Refreshed by S1D13705 o oo o Programming Notes and Examples Issue Date 02 01 22 Page 5 S1D13705 X27A G 002 03 Page 6 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 7 Vancouver Design Center 1 Introduction This guide demonstrates how to program the S1D13705 Embedded Memory Color LCD Controller The guide presents the basic concepts of the LCD controller and provides methods to directly program the registers It explains some of the advanced techniques used and the special features of the S1D13705 The guide also introduces the Hardware Abstraction Layer HAL which is designed to make programming the S1D13705 as easy as possible
407. rmation structure Return Value ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE the HAL was unable to find an 1D13705 Note seRegisterDevice MUST be called before any other HAL functions No S1D13705 registers are changed by calling seRegisterDevice seSetlnit Description Configures the S1D13705 for operation This function sets all the S1D13705 control registers to their default values Initialization of the S1D13705 is a two step process to accommodate those programs e g 13705PLAY EXE which do not initialize the 1D13705 on start up Parameters None Return Value ERR_OK operation completed with no problems Note After this call the Look Up Table will be set to a default state appropriate to the display type Unlike S1D1350x HAL versions this function does not call seSetDisplayMode as this function does not exist in the 13705 HAL Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 52 9 4 2 General HAL Support Epson Research and Development Vancouver Design Center Functions in this group do not fit into any specific category of support They provide a miscellaneous range of support for working with the S1D13705 int seGetld int pld Description Parameters Return Value Reads the 1D13705 revision code register to determine the chip product and revisions The interpreted value is returned in pID pld pointer to an integer which will recei
408. rocessor 1D13705 Issue Date 01 02 13 X27A G 004 02 Page 18 Epson Research and Development Vancouver Design Center 6 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 1357CFG or by directly modifying the source The Windows CE v2 0 display drivers can be customized by the OEM for different panel types resolutions and color depths only by modifying the source The S1D13705 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or www eea epson com S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 EPSON LCD Controllers S1D13705 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 North America Epson Electronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong
409. rocessor S1D13705 X27A G 008 02 Issue Date 01 02 13 Page 14 Epson Research and Development Vancouver Design Center 4 3 NEC VR4102 VR4111 Configuration The NEC VR4102 VR4111 provides the internal address decoding necessary to map to an external LCD controller Physical address 0A000000h to OAFFFFFFh 16M bytes is reserved for an external LCD controller The S1D13705 supports up to 80K bytes of display buffer memory and 32 bytes for internal registers Therefore the S1D13705 will be shadowed over the entire 16M byte memory range at 128K byte segments The starting address of the display buffer is 0A000000h and register O of the S1D13705 REG 00h resides at O0AO1FFEOh The NEC VR4102 VR4111 has a 16 bit internal register named BCUCNTREG2 located at address 0B000002h It must be set to the value of 0001h to indicate that LCD controller accesses use a non inverting data bus The 16 bit internal register named BCUCNTREGI located at address OBOO0000h must have bit D 13 ISA LCD bit set to 0 to reserve the 16M bytes space 0A000000h to OAFFFFFFh for LCD use and not as ISA bus memory space S1D13705 Interfacing to the NEC VR4102 VR4111 Microprocessor X27A G 008 02 Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center 5 Software Test utilities and Windows CE v2 0 display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test ut
410. rocessors S1D13705 Issue Date 01 02 13 X27A G 007 04 Page 22 Epson Research and Development Vancouver Design Center 4 Interfacing to the MC68VZ328 4 1 The MC68VZ328 System Bus The MC68VZ328 is Motorola s third generation Dragonball microprocessor The Dragon ballVZ is an integrated controller for handheld products based upon the FLX68000 micro processor core with an external 24 bit address bus and 16 bit data bus The DragonballVZ differs from 1ts predecessor mainly in that it has increased speed and support for SDRAM has been added to the DRAM controller The bus interface consists of all the standard MC68000 bus interface signals except AS plus some new signals intended to simplify the task of interfacing to typical memory and peripheral devices The 68000 signals are multi plexed with IrDA SPI and LCD controller signals The MC68000 bus control signals are well documented in Motorola s user manuals and will not be described here A brief summary of the new signals appears below Output Enable OE is asserted when a read cycle is in process it is intended to connect to the output enable control of a typical static RAM EPROM or Flash EPROM device e Upper Write Enable and Lower Write Enable UWE LWE are asserted during memory write cycles for the upper and lower bytes of the 16 bit data bus they may be directly connected to the write enable inputs of a typical memory device The S1D13705 implements the MC68000 bu
411. rogram commands are received from the standard input device and output is sent to the standard output device console for Intel and terminal for embedded platforms This utility requires the target platform to support standard IO 13705PLAY commands can be entered interactively using a keyboard monitor or they can be executed from a script file Scripting is a powerful feature which allows command sequences played back from a file thus avoiding having to retype lengthy sequences The 13705PLAY display utility must be configured and or compiled to work with your hardware platform The program 13705CFG EXE can be used to configure 13705PLAY Consult the 13705CFG users guide document number X27A B 001 xx for more infor mation on configuring S1D13705 utilities This software is designed to work in both embedded and personal computer PC environ ments For the embedded environment it is assumed that the system has a means of downloading software from the PC to the target platform Typically this is done by serial communications The PC uses a terminal program to send control commands and infor mation to the target processor Alternatively the PC can program an EPROM which is then placed in the target platform Some target platforms can also communicate with the PC via a parallel port connection or an Ethernet connection S1D13705 Supported Evaluation Platforms 13705PLAY Diagnostic Utility Issue Date 01 07 04 13705PLAY has been test
412. roject such as x myproject set the platform name such as myplatform and set the Processors to Win32 WCE x86 d Click the OK button e In the dialog box WCE Platform Step 1 of 2 select CEPC f Click the Next button g In the dialog box WCE Platform Step 2 of 2 select Minimal OS MinKern h Click the Finish button j i o In the dialog box New Platform Information click the OK button Set the active configuration to Win32 WCE x86 Release a From the Build menu select Set Active Configuration b Select MYPLATFORM Win32 WCE x86 Release c Click the OK button Add the environment variable CEPC_DDI_S1D13X0X a From the Platform menu select Settings b Select the Environment tab c In the Variable box type CEPC_DDI_S1D13X0X Windows CE 3 x Display Drivers Issue Date 01 05 25 Epson Research and Development Page 5 Vancouver Design Center d Inthe Value box type 1 e Click the Set button f Click the OK button 7 Create a new directory S1D13705 under x wince300 platform cepc drivers display and copy the 1D13705 driver source code into this new directory 8 Add the S1D13705 driver component a From the Platform menu select Insert User Component b Set Files of type to All Files c Select the file x wince300 platform cepc drivers display S 1D13705 sources d In the User Component Tar
413. ronics America Inc 150 River Oaks Parkway San Jose CA 95134 USA Tel 408 922 0200 Fax 408 922 0238 http www eea epson com Europe Epson Europe Electronics GmbH Riesstrasse 15 80992 Munich Germany Tel 089 14005 0 Fax 089 14005 110 Personal Computer Memory Card International Association 2635 North First Street Suite 209 San Jose CA 95134 Tel 408 433 2273 Fax 408 433 9558 http www pc card com S1D13705 X27A G 009 02 Epson Research and Development Vancouver Design Center Taiwan R O C Epson Taiwan Technology amp Trading Ltd 10F No 287 Nanking East Road Sec 3 Taipei Taiwan R O C Tel 02 2717 7360 Fax 02 2712 9164 Singapore Epson Singapore Pte Ltd No 1 Temasek Avenue 36 00 Millenia Tower Singapore 039192 Tel 337 7911 Fax 334 2716 Interfacing to the PC Card Bus Issue Date 01 02 13 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the Motorola MPC821 Microprocessor Document Number X27A G 010 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described
414. rs Issue Date 01 02 13 Epson Research and Development Page 11 Vancouver Design Center 2 3 3 MC68K 1 Interface Mode The MC68K 1 Interface Mode can be used to interface to the MC68328 microprocessor 1f the previously mentioned multiplexed bus signals will not be used for other purposes The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs AB1 through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space AO and WE 1 are the enables for the low order and high order bytes respectively to be driven low when the host CPU is reading or writing data to the S1D13705 RD WRF is the read write signal that is driven low when the CPU writes to the S1D13705 and is driven high when the CPU is doing a read from the 1D13705 WAIT is a signal which is output from the S1D13705
415. ry are read writable LCD output is forced low 3 normal operation all outputs function normally Return Value ERR_OK operation completed with no problems Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 61 Vancouver Design Center 9 4 6 Drawing The Drawing routines cover HAL functions that deal with displaying pixels lines and shapes int seSetPixel long x long y DWORD Color Description Draws a pixel at coordinates x y in the requested color This routine can be used for any color depth Parameters x horizontal coordinate of the pixel starting from 0 y vertical coordinate of the pixel starting from 0 Color at 1 2 4 and 8 bpp Color is an index into the LUT At 15 and 16 bpp Color defines the color directly i e rrrrrggggggbbbbb for 16 bpp Return Value ERR_OK operation completed with no problems int seGetPixel long x long y DWORD pColor Description Reads the pixel color at coordinates x y This routine can be used for any color depth Parameters x horizontal coordinate of the pixel starting from 0 y vertical coordinate of the pixel starting from 0 pColor at 1 2 4 and 8 bpp pColor points to an index into the LUT At 15 and 16 bpp pColor points to the color directly i e rrrrregggggbbbbb for 16 bpp Return Value ERR_OK operation completed with no problems int seDrawLine int x1 int y1 int x2 int y2 DWORD Color De
416. ry is always displayed at the top of the screen followed by screen 2 memory This relationship holds true regardless of where in display memory Screen 1 Start Address and Screen 2 Start Address are pointing For instance Screen 2 Start Address may point to offset zero of display memory while Screen 1 Start Address points to a location several thousand bytes higher Screen 1 will still be shown first on the display While not particularly useful itis even possible to set screen 1 and screen 2 to the same address Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 33 Vancouver Design Center REG 0Eh Screen 2 Display Start Address 0 LSB Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit 7 6 5 4 3 2 1 0 REG 0Fh Screen 2 Display Start Address 1 MSB Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit Start Addr Bit 15 14 13 12 11 10 9 8 Programming Notes and Examples Issue Date 02 01 22 Screen 2 Start Address Registers These three registers form the seventeen bit Screen 2 Start Address Screen 2 is always displayed immediately following the screen data and will begin at the left most pixel on a line Keep in mind that if the Screen 1 Vertical Size is equal to or greater than the physical display then S
417. s Issue Date 01 02 13 1D13705 X27A G 007 04 Page 24 Epson Research and Development Vancouver Design Center 4 3 2 Generic 1 Interface Mode S1D13705 X27A G 007 04 Generic 1 interface mode is the most general and least processor specific interface mode on the S1D13705 The Generic 1 interface mode was chosen for this interface due to the simplicity of its timing The interface requires the following signals BUSCLK is a clock input which is required by the S1D13705 host interface It is sepa rate from the input clock CLKD and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the
418. s X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Page 83 Vancouver Design Center xk Copyright c 1998 1999 Epson Research and Development Inc All Rights Reserved Module Name KK toctl h Abstract E Include file for S1D13x0x PCI Board Driver KX Define the IOCTL codes we will use The IOCTL code contains a command x identifier plus other information about the device the type of access AK with which the file must have been opened and the type of buffering k k Xj define SED_TYPE FILE_DEVICE_CONTROLLER The IOCTL function codes from 0x800 to OxFFF are for customer use define IOCTL_SED_QUERY_NUMBER_OF_PCI_BOARDS CTL_CODE SED_TYPE 0x900 METHOD_BUFFERED FILE ANY ACCESS define IOCTL_SED_MAP_PCI_BOARD CTL_CODE SED_TYPE 0x901 METHOD_B define IOCTL_SED_MAP_PHYSICAL MEMORY CTL_CODE SED_TYPE 0x902 ETHOD_BUFFERED FILE_ANY_ACCESS RY OD_B T Gl T UFFERED FILE_ANY_ACCESS Gl T define IOCTL_SED_UNMAP_LINEAR_MEMO CTL_CODE SED_TYPE 0x903 ETH Gl T UFFERED FILE_ANY_ACCESS Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 84 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Programm
419. s X27A E 001 03 Issue Date 01 06 07 EPSON 1D13705 Embedded Memory LCD Controller Wind River WindML v2 0 Display Drivers Document Number X27A E 002 03 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Wind River WindML v2 0 Display Drivers X27A E 002 03 Issue Date 01 04 06 Epson Research and Development Page 3 Vancouver Design Center Wind River WindML v2 0 DISPLAY DRIVERS The Wind River WindML v2 0 display drivers for the S1D13705 Embedded Memory LCD Controller are intended as reference source code for OEMs developing for Wind River s WindML v2 0 The driver package provides support for 8 bit per pixel color depth The source code is written for portability and contains functionality for most features of the S1D137
420. s interface using its MC68K 1 mode This mode may be used to interface the S1D13705 to the Dragonball VZ if external logic is used to generate AS The Generic 1 interface mode on the 1D 13705 is also well suited to interface to the MC68VZ328 4 2 Chip Select Module 1D13705 X27A G 007 04 The MC68VZ328 can generate up to 8 chip select outputs organized into four groups A through D Each chip select group has a common base address register and address mask register to set the base address and block size of the entire group In addition each chip select within a group has its own address compare and address mask register to activate the chip select for a subset of the group s address block Finally each chip select may be individually programmed to control an 8 or 16 bit device and each may be individually programmed to generate from 0 through 6 wait states internally or allow the memory or peripheral device to terminate the cycle externally through use of the standard MC68000 DTACK signal Groups A and B are used to control ROM SRAM and Flash memory devices and have a block size of 128K bytes to 16M bytes Chip select AO is active immediately after reset and is a global chip select so it is typically used to control a boot EPROM device This chip select ceases to decode globally once this chip select s registers are programmed Groups C and D are special in that they can also control DRAM interfaces These last two grou
421. s placed on the PC Card bus and one or both of the card enable signals CE1 and CE2 are driven low REG must be kept inactive If only CE1 is driven low 8 bit data transfers are enabled and AO specifies whether the even or odd data byte appears on data bus lines D 7 0 If both CE1 and CE2 are driven low a 16 bit word transfer takes place If only CE2 is driven low an odd byte transfer occurs on data lines D 15 8 Interfacing to the PC Card Bus Issue Date 01 02 13 Epson Research and Development Page 9 Vancouver Design Center During a read cycle OE output enable is driven low A write cycle is specified by driving OE high and driving the write enable signal WE low The cycle can be lengthened by driving WAIT low for the time needed to complete the cycle Figure 2 1 and Figure 2 2 illustrate typical memory access cycles on the PC Card bus A 25 0 REG CE1 CE2 OE WAIT D 15 0 ADDRESS VALID Hi Z Hi Z DATA VALID 7 Transfer Start Transfer Complete Figure 2 1 PC Card Read Cycle A 25 0 REG CE1 CE2 OE WE WAIT D 15 0 ADDRESS VALID Hi Z Hi Z DATA VALID Transfer Start Transfer Complete Figure 2 2 PC Card Write Cycle Interfacing to the PC Card Bus S1D13705 Issue Date 01 02 13 X27A G 009 02 Page 10 3 S1D13705 Bus Interface Thi
422. s section is a summary of the host bus interface modes available on the S1D13705 that would be used to interface to the PC Card bus The S 1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The interface mode used for the PC Card bus is e Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte 3 1 Host Bus Pin Connection The following table shows the functions of the host bus interface signals Table 3 1 Host Bus Interface Pin Mapping darts Generic 2 AB 15 1 A 15 1 ABO AO DB 15 0 D 15 0 WE1 BHE CS External Decode BCLK BCLK BS connect to lO Vpp RD WR connect to lO Vpp RD RD WEO WE WAIT WAIT RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx 1D13705 X27A G 009 02 Epson Research and Development Vancouver Design Center Interfacing to the PC Card Bus Issue Date 01 02 13 Epson Research and Development Page 11 Vancouver Design Center 3 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13705 The Generic 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with t
423. s this utility Displays Help information 13705PLAY Example 1 Type 13705PLAY to start the program 2 Type for help 3 Type i to initialize the registers 4 Type xa to display the contents of the registers 5 Type x 5 to read register 5 6 Type x 3 10 to write 10 hex to register 3 7 Type f 0 400 aa to fill the first 400 hex bytes of display memory with AA hex 8 Type f 0 14000 aa to fill 80k bytes of display memory with AA hex 9 Type r 0 ff to read the first 100 hex bytes of display memory 10 Type q to exit the program 13705PLAY Diagnostic Utility 1D13705 Issue Date 01 07 04 X27A B 005 04 Page 6 Scripting Comments S1D13705 X27A B 005 04 Epson Research and Development Vancouver Design Center 13705PLAY can be driven by a script file This is useful when e there is no standard display output to monitor command entry and results e various registers must be quickly changed faster than can achieved by typing e The same series of keystrokes is being entered time and again A script file is an ASCII text file with one 13705PLAY command per line All scripts must end with a q quit command in order to return control to the operating system The semi colon is used as a comment delimitor Everything on a line after the semi colon will be ignored On a PC platform a typical script command line is 13705PLAY lt dumpregs scr gt results This causes the scri
424. s value is only used by Epson evaluation software designed for the S5U13705B00C evaluation board 1D13705 13705CFG Configuration Program X27A B 001 03 Issue Date 02 03 11 Epson Research and Development Page 17 Vancouver Design Center Power Up Time Delay This setting controls the time delay between when the S1D13705 control signals are turned on and the LCD panel is powered on This setting must be configured according to the specification for the panel being used This value is only used by Epson evaluation software designed for the S3U13705B00C evaluation board Registers Tab 51D13705 Configuration Utility Mal x File Help Press Enter or double click on a line to modify a register The Registers tab allows viewing and direct editing the S1D13705 register values Scroll up and down the list of registers and view their configured values based on the settings in the previous tabs Individual register settings may be changed by double clicking on the register in the listing Manual changes to the registers are not checked for errors so caution is warranted when directly editing these values It is strongly recommended that the D13705 Hardware Functional Specification document number X27A A 001 xx be referred to before making a manual register settings Manually entered values may be changed by 13705CFG if further configuration changes are made on the other tabs In this case the user is notified 13705CFG Configuration
425. scription This routine draws a line on the display from the endpoints defined by x1 y1 to the endpoint x2 y2 in the requested Color Currently seDrawLine only draws horizontal and vertical lines Parameters x1 yl first endpoint of the line in pixels x2 y2 second endpoint of the line in pixels see note below Color color to draw with Color is an index into the LUT Return Value ERR_OK operation completed with no problems Note Functionality differs from the 135x HAL Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 62 Epson Research and Development Vancouver Design Center int seDrawRect long x1 long y1 long x2 long y2 DWORD Color BOOL SolidFill Description Parameters This routine draws and optionally fills a rectangular area of display buffer The upper right corner is defined by x1 y1 and the lower right corner is defined by x2 y2 The color defined by Color applies both to the border and to the optional fill xl yl top left corner of the rectangle in pixels x2 y2 bottom right corner of the rectangle in pixels Color The color to draw the rectangle outline and fill with Color is an index into the Look Up Table SolidFill Flag whether to fill the rectangle or simply draw the border Set to O for no fill set to non 0 to fill the inside of the rectangle Return Value ERR_OK operation completed with no problems 9 4 7 LUT Manipulation
426. se This settings is only available when the selected panel type is TFT Refer to 1D13705 Hardware Functional Specifi cation document number X27A A 001 xx for a complete description of the FPFRAME pulse settings Predefined Panels 13705CFG uses a file panels def which lists various panel manufacturers recommended settings If the file panels def is present in the same directory as 13705cfg exe the settings for a number of predefined panels are available in the drop down list If a panel is selected from the list 13705CFG loads the predefined settings contained in the file 13705CFG Configuration Program 1D13705 Issue Date 02 03 11 X27A B 001 03 Page 16 Epson Research and Development Vancouver Design Center Panel Power Tab 05 51D13705 Configuration Utility Hardware Power Save Enable Power Down Time Dela Power Up Time Delay The S5U13705B00C evaluation board is designed to use the GPIOO signal to control the LCD bias power The following settings allow configuration of the necessary delays Hardware Power Save Enable When this box is checked Hardware Power Save using GPIOO0 is enabled When this box is unchecked the Hardware Power Save function is not available Power Down Time Delay This setting controls the time delay between when the LCD panel is powered off and when the 1D13705 control signals are turned off This setting must be configured according to the specification for the panel being used Thi
427. se we use a value of 256 pixels for ak our calculations instead of the panel dimension of 240 Programming Notes and Examples X27A G 002 03 Issue Date 02 01 22 Epson Research and Development Vancouver Design Center x 110 Page 75 pMem p13705 y 256 BitsPerPixel 8 x BitsPerPixel 8 for x 110 x lt 210 x oMem 0x01 Draw a pixel in LUT color 1 pMem IntelGetLinAddressW32 DWORD physaddr DWORD linaddr return value k k AR O No error ER Sh EMLor int IntelGetLinAddressW32 DWORD physaddr DWORD linaddr HANDLE hDriver DWORD cbReturned int rc retVal unsigned Arr 2 First see if we are running under WinNT DWORD dwVersion GetVersion if dwVersion lt 0x80000000 hDriver CreateFile S1D13x0x GENERIC_READ GENERIC_WRIT 0 NULL OPEN_EXISTING FILE_ATTRIBUTE_NORMAL NULL else Win95 98 Dynamically load and prepare to call s1D13x0x Gl The FILE_FLAG_DELETE_ON_CLOSE flag is used so that CloseHandle can T be used to dynamically unload the VxD The CREATE_NEW flag is not necessary hDriver CreateFile S1D13x0x VxXD 0 0 0 CREATE_NEW FILE_FLAG_DELETE_ON_CLOSE 0 if hDriver INVALID HANDLE VALUE return 1 From
428. se 2 Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 25 Ts 1 Ts pixel clock period 2 timin t8min 9TS 3 18min REG 04h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 Ts 4 t62min REG O8h bits 4 0 x 8 Ts 5 t6bmin REG O8h bits 4 0 x 8 2 Ts 6 t7amin REG O8h bits 4 0 x 8 11 Ts 7 t70min REG O8h bits 4 0 x 8 11 t10 Ts Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 46 Epson Research and Development Vancouver Design Center 7 3 7 Single Color 8 Bit Panel Timing Format 2 le VDP sie VNDP y FPFRAME FPLINE j I j j l eel j l j fl I DRDY MOD X 0 X FPDAT 7 0 LINE1 X LINE2 X LINES X LINE4 XLINE479X LINE480 LINE1 X LINE2 Pi FPLINE DRDY MOD 4 HDP pe HNDP gt BE hy he e ia dE a MA AA AA EE FPDAT7 __ ___ X FRI YX 1 B3 1 66 x Ere X1 C838 XK FPDAT6 or Gi X 1 R4 X 1 86 Y 1 B638 X FPDATS B1 X 1 4 X 1 7 X Y y X1 R639 X FPDAT4 N R2 X _1 B4X_1 G7 X X Xy X FPDAT3 pupae X 1 85 X 1 B7 x Y 1 B639 X FPDAT2 __ 1B2X 16X1 A X XERO X FPDAT1 XK 1R X15 X 1 48 A Y Ns y FPDATO Kk 1 8 X 1 R6 Y 1 B8 ee YV VIBO y Diagram drawn with 2 FPLINE vertical blank period Example timing for a 640x480 panel
429. se falling edge to Shift Pulse falling edge t14 1 Ts t9 Shift Pulse period 2 Ts t10 Shift Pulse pulse width low 1 Ts t11 Shift Pulse pulse width high 1 Ts t12 FPDATT 7 0 setup to Shift Pulse falling edge 1 Ts t13 FPDAT 7 0 hold to Shift Pulse falling edge 1 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 39 Ts 1 Ts pixel clock period 2 Umin t8min 9Ts 3 tBmin REG O4h bits 6 0 1 x 8 REG O8h bits 4 0 4 x 8 x 2 Ts 5 t6min REG O8h bits 4 0 x 2 x 8 17 Ts 6 t min REG O8h bits 4 0 x 2 x 8 26 Ts Hardware Functional Specification S1D13705 Issue Date 02 02 01 X27A A 001 10 Page 52 Epson Research and Development Vancouver Design Center 7 3 10 9 12 Bit TFT D TFD Panel Timing VNDP gt VDP VNDP FPFRAME ple p4 FPLINE JO FPDAT 11 0 LINE480 LINE1 X X LINE480 DRDY FPLINE HNDP T HDP HNDP FPSHIFT Qe DRDY FPDAT 9 FPDAT 2 0 FPDAT 10 FPDAT 4 3 FPDAT 11 FPDAT 8 6 Note DRDY is used to indicate the first pixel Example Timing for 12 bit 640x480 panel Figure 7 25 12 Bit TFT D TFD Panel Timing VDP Vertical Display Period VNDP Vertical Non Display Period VNDP1 Vertical Non Display Period 1 VNDP2 Vertical Non Display Period 2 HDP Horizontal Display Period HNDP Horizontal Non Display Period HND
430. solutions and color depths only by modifying the source The S1D13705 test utilities and Windows CE v2 0 display drivers are available from your sales support contact or on the internet at http www eea epson com Interfacing to the NEC VR4181A Microprocessor 1D13705 Issue Date 01 02 13 X27A G 013 02 Page 16 Epson Research and Development Vancouver Design Center 6 References 6 1 Documents NEC VR4181A Target Specification Revision 0 5 9 11 98 Epson Research and Development Inc 1D13705 Hardware Functional Specification Document Number X27A A 002 xx e Epson Research and Development Inc S5UI13705B00C Rev 1 0 ISA Bus Evaluation Board User Manual Document Number X27A G 005 xx Epson Research and Development Inc S1D13705 Programming Notes and Examples Document Number X27A G 002 xx 6 2 Document Sources e NEC website at http www nec com e Epson Electronics America website at http www eea epson com S1D13705 Interfacing to the NEC VR4181A Microprocessor X27A G 013 02 Issue Date 01 02 13 Epson Research and Development Vancouver Design Center 7 Technical Support 7 1 Epson LCD Controllers S1D13705 Japan Seiko Epson Corporation Electronic Devices Marketing Division 421 8 Hino Hino shi Tokyo 191 8501 Japan Tel 042 587 5812 Fax 042 587 5564 http Awww epson co jp Hong Kong Epson Hong Kong Ltd 20 F Harbour Centre 25 Harbour Road Wanchai Hong Kong Tel 2585 4600 Fax
431. solves these contentions by forcing the host to wait until the resource arbitration is complete The Bus Status BS signal indicates that the address on the address bus is valid The WEO and RD signals is not used in the bus interface for MC68K 1 and must be tied high tied to IO Vpp 1D13705 X27A G 007 04 Page 26 4 4 MC68VZ328 To S1D13705 Interface 4 4 1 Hardware Description Using The MC68K 1 Host Bus Interface Epson Research and Development Vancouver Design Center The interface between the MC68VZ328 and the S1D13705 can be implemented using either the MC68K 1 or Generic 1 host bus interface of the S1D13705 The MC68VZ328 multiplexes dual functions on some of its bus control pins specifically UDS LDS and DTACK In implementations where all of these pins are available for use as bus control pins then the S1D13705 interface is a straightforward implementation of the MC68K 1 host bus interface Since AS is not provided by the DragonballVZ CSB1 is connected to BS and indicates that a valid address is on the bus The following diagram shows a typical implementation of the MC68VZ328 to S1D13705 using the MC68K 1 host bus interface For further information on the MC68K 1 host bus interface and AC Timing refer to the 1D13705 Hardware Functional Specification document number X27A A 001 xx MC68VZ328 S1D13705 A 16 0 gt AB 16 1 D 15 0 gt DB 15 0
432. son com for the latest revision of this document before beginning any development We appreciate your comments on our documentation Please contact us via email at techpubs O erd epson com Interfacing to the Motorola MCF5307 ColdFire Microprocessor S1D13705 Issue Date 01 02 13 X27A G 011 02 Page 8 Epson Research and Development Vancouver Design Center 2 Interfacing to the MCF5307 2 1 The MCF5307 System Bus 2 1 1 Overview The MCF5200 5300 family of processors feature a high speed synchronous system bus typical of modern microprocessors This section is an overview of the operation of the CPU bus to establish interface requirements The MCF5307 microprocessor family uses a synchronous address and data bus very similar in architecture to the MC68040 and MPC8xx All outputs and inputs are timed with respect to a square wave reference clock called BCLKO Master Clock This clock runs at a software selectable divisor rate from the machine cycle speed of the CPU core typically 20 to 33 MHz Both the address and the data bus are 32 bits in width All IO accesses are memory mapped there is no separate IO space in the Coldfire architecture The bus can support two types of cycles normal and burst Burst memory cycles are used to fill on chip cache memories and for certain on chip DMA operations Normal cycles are used for all other data transfers 2 1 2 Normal Non Burst Bus Transactions 1D13705 X27A G 011 02 A data
433. space Common memory may be accessed by a host system for memory read and write operations Attribute memory is used for defining card specific information such as configuration registers card capabilities and card use IO space maintains software and hardware compatibility with hosts such as the Intel x86 architecture which address peripherals independently from memory space Bit notation follows the convention used by most microprocessors the high bit is the most significant Therefore signals A25 and D15 are the most significant bits for the address and data bus respectively Support is provided for on chip DMA controllers To find further information on these topics refer to Section 6 References on page 15 PC Card bus signals are asynchronous to the host CPU bus signals Bus cycles are started with the assertion of either the CE1 and or the CE2 card enable signals The cycle ends once these signals are de asserted Bus cycles can be lengthened using the WAIT signal Note The PCMCIA 2 0 JEIDA 4 1 and later PC Card Standard support the two signals WAIT and RESET which are not supported in earlier versions of the standard The WAIT signal allows for asynchronous data transfers for memory attribute and IO ac cess cycles The RESET signal allows resetting of the card configuration by the reset line of the host CPU 2 1 2 Memory Access Cycles 1D13705 X27A G 009 02 A data transfer is initiated when the memory address i
434. ssue Date 01 02 13 X27A G 008 02 Page 10 3 S1D13705 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13705 that would be used to interface to the VR4102 VR4111 The 1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The interface mode used for the VR4102 VR4111 is e Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping darts Generic 2 AB 15 1 A 15 1 ABO AO DB 15 0 D 15 0 WE1 BHE CS External Decode BCLK BCLK BS connect to lO Vpp RD WR connect to lO Vpp RD RD WEO WE WAIT WAIT RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx 1D13705 X27A G 008 02 Interfacing to the NEC VR4102 VR4111 Microprocessor Issue Date 01 02 13 Epson Research and Development Vancouver Design Center Epson Research and Development Page 11 Vancouver Design Center 3 2 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13705 The Generic 2
435. ssue Date 02 01 22 Epson Research and Development Page 73 Vancouver Design Center Register 17h Look Up Table Data ae Write 16 RGB triplets to the LUT zy pLUT L T for tmp 0 tmp lt 16 tmp SET_REG 0x17 pLUT Set Red pLUT SET_REG 0x17 pLUT Set Green pLUT SET_REG 0x17 pLUT Set Blue pLUT Clear all of video memory by writing 81920 bytes of 0 xy pMem p13705 for tmp 0 tmp lt MEM_SIZE tmp pMem 0 pMem y Draw a 100x100 red rectangle in the upper left corner 0 0 of the display 7 for y 0 y lt 100 y Set the memory pointer at the start of each line EN Pointer MEM_OFFSET Y Line Width BPP 8 X BPP 8 pMem p13705 y 320 BitsPerPixel 8 0 for x 0 x lt 100 x pMem 0x4 Draw a pixel with LUT color 4 pMem Wait for the user to press a key before continuing rs printf Press any key to continue getch jk Set and use PORTRAIT mode ky Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 74 S1D13705 Epson Research and Development Vancouver Design Center Clear the display and all of video memory by writing 81920 bytes of 0 This is done because an image in display memory is not rotated when the switch to portrait display mode
436. st be multiples of 8 If a value is entered that does not match these require ments a notification box appears and 13705CFG rounds up the value to the next allowable width It is recommended that these automatically generated non display values be used without adjustment However manual adjustment may be useful in fine tuning the non display width and non display height These settings show the Frame Rate and Pixel Clock timings This field displays the effective frame rate of the LCD panel Panel dimensions are fixed therefore frame rate can only be adjusted by changing either PCLK or non display period values Higher frame rates correspond to smaller horizontal and vertical non display values or higher PCLK frequencies The pixel clock used for the LCD panel is displayed in this field The pixel clock is dependent on the CLKI frequency Specifies the delay in pixels from the start of the horizontal non display period to the leading edge of the FPLINE pulse This setting is only available when the selected panel type is TFT Refer to 1D13705 Hardware Functional Specifi cation document number X27A A 001 xx for a complete description of the FPLINE pulse settings 13705CFG Configuration Program Issue Date 02 03 11 Epson Research and Development Page 15 Vancouver Design Center TFT FPFRAME Start Pos Specifies the delay in lines from the start of the vertical non display period to the leading edge of the FPFRAME pul
437. start address is determined by a DIP switch setting See Table 2 1 Configu ration DIP Switch Settings on page 8 1 When switch S1 5 is in the closed position the S1D13705 is mapped into segments 0C0000h and ODOOOOh This memory space is in the first 1M byte of ISA bus memory and should be used if these segments are not taken up by other devices such as network adapters SCSI cards or other peripherals Note Since VGA and VGA compatible video adapters use address 0C8000 these cards can not be used while using the S5U13705BO0C board at this memory address A mono chrome display adapter a terminal or a non VGA compatible display adapter must be used 2 When switch S1 5 is in the open position the S1D13705 is mapped into the upper megabyte of ISA bus memory starting address of F00000h To use this memory on an ISA bus system the system BIOS has to be configured to set a memory hole starting at this address Some systems allow the user to configure the size of this hole and the starting address of where it begins while others just allow a 1M byte hole at the top of the 16M byte memory space This memory hole is configured by entering the system CMOS Setup Utility This memory space should be used if segments ODh and OEh are being used by other devices or if a VGA display adapter is needed Starting at the SRAM start address the board design decodes a 128K byte segment accom modating both the 80K byte display buffer and th
438. subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 QNX Photon v2 0 Display Driver X27A E 005 01 Issue Date 01 09 10 Epson Research and Development Page 3 Vancouver Design Center QNX Photon v2 0 Display Driver The Photon v2 0 display drivers for the S1D13705 Color LCD Controller are intended as reference source code for OEMs developing for QNX platforms The driver package provides support for 8 bit per pixel color depths The source code is written for portability and contains functionality for most features of the S1D13705 Source code modification is required to provide a smaller driver for mass production The current revision of the driver is designed for use with either QNX RTP or QNX4 from the latest product CD Dec 99 The Photon v2 0 display driver is designed around a common configuration include file called S1D13705 h which is gene
439. t Inc does not assume liability for any damage done to the display device as a result of configuration errors 13705CFG Configuration Program Issue Date 02 03 11 EPSON 1D13705 Embedded Memory LCD Controller 13705SHOW Demonstration Program Document No X27A B 002 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation All other Trademarks are the property of their respective owners Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 13705SHOW Demonstration Program X27A B 002 02 Issue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center 13705SHOW 13705SHOW is a program designed to demonstrate rudimentary display capabilities of the S1D13705 The display abilities are shown by drawing a pattern image to the video display at all supported color depths 1 2 4 and 8 bits per pixel The 13705SHOW display utility must be
440. t Page 11 Vancouver Design Center 3 3 Generic 2 Interface Mode Generic 2 interface mode is a general and non processor specific interface mode on the S1D13705 The Generic 2 interface mode was chosen for this interface due to the simplicity of its timing and compatibility with the PR31500 PR31700 control signals The interface requires the following signals BUSCLK is a clock input which synchronizes transfers between the host CPU and the S1D13705 It is separate from the input clock CLKI and is typically driven by the host CPU system clock The address inputs ABO through AB16 and the data bus DBO through DB15 connect directly to the CPU address and data bus respectively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WE1F is the high byte enable for both read and write cycles WEO is the write enable signal for the S1D13705 to be driven low when the host CPU is writing data from the S1D13705 RD is the read enable for the S1D13705 to be driven low when the host CPU is reading data from the S1D13705 WAIT is a signal which is output from the S1
441. t Transfer Complete Starts Figure 2 1 MCF5307 Memory Read Cycle sexo J Ill id LU UL TS TA TIP AHO Xo o X RW XX LIO SIZ 1 0 TT 1 0 X Drst 0 XXXXXXX valid XXX Transfer Start Wait States Transfer Next Transfer Complete Starts Figure 2 2 MCF5307 Memory Write Cycle Burst Cycles Burst cycles are very similar to normal cycles except that they occur as a series of four back to back 32 bit memory reads or writes with the TIP Transfer In Progress output asserted continuously through the burst Burst memory cycles are mainly intended to facil itate cache line fill from program or data memory they are typically not used for transfers to or from IO peripheral devices such as the S1D13705 The MCF5307 chip selects provide a mechanism to disable burst accesses for peripheral devices which are not able to support them Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 13 1D13705 X27A G 011 02 Page 10 Epson Research and Development Vancouver Design Center 2 2 Chip Select Module S1D13705 X27A G 011 02 In addition to generating eight independent chip select outputs the MCF5307 Chip Select Module can generate active low Output Enable OE and Write Enable BWE signals compatible with most memory and x86 style peripherals The MCF5307 bus controller also provides a Read Write R W signal w
442. t is up to the programmer to ensure that they adhere to the interface and use valid pointers Programmers are recommended to use the highest warning levels of their compiler in order to verify the parameter types 9 4 API for 13705HAL This section is a description of the HAL library Application Programmers Interface API Updates and revisions to the HAL may include new functions not included in this documen tation Table 9 1 HAL Functions Function Description Registers the S1D13705 parameters with the HAL calls selnitHal if necessary seRegisterDevice seRegisterDevice MUST be the first HAL function called by an application Programs the S1D13705 for use with the default settings calls seSetDisplayMode to do the seSetinit work clears display memory Note either seSetlnit or seSetDisplayMode must be called AFTER calling seRegisterDevice seGetld Interpret the revision code register to determine chip id seGetHalVersion Return version information on the HAL library seGetLastUsableByte Determine the offset of the last unreserved usable byte in the display buffer seGetBytesPerScanline Determine the number of bytes or memory consumed per scan line in current mode seGetScreenSize Determine the height and width of the display surface in pixels seDelay Use the frame rate timing to delay for required seconds requires registers to be initialized seSetHighPerformance Used in color
443. ta Ley from Display Buffer _ unused Look Up Table entries Figure 11 4 1 Bit per pixel Color Mode Data Output Path Hardware Functional Specification Issue Date 02 02 01 1D13705 X27A A 001 10 Page 74 Epson Research and Development Vancouver Design Center 2 Bit per pixel Color Mode Red Look Up Table 256x4 oi 7 4 bit Red Data 7 01 gt 02 10 03 A OL 04 pa Eo 7 FD FE FF 7 00 4 bit Green Data 01 gt De 10 03 11 Ba FC FD FE FF Blue Look Up Table 256x4 P Wee a 00 4 bit Blue Data 01 gt E 10 03 11 04 E ji FD FE FF 2 bit per pixel data from Display Buffer unused Look Up Table entries Figure 11 5 2 Bit per pixel Color Mode Data Output Path S1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Vancouver Design Center 4 Bit per pixel Color Mode Page 75 4 bit per pixel data Red Look Up Table 256x4 t 0000 t 0001 10010 10011 10100 10101 10110 10111 1000 1001 1010 1011 1100 1101 1110 1111 Green Look Up Table 256x4 0000 000
444. talled as follows 1 2 Install the evaluation board in the computer and boot the computer Copy the files S1D13XXX INF and S1D13XXX SYS to a directory on a local hard drive Right click your mouse on the file SID13XXX INF and select INSTALL from the menu Windows will install the device driver and ask you to restart S1D13XXX 32 Bit Windows Device Driver Installation Guide Issue Date 01 04 17 X00A E 003 04 Page 4 Windows 2000 Epson Research and Development Vancouver Design Center All PCI Bus Evaluation Cards 9 Install the evaluation board in the computer and boot the computer Windows will detect the new hardware as a new PCI Device and bring up the FOUND NEW HARDWARE dialog box Click NEXT The New Hardware Wizard will bring up the dialog box to search for a suitable driver Click NEXT When Windows does not find the driver it will allow you to specify the location of it Type the driver location or select BROWSE to find it Click NEXT Windows 2000 will open the installation file and show the option EPSON PCI Bridge Card Select this file and click OPEN Windows then shows the path to the file Click OK 10 Click NEXT 11 Click FINISH All ISA Bus Evaluation Cards X00A E 003 04 1 2 Install the evaluation board in the computer and boot the computer Go to the CONTROL PANEL and select ADD REMOVE HARDWARE click NEXT Select ADD TROUBLESHOOT A DEVICE and click NEXT Wind
445. tate signal is active high The Bus Status BS signal is not used in the bus interface for Generic 1 mode However BS is used to configure the 1D13705 for Generic 1 mode and should be tied low connected to GND Interfacing to the Motorola MPC821 Microprocessor Issue Date 01 02 13 Epson Research and Development Page 15 Vancouver Design Center 4 MPC821 to S1D13705 Interface 4 1 Hardware Description The interface between the S1D13705 and the MPC821 requires minimal glue logic One inverter is required to change the polarity of the WAIT signal an active low signal to insert wait states in the bus cycle The MPC821 Transfer Acknowledge signal TA is an active low signal which ends the current bus cycle The inverter is enabled using CS so that TA is not driven by the S1D13705 during non S 1D 13705 bus cycles A single resistor is used to speed up the rise time of the WAIT TA signal when terminating the bus cycle BS bus start is not used in this implementation and should be tied low connected to GND The following diagram shows a typical implementation of the MPC821 to S1D13705 interface MPC821 S1D13705 A 15 31 gt AB 16 0 D O 15 k gt DB 15 0 cs4 CS Vcc BS 470 7 G 4 WAIT m o Y WE1 m v WEO O m v RD WR gt RD SYSCLK BUSCLK y System RESET RESET Note When
446. tempt to match a mode table against them All values must be present and valid for a match to occur otherwise the display driver will default to the FIRST mode table in your list A WinCE desktop application or control panel applet can change these registry values and the display driver will select a different mode upon warmboot This allows the display driver to support different display configurations and or orientations An example appli cation that controls these registry values will be made available upon the next release of the display driver preliminary alpha code is available by special request Windows6 CE 2 x Display Drivers Issue Date 01 06 07 Epson Research and Development Page 13 Vancouver Design Center Comments e The display driver is CPU independent allowing use of the driver for several Windows CE Platform Builder supported platforms e When using 13705CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number e At this time the drivers have been tested on the x86 CPUs and have been run with version 2 0 of the ETK Platform Builder v2 1x Windows CE 2 x Display Drivers 1D13705 Issue Date 01 06 07 X27A E 001 03 Page 14 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Windows6 CE 2 x Display Driver
447. the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WEO and WE1 are write enables for the low order and high order bytes respectively to be driven low when the host CPU is writing data to the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU RD and RD WR are read enables for the low order and high order bytes respectively to be driven low when the host CPU is reading data from the S1D13705 These signals must be generated by external hardware based on the control outputs from the host CPU WAIT is a signal output from the 1D13705 that indicates the host CPU must wait until data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update 1t is possible that contention may occur in accessing the S1D13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS
448. the icon Build Minshell for x86 d Drag the icon Build Minshell for x86 onto the desktop using the right mouse button Windows CE 2 x Display Drivers Issue Date 01 06 07 Epson Research and Development Page 7 Vancouver Design Center e Choose Copy Here f Rename the icon Build Minshell for x86 to Build Epson for x86 by right clicking on the icon and choosing rename g Right click on the icon Build Epson for x86 and click on Properties to bring up the Build Epson for x86 Properties window h Click on Shortcut and replace the string Minshell under the entry Target with Epson i Click on OK to finish 5 Create an EPSON project a Make an Epson directory under x wince public b Copy MAXALL and its sub directories x wince public maxall to the Epson di rectory xcopy s e x wince public maxall wince public epson c Rename x wince public epson maxall bat to epson bat d Edit EPSON BAT to add the following lines to the end of the file echo on set CEPC_DDI_S1D13705 1 echo off 6 Make an S1D13705 directory under x wince platform cepc drivers display and copy the S1D13705 driver source code into x wince platform cepc drivers dis play S1D13705 7 Edit the file x wince platform cepc drivers display dirs and add S1D13705 into the list of directories 8 Edit the file x wince platform cepc files platform bib and make the
449. their four colors by indexing into positions O through 3 of the Look Up Table These four LUT entries can be set to any of the 4096 possible color combinations Monochrome panels derive four gray shades by indexing into the first four elements of the green component of the Look Up Table Any of the four LUT entries can be set to any of the sixteen possible gray shades Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pixel 0 Pixel 0 Pixel 1 Pixel 1 Pixel 2 Pixel 2 Pixel 3 Pixel 3 Bit 1 Bit O Bit 1 Bit O Bit 1 Bit 0 Bit 1 Bit 0 Figure 3 2 Pixel Storage for 2 Bpp 4 Colors Gray Shades in One Byte of Display Buffer 3 3 4 Bit Per Pixel 16 Colors Gray Shades Four bit pixels support 16 color gray shades In this memory format each byte of display buffer contains two adjacent pixels Setting or resetting any pixel requires reading the entire byte masking out the upper or lower nibble 4 bits and setting the appropriate bits to 1 Color panels can display up to sixteen colors simultaneously These sixteen colors are derived by indexing into the first sixteen elements of the Look Up Table Each of these colors may be selected from the 4096 possible available colors On a monochrome panel the gray shades are generated by indexing into the first sixteen green components of the LUT Each of these sixteen possible gray shades can be adjusted to any of the sixteen possible gray shades For instance one could pr
450. there is no separate IO space in the Power PC architecture Support is provided for both on chip DMA controllers and off chip other processors and peripheral controllers bus masters For further information on this topic refer to Section 6 References on page 23 The bus can support both normal and burst cycles Burst memory cycles are used to fill on chip cache memory and for certain on chip DMA operations Normal cycles are used for all other data transfers 1D13705 Interfacing to the Motorola MPC821 Microprocessor X27A G 010 02 Issue Date 01 02 13 Epson Research and Development Page 9 Vancouver Design Center 2 2 1 Normal Non Burst Bus Transactions A data transfer is initiated by the bus master by placing the memory address on address lines AO through A31 and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e TSIZ 0 1 Transfer Size indicates whether the bus cycle is 8 16 or 32 bit e RD WR set high for read cycles and low for write cycles e AT 0 3 Address Type Signals provides more detail on the type of transfer being attempted When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle to complete the bus transaction Once TA has been asserted the MPC821 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction
451. third LUT entry and 11 displays a color from the fourth LUT entry The following table shows the example values for 2 bit per pixel display mode Table 4 2 Example LUT Values for 2 Bpp Color Mode Index Red Green Blue 00 00 00 00 01 70 70 70 02 AO AO AO 03 FO FO FO 04 00 00 00 00 00 00 FF 00 00 00 indicates unused entries Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Page 19 Vancouver Design Center 4 bpp color When the 1D13705 is configured for 4 bpp color mode the displayed colors are selected from the first sixteen entries of the Look Up Table The LUT entries may be set to any of the 4096 possible colors Each byte in the display buffer contains two adjacent pixels If a nibble has a value of 0000 then the color in LUT index 0 is displayed A nibble value of 0001 results in the color in LUT index 1 being displayed The pattern continues to the nibble pattern of 1111 which results in the sixteenth color of the Look Up Table being displayed The following table shows the example values for 4 bit per pixel display mode These colors simulate the colors used by the sixteen color modes of a VGA Table 4 3 Suggested LUT Values to Simulate VGA Default 16 Color Palette Index Red Green Blue 00 00 00 00 01 00 00 AO 02 00 AO 00 03 00 AO AO 04 AO
452. tion of the viewport Scrolling down causes the image to appear to slide up and scrolling up causes the image to appear to slide down Both panning and scrolling are performed by modifying the start address register The start address registers in the S1D13705 are a word offset to the data to be displayed in the top left corner of a frame Changing the start address by one means a change on the display of the number of pixels in one word The number of pixels in word varies according to the color depth At 1 bit per pixel a word contains sixteen pixels At 2 bit per pixel there are eight pixels at 4 bit per pixel there are four pixels and at 8 bit per pixel there is two pixels in each word The number of pixels in each word represent the finest step we can pan to the left or right When portrait mode see Hardware Rotation on page 37 is enabled the start address registers become offsets to bytes In this mode the step rate for the start address registers if halved making for smoother panning Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 28 Epson Research and Development Vancouver Design Center 5 2 1 Registers REG 0Ch Screen 1 Display Start Address 0 LSB Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Start Addr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REG 0Dh Screen 1 Display Start Address 1 MSB Start Addr Start Addr Start Ad
453. tively On 32 bit big endian architec tures such as the Power PC the data bus would connect to the high order data lines on little endian hosts or 16 bit big endian hosts they would connect to the low order data lines The hardware engineer must ensure that CNF3 selects the proper endian mode upon reset Chip Select CS is driven by decoding the high order address lines to select the proper register and memory address space WE1F is the high byte enable for both read and write cycles for the S1D13705 to be driven low when the host CPU accesses the 1D13705 WEO is the write enable for the S1D13705 to be driven low when the host CPU is reading data from the 1D13705 RD is the read enable for the S1D13705 to be driven low when the host CPU is reading data from the 1D13705 WAIT is a signal which is output from the S1D137053 to the host CPU that indicates when data is ready read cycle or accepted write cycle on the host bus Since host CPU accesses to the S1D13705 may occur asynchronously to the display update it is possible that contention may occur in accessing the 13705 internal registers and or refresh memory The WAIT line resolves these contentions by forcing the host to wait until the resource arbitration is complete This signal is active low and may need to be inverted if the host CPU wait state signal is active high The Bus Status BS and Read Write RD WR signals are not used in the bus inter face for Generic
454. transfer is initiated by the bus master by placing the memory address on address lines A31 through AO and driving TS Transfer Start low for one clock cycle Several control signals are also provided with the memory address e SIZ 1 0 Transfer Size which indicate whether the bus cycle is 8 16 or 32 bits in width e R W which is high for read cycles and low for write cycles e A set of transfer type signals TT 1 0 which provide more detail on the type of transfer being attempted TIP Transfer In Progress which is asserted whenever a bus cycle is active When the peripheral device being accessed has completed the bus transfer it asserts TA Transfer Acknowledge for one clock cycle completing the bus transaction Once TA has been asserted the MCF5307 will not start another bus cycle until TA has been de asserted The minimum length of a bus transaction is two bus clocks Figure 2 1 illustrates a typical memory read cycle on the MCF5307 system bus and Figure 2 2 illustrates a memory write cycle Interfacing to the Motorola MCF5307 ColdFire Microprocessor Issue Date 01 02 13 Epson Research and Development Vancouver Design Center Page 9 BCLKO TS TA TIP Ast X Rw XV XXXXXK SIZ 1 0 TT 1 0 X A D131 0 0000000000000 00000 JU Sampled when TA low Transfer Start Wait States Transfer Nex
455. ty This discussion of display rotation is intended to augment the excellent description of the hardware functionality found in the Hardware Functional Specification The S1D13705 supports two portrait modes Default Portrait Mode and Alternate Portrait Mode 7 2 Default Portrait Mode Default portrait mode was designed to reduce power consumption for portrait mode use The reduced power consumption comes with certain trade offs The most obvious difference between the two modes is that Default Portrait Mode requires the portrait width be a power of two e g a 240 line panel used in portrait mode requires setting a virtual width of 256 pixels Also default portrait mode is only capable of scrolling the display in two line increments The benefits to using default portrait mode lies in the ability to use a slower input clock and in reduced power consumption The following figure depicts the ways to envision memory layouts for the S1D137053 in default portrait mode This example uses a 320x240 panel Programming Notes and Examples 1D13705 Issue Date 02 01 22 X27A G 002 03 Page 38 Epson Research and Development Vancouver Design Center physical memory start Sus 236 address aly B E 7 A g portrait P a o window display S o A start 58 ai address a s lt O y C D vou 4 320 SS 240 image seen by programmer image refreshed by S1D13705 image in display buffer Figure
456. type clocks decode addresses rotation etc by OEMs For further information on 13705CFG see the 13705CFG Configuration Program User Manual document number X27A B 001 xx Note The Linux console driver is provided as reference source code only The driver is in tended to provide a basis for OEMs to develop their own drivers for Linux This document and the source code for the Linux console drivers are updated as appro priate Please check the Epson Research and Development website at http www erd epson com for the latest revisions or before beginning any development We appreciate your comments on our documentation Please contact us via e mail at documentation erd epson com S1D13705 X27A E 004 02 Page 4 Epson Research and Development Vancouver Design Center Building the Console Driver for Linux Kernel 2 2 x S1D13705 X27A E 004 02 Follow the steps below to construct a copy of the Linux operating system using the S1D13705 as the console display device These instructions assume that the GNU devel opment environment is installed and the user is familiar with GNU and the Linux operating system 1 Acquire the Linux kernel source code You can obtain the Linux kernel source code from your Linux supplier or download the source from ftp ftp kernel org The S1D13705 reference driver requires Linux kernel 2 2 x or greater The example S1D13705 reference driver available on www erd epson com was built using Red Hat
457. ual split screen operation a enables automatic split screen operation a timer is used to move screen 2 1 display the help screen After starting 13705SPLT the following keyboard commands are available Manual mode u move Screen 2 up de a move Screen 2 down HOME covers Screen 1 with Screen 2 END displays only Screen 1 Automatic mode any key change the direction of split screen movement for PC only Both modes b changes the color depth bits per pixel ESC exits 13705SPLT 13705SPLT Display Utility Issue Date 01 02 12 Epson Research and Development Page 5 Vancouver Design Center 13705SPLT Example 1 Type 13705splt a to automatically move the split screen 2 Press b to change the color depth from 1 bit per pixel to 2 bit per pixel 3 Repeat step 2 for the remaining color depths 4 and 8 bit per pixel 4 Press lt ESC gt to exit the program Program Messages ERROR Did not find a 13705 device The HAL was unable to read the revision code register on the S1D13705 Ensure that the S1D13705 hardware is installed and that the hardware platform has been configured correctly Also check that the display memory address has been configured correctly ERROR Unable to locate load S1D13XXX VXD 13705PLAY was unable to load a required driver The file S1D13XXX VXD should be located in x WINDOWS SYSTEM or in xNWINNTAS Y STEM If the file is not there install it as described in the S1D13XXX 32 Bit Windows
458. ue Date 01 02 12 Epson Research and Development Page 3 Vancouver Design Center 13705BMP Installation Usage Comments 13705BMP is a demonstration program for the S1D13705 which can read and display BMP format Windows bitmap files The 13705BMP display utility is designed to operate on an x86 based personal computer There are both 16 bit and 32 bit versions of 13705BMP The 16 bit version is for use under DOS when the S1D13705 evaluation board has been configured for D0000 The 32 bit version is intended for use under Win32 Before use 13705BMP must be configured for the display system Consult documentation for the program 13705CFG EXE which can be used to configure 13705BMP 13705BMP is not supported on non PC platforms For 16 Bit Program Version copy the file 13705BMP EXE to a directory that is in the DOS path on your hard drive For 32 Bit Program Version install the 32 bit Windows device driver S1D13X0X VXD as described in the S1D13X0X 32 Bit Windows Device Driver Installation Guide document number XOOA E 003 xx Copy the file 13705BMP EXE to a directory that is in the DOS path on your hard drive At the prompt type 13705bmp bmp_file a time 1 p noinit Where bmp_file the name of the file to display a time automatic mode returns to the operating system after time seconds If time is not specified the default is 5 seconds This option is intended for use with batch files to automate displ
459. ugh this host bus interface that the S1D13705 connects to the PR31500 PR31700 processor The S1D13705 can be successfully interfaced using one of two configurations e Direct connection to PR31500 PR31700 see Section 4 Direct Connection to the Philips PR31500 PR31700 on page 12 e System design using one ITE IT8368E PC Card GPIO buffer chip see Section 5 Using the ITE IT8368E PC Card Buffer on page 15 Interfacing to the Philips MIPS PR31500 PR31700 Processor Issue Date 01 02 13 Epson Research and Development Page 9 Vancouver Design Center 3 S1D13705 Host Bus Interface This section is a summary of the host bus interface modes available on the S1D13705 that would be used to interface to the PR31500 PR31700 The S1D137053 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The interface modes used for the PR31500 PR31700 are e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte e Generic 2 External Chip Select shared Read Write Enable for high byte individual Read Write Enable for low byte 3 1 Host Bus Pin Connection The following table shows the functions of each host bus interface signal Table 3 1 Host Bus Interface Pin Mapping lA Generic 1 Generic 2 AB 15 1 A 15 1 A 15 1 ABO AO AO DB 15 0 D 15 0 D 15 0 WE1
460. umber X27A E 004 02 Copyright 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or International Patent laws EPSON is a registered trademark of Seiko Epson Corporation Page 2 Epson Research and Development Vancouver Design Center THIS PAGE LEFT BLANK S1D13705 Linux Console Driver X27A E 004 02 Issue Date 01 09 19 Epson Research and Development Page 3 Vancouver Design Center Linux Console Driver Linux Console Driver Issue Date 01 09 19 The Linux console driver for the S1D13705 Embedded Memory LCD Controller is intended as reference source code for OEMs developing for Linux and supports 4 and 8 bit per pixel color depths A Graphical User Interface GUI such as Gnome can obtain the frame buffer address from this driver allowing the Linux GUI the ability to update the display The console driver is designed around a common configuration include file called s1d13705 h which is generated by the configuration utility 13705CFG This design allows for easy customization of display
461. ummary of the host bus interface mode used on the S1D13705 to interface to the MPC821 The S1D13705 implements a 16 bit interface to the host microprocessor which may operate in one of several modes compatible with most of the popular embedded microprocessor families The interface mode used for the MPC821 is e Generic 1 Chip Select plus individual Read Enable Write Enable for each byte 3 1 Host Bus Interface Modes Table 3 1 Host Bus Interface Pin Mapping elaine Generic 1 AB 15 1 A 15 1 ABO AO DB 15 0 D 15 0 WE1 WE1 CS External Decode BCLK BCLK BS connect to Vss RD WR RD1 RD RDO WEO WEO WAIT WAIT RESET RESET For details on configuration refer to the S1D13705 Hardware Functional Specification document number X27A A 001 xx Interfacing to the Motorola MPC821 Microprocessor 1D13705 Issue Date 01 02 13 X27A G 010 02 Page 14 Epson Research and Development Vancouver Design Center 3 2 Generic 1 Host Bus Interface Mode 1D13705 X27A G 010 02 Generic 1 host bus interface mode is the most general and least processor specific host bus interface mode on the S1D13705 The Generic 1 host bus interface mode was chosen for this interface due to the simplicity of its timing The host bus interface requires the following signals BUSCLK is a clock input which is required by the S1D13705 host interface It is sepa rate from the input clock CL
462. uses these values but does not refer to this array In a typical application these values would be written to the registers using a loop hh unsigned char Reg 0x20 0x00 0x23 0xC0 0x03 0x27 OxEF 0x00 0x00 0x00 0x00 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 OxFF 0x03 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 y define MEM_SIZE 0x14000 80 kb display buffer typedef unsigned short WORD Some useful types typedef unsigned long DWORD typedef unsigned char BYTE typedef BYTE PBYTE define LOBYTE BYTE w define HIBYTE BYTE WORD w gt gt 8 OxFF define SET_REG idx val pRegs idx val js void main void PBYTI PBYTI p13705 pRegs PBYTE pMem PBYTE pLUT int X y tmp E E E E int BitsPerPixel 8 int Width 320 int Height 240 int OffsetBytes int rc fk Get a linear address we can use in our code to access the s1D13705 This is only needed to access the S1D13705 on the ISA eval board Programming Notes and Examples S1D13705 Issue Date 02 01 22 X27A G 002 03 Page 70 S1D13705 Epson Research and Development Vancouver Design Center DWORD dwLinearAddress rc IntelGetLinAddressW32 0xF00000 amp dwLinearAddress if re 0 printf Error getting linear address return p13705 PBYTE dwLinea
463. ve FPDAT 11 0 FPSHIFT see note Forced Low Forced Low Active FPLINE FPFRAME DRDY Forced Low Forced Low Active Note When FPDAT 11 8 are designated as GPIO outputs the output state prior to enabling the Power Save Mode is maintained When FPDAT 11 8 are designated as GPIO in puts unused inputs must be tied to either IO Vpp or GND see Table 5 5 LCD Inter face Pin Mapping on page 23 13 4 Panel Power Up Down Sequence After chip reset or when entering exiting a power save mode the Panel Interface signals follow a power on off sequence shown below This sequence is essential to prevent damage to the LCD panel Hardware Functional Specification 1D13705 Issue Date 02 02 01 X27A A 001 10 Page 84 Epson Research and Development Vancouver Design Center RESET Software Power Save REG 03h bits 1 0 or Hardware Power Save LCDPWR Panel Interface Output Signals except LCDPWR y 00 Power Save Mode gt 0 frame power up 127 frames power down gt 0 frame power up 13 5 Turning Off BCLK Between Accesses S1D13705 X27A A 001 10 Figure 13 1 Panel On Off Sequence After chip reset LCDPWR is inactive and the rest of the panel interface output signals are held low Software initializes the chip i e programs all registers except the Look Up Table registers and the
464. ve the controller ID 1D13705 values returned in pID are ID_S1D13705_REVO ID_UNKNOWN Other HAL libraries will return their respective controller IDs upon detection of their controller ERR_OK operation completed with no problems ERR_UNKNOWN_DEVICE the HAL was unable to identify the display controller Returned when pID returns ID_UNKNOWN void seGetHalVersion const char pVersion const char pStatus const char pStatusRevision Description Parameters Return Value Example 1D13705 X27A G 002 03 Retrieves the HAL library version The return pointers are all to ASCII strings A typical return would be pVersion 1 01 HAL version 1 01 pStatus B The B is the beta designator pStatusRevision 5 The programmer need only create pointers of const char type to pass as parameters see Example below pVersion Pointer to string to return the version in must point to an allocated string of size VER_SIZE pStatus Pointer to a string to return the release status in must point to an allocated string of size STATUS_SIZE pStatusRevision Pointer to return the current revision of status must point to an allocated string of size STAT_REV_SIZE None const char pVersion pStatus pStatusRevision seGetHalVersion amp pVersion amp pStatus amp pStatusRevision Programming Notes and Examples Issue Date 02 01 22 Epson Research and Development Vancouver Design C
465. w See Host Bus Selection table below CNF2 CNF3 Little Endian Big Endian CNF4 Active low LCDPWR signal Active high LCDPWR signal configuration for 8 bit processor host bus interface Table 4 2 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus Interface Ss required configuration for this application 4 3 Register Memory Mapping 1D13705 X27A G 015 01 The S1D13705 needs a 128K byte block of memory to accommodate its 80K byte display buffer and its 32 byte register set The starting memory address is located at 00000h of the 128K byte memory block while the internal registers are located in the upper 32 bytes of this memory block i e REG 0 1FFEOh An external decoder can be used to decode the address lines and generate a chip select for the S1D13705 whenever the selected 128K byte memory block is accessed If the processor supports a general chip select module its internal registers can be programmed to generate a chip select for the S1D13705 whenever the 1D13705 memory block is accessed Interfacing to an 8 bit Processor Issue Date 01 12 20 Epson Research and Development Page 13 Vancouver Design Center 5 Software Test utilities and display drivers are available for the S1D13705 Full source code is available for both the test utilities and the drivers The test utilities are configurable for different panel types using a program called 13705CFG The display drivers can be customized by the OEM for different p
466. x4 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 1111 1110 Blue Look Up Table 256x4 00 0000 0000 01 0000 0001 02 0000 0010 03 0000 0011 04 0000 0100 05 0000 0101 06 0000 0110 07 0000 0111 F8 1111 1000 F9 1111 1001 FA 1111 1010 FB 1111 1011 FC 1111 1100 FD 1111 1101 FE 1111 1110 FF 1111 1111 Las from Display Buffer 4 bit Red Data 4 bit Green Data 4 bit Blue Data 1D13705 X27A A 001 10 Figure 11 7 8 Bit per pixel Color Mode Data Output Path Hardware Functional Specification Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 77 12 SwivelView Many of todays applications use the LCD panel in a portrait orientation In this case it becomes necessary to rotate the displayed image by 90 This rotation can be done by software at the expense of performance or it can be done by the S1D13705 hardware with no CPU penalty There are two SwivelView modes Default Swivel View Mode and Alternate SwivelView Mode 12 1 Default SwivelView Mode Default SwivelView Mode requires the SwivelView image width be a power of two e g a 240 line panel requires a minimum virtual image width of 256 This mode should be used whenever the required virtual image can be contained within the integrated display buffer i e
467. y PORepaint Change PORepaint as follows PORepaint dword 2 Windows CE 3 x Display Drivers 1D13705 Issue Date 01 05 25 X27A E 006 01 Page 16 Epson Research and Development Vancouver Design Center Comments e The display driver is CPU independent allowing use of the driver for several Windows CE Platform Builder supported platforms e If you are running 13705CFG EXE to produce multiple MODE tables make sure you change the Mode Number in the WinCE tab for each mode table you generate The display driver supports multiple mode tables but only if each mode table has a unique mode number e At this time the drivers have been tested on the x86 CPUs and have been built with Plat form Builder v3 00 S1D13705 Windows6 CE 3 x Display Drivers X27A E 006 01 Issue Date 01 05 25 EPSON S1D13705 Embedded Memory LCD Controller Interfacing to the Toshiba MIPS TMPR3912 Microprocessor Document Number X27A G 004 02 Copyright O 2001 Epson Research and Development Inc All Rights Reserved Information in this document is subject to change without notice You may download and use this document but only for your own use in evaluating Seiko Epson EPSON products You may not modify the document Epson Research and Development Inc disclaims any representation that the contents of this document are accurate or current The Programs Technologies described in this document may contain material protected under U S and or Internati
468. y is available on the LCD module therefore only panels which have their own bias voltage supply or those that use a positive supply can be connected to J4 The LCD module can only support these panels as well Header J4 and its associated buffers and components have been left unpopulated on the CPU module These parts can be added by the user if desired 4 3 LCD Controller 4 3 1 S1D13704 vs S1D13705 The LCD controller used in conjunction with the TMPR3912 22U microprocessor can either be a S1D13704 or aS1D13705 If a S1D13704 is used jumper JP7 must be set to position 1 2 This setting allows CNF4 to be configured for the S1D13704 CNF4 controls the polarity of the LCDPWR signal and can be set either high or low with jumper JP11 If a S1D13705 is used jumper JP7 must be set to position 2 3 This setting allows pin 45 of the LCDC to be used as address bit AB16 which is needed on the S1D13705 to accom modate the larger display memory 4 3 2 LCDPWR Polarity The power supply on the LCD module used LCDON an active low signal to turn on the supply This signal is connected to LCDPWR Since LCDPWR is configurable on the S1D13704 and is set active high on the S1D13705 a facility must be provided to invert this signal if it is active high so that LCDON will be the right polarity to turn on the LCD power supply Jumper JP10 must be set to position 1 2 if LCDPWR is active low and to position 2 3 if LCDPWR is active high 4 3 3 S1D1370417
469. ystem RESET gt RESET ADD 16 0 gt AB 16 0 DATA 15 0 DB 15 0 BUSCLK BUSCLK Vec y BS Vcc T RD WR Note When connecting the S1D13705 RESET pin the system designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 Typical Implementation of VR4102 VR4111 to SID137053 Interface S1D13705 Interfacing to the NEC VR4102 VR4111 Microprocessor X27A G 008 02 Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center 4 2 S1D13705 Hardware Configuration The S1D13705 uses CNF3 through CNFO and BS to allow selection of the bus mode and other configuration data on the rising edge of RESET Refer to the 7D13705 Hardware Functional Specification document number X27A A 001 xx for details The tables below show those configuration settings important to the Generic 2 host bus interface Table 4 1 Summary of Power On Reset Options Signal value on this pin at the rising edge of RESET is used to configure 0 1 0 1 CNFO CNF1 See Host Bus Selection table below See Host Bus Selection table below CNF2 configuration for NEC VR4102 VR4111 support Table 4 2 Host Bus Selection CNF2 CNF1 CNFO BS Host Bus Interface configuration for NEC VR4102 VR4111 support Interfacing to the NEC VR4102 VR4111 Microp
470. ystem designer should be aware of all conditions that may reset the S1D13705 e g CPU reset can be asserted during wake up from power down modes or during debug states Figure 4 1 SID13705 to TMPR3912 Direct Connection Note See Section 3 1 on page 9 and Section 3 3 on page 11 for Generic 2 pin descriptions S1D13705 Interfacing to the Toshiba MIPS TMPR3912 Microprocessor X27A G 004 02 Issue Date 01 02 13 Epson Research and Development Page 13 Vancouver Design Center The Generic 2 host interface control signals of the S1D13705 are asynchronous with respect to the S1D13705 bus clock This gives the system designer full flexibility to choose the appropriate source or sources for CLKI and BCLK The choice of whether both clocks should be the same and whether to use DCLKOUT divided as clock source should be based on the desired e pixel and frame rates e power budget e part count e maximum S1D13705 clock frequencies The S1D13705 also has internal clock dividers providing additional flexibility 4 2 Memory Mapping and Aliasing In this example implementation the TMPR3912 control signal CARDREG is ignored therefore the S1D13705 takes up the entire PC Card slot 1 The S1D13705 requires an addressing space of 128K bytes The on chip display memory occupies the range O through 13FFFh The registers occupy the range 1FFEOh through 1FFFFh The TMPR3912 demultiplexed address lines A17 and above are ignored thus the
471. zontal Horizontal Horizontal Horizontal Horizontal Horizontal Horizontal n a Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit Panel Size Bit 6 5 4 3 2 1 0 bits 6 0 Horizontal Panel Size Bits 6 0 This register determines the horizontal resolution of the panel This register must be pro grammed with a value calculated as follows HorizontalPanelSizeRegister Note This register must not be set to a value less than 03h A 1 8 REG 05h Vertical Panel Size Register LSB Address 1FFE5h Read Write Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Vertical Panel Size Size Size Size Size Size Size Size Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O REG 06h Vertical Panel Size Register MSB Address 1FFE6h Read Write Vertical Panel Vertical Panel n a n a n a n a n a n a Size Size Bit 9 Bit 8 REG 05h bits 7 0 REG 06h bits 1 0 S1D13705 X27A A 001 10 Vertical Panel Size Bits 9 0 programmed with a value calculated as follows VerticalPanelSizeRegister VerticalPanelResolution lines 1 This 10 bit register determines the vertical resolution of the panel This register must be 3FFh is the maximum value of this register for a vertical resolution of 1024 lines Hardware Functional Specification Issue Date 02 02 01
472. zontal Non Display Period REG 08h 4 x 8Ts 1D13705 Hardware Functional Specification X27A A 001 10 Issue Date 02 02 01 Epson Research and Development Vancouver Design Center Page 41 Sync Timing A Frame Pulse t 13 gt Line Pulse t5 DRDY MOD Data Timing Line Pulse t6 t8 t9 t7 t14 tt t10 4 gt A 4 Shift Pulse t12 t13 FPDAT 7 0 i gt X Note For this timing diagram Mask FPSHIFT REG 01h bit 3 is set to 1 Figure 7 14 Single Monochrome 8 Bit Panel A C Timing Table 7 12 Single Monochrome 8 Bit Panel A C Timing Symbol Parameter Min Typ Max Units t1 Frame Pulse setup to Line Pulse falling edge note 2 note 1 t2 Frame Pulse hold from Line Pulse falling edge 9 Ts t3 Line Pulse period note 3 t4 Line Pulse pulse width 9 Ts t5 MOD delay from Line Pulse rising edge 1 Ts t6 Shift Pulse falling edge to Line Pulse rising edge note 4 t7 Shift Pulse falling edge to Line Pulse falling edge note 5 t8 Line Pulse falling edge to Shift Pulse falling edge t14 4 Ts t9 Shift Pulse period 8 Ts t10 Shift Pulse pulse width low 4 Ts t11 Shift Pulse pulse width high 4 Ts t12 FPDAT 7 0 setup to Shift Pulse falling edge 4 Ts t13 FPDATT 7 0 hold to Shift Pulse falling edge 4 Ts t14 Line Pulse falling edge to Shift Pulse rising edge 23 Ts 1 Ts pixel clock period 2 tlmin t3min 9Ts 3

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