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1. AT wae 3C0H 3E0H Only 3 words used Set all others to O Broadcast 1553B Look up Table Reserved Broadcast 1553B Mode Commands Look up Table Address Figure 3 2 Remote Terminal Simulation Table 3 5 1 Simulation Type Word Bits 14to0 are for MRT only UM 10974 Rev B BIT 15 BIT 14 BIT 13 BIT 12 BIT 7 BIT 6 BITO other bits Bits 7 and 6 1 RT simulated 1 Reserved 1 Inhibit transmitter 1553B on primary bus 1 Inhibit transmitter 1553B on secondary bus 1 Errors enabled on primary bus status word and data 1 Errors enabled on secondary bus Status word and data 1 Enable global error injection 0 Enable global RT errors defined in the RT simulation table as message per message errors defined in the look up tables 27 3 5 2 Status Word Broadcast and message error bits are dynamically updated Service request bit automatically set by the request files and cleared by the TX vector word mode code command Busy bit can be set by user to disable data transmission 3 5 3 1553B Last Command Word Automatically updated including broadcast so the TX last command mode code is correctly simulated 3 5 4 1553B Bit Word For user purposes NOTES l 1553B Mode Commands TX shutdown and override TX shutdown are fully simulated The status of the transmitters are available to the user in the Base Registers 2 The user can
2. Table 3 4 Instruction Set Background Program 0000H XXXXH XXXX Delay LSB of 10us 0001H PC PC 0002H PC PC 2 0003H PC PC 3 0004H XXXXH XXXX 16 bit signed branch to subroutine 0006H XXXXH XXXX 16 bit signed branch 0007H XXXXH XXXX 16 bit absolute address for jump 0008H Return from subroutine 0009H Return from insertion routine OOOAH Enable program insertion OOOBH Disable program insertion 000CH XXXXH Load loop counter with value XXXX 000DH XXXXH LOOP LOOP 1 If lt gt O branch signed offset XXXX OOOEH XXXXH Initialise frame duration to XXXX LSB 10uS OOOFH Wait for new on board start of frame 0010H End of BC program 0011H XXXXH Set low priority IRQ Push XXXX on LO queue 0012H XXXXH Set high priority IRQ Push XXXX on H1 queue 0013H wait for external Trig LO HI for new frame 0014H XXXXH Send message XXX XH absolute address of MDB 0015H XXXXH Trig out to the XXXXH level e Instructions NOP 1 2 3 e By a NOPx the user can replace one two or three instruction words BSR BRA DNBE e The offset is defined in bytes count always even offset BSR e 15 levels of subroutines available TRGOUT xxxx e Instructions to put TRIGOUT at 0 if xxxx OOOOH or 1 if xxxx OOOIH e On power on the output is on O level per default LOOP xxxx e Load loop counter with value XXXX e Only one level of loop UM 10974 Rev B 21 INITF xxxx XXXX Minor frame duration minor cycle time 10 us f
3. LOOK UP TABLE Reserved MRT Data descriptor Block Address Reserved MRT Data descriptor Block Address Figure 4 2 UM 10974 Rev B 1553B TYPE DATA DESCRIPTOR BLOCK Option mask Header Address Data Word Count Data Status Report Toggle Freq Buffer Addr High Buffer Address Low Link Pointer to another DDB Reserved Reserved Message Interrupt Code Set of Message Number Reserved Reserved Reserved Reserved Data Buffers Simulation and Monitoring 35 These paths use a look up table and data 1553B DATA BUFFERS Time Tag High Time Tag Low Data Data Data Data Data 4 3 1 Look Up Table The sixth word of a message descriptor block points to a double word in the look up table that contains the address of a 1553B data descriptor block An identical architecture is defined in MRT mode but using 1553B subaddresses to point into the look up table Look up Table Address Error Injection Word MRT only 02H DDB Address Extended Subaddress look up table address 4 3 2 Data Descriptor Block A data descriptor block is associated with each data message this 16 word set defines the data buffering and associated queue control information Interrupt selection is defined in the option mask word interrupt on correct or erroneous message or after a set of diffe
4. This register will contain the desired PAGE address for the start of the monitor stack area 06H Finish Page Register FPR This register will contain the desired PAGE address for the end of the monitor stack area This value must be greater than the Start Page Register value 08H Window Word Count Register This register will contain the word number in the specified message on which the window trigger test is to be carried out If this value is zero the test will be carried out on any word within the specified message 0AH Reserved UM 10974 Rev B 52 0CH Hardware Trigger Register D15 Did D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 0 0 0 0 0 0 0 0 0 C T N P P 1 The Monitor will wait for LO HI transition on the TRIG IN input before storing messages and searching for the software trigger condition N 1 The Monitor will wait for a HI LO transition on the TRIG IN input before storing messages and searching for the software trigger condition T 1 The Monitor will generate a gt 1 5uS pulse on the TRIG OUT when the software trigger condition has been detected C 1 The Monitor will generate a gt 1 5uS pulse on the TRIG OUT when the post trigger message count has been reached 6 3 DETAILED TRIGGER DESCRIPTION The Bus Monitor has four triggers that can be set up to trigger on a wide variety of complex conditions Each
5. UM 10974 Rev B 48 6 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION 6 1 INTRODUCTION When acting in BC or MRT mode a comprehensive window monitor facility is provided However the Western Avionics TIB 1553 PMC can also act as a chronological monitor for bus event detection and message recording In this mode the Western Avionics IIB 1553 PMC can be set to trigger on specific events and sequentially record precise time stamped messages on a stack The size and position of this stack can be defined by the user NOTE When the Western Avionics IIB 1553 PMC is in this mode the BC MRT facility is not available All address pointers for the Bus Monitor are 16 bit words defining a PAGE address Each page is 32 bytes Example If a message pointer contains the value 2301H this indicates an absolute address of BASE 2301H x 20H BASE 46020H 62 BASE REGISTERS Table 6 1 Base Registers BASE REGISTER 00H Control Register Write Clock HI Word Read 02H Clock LO Word Read LSB of clock 0 5 uS 04H Command Register CR 06H Status Register SR 08H Reserved to Reserved 2AH Reserved 2CH Reserved 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Reserved 38H Load Clock HI Register 3AH Load Clock LO Register 3CH Reserved 3EH Reserved 40H Reserved 42H Current Address Register CAR 44H Trigger Occurrence Register TOR 46H Trigge
6. WESTERN AVIONICS MIL STD 1553B PMC INTELLIGENT INTERFACE BOARD P N 1U10974G01 Rev A User Manual UM 10974 Rev B Western Avionics Ltd 13 14 Shannon Free Zone Co Clare Ireland 17 July 2000 1 LA Table of Contents GENERAL INFORMATION cccsssssssssssccsssssescsccsscsssccscssecsscssscssscsssessssssscsscenecsneesseesscssesscssscesssssssessesesens 6 1 1 INTRODUCTION E 6 1 2 MANUAL DESCRIPTION cocoa A A eege 6 1 3 CAPABILITIES iii A EO EE HE EE OE cated 6 1 3 1 Generdk EE ee eeh cee ene ee e E ere eee cee 6 1 3 2 Bus Controller BC Features With MRT Simulation and Data Monitoring uie esse es see se ee se ee 7 L33 Multiple Remote Terminal MRT Features 7 1 3 4 Chronological Bus Monitor CM Features cccccccssccessceesseceesceennecesneeeacecseceeesaeceaeeeeaceceeeeeaeeeneeeeaeees 7 1 4 THE ITB 1553 PMC ARCHITECTURE ees ee ee see ee ee se ee ee ee ee ee ee Ge ge ee ee ee ee ee rE ee TE ee ee ee E ee ee ee Ge Re ee ee Eia 8 1 5 PROTOCOL MANAGEMENT UNIT sees esse se ee ee se ees ee ee ee ee ee ee ee Ge Re ee Ee Re ee GR ee ee ER Re ee ee RA ee GR ee ER Re ee ee ee 8 1 6 Jh EN EREM ie aaa 8 17 FEATURES RR EE IR EE EE EE AE EE ER EE GE 9 1 8 SYSTEM CHARACTERISTICS AND SPECIFICATIONS ee see ees se ee ee ee ee ee ee ee ee ee ee ee see ee ee ee ee ee ee ee ee ee ee ee 9 1 9 LIST OF RURNISHPIDTITEMS ee ee ee se ee ee ee se ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee nn ee ee ee ee
7. DO7 DO6 DOS D04 D03 D02 DO1 DOO ED 0 0 Py Mn Lg Sh Tl TO WC B1 BO NR TA Sy O ED 1 Indicates last 1553B word in message Py 1553B data word had a Parity error Mn 1 1553B data word had a Manchester error Lg 1 1553B data word had too many bits Long Sh 1 1553B data word had too few bits Short UM 10974 Rev B 63 T1 TO describe the 1553B word type as follows T1 TO WORD TYPE 0 0 Command Word 0 1 Status Word 1 0 Data Word 1 1 RT RT Command Word WC 1 Indicates 1553B message had a word count error Only set for last word Bl BO Describe the bus the 1553B word was captured on as follows Bl BO BUS ID 0 0 Illegal 0 1 Secondary 1 0 Primary 1 1 Both Buses NR 1 Indicates that an RT failed to respond to a command No Response Only set for last word TA 1 Indicates that the RT status word did not match the address of the command word Terminal Address Error Sy 1 Indicates that the 1553B word did not have the correct SYNC type 6 4 4 Next Address Pointer This word will define the page address of the next message This value will be set to FFFFH for the last message after the post trigger count has expired and capturing has stopped 6 4 5 RT Response Time 1 2 These two locations will define the RT response times if any of the Status words in the message The s
8. 0800H DDB address On data messages with error OCOOH DDB address On mode commands without error 0900H DDB address On mode commands with error ODOOH DDB address 5 6 2 Message Interrupts or set of messages interrupt One word code equals message interrupt code in data descriptor block The code is pushed in queue only if the message is correct Sets of Messages Same feature as for BC mode 5 6 3 Status Report Queue two words per report Code pushed into queue only if error on message and Interrupt on erroneous message not set in the DDB Ist Word Pointer to the double word in look up table look up table address index 2nd Word Events BIT 15 Wrong Both Buses Error IT14 No Response Error IT13 RT Address Error IT12 TX Error Mn Lg Sh Py WC Late Response BIT 11 SYNC Type Error BIT 10 to 0 Not Used 5 7 SPECIFIC FUNCTIONS 5 71 Data Message Reception Each data message not transmitted by the Western Avionics ITB 1553 PMC board may be stored The path to access the data buffer is given by the RT look up table for messages BC lt gt RT Except for RT gt RT messages even if the RTs are simulated or not the path to point to the data buffer is always given by the transmitting RT look up table but the receiving RT look up table must point to a false DDB Received status words from RTs not simulated on board are stored in the associated disabled RT SIM table If an external RT fails to respond a value of F
9. 1 Error condition disabled Trigger Data 2 Error Word Register Base Address 46H This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 Py Mn Lg Sh O 0 WC 0 0 NR TA Sy O Sy 1 Sync Type Error Sh 1 Short Word Error TA 2f Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error UM 10974 Rev B 57 Trigger Data 3 Trigger Data 3 Bit Mask Register Base Address 48H This register will define the bits to be ignored in the trigger bit pattern for trigger data 3 Any bit set in this register will be masked from the trigger test condition Trigger Data 3 Bit Pattern Register Base Address 4AH This register will define the bit pattern required for trigger data 3 Trigger Data 3 Bus ID Word Type Mask Base Address 4CH This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 DO3 D02 DO1 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 3 Bus ID Word Type R
10. 45 D01 X D00 X 5 5 2 Message Error Injection Word Look up Table The following word defines the errors that can be injected into the message D15 DI4 D13 D12 DII DIO DO9 DOS D07 D06 DOS DO4 D03 D02 DOI DOO T T T X X X X X X X X X 0 X X X TTT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error O status word 1 1 data word Y Y Y Y Y Y Y ERROR TYPE 0 0 0 0 0 0 0 Parity error O S5 S4 S3 S2 SI SO Synchro Pattern Error 1 0 B4 B3 B2 Bl BO Manchester Bit Error 1 1 LA L3 L2 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX OOOOOOOORRRRR RRRR Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 TTT 101 gt Illegal Command XXXXXXXXXXXXX 0000000000000 TTT 110 gt Extended Subaddress XXXXXXXXXXXXX 0000000000000 TTT 111 gt Resync System Clock XXXXXXXXXXXXX 0000000000000 NOTE For NO ERROR set TTT 000 and WWWWWW 111111 UM 10974 Rev B 46 5 6 INTERRUPTS CODING 5 61 Low and High Priority Interrupts two word code On data messages without error
11. CO to 1 See Command Register below Synchronise Clock If the above procedure is carried out using the synchronise clock command 0010H the contents of LOAD Clock HI will be added to the current clock value as a 32 bit signal offset UM 10974 Rev B 18 3 4 2 3 Command Register CR 04H Prior to clearing the command request bit CO in the control register the user must first test that the command register is clear When the command register is clear the user can insert the next command to be executed After the command is loaded bit CO in the control register can be cleared When the command register clears the board is ready for a new command Refer to table 3 2 Table 3 2 Command Register CR CODE COMMAND 0000H Illegal 0001H GO TO BC MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H BC COLD Start 0005H BC WARM Start 0006H BC STOP 0007H MRT COLD Start 0008H MRT WARM Start 0009H MRT STOP OOOAH PAUSE OOOBH UNPAUSE 000CH LOAD CLOCK 000DH SELFTEST OOOEH RUN MONITOR OOOFH STOP MONITOR 0010H Synchronise CLOCK UM 10974 Rev B 19 3 4 2 4 Status Register SR 06H The status register will contain a word reflecting the status of the board as shown in table 3 3 Table 3 3 Status Register CODE STATUS 0001H BC IDLE 0002H MRT IDLE 0003H MON IDLE 0004H BC RUNNING 0005H BC INSERTION RUNNING 8004H BC
12. ORGANISATION DIAGRAM The organisation diagram figure 3 1 shows how the functional areas of the Western Avionics ITB 1553 PMC board can be controlled 3 4 BASE REGISTERS The only fixed position registers are the Base Registers The Base Registers are the starting points for a description of operation of any of the three modes of operation BC MRT and CM They are located starting at the board Base Address UM 10974 Rev B 15 BC MRT 1553B LUT Reserved MRT Pa y DDB Address DDB DATA BUFFERS Time Tag HI Time Tag LO Data Options mask Data buffer Address HI Data buffer Address LO a BC O MRT Dl Background Program Block A Message Number rea Ni 1 1 eM 7 Address in LUT BASE REGISTER A BRP IRP N A Queues Address A Insertion Program RTSTAD 1553 LUT RT Simulation Table Error Injection E I553BLUT LW E Word gt Address DDB Address Low High Priority Priority Interrupt Interrupt RTI RT1 A E RT30 Message Message RT30 Interrupt Status Report Figure 3 1 Organisation Diagram UM 10974 Rev B 16 DDB Options mask Data buffer Address HI Data buffer Address LO DATA BUFFERS Time Tag HI Time Tag LO
13. PAUSED Background 8005H BC PAUSED Insertion 9004H EXECUTING SOFTWARE PAUSE SWPSE A004H EXECUTING HARDWARE PAUSE HWPSE 0006H MRT RUNNING 8006H MRT PAUSED 0007H MON RUNNING 0008H MON RUNNING XXX8H EXECUTING SELFTEST FINISHED SELFTEST The status register will contain the following information after completion of self test D15 D14 D13 D12 Dil D10 D09 DOS D07 DO6 DOS D04 DO3 D02 DO DOO 1 0 0 LS 0 0 LC M5 M4 M3 M2 MI 1 0 0 0 LS 1 1553B Interface Test Failed LC 1 Local Clock Test Failed M5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed Mi 1 Memory Test 1 Failed Several bits can be set simultaneously If no self test errors are detected the code in the status register will be 8008H UM 10974 Rev B 20 3 4 2 5 Background Running Pointer BRP 08H In the BC mode the Background Running Pointer BRP directs the firmware to the location of a background program which can be used to organise the message sequencing Before sending a BC start the user must initialise the BRP BRP is updated by the on board processor after executing a BC STOP command Table 3 4 is a list of the possible instructions with descriptions and examples DELAY NOPI NOP2 NOP3 BSR BRA JMP RTS RTI ENI DSI LOOP DBNE INITF SWPSE HALT SITL SITH HWPSE SMB TRGOUT
14. Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 1 Error Word Mask Register Base Address 38H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 DIO D09 DOS D07 DO6 DOS D04 D03 D02 DOL DOO 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 1 Error Word Register Base Address 3AH This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 Did D13 D12 D11 DIO DO9 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 Py Mn Lg Sh vu 0 WC O 0 NR TA Sy O Sy 1 Sync Type Error Sh 1 Short Word Error TA EN Terminal Address Error Lg Long Word Error NR No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error UM 10974 Rev B 56 Trigger Data 2 Trigger Data 2 Bit Mask Register Base Address 3CH This register will define the bits to be ignored in the trigger bit pattern for trigger data 2 Any bit set in this register will be masked from the trigger test condition Trigger Data 2 Bit Pattern Reg
15. UM 10974 Rev B Capture of all bus activity in chronological stack with time tagging of each message Comprehensive multi trigger facilities allowing selective capture and interrupts to be performed on complex data sequence Cyclical stack up to 2Mbyte with interrupt on completion of capture All 1553B errors detected 1 4 The ITB 1553 PMC ARCHITECTURE The Western Avionics IIB 1553 PMC board is a memory mapped PMC MIL STD 1553B interface with high performance architecture and complex features Plugged into a 3 3V or 5V PMC universal the PMC IIB 1553 PMC card provides enhanced test and simulation functions for all modes of operation of a MIL STD 1553B bus The host equipment using the on board RAM defines all configuration and data structures Protocol 1553B UNIVERSAL Management Pa INTERFACE 1553B Lines in out INTERFACE Unit INTERRUPT Figure 1 1 TIB 1553 PMC Functional Block Diagram 15 PROTOCOL MANAGEMENT UNIT A micro controller based structure running at 40Mhz handles the management of the 1553B protocol for each of the operating modes BC MRT BM The micro controller works each of the 1553B command status and data words functions of its operating mode and the configuration tables in RAM The micro controller management unit allows flexibility and expandability for the bus control tasks and user interface 1 6 1553B INTERFACE The 1553B interface is a dual redundant interface which includes a standard dual redu
16. modify the RTs simulation state in real time UM 10974 Rev B 28 4 BUS CONTROLLER MODE OF OPERATION 4 1 INTRODUCTION In the Bus Controller mode the Western Avionics 1IB 1553 PMC board runs a list of instruction pointed to by the Background Running Pointer defining the bus frame Each bus message is defined by a Message Descriptor Block MDD and the associated data is accessed through a Look Up Table LUT and Data Descriptor Blocks DDB the same way as in the Multi Remote mode Remote Terminals can simultaneously be simulated All non simulated data buffers can be monitored An internal minor frame duration counter allows autonomous control of cycling frames Acrylic messages can be inserted on the host request Insertion instruction lists define sequences of messages to be inserted Refer to figure 4 1 the Bus Controller Organisation Diagram BASE REGISTER Message Descriptor Block Message Number Background Program T E BRP we Area By TRP a e Address in LUT ED To LUT e TT D aung Af 2 b SMB V A Insertion Program Queues Address RTSTAD Po RT Simulation es Table ah DATA RTO BUFFERS RTI Time Tag HI DDB tions mask j S High RT30 Data buffer Address HI Data buffer Address LO Low Priority Priority Interrupt ES m Address from MDB Message Status Report Lee
17. 1553B ERROR INJECTION DEFINITION Error injection on status word and 1553B data words transmitted can be defined message by message using the message error descriptor word in the look up table or globally for all messages transmitted by an RT using global RT error injection word in each RT simulation table UM 10974 Rev B 44 5 5 1 Global RT Error Description Word RT Simulation Table The following word defines the errors that can be injected into the message D15 DI4 D13 D12 DI1 DIO DO9 DOS D07 D06 DOS DO4 D03 D02 T T T X X X X X X X X X X X TTT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWWWWW Word Number For Modulation Error Y Y 0 0 0 SS 1 0 1 1 Y Y Y Y Y ERROR TYPE 0 0 0 00 Parity error S4 S3 S2 Sl SO Synchro Pattern Error B4 B3 B2 B1 BO Manchester Bit Error LA L3 12 L1 LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P 2 3 Word Count Error Polarity Word Count Error VE Word Count Error VE CCCCCC Word Count Error Value Allows 64 Words TTT 100 gt Response Time Error XXXXXXXXXXXXX 00000000RRRRR RRRR NOTE UM 10974 Rev B Unique Response Time for simulated RT in uS See NOTE 4 in paragraph 5 5 2 Global error injection is enabled disabled by the LSB bit of the simulation type word
18. 4 Ground 15 PRI Primary 1553 negative 16 Ground 17 SEC Secondary 1553 negative 18 Ground 19 TOUTE Trigger Out Emitter 20 Ground 21 Ground 22 Ground 23 TINK Trigger In Cathode 24 Ground 25 N C Not connected 26 N C Not connected DI CU aaqaa qaaaananana ee aa A PCB Figure 2 2 IIB 1553 PMC Front Panel UM 10974 Rev B 14 3 OPERATION 31 INTRODUCTION The Western Avionics ITB 1553 PMC Intelligent Interface Board provides Bus Controller BC Multi Remote Terminal MRT functions which may be run either independently or simultaneously An independent Chronological Bus Monitor CM is also provided In order to run any of these functions information must be loaded into specific fixed register locations Base Registers Some of these registers contain pointers to other areas of memory registers The selection of these pointers is left up to the discretion of the user Therefore memory blocks can be positioned in the on board memory to suit user requirements This set up means that fixed position registers are minimal 32 CONVENTIONS 1 BASE PMC Base Address of this board 2 The memory range BASE IOOOOH to End of Memory is reserved for the 1553B data blocks All other data must reside in the first 64Kbytes After a Power On On board processor doing its power on initialisation Then executing Self Test Then waiting for a user command DSI per default insertion program is disabled 33
19. 53 PMC board can simulate up to 31 RTs After initialisation by the host the board is ready to listen to the bus activity and to respond to command words for the simulated RTs mode providing the same associated features multiple data buffering signalisation etc Multiple Remote Terminal Organisation Diagram The specifics of the MRT mode of operation mainly concern the following e The logical path to point into the look up tables e The errors injection capabilities RTO 1553B LUT DDB Illegalization Word Options mask DDB Address Data buffer Address HI TX Data buffer Address LO BASE REGISTER RT Simulation Table RTO BRP RTI IRP Queues Address RT30 RTSTAD RT31 Broadcast Low High Priority Priority Interrupt Interrupt Message Message Interrupt Status Report Figure 5 1 UM 10974 Rev B RTO 1553B Mode Code LUT Illegalization Word DDB Address TX DDB Options mask Data buffer Address Multiple Remote Terminal Organisation Diagram 43 The description of the mode of operation uses tables similar to those defining the bus controller Refer to figure 5 1 the DATA BUFFERS Time Tag HI Time Tag LO Data DATA BUFFERS Time Tag HI Time Tag LO Data 52 LOOK UP TABLES For each RT the Western Avionics I
20. Data 3 4 1 Base Register Names and Locations The names and locations of the Base Registers are contained in table 3 1 UM 10974 Rev B Table 3 1 Base Register Names and Locations BASE Control Register Write Clock HI Word Read 02H Clock LO Word Read only 04H Command Register CR 06H Status Register SR 08H Background Running Pointer BRP Address of Program 0AH Insertion Running Pointer IRP Address of Program 0CH Reserved 0EH Low Priority Interrupt Queue Start Address Pointer 10H Reserved 12H High Priority Interrupt Queue Start Address Pointer 14H Reserved 16H Message Interrupt Queue Start Address Pointer 18H Reserved HAH Status Report Oueue Start Address Pointer 1CH Reserved EH RT Simulation Table Address Register RTSTAD 20H Amplitude Register 22H Coupling Register 24H Toggle Buffer Address Offset MSB 1 Global Enable 26H SET OF MESSAGES Start Address 28H Global RT Response Time Register us 2AH RT No Response Timeout Register us 2CH Reserved 2EH Reserved 30H Reserved 32H Reserved 34H IRQ Selection Register 36H Minor Frame Counter Register 38H Load Clock HI Register 3AH Load Clock LO Register 3CH Test and Set register TASR 3EH Service Request Queue Address Pointer SRQADSP 40H Cycling Interrupt Update Register 42H Monitor Current Address
21. FFFH will be stored in the SIM table 5 72 Reception of Mode Commands Data Words For each mode command with data word message if the data word is not transmitted by the board it must be stored RT simulated or not The path for storing the data word is given by the RT mode command look up table UM 10974 Rev B 47 5 7 3 Mode Command Synchronise with Data Word When receiving a broadcast mode command Synchronise with Data word the on board processor e Stores the data word value in the Cycling Interrupt Update Register in base registers and set the cycling IRQ e Accesses to a DDB to store the data word in a buffer and time tag the data buffer e Uses the value of the data word which is for example the minor cycle number 0 to 7 to manage frequency toggling of the data buffers 5 7 4 Frequency Toggle The frequency toggle option works in the same manner as the BC mode except that the minor cycle number is given by the data word associated to the mode command synchronise with data word This mode command is due to circulate on the bus at the beginning of each minor cycle and toggles bank A or B are managed when this message occurs Minor Cycle 0 1 2 3 4 5 6 7 8 19 A B JC frequency F F Hz A B A B A B A B A BB A IB JIA F 2 Hz A A B B A A B IB IB JA IB B A F 4 Hz A JA JA JA IB IB B B JAJAJA A B F 8 Hz A JA JA JA JA JA A A IB B B IB B
22. Ge Re ee ee Re ee ee ee ee ee Re ee ee 10 1 10 LIST OF RELATED PUBLICATIONS sees se se ee esse ee ee ee se ee ee ee ee ee ee se Ee dee ee ee ee E R Ee ee Ee Gee E EEE SR Re ee 10 111 STORAGE DATA see DE ee se GE Ee SE od ieee 10 1 12 TOOLS AND TEST EQUIPMENT ees se ee ee ee se ee ee see ee ee ee ee ee ee ee ee ee ee ee ee ee Re ee ee ee ee GR Re ee ee r En Ge ee ee RR Re ee ee 10 1 13 SAFETY PRECAUTIONS ees ee ee ee se ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee ee Re ee Ge Re ee ee Re ee ee ee Re ee GR Re ee ER Re ee ee ee ee ee Re ee ee 10 INSTALLATION AND PREPARATION FOR USE esse esse esse ese ese see see see es Ge ee Ge se ee bee bee bee Se ee ee Ge ee 11 2 1 GENERAL EE a E RE EE De ce 11 2 2 INSTALLATION OF THE IIB 1553 PMC ese ese se ee ee se ee ee ee se ee ee ee ee ee ee ee ee Ge ee ee ee Ge Re ee ee Re ee ee ee ee ee Re ee ee 11 23 TURN ON Sia 11 2 4 RESE EE EE EE OE EE OE EE OE EE EE we RA LA EE 11 2 5 SPECIFIC EEATURES cc ER IE EE RE N OE N ER N N 12 2 5 1 Control Register Feature iia AAR EE EA 12 2 5 2 Counter Features ida 12 23 3 Trig er IN Features RE ER a a Ed EE a a a a isai 12 2 5 4 Trigger Out FCOMTES A EE N OE OE 12 2 6 PMC INTERFACE AAA 13 2 6 1 IntroduchO A 13 2 6 2 EG ENG Pi es ik SE ER OE RE MO ME N EE EE 13 2 6 3 OER EE EE EE EE EE N 13 2 7 1553B OH do OER N EE EE OE 13 2 7 1 A E TE E EN ee AS 13 2 7 2 AE AS Pi sk SE ai cs 13 2 8 1593 PMC CONNECTOR EA EE EE EE EE asais Saa 14 2 8 1 JT Conn
23. IT 13 BIT 12 BIT 11 to 8 BIT 07 BIT 06 BIT 05 BIT 04 BIT 03 BIT 02 BIT 01 BIT 00 NOTES UM 10974 Rev B CO E CO ORR Re Extended Subaddress Retry on EVENT Interrupt on EVENT enabled Interrupt on EVENT HI priority queue 0 LO priority 1 1553B TX on PRI bus 1 1553B TX on SEC bus 0 0 11 10 09 08 0 0 0 0 1553B MODE WITHOUT DATA 0 0 0 1 1553B MODE WITH DATA 0 0 1 0 1553B RT RT 0 0 1 1 1553B BC RT RT BC 0 1 0 0 Reserved 0 1 0 1 Reserved 0 1 1 0 Reserved 0 1 1 1 Reserved 0 0 0 0 1553B MODE WITHOUT DATA BROADCAST 1 0 0 1 1553B MODE WITH DATA BROADCAST 1 0 1 0 1553B RT RT BROADCAST 1 0 1 1 1553B BC RT BROADCAST 1 1 0 0 Reserved BROADCAST 1 1 0 1 RECEIVE CLOCK BROADCAST 1 1 1 0 Reserved BROADCAST 1 1 1 1 Reserved BROADCAST If RETRY is enabled and IRQ on EVENT is disabled the RETRY will still take place Broadcast Receive Clock is a special message used for transmitting the 32 bit clock as data This message type only requires an MBD to define the command word and the inter message gap No queue interrupt or buffer control is carried out The transmitted message will be the command word defined by the MDB followed by two data words Clock Value HI and Clock Value LO clock value at the end message on the bus The transmission of a Broadcast Synchronise with Data mode code using the 1553B mode with data broadcast message type will cause cycling interrupt to be generated if ena
24. Look Up Table UA 33 4 2 7 Command Word 1 OCH sssrinin EE SE Ge Re EE DEE EE GEE bee a Ek ende Gede GE Nee Gee 33 4 2 8 Command Word 2 VEN ata SN 33 4 2 9 Retry Subroutine Absolute Address IA4H iese es se ee SR ee ER Re GR ee ER Re ee ee Re ee GR ee ee ER Re ee ee ee Re ee 33 CERN 34 Aai Status Word LUCI A aio 34 42 12 Status BASE EE NE RE dae 34 4 3 DATA BUFFERS SIMULATION AND MONITORING AAA 35 4 3 1 ET abt KEER EE EE ER EE N 4 3 2 Data Descriptor AE A A Ar 4 3 2 1 Option Mask OOH N RE EA EE OE RO EEEN 4 3 2 2 Data Status Report 06H vo 4 3 2 3 Toggle Frequency and Buffer Address HI OH 4324 Link Pointer to New DDB OCH 4 3 2 5 Address of Modify Word Value to Write OEH 10H dog 4 32 6 Extended Sub Address ucraniana doe FR ees dae see Gee ERG GE be ue 4 3 3 Data MOORE EE EE EE ER EE EE EE ee 4 4 le BAG ESE IR KERE EE OE ET EE EE EE EE EE OK 4 5 INTERRUPT dele ONSE EE N N NE OR EE N EO OE OG 4 5 1 Interrupt CODING ME EE EA EE OE EO EE 4 5 2 Set Message Interrupts EE EE Eee 4 5 3 Message Status Report Queue iii ii di idea died UM 10974 Rev B 3 5 MULTIPLE REMOTE TERMINAL MODE OF OPERATION sees se ese se esse sees se ese se ees se ese sees se sees se es ee se es 43 5 1 INTRODUCTION BE 43 2 LOOK UP TABLES oo alii 44 5 3 MODE COMMANDS SPECIFICATIONS ee see se see ee ee ee se ee ee ee ee ee ee se ee se non ee E Re cone Gee ee Re Ge Re ee ee 44 34 DATA WORDS STORAGE boccsscsseesccesciiasseneasesvensboissncoeva
25. MRT Figure 4 1 Bus Controller Organisation Diagram UM 10974 Rev B 29 4 2 MESSAGE DESCRIPTOR BLOCK MDB Each bus message is defined by a message descriptor block as shown in table 4 1 Table 4 1 Message Descriptor Block MBD ADDRESS MESSAGE NUMBER 02H 1553B Event Mask 04H Message Type Word 06H 1553B Message Error Phase Definition 08H 1553B Message Error Description Word 0AH Address in Look up Table 0CH Command Word 1 0EH Command Word 2 10H Reserved 12H Reserved 14H Retry Subroutine Absolute Address 16H Reserved 18H Inter message Gap Time 1AH Reserved 1CH Status Word 1 received 1EH Status Word 2 for RT RT received 421 Message Number 00H The number of the message is used in Message Status Report to identify messages 42 2 1553B Event Mask 02H A logical AND is carried out with the 1553B event mask and the detected bus events If the result is lt gt 0 a message status report will occur and a retry if selected BIT 15 Wrong Both bus error BIT 14 No response error BIT 13 RT address error BIT 12 Transmission error BIT 11 f Wrong sync error Bit 10 to 00 Status bits of RX status word not including address bits NOTE Transmission error includes Manchester error Long or Short word error Parity error Word Count error and Late Response error UM 10974 Rev B 30 42 3 Message Type Word 04H BIT 15 BIT 14 B
26. RE 23 3 4 2 18 Reserved O2H wi 23 3 4 2 19 Toggle Buffer Address Offset 24H 3 4 2 20 Set of Messages Start Address 26H 3 4 2 21 Global RT Response Time Register 28H oonnoncnnccncnocinononcnnnononnnanonnononacon ee corn conc Ge ee 3 4 2 22 RT No Response Time Out Register OAH iese sesse see se ee ke Ge Ge ee ee ee Re Re Ge we 24 3 4 2 23 IRQ Selection Register 34H scscssscsssssssersssscesssssssnsesscenseeesenscesceatseesensseecerscenessesentenses 25 3 4 2 24 Test and Set Register and SRQADP 3CH 10 29 3 4 2 25 Reserved 40M OR OR EE N N EE EE E OE 26 3 4 2 26 PRI SEC 1553B RT TX Inhibit HI LO 48H AED 26 3 5 REMOTE TERMINAL SIMULATION TABLE esse ese ee se se esse ee ee se ee se ee ee ee ee se ee ee ge ee se ee ee ee ee ee ee ge ee ee ee 27 3 5 1 Simulation Type Word cid OE EE iia HE N 27 3 3 2 Stats WOT N RR E AE A E 28 3 3 3 1553B Last Command Mord 28 3 5 4 TDI SB Bil WOTA RE EE RE 28 4 BUS CONTROLLER MODE OF OPERATION esse esse esse sesse esse ss ee sees ee see bee bee se Ge sede bede bee Ge bee Bee See ee ee 29 4 1 INTRODUCTION 2 lie 29 4 2 MESSAGE DESCRIPTOR BLOCK MIDD 30 4 2 1 Message Number 00H voii ita 30 4 2 2 1553B III AAA A 30 4 2 3 Message Type Word 04H ici ad a a e 31 4 2 4 1553B Message Error Phase Definition Oo 32 4 2 5 1553B Message Error Description Word O8H ees ees ees see se ee se ee se ee ee nono cnn Se AG Ge oran cnn cnn ee 32 4 2 6 Address in
27. Register CAR 44H Monitor Trigger Occurrence Register TOR 46H Monitor Trigger Set up Pointer TSP 48H PRI Bus 1553B RT TX inhibit bits HI 4AH PRI Bus 1553B RT TX inhibit bits LO 4CH SEC Bus 1553B RT TX inhibit bits HI 4EH SEC Bus 1553B RT TX inhibit bits LO 50H Reserved 52H Reserved 54H Reserved 56H Reserved 17 3 4 2 Base Register Descriptions The Base Register functions are defined in the following paragraphs 3421 Control Register Write 00H DIS DI4 D13 D12 DI1l D10 D09 DOS DO7 D06 DOS D04 D03 D02 DO DOO 0 0 0 0 0 0 0 HR 0 IEN IRQ 0 0 0 Cl CO CO Clear gt Command Request Cl Clear gt Insertion Request HR Clear gt Hardware RESET If IEN is set and IRQ is set then interrupt line will be cleared If IEN is set and IRQ is clear then the interrupt line will be asserted for test purposes only If TEN is clear the value of IRQ is unaffected Note This register must be accessed to clear the interrupt during an interrupt service routine Examples 1 0102H generates a command request 2 0163H clears the interrupt line 3422 Clock HI Word Read 00H Clock LO Word Read 02H e Local Clock Reading CK HI LO Read as a 32 bit word Update Local Clock by the User Write the new value in the registers LOAD Clock HI LO Registers Write the LOAD CK code 000CH in the command register Write CO 0 in the control register After executing the command the on board processor sets
28. TB 1553 PMC board manages three different look up tables the address of these tables are obtained from the RT simulation tables These tables are as follows e 1553B Look up Table giving a descriptor for each 1553B sub address e 1553B Mode Command Look up Table giving a descriptor for each 1553B mode code NOTE The T R bit of the Command word or Action word is used as an offset to point to the RX or TX block of the look up tables Each descriptor includes e A Message Error Description or Illegalization word e A Data Descriptor Block Address or Extended sub address look up table address as for BC mode 53 MODE COMMANDS SPECIFICATIONS All illegal mode codes defined in the 1553B standard are automatically illegalized The error descriptor word allows illegalization of complementary mode codes Associated data words which are not obtained from the RT Simulation Tables can be obtained from or stored in memory using Data Descriptor Blocks For each mode code DDB can be used to define IRQ s 54 DATA WORDS STORAGE To avoid data buffers overwriting in memory when receiving a data message the IIB 1553 PMC board does not store more data words than the number defined by Data Word Count 1 if no header option or Data Word Count Header Word Count 1 if header option Data Word Count is defined in the DDB The extra word for 1553B messages will be the last received word of a message in excess of the DDB data word count 5 5
29. Word 2 0EH Second Command Word RT RT 1553B 4 2 9 Retry Subroutine Absolute Address 14H On completion of a message if an Event defined by the Mask has occurred and the Retry Event is enabled the Subroutine defined by this absolute address will be called NOTES 1 The retry subroutine must be terminated by the RTS instruction to return execution back to the main background or insertion program 2 This feature can be used for immediate insertion of Acyclic messages or retry of the same message on the alternate bus UM 10974 Rev B 33 4 2 10 Inter message Gap Time 18H e Gap between the end of this message and the 1553B line and the beginning of the next one next MDB e LSB 0 l uS 4 2 11 Status Word 1 ICH First RX Status Word in the message If the BC detects no response error this value will be updated with FFFFH 4 2 12 Status Word 2 IEH Second RX Status Word in the message RT RT If the BC detects a no response error from the second RT this value will be updated with FFFFH UM 10974 Rev B 34 43 DATA BUFFERS SIMULATION AND MONITORING The Western Avionics IIB 1553 PMC board processes all the data buffers running on the 1553B lines Data buffers to be issued by the BC or the simulated RTs are transmitted by the Western Avionics ITB 1553 PMC board all others can be monitored A multiple data buffering structure is implemented descriptor block Refer to figure 4 2 Data Buffers Simulation and Monitoring
30. Words TTT 100 gt Response Time Error XXXXXXXXXXXXX OOOOOOOORRRRR RRRR Unique Response Time for simulated RT in uS TTT 101 gt Illegal Command Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 TTT 110 gt Extended Subaddress Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 TTT 111 gt Resync System Clock Not applicable for BC Mode XXXXXXXXXXXXX 0000000000000 UM 10974 Rev B 32 NOTES 1 Word Number For the first word of the message command or status WWWWWW 000000 2 Synchro Pattern Error Defines a specific synchro bit each Si defines the level for 500ns duration at least 1 bit of S5 SO must be set S5 S4 KE KR Sl SO right synchro bit example false synchro bit example S5 SO 011001 3 Manchester Bit Error B4 BO defines the bit position in the word for the error 4 Word Length Error L4 LO defines the number of bits in the word NOTE This count has an offset of 1 such that a value of 01111 will result on a valid word with a data bit count of 16 e Wrong bus error f RT response on the wrong bus e Both busses error RT response on both busses e Response time error i RRRRR replaces the global RT response time LSB 1 uS e Illegal command Reserved for MRT only 4 2 6 Address in Look Up Table OAH This will contain the address in the look up table for the DDB pointer See figure 4 1 42 7 Command Word 1 0CH First Command Word 4 2 8 Command
31. a new command UM 10974 Rev B 50 6 2 3 Status Register SR This register contains a code reflecting the status of the board as shown in table 6 3 Table 6 3 Status Registers CODE COMMAND 0001H Reserved 0002H Reserved 0003H MONITOR IDLE 0004H Reserved 0005H Reserved 0006H Reserved 0007H MONITOR RUNNING 0008H Reserved The Status Register will contain the following information after completion of selftest D15 D14 D13 D12 D11 D10 D09 DOS DO7 DO6 DOS DO4 DO3 D02 DO1 DOO 1 0 0 ES 0 0 LC M M4 M3 M2 MI I 0 0 0 LS 1 1553B Interface Test Failed FR 1 Frame Counter Test Failed LC 1 Local Clock Test Failed M5 1 Memory Test 5 Failed M4 1 Memory Test 4 Failed M3 1 Memory Test 3 Failed M2 1 Memory Test 2 Failed MI 1 Memory Test 1 Failed If no selftest errors are detected the Status Register will be 8008H 6 2 4 IRQ Selection Register 34H DIS DI4 DI3 Di2 D11 D10 D09 D0O8 D07 D06 DOS DO4 DO3 D02 DOI DOO 0 0 0 0 Trigger Post Trigger Full Stack Half Stack 0 0 T 0 0 P 0 0 F 0 0 H T If set a physical INTA interrupt will be generated when the trigger condition is met P If set a physical INTA interrupt will be generated when all the post trigger data is captured F If set a physical INTA interrupt will be generated when the stack is full H If set a physical INTA interrupt
32. ata Message 2 Header Message 1 Header Word Data Message 1 Time Tag High Time Tag Low Data Data Data Buffer Address Data Data UM 10974 Rev B 39 DB ADDRESS 1553B BUFFER 00H Time Tag HI 02H Time Tag LO 04H Data 06H Data 08H Data 0AH Data 0CH i with or without Header Word Table 4 3 Data Buffers 44 MODE COMMANDS In Bus Controller mode the Western Avionics ITB 1553 PMC board can transmit all mode command messages For each mode command message data descriptor blocks pointed through the look up table allow the definition of interrupt requests or associated data word address storage If such a command is directed to an on board simulated RT the corresponding actions are made on the RT simulation table e Transmit RT status word last command word bit word e Inhibit or override inhibit Examples a Synchronise with Data Word The data is obtained from the data buffer pointed by the DDB b Transmit Last Command H A DDB is analysed the data word transmitted is stored in the data buffer If the RT is simulated the last command word from the RT simulation table 1s transmitted c Transmit Bit Word Similar to transmit last command d Transmit Vector Word Similar the transmit last command and then if the RT is simulated the service request bit in the RT status word is
33. bled and the associated data word defined in the data buffer will be stored in the cycling interrupt base register 40H 31 4 2 4 1553B Message Error Phase Definition 06H The following word defines the location of errors that can be injected into the 1553B message D15 DI4 D13 D12 DII DIO DO9 DOS D07 D06 DOS DO4 D03 D02 DO DOO 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X XXX 000 gt Error Injection Disabled XXX 001 gt Inject Error in 1st BC TX Initial BC message XXX 011 gt Inject Error in 1st RT SIM lst RT response XXX 100 gt Inject Error on 2nd RT SIM 2nd RT RT response 4 2 5 1553B Message Error Description Word 08H The following word defines the errors that can be injected into the 1553B message D15 DI4 D13 D12 DII DIO DO9 DOS D07 D06 DOS D04 DO3 D02 DO DOO T T T X X X X X X X X X X X X X TTT 000 gt Modulation Error XXXXXXXXXXXXX WWWWWWYYYYYYY WWW WWW Word Number For Modulation Error Y Y Y Y Y Y Y ERROR TYPE 0 0 0 0 0 0 0 Parity error 0 1 1 S5 S4 S3 S2 Sl SO Synchro Pattern Error O B4 B3 B2 Bl BO Manchester Bit Error 1 14 L3 12 LI LO Word Length Error TTT 001 gt Wrong Bus Error XXXXXXXXXXXXX 0000000000000 TTT 010 gt Both Bus Error XXXXXXXXXXXXX 0000000000000 TTT 011 gt Word Count Error XXXXXXXXXXXXX 000000PCCCCCC P Word Count Error Polarity 0 Word Count Error VE 1 Word Count Error VE CCCCCC Word Count Error Value Allows 64
34. cator gt 000 FHz 001 F 2Hz 011 F 4Hz 111 F 8Hz Buffer Address Hl 37 When global toggle is enabled for a data buffer 1f the toggle feature is selected bit 15 1 the address of the toggle buffer is Buffer Address High Toggle Buffer Offset 15 bits Buffer Address Low DDB Buffer Bank A bitl5 1 Buffer Address Offset Buffer Bank B The toggle is synchronised on the minor frame counter register which is incremented on each minor cycle restart The on board processor stores the data buffer in bank A or B depending on the number of the running minor cycle and the frequency indicator of the message Minor Cycle 0 1 2 3 4 5 6 7 18 9 A B JC frequency F F Hz A B IA B IA VB JA IB JA BB A B JIA F 2 Hz A JA IB B JAJA B IB IB JA IB B JA F 4 Hz A JA JA JA IB IB B B A A JA A B F 8 Hz A JA JA A JA JA A A B B B IB B 4 3 2 4 Link Pointer to New DDB 0CH If the message is good or bit 10 of the option mask is clear and bit 9 of the option mask is set the value in this location will replace the original DDB address in the look up table This feature defines a different DDB for the next occurrence of the same message 4 3 2 5 Address of Modify Word Value to Write 0EH 10H After the message is complete and bit 8 of the option mask is set the Value to Write is written in t
35. ceysbensntebieusneas EEND AA De ENEE Reg deed ED 44 5 5 1553B ERROR INJECTION DEFINITION ee ees esse esse esse esse ese see nono nono ee Gee se nono rra ee naar narco Re cn Re ee ee 44 5 5 1 Global RT Error Description Word RT Simulation Table 45 3 3 2 Message Error Injection Word Look up Table A 46 3 6 INTERRUPTS SO Pd EA EO N ER OE EE EE EE 47 5 6 1 Low and High Priority Interrupts two word code 47 5 6 2 Message Interrupts or set of messages interrupt eise see see se ee ee ee be ee ee ee ee ee SR RA Ge ee ee 47 5 6 3 Status Report Queue two words per report ees esse se se Se Se cono Se on nono nora nono conan ran rra ee anar cnn cnn 47 5 7 SPECIFIC FUNCTIONS viii EEE E EE EEE RE EE EE 47 Izal Data Message Receptores ei iE gek bo E EEE NE EE 47 5 7 2 Reception of Mode Commands Data Words see se ee Se ee nono ee ee ee ener recrean 47 5 7 3 Mode Command Synchronise with Data Mord 48 5 7 4 Frequency LOG Ele iaa 48 6 CHRONOLOGICAL BUS MONITOR MODE OF OPERATION u scscssssssssscssssssescsseserssenessessessesseees 49 6 1 INTRODUCTION BE EE AA EE AE EE 49 DL E AAA OO 49 6 2 1 Control Register Write OOH c sscccssccesscesscecsseceesceceecesscecesceesaeecaceesacecaceeeaeecsaeeeeneeceaeeceeaeecnaeeesnee 50 6 2 2 Command Register E 50 6 2 3 Status ONA SERE OE N RR RE ET OE ER E 51 6 2 4 IRQ Selection Register 242 51 6 2 5 Load Clock HI LO Registers 38H1 3AH cccccscccssscsssscesnceesseceeneec
36. conforms to PCI LOCAL BUS specification Rev 2 2 2 6 2 Electrical Characteristics 5V 3 3V and 12V All driving and loading rules are respected 2 6 3 Capabilities The Western Avionics IIB 1553 PMC board is used as a 2Mbyte field R W Static RAM 2Mbyte Read only 32 bit counter one 32 bit access Write only 16 bit register one 16 bit access 2 7 1553B INTERFACE 2 7 1 Introduction The 1553B interface matches the MIL STD 1553B Standard 2 12 Electrical Characteristics The 1553B interface provides one dual redundant bus e Primary bus e Secondary bus The 1553B interface can be programmed to be e Transformer coupled e Direct coupled UM 10974 Rev B 13 2 8 1553 PMC Connector 2 8 1 J1 Connector details The connector used at Jl is a 26 way receptacle assembly Right Angle PCB mounted Amplimite 050 Series to AMP Part Number 787190 2 This connector provides all input output connections for the PMC card and is the only connector used on the front panel Connector pin outs on this connector are as follows Connector Pin Signal Comments Number designation 1 Ground 2 PRI Primary 1553 positive 3 Ground 4 SEC Secondary 1553 positive 5 Ground 6 TOUTC Trigger Out Collector 7 Ground 8 EXTRIG External Trigger 9 Ground 10 TINA Trigger In Anode 11 Ground 12 N C Not connected 13 N C Not connected 1
37. d publications 1 MIL STD 1553 2 PCILOCAL BUS specification 111 STORAGE DATA As the PC card contains electrostatic sensitive devices ESD s special storage and handling is required Do not store near electrostatic electromagnetic magnetic or radiation fields 1 12 TOOLS AND TEST EQUIPMENT No special tools or test equipment is required to test the Western Avionics IB 1553 PMC 1 13 SAFETY PRECAUTIONS WARNING UM 10974 Rev B 10 2 INSTALLATION AND PREPARATION FOR USE 21 GENERAL On delivery inspect the unit for possible damage If it is damaged notify the shipping company and contact your distributor or the Western Avionics for details of return procedure When unpacking remove all protective covering and store covering and packing container as unit may need to be reshipped at a later date CAUTION 22 INSTALLATION OF THE IIB 1553 PMC Prior to installing the Western Avionics IIB 1553 PMC ensure that all power has been removed from the host computer 23 TURN ON Set mains power on host computer to ON The Western Avionics IIB 1553 PMC will perform system self test on the BC MRT and CM lasting approximately four seconds 24 RESET The Western Avionics IIB 1553 PMC hardware and firmware are reset as follows Reset e Signal RES from the PMC bus e Power up and power down e Bit location in control register accessible by the PMC interface UM 10974 Rev B 11 2 5 SPECIFIC FEATURES 2 5 1 Control Register Fea
38. econd Response time is only applicable for 1553B RT RT transfers 6 4 6 Flow Diagram TRIGGER SETUP Base 46H Trigger STACK Set up Register PTCR SCCR SPR FPR etc UM 10974 Rev B 64
39. ector detail Susie as 14 UNO d d URE EE EE EA EE N EE 15 3 1 INTRODUCTION ee se ee ee se AR AA ER Re GE RA GR Re ER Re ee Ge RA ee GR Re ee Ee Re ee RA ee ER ee ee RR Re ee ee ee ee ee Re ee ee 3 2 CONVENTIONS EES ee ee Eet a een roe 3 3 ORGANISATION DIAGRAM degt ENEE daci n 3 4 BASE REGISTER SA a 3 4 1 Base Register Names and Locations 3 4 2 Base Register eege EELER 3 4 2 1 Control Register Write OO 3422 Clock HI Word Read 00H Clock LO Word Read 02H 3 4 2 3 Command Register CR O40 A 3 4 2 4 Status Register SR OGH c ccccsssccesscssscscsccssccescesscossssssonnsscesssessccssesbesnssvadeataceesscsscaenessconssssaasazse 3 4 2 5 Background Running Pointer BRP 08H sesse ee ee se ke ee Re AR ee ee 3 4 2 6 Insertion Running Pointer IRP OAH sesse see see see ee Re GR ee Re AA Re Re ee Re RA Re ee Re Re ee 3 4 2 7 EERDER sitiada OR OK EE EE diria ates 3 42 8 LPIOAP 0EH Low priority interrupt queue start address 3 4 2 9 Reserved LO iii EE EE OE N esis ne N Rd 3 4 2 10 HPIOAP 12H High priority interrupt queue start address 3 4 2 11 Reserved GES OAR asst dvactescdveeass sia 3 4 2 12 MIQAP 16H Message interrupt queue start address 23 UM 10974 Rev B 2 3 4 2 13 Reserved ON EE OE aa 23 3 4 2 14 SRQAP IAH Status report queue start address iese se se ee ee Ge ee ee ee Re ke Ge ee ge 23 3 4 2 15 A EE A EE E EARE N An 23 3 4 2 16 RTSTAD IEH RT simulation table start address 23 3 4 2 17 EL o TI
40. ee Ge ed Gee Gee Ge ee ee ee ee ee ee ee 43 List of Tables Base Register Names and Locations see se ee se ee ee ee GR ee GR Re ee Re ee E GR Re Re ee Re ee ee be 17 Command Register CR apreis oe EE EE EE OE ER EE N EE N 19 Status Su EO OR OE RE EE EE OR EE OD 20 Message Descriptor Block ERA ER RE N RE N KEE 30 Data Descriptor Block SE ER RE RE EE RE EE EE wes pee N 36 Data BUS AE EE EE OE NEE EE 40 Base GOUE EE EE N EE ean NE i 49 Command ul AE EE EE N 50 Status EE 51 Stack Data de ae EE EE OE EE EE EE EE EE EE 63 UM 10974 Rev B 5 1 GENERAL INFORMATION 11 INTRODUCTION This manual applies to 1553 PMC units to top assembly number 1U10974G01 using PCB to P N 1U10975H02 and schematic drawing no 1U10975 Rev B The Western Avionics IIB 1553 PMC Intelligent Interface Board is a standard PMC card designed to meet the requirements of MIL STD 1553B and STANAG 3838 The Western Avionics IIB 1553 PMC provides a powerful and intelligent interface between a PMC based host equipment and the 1553B data bus Bus Controller and Multi Remote Terminal functions can operate both independently or simultaneously An additional independent Chronological Bus Monitor function is provided The Western Avionics ITB 1553 PMC provides complete and comprehensive test and simulation functions for all applications in MIL STD 1553B systems 1 2 MANUAL DESCRIPTION The following paragraphs provide a general description of the manual layout and content Secti
41. efine a specific bit pattern of a particular word within this message If the Window Trigger Fail Register points back to the Single Trigger requirements then the monitor will start again with the next 1553B message Reserved Selective 1 Trigger Mode The Selective 1 Trigger searches for a particular word as with the Single Trigger type However if the last word of a message is encountered before this trigger condition is met the message is not saved on the stack If this trigger condition is met it will branch to the trigger defined by the Pass Register Selective 2 Trigger Mode This trigger type is the same as the Window Trigger with the following exceptions a If the specific word within the message is not found the message will not be stored on the stack and the next trigger is defined by the contents of the Fail Pointer Register b When the trigger condition is found the message is stored on the stack If the number of selective messages defined by the Selective Capture Count Register have not been stored the next trigger is defined by the contents of the Fail Pointer Register UM 10974 Rev B 53 When the programmed number of messages have been stored the next trigger is defined by the Pass register Therefore the two selective capture triggers allow the storage of a specific message or messages Value 6 Post Trigger Count Mode This mode is used as a terminator to the trigger sequence This mode simply stores the number
42. efined by Trigger Data followed by the Nth word within that message which does not meet the conditions of Trigger Data 2 TTRI OOOIH TDP OOOIH TPP 0002H TFP1 OOOIH TTR2 0002H TDP2 0002H TPP2 0001H TEP2 0004H Be 0006H UM 10974 Rev B 62 64 STACK DATA FORMAT When the Bus Monitor is commanded to start all messages will be stored before the trigger condition is met Therefore all pre trigger data is captured The first captured message will start at the address defined by the Start Page Register All following messages will start on an even PAGE boundary The STACK data will wraparound after the Finish Page Register value has been exceeded The format of the messages are shown in table 6 4 Table 6 4 Stack Data Format WORD No NAME 1 Previous Address Pointer 2 Time Stamp HI 3 Time Stamp LO 4 Data 5 Errors N 4 Data N 3 Errors N 2 RT Response Time 1 LSB 0 5 uS N 1 RT Response Time 2 LSB 0 5 uS N Next Address Pointer 6 4 1 Previous Address Pointer The first word of each message will define the page address of the previous message The first message stored will set this pointer to OOOOH 642 Time Stamp HI LO These two locations are a 32 bit word defining the value of the 32 bit 0 5uS clock when the message started 6 4 3 Data These words describe the previous DATA word TYPE BUS_ID and associated errors as follows D15 Did D13 D12 D11 DIO D09 DOS
43. egister Base Address 4EH This register will define the Bus ID and Word Type for the trigger condition D15 Did D13 D12 D11 DIO D09 DOS D07 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Ilegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Date 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 3 Error Word Mask Register Base Address 50H This register will define if the Error Word Register is to be included in the trigger condition D15 Did D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 3 Error Word Register Base Address 52H This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 D14 D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO o lo lo Py Mn tg sh lo lo wclo lo INR TA sy lo Sy 1 Sync Type Error Sh 1 Short Word Error TA EN Terminal Address Error Lg 1 Long Word Error NR sl No Response Error Mn sl Manchester Error WC 1 Wordcount E
44. from DDB Only if Message is Good 4 5 2 Set Message Interrupts When in a DDB bit 12 of the option mask word is set e The 10th word gives a set of message numbers 00H to FFH e The 12th word gives a message indicator e For each set the on board processor manages a set word register It makes an OR with the message indicator in the set word register Then if the set word register is equal to FFFFH the on board processor sends a message interrupt code defined in the 9th word of the DDB and resets the set word register It is possible to define sets from 2 to 16 messages The user initialises at O the set of messages table The 256 word set of messages table is pointed to by the set of Messages Start Address 26H in Base registers UM 10974 Rev B 41 4 5 3 Message Status Report Queue At the end of a message if an event is detected and matches with the 1553B Event Masks of the MDB a Message Status Report is pushed in to the Message Status Report queue 2 words per report Message Number MSB 0 EVENTS with EVENTS BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 Bit 09 BIT 10 BITS 08 to 00 UM 10974 Rev B Wrong Both Buses Error NO RESPONSE Error RT ADDRESS Error TX Error Mn LG SH Py WC Late Response SYNC Type Error 0 Ist Status 1 2nd Status RX Status Bits 42 5 MULTIPLE REMOTE TERMINAL MODE OF OPERATION 5 1 INTRODUCTION In Multiple Remote Terminal mode the Western Avionics IIB 15
45. gger Data 1 then save the number of messages defined by the PTC register TTRI OOOIH TDPI OOOIH TPP 0005H TFPI 0001H TSR 0006H Example 2 Find the message with word defined by the Trigger Data 2 followed by the Nth word within the message defined by the Trigger Data 4 Then save the number of messages defined by the PTC register TTRI 0001H TDPI 0002H TPP 0002H TFPI 0001H TTR2 0002H TDP2 0004H TPP2 0005H TFP2 0001H gt TSR 0006H UM 10974 Rev B 60 Example 3 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 by Trigger Data 3 i e Trigger on a specific 32 bit word TTRI 0001H 1 TDPI 0004H TPPI 0002H 0001H TTR2 0002H TDP2 0001H TPP2 0003H CS 0001H Ly TTR3 0001H TDP3 0003H TPP3 0005H TFP3 0001H Ly TTR4 0006H Example 4 Find the message with word defined by Trigger Data 4 followed by the Nth word within the message defined by Trigger Data 1 Then selectively capture all messages with word defined by Trigger Data 3 followed by word within the message defined by Trigger Data 2 TTRI TDPI TPPI WK gt TTR2 TDP2 TPP2 TFP2 gt TTR3 TDP3 TPP3 TFP3 gt TTR4 TDR4 TPP4 TFP4 TSR UM 10974 Rev B 0001H 0004H 0002H 0001H 0002H 0001H 0003H 0001H 0004H 0003H 0004H 0003H 0005H 0002H 0005H 0003H 0006H 61 Example 5 Find the message with word d
46. he address defined by the contents of OEH Action is limited to the first 64Kbytes of the memory UM 10974 Rev B 38 4 3 2 6 Extended Sub Address To enable the extended sub address feature see the MDB type word When enabled the value of the DDB address in the look up table is in fact a pointer for a further look up table called the extended look up table The on board processor uses the 1553B byte of the first data word received multiplied by four to calculate an offset in the extended look up table to find the true DDB address word Therefore the DDB and data buffer used is defined by the value of the first 1553B RX data word offset gt Reserved MRT 02H DDB address 43 3 Data Buffers Data buffers are pointed to by the buffer address word contained in the data descriptor blocks The address of the toggled buffer is calculated by adding the global toggle offset to the data buffer address value in the DDB The first two words of a data buffer are updated with the value of the local clock at the beginning of the message 1553B data buffers can be stored as follows e The standard way data words behind the time tag words e A particular way allowing the user to store header words of the data message in a different buffer from the following data words The header option and the number of header words are defined in the option mask Header Address Header Message K Data Message K Header Message 2 D
47. he service request bit in the status word If a Transmit Vector Word mode command message occurs the on board processor reads the RT FIFO s If empty the on board processor resets the service request bit and the vector word Otherwise the on board processor reads the FIFO s and writes this next value in the RT vector word High priority vector words are processed before low priority vector words The following 4Kbyte block after the service request queue is reserved for the individual RT requesting FIFO s managed by the on board processor SROADP errorcnnnnnananannns gt EE N N SERVICE REQUEST QUEUE OE SEE ES seen gt EE EE OOAOH TEE ee esse sees ees ee ee ee gt RARA ARA Rls Rls RRR RR Rn RR RR Rn RR RR UM 10974 Rev B 25 To enter a request in the User Requesting Queue the user must manage the current writing pointer SRQADP in Base Registers and control the words pointed at are clear if these words are non zero the queue is full Reaching the end of the queue the user must restart at the beginning of the queue If several user CPUs can enter requests at the same time it is necessary to share control of SRQADP using for example the TASR flag with a test and set instruction To enter a request a CPU must carry out the following procedure Test and set the TASR word MSB bit and a b e If free the SRQADP is read to define the entry address in the queue If the entry location defined by the SRQADP are c
48. igger condition passes This value will be the range to 5 Trigger 2 Fail Pointer Base Address 1CH This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 UM 10974 Rev B 54 Trigger 3 Trigger 3 Type Register Base Address 1EH This register will define the trigger type allocated to trigger 3 This value will be the range 1 to 6 Trigger 3 Data Pointer Base Address 20H This register will define the trigger data allocated to trigger 3 This value will be the range 1 to 4 Trigger 3 Pass Pointer Base Address 22H This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 3 Fail Pointer Base Address 24H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 4 Trigger 4 Type Register Base Address 26H This register will define the trigger type allocated to trigger 4 This value will be the range 1 to 6 Trigger 4 Data Pointer Base Address 28H This register will define the trigger data allocated to trigger 4 This value will be the range 1 to 4 Trigger 4 Pass Pointer Base Address 2AH This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 4 Fail Pointer Base Address 2CH This regi
49. ister Base Address 3EH This register will define the bit pattern required for trigger data 2 Trigger Data 2 Bus ID Word Type Mask Base Address 40H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 DIO D09 DO8 D07 DOG DOS D04 D03 D02 DOL DOO 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 2 Bus ID Word Type Register Base Address 42H This register will define the Bus ID and Word Type for the trigger condition D15 D14 D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DOI DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 2 Error Word Mask Register Base Address 44H This register will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D
50. lear the two words may be entered in the queue If these words are non zero the queue is full Increments the SRQADP if the end is reached reinitialise it to the beginning Resets the TASR If not free waits until free 3 4 2 25 Reserved 46H 3 4 2 26 PRI SEC 1553B RT TX Inhibit HI LO 48H 4EH HI RT 30 er aoe RT17 RT16 LO RT15 RT14 RT1 RTO 0 enable the transmitter 1 disable the transmitter A bit set defines the specific RT transmitter as inhibited Initialisation by the user before cold start Disable enable by corresponding mode command messages The user can modify the inhibit bits in real time The receive function of the simulated RT is never disabled UM 10974 Rev B 26 3 5 REMOTE TERMINAL SIMULATION TABLE For each RT 16 words are used to define and store information concerning RTs The pointer to this table RTSTAD must be a multiple of 20H Refer to table 3 2 RTSTAD _ gt _ 00H Simulation Type word 02H RT Status Word 04H 1553B Last Command Word 06H 1553B Look up Table Address MRT Only 08H Reserved 0AH 1553B Mode Commands Look up table Address MRT Only 0CH Vector Word 0EH 1553B BIT Word ay 10H Reserved 12H Reserved 14H Reserved 16H Global RT Error Descriptor Word MRT Only 18H Not Used 1AH Not Used 1CH Not Used 1EH Not Used 20H RT1 Si Co RT30 RT31 Broadcast 4
51. ndant transceiver and a Manchester encoder decoder with full error detection and error injection capabilities which include Manchester bit error Synch bit error Parity error Word length error Wrong bus error Both bus error Response time error UM 10974 Rev B 8 17 FEATURES The features of the Western Avionics I IB 1553 PMC are listed as follows Universal PMC card Can be used in 3 3V or 5V slot Memory mapped real time PMC interface 2MByte of RAM Multiple interrupt queues for various events 1553B data protocol managed by a micro controller providing complete flexibility and extension capability Error Injection and detection External Triggers Internal Self tests 18 SYSTEM CHARACTERISTICS AND SPECIFICATIONS The characteristics and specifications of the Western Avionics ITB 1553 PMC are listed as follows Size Standard PMC card 148 by 74 mm Power 15Vdc 450 mAmps 3 3V 150mAmps 3 3V slot use 5Vdc 600 mAmps 5V slot use 12Vdc 160 mAmps Temperature e Operating 0 C to 50 C e Non operating 20 C to 70 C MTBF e 104 817 Hrs Ground Benign 25 C e Front Panel Connectors UM 10974 Rev B eTrig In Trig Out e 1553B Primary and 1553B Secondary 19 LIST OF FURNISHED ITEMS The following is a list of furnished items 1 Bus Analyser Simulator Model ITB 1553 PMC 2 Users Manual UM10974 This document 1 10 LIST 0F RELATED PUBLICATIONS The following is a list of relate
52. of messages defined by the Post Trigger Count Register on the stack and then stops activity If the PTC is set to H8000 storage will continue until the board is commanded to halt NOTES This trigger mode always resides in the Trigger Stop Register and never in any other register This is trigger 5 and must always be pointed at as the last part of the trigger sequence Trigger 1 Trigger 1 type Register Base Address 0EH This register will define the trigger type allocated to trigger 1 This value will be in the range 1 to 6 Trigger 1 Data Pointer Base Address 10H This register will define the trigger data allocated to trigger 1 This value will be the range 1 to 4 Trigger 1 Pass Pointer Base Address 12H This register will define the new trigger to be activated if this trigger condition passes This value will be the range 1 to 5 Trigger 1 Fail Pointer Base Address 14H This register will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger 2 Trigger 2 Type Register Base Address 16H This register will define the trigger type allocated to trigger 2 This value will be the range 1 to 6 Trigger 2 Data Pointer Base Address 1 8H This register will define the trigger data allocated to trigger 2 This value will be the range 1 to 4 Trigger 2 Pass Pointer Base Address 1AH This register will define the new trigger to be activated if this tr
53. on 1 General Information contains a brief description of the manual and a general description of the Western Avionics IIB 1553 PMC This section also contains the architecture protocol management MIL STD 1553B interface information instrument specifications information concerning accessories furnished items and also safety precautions Section 2 Installation and Preparation for Use contains instructions on installation preparation for use self test and reset of the Western Avionics IIB 1533 PMC card Section 3 Operation contains a functional description of the Western Avionics IIB 1553 PMC and Operating procedures necessary to run the card Section 4 Bus Controller Mode of Operation contains information on the mode of operation for the Bus Controller function of the Western Avionics IIB 1553 PMC card Section 5 Multiple Remote Terminal Mode of Operation contains information on the mode of operation for the Multiple Remote Terminal function of the Western Avionics IIB 1553 PMC card Section 6 Chronological Bus Monitor Mode of Operation contains information on the mode of operation for the Chronological Bus Monitor function of the Western Avionics IIB 1553 PMC card 1 3 CAPABILITIES The Western Avionics IIB 1553 PMC provides the following capabilities and functions 1 3 1 General Memory mapped real time universal PMC interface 2MByte of RAM INTA interrupt 1553B data protocol managed by a micro controller p
54. or the LSB the value for 20ms is 7DOH It must be initialised at the beginning of the background program This instruction resets the minor frame counter register SWPSE Software Pause e To be put at the end of each minor cycle instruction list with the minor frame duration utility to have automatic minor frame restart Examples INITF xxxx HWSPE waiting an external trig SWPSE JSR Minor Cycle 1 SWPE SWPSE BRA xxxx with Minor cycle X SMB xxxx SMB xxxx RTS LOOP 8 JSR Minor cycle SWPSE DBNE xxxx SITH BRA xxxx e Insertion Commands can be executed during SWPSE state e HALT e On completion of this instruction the board will return to the BC idle state e To re start the board BC Cold Warm Start command register SITH xxxx SITL xxxx e The on board processor puts the value code xxxx in the cycling FIFO s H gt High Priority L gt Low Priority HWPSE Hardware Pause e Restart by the external Trig In external CK e All the registers are not initialised e Used to synchronise messages of minor frames on external Trig In Example See SWPSE above UM 10974 Rev B 22 3 4 2 6 Insertion Rumning Pointer IRP OAH The Insertion Running Pointer IRP has the same set of instructions as Instruction Set Background Program To initiate an insertion the user must first load the IRP with the address of the insertion program Then bit Cl can be cleared in the con
55. r Set up Pointer TSP UM 10974 Rev B 49 6 2 1 Control Register Write 00H D15 DI4 D13 D12 DI1l DIO D09 DOS DO7 D06 DOS D04 DO3 D02 DOL DOO 0 0 0 0 0 0 0 HR 0 IEN IRQ 0 0 0 Cl CO CO Clear gt Command Request Cl Clear gt Insertion Request HR Clear gt Hardware RESET If IEN is set and IRQ is set then interrupt line will be cleared If IEN is set and IRQ is clear then the interrupt line will be asserted for test purposes only If TEN is clear the value of IRQ is unaffected Note This register must be accessed to clear the interrupt during an interrupt service routine Examples 1 0102H generates a command request 2 0163H clears the interrupt line 6 2 2 Command Register CR Prior to clearing the Command Request bit CO in the Control Register the user must first test that the CR is clear When the CR is clear the user can insert the next command to be executed Refer to table 6 2 Table 6 2 Command Registers CODE COMMAND 0000H Illegal 0001H GO TO BCT MODE 0002H GO TO MRT MODE 0003H GO TO MON MODE 0004H Reserved 0005H Reserved 0006H Reserved 0007H Reserved 0008H Reserved 0009H Reserved 000AH Reserved 000BH Reserved 000CH LOAD CLOCK 000DH SELFTEST OOOEH RUN MONITOR OOOFH STOP MONITOR 0010H SYNCHRONISE CLOCK After the command is loaded bit CO in the Command register can be cleared When the CR clears the board is ready for
56. rent messages priority of interrupt three different available one interrupt only per message The data word count contains the data word count expected by the user The Western Avionics IIB 1553 PMC processor compares this word count with real data word count transmitted on the bus and writes the difference if any in the data status report word This last word also contains the status flag of the transmission message received correct or with error message running The most significant byte of data buffer address can be used to enable toggled buffer control toggle on beginning of each minor frame or on multiple cycles of this minor frame This allows user software synchronised on the frame cycle to always access the correct buffer The set of message interrupt features provides the possibility to send an interrupt after the last message of the set of messages It is to be used when the frame sequence is not purely repetitive Up to 128 different sets of messages from 2 to 16 messages each can be defined Refer to table 4 Error injection on 1553B data words is defined in the message descriptor blocks Table 4 2 Data Descriptor Block DDB ADDRESS OPTION MASK 02H Header Address 04H Data Word Count 06H Data Status Report 08H Toggle Frequency and Buffer Address HI 0AH Buffer Address LO 0CH Link Pointer to Address of another DDB 0EH Address of Modify Word 10H Value to Write 12H Message Interrup
57. reset and the vector word is reset or updated with the next vector word in FIFO s if any UM 10974 Rev B 40 4 55 INTERRUPT REQUESTS Three types of interrupt requests IRQ can be generated by the Western Avionics ITB 1553 PMC board e IRQ L and IRQ H low priority and high priority are synchronisation interrupts defined as follows By instructions in the BC instruction list In message descriptor block to report on bus events detection In data descriptor block to signal the transmission of a message e IRQ M is a data message interrupt and occurs only when the transmission of a data buffer is correct and the requesting bit is set in the data descriptor block It can also be programmed to occur with the last message of a set of 2 to 16 messages set of messages option When setting an IRQ the Western Avionics I B 1553 PMC board pushes a vector code into queues each code defines the event origin of the IRQ Each queue must start at an address multiple of 200H The user must manage the reading pointer and erase with a OOOOH value the codes after reading 4 5 1 Interrupt Coding l LO and HI priority interrupts two words Messages without error 0800H DDB Address Messages with error 0C00H DDB Address BC Event without RETRY 1000H Status Queue Address BC Event with RETRY 4000H Status Queue Address Send Interrupt SITL SITH 2000H SITL SITH Vector 2 Message Interrupts one word Message Interrupt Code
58. ress 26H This is the pointer of a 256 word table reserved to the on board processor to compute the registers Set of Messages For further details refer to paragraph 4 5 2 3 4 2 21 Global RT Response Time Register 28H This is the response time for all the simulated RT s Different RT response time can be defined in the error description words LSB lus For some modes this global RT response time register is not programmable fixed at 4us e 1553B Mode without data If the value is less than 4 the on board processor selects 4uS 3 4 2 22 RT No Response Time Out Register 2AH RT Response Time The programmable RT no response time out defines the maximum RT response time allowed by the board to an RT before detecting NO RESPONSE LSB lus UM 10974 Rev B 24 3 4 2 23 IRQ Selection Register 34H DIS D14 D13 D12 D11 D10 D09 DO8 D07 D06 DOS D04 DO3 DO2 DOI DOO 0 0 0 0 Cycling Message HI Queue LO Queue 0 0 c o 0 M o 0 H o 0 L C If set a physical INTA interrupt will be generated when a Broadcast Synchronise With Data mode code occurs M If set a physical INTA interrupt will be genera
59. roviding flexibility and extensibility Comprehensive Error Injection External Triggers Internal Self tests Standard single PMC card format UM 10974 Rev B 6 1 3 2 Bus Controller BC Features With MRT Simulation and Data Monitoring Bus Control Autonomous frame control using comprehensive set of instructions and message descriptor blocks Acyclic message insertion Error injection Frame frequency selection Inter message gap selection Response time out selection Bus events detection mask storage and reporting bus errors status word bits Simultaneous MRT Simulation up to 31 Data Words Transfers Data buffer simulation for the BC and the simulated RT s Sub address based data buffer access with data descriptor blocks defining each bus message Multi buffering linked buffers or frequency toggled buffers Interrupt queues Data status report Data buffer time tagging 32 bits time tag Simultaneous monitoring of all data buffers 1 3 3 Multiple Remote Terminal MRT Features Simulation Up to 31 1553B RT simulations Mode and Broadcast commands handling Comprehensive Error Injection Data Words Transfers Data buffer simulation for simulated RTs e Sub address based data buffer access offering the same powerful data buffering as in the bus controller mode All non transmitted data messages are monitored 1 3 4 Chronological Bus Monitor CM Features
60. rror Py sl Parity Error UM 10974 Rev B 58 Trigger Data 4 Trigger Data 4 Bit Mask Register Base Address 54H This register will define the bits to be ignored in the trigger bit pattern for trigger data 4 Any bit set in this register will be masked from the trigger test condition Trigger Data 4 Bit Pattern Register Base Address 56H This register will define the bit pattern required for trigger data 4 Trigger Data 4 Bus ID Word Type Mask Base Address 58H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 Did D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits 1 Ignore Bus ID in trigger condition Trigger Data 4 Bus Word Type Register Base Address 5AH This register will define the Bus ID and Word Type for the trigger condition D15 Did D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Wmsb WLsb BMsb BLsb 0 0 Trigger on Command 0 0 Illegal 0 1 Trigger on Status 0 1 Trigger on Primary 1 0 Trigger on Data 1 0 Trigger on Secondary 1 1 Trigger on RT RT Transfer 1 1 Trigger on Both Buses Trigger Data 4 Error Word Mask Register Base Address 5CH This regis
61. seceeaeeeseceeceecnaeceeneeseaaeceeeeeenaees 52 6 2 6 Current Address Register CAR Z2H 52 6 2 7 Trigger Occurrence Register TOR 3430 52 6 2 8 Trigger Set up Pointer TSP 20 sesse ee esse sesse ee se es se Gee Se Ge nono nn rca none nro recon cnn canon nn E ee 52 6 2 8 L Tripper Setup Dala EE EE NA ME AE EN 52 6 3 DETAILED TRIGGER DESCRIPTION ee see see ee ese ee ee ee ee ee ee ee ee ee be nro cnn earn canon nn nn neon nn Re Re ee ee 53 AN eo de ve Vd ENE EE id 63 6 4 1 Previous Address di ani EE EE EE 63 6 4 2 TRY da ME ORN EE NE EE RE EE EE ON N 63 6 4 3 RE ER EE EL EA ML ER OE EE ON 63 6 4 4 Next Address Poltica EE EE EE EE RE E EA 64 6 4 5 RT Response Time EE ORE OE EEE 64 6 4 6 Flow DGS EE ER EN OR EO OE FOK 64 UM 10974 Rev B 4 Figure 1 1 Figure 2 2 Figure 3 2 Figure 4 1 Figure 4 2 Figure 5 1 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 4 2 Table 4 3 Table 6 1 Table 6 2 Table 6 3 Table 6 4 List of Figures TIB 1553 PMC Functional Block Diagram iese sees se esse es es ee RA Re Ge ee Ge ee cnn ee cono RA RA GR RA ee 8 TIB 1533 PMC Front SEA AE EE N EE N 14 Remote Terminal Simulation Table 27 Bus Controller Organisation Diagram sesse esse esse ese ee ee se ee ee Ge Se SR GR RA RA GR Gee Ge ee ee ee ee 29 Data Buffers Simulation and Monitoring 0 0 0 ee ee ee ee ee Ge RA GRA GRA Gee RA RA ee Gee Ge ee ee ee ee ee 35 Multiple Remote Terminal Organisation Diagram esse see see see see s
62. ster will define the new trigger to be activated if this trigger condition fails This value will be the range 1 to 5 Trigger Stop Register Base Address 2EH This register will always be programmed to the value 6 This register is the STOP trigger sequence register UM 10974 Rev B 55 Trigger Data 1 Trigger Data 1 Bit Mask Register Base Address 30H This register will define the bits to be ignored in the trigger bit pattern for trigger data 1 Any bit set in this register will be masked from the trigger test condition Trigger Data 1 Bit Pattern Register Base Address 32H This register will define the bit pattern required for trigger data 1 Trigger Data 1 Bus ID Word Type Mask Base Address 34H This register will define the Bus ID and Word Type bits to be ignored in the Bus ID Word Type Register D15 D14 D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 Both W bits 1 Ignore Word Type in trigger condition Both B bits Ignore Bus ID in trigger condition Trigger Data 1 Bus ID Word Type Register Base Address 36H This register will define the Bus ID and Word Type for the trigger condition D15 Did D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 0 0 0 0 W W 0 B B 0 0 0 0 WMsb WLsb BMsb BLsb 0 0
63. t Code 14H Set of Message Number 16H Message Indicator in the Set of Messages 18H Reserved 1AH Reserved 1CH Reserved 1EH Reserved UM 10974 Rev B 36 4 3 2 1 Option Mask 00H BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 09 BIT 08 BIT 07 BIT 06 BIT 05 BIT 04 to 00 1 Interrupt on Correct Message 1 Interrupt on Error Message 1 HI LO Priority Queue 0 LO 1 HI 1 Interrupt on Set of Messages 1 Message Interrupt If Message Correct 1 Link only on Correct Message 1 Link to New DDB Enabled 1 Modify Word Enabled 0 0 0 Header Word Count 4322 Data Status Report 06H BIT 15 to 14 BIT 13 to 00 NOTE 00 Good Message 01 Message Running 10 Error Message Signed Wordcount Error 0 No Wordcount Error The wordcount error is calculated as follows TX Wordcount Command Wordcount DDB Count Header Count RX Wordcount Wordcount Received DDB Count Header Count 4 3 2 3 Toggle Frequency and Buffer Address HI 08H The word 24H in Base Registers defines if the data buffer toggle feature is enabled and also the toggle offset MSB 1 global toggle enabled 0 no toggle offset 15 bits MSB OFFSET 15 14 0 The 5th word in a DDB enables the toggle feature for the corresponding data buffer and the toggle frequency BIT 15 BIT 14 to 11 BIT 10 to 08 BIT 07 to 00 UM 10974 Rev B 1 Enable toggle local 0 Frequency indi
64. ted when a push to the Message Queue occurs H Tf set a physical INTA interrupt will be generated when a push to the High Priority Queue occurs L If set a physical INTA interrupt will be generated when a push to the Low Priority Queue occurs 34224 Test and Set Register and SRQADP 3CH These two words are used to automatically manage FIFO s of vector words for each simulated RT For simulated RTs the Service Request bit in the status word can be set and reset by the user The vector word can be initialised by the user After a Transmit Vector Word mode command message the on board processor automatically resets the service request bit and the vector word On the other hand a service request queue is defined to automatically queue words representing successive requests for the simulated RTs This service request queue is 3 words long starting at the initial address in the service request queue address pointer SRQADP For a request two words are set in the queue as follows 1 RT number 000000000RRRRRIX R RT address X Priority BIT 1 1 2 Vector word Two different priorities are available X O High priority X 1 Low priority Reading this FIFO the on board processor manages each RT two 32 word vector words FIFO s one per priority These vector words are then used by the RT simulation If an RT FIFO is not empty the on board processor reads it then writes the value in RT vector words RT Simulation Table and sets t
65. ter will define if the Error Word Register is to be included in the trigger condition D15 D14 D13 D12 D11 DIO D09 DOS D07 DO6 DOS D04 D03 D02 DOL DOO 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 D 1 Error condition disabled Trigger Data 4 Error Word Register Base Address 5EH This register will define the Errors required in the trigger condition If more than one error is set the trigger condition will be a logical OR of the errors D15 Did D13 D12 D11 DIO D09 DOS DO7 DO6 DOS D04 D03 D02 DO1 DOO 0 0 0 Py Mn Lg Sh vu 0 WC 0 0 NR TA Sy O Sy 1 Sync Type Error Sh 1 Short Word Error TA 1 Terminal Address Error Lg 1 Long Word Error NR 1 No Response Error Mn 1 Manchester Error WC 1 Wordcount Error Py 1 Parity Error Trigger Start Register Base Address 60H This register defines the first trigger to be used in the trigger sequence This will be in the range 1 to 5 UM 10974 Rev B 59 Examples The first trigger used in the sequence is defined by the contents of the Trigger Start Register For these examples assume that the Trigger Start Register points to Trigger 1 value 1 Key TTR Trigger Type Register TDP Trigger Data Pointer TPP Trigger Pass Pointer TFP Trigger Fail Pointer TSR Trigger Stop Register Example 1 Find the word defined by Tri
66. trigger can be allocated one of four different data and error conditions If a trigger passes this condition it then moves on to the trigger defined by the Pass register If a trigger fails this condition it then moves on to the trigger defined by the Fail Register Value 1 Value 2 Value 3 Value 4 Value 5 Ea ch trigger is allocated a trigger type value from one to six and these are as follows Single Trigger Mode The Single Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register If this condition is TRUE for the incoming 1553B word the Single Trigger will branch to the trigger defined in the Pass Register If it fails it will branch to the trigger defined by the Fail Trigger Register Window Trigger The Window Trigger Mode will search for the trigger data defined by the Trigger Data Pointer Register within the first 1553B message it encounters If this condition is TRUE for a word within the incoming message the Window Trigger will branch to the trigger defined in the Pass Register If the value of the Window Word Count Register is non zero the Window Trigger will use this value to specify the word number within the message for the Trigger test to be carried out If this value is zero all words within the message will be tested The Window Trigger would normally be preceded by a Single Trigger The Single Trigger would define the specific 1553B command word then pass to the Window Trigger to d
67. trol register 3 4 2 7 3 4 2 8 3 4 2 9 3 4 2 10 3 4 2 11 3 4 2 12 3 4 2 13 3 4 2 14 3 4 2 15 3 4 2 16 3 4 2 17 3 4 2 18 The background program can be interrupted by an insertion command The insertion program cannot be interrupted by any other insertion command In this case the second insertion request will be delayed until the end of the first one Insertion program starting just before a minor cycle start will delay this one IRP is updated by the on board processor after executing a BC stop command Reserved 0CH LPIQAP 0EH Low priority interrupt queue start address Reserved 10H HPIQAP 12H High priority interrupt queue start address Reserved 14H MIQAP 16H Message interrupt queue start address Reserved 18H SRQAP IAH Status report queue start address Reserved OCH RTSTAD IEH RT simulation table start address Contains the address of the RT Simulation Tables which defines the RT status when they are simulated Reserved 20H Reserved 22H UM 10974 Rev B 23 3 4 2 19 Toggle Buffer Address Offset 24H MSB 1 global toggle enable 0 no toggle offset 15 bits MSB offset 15 14 0 For a data buffer if the toggle feature is selected bit 15 1 the address of the toggle buffer is Buffer Address High Toggle Buffer Offset Buffer Address Low 15 bits For further details refer to paragraph 4 3 3 3 3 4 2 20 Set of Messages Start Add
68. tures This is a 16 bit write only register accessible from the PMC bus This register is mapped into the memory field The features are as follows e Hardware reset e Three prioritised interrupts to the local on board processor for indication and control e Acknowledge PMC Interrupt 2 5 2 Counter Features This 32 bit counter is a free running counter with a 0 5us or lus LSB and can be read from a memory mapped location via the PMC bus interface The counter should be read in a single 32 bit access The counter can be updated and used by the on board processor as follows Used Data buffers time tagging Frame cycles control Bus Monitoring Updated User request 1553B command 2 5 3 Trigger In Features Trigger In enters the board logic through the front panel connector and then an opto coupler Inputs to this feature can be used for hardware starts of the major and or minor frames or external trigger for the bus monitor 2 5 4 Trigger Out Features Trigger Out is in fact a bit in a register accessible by the on board processor to indicate to the external world that an event has been detected This event can be as follows Beginning of the major and or minor frames Beginning of a message Bus Monitor trigger detected Trigger Out exits the board through an opto coupler and the front panel connector UM 10974 Rev B 12 2 6 PMC INTERFACE 2 6 1 Introduction The PMC interface on the Western Avionics IIB 1553 PMC board
69. will be generated when the stack is half full UM 10974 Rev B 51 6 2 5 Load Clock HI LO Registers 38H1 3AH If a LOAD CLOCK command is executed these two registers define a 32 bit value to be loaded into the counter If a SYNCHRONIZE CLOCK command is executed the two registers define a 32 bit signed number to be added to the current clock value 6 2 6 Current Address Register CAR 42H This register contains the PAGE address of the current message being stored 6 2 7 Trigger Occurrence Register TOR 44H This register contains the PAGE address of the message that met the pre programmed trigger condition 6 2 8 Trigger Set up Pointer TSP 46H This register contains the absolute address of the trigger set up data NOTE This value is only 16 bits All trigger set up data must reside in the first 64Kbytes of the board 6 2 8 1 Trigger Set up Data TSP Address 00H Post Trigger Count Register PTCR This register will contain the number of messages to be stored after the trigger condition is met This value will be in the range 0000H to 8000H 0000H Stop immediately after trigger message 8000H Capture Forever 02H Selective Capture Count Register SCCR This register will contain the number of messages to be stored when the monitor is in the Selective Capture Mode This value will be in the range 0000H 8000H 20000H 1 message 8000H Selective Capture Forever 04H Start Page Register SPR

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