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S3C8275/F8275/C8278 /F8278/C8274/F8274

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2. 2 13 Using the RPs to Calculate the Sum of a Series of Registers 2 14 Addressing the Common Working Register 2 18 Standard Stack Operations Using PUSH and 2 23 Chapter 7 Clock Circuit Switching the CPU Glock c ME 7 7 Chapter 16 Embedded Flash Memory Interface Secior 16 8 Liege EE 16 9 Fi adirig mb titius cite tutta LL t ti 16 10 Hard eres ndis zie n NE ECC ET ITIN 16 11 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER xvii Register Identifier BLDCON BTCON CLKCON CLOCON EXTICONH EXTICONL EXITPND FLAGS FMCON FMSECH FMSECL FMUSR IMR IPH IPL IPR IRQ LCON OSCCON POCONH POCONL POPUR P1CONH P1CONL P1PUR P2CONH P2CONL P2PUR P3CONH P3CONL P3PUR P4CONH P4CONL P5CONH P5CONL P6CON PP RPO RP1 SIOCON SPH SPL STPCON SYM TACON TBCON WTCON 3C8275 F8275 C8278 F8278 C8274 F8274 MICROCONTROLLER List of Register Descriptions Full Register Name Page Number Battery Level Detector Control 4 5 Basic Timer Control 4 6 System Clock Control 4 7
3. 3 4 3 5 Indirect Working Register Addressing to Register 3 5 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 3 7 Indexed Addressing to Register 3 7 3 8 Indexed Addressing to Program or Data Memory with Short Offset 3 8 3 9 Indexed Addressing to Program or Data Memory 3 9 3 10 Direct Addressing for Load 3 10 3 11 Direct Addressing for Call and Jump Instructions 3 11 3 12 Eee a Ge bdo Prades 3 12 3 13 Relative Addressing 2 eene oe ee D eue tree ud 3 13 3 14 Immediate 0 3 14 4 1 Register Description 4 4 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER List of Figures Figure Title Page Number Number 5 1 S3C8 Series Interrupt 5 2 5 2 53 8275 8278 8274 Interrupt 53 5 3 ROM Vector Address nnns 5 4 5 4 Interrupt Function Diagram 5 7 5 5 System Mode Register 5 5 9 5 6 Interrupt Mask Register Hem 5 10 5 7 Interru
4. 6 6 Fag Descriptions aniren mI ES 6 7 Instruction Set NOtation soot et ete rp d tee le x ETHER OS 6 8 Condition Codes sic cake ae ava ea eet a eel 6 12 Instruction Descriptioris nisi iet ee cord bored denies oret E bem SEE adi 6 13 vi 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER Table of Contents continued Part Hardware Descriptions Chapter 7 Clock Circuit OVE EWA eo rictu eor concise S gabe teris edid cete Eb te feria 7 1 vent E 7 1 7 2 Sub Oscillator 7 2 Clock Status During Power Down 7 3 System Clock Control Register ener rennen nnne 7 4 Clock Output Control Register 00 00 7 5 Oscillator Control Register 06 7 6 SwitchingAhe CPU Clock enc Ee pare eive tr OUR Ma UE TENERE 7 7 Chapter 8 RESET and Power Down System Heset ete Seed T eee seca ERU En RE EP ERR e ERU 8 1 eM EE 8 1 Normal Mode Reset
5. BLD block works only when BLDCON 3 is set If Vpp level is lower than the reference voltage selected with BLDCON 2 0 BLDCON 4 will be set If Vpp level is higher BLDCON 4 will be cleared When users need to minimize current consumption do not operate the BLD block Vpp Pin Battery Level BLDCON 4 Detector BLD Out BLDCON 3 VBLDREF P2 0 BLD Run Battery Level Setting P2CONL 1 0 ExtRef Input BLDCON 2 0 Enable Set the Level Figure 15 1 Block Diagram for Voltage Level Detect ELECTRONICS 15 1 BATTERY LEVEL DETECTOR 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BATTERY LEVEL DETECTOR CONTROL REGISTER BLDCON The bit 3 of BLDCON controls to run or disable the operation of Battery level detect Basically this Vg pis set as 2 2 V by system reset and it can be changed in 3 kinds voltages by selecting Battery Level Detect Control Register BLDCON When you write bit data value to BLDCON an established resistor string is selected and the Vg p is fixed in accordance with this resistor Table 15 1 shows specific Vg p of levels Resistor String Battery Level Detector Control Register F4H Set 1 Bank 1 R W Reset 00H Not use o UL C VIN Mux BLD our VBLDREF BLD Enable Disable P2CONL 1 0 NOTES 1 The reset value of BLDCON is 00H 2 VREF is about 1 volt Figure 15 2 Battery Level Detect Circuit and Cont
6. 1 0 fxx 64 o o fwen 1 o o ES 1 0 TICK external clock Timer 1 A Counter Clear Bit 1 Clear the timer 1 A counter when write automatically cleared to 0 after being cleared basic timer counter Timer 1 A Counter Operating Enable Bit Disable counting operation Enable counting operation Timer 1 A Interrupt Enable Bit Disable interrupt Enable interrupt Timer 1 A Interrupt Pending Bit No interrupt pending when read clear pending bit when write Interrupt is pending when read 4 45 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec TBCON Timer B Control Register E7H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode 4 46 Register addressing mode only Not used for 5308275 C8278 C8274 Timer B Clock Selection Bits fxx 512 fxx 256 fxx 64 e o memdd Timer B Counter Clear Bit 1 Clear the timer B counter when write automatically cleared to 0 after being cleared basic timer counter Timer B Counter Operating Enable Bit Disable counting operation Enable counting operation 1 Timer B Interrupt Enable Bit Disable interrupt 1 Enable interrupt Timer B Interrupt Pending Enable Lo No interrupt pending when read clear pending bit when write Interrupt is pending when read LI E
7. ___ pau 2 ELECTRONICS 1 7 PRODUCT OVERVIEW PIN CIRCUITS VDD P Channel N Channel 53 8275 8275 8278 8278 8274 8274 Preliminary Spec VDD Pull Up Resistor Schmitt Trigger Figure 1 4 Pin Circuit Type A Open Drain Data Output Disable Figure 1 5 Pin Circuit Type B nRESET VDD Pull up VDD Resistor box Resistor Enable Schmitt Trigger Figure 1 6 Pin Circuit Type E4 PO P1 1 8 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PRODUCT OVERVIEW COM SEG Output Disable VLC2 Vss Figure 1 7 Pin Circuit Type H 4 Pull Up Resistor Resistor Enable Disable 1 Circuit Output Type H 4 Disable 2 Figure 1 8 Pin Circuit Type H 8 P2 1 P2 7 P3 ELECTRONICS 1 9 PRODUCT OVERVIEW Data Output Disable 1 COM SEG Output Disable 2 53 8275 8275 8278 8278 8274 8274 Preliminary Spec Pull Up Resistor lt Resistor Enable Circuit Type H 4 Figure 1 9 Pin Circuit Type H 9 P4 P5 P6 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PRODUCT OVERVIEW Pull Up Resistor A Resistor Enable Alternative Function BLDEN BLD Select To BLD Figure 1 10 Pin Circuit Type H 10 P2 0 ELECTRONICS 1 11 PRODUCT OVERVIEW 53 8275 8275 8278 8278 8274
8. 20 3 20 3 40 Pin Connectors J101 J102 for 8275 8 4 00 20 7 20 4 S3E8270 Cables for 64 QFP mee 20 7 xiv 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER Table Number 1 1 2 1 2 2 4 1 4 2 4 3 5 1 5 3 6 1 6 2 6 3 6 5 6 6 8 1 8 2 8 3 List of Tables Title S3C8275 F8275 C8278 F8278 C8274 F8274 Pin Descriptions S3C8275 Register Type 3C8278 C8274 Register Type Set 1 FegiSters Bank O Registers eee Tes deoa Seti Bank 1 Regislers x uci It fH eroe Een RR EE deeded Interrupt Vectors aniio tec eines ees Interrupt Control Register Overview Interrupt Source Control and Data Instruction Group 2 Flag Notation Conventions Instruction Set Symbols Instruction Notation Conventions He Opcode Quick Reference D RT DNI ied 60065 5 Lor Paket EE Pede aser 53 8275 8278 8274 Set 1 Register and Values After RESET 53 8275 8278 8274 Se
9. Pn2 1 0 Figure 9 1 53C8275 C8278 C8274 1 0 Port Data Register Format 9 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORTS PORT 0 Port 0 is an 8 bit I O port with individually configurable pins Port 0 pins are accessed directly by writing or reading the port 0 data register PO at location FOH in set 1 bank 0 0 0 0 7 can serve as inputs with or without pull up as output push pull or open drain or you can be configured the following functions Lownibble pins 0 0 0 3 INTO INT2 High nibble pins P0 4 P0 7 TAOUT TBOUT CLKOUT BUZ Port 0 Control register POCONH POCONL Port 0 has a 8 bit control register POCONH for 0 4 0 7 and POCONL for P0 0 P0 3 A reset clears the POCONH and POCONL registers to configuring 0 0 0 2 pins to input mode with interrupt and PO 3 PO 7 input mode You use control register setting to select input or output mode push pull or open drain and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port O control registers must also be enabled in the associated peripheral module Port 0 Pull up Resistor Control Register POPUR Using the port 0 pull up resistor control register P1 PUR E6H set 1 bank 0 you can configure pull up resistors to individual port O pins Port 0 Interrupt Control Registers EXTICONL
10. eaa 1 2 eje PIE p ME EC stagnate see a tee sheeted 1 3 0c IEEE 1 4 Pin DESCIIPUONS jie e P 1 6 e a a a A a E E rT 1 8 Chapter 2 Address Spaces ues ef a a Ee 2 1 Program Memory ER HERE ERR RAD 2 2 Smart EET 2 3 Register Architecture reget RT bec Reg Eon hake 2 5 Register Page Pointer PP enero tiet eter a ea Tee Hanah cetacean ena 2 8 BEEE HD 2 10 Register p PE 2 10 Prime Register Space 1 2 RE tac dne eU E 2 11 Working Heglslers 2 12 Using the Register Points 2 2 2 13 Register Addressing yeh e TUE 2 15 Common Working Register Area 2 17 4 Bit Working Register 3 2 18 8 Bit Working Register 2 20 systemvand User Stack Pont ce e law 2 22 Chapter 3 Addressing Modes 2 doceo
11. 1 11114 0 1 2 3 4 5 6 7 0 1 2 3 fol 4 5 6 7 Data Register page 4 address B2H Data Register page 4 address B1H LD B2H 63h Data Register page 4 address BOH LD B1H 7Ah LD BOH 3Eh Figure 13 9 LCD Signals and Wave Forms Example in 1 4 Duty 1 3 Bias Display Mode 13 8 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SERIAL I O INTERFACE SERIAL I O INTERFACE OVERVIEW Serial I O modules SIO can interface with various types of external device that require serial data transfer The components of SIO function block are 8 bit control register SIOCON Clock selector logic 8 bit data buffer SIODATA 8 bit prescaler SIOPS 3 bit serial clock counter Serial data I O pins SI SO Serial clock input output pin SCK The SIO module can transmit or receive 8 bit serial data at a frequency determined by its corresponding control register settings To ensure flexible data transmission rates you can select an internal or external clock source PROGRAMMING PROCEDURE To program the SIO module follow these basic steps T 2 Configure the I O pins at port SCK SI SO by loading the appropriate value to the P 1CONL register if necessary Load an 8 bit value to the SIOCON control register to properly configure the serial I O module In this operation SIOCON 2 must be set to 1 to enable the data shifter For interrupt generation set the serial I O interrup
12. SWAP 02H gt Register 02H register 4AH In the first example if general register 00H contains the value 3EH 00111110B the statement SWAP 00H swaps the lower and upper four bits nibbles in the OOH register leaving the value 11100011B ELECTRONS 6 83 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec TCM Test Complement Under Mask TCM dst src Operation NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine the result The destination and source operands are unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 63 r Ir opc src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Examples Given RO OC7H R1 02H R2 12H register 00H 2BH register 01H 02H and register 02H 23H TCM RO R1 gt RO OC7H R1 02H 2 1 TCM RO R1 gt RO OC7H R1 02H register 02H 23H Z 0 TCM 00H 01H gt Register OOH 2BH register 01H 02H Z 1 TCM 0
13. High nibble pins P5 4 P5 7 SEG3 SEGO Port 5 Control Registers PSCONH PSCONL Port 5 has two 8 bit control registers for P5 4 P5 7 and PSCONL for P5 0 P5 3 A reset clears the P5CONH and P5CONL registers to configuring all pins to input mode You use control registers setting to select input or output mode Port 5 Control Register High Byte EBH Set 1 Bank 1 R W P5 7 SEGO P5 6 SEG1 P5 5 SEG2 P5 4 SEG3 P5CONH bit pair pin configuration settings Input mode Input with pull up resistor Push pull output mode Alternative function SEGO SEG3 Figure 9 21 Port 5 High Byte Control Register 5 Port 5 Control Register Low Byte PSCONL ECH Set 1 Bank 1 R W P5 3 SEG4 P5 2 SEG5 P5 1 SEG6 P5 0 SEG7 P5CONL bit pair pin configuration settings Input mode Input with pull up resistor Push pull output mode Alternative function SEG4 SEG7 Figure 9 22 Port 5 Low Byte Control Register PSCONL 9 16 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORTS PORT 6 Port 6 is a 4 bit I O port with bit pair configurable pins Port 6 pins are accessed directly by writing or reading the port 6 data register P6 at location F6H in set 1 bank 0 P6 0 P6 3 can serve as inputs with or without pull up as push pull outputs or you can be configured the following functions Low nibble pins P6 0 P6 3 0 Port 6 Control Reg
14. Watch timer for real time FLASH The S3F8275 F8278 F8274 are FLASH version of the S8C8275 C8278 C8274 microcontroller The S3F8275 F8278 F8274 microcontroller has an on chip FLASH ROM instead of a masked ROM The S3F8275 F8278 F8274 is comparable to the 53C8275 C8278 C8274 both in function and in pin configuration The 53 8275 only is a full flash The full flash means that data can be written into the program ROM by a instruction ELECTRONICS 1 1 PRODUCT OVERVIEW FEATURES CPU e SAM88RC CPU core Memory e Program Memory ROM 16K x8 bits program memory S3C8275 F8275 8Kx8 bits program memory S3C8278 F8278 4Kx8 bits program memory S3C8274 F8274 Internal flash memory Program memory v Sector size 128 Bytes v 10 Years data retention v Fast programming time Chip erase 16ms Sector erase 10ms Byte program 30us v User programmable by LDC instruction v Endurance 10 000 erase program cycles v Sector 128 bytes erase available v Byte programmable y External serial programming support v Expandable OBPTM On board program sector e Data Memory RAM Excluding LCD display data memory 512 x 8 bits data memory S3C8275 F8275 256 x 8 bits data memory S3C8278 F8278 256 x 8 bits data memory S3C8274 F8274 Instruction Set e 78 instructions e Idle and Stop instructions added for power down modes 52 I O Pins e 1 0 16 pins e 1 0 36 pins Sharing with LCD signal outputs Interrupts e 8 interrupt level
15. Compare CP dst src Operation dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Flags C Setif a borrow occurred src dst cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src opc dst 2 4 A2 r r SIC 6 A3 r Ir opc src dst 3 6 A4 R R 6 A5 R IR opc dst src 3 6 A6 R IM Examples 1 Given R1 02H and R2 OSH CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Because a borrow occurs and the difference is negative C and S are 1 2 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement CP R1 R2 generates 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 6 30 ELECTRONES 3C8275 F8275 C82
16. Timer B Control Register TBCON E7H Set 1 bank 1 R W Timer B clock selection bits 000 fxx 512 001 fxx 256 010 fxx 64 011 fxx 8 100 fxt sub clock Others Not available Timer B interrupt pending bits 0 No interrupt pending when read Clear pending bit when write 1 Interrupt is pending when read No effect when write Timer B match interrupt enable bit 0 Disable match interrupt 1 Enable match interrupt Timer B count enable bit 0 Disable counting operating 1 Enable counting operating Timer B counter clear bit 0 No effect 1 Clear the timer B counter when write Figure 11 4 Timer B Control Register TBCON ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec TIMER 1 0 6 4 XIN or XTIN Data Bus TACON 3 TACNT Clear 8 Bit Up Counter R TACON 1 Match 0 Match Signal TACLR TADATA Register Data Bus NOTE When two 8 bit timers mode TACON 7 lt 0 Timer A Figure 11 5 Timer A Block Diagram Two 8 bit Timers Mode ELECTRONICS 11 7 TIMER 1 3C8275 F8275C8278 F8278 C8274 F8274 Preliminary Spec 0 TBCON 6 4 XIN or XTIN Match Signal TBCLR TBDATA Register Data Bus NOTE When two 8 bit timers mode TACON 7 lt 0 Timer B Figure 11 6 Timer B Block Diagram Two 8 bit Timers Mode 11 8 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminar
17. BLDCON Battery Level Detector Control Register F4H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 Read Write R W R R W R W R W R W Addressing Mode Register addressing mode only 7 6 Not used for the S3C8275 C8278 C8274 5 Vin Source Bit source 1 External source Internal 4 Battery Level Detector Output Bit 0 Vin gt Vp when BLD is enabled Vin lt Vggr when BLD is enabled 3 Battery Level Detector Enable Disable Bit 0 Disable BLD Enable BLD 2 0 Detection Voltage Selection Bits BOGE oco Other values Not available ELECTRONICS 4 5 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BTCON Basic Timer Control Register D3H Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Watchdog Timer Function Disable Code for System Reset 1 0 1 0 Disable watchdog timer function Other values Enable watchdog timer function 3 2 Basic Timer Input Clock Selection Bits fxx 4096 3 1 fxx 1024 fxx 128 1 fxx 16 Basic Timer Counter Clear Bit 1 ET ES No effect 1 Clear the basic timer counter value 0 Clock Frequency Divider Clear Bit for Basic Timer and Timer Counters 2 No effect 1 Clear both clock frequency dividers NOTES 1 When you write a 1 to BTCON 1 the basic timer counter value is cleared to 00H Immediately following
18. COH C7H RP1 C8H CFH This 16 byte address range is called common area That is locations in this area can be used as working registers by operations that address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations between different pages Following a hardware reset register pointers RPO and RP1 point to the common working register area locations COH CFH LCD Data NOTE In case of S3C8278 C8274 there are page 0 and page 2 Page 2 is for LCD display register 16 bytes Figure 2 12 Common Working Register Area ELECTRONICS 2 17 ADDRESS SPACES 3C8275 F8275 C8278 F8278C8274 F8274 Preliminary Spec PROGRAMMING Addressing the Common Working Register Area As the following examples show you should access working registers in the common area locations COH CFH using working register addressing mode only Examples 1 LD 0C2H 40H Invalid addressing mode Use working register addressing instead SRP 0COH LD R2 40H R2 C2H the value in location 40H 2 ADD 0C3H 45H Invalid addressing mode Use working register addressing instead SRP 0COH ADD R3 45H R3 45H 4 BIT WORKING REGISTER ADDRESSING Each register pointer defines a movable 8 byte slice of working register space The address information stored in a register pointer serves as an addressing window that makes it possible for instructions to a
19. Chapter 12 Watch Timer ER mE 12 1 Watch Timer Control Register 12 2 Watch Timer Circuit euh iR Dr ae arte e 12 3 Chapter 13 LCD Controller Driver C PEDEM 13 1 LCD Circuit Diagram E EET 13 2 Ee BEST e 13 3 LCD Control Register LOGON IEEE 13 4 LCD Voltage Dividing Resistor neret nere Eure tied avd eid 13 5 Common COM Signals RT a bay thee ie 13 6 Segment SEG Sighals trei ctt t diee ett vss tees obese EE pre es ERE ee encre rape 13 6 Chapter 14 Serial I O Interface EP 14 1 Programming Procedure ina Seit e pete aides ge eee 14 1 SIO Control Registers SIOGCON uet aho reote eR E ona ek 14 2 SIO Pre Scaler Register SIO 14 3 SIO Block E 14 3 Serial 7O Timing Diagram SlO ssc5 eoi rb io deltas fig 14 4 Chapter 15 Battery Level Detector M Mmmm 15 1 Battery Level Detector Control Register BLDCON viii 3C8275 F8275 C8278 F8278 C8274 F8274 MICROCONTROLLER Table of Contents continued Chapter 16 Embedded Flash Memory Interface Overview Flash Memory Control Registers User Program Mode ISP On Board Programming Sector Sector Erase Chapter 17 Ele
20. When 12 5 V is supplied to the Vpp TEST pin of the S3C8275 C827 8 C8274 the Flash ROM programming mode is entered The operating mode read write or read protection is selected according to the input signals to the pins listed in Table 19 3 below Table 19 3 Operating Mode Selection Criteria Vu Vpp TEST REG MEM Address R W A15 A0 12 5 V 0000H 01 Flash ROM program 12 5V mE 0000H E Flash ROM verify 12 5V OESFH Flash ROM read protection NOTE 0 means Low level 1 means High level ELECTRONES 19 5 S3F8275 F8278 F8274 FLASH MCU 3C8275 F8275 C827 8 F8278 C8274 F8274 Preliminary Spec Unit Table 19 4 D C Hectrical Characteristics TA 25 to 85C 20V to 3 6V 1 Supply current 1 Ippi Run mode 8 0 MHz 3 0 Vpp233 V O3V Crystal oscillator 4 0 MHz 1 5 3 0 C1 C2 22pF lope 2 Idle mode 8 0 MHz 0 5 1 6 Vpp 33 V 03V Crystal oscillator 4 0 MHz 0 4 1 2 C1 C2 22pF Ippg Run mode 3 3 V 0 3V 32 kHz crystal oscillator TA 25 C OSCCON 7 1 3 Idle mode Vpp 3 3 V 0 3 V 32 kHz crystal oscillator Ta 25 C OSCCON 7 1 Ipps 4 Stop mode Vpp 3 3V peser 25 C 0 NOTES 1 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors the LVR block and external output current loads include power consumption for sub clock oscillation Ippg and Ipp4
21. 0 TM R0 R1 E RO 0C7H R1 02H register 02H 23H Z 0 TM 00H01H gt Register OOH 2BH register 01H 02H Z TM 00H 01H gt Register 00H 2BH register 01H 02H register 02H 23H Z 0 00H 54H gt Register OOH 2BH Z 1 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TM RO R1 tests bit in the destination register for a 0 value Because the mask value does not match the test bit the Z flag is cleared to logic zero and can be tested to determine the result of the TM operation ELECTRONS 6 85 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec WEI wait tor Interrupt WFI Operation Flags Format Example 6 86 The CPU is effectively halted until an interrupt occurs except that DMA transfers can still take place during this wait state The WFI status can be released by an internal interrupt including a fast interrupt No flags are affected Bytes Cycles Opcode Hex 1 4n 3F n 1 2 3 The following sample program structure shows the sequence of operations that follow a WFI statement Main program H Enable global interrupt Wait for interrupt Next instruction Interrupt occurs Interrupt service routine Clear interrupt flag IRET Service routine completed ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274
22. 02H DEC gt Register 03H OFH INSTRUCTION SET Addr Mode dst R IR In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value contained in the destination register by one leaving the value OFH ELECTRONS 6 35 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec DECW Decrement Word DECW dst Operation dst lt dst 1 The contents of the destination location which must be an even address and the operand following that location are treated as a single 16 bit value that is decremented by one Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 80 RR 81 IR Examples Given RO 12H R1 R2 register OFH and register 21H DECW RRO gt RO 12H R1 33H DECW R2 gt Register 30H OFH register 31H 20H In the first example destination register RO contains the value 12H and register R1 the value 34H The statement DECW RRO addresses RO and the following operand R1 as a 16 bit word and decrements the value of R1 by one leaving the va
23. 8274 Preliminary Spec NOTES 1 12 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES ADDRESS SPACES OVERVIEW The S3C8275 C8278 C8274 microcontroller has two types of address space Internal program memory ROM Internal register file A 16 bit address bus supports program memory operations A separate 8 bit register bus carries addres ses and data between the CPU and the register file The S3C8275 has an internal 16 Kbyte mask programmable ROM The S3C8278 has an internal 8 Kbyte mask programmable ROM S3C8274 has an internal 4 Kbyte mask programmable ROM The 256 byte physical register space is expanded into an addressable area of 320 bytes using addressing modes A 16 byte LCD display register file is implemented There are 605 mapped registers in the internal register file Of these 528 are for general purpose This number includes a 16 byte working register common area used as a scratch area for data operations two 192 byte prime register areas and two 64 byte areas Set 2 Thirteen 8 bit registers are used for the CPU and the system control and 48 registers are mapped for peripheral controls and data registers Nineteen register locations are not mapped ELECTRONICS 2 1 ADDRESS SPACES S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PROGRAM MEMORY ROM Program memory ROM stores program codes or table data The S3C8275 has 16K bytes internal mask
24. Clock Output Control Register 4 8 External Interrupt Control Register High 4 9 External Interrupt Control Register Low Byte 4 10 External Interrupt Pending 4 11 System Flags Register s coto etri 4 12 Flash Memory Control 4 13 Flash Memory Sector Address Register High Byte 444 Flash Memory Sector Address Register Low 444 Flash Memory User Programming Enable 445 Interrupt Mask 4 16 Instruction Pointer High Byte eee 4 17 Instruction Pointer Low Byte nnne 4 17 Interrupt Priority 4 18 Interrupt Request 4 19 LGDGonttrol Begister 4 20 Oscillator Control 4 21 Port 0 Control Register High Byte 4 22 Port 0 Control Register Low Byte 4 23 Port 0 Pull Up Control 4 24 Por
25. Mode Select CLK g Bit SIO Shift Buffer SIODATA E2H set 1 bank 0 SIOCON 6 LSB MSB First Mode Select Figure 14 3 SIO Functional Block Diagram ELECTRONS 14 3 SERIAL I O INTERFACE 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SERIAL 1 TIMING DIAGRAM SIO A O so Coon Joe SIO INT Transmit Complete 4 Set SIOCON 3 Figure 14 4 Serial I O Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 Transmit Complete Bor Set SIOCON 3 Figure 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BATTERY LEVEL DETECTOR BATTERY LEVEL DETECTOR OVERVIEW The S3C8275 C8278 C8274 micro controller has a built in BLD Battery Level Detector circuit which allows detection of power voltage drop or external input level through software Turning the BLD operation on and off can be controlled by software Because the IC consumes a large amount of current during BLD operation It is recommended that the BLD operation should be kept OFF unless it is necessary Also the BLD criteria voltage can be set by the software The criteria voltage can be set by matching to one of the 3 kinds of voltage below that can be used 2 2 V 2 4 V or 2 8 V V pp reference voltage or external input level External reference voltage
26. 1 N channel open drain output mode Push pull output mode 1 Not used for S3C8275 C8278 C8274 Schmitt trigger input mode N channel open drain output mode 0 Push pull output mode Not used for 53 8275 8278 8274 Schmitt trigger input mode N channel open drain output mode Push pull output mode Not used for S83C8275 C8278 C8274 ELECTRONICS 4 25 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec P1CONL Port 1 Contro Register Low Byte E8H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 3 INT3 Configuration Bits 0 0 Schmitt trigger input mode N channel open drain output mode EN Push pull output mode Not used for 53 8275 8278 8274 5 4 3 2 Schmitt trigger input mode N channel open drain output mode Push pull output mode 1 0 Schmitt trigger input mode SCK N channel open drain output mode Push pull output mode Alternative function SCK 4 26 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER P1PUR Por Pull up Control Register F9H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P1 7 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 6 P1 6 s Pull up Resistor Enable Bit Disable pull up resisto
27. 1 60 NOTE Dimensions in millimeters Figure 18 2 64 Pin LQFP Package Dimensions 64 LQFP 1010 18 2 ELECTRONES 53 8275 8275 8278 8278 8274 8274 Preliminary Spec S3F8275 F8278 F8274 FLASH MCU 53 8275 8278 8274 FLASH MCU OVERVIEW The S3F8275 F8278 F8274 single chip CMOS microcontroller is the Flash MCU version of the 3C8275 C8278 C8274 microcontroller It has an on chip Flash ROM instead of masked ROM The Flash ROM is accessed by serial data format The S3F8275 F8278 F8274 is fully compatible with the S8C8275 C8278 C8274 both in function and in pin configuration Because of its simple programming requirements the S3F8275 F8278 F8274 is ideal for use as an evaluation chip for the S8C8275 C8278 C8274 ELECTRONES 19 1 S3F8275 F8278 F8274 FLASH MCU 3C8275 F8275 C827 8 F8278 C8274 F8274 Preliminary Spec 63 FO SEG2 P5 5 62 SEG3 P5 4 61 E SEG4 P5 3 60 SEG5 P5 2 59 F3 SEG6 P5 1 58 3 SEG7 P5 0 57 SEG8 P4 7 56 3 5 9 4 6 55 SEG10 P4 5 54 Fo SEG11 P4 4 53 SEG12 P4 3 52 SEG13 P4 2 SEGO P5 7 COMO P6 0 COM1 P6 1 COM2 P6 2 COM3 P6 3 VLCO SDAT VLC1 SCLK VLC2 VDD V DD SEG14 P4 1 SEG15 P4 0 SEG16 P3 7 SEG17 P3 6 SEG18 P3 5 SEG19 P3 4 S3F8275 SEG20 P3 3 SEG21 P3 2 53 8278 SEG22 P3 1 Vss Vss S3F8274 SEG23 P3 0 XOUT SEG24 P2 7 XIN 2 4 SEG25 P2 6 VPP TEST 64 QFP 1420F SEG26 P2 5 XTIN SEG27 P2 4 XTOUT S
28. Address Register High Byte indicates the high byte of sector address The FMSECH is needed for S3F8275 because it has 128 sectors respectively One sector consist of 128 bytes Each sector s address starts XX00H or XX80H that is a base address of sector is XX00H or XX80H So FMSECL register 6 0 don t mean whether the value is 1 or 0 We recommend that the simplest way is to load sector base address into FMSECH and FMSECL register When programming the flash memory you should write data after loading sector base address located in the target address to write data into FMSECH and FMSECL register If the next operation is also to write data you should check whether next address is located in the same sector or not It case of other sectors you must load sector address to FMSECH and FMSECL register according to the sector Flash Memory Sector Address Register High Byte FMSECH F2H Set 1 Bank 1 R W Flash Memory Sector Address High Byte NOTE High byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 16 3 Flash Memory Sector Address Register High Byte FMSECH Flash Memory Sector Address Register Low Byte FMSECL F3H Set 1 Bank 1 R W Flash memory sector address Low Byte Don t Care NOTE The Low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Figure 16 4 Flash Memory Sector Address Register L
29. Disable Erasable by LDC 10 500H ISP area size 1024 byte 11 900H ISP area size 2048 byte ROM Address 003FH These bits should be LVR Enable Disable Bit always logic 110b Criteria Voltage 2 2V 0 Disable LVR 0 Enable LVR ROM Address 003CH Not used ROM Address 003DH Not used NOTE After selecting ISP reset vector address in selecting ISP protection size don t select upper than ISP area size Figure 2 2 Smart Option ELECTRONICS ADDRESS SPACES S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Smart option is the ROM option for start condition of the chip The ROM address used by smart option is from 003CH to 003FH The ISP of smart option 003EH is available in the S3F8275 only The default value of ROM address 003EH is FFH And ROM address 003EH should be kept FFH when used the S3C8275 F8275 C8278 F8278 C8274 F8274 LVR of smart option 003FH is available in all the device S3C8275 F8275 C8278 F8278 C8274 F8274 The default value of ROM address 003FH is FFH 2 4 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES REGISTER ARCHITECTURE In the S8C8275 C8278 C8274 implementation the upper 64 byte area of register files is expanded two 64 byte areas called set 7 and set 2 The upper 32 byte area of set 1 is further expanded two 32 byte register banks bank 0 and bank 1 and the lower 32 byte area is a single 32 byte common area In case of
30. Later you can reference the information in Part as necessary Part Il hardware Descriptions has detailed information about specific hardware components of the S3C8275 F8275 C8278 F8278 C8274 F8274 microcontroller Also included in Part Il are electrical mechanical Flash MCU and development tools data It has 14 chapters Chapter 7 Clock Circuit Chapter 14 Serial I O Interface Chapter 8 RESET and Power Down Chapter 15 Battery Level Detector Chapter 9 Ports Chapter 16 Embedded Flash Memory Interface Chapter 10 Basic Timer Chapter 17 Electrical Data Chapter 11 Timer 1 Chapter 18 Mechanical Data Chapter 12 Watch Timer Chapter 19 S3F8275 F8278 F8274 Flash MCU Chapter 13 LCD Controller Driver Chapter 20 Development Tools Two order forms are included at the back of this manual to facilitate customer order for 3C8275 F8275 C8278 F8278 C8274 F8274 microcontrollers the Mask ROM Order Form and the Mask Option Selection Form You can photocopy these forms fill them out and then forward them to your local Samsung Sales Representative 3C8275 F8275 C8278 F8278 C8274 F8274 MICROCONTROLLER iii Table of Contents Part Programming Model Chapter 1 Product Overview S93G8 Series Microcontrollers 22 Ue Ge El e ag e Sr eei EHE up yee 1 1 3C8275 F8275 C8278 F8278 C8274 F8274 1 1 Eti xL 1 1 arum
31. Main oscillator control bit 0 Main oscillator RUN 1 Main oscillator STOP NOTE Acapacitor 0 1uF should e connected between VREG and GND when the sub oscillator is used to power saving mode OSCCON 7 1 Figure 7 11 Oscillator Control Register OSCCON 7 6 ELECTRONICS 3C8275 C8278 C8274 F8275 F8278 F8274 Preliminary Spec CLOCK CIRCUIT SWITCHING THE CPU CLOCK Data loading in the oscillator control register OSCCON determine whether a main or a sub clock is selected as the CPU clock and also how this frequency is to be divided by setting CLKCON This makes it possible to switch dynamically between main and sub clocks and to modify operating frequencies 5 0 select the main clock fx or the sub clock fxt for the CPU clock OSCCON 3 start or stop main clock oscillation and OSCCON 2 start or stop sub clock oscillation CLKCON 4 control the frequency divider circuit and divide the selected fxx clock by 1 2 8 16 For example you are using the default CPU clock normal operating mode and a main clock of fx 16 and you want to switch from the fx clock to a sub clock and to stop the main clock To do this you need to set CLKCON 4 3 to 11 OSCCON O0 to 1 and OSCCON 3 to 1 simultaneously This switches the clock from fx to fxt and stops main clock oscillation The following steps must be taken to switch from a sub clock to the main clock first set OSCCON 3 to 0 to enable main clock oscil
32. PIN ASSIGNMENT 63 SEG2 P5 5 62 r3 SEG3 P5 4 61 SEG4 P5 3 60 SEG5 P5 2 59 L3 SEG6 P5 1 58 SEG7 P5 0 57 L3 SEG8 P4 7 56 5 SEG9 P4 6 55 SEG10 P4 5 54 3 SEG11 P4 4 53 SEG12 P4 3 52 L3 SEG13 P4 2 SEGO P5 7 1 C SEG14 P4 1 COMO P6 0 2 SEG15 P4 0 COM1 P6 1 3 SEG16 P3 7 COM2 P6 2 4 SEG17 P3 6 COM3 P6 3 5 SEG18 P3 5 VLCO 6 4 SEG19 P3 4 VLC1 7 S3C8275 F8275 SEG20 P3 3 VLC2 8 4 SEG21 P3 2 vo 8278 8278 SEG22 P3 1 Vss 10 S3C8274 F8274 SEG23 P3 0 XOUT 11 4 SEG24 P2 7 XIN 12 SEG25 P2 6 TEST 64 QFP 1420F SEG26 P2 5 XTIN SEG27 P2 4 XTOUT SEG28 P2 3 nRESET SEG29 P2 2 VREG SEG30 P2 1 PO O INTO SEG31 P2 0 VBLDREF PO 1 INT1 P1 7 INT7 PO 2 INT2 C 20 0 3 21 PO 4 TAOUT 22 5 23 6 C4 24 P0 7 BUZ C 25 P1 0 SCK C 26 P1 1 50 27 1 2 5 28 P1 3 INT3 29 P1 4 INT4 C 30 P1 5 INT5 31 P1 6 INT6 32 Figure 1 2 S3C8275 F8275 C8278 F8278 C8274 F8274 Pin Assignments 64 QFP 1420F 1 4 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PRODUCT OVERVIEW 63 SEG2 P5 5 62 SEG3 P5 4 61 SEG4 P5 3 60 SEG5 P52 59 L3 SEG6 P5 1 58 SEG7 P5 0 57 3 SEG8 P4 7 56 SEG9 P4 6 55 SEG10 P4 5 54 E3 SEG11 P4 4 53 L3 SEG12 P4 3 52 L3 SEG13 P4 2 51 SEG14 P4 1 50 L3 SEG15 P4 0 49 SEG16 P3 7 SEGO P5 7 COMO P6 0 COM1 P6 1 COM2 P
33. Port control register ow byt acon zx een fofo oTo Port pull up resistor enable register P3PUR 29 0 0 0 0 Pono aaa regster Porras m FM Ponza regse 4 f Pa oa o o o o o Pon Sdaarcssee o o o o o o EE EE SS FExtemalinterupt pending register EXTPND 27 fo External interrupt control register high byte EXTICONH External interrupt control register low byte cana Location FAH is not mapped STOP control register STPCON 251 0 0 0 0 0 0 0 Location FCH is not mapped Basic timer counter BTCNT 2 FH o ojo o ojo ojo Location FEH is not mapped Interrupt priority register PR x Ix x x x x x x ELECTRONICS 8 3 RESET and POWER DOWN 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 8 3 S3C8275 C8278 C8274 Set 1 Bank 1 Register Values After RESET Register Name Address Bit Values After RESET usce won zs em oo ofa ae ee Timer Acounter TANT 226 ezn o Timer B counter CNT 227 E3H O Timer convo regse esee ne To 8280000000 Seek pupal contol NNNM E EN eseon P
34. Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 6 Condition Codes 0000 F Always false 1000 Always true 0111 note Carry 1111 note No carry 0110 note Zero 1110 note Not zero 1101 Plus 0101 Minus 0100 Overflow 1100 No overflow 0110 note Equal C C Z Z S S V V Z Z 1110 note Not equal 1001 Greater than or equal 0001 Less than 1010 Greater than 0010 Less than or equal 1111 note Unsigned greater than or equal 0 0111 note Unsigned less than C 1 1011 Unsigned greater than C20 AND Z 0 1 0011 Unsigned less than or equal C OR Z 1 NOTES 1 It indicates condition codes that are related to two different mnemonics but which test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z would probably be used after a CP instruction however EQ would probably be used 2 For operations involving unsigned numbers the special condition codes UGE ULT and ULE must be used 6 12 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET INSTRUCTION DESCRIPTIONS This section contains detailed information and programming examples for each instruction in the SAMB8 instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information
35. gt LD 00H 02H LD RO LOOP R1 gt LD 4LOOP RO R gt 6 50 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec OAH register OOH 01H register 01H 20H and register RO 10H RO 20H register 01H 20H Register 01H 01H RO 01H R1 20H RO 01H RO 01H R1 OAH register 01H OAH Register OOH 20H register 01H 20H Register 02H 20H register 00H 01H Register OOH OAH Register OOH O1H register 01H 10H Register OOH 01H register 01H 02 register 02H 02H RO OFFH R1 OAH Register 31H OAH RO 01H R1 OAH ll ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET LDB Load Bit LDB LDB Operation Flags Format Examples dst src b dst b src dst 0 lt src b or dst b lt src 0 The specified bit of the source is loaded into bit zero LSB of the destination or bit zero of the source is loaded into the specified bit of the destination No other bits of the destination are affected The source is unaffected No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst b 0 src 3 6 47 ro Rb opc dst 3 6 47 Rb NOTE second byte of the instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given RO O6H and general register OOH O5
36. 1F Example The diagram below shows one example of how to use an ENTER statement Before After Address Data IP Address Address Data PC 40 Enter PC 40 Enter 41 Address H 42 Address L 43 Address H 41 Address H 42 Address L 43 Address SP 20 110 Routine 21 22 Data 22 Memory Stack Stack ELECTRONES 6 41 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec EXIT exit EXIT Operation IP lt SP SP lt SP 2 IP IP lt IP 2 This instruction is useful when implementing threaded code languages The stack value is popped and loaded into the instruction pointer The program memory word that is pointed to by the instruction pointer is then loaded into the program counter and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14 internal stack 2F 16 internal stack Example The diagram below shows one example of how to use an EXIT statement Before After Address Data Address Data Address Data Address Data s 50 PCL old 60 60 Main 51 PCH 00 140 Exit 2F 20 21 50 22 Data Memory 22 Data Memory Stack Stack 6 42 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET IDLE Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt r
37. 1H RO 7FH R6 22H R7 OOH LDEPI RR6 RO RR6 lt RR6 1 TFH contents of RO is loaded into external data memory location 2200H 21FFH 1H RO R6 22H 7 OOH ELECTRONES 6 57 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LDW Load Word LDW dst src Operation dst lt src The contents of the source a word are loaded into the destination The contents of the source are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 C4 RR RR C5 RR IR opc dst src 4 8 C6 RR IML Examples Given R4 06H R5 1CH R6 05H R7 02H register OOH 1AH register 01H 02H register 02H 03H and register 03H OFH LDW RR6 RR4 gt R6 06H R7 1CH R4 06H R5 1CH LDW 00H 02H gt Register OOH register 01H OFH register 02H register LDW RR2 R7 gt R2 03H R3 OFH LDW 04H 01H gt Register 04H register OFH LDW RR6 1234H gt R6 12H R7 34H LDW 02H 0FEDH gt Register 02H OFH register 03 OEDH In the second example please note that the statement LDW 00H 02H loads the contents of the source word 02H 03H into the destination word 00H 01H This leaves the value 03H in general register OOH and the value OFH in register 01H The other examples show how to use the LDW instruction with various addressing modes and formats 6 58 ELEC
38. 5 0 EXTIPND 2 0 To process external interrupts at the port 0 pins two additional control registers are provided the port 0 interrupt control register EXTICONL F9H set 1 bank 0 the port 0 interrupt pending bits EXTI PND 2 0 F7H set 1 bank 0 The poet 0 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the EXTIPND 2 0 register at regular intervals When the interrupt enable bit of any port 0 pin is 1 a rising or falling edge at that pin will generate an interrupt request The corresponding EXTIPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a to the corresponding EXTIPND bit ELECTRONICS 9 3 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Port 0 Control Register High Byte POCONH E4H Set 1 Bank 0 R W alls 7 BUZ os bor 5 TBOUT P0 6 CLKOUT P0 4 TAOUT POCONH bit pair pin configuration settings Schmitt trigger input mode N channel open drain output mode Push pull output mode Alternative function BUZ CLKOUT TBOUT TAOUT 9 4 Figure 9 2 Port 0 High Byte Control Register POCONH Port 0 Control Register Low
39. 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER xiii List of Figures Concluded Page Title Page Number Number 17 1 Stop Mode Release Timing When Initiated by an External Interrupt 17 5 17 2 Stop Mode Release Timing When Initiated by 17 6 17 3 Input Timing for External 17 7 17 4 Input Timing for RESET esc t ete tree ERE epit eee e ORE rr end ret dun 17 8 17 5 Serial Data Transfer 17 8 17 6 LVR Low Voltage Reset 0 000 17 9 17 7 Clock Timing Measurement at emn 17 11 17 8 Clock Timing Measurement at HH 17 12 17 9 Operating Voltage nnne nennen nnne 17 13 18 1 64 Pin QFP Package Dimensions 64 1420 18 1 182 64 Pin LQFP Package Dimensions 64 1010 18 2 19 1 S3F8275 F8278 F8274 Pin Assignments 64 1420 19 2 19 2 S3F8275 F8278 F8274 Pin Assignments 64 1010 19 3 19 8 Operating Voltage 19 7 20 1 SMDS Product Configuration SMDS2 esee 20 2 20 2 TB8275 8 4 Target Board
40. 8 1 Hardware Reset Lp L tae 8 2 6 TE T EEA 8 5 510 ETE 8 5 lde MOG pL 8 6 Chapter 9 Ports eee elie GU eee es ee 9 1 Port Data REGISTE Sien nut Quse ca RE 9 2 9 3 POU EE M M EE 9 7 re ER De east ted iets aetna elt dc tee rud Ae Reed 9 11 pc EE 9 13 e EE 9 15 rcc M 9 16 db 9 17 Chapter 10 Basic Timer I E 10 1 Basic Timer Control Register 10 2 Basic Timer Function 10 3 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER vii Table of Contents continued Chapter 11 Timer 1 One 16 Bit Timer Mode Timer 1 OVOIVIGW e e Rei ctepd decer adhi ti 11 1 Function Descriptions 2 rere ee ier Duce oaa Cree 11 1 Two 8 Bit Timers Mode Timer A 11 4 OVOILVIOW3 tute Bet ear otc eee ero senec ad ie rue 11 4 F nctlomDesecriptiorz s i acte tote 11 4
41. 8 bit value to concatenate the full 16 bit address and the service routine is executed Levels Vectors Sources Reset Clear RESET 100H Basic timer overflow HAN FOH Timer 1 A match S W IRQO F2H Timer B match S W IRQ1 810 interrupt SN 2 F6H Watch timer overflow P0 0 external interrupt IRQ4 E2H external interrupt IRQ5 P0 2 external interrupt IRQ6 P1 3 external interrupt E8H P1 4 external interrupt P1 5 external interrupt ECH P1 6 external interrupt P1 7 external interrupt NOTES 1 Within a given interrupt level the low vector address has high priority For example FOH has higher priority than F2H within the level IRQ 0 the priorities within each level are set at the factory 2 External interrupts are triggered by a rising or falling edge depending on the corresponding control register setting Figure 5 2 S3C8275 C8278 C8274 Interrupt Structure ELECTRONICS 5 3 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec INTERRUPT VECTOR ADDRESSES All interrupt vector addresses for the S3C8275 C8278 C8274 interrupt
42. 80H 83H C ADC 80H 84H 80H lt 80H 84H C ADC 80H 85H lt 80H 85H C Now the sum of the six registers is also located in register 80H However this instruction string takes 15 bytes of instruction code rather than 12 bytes and its execution time is 50 cycles rather than 36 cycles 2 14 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES REGISTER ADDRESSING The S3C8 series register architecture provides an efficient method of working register addressing that takes full advantage of shorter instruction formats to reduce execution time With Register R addressing mode in which the operand value is the content of a specific register or register pair you can access any location in the register file except for set 2 With working register addressing you use a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space Registers are addressed either as a single 8 bit register or as a paired 16 bit register space In a 16 bit register pair the address of the first 8 bit register is always an even number and the address of the next register is always an odd number The most significant byte of the 16 bit data is always stored in the even numbered register and the least significant byte is always stored in the next 1 odd numbered register Working register addressing differs from Register addressing as it uses a r
43. Byte POCONL E5H Set 1 Bank 0 R W PO S TICLK PO 2 INT2 1 PO 0 INTO POCONL bit pair pin configuration settings Schmitt trigger input mode T1CLK N channel open drain output mode Push pull output mode Not available Figure 9 3 Port 0 Low Byte Control Register POCONL ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORTS Port 0 Pull up Control Register POPUR E6H Set 1 Bank 0 R W 0 7 PO 6 P0 5 PO 4 02 01 0 0 POPUR bit configuration settings 0 Disable pull up resistor 1 Enable pull up resistor NOTE pull up resistor of port 0 is automatically disabled when the corresponding pin is selected as push pull output or alternative function Figure 9 4 Port 0 Pull up Control Register POPUR External Interrupt Control Register Low Byte EXTICONL E9H Set 1 Bank 0 R W P1 3 INT3 PO 2 INT2 P0 1 INT1 PO 0 INTO EXTICONL bit configuration settings Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9 5 External Interrupt Control Register Low Byte EXTICONL ELECTRONICS 9 5 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec External Interrupt Pending Register EXTIPND F7H Set 1 Bank 0 R W P1 7 P1 6 P1 5 P1 4 P1 3 02 P01 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO EXTIPND bit configuration sett
44. Byte Control Register P1CONH Port 1 Control Register Low Byte P1CONL E8H Set 1 Bank 0 R W P1 3 INT3 P1 2 SI P1 1 SO P1 0 SCK P1CONL bit pair pin configuration settings Schmitt trigger input mode SI SCK N channel open drain output mode Push pull output mode Alternative function SCK SO 9 8 Figure 9 8 Port 1 Low Byte Control Register P1 CONL ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec PORTS Port 1 Pull up Control Register P1PUR E9H Set 1 Bank 0 R W P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 0 P1PUR bit configuration settings 0 Disable pull up resistor 1 Enable pull up resistor A pull up resistor of port 1 is automatically disabled when the corresponding pin is selected as push pull output or alternative function Figure 9 9 Port 1 Pull up Control Register P1PUR External Interrupt Control Register High Byte EXTICONH F8H Set 1 Bank 0 R W P1 7 INT7 1 6 6 P1 5 INT5 P1 4 INT4 EXTICONH bit configuration settings Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9 10 External Interrupt Control Register High Byte EXTICONH ELECTRONICS 9 9 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec External Interrupt Control Register Low Byte EXTICONL F9H Set 1 Bank 0 R W P1 3 INT3 2 1 2 P0 1 INT1 PO 0 INTO
45. CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec IPR Interrupt Priority Register FFH Set 1 Bank 0 Reset Value X X X X X X x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 and 1 Priority Control Bits for Interrupt Groups A B and C note 6 Interrupt Subgroup C Priority Control Bit 0 IRQ6 gt IRQ7 IRQ7 gt IRQ6 5 Interrupt Group C Priority Control Bit IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQS 3 Interrupt Subgroup B Priority Control Bit IRQ3 gt IRQ4 IRQ4 gt IRQS pg 2 Interrupt Group Priority Control 0 IRQ2 gt IRQ3 IRQ4 IRQ4 gt IRQ2 0 Interrupt Group A Priority Control Bit IRQO gt IRQ1 IRQ1 gt IRQO NOTE Interrupt Group A IRQO IRQ1 Interrupt Group B IRQ2 IRQ3 IRQ4 Interrupt Group C IRQS IRQ6 IRQ7 BE 4 18 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER IRQ Interrupt Request Register DCH Set 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R R R R Addressing Mode Register addressing mode only 7 Level 7 IRQ7 Request Pending External Interrupt P1 4 1 7 Not pending Pending le 6 Lev 6 IRQ6 Request Pending Bit External Interrupt P1 3 Not pending le Pending 5 Level 5 IRQ5 Request Pending Bit External Interrupt P0 2 Not pending Pending 4 Level 4 IRQ4 Request Pending Bit Ex
46. Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the S3C8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3C8275 F8275 C8278 F8278 C8274 F 8274 interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3C8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program A basic familiarity with the information in Part will help you to understand the hardware module descriptions in Part Il If you are not yet familiar with the S8C8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters 4 5 and 6
47. Control m mene nennen there nnns 5 7 Peripheral Interrupt Control Registers 5 8 System Mode Register 5 9 Interrupt Mask Register IMR e a a aE 5 10 Interrupt Priority Register 5 11 Interrupt Request Register 1 1 5 13 Interrupt Pending Function 5 14 Interrupt Source Polling 5 15 Interrupt Service Routiries Dee Ld ch a iu Ye YR UE Pe Ede 5 15 Generating Interrupt Vector Addresses 5 16 Nesting of Vectored Interr pts eto Hen C cepere PE DI E peres 5 16 Instruction Pointer ad IP ERE EIU H w 5 16 East Interr pt Processing de s Co ed areae i aped t er teda ev odas es obe eb Zebedees 5 16 Chapter 6 Instruction Set OVENVIOW pe 6 1 6 1 Register Address ING fest eerte tpa ese danas en ty epee a eerie ae 6 1 Addressing Modes tb pr sausages EROR HR S ARI ER MUR MIRA OR Mate ex EHI 6 1 Flags Register FLAGS cscs scene t aii reine oO eil devo e eT henner be
48. F8275 C8278 F8278 C8274 F8274 Preliminary Spec SB1 Select Bank 1 SB1 Operation BANK lt 1 SB1 instruction sets the bank address flag in the FLAGS register FLAGS 0 to logic one selecting bank 1 register addressing in the set 1 area of the register file Bank 1 is not implemented in some S3C8 series microcontrollers Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 5F Example The statement SB1 sets FLAGS 0 to 1 selecting bank 1 register addressing if implemented 6 76 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET SBC subtract with Carry SBC dst src Operation dst dst src c The source operand along with the current value of the carry flag is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operands Flags C Set if a borrow occurred src gt dst cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite sign and the sign of th
49. INSTRUCTION SET DJNZ Decrement and Jump if Non Zero DJNZ Operation Flags Format Example r dst 1 f r z0 PC dst The working register being used as a counter is decremented If the contents of the register are not logic zero after decrementing the relative address is added to the program counter and control passes to the statement whose address is now in the PC The range of the relative address is 127 to 128 and the original value of the PC is taken to be the address of the instruction byte following the DJNZ statement NOTE case of using DJNZ instruction the working register being used as a counter should be set at the one of location to OCFH with SRP SRPO or SRP1 instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst r opc dst 2 8 jump taken rA RA 8 no jump r OtoF Given R1 02H and LOOP is the label of a relative address SRP DJNZ R1 LOOP DJNZ is typically used to control a loop of instructions In many cases a label is used as the destination operand instead of a numeric relative address value In the example working register R1 contains the value 02H and LOOP is the label for a relative address The statement DJNZ R1 LOOP decrements register R1 by one leaving the value 01H Because the contents of R1 after the decrement are non zero the jump is taken to the relative address specified by the LOOP label ELECT
50. Measurement Using a Main or Sub Clock Source Main clock divided by 2 fx 128 or Sub clock fxt Clock Source Generation for LCD Controller f pin for Buzzer Output Frequency Generator P 0 7 BUZ Timing Tests in High Speed Mode Watch timer overflow interrupt IRQ 2 vector F6H generation Watch timer control register WTCON set 1 bank 1 E1H read write ELECTRONICS 12 1 WATCH TIMER 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec WATCH TIMER CONTROL REGISTER WTCON The watch timer control register WTCON is used to select the input clock source the watch timer interrupt time and Buzzer signal to enable or disable the watch timer function It is located in set 1 bank 1 at address E1H and is read write addressable using register addressing mode A reset clears WTCON to OOH This disable the watch timer and select fx 128 as the watch timer clock So if you want to use the watch timer you must write appropriate value to WTCON Watch Timer Control Register WTCON E1H Set 1 Bank 1 R W Watch timer clock selection bit Watch timer interrupt pending bits 0 Main clock divided by 0 No interrupt pending when read 27 fx 128 Clear pending bit when write 1 Sub clock fxt 1 Interrupt is pending when read No effect when write Watch timer INT Enable Disable bit Watch timer Enable Disable bit 0 Disable watch timer INT 0 Disable watch timer 1 Enable watc
51. No Select Signal in 1 2 Duty 1 2 Bias Display 13 7 13 8 Select No Select Signal 1 3 Duty 1 3 Bias Display 13 7 13 9 LCD Signals and Wave Forms Example in 1 4 Duty 1 3 Bias Display Mode 13 8 14 1 Serial I O Module Control Register 14 2 142 SIO Prescaler Register 14 3 143 SIO Functional Block 14 3 14 4 Serial Timing in Transmit Receive Mode Tx at falling SIOCON 4 0 14 4 14 5 Serial I O Timing in Transmit Receive Mode Tx at rising SIOCON 4 1 14 4 15 1 Block Diagram for Voltage Level 15 1 152 Battery Level Detect Circuit and Control 15 2 16 1 Flash Memory Control Register 16 2 16 2 Flash Memory User Programming Enable Register 16 3 16 3 Flash Memory Sector Address Register High Byte FMSECH 16 4 16 4 Flash Memory Sector Address Register Low Byte 16 4 16 5 Program Memory Address 16 5 16 6 Sector Configurations in User Program 16 7
52. Preliminary Spec INSTRUCTION SET XOR Logical Exclusive OR XOR Operation Flags Format Examples dst src dst lt dst src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a bit is stored C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 B3 r Ir opc src dst 3 6 B4 R R 6 B5 R IR opc dst src 3 6 B6 R IM Given RO OC7H R1 02H R2 register OOH 2BH register 01H 02H and register 02H 23H XOR RO R1 gt RO OC5H R1 02H XOR RO R1 gt RO 0E4H R1 02H register 02H 23H XOR 00H 01H gt Register OOH 29H register 01H 02H XOR 00H 01H gt Register OOH 08H register 01H 02H register 02H 23H XOR 00H 54H gt Register OOH 7FH In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement 1 logically exclusive ORs the R1 value with the RO value and stores the result OC5H in the destination register RO ELECTRONS 6 87 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NOTES 6 88 ELECTR
53. R W R W R W Addressing Mode Register addressing only 7 3 Register Pointer 1 Address Value Register pointer 1 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RP1 points to address C8H in register set 1 selecting the 8 byte working register slice C8H CFH 2 0 Not used for the S3C8275 C8278 C8274 4 40 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER SIOCON SIO Control Register E1H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 SIO Shift Clock Selection Bit Internal clock P S clock 1 External clock SCK 6 Data Direction Control Bit MSB first mode 1 LSB first mode 5 SIO Mode Selection Bit Receive only mode 1 Transmit receive mode 4 Shift Clock Edge Selection Bit 0 1 Tx at falling edges Rx at rising edges Tx at rising edges Rx at falling edges 13 SIO Counter Clear and Shift Start Bit 0 No action 1 Clear 3 bit counter and start shifting 2 SIO Shift Operation Enable Bit Disable shifter and clock counter Enable shifter and clock counter 1 SIO Interrupt Enable Bit Disable SIO interrupt 1 Enable SIO interrupt 0 SIO Interrupt Pending Bit No interrupt pending w
54. RL Rotate Left RL Operation dst C c dst 7 dst 0 dst 7 dst n 1 lt dst n 0 6 The contents of the destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position and also replaces the carry flag Flags Format Examples C Setif the bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst Opc dst 2 4 90 R 91 IR Given Register OOH OAAH register 01H 02H and register 02H 17H RL 00H gt Register OOH 55H 1 RL 01H gt Register 01H 02H register 02H 2 C 0 In the first example if general register 00H contains the value OAAH 10101010B the statement RL OOH rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags ELECTRONS 6 71 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RLC Rotate Left Through Carry RLC dst Operation dst 0 C dst 7 dst n 1 lt dst n n 06 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of the car
55. Register Low Byte 9 5 9 6 External Interrupt Pending Register EXTIPND eee 9 6 9 7 Port 1 High Byte Control Register 9 8 9 8 Port 1 Low Byte Control Register 9 8 9 9 Port 1 Pull up Control Register 9 9 9 10 External Interrupt Control Register High Byte 9 9 9 11 External Interrupt Control Register Low Byte 9 10 9 12 External Interrupt Pending Register EXTIPND seem 9 10 9 13 Port 2 High byte Control Register 2 9 11 9 14 Port 2 Low byte Control Register 2 9 12 9 15 Port 2 Pull up Control Register 9 12 9 16 Port High Byte Control Register 9 13 9 17 Port Low Byte Control Register 9 14 9 18 Port Pull up Control Register 9 14 xii 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER List of Figures continued Page Title Page Number Number 9 19 Port 4 High Byte Control Register PACONH 9 15 9 20 Port 4 Low Byte Control Registe
56. Target Board Configuration ELECTRONES 20 3 DEVELOPMENT TOOLS To User Vcc Settings To User V cc To User V cc S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 20 1 Power Selection Settings for TB 8275 8 4 Operating Mode TB8275 TB8278 TB8274 TB8275 TB8278 External TB8274 Voc gt Vss gt Comments The SMDS2 SMDS2 supplies Vac to the target board evaluation chip and the target system The SMDS2 SMDS2 supplies Voc only to the target board evaluation chip The target system must have its own power supply NOTE The following symbol in the To User_Vcc Setting column indicates the electrical short off configuration 9 of Main Clock Settings XTAL MDS 20 4 Table 20 2 Main clock Selection Settings for 8275 8 4 Operating Mode EVA Chip S3E8270 P4 XOUT XIN L No Connection 100 Pin Connector SMDS2 SMDS2 EVA Chip 53 8270 XOUT XIN XTAL Target Board Commenis Set the XI switch to MDS when the target board is connected to the SMDS2 SMDS2 Set the XI switch to XTAL when the target board is used as a standalone unit and is not connected to the SMDS2 SMDS2 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Spec DEVELOPMENT TOOLS Table 20 3 Select Smart Option Source Setting for TB8275 8 4 Smart Option Source Operating Mode Comments Selection Settings The S
57. V Symbol Conditions Typ 3 Supply current 1 2 Run mode 8 0 MHz 0 Vpp 33 0 3 V Crystal oscillator 4 0 MHz 1 5 C1 C2 22pF Idle mode 8 0 MHz Vp 3 3 V 0 3 V Crystal oscillator 4 0 MHz 0 4 C1 C2 22pF Run mode Vpp 3 3 V 0 3 V 12 0 32 kHz crystal oscillator Ta 25 C OSCCON 7 1 Idle mode Vpp 3 3 V 0 3 V 32 kHz crystal oscillator Ta 25 C OSCCON 7 1 Stop mode Vpp 3 3 V pw 25 ul Ipp3 are current when main clock oscillation stops and the sub clock is used OSCCON 7 1 Ipps is current when main clock and sub clock oscillation stops Every values in this table is measured when bits 4 3 of the system clock control register CLKCON 4 3 is set to 11B 17 4 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec ELECTRICAL DATA Table 17 3 Data Retention Supply Voltage in Stop Mode TA 257 to 85 C Symbol Data retention supply VDDDR voltage Data retention supply Stop mode 25 C rrent Idle Mode Basic Timer Active Stop Mode gt Normal lt Data Retention Mode gt Operating Mode Execution of STOP Instruction NOTE twAIT is the same as 16 x 1 BT clock Figure 17 1 Stop Mode Release Timing When Initiated by an External Interrupt ELECTRONICS 17 5 ELECTRICAL DATA 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Oscillation S
58. and improved version of SMDS2 Samsung also offers support software that includes debugger assembler and a program for setting options SHINE Samsung Host Interface for In Circuit Emulator SHINE is a multi window based debugger for SMDS2 SHINE provides pull down and pop up menus mouse support function hot keys and context sensitive hyperJinked help It has an advanced multiple windowed user interface that emphasizes ease of use Each window can be sized moved scrolled highlighted added or removed completely SAMA ASSEMBLER The Samsung Arrangeable Microcontroller SAM Assembler SAMA is a universal assembler and generates object code in standard hexadecimal format Assembled program code includes the object code that is used for ROM data and required SMDS program control data To assemble programs SAMA requires a source file and an auxiliary definition DEF file with device specific information SASM88 The 5 5 88 is a relocatable assembler for Samsung s S3C8 series microcontrollers The SASM88 takes a source file containing assembly language statements and translatesinto a corresponding source code object code and comments The SASM88 supports macros and conditional assembly It runs on the MS DOS operating system It produces the relocatable object code only so the user should link object file Object files can be linked with other object files and loaded into memory HEX2ROM HEX2ROM file generates ROM code from H
59. and one 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes ELECTRONICS 2 5 ADDRESS SPACES S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Bank 0 Page 0 System and Set 2 Peripheral Control Registers General Purpose Register Addressing Mode Data Registers Indirect Register Indexed Mode and Stack Operations System Registers Register Addressing Mode General Purpose Register Register Addressing Mode Page 0 Page 2 Prime Prime Data Registers 16 Data Registers All Addressing Modes Bytes All addressing modes LCD Display Reigster 00H Figure 2 3 Internal Register File Organization S3C8275 2 6 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES Set1 Bank 0 System and Peripheral Control Registers Register Addressing Mode System Registers Register Addressing Mode General Purpose Register Register Addressing Mode Page 2 OFH D ome 16 Data Registers All addressing modes 00H NOTE FFH Page 0 Set 2 EOH General Purpose Data Registers Indirect Register Indexed Mode and Stack Operations COH 256 BFH Bytes Page 0 192 Prime Bytes Data Registers All Addressing Modes In case of S3C8278 C8274 there are page 0 and page 2 Page 2 is for LCD display reg
60. are current when main clock oscillation stops and the sub clock is used OSCCON 721 Ipps is current when main clock and sub clock oscillation stops Every values in this table is measured when bits 4 3 of the system clock control register CLKCON 4 3 is set to 11 19 6 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec S3F8275 F8278 F8274 FLASH MCU Instruction Clock fx Main Sub oscillation frequency 2 MHz 8 MHz 1 05 MHz 4 2 MHz 6 25 kHz main 8 2 kHz sub 400 kHz main 32 8 kHz sub 3 4 2 5 3 6 Supply Voltage V Instruction Clock 1 4n x oscillator frequency n 1 2 8 16 Figure 19 3 Operating Voltage Range ELECTRONES 19 7 S3F8275 F8278 F8274 FLASH MCU 3C8275 F8275 C827 8 F8278 C8274 F8274 Preliminary Spec NOTES 19 8 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Spec DEVELOPMENT TOOLS DEVELOPMENT TOOLS OVERVIEW Samsung provides a powerful and easy to use development support system in turnkey form The development support system is configured with a host system debugging tools and support software For the host system any standard computer that operates with MS DOS Windows 95 and 98 as its operating system can be used One type of debugging tool including hardware and software is provided the sophisticated and powerful in circuit emulator SMDS2 and OPENice for S3C7 S3C9 S3C8 families of microcontrollers The SMDS2 is a new
61. cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 oor or 6 13 r Ir opc src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H C flag 1 register 01H 20H register 02H 03H and register 03H OAH ADC R1 R2 gt R1 14H R2 03H ADC R1 R2 gt R1 1BH R2 03H ADC 01H 02H gt Register 01H 24H register 02H 03H ADC 01H 02H gt Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value the carry flag is set to 1 and the source working register R2 contains the value The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 6 14 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADD Ada ADD Operation Flags Format Examples dst src dst dst src INSTRUCTION SET The source operand is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed C Setif there is a carry from the most significant bit of the result cleared otherwise Z Setif the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurred that is if both operands are of the same sign and the result is of the oppos
62. common signal output pin selection COM pin selection varies according to the selected duty cycle In 1 4 duty mode pins are selected In 1 3 duty mode COMO COM2 pins are selected In 1 2 duty mode COMO COM pins are selected SEGMENT SEG SIGNALS The 32 LCD segment signal pins are connected to corresponding display RAM locations at page 2 Bits of the display RAM are synchronized with the common signal output pins When the bit value of a display RAM location is 1 a select signal is sent to the corresponding segment pin When the display bit is 0 a no select signal to the corresponding segment pin gt Select pea Non Select p k 1 Frame gt Figure 13 6 Select No Select Signals in Static Display Mode 13 6 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LCD CONTROLLER DRIVER S Select Non Select lt 1 Frame gt COM SEG Figure 13 7 Select No Select Signal in 1 2 Duty 1 2 Bias Display Mode 4 Select J Non Select Figure 13 8 Select No Select Signal in 1 3 Duty 1 3 Bias Display Mode ELECTRONS 13 7 LCD CONTROLLER DRIVER 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Lo 21 1 1 1 2 SEGO It lolo SEG1 SEG3 H
63. following reset 2 Adash means that the bit is neither used nor mapped but the bit is read as 0 ELECTRONICS 4 3 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Bit number s that is are appended to Name of individual the register name for bit addressing bit or related bits Register location Register address in the internal Register ID Full Register name hexadecimal register file FLAGS System Flags Register D5H Set 1 Reset Value x x x x x x x 7 0 Read Write R W R W R W R W R W RN R W R W Bit Addressing Register addressing mode only Mode Carry Flag C 0 Operation does not generate a carry or borrow condition Operation generates carry out or borrow into high order bit 7 Zero Flag Z o Operation result is a non zero value o Operation result is zero Sign Flag S o Operation generates positive number MSB 0 Operation generates negative number MSB 1 R Read only Description of the Bit number W Write only effect of specific MSB Bit 7 R W Read write bit settings LSB Bit 0 Not used Type of addressing nRESET value notation that must be used to Not used address the bit x Undetermined value 1 bit 4 bit or 8 bit 0 Logic zero 1 Logic one Figure 4 1 Register Description Format 4 4 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER
64. gt Register 01H 02H register 02H OOH In Register R addressing mode the statement CLR OOH clears the destination register 00H value to In the second example the statement CLR 01H uses Indirect Register IR addressing mode to clear the 02H register value to OOH ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET COM Complement COM Operation Flags Format Examples dst dst NOT dst The contents of the destination location are complemented one s complement all 1s are changed to Os and vice versa C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to O D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst Opc dst 2 4 60 R 61 IR Given R1 07H and register 07H COM Ri gt R1 OF8H COM QHRi gt R1 07H register 07H OEH In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 all logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B ELECTRONS 6 29 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CP
65. instruction ELECTRONS 6 7 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET NOTATION Table 6 2 Flag Notation Conventions Description O Carry flag Zero flag Sign flag Overflow flag Decimal adjust flag Half carry flag Cleared to logic zero Set to logic one Set or cleared according to operation Z S V D H 0 1 Value is unaffected Value is undefined Table 6 3 Instruction Set Symbols Destination operand Source operand Indirect register address prefix Program counter Instruction pointer Flags register D5H Register pointer Immediate operand or register address prefix Hexadecimal number suffix Decimal number suffix Binary number suffix Opcode 6 8 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET Table 6 4 Instruction Notation Conventions Condition code Working register only Bit b of working register Bit 0 LSB of working register Working register pair Register or working register Bit b of register or working register Register pair or working register pair Indirect addressing mode Indirect working register only Indirect register or indirect working register Indirect working register pair only Indirect register pair or indirect working register pair Indexed addressing mode Indexed short offset addressing mode Indexed long offset addressing mode Direct addressing mode R
66. is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File FI FCTRONICS 3 3 ADDRESSING MODES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INDIRECT REGISTER ADDRESSING MODE Continued Register File Example REGISTER Instruction PAIR roc s ET Program Register Pair EB Memory Address Points to Program Memory Program Memory Sample Instructions a ie JP RR2 Figure 3 4 Indirect Register Addressing to Program Memory 3 4 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE Continued Register File RPO RPO or i Selected RP points to start fo working register 4 bit block die Working 1 9L888 Register Point to the Address Working Register 1 of 8 Sample Instruction Value used in OR R3 R6 Instruction Figure 3 5 Indirect Working Register Addressing to Register File FI FCTRONICS 3 5 ADDRESSING MODES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INDIRECT REGISTER ADDRESSING MODE Concluded Register File c M mm RPO or RP1 Selected RP points to start of Program Memory Wie 4 bit Working block Register Address Next 2 bit Point Pair Example Instruction to Working o References either Register Pair 16 Bit Pro
67. label of an 8 bit register address Figure 3 1 Register Addressing Register File MSB Point to RPO ot RP1 RPO or Selected RP points to start 4 bit of Em Working Register register block Point to the Working Register Program Memory Two Operand Instruction Example Sample Instruction ADD R1 R2 Where R1 and R2 are registers in the currently selected working register area Figure 3 2 Working Register Addressing 3 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESSING MODES INDIRECT REGISTER ADDRESSING MODE IR In Indirect Register IR addressing mode the content of the specified register or register pair is the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figures 3 3 through 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Please note however that you cannot access locations in set 1 using the Indirect Register addressing mode Program Memory Register File 8 bit Register File Address ADDRESS Point to One Register in Register One Operand File Instruction Example Address of Operand used by Instruction Value used in Instruction Execution Sample Instruction RL SHIFT Where SHIFT
68. nRESET IRQO IRQ7 Interrupts Interrupt Priority Vector Register Interrupt Interrupt Mask Register Global Interrupt Control El DI or SYM 0 manipulation Figure 5 4 Interrupt Function Diagram ELECTRONICS 5 7 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec PERIPHERAL INTERRUPT CONTROL REGISTERS For each interrupt source there is one or more corresponding peripheral control registers that let you control the interrupt generated by the related peripheral see Table 5 3 Table 5 3 Interrupt Source Control and Data Registers Interrupt Source Interrupt Level Register s Location s in Set 1 Timer B match TBCON TBDATA TBCNT E7H E5H E3H bank 1 Timer 1 A match TACON TADATA TACNT E6H E4H E2H bank 1 SIO interrupt IRQ1 Watch timer overflow IRQ2 WTCON E1H bank 1 0 0 external interrupt 0 1 external interrupt 0 2 external interrupt P1 3 external interrupt P1 7 external interrupt P1 6 external interrupt P1 5 external interrupt P1 4 external interrupt 5 8 SIOCON SIODATA SIOPS POCONL EXTICONL EXTIPND POCONL EXTICONL EXTIPND POCONL EXTICONL EXTIPND P1CONL EXTICONL EXTIPND P1CONH EXTICONH EXTIPND E1H bank 0 E2H bank 0 E3H bank 0 E5H bank 0 F9H bank 0 F7H bank 0 E5H bank 0 F9H bank 0 F7H bank 0 E5H bank 0 F9H bank 0 F7H bank 0 E8H bank 0 F9H bank 0 F7H bank 0 E7H bank 0 F8H bank 0 F7H bank 0 5
69. one time to form a 16 byte working register block Using the register pointers you can move this 16 byte register block anywhere in the addressable register file except the set 2 area The terms slice and block are used in this manual to help you visualize the size and relative locations of selected working register spaces working register s iceis 8 bytes eight 8 bit working registers 0 7 or R8 R15 working register block is 16 bytes sixteen 8 bit working registers RO R15 All the registers in an 8 byte working register slice have the same binary value for their five most significant address bits This makes it possible for each register pointer to point to one of the 24 slices in the register file The base addresses for the two selected 8 byte register slices are contained in register pointers RPO and RP1 After a reset RPO and RP1 always point to the 16 byte common area in set 1 COH CFH Slice 32 Slice 31 11111XXX Set 1 Only RP1 Registers R8 R15 Each register pointer points to one 8 byte slice of the register space selecting a total 16 byte working register block 00000XXX RPO Registers RO R7 Figure 2 7 8 Byte Working Register Areas Slices 2 12 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES USING THE REGISTER POINTS Register pointers RPO and RP1 mapped to addresses D6H and D7H in set 1 are used to select two movable 8
70. priority if more than one levels are currently requesting service The interrupt must be enabled at the interrupt s source peripheral control register When all the above conditions are met the interrupt request is acknowledged at the end of the instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 2 3 4 Reset clear to 0 the interrupt enable bit in the SYM register SYM 0 to disable all subsequent interrupts Save the program counter PC and status flags to the system stack Branch to the interrupt vector to fetch the address of the service routine Pass control to the interrupt service routine When the interrupt service routine is completed the CPU issues an Interrupt Return IRET The IRET restores the PC and status flags setting SYM O to 1 It allows the CPU to process the next interrupt request ELECTRONICS 5 15 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec GENERATING INTERRUPT VECTOR ADDRESSES The interrupt vector area in the ROM 00H FFH contains the addresses of interrupt service routines that correspond to each level in the interrupt structure Vectored interrupt processing follows this sequence 1 Push the program counter s low byte value to the stack Push the program counter s high byte value to the stack Push the FLAG register values to the stack Fetch the service routine s high byte address from the v
71. program memory of S3F8275 is divided into 128 sectors for unit of erase and programming Every sector has all 128 byte sizes of program memory areas So each sector should be erased first to program a new data byte into a sector Minimum 10ms delay time for erase is required after setting sector address and triggering erase start bit 0 Sector Erase is not supported Tool Program Modes MDS mode tool or Programming tool Sector 127 128 Byte Sector 10 128 Byte Sector 0 9 128 byte x 10 53 8275 Figure 16 6 Sector Configurations in User Program Mode ELECTRONES 16 7 EMBEDDED FLASH MEMORY INTERFACE 53 8275 8275 8278 8278 8274 8274 Preliminary Spec The Sector Program Procedure in User Program Mode Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Sector Address Register FMSECH FMSECL Set Flash Memory Control Register FMCON to 10100001B Set Flash Memory User Programming Enable Register FMUSR to 00000000 ox aw mo Ll Check the sector erase status bit whether sector erase is success of not 55 PROGRAMMING TIP Sector Erase SB1 reErase LD FMUSR 0A5H User program mode enable LD FMSECH 10H LD FMSECL 00H Set sector address 1000H 107FH LD FMCON 10100001B Start sector erase NOP Dummy instruction this instruction must be needed NOP Dummy instruction this instruction must be needed LD FMUSR 0 User program m
72. programmable program memory the 3C8278 has 8K bytes the S8C8274 has 4K bytes The first 256 bytes of the ROM are reserved for interrupt vector addresses Unused locations in this address range can be used as normal program memory If you use the vector address area to store a program code be careful not to overwrite the vector addresses stored in these locations The ROM address at which a program execution starts after a reset is 0100H in the S8C8275 C8278 C8274 The reset address of ROM can be changed by a smart option only in the S3F8275 Full Flash Device Refer to the chapter 16 Embedded Flash Memory Interface for more detail contents Decimal 16 383 Decimal 8 191 16K bytes Internal Program Decimal Area 8K bytes 4 095 Internal Program 4K bytes Memory Internal Program Memory Interrupt Vector Area 53 8275 8275 53 8278 8278 53 8274 8274 Figure 2 1 Program Memory Address Space 2 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES SMART OPTION ROM Address 003EH men used ISP Reset Vector m Enable Disable Bit 01 512 bytes 0 OBP reset vector address 10 1024 bytes 1 Normal vector address 0100H 11 2048 bytes ISP Reset Vector Address Selection Bit ISP Protection Enable Disable Bit 00 200H ISP area size 256 byte 0 Enable not erasable by LDC 01 300H ISP area size 512 byte 0
73. read 1 Fast interrupt service routine in progress when read 0 Bank Address Selection Flag BA 0 Bank 0 is selected Bank 1 is selected 4 12 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER FMCON riash Memory Control Register FOH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 Read Write R W R W R W R W R R W Addressing Mode Register addressing mode only 7 4 Flash Memory Mode Selection Bits 0 1 0 1 Programming mode fi folio Erase mode r otom Other values Not available 3 Sector Erase Status Bit 0 Success sector erase 1 Fail sector erase 2 1 Not used for S3F8275 F8278 F8274 0 Flash Operation Start Bit Operation stop 1 Operation start This bit will be cleared auto matically just after the corresponding operator completed ELECTRONICS 4 13 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec FMSECH Flash Memory Sector Address Register High Byte F2H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory Sector Address Bits High Byte The 15th 8th bits to select a sector of flash ROM NOTE high byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address FMSECL Flash Memory Sector Address Register Low Byte F3H Set 1 Bank 1 Bit Identifier 7 6 5 A 3 2 4 0
74. the register file you can use the SPH register as a general purpose data register However if an overflow or underflow condition occurs as a result of increasing or decreasing the stack address value in the SPL register during normal stack operations the value in the SPL register will overflow or underflow to the SPH register overwriting any other data that is currently stored there To avoid overwriting data in the SPH register you can initialize the SPL value to FFH instead of OOH 2 22 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES 8 Programming Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD PUSH PUSH PUSH PUSH POP POP POP POP ELECTRONICS SPL 0FFH PP RPO RP1 R3 R3 RP1 RPO PP SPL lt FFH Normally the SPL is set to OFFH by the initialization routine Stack address PP Stack address OFDH lt RPO Stack address OFCH lt RP1 Stack address OFBH lt R3 R3 lt Stack address OFBH RP1 lt Stack address OFCH RPO lt Stack address OFDH PP lt Stack address 2 23 ADDRESS SPACES 3C8275 F8275 C8278 F8278C8274 F8274 Preliminary Spec NOTES 2 24 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec ADDRESSING MODES ADDRESSING MODES OVERVIEW Instruction
75. to high level all system and peripheral control registers are reset to their default hardware values and the contents of all data registers are retained A reset operation automatically selects a slow clock fxx 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the programmed oscillation stabilization interval has elapsed the CPU starts the system initialization routine by fetching the program instruction stored in ROM location 0100H and 0101H Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Which interrupt you can use to release Stop mode in a given situation depends on the microcontroller s current internal operating mode The external interrupts in the 5308275 C8278 C8274 interrupt structure that can be used to release Stop mode External interrupts 0 2 INTO INT2 and P1 3 P1 7 INT3 INT7 Please note the following conditions for Stop mode release If you release Stop mode using an external interrupt the current values in system and peripheral control registers are unchanged except STPCON register If you use an internal or external interrupt for Stop mode release you can also program the duration of the oscillation stabilization interval To do this you must make the appropriate control and clock settings before entering Stop mode When the Stop mode is released by external interrupt the CLKCON 4
76. up Resistor Enable Bit Disable pull up resistor BE Enable pull up resistor 6 0 6 5 Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 5 PO s Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 4 P0 4 s Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 3 P0 3 s Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 2 P0 2 s Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 4 PO s Pull up Resistor Enable Bit Disable pull up resistor l Enable pull up resistor 0 0 0 5 Pull up Resistor Enable Bit Disable pull up resistor pg Enable pull up resistor NOTE A pull up resistor of port 0 is automatically disabled only when the corresponding pin is selected as push pull output or alternative function LI 4 24 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER P1CONH Port 1 Control Register High Byte E7H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P1 7 INT7 Configuration Bits 0 Schmitt trigger input mode 0 EREN N channel open drain output mode ifo Push pull output mode Not used for S3C8275 C8278 C8274 5 4 P1 6 INT6 Configuration Bits 0 Schmitt trigger input mode
77. was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst Opc dst 2 4 CO R C1 IR Examples Given Register OOH 55H register 01H 02H register 02H 17H and 0 RRC 00H gt Register OOH 2AH C i RRC Register 01H 02H register 02H 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC 00H rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of the C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register OOH The sign flag and overflow flag are both cleared to 0 6 74 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET SBO Select Bank 0 SBO Operation BANK 0 The SBO instruction clears the bank address flag in the FLAGS register FLAGS 0 to logic zero selecting bank 0 register addressing in the set 1 area of the register file Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 4 4F Example The statement SBO clears FLAGS 0 to 0 selecting bank 0 register addressing ELECTRONS 6 75 INSTRUCTION SET 3C8275
78. writing Can be assigned as an input or push pull output port VLC2 SCLK 1 Serial clock pin Input only pin TEST Vpp 13 Power supply pin for Flash ROM cell writing indicates that FLASH MCU enters into the writing mode When 12 5V is applied FLASH MCU is in writing mode and when 3 3V is applied FLASH MCU is in reading mode nRESET nRESET o o Chip initialization Vss Vss 9 10 Power supply pin for logic circuit Vpp should be tied to 3 3V during programming ELECTRONES 16 1 EMBEDDED FLASH MEMORY INTERFACE 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec User Program Mode This mode supports sector erase byte programming byte read and one protection mode Hard lock protection The read protection mode is available only in Tool Program mode So in order to make a chip into read protection you need to select a read protection option when you program a initial your code to a chip by using Tool Program mode by using a programming tool The S3F8275 has the pumping circuit internally therefore 12 5V into VPP test pin is not needed To program a flash memory in this mode several control registers will be used There are four kind functions programming reading sector erase hard lock protection FLASH MEMORY CONTROL REGISTERS USER PROGRAM MODE Flash Memory Control Register FMCON register is available only in user program mode to select the Flash Memory operation mode sector eras
79. 0H 01H gt Register 00H 2BH register 01H 02H register 02H 23H Z 1 TCM 00H 34 gt Register OOH 2BH Z 0 In the first example if working register RO contains the value 0C7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO0 R1 tests bit one in the destination register for a 1 value Because the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of the TCM operation 6 84 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET TM Test Under Mask TM Operation Flags Format Examples dst src dst AND src This instruction tests selected bits in the destination operand for a logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always reset to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src 6 73 r Ir opc src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Given RO OC7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H TM RO R1 RO OC7H Ri 02H Z
80. 1 to 1 leaving the value OFH 00001111B ELECTRONS 6 21 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BOR Bit or BOR dst src b BOR dst b src Operation dst 0 lt dst 0 OR src b Flags Format Examples 6 22 or dst b lt dst b OR src 0 The specified bit of the source or the destination is logically ORed with bit zero LSB of the destination or the source The resulting bit value is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Tesch Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 3 6 07 0 Pb opc dst 3 6 07 Rb ro NOTE the second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit Given R1 07H and register 01H BOR 1 01H 1 gt R1 07H register 01H BOR 01H 2 R1 Register 01H 07H R1 07H In the first example destination working register R1 contains the value 07H 00000111B and source register 01H the value 00000011B The statement BOR R1 01H 1 logically ORs bit one of register 01H source with bit zero of R1 destination This leaves the same value 07H in working register R1 In the second example dest
81. 15 SEG12 High nibble pins 4 4 4 7 SEG11 SEG8 Port 4 Control Registers PACONH PACONL Port 4 has two 8 bit control registers PACONH for P4 4 P4 7 and PACONL for P4 0 P4 3 A reset clears the P4CONH and P4CONL registers to 00H configuring all pins to input mode You use control registers setting to select input or output mode Port 4 Control Register High Byte PACONH E9H Set 1 Bank 1 R W P4 7 SEG8 XP4 6 SEG9 P4 5 SEG10 P4 4 SEG11 P4CONH bit pair pin configuration settings Input mode Input with pull up resistor Push pull output mode Alternative function SEG8 SEG1 1 Figure 9 19 Port 4 High Byte Control Register PACONH Port 4 Control Register Low Byte PACONL EAH Set 1 Bank 1 R W P4 3 SEG12 P4 2 SEG13 P4 1 SEG14 P4 0 SEG15 P4CONH bit pair pin configuration settings 00 Input mode 01 Input with pull up resistor 10 Push pull output mode 11 Alternative function SEG12 SEG15 Figure 9 20 Port 4 Low Byte Control Register PACONL ELECTRONICS 9 15 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORT 5 Port 5 is an 8 bit I O port with individually configurable pins Port 5 pins are accessed directly by writing or reading the port 5 data register P5 at location F5H in set 1 bank 0 P5 0 P5 7 can serve as inputs with or without pull up as push pull output or you can be configured the following functions Low nibble pins P5 0 P5 3 SEG7 SEG4
82. 1H gt Register 00H 02H register 01H 05H register 02H 05H If the user stack pointer register 00H for example contains the value 03H the statement PUSHUD 200H 01H decrements the user stack pointer by one leaving the value 02H The 01H register value 05H is then loaded into the register addressed by the decremented user stack pointer ELECTRONS 6 67 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PUSHUI Push user stack Incrementing PUSHUI Operation Flags Format Example 6 68 dst src IR IR 1 dst lt src This instruction is used for user defined stacks in the register file PUSHUI increments the user stack pointer and then loads the contents of the source into the register location addressed by the incremented user stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 83 IR R Given Register OOH register 01H and register 04H 2AH PUSHUI 00H 01H gt Register 00H 04H register 01H 05H register 04H 05H If the user stack pointer register OOH for example contains the value 03H the statement PUSHUI 00H 01H increments the user stack pointer by one leaving the value 04H The 01H register value 05H is then loaded into the location addressed by the incremented user stack pointer ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET RCF Rese
83. 275 8278 8278 8274 8274 Preliminary Spec ELECTRICAL DATA Table 17 2 D C Electrical Characteristics Continued TA 25 to 85 C Vp 20V to 36 V Symbol Conditions Typ Unit Input low 0 V leakage current All input pins except nRESET _ 112 Vi 0V Xn XT our 11 leakage current All output pins mue o leakage current All pins Pull Up resistors 0 V Ta 25 C pats 0 6 0 V Vpp 3V Ta 25 Z Oscillator feed Rosci Ta 25 C 1700 3000 XTN VDD XTour 0 V dividing resistor Vicp COMi 15 uA per common voltage drop i 0 3 Vicp SEGx 15 per common voltage drop x 0 31 Middle output Vict Vpp 27 V to 3 6 V 1 3 bias 2 3Vpp 0 2 2 3Vpp 2 32Vppg 02 V voltage 1 LCD clock OHZ Vico 1 3Vpg 0 2 t 8Vpg t 2Vpg 0 2 NOTE Itis middle output voltage when the co pin are opened ELECTRONICS 17 3 ELECTRICAL DATA 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Unit NOTES 1 Supply current does not include current drawn through internal pull up resistors LCD voltage dividing resistors the LVR block and external output current loads Ipp1 and power consumption for sub clock oscillation Table 17 2 D C Electrical Characteristics Concluded TA 25 to 85 C Vg 20V to 3 6
84. 275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET Table 6 1 Instruction Group Summary Concluded Mnemonic Operands Instruction Rotate and Shift Instructions RL dst Rotate left RLC dst Rotate left through carry RR dst Rotate right RRC dst Rotate right through carry SRA dst Shift right arithmetic SWAP dst Swap nibbles CPU Control Instructions CCF Complement carry flag DI Disable interrupts EI Enable interrupts IDLE Enter Idle mode NOP No operation RCF Reset carry flag SBO Set bank 0 SB1 Set bank 1 SCF Set carry flag SRP src Set register pointers SRPO src Set register pointer 0 SRP1 src Set register pointer 1 STOP Enter Stop mode ELECTRONS 6 5 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec FLAGS REGISTER FLAGS The flags register FLAGS contains eight bits that describe the current status of CPU operations Four of these bits FLAGS 7 FLAGS 4 can be tested and used with conditional jump instructions two others FLAGS 3 and FLAGS 2 are used for BCD arithmetic The FLAGS register also contains a bit to indicate the status of fast interrupt processing FLAGS 1 and a bank address status bit FLAGS 0 to indicate whether bank 0 or bank 1 is currently being addressed FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affe
85. 3 8275 8275 8278 8278 8274 8274 Preliminary Spec INTERRUPT STRUCTURE SYSTEM MODE REGISTER SYM The system mode register SYM set 1 DEH is used to globally enable and disable interrupt processing and to control fast interrupt processing see Figure 5 5 A reset clears SYM 1 and SYM 0 to 0 The 3 bit value for fast interrupt level selection SYM 4 SYM 2 is undetermined The instructions El and DI enable and disable global interrupt processing respectively by modifying the bit O value of the SYM register In order to enable interrupt processing an Enable Interrupt El instruction must be included in the initialization routine which follows a reset operation Although you can manipulate SYM 0 directly to enable and disable interrupts during the normal operation it is recommended to use the El and DI instructions for this purpose System Mode Register SYM DEH Set 1 R W Al g Global interrupt enable bit ways logic 0 Disable all interrupts processing 1 Enable all interrupts processing Not used for the S3C8275 C8278 C8274 Fast interrupt enable bit 0 Disable fast interrupts processing Fast interrupt level 1 Enable fast interrupts processing selection bits 0 0 IRQO 0 1 IRQ1 IRQ2 1 IRQ3 0 IRQ4 1 IRQ5 0 IRQ6 1 IRQ7 0000 Figure 5 5 System Mode Register SYM ELECTRONICS 5 9 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec INTERRUPT MA
86. 3 byte format is used for a conditional jump and the 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the opcode are both four bits Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W gt LABEL_W 1000H PC 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement JP C LABEL_W replaces the contents of the PC with the value 1000H and transfers control to that location Had the carry flag not been set control would then have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the PC with the contents of the register pair OOH and 01H leaving the value 0120H ELECTRONES 6 47 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec JR Jump Relative JR Operation Flags Format Example 6 48 cc dst If cc is true PC PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See list of condition codes The range of the relative address is 127 128 and the original val
87. 5 C8278 C8274 microcontroller two interrupt types are implemented Levels Vectors Sources Typei 1 vi 81 61 2 52 3 IRQn NOTES 1 The number of Sn and Vn value is expandable 2 In the S3C8275 C8278 C8274 implementation interrupt types 1 and 3 are used Figure 5 1 S3C8 Series Interrupt Types 5 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INTERRUPT STRUCTURE 3C8275 C8278 C8274 INTERRUPT STRUCTURE The S3C8275 C8278 C8274 microcontroller supports twelve interrupt sources All twelve of the interrupt sources have a corresponding interrupt vector address Eight interrupt levels are recognized by the CPU in this device specific interrupt structure as shown in Figure 5 2 When multiple interrupt levels are active the interrupt priority register IPR determines the order in which contending interrupts are to be serviced If multiple interrupts occur within the same interrupt level the interrupt with the lowest vector address is usually processed first The relative priorities of multiple interrupts within a single level are fixed in hardware When the CPU grants an interrupt request interrupt processing starts All other interrupts are disabled and the program counter value and status flags are pushed to stack The starting address of the service routine is fetched from the appropriate vector address plus the next
88. 53 8275 8275 8278 8278 8274 8274 8 5 MICROCONTROLLERS USER S MANUAL Revision 0 ELECTRONICS Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assumes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in syste
89. 6 2 COMS P6 3 VLCO VLC1 SEG17 P3 6 SEG18 P3 5 SEG19 P3 4 SEG20 P3 3 SEG21 P3 2 53 8275 8275 SEG22 P3 1 VLC deat sed SEG24P2 7 VoD S3C8274 F8274 SEG25 P2 6 Vss SEG26 P2 5 XOUT SEG27 P2 4 XIN 64 LQFP 1010 SEG28 P2 3 TEST SEG29 P2 2 XTIN SEG30 P2 1 XTOUT SEG31 P2 0 VBLDREF nRESET P1 7 INT7 1 2 3 4 5 6 7 8 9 PO O INTO 18 19 PO 2 INT2 CJ 20 PO 3 TICLK 21 PO 4 TAOUT 22 P0 5 TBOUT c4 23 P0 6 CLKOUT 24 P0 7 BUZ 25 P1 0 SCK C4 26 P1 1 50 C4 27 1 2 51 C 28 P1 3 INT3 Co 29 P1 4 INT4 C 30 P1 5 INT5 C 31 P1 6 INT6 Co 32 Figure 1 3 S3C8275 F8275 C8278 F8278 C8274 F8274 Pin Assignments 64 LQFP 1010 ELECTRONICS 1 5 PRODUCT OVERVIEW 3C8275 F8275 C8278 F8278C8274 F8274 Preliminary Spec PIN DESCRIPTIONS Table 1 1 S3C8275 F8275 C8278 F8278 C8274 F8274 Pin Descriptions Pin Circuit Shared Description Type Functions P0 0 PO 2 port with bit programmable pins INTO INT2 P0 3 Schmitt trigger input or push pull open drain T1CLK P0 4 output and software assignable pull ups TAOUT P0 5 P0 0 PO 2 are alternately used for external TBOUT P0 6 interrupt input noise filters interrupt enable and CLKOUT PO 7 pending control P1 0 I O port with bit programmable pins P1 1 Schmitt trigger input or push pull open drain P1 2 output and software assignable pull ups 1 3 1 7 1 3 1 7 are alternately used for external in
90. 6 60 0120 44 Address L 10 lt QIP IP lt IP 2 The NEXT instruction is useful when implementing threaded code languages The program memory word that is pointed to by the instruction pointer is loaded into the program counter The instruction pointer is then incremented by two No flags are affected Bytes Cycles Opcode Hex opc 1 10 OF The following diagram shows one example of how to use the NEXT instruction Before After Data Address Data 43 Address H 44 Address L 45 Address H Address 43 Address H 01 45 Address H 120 130 Routine Memory Memory ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET NOP Operation NOP Operation No action is performed when the CPU executes this instruction Typically one or more NOPs are executed in sequence in order to effect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time ELECTRONS 6 61 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec OR Logical OR OR dst src Operation dst lt dst OR src The source operand is logically ORed with the destination operand and the result is stored in the destination The contents of the source are unaf
91. 78 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET CPIJE Compare Increment and Jump on Equal CPIJE Operation Flags Format Example dst src RA If dst src 0 PC RA r e Ir 1 The source operand is compared to subtracted from the destination operand If the result is O the relative address is added to the program counter and control passes to the statement whose address is now in the program counter Otherwise the instruction immediately following the CPIJE instruction is executed In either case the source pointer is incremented by one before the next instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src ax so ast RA NOTE Execution time is 18 cycles if the jump is taken 16 cycles if it is not taken Given R1 02H R2 and register 02H R1 R2 SKIP gt R2 04H PC jumps to SKIP location In this example working register R1 contains the value 02H working register R2 the value 03H and register 03 contains 02H The statement R1 R2 SKIP compares the R2 value 02H 00000010B to 02H 0000001 0B Because the result of the comparison is equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source register R2 is incremented by one leaving a value of 04H Remember that the memory location must be within the allowed rang
92. 8 C8274 F8274 Preliminary Spec DA Decimal Adjust DA Example Continued Given Working register RO contains the value 15 BCD working register R1 contains 27 BCD and address 27H contains 46 BCD ADD R1 RO C amp 0 Bits 4 7 3 bits 0 3 C R1 3CH DA R1 R1 lt 3CH 06 If addition is performed using the BCD values 15 and 27 the result should be 42 The sum is incorrect however when the binary representations are added in the destination location using standard binary arithmetic 0001 0101 15 0010 0111 27 0011 11002 3CH The DA instruction adjusts this result so that the correct BCD representation is obtained 0011 1100 0000 0110 0100 0010 2 42 Assuming the same values given above the statements SUB 27 C amp H lt 0 Bits 4 7 3 bits 0 3 1 DA R1 R1 lt 31 0 leave the value 31 BCD in address 27H OR1 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec DEC Decrement DEC Operation Flags Format Examples dst dst dst 1 The contents of the destination operand are decremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Hex opc dst 2 4 00 01 Given R1 and register 03H 10H DEC Ri gt R1
93. 8274 Preliminary Spec INSTRUCTION SET SRA Shift Right Arithmetic SRA Operation dst dst 7 lt dst 7 C lt dst 0 dst n lt dst 1 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero the LSB replaces the carry flag The value of bit 7 the sign bit is unchanged and is shifted into bit position 6 Flags Format Examples C Set if the bit shifted from the LSB position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 DO R D1 IR Given Register OOH 9AH register 02H register OBCH and C 1 SRA 00H gt Register OOH OCD 0 SRA 02H gt Register 02H register C 0 In the first example if general register 00H contains the value 9AH 10011010B the statement SRA OOH shifts the bit values in register OOH right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted into the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in destination register ELECTRONS 6 79 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SRP SRPO SRP1 set Register Pointer SRP SRPO SRP1 Operation Flags
94. 8274 into a known operating status To allow time for internal CPU clock oscillation to stabilize the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required time of a reset operation for oscillation stabilization is 1 millisecond Whenever a reset occurs during normal operation that is when both V pp and nRESET are High level the nRESET pin is forced Low level and the reset operation starts All system and peripheral control registers are then reset to their default hardware values In summary the following sequence of events occurs during a reset operation All interrupt is disabled The watchdog function basic timer is enabled Ports 0 6 are set to input mode and all pull up resistors are disabled for the I O port Peripheral control and data register settings are disabled and reset to their default hardware values The program counter PC is loaded with the program reset address in the ROM 0100H When the programmed oscillation stabilization time interval has elapsed the instruction stored in ROM location 0100H and 0101H is fetched and executed at normal mode by smart option The reset address at ROM can be changed by Smart Option only in the S3F8275 full flash device Refer to The chapter 16 Embedded Flash Memory Interface for more detail contents NORMAL MODE RESET OPERATION In normal masked ROM mode the Tes
95. A 10 src 0001 DAL 4 14 B7 DA r NOTES 1 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 2 For formats and 4 the destination address XS rr and the source address XS rr are each one byte 3 For formats 5 and 6 the destination address rr and the source address rr are each two bytes 4 The DA and r source values for formats 7 and 8 are used to address program memory the second set of v alues used in formats 9 and 10 are used to address data memory 6 52 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET LDC LDE Load Memory LDC LDE Examples Continued Given RO R1 34H R2 04H R3 04H Program memory locations 0103H 4FH 0104H 0105H 6DH and 1104H 88H External data memory locations 0103H 0104H 2AH 0105H 7DH 1104H 98H LDC RO RR2 RO lt contents of program memory location 0104H RO R2 01H 04H LDE RO RR2 RO lt contents of external data memory location 0104H RO 2AH R2 01H 04H LDC note RR2 RO 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 no change LDE RR2 RO 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 no change LDC RO 01H RR2 RO lt contents of prog
96. BASIC TIMER CONTROL REGISTER BTCON The basic timer control register BTCON is used to select the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function It is located in set 1 address D3H and is read write addressable using Register addressing mode A reset clears BTCON to OOH This enables the watchdog function and selects a basic timer clock frequency of 5o 4096 To disable the watchdog function you must write the signature code 1010B to the basic timer register control bits 7 4 The 8 bit basic timer counter BTCNT et 1 bank 0 FDH be cleared at any time during normal operation by writing a 1 to BTCON 1 To clear the frequency dividers for the basic timer input clock and timer counters you write a 1 to 0 Basic Timer Control Register BTCON D3H Set 1 R W Divider clear bit for basic timer and timer counters Watchdog function enable bits 0 No effect 1010B Disable watchdog timer 1 Clear divider Other values Enable watchdog timer Basic timer counter clear bit 0 No effect 1 Clear BTCNT Basic timer input clock selection bits fxx 4096 01 fxx 1024 fxx 128 11 fxx 16 Figure 10 1 Basic Timer Control Register BTCON 10 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BASIC TIMER BASIC TIMER FUNCTION DESCRIPTION Watchdog Timer Function Y
97. CLKOUT 3 2 P0 5 TBOUT Configuration Bits o o Schmitt tiggerinputmeds 0 1 N channel open drain output mode 1 0 P0 4 TAOUT Configuration Bits Schmitt trigger input mode 1 N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function TAOUT 4 22 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER POCONL Port 0 Control Register Low Byte E5H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 3 T1CLK Configuration Bits 0 Schmitt trigger input mode 1 1 Em N channel open drain output mode ifo Push pull output mode Not used for 53 8275 8278 8274 5 4 P0 2 INT2 Configuration Bits 0 Schmitt trigger input mode HESS NN Fro Pnom SSS 3 2 P0 1 INT1 Configuration Bits schmittigserinpstmods 0 1 N channel open drain output mode 1 0 P0 0 INTO Configuration Bits fo Schmitt trigger input mode pofa N channel open drain output mode 1 0 Push pull output mode 1 1 Not used for S3C8275 C8278 C8274 ELECTRONICS 4 23 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec POPUR Porto Pull Up Control Register E6H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P0 7 s Pull
98. COM TCM TCM TCM TCM TCM BAND R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM I0 Rb 7 PUSH PUSH TM TM TM TM TM BIT R2 IR2 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b DECW DECW PUSHUD PUSHUI MULT MULT MULT RR1 IR1 IR1 R2 IR1 R2 R2 RR1 IR2 RR1 IM RR1 X 2 POPUD POPUI DIV DIV DIV in IR2 R1 IR2 R1 R2 RR1 IR2 RR1 IM RR1 25 X dt INCW INCW CP CP CP CP LDC RR1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 BT i r1 Irr2 xL rs CLR XOR XOR XOR XOR XOR LDC IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL RRC RRC CPIJE LDC LDW LDW LDW LD R1 IR1 Ir r2 RA r1 Irr2 RR2 RR1 IR2 RR1 RR1 IML r1 Ir2 SRA SRA CPIJNE LDC CALL LD LD R1 IR1 Irr r2 RA r2 lrr1 1 1 IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 Irr2 r1 Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F SWAP SWAP LDCPD LDCPI CALL LD CALL LDC R1 IR1 r2 lrr1 r2 lrr1 IRR1 IR2 R1 DA1 r2 xs 6 10 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET Table 6 5 Opcode Quick Reference Continued OPCODE MAP LOWER NIBBLE HEX ELECTRONS 6 11 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONDITION CODES The opcode of a conditional jump always contains a 4 bit field called the condition code cc This specifies under which conditions it is to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Condition codes are listed in Table 6 6 The carry C zero
99. CS 5 17 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec NOTES ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET INSTRUCTION SET OVERVIEW The SAM88RC instruction set is specifically designed to support the large register files that are typical of most 8 microcontrollers There are 78 instructions The powerful data manipulation capabilities and features of the instruction set include A full complement of 8 bit arithmetic and logic operations including multiply and divide special I O instructions I O control data registers are mapped directly into the register file Decimal adjustment included in binary coded decimal BCD operations 16 bit word data can be incremented and decremented Flexible instructions for bit addressing rotate and shift operations DATA TYPES The SAM8 CPU performs operations on bits bytes BCD digits and two byte words Bits in the register file can be set cleared complemented and tested Bits within a byte are numbered from 7 to 0 where bit 0 is the least significant right most bit REGISTER ADDRESSING To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit data or 16 bit program memory or data memory addresses For detailed information about register addressing please refer t
100. E Inthe second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H and register 01H 05H BAND R1 01H 1 gt R1 06H register 01H 05H BAND 01H 1 R1 gt Register 01H 05H R1 07H In the first example source register 01H contains the value 05H 00000101B and destination working register R1 contains 07H 00000111B The statement BAND R1 01H 1 ANDs the bit 1 value of the source register 0 with the bit 0 value of register R1 destination leaving the value 06H 000001 10B in register R1 ELECTRONS 6 17 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BCP sit Compare BCP Operation Flags Format Example 6 18 dst src b dst 0 src b The specified bit of the source is compared to subtracted from bit zero LSB of the destination The zero flag is set if the bits are the same otherwise it is cleared The contents of both operands are unaffected by the comparison Unaffected Set if the two bits are the same cleared otherwise Cleared to 0 Undefined Unaffected Unaffected DO QOEM Bytes Cycles Opcode Addr Mode Hex dst src NOTE the second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H a
101. EG28 P2 3 nRESET nRESET SEG29 P2 2 VREG SEG30 P2 1 PO O INTO SEG31 P2 0 VBLDREF PO 1 INT1 P1 7 INT7 PO 2 INT2 CJ 20 21 PO 4 TAOUT 22 P0 5 TBOUT c3 23 6 24 P0 7 BUZ C4 25 1 0 5 26 P1 1 SO 27 1 2 51 28 P1 3 INT3 29 P1 4 INT4 30 P1 5 INT5 C 31 P1 6 INT6 32 Figure 19 1 S3F8275 F8278 F8274 Pin Assignments 64 QFP 1420F 19 2 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SEGO P5 7 COMO P6 0 COM1 P6 1 COM2 P6 2 COM3 P6 3 VLCO SDAT VLC1 SCLK VLC2 VDD VDD Vss Vss XOUT XIN VPP TEST XTIN XTour nRESET nRESET 63 L3 SEG2 P5 5 62 E SEG3 P5 4 61 SEG4 P5 3 60 SEG5 P5 2 59 3 SEG6 P5 1 58 F SEG7 P5 0 57 L3 SEG8 P4 7 56 5 9 4 6 55 SEG10 P4 5 54 Fo SEG11 P4 4 53 L3 SEG12 P4 3 52 1 SEG13 P4 2 51 SEG14 P4 1 50 SEG15 P4 0 49 SEG16 P3 7 S3F8275 53 8278 53 8274 64 LQFP 1010 PO 2 INT2 20 P0 7 BUZ Cj 25 P1 0 SCK 26 P1 1 SO C4 27 1 2 51 28 P1 3 INT3 29 1 4 30 P1 5 INT5 C4 31 P1 6 INT6 32 PO O INTO C4 18 PO 3 TICLK c4 21 PO 1 INT1 PO 4 TAOUT 22 PO 5 TBOUT c4 23 6 24 S3F8275 F8278 F8274 FLASH MCU SEG17 P3 6 SEG18 P3 5 SEG19 P3 4 SEG20 P3 3 SEG21 P3 2 SEG22 P3 1 SEG23 P3 0 SEG24 P2 7 SEG25 P2 6 SEG26 P2 5 SEG27 P2 4 SEG28 P2 3 SEG29 P2 2 SEG30 P2 1 SEG31 P2 0 VBLDREF P1 7 IN
102. EG5 Configureation Bits Push pull output mode 1 Alternative function SEG5 3 2 P5 1 SEG6 Configureation Bits 0 Input mode 1 Input mode with pull up resistor Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode Alternative function SEG6 1 0 P5 0 SEG7 Configureation Bits o Input mode Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG7 ELECTRONICS 4 37 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec P6CON Port 6 Control Register EDH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P6 3 COM3 Configureation Bits 0 0 Input mode Input mode with pull up resistor EN Push pull output mode Alternative function COM3 Push pull output mode Alternative function COMO 4 38 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER Register Page Pointer DFH Set 1 Bit Identifier Les a 2 fa Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 4 Destination Register Page Selection Bits Destination page 0 0 0 0 0 o o estination page 1 Not used for the 6308278 824 1 0 Others Destination page 2 Not used for the S3C8275 C8278 C8274 3 0 S
103. ES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec IMMEDIATE MODE IM In Immediate IM addressing mode the operand value used in the instruction is the value supplied in the operand field itself The operand may be one byte or one word in length depending on the instruction used Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND The Operand value is in the instruction Sample Instruction LD Figure 3 14 Immediate Addressing 3 14 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER CONTROL REGISTERS OVERVIEW In this chapter detailed descriptions of the S8C8275 C8278 C8274 control registers are presented an easy to read format You can use this chapter as a quick reference source when writing application programs Figure 4 1 illustrates the important features of the standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic More detailed information about control registers is presented in the context of the specific peripheral hardware descriptions in Part Il of this manual Data and counter registers are not described in detail in this reference chapter More information about all of the registers used by a specific peripheral is presented in the corresponding peripheral descriptions in Part Il of this manual The locat
104. EX file which has been produced by assembler ROM code must be needed to fabricate a microcontroller which has a mask ROM When generating the ROM code OBJ file by HEX2ROM the value FF is filled into the unused ROM area up to the maximum ROM size of the target device automatically TARGET BOARDS Target boards are available for all S3C8 series microcontrollers All required target system cables and adapters are included with the device specific target board ELECTRONES 20 1 DEVELOPMENT TOOLS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec IBM PC AT or Compatible RS 232C SMDS2 Target lt gt PROM OTP Writer Unit Application System RAM Break Display Unit gt Trace Timer Unit TB8275 8 4 8 Base Unit Target Board EVA gt Power Supply Unit Chip Figure 20 1 SMDS Product Configuration SMDS2 20 2 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Spec DEVELOPMENT TOOLS TB8275 8 4 TARGET BOARD The TB 8275 8 4 target board is used for the S8C82 75 C8278 C8274 microcontroller It is supported with the SMDS2 8275 8 4 ToUser IDLE BLOF OFF ON Y1 sub clock 7 E a a o 160 3E8270 EVA Chip 100 pin connector Device Selection Select Smart Option Source Low S3F8278 4 Low Internal High S3F8275 High External Smart Option 1 50 pin connector 50 pin connector SMDS2 SMDS2 Figure 20 2 TB8275 8 4
105. EXTICONL bit configuration settings Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Figure 9 11 External Interrupt Control Register Low Byte EXTICONL External Interrupt Pending Register EXTIPND F7H Set 1 Bank 0 R W P1 7 P1 6 P1 5 P1 4 P1 3 02 P01 0 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO EXTIPND bit configuration settings 0 No interrupt pending when read clear pending bit when write 1 Interrupt is pending when read Figure 9 12 External Interrupt Pending Register EXTIPND 9 10 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORTS PORT 2 Port 2 is an 8 bit I O port with individually configurable pins Port 2 pins are accessed directly by writing or reading the port 2 data register P2 at location F2H in set 1 Bank 0 P2 0 P2 7 can serve as inputs with or without pull up as outputs push pull or open drain or you can be configured the following functions Low nibble pins P2 0 P2 3 SEG31 SEG28 Vg pace High nibble pins P2 4 P2 7 SEG27 SEG24 Port 2 Control Register 2 P2CONL Port 2 has two amp bit control register 2 for 2 4 2 7 and P2CONL for P2 0 P2 3 A reset clears the 2 and P2CONL registers to 00H configuring all pins to input mode You use control register setting to select input or output mode push pull o
106. Flash ROM TA 25 C to 85 Vpp 2 2 V to 3 6 V Parameter Conditions Unit Programming time 1 _ a a Sectorerasingtime FB 0 rs A NOTES 1 The programming time is the time during which one byte 8 bit is programmed 2 Thechip erasing time is the time during which all 16K byte block is erased 3 The sector erasing time is the time during which all 128 byte block is erased 4 Thechip erasing is available in Tool Program Mode only ELECTRONICS 17 13 ELECTRICAL DATA 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NOTES 17 14 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec MECHANICAL DATA MECHANICAL DATA OVERVIEW S3C8275 C8278 C8274 microcontroller is currently available in a 64 and LQFP package 23 90 0 30 20 00 0 20 0 10 0 15 0 05 0 MAX 64 QFP 1420F 14 00 020 17 90 0 30 0 80 0 20 gt H 5 1 J 0 1 0 40 0 05 T TOTO 15 MAX 0 05 MIN 1 00 qe lt gt 2 65 0 10 3 00 MAX 0 80 0 20 Hn NOTE Dimensions are in millimeters Figure 18 1 64 Pin QFP Package Dimensions 64 QFP 1420F ELECTRONS 18 1 MECHANICAL DATA 53 8275 8275 8278 8278 8274 8274 Preliminary Spec 12 00 BSC 64 LQFP 1010 0 08 MAX Q Q e N a 0 45 0 75 1 40 0 05
107. Format Examples 6 80 src src src If src 1 1 and src 0 then RPO 3 7 lt src 3 7 If src 1 O src 0 1 then 8 7 lt src 3 7 If src 1 and src 0 O then RPO 4 7 lt src 4 7 RPO 3 lt 0 4 7 lt src 4 7 RP1 3 lt 1 The source data bits and zero LSB determine whether to write or both of the register pointers RPO and RP1 Bits 3 7 of the selected register pointer are written unless both register pointers are selected RPO 3 is then cleared to logic zero and RP1 3 is set to logic one No flags are affected Bytes Cycles Opcode Addr Mode Hex src opc src 2 4 31 IM The statement SRP 40H sets register pointer 0 RPO at location OD6H to 40H and register pointer 1 RP1 at location OD7H to 48H The statement SRPO 50H sets RPO to 50H and the statement SRP1 68H sets RP1 to 68H ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET STOP Stop Operation STOP Operation The STOP instruction stops the both the CPU clock and system clock and causes the microcontroller to enter Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and I O port control and data registers are retained Stop mode can be released by an external reset operation or by external interrupts For the reset operation the RESET pin must be held to Low level until the required oscillation sta
108. H LDB R0 00H 2 gt RO O7H register 00H 05H LDB 00H 0 RO gt RO 06H register OOH 04H In the first example destination working register RO contains the value 06H and the source general register the value 05H The statement LD RO 00H 2 loads the bit two value of the 00H register into bit zero of the RO register leaving the value 07H in register RO In the second example is the destination register The statement LD 00 0 0 loads bit zero of register RO to the specified bit bit zero of the destination register leaving 04H in general register OOH ELECTRONS 6 51 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LDC LDE Load Memory LDC LDE dst src Operation dst lt src This instruction loads a byte from program or data memory into a working register or vice versa The source values are unaffected LDC refers to program memory and LDE to data memory The assembler makes or rr values an even number for program memory and odd an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex src 1 opc 2 10 C3 r 2 2 10 Irr r 3 opc dst src XS 3 12 E7 r XS rr 4 opc 3 12 xm 5 opc dst src X 4 14 A7 r XL rr 6 opc src dst gt lt 4 14 B7 Xj r 7 opc dst 0000 DAL DAY 4 14 r DA 8 opc src 0000 DA DAY 4 14 B7 DA r 9 opc dst 0001 DAL DAH 4 14 A7 r D
109. ID code A5H is written to the FMUSR register A mode of sector erase user program and hard lock may be executed unfortunately So It should be careful of the above situation 16 2 ELECTRONES 53 8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec EMBEDDED FLASH MEMORY INTERFACE Flash Memory User Programming Enable Register The FMUSR register is used for a safety operation of the flash memory This register will protect undesired erase or program operation from malfunctioning of CPU caused by an electrical noise After reset the user programming mode is disabled because the value of FMUSR is 00000000B by reset operation If necessary to operate the flash memory you can use the user programming mode by setting the value of FMUSR to 10100101B The other value of 10100101b user program mode is disabled Flash Memory User Programming Enable Register FMUSR F1H Set 1 Bank 1 R W Flash memory user programming enable bits 10100101 Enable user programming mode Other values disable user programming mode Figure 16 2 Flash Memory User Programming Enable Register FMUSR ELECTRONES 16 3 EMBEDDED FLASH MEMORY INTERFACE 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Flash Memory Sector Address Registers There are two sector address registers for addressing a sector to be erased The FMSECL Flash Memory Sector Address Register Low Byte indicates the low byte of sector address and FMSECH Flash memory Sector
110. ION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BTJ RT Bit Test Jump Relative on True BTJRT Operation Flags Format Example 6 24 dst src b If src b is a 1 then PC PC dst The specified bit within the source operand is tested If it is a 1 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRT instruction is executed No flags are affected Bytes Cycles Opcode Addr Mode Vote 1 Hex dst src opc dst 3 10 37 RA rb NOTE In the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRT SKIP R1 1 If working register R1 contains the value 07H 00000111B the statement BTJRT SKIP R1 1 tests bit one in the source register R1 Because it is a 1 the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET BXOR Bit xor BXOR dst src b BXOR dst b src Operation dst 0 lt dst 0 src b Flags Format Examples or dst b lt dst b src 0 The specified bit of the source or the destination is logic
111. Interrupt Level 3 IRQ3 Enable Bit External Interrupt P0 0 0 Disable mask 1 Enable unmask 2 Interrupt Level 2 IRQ2 Enable Bit Watch Timer Overflow Disable mask 1 Enable unmask 41 Inte rupt Level 1 IRQ1 Enable Bit SIO Interrupt Disable mask Enable unmask EG 0 Inte rupt Level 0 IRQO Enable Bit Timer 1 A Match Timer B Match Disable mask 1 Enable unmask NOTE When an interrupt level is masked any interrupt requests that may be issued are not recognized by the CPU LI 4 16 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER IPH instruction Pointer High Byte DAH Set 1 Reset Value X X X x x X X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address High Byte The high byte instruction pointer value is the upper eight bits of the 16 bit instruction pointer address IP15 IP8 The lower byte of the IP address is located in the IPL register DBH IPL instruction Pointer Low Byte DBH Set 1 Reset Value x X X X X x x X Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Instruction Pointer Address Low Byte The low byte instruction pointer value is the lower eight bits of the 16 bit instruction pointer address IP7 4PO The upper byte of the IP address is located in the IPH register DAH ELECTRONICS 4 17
112. LECTHONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER WTCON watch Timer Control Register E1H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Watch Timer Clock Selection Bit 0 Main system clock divided by 27 fx 128 1 Sub system clock fxt 6 Watch Timer Interrupt Enable Bit Disable watch timer interrupt Enable watch timer interrupt 5 4 Buzzer Signal Selection Bits 3 2 Watch Timer Speed Selection Bits fo Set watch timer interrupt to 1s fo Set watch timer interrupt to 0 5s ilo Set watch timer interrupt to 0 25s Set watch timer interrupt to 3 91ms 1 Watch Timer Enable Bit Disable watch timer Clear frequency dividing circuits 1 Enable watch timer 0 Watch Timer Interrupt Pending Bit Interrupt is not pending clear pending bit when write Interrupt is pending NOTE Watch timer clock frequency fw is assumed to be 32 768 kHz ELECTRONICS 4 47 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NOTES 4 48 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec INTERRUPT STRUCTURE INTERRUPT STRUCTURE OVERVIEW The S3C8 series interrupt structure has three basic components levels vectors and sources The SAM8RC CPU recognizes up to eight interrupt levels and supports up to 128 interrupt vectors When a sp
113. MULT NEXT NOP OR POP POPUD POPUI PUSH PUSHUD PUSHUI RCF RET RL RLC RR RRC SBO SB1 SBC SCF SRA SRP SRPO SRP1 STOP SUB SWAP TCM TM WFI XOR xxii List of Instruction Descriptions continued Full Register Name Page Number Load MEMO T 6 52 Load Memory and 6 54 Load Memory and Increment eene emen 6 55 Load Memory with Pre Decrement nnn 6 56 Load Memory with Pre Increment sssse emen 6 57 Load oec LL 6 58 Multiply Unsigried iot Rec P RR RR 6 59 MI ee eee 6 60 No Operationen dt de ket ioo xut elt ETE FR d Eoo deti 6 61 Logica OR mom 6 62 Pop from Stack e ie LC a Hop ERU Re 6 63 Pop User Stack n 6 64 Pop User Stack 6 65 Puslito Stack ado ro eb eio er Ri A 6 66 Push User Stack 6 67 Push User Stack Incrementing 0 eae eeeeeaaeeeeeeaaeeeeeeaaaaaaeeees 6 68 Reset Carry Flags c 6 69 E S 6 70 Rotate Left iic Due ek Ote hoe eed voie EE gi Peor e 6 71 Rotate Le
114. ONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CLOCK CIRCUIT CLOCK CIRCUIT OVERVIEW The 53 8275 8278 8274 microcontroller has two oscillator circuits a main clock and a sub clock circuit The CPU and peripheral hardware operate on the system clock frequency supplied through these circuits The maximum CPU clock frequency of S3C8275 C8278 C8274 is determined by register settings SYSTEM CLOCK CIRCUIT The system clock circuit has the following components External crystal ceramic resonator RC oscillation source or an external clock source Oscillator stop and wake up functions Programmable frequency divider for the CPU clock fxx divided by 1 2 8 or 16 System clock control register CLKCON Oscillator control register OSCCON and STOP control register STPCON Clock output control register CLOCON CPU Clock Notation In this document the following notation is used for descriptions of the CPU clock fx main clock fxt sub clock fxx selected system clock ELECTRONICS 7 1 CLOCK CIRCUIT MAIN OSCILLATOR CIRCUITS XIN XOUT Figure 7 1 Crystal Ceramic Oscillator fx XIN XOUT Figure 7 2 External Oscillator fx XIN XouT Figure 7 3 RC Oscillator fx 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SUB OSCILLATOR CIRCUITS 32 768 kHz Figure 7 4 Crystal Ceramic Oscillator fxt Normal 32 768 kHz Figure 7 5 Crystal C
115. POPUD 02H 00H loads the contents of register 42H into the destination register 02H The user stack pointer is then decremented by one leaving the value 41H ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET POPUI Pop User Stack Incrementing POPUI Operation Flags Format Example dst src dst lt src IR IR 1 The POPUI instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then incremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 93 R IR Given Register OOH 01H and register 01H 70H POPUI 02H 00H gt Register 02H register 01H 70H register 02H 70H If general register OOH contains the value 01H and register 01H the value 70H the statement POPUI 02H 00H loads the value 70H into the destination general register 02H The user stack pointer register 00H is then incremented by one changing its value from 01H to 02H ELECTRONS 6 65 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PUSH Push To Stack PUSH Operation Flags Format Examples src SP lt SP 1 SP lt src A PUSH instruction decrements the stack pointer value and loads the contents of the source src into the location addressed by the dec
116. Preliminary Spec TIMER 1 TIMER 1 ONE 16 BIT TIMER MODE TIMER 1 The 16 bit timer 1 is used one 16 bit timer or two 8 bit timers mode If TACON 7 is set to 1 timer 1 is used as a 16 bit timer If TACON 7 is set to 0 timer 1 is used as two 8 bit timers One 16bit timer mode Timer 1 Two 8 bit timers mode Timer A and B OVERVIEW The 16 bit timer 1 is an 16 bit general purpose timer Timer 1 has the interval timer mode by using the appropriate TACON setting Timer 1 has the following functional components Clock frequency divider fxx divided by 512 256 64 8 or 1 fxt and T1CLK External clock with multiplexer 16 bit counter TACNT TBCNT 16 bit comparator and 16 bit reference data register TADATA TBDATA Timer 1 match interrupt IRQ 0 vector FOH generation Timer 1 control register TACON set 1 bank 1 E6H read write FUNCTION DESCRIPTION Interval Timer Function The timer 1 module can generate an interrupt the timer 1 match interrupt belongs to the interrupt level IRQ 0 and is assigned a separate vector address FOH The T1INT pending condition should be cleared by software after IRQ 0 is serviced The T1INT pending bit must be cleared by the application sub routine by writing a 0 to the 0 pending bit In interval timer mode a match signal is generated when the counter value is identical to the values written to the timer 1 reference data re
117. RONS 6 39 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec El Enable Interrupts El Operation Flags Format Example 6 40 SYM 0 1 An El instruction sets bit zero of the system mode register SYM O to 1 This allows interrupts to be serviced as they occur assuming they have highest priority If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 9F Given SYM OOH EI If the SYM register contains the value 00H that is if interrupts are currently disabled the statement El sets the SYM register to 01H enabling all interrupts SYM 0 is the enable bit for global interrupt processing ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET ENTER Enter ENTER Operation SP lt SP 2 SP lt IP IP IP IP IP 2 This instruction is useful when implementing threaded code languages The contents of the instruction pointer are pushed to the stack The program counter PC value is then written to the instruction pointer The program memory word that is pointed to by the instruction pointer is loaded into the PC and the instruction pointer is incremented by two Flags No flags are affected Format Bytes Cycles Opcode Hex opc 1 14
118. Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Flash Memory Sector Address Bit Low Byte The 7th bit to select a sector of flash ROM 6 0 Bits 6 0 Don t care NOTE The low byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address 4 14 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER FMUSR rasn Memory User Programming Enable Register F1H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Flash Memory User Programming Enable Bits 10100101 Enable user programming mode Other values Disable user programming mode ELECTRONICS 4 15 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec IMR Interrupt Mask Register DDH Set 1 Reset Value x x x x x x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Interrupt Level 7 IRQ7 Enable Bit External Interrupts P1 4 1 7 Disable mask Enable unmask 6 Inte rupt Level 6 IRQ6 Enable Bit External Interrupts P1 3 Disable mask 1 Enable unmask 5 Interrupt Level 5 IRQ5 Enable Bit External Interrupt P0 2 Disable mask 1 Enable unmask 4 Interrupt Level 4 IRQ4 Enable Bit External Interrupt PO 1 Disable mask 1 Enable unmask 3
119. S3C8275 the total number of addressable 8 bit registers is 605 Of these 605 registers 13 bytes are for CPU and system control registers 16 bytes are for LCD data registers 48 bytes are for peripheral control and data registers 16 bytes are used as a shared working registers and 512 registers are for general purpose use page 0 page 1 in case of 5308278 C8274 page 0 You can always address set 1 register locations regardless of which of the two register pages is currently selected Set 1 locations however can only be addressed using register addressing modes The extension of register space into separately addressable areas sets banks and pages is supported by various addressing mode restrictions the select bank instructions SBO and SB1 and the register page pointer PP Specific register types and the area in bytes that they occupy in the register file are summarized in Table 2 1 Table 2 1 S3C8275 Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common working register area two 192 byte prime register area and two 64 byte set 2 area LCD data registers CPU and system control registers Mapped clock peripheral I O control and data registers Total Addressable Bytes Table 2 2 S3C8278 C8274 Register Type Summary Register Type Number of Bytes General purpose registers including the 16 byte common working register area one 192 byte prime register area
120. SK REGISTER IMR The interrupt mask register IMR set 1 DDH is used to enable or disable interrupt processing for individual interrupt levels After a reset all IMR bit values are undetermined and must therefore be written to their required settings by the initialization routine Each IMR bit corresponds to a specific interrupt level bit 1 to IRQ1 bit 2 to IRQ2 and so on When the IMR bit of an interrupt level is cleared to 0 interrupt processing for that level is disabled masked When you set a level s IMR bit to 1 interrupt processing for the level is enabled not masked The IMR register is mapped to register location DDH in set 1 Bit values can be read and written by instructions using the Register addressing mode Interrupt Mask Register IMR DDH Set 1 R W irae IRQ5 IRQ6 IRQ7 Interrupt level enable bits 0 Disable mask interrupt level 1 Enable un mask interrupt level NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended Figure 5 6 Interrupt Mask Register IMR 5 10 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec INTERRUPT STRUCTURE INTERRUPT PRIORITY REGISTER IPR The interrupt priority register IPR set 1 bank 0 FFH is used to set the relative priorities of the interrupt levels in the microcontroller s interrupt structure After a reset all IPR bit values are undetermined and mus
121. SP Sector Size Smart Option 003EH ISP Size Selection Bit Area of ISP Sector ISP Sector Size Bi2 Bito Ce ee 9 moH TFFH 56 bo 256 es 1 0 100H 4FFH 1024 byte 1024 Bytes 1 1 100H 8FFH 2048 byte 2048 Bytes NOTE The area of the ISP sector selected by Smart Option bit 003 2 003EH 0 can not be erased and programmed by LDC instruction in user program mode ISP Reset Vector and ISP Sector Size If you use ISP sectors by setting the ISP enable disable bit to 0 and the Reset Vector Selection bit to 0 at the Smart Option you can choose the reset vector address of CPU as shown in Table 16 3 by setting the ISP Reset Vector Address Selection bits Table 16 3 Reset Vector Address Smart Option 003EH ISP Reset Reset Vector Usable Area for ISP ISP Sector Size Vector Address Selection Bit Address After POR Sector 100H 1FFH 256 Bytes 100H 2FFH 512 Bytes 100H 4FFH 1024 Bytes NOTE The selection of the ISP reset vector address by smart option 003EH 7 003EH 5 is not dependent of the selection of ISP sector size by smart option 003 2 16 6 ELECTRONES 53 8275 F8275 C8278 F8278 C8274 F8274 Rreliminary Spec EMBEDDED FLASH MEMORY INTERFACE SECTOR ERASE User can erase a flash memory partially by using sector erase function only in User Program Mode The only unit of flash memory to be erased and programmed in User Program Mode is called sector The
122. See ee creo dle rdc qe teo 3 1 Register Addressing Mode 3 2 Indirect Register Addressing Mode 3 3 Indexed Addressing Mode 3 7 Direct Address Seiten cele Beri reat et deck prega Shanes 3 10 Indirect Address Mode 2 Psi ives 3 12 Relative Address Mode R yag Eee pagis 3 13 lmmediate Mode cc EE 3 14 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER Table of Contents continued Chapter 4 Control Registers OVEIVICW Mr EE 4 1 Chapter 5 Interrupt Structure OVetVIQW Ue ut ee D xe eon aue tree let ache aes ea 5 1 5 2 3C8275 C8278 C8274 Interrupt 53 Interrupt Vector Addresses e etes ee pepe Eee e Po 5 4 Enable Disable Interrupt Instructions El 5 6 System Level Interrupt Control Registers 5 6 Interrupt Processing
123. T7 Figure 19 2 S3F8275 F8278 F8274 Pin Assignments 64 LQFP 1010 ELECTRONES 19 3 S3F8275 F8278 F8274 FLASH MCU 3C8275 F8275 C827 8 F8278 C8274 F8274 Preliminary Spec Table 19 1 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming VLC1 SDAT 7 Serial data pin Output port when reading and input port when writing Can be assigned as a Input push pull output port VLC2 SCLK E Serial clock pin Input only pin TEST Power supply pin for Flash ROM cell writing indicates that FLASH MCU enters into the writing mode When 12 5V is applied FLASH MCU is in writing mode and when 3 3V is applied Flash MCU is in reading mode nRESET nRESET 1 6 1 Chip initialization Vpp Vss Vpp Vss 9 10 Power supply pin for logic circuit Vpp should be tied to 3 3 V during programming NOTE Parentheses indicate pin number for 64 pin QFP 1420F package Table 19 2 Comparison of S3F8275 F8278 F8274 and S3C8275 C8278 C8274 Features Characteristic S3F8275 F8278 F8274 3C8275 C8278 C8274 16 Kbyte Flash ROM 16 Kbyte mask ROM Operating voltage V pp 2 0 V to 3 6V 2 0 V to 3 6V Flash ROM programming mode Vp 3 3 V Vpp TEST 12 5V Pin configuration 64 QFP 64 QFP Flash ROM programmability User Program 10 000 time Programmed at the factory 19 4 ELECTRONES 53 8275 8275 8278 8278 8274 8274 Preliminary Spec S3F8275 F8278 F8274 FLASH MCU OPERATING MODE CHARACTERISTICS
124. TION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BITR Bit Reset BITR Operation Flags Format Example 6 20 dst b dst b lt 0 The BITR instruction clears the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BTR R11 gt R1 05H If the value of working register R1 is 07H 00000111B the statement BITR R1 1 clears bit one of the destination register R1 leaving the value 05H 00000101B ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET BITS Bit Set BITS Operation Flags Format Example dst b dst b lt 1 The BITS instruction sets the specified bit within the destination without affecting any other bits in the destination No flags are affected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 O7H BITS R13 gt R1 OFH If working register R1 contains the value 07H 00000111B the statement BITS R1 3 sets bit three of the destination register R
125. TRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET MULT multiply Unsigned MULT Operation Flags Format Examples dst src dst lt dstx src The 8 bit destination operand even register of the register pair is multiplied by the source operand 8 bits and the product 16 bits is stored in the register pair specified by the destination address Both operands are treated as unsigned integers C Set if result is gt 255 cleared otherwise Z Set if the result is 0 cleared otherwise S Set if MSB of the result is a 1 cleared otherwise V Cleared D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 22 84 RR R 22 85 RR IR 22 86 RR IM Given Register OOH 20H register 01H 03H register 02H 09H register 03H 06H MULT 00H 02H gt Register 00H 01H register 01H 20H register 02H 09H MULT 00H 01 Register OOH OOH register 01H OCOH MULT 00H 30H gt Register OOH 06H register 01H OOH In the first example the statement MULT 00H 02H multiplies the 8 bit destination operand in the register OOH of the register pair OOH 01H by the source register 02H operand 09H The 16 bit product 0120H is stored in the register pair OOH 01H ELECTRONS 6 59 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NEXT next NEXT Operation Flags Format Example Address
126. This causes the PC to jump to address 100H and the IP to keep the return address The last instruction in the service routine normally is a jump to IRET at address FFH This causes the instruction pointer to be loaded with 100H again and the program counter to jump back to the main program Now the next interrupt can occur and the IP is still correct at 100H 0H FFH 100H Interrupt Service Routine JP to FFH FFFFH In the fast interrupt example above if the last instruction is not a jump to IRET you must pay attention to the order of the last two instructions The IRET cannot be immediately proceeded by a clearing of the interrupt status as with a reset of the IPR register ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET JP Jump JP JP Operation Flags Format 1 Examples cc dst Conditional dst Unconditional If cc is true dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP simply replaces the contents of the PC with the contents of the specified register pair Control then passes to the statement addressed by the PC No flags are affected Bytes Cycles Opcode Addr Mode 2 Hex dst cc opc dst 3 8 ccD DA cc Oto F opc dst 2 8 30 IRR NOTES 1 The
127. W SMDS2 IDLE LED The Yellow LED is ON when the evaluation chip S3E8270 is in idle mode STOP LED Red LED is ON when the evaluation chip 53 8270 is in stop mode 20 6 ELECTRONES SEGO P5 7 COM1 P6 1 COM3 P6 3 VLC1 VDD N C TEST N C VREG INT1 P0 1 T1CLK P0 3 TBOUT PO 5 BUZ PO 7 SO P1 1 INT3 P1 3 INT5 P1 5 N C N C N C N C P6 0 COMO P6 2 COM2 VLCO VLC2 nRESET PO 0 INTO PO 2 INT2 PO 4 TAOUT P0 6 CLKOUT P1 0 SCK P1 2 SI P1 4 INT4 P1 6 INT6 N C N C N C N C 3C8275 F8275 C8278 F8278 C8274 F8274 Spec INT7 P1 7 SEG30 P2 1 SEG28 P2 3 SEG26 P2 5 SEG24 P2 7 SEG22 P3 1 SEG20 P3 3 SEG18 P3 5 SEG16 P3 7 SEG14 P4 1 SEG12 P4 3 SEG10 P4 5 SEG8 P4 7 SEG6 P5 1 SEG4 P5 3 SEG2 P5 5 N C N C N C N C DEVELOPMENT TOOLS SEG31 P2 0 VBLDREF SEG29 P2 2 SEG27 P2 4 SEG25 P2 6 SEG23 P3 0 SEG21 P3 2 SEG19 P3 4 SEG17 P3 6 SEG15 P4 0 SEG13 P4 2 SEG11 P4 4 SEG9 P4 6 SEG7 P5 0 SEG5 P5 2 SEG3 P5 4 SEG1 P5 6 N C N C N C N C Figure 20 3 40 Pin Connectors J101 J102 for TB8275 8 4 Target Board Target Board J101 J102 J102 J101 2 33 34 Target Cable for 40 pin Connector Part Name AS40D A Order Code SM6306 JOJOBUUOD 40 Pin Connector 1 31 32 63 64 Figure 20 4 S3E8270 Cables for64 QFP Package ELECTRONES 20 7 DEVELOPMENT TOOLS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NOTES 20 8 ELECTRONES
128. W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 3 SEG28 Configuration Bits 0 Input mode 0 EREN N channel open drain output mode ifo Push pull output mode Alternative function SEG28 5 4 P2 2 SEG29 Configuration Bits 0 Input mode 1 N channel open drain output mode Push pull output mode Alternative function SEG29 3 2 P2 1 SEG30 Configuration Bits Input mode 0 1 N channel open drain output mode 0 Push pull output mode 1 0 P2 0 SEG31 Vg paper Configuration Bits oo mumd Fo 1 Neemeropedamoupurme ilo Push pull output mode Alternative function SEG31 or Vg par ELECTRONICS 4 29 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec P2PUR Port2 Pull up Control Register ECH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P2 7 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 6 P2 6 s Pull up Resistor Enable Bit Disable pull up resistor BE Enable pull up resistor 5 P2 5 s Pull up Resistor Enable Bit Disable pull up resistor BE Enable pull up resistor 4 P2 A s Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 3 P2 5 Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor BG 2 P2 2 s Pull u
129. a Transfer Timing ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ELECTRICAL DATA Table 17 6 Characteristics of Battery Level Detect Circuit TA 25 C 20 V to 3 6 V Symbol Voltage of BLD VBip BLDCON 2 0 000b BLDCON 2 0 101b BLDCON 2 0 011b IVpp 22V Hysteresis voltage of BLD BLDCON 2 0 000b 100 101b 011b BLD circuit response time Fw 32 768 kHz _ Current consumption DE UNES 3 3 V Table 17 7 LVR Low Voltage Reset Circuit Characteristics Hysteresis of LVR NENNEN NOTES 1 The current of LVR circuit is consumed when LVR is enabled by Smart Option 2 Current consumed when low voltage reset circuit is provided internally Figure 17 6 LVR Low Voltage Reset Timing ELECTRONICS 17 9 ELECTRICAL DATA 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 17 8 Main Oscillation Characteristics TA 25 C to 85 C Oscillator Clock Configuration Test Condition Crystal C1 Main oscillation 25V 3 6V 0 4 frequency 2 0 V 3 6V Ceramic C1 Main oscillation 25V 3 6V 0 4 oscillator frequency co XOUT 2 0 V 3 6 V 0 4 0 4 Typ Max units MHz External Xn input frequency 25V 3 6 clock 2 0V 3 6V RC Frequency 3 3V oscillator MHz Cw Table 17 9 Sub Oscillation Characteristics TA 25 C to 85 C Crystal C1 Sub oscillat
130. ackage Type e 64 QFP 1420F 644 QFP 1010 Smart Option e Low Voltage Reset LVR level and enable disable are at your hardwired option ROM address 3FH e ISP related option selectable ROM address 3EH ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec PRODUCT OVERVIEW BLOCK DIAGRAM Watchdog XIN Xour i nRESET VPEG mer TAOUT PO 4 8 Bit Timer T1CLK P0 3 gt Counter A 16 Bit 8 Bit Timer Timer TBOUT PO 5 4 Counter B Counter 1 Basic Timer ow Voltage Reset PO 0 INTO PO 1 INT1 P n CLKOUT PO 6 PO 2 INT2 Port I O and Interrupt Control oc P0 3 T1CLK PO4 TAOUT Port 0 Bc P0 5 TBOUT Watch Timer 2 7 0 7 BUZ COMO0 COWM3 P6 0 P6 3 P1 0 SCK 88 CPU SEGO SEG7 P5 7 P5 0 P1 1 SO P1 2 SI SEG8 SEG15 P4 7 P4 0 1 LCD P1 4 INT4 lt gt Port 1 Driver SEG16 SEG23 P3 7 P3 0 P1 5 INT5 SEG24 SEG30 P2 7 P2 1 P1 6 INT6 P1 7 INT7 SEG31 P2 0 VBLDREF 544 288 Byte 16 8 4 Kbyte gt VLCO VLC2 Register File ROM lt P2 0 SEG31 VBLDREF Port 2 Sio lt gt 1 P2 1 P2 7 SEG30 SEG24 lt gt 4 P1 2 SI P6 0 P6 3 P3 0 P3 7 SEG23 SEG16 lt p Port 3 VO Pot6 4 como com3 P5 0 P5 7 lOPot5 4 P4 0 P4 7 SEG15 SEG8 lt p Port 4 SEG7 SEGO Figure 1 1 Block Diagram ELECTRONICS 1 3 PRODUCT OVERVIEW 3C8275 F8275 C8278 F8278C8274 F8274 Preliminary Spec
131. ally exclusive ORed with bit zero LSB of the destination or source The result bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Bytes Cycles Opcode Addr Mode Hex dst src dst b 0 3 6 27 0 Rb opc dst 3 6 27 Rb r0 NOTE second byte of the 3 byte instruction formats the destination or source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H 00000111B and register 01H 03H 00000011B BXOR R1 01H 1 gt R1 O6H register 01H 03H BXOR 01H 2 R1 gt Register 01H 07H R1 07H In the first example destination working register R1 has the value 07H 00000111B and source register 01H has the value 03H 00000011B The statement BXOR R1 01H 1 exclusive ORs bit one of register 01H source with bit zero of R1 destination The result bit value is stored in bit zero of R1 changing its value from 07H to 06H The value of source register 01H is unaffected ELECTRONS 6 25 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CALL Call Procedure CALL Operation Flags Format Examples dst SP lt SP 1 SP lt PCL SP lt SP 1 SP lt PCH PC lt dst The current contents of the prog
132. an interrupt within a given level to be completed in approximately 6 clock cycles rather than the usual 16 clock cycles To select a specific interrupt level for fast interrupt processing you write the appropriate 3 bit value to SYM 4 SYM 2 Then to enable fast interrupt processing for the selected level you set SYM 1 to 1 5 16 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec INTERRUPT STRUCTURE FAST INTERRUPT PROCESSING Continued Two other system registers support fast interrupt processing The instruction pointer IP contains the starting address of the service routine and is later used to swap the program counter values and When a fast interrupt occurs the contents of the FLAGS register is stored in an unmapped dedicated register called FLAGS FLAGS prime NOTE For the S8C8275 C8278 C8274 microcontroller the service routine for any one of the eight interrupt levels IRQO IRQ can be selected for fast interrupt processing Procedure for Initiating Fast Interrupts To initiate fast interrupt processing follow these steps 1 Load the start address of the service routine into the instruction pointer IP 2 Load the interrupt level number IRQn into the fast interrupt selection field SYM 4 SYM 2 3 Write a 1 to the fast interrupt enable bit in the SYM register Fast Interrupt Service Routine When an interrupt occurs in the level selected for fast interrupt processi
133. and CLKCON 3 bit pair setting remains unchanged and the currently selected clock value is used The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed How to Enter into Stop Mode Handling STPCON register then writing Stop instruction keep the order LD STPCON 10100101B STOP NOP NOP NOP ELECTRONICS 8 5 RESET and POWER DOWN 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec IDLE MODE Idle mode is invoked by the instruction IDLE opcode 6FH In idle mode CPU operations are halted while some peripherals remain active During idle mode the internal clock signal is gated away from the CPU but all peripherals timers remain active Port pins retain the mode input or output they had at the time idle mode was entered There are two ways to release idle mode 1 Execute a reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The reset automatically selects the slow clock fxx 16 because CLKCON 4 and CLKCON 3 are cleared to OOB If interrupts are masked a reset is the only way to release idle mode 2 Activate any enabled interrupt causing idle mode to be released When you use an interrupt to release idle mode the CLKCON 4 and CLKCON 3 register values remain unchanged and the currently selecte
134. and an odd number for external data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src ope 2 14 F2 Irr r Given RO 77H R6 30H and R7 00H LDCPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into program memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 OFFH LDEPD RR6 RO RR6 lt RR6 1 77H contents of RO is loaded into external data memory location 2FFFH 3000H 1H RO 77H R6 2FH R7 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET LDCPI LDEPI Load Memory with Pre Increment LDCPI LDEPI dst src Operation r err 1 dst src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first incremented The contents of the source location are loaded into the destination location The contents of the source are unaffected LDCPI refers to program memory and LDEPI refers to external data memory The assembler makes an even number for program memory and an odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 2 14 F3 Ire r Examples Given RO 7FH R6 21H and R7 OFFH LDCPI RR6 RO RR6 lt RR6 1 contents of RO is loaded into program memory location 2200H 21FFH
135. at the rate of fxx 4096 for reset or at the rate of the preset clock source for an internal and an external interrupt When BTCNT 3 overflows a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation In summary the following events occur when stop mode is released 1 During stop mode a power on reset or an internal and an external interrupt occurs to trigger the stop mode release and oscillation starts 2 If a power on reset occurred the basic timer counter will increase at the rate of 4096 If an internal and an external interrupt is used to release stop mode the BTCNT value increases at the rate of the preset clock source Clock oscillation stabilization interval begins and continues until bit 3 of the basic timer counter overflows When a BTCNT 3 overflow occurs normal CPU operation resumes ELECTRONICS 10 3 BASIC TIMER 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RESET or STOP Basic Timer Control Register v Write 1010xxxxB to Disable Data Bus fxx 4096 fxx 1024 8 Bit Up Counter 128 BTCNT Read Only Start the CPU ne NOTE During a power on reset operation the CPU is idle during the required oscillation stabilization interval until bit 4 of the basic timer counter overflows Figure 10 2 Basic Timer Block Diagram 10 4 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274
136. ata memory LDE if implemented Program or Data Memory Lower Address Byte LSB Selects Program Memory or Data Memory 0 Program Memory 1 Data Memory Memory Address P M rogram Memory Used Upper Address Byte Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H ldentical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions 3 10 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec ADDRESSING MODES DIRECT ADDRESS MODE Continued Program Memory Next OPCODE Memory Address Used Upper Address Byte Lower Address Byte Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instructions FI FCTRONICS 3 11 ADDRESSING MODES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INDIRECT ADDRESS MODE In Indirect Address IA mode the instruction specifies an address located in the lowest 256 bytes of the program memory The selected pair of memory locations contains the actual address of the next instruction to be executed Only the CALL instruction can use the Indirect Address mode Because the Indirect Address mode assumes that the operand is located in the lowest 256 bytes of program memory on
137. ber that the memory location must be within the allowed range of 127 to 128 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec DA Decimal Adjust INSTRUCTION SET The destination operand is adjusted to form two 4 bit BCD digits following an addition or subtraction operation For addition ADD ADC or subtraction SUB SBC the following table indicates the operation performed The operation is undefined if the destination operand was not the result of a valid addition or subtraction of BCD digits Bits 4 7 Value Hex 0 9 0 8 0 9 A F 9 F A F 0 2 0 2 0 3 0 9 0 8 7 F 6 F H Flag Before DA 0 0 1 O O O O O Bits 0 3 Value Hex 0 9 A F 0 3 0 9 A F 0 3 0 9 A F 0 3 0 9 6 F 0 9 6 F Number Added to Byte 00 FA 0 9A 00 06 06 60 66 66 60 66 66 06 60 66 Carry After DA 0 amp oof LB C Set if there was carry from the most significant bit cleared otherwise see table Z Set if result is 0 cleared otherwise S Set if result bit 7 is set cleared otherwise DA dst Operation dst lt DA dst Instruction Carry Before DA 0 0 0 ADD 0 ADC 0 0 1 1 1 0 SUB 0 SBC 1 1 Flags V Undefined D Unaffected H Unaffected Format ELECTRONS dst Bytes Cycles Opcode Hex 40 41 Addr Mode dst R IR 6 33 INSTRUCTION SET 3C8275 F8275 C8278 F827
138. bilization interval has elapsed In application programs a STOP instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after STOP instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement STOP halts all microcontroller operations NOP NOP NOP ELECTRONS 6 81 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SUB Subtract SUB dst src Operation dst lt dst src The source operand is subtracted from the destination operand and the result is stored in the destination The contents of the source are unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Set if a borrow occurred cleared otherwise Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is of the same as the sign of the source operand cleared otherwise D Always set 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set oth
139. both falling and rising edge 0 Disable interrupt 1 Enable interrupt by falling edge Lo Enable interrupt by rising edge Enable interrupt by both falling and rising edge Disable interrupt Enable interrupt by falling edge 0 Enable interrupt by rising edge Enable interrupt by both falling and rising edge Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge 4 10 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER EXITPND external Interrupt Pending Register F7H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 4 P1 7 INT7 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 6 P1 6 INT6 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 5 P1 5 INT5 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 4 P1 4 INT4 Interrupt Pending Bit 0 1 Interrupt request is not pending pending bit clear when write 0 Interrupt request is pending 3 P1 3 INT3 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 2 P0 2 INT2 Interrupt Pending Bit Inter
140. byte working register slices in the register file After a reset they point to the working register common area RPO points to addresses COH C7H and RP1 points to addresses C8H CFH To change a register pointer value you load a new value to RPO and or RP1 using an SRP or LD instruction see Figures 2 8 and 2 9 With working register addressing you can only access those two 8 bit slices of the register file that are currently pointed to by RPO and RP1 You cannot however use the register pointers to select a working register space in set 2 COH FFH because these locations can be accessed only using the Indirect Register or Indexed addressing modes The selected 16 byte working register block usually consists of two contiguous 8 byte slices As a general programming guideline it is recommended that RPO point to the lower slice and RP1 point to the upper slice see Figure 2 8 In some cases it may be necessary to define working register areas in different non contiguous areas of the register file In Figure 2 7 RPO points to the upper slice and RP1 to the lower slice Because a register pointer can point to either of the two 8 byte slices in the working register block you can flexibly define the working register area to support program requirements 58 PROGRAMMING TIP Setting the Register Pointers SRP 70H RPO lt 70H RP1 lt 78H SRP1 48H RPO lt nochange RP1 lt 48H SRPO 0A0H RPO lt AOH 1 lt n
141. ccess working registers very efficiently using short 4 bit addresses When an instruction addresses a location in the selected working register area the address bits are concatenated in the following way to form a complete 8 bit address high order bit of the 4 bit address selects one of the register pointers 0 selects RPO 1 selects The five high order bits in the register pointer select an 8 byte slice of the register space The three low order bits of the 4 bit address select one of the eight registers in the slice As shown in Figure 2 13 the result of this operation is that the five high order bits from the register pointer are concatenated with the three low order bits from the instruction address to form the complete address As long as the address stored in the register pointer remains unchanged the three bits from the address will always point to an address in the same 8 byte register slice Figure 2 14 shows a typical example of 4 bit working register addressing The high order bit of the instruction INC R6 is 0 which selects RPO The five high order bits stored in RPO 01110B are concatenated with the three low order bits of the instruction s 4 bit address 110B to produce the register address 76H 01110110B 2 18 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES RP1 Selects RPO or RP1 Address OPCODE LL TT PTT Ty 4 bit address provide
142. cific interrupt levels After a reset all IRQ status bits are cleared to 0 You can poll IRQ register values even if a DI instruction has been executed that is if global interrupt processing is disabled If an interrupt occurs while the interrupt structure is disabled the CPU will not service it You can however still detect the interrupt request by polling the IRQ register In this way you can determine which events occurred while the interrupt structure was globally disabled Interrupt Request Register IRQ DCH Set 1 Read only Interrupt level request pending bits 0 Interrupt level is not pending 1 Interrupt level is pending Figure 5 9 Interrupt Request Register IRQ ELECTRONICS 5 13 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec INTERRUPT PENDING FUNCTION TYPES Overview There are two types of interrupt pending bits one type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared in the interrupt service routine Pending Bits Cleared Automatically by Hardware For interrupt pending bits that are cleared automatically by hardware interrupt logic sets the corresponding pending bit to 1 when a request occurs It then issues an IRQ pulse to inform the CPU that an interrupt is waiting to be serviced The CPU acknowledges the interrupt source by sending an IACK executes the service routine and c
143. ct fxx 16 10 Select fxx 8 11 Select fxx 4 Figure 7 9 Clock Output Control Register CLOCON CLOCON 1 0 POCONH 5 4 CLKOUT PO0 6 Figure 7 10 Clock Output Block Diagram ELECTRONICS 7 5 CLOCK CIRCUIT 3C8275 C8278 C8274 F8 275 F8278 F8274 Preliminary Spec OSCILLATOR CONTROL REGISTER OSCCON The oscillator control register OSCCON is located in set 1 bank 0 address EOH It is read write addressable and has the following functions System clock selection Main oscillator control Sub oscillator control Sub oscillator circuit selection OSCCON 0 register settings select Main clock or Sub clock as system clock After a reset Main clock is selected for system clock because the reset value of 5 0 is The main oscillator can be stopped or run by setting OSCCON 3 The sub oscillator can be stopped or run by setting OSCCON 2 Oscillator Control Register OSCCON EOH Set 1 Bank 0 R W Not used for S3C8275 System clock selection bit C8278 C8274 0 Main oscillator select 1 Sub oscillator select Sub oscillator circuit selection bit 0 Select normal circuit for sub oscillator 1 Select power saving circuit for sub oscillator Automatically cleared to 0 when the sub oscillator is stopped by OSCCON 2 or the CPU Sub oscillator control bit is entered into stop mode in sub operation mode 0 Sub oscillator RUN 1 Sub oscillator STOP Not used for S3C8275 C8278 C8274
144. ct the Flags register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the Flags register as the destination then simultaneously two write will occur to the Flags register producing an unpredictable result System Flags Register FLAGS D5H Set 1 RAW Bank address Carry flag C status flag BA Fast interrupt Zero flag Z status flag FIS Sign flag S Half carry flag H Overflow flag V Decimal adjust flag D Figure 6 1 System Flags Register FLAGS 6 6 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET FLAG DESCRIPTIONS C FIS BA Carry Flag FLAGS 7 The C flag is set to 1 if the result from an arithmetic operation generates a carry out from or a borrow to the bit 7 position MSB After rotate and shift operations it contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag Zero Flag FLAGS 6 For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero Sign Flag FLAGS 5 Following arithmetic logic rotate or shift operations the sign bit identifies the state of the MSB of the result A logic zero indicates a positi
145. ctrical Data Overview Chapter 18 Mechanical Data Overview Chapter 19 S3F8275 F8278 F8274 Flash MCU Overview Operating Mode Characteristics Chapter 20 Development Tools Target Boards TB8275 8 4 Target Board SMDS2 Selection SAM8 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER List of Figures Figure Title Page Number Number 1 1 Block MBIEUII ME 1 3 1 2 3C8275 F8275 C8278 F8278 C8274 F8274 Pin Assignments 64 QFP 1420F 1 4 1 3 3C8275 F8275 C8278 F8278 C8274 F8274 Pin Assignments 64 LQFP 1010 1 5 1 4 Pin Circuit TypeA relier ecce P Is Poets E E 1 8 1 5 Pin Circuit Type B ARESE ritenere ete a 1 8 1 6 Pin Circuit Type EMA PO BT estoit het err EP Paneg tpe ete e SEU REPE AIRES 1 8 1 7 Pin Circuit HM erac recedere ohne eoa de 1 9 1 8 Pin Circuit Type H 8 P2 1 P2 7 1 9 1 9 Pin Circuit Type H 9 P4 P5 P6 nehmen eene 1 10 1 10 Pin Circuit Type H 10 P2 0 eec ete ee eta c Dn ve Ede M VR DRIN 1 11 2 1 Program Memory Address nhe nenne 2 2 2 2 Smart 2 3 2 3 Internal Register File Organizaion 5368275 2 6 2 4 Internal Register File Organization 53 8278 8274 2 7 2 5 Register Page Poi
146. d clock value is used The interrupt is then serviced When the return from interrupt IRET occurs the instruction immediately following the one that initiated idle mode is executed 8 6 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec PORTS PORTS OVERVIEW The S3C8275 C8278 C8274 microcontroller has seven bit programmable I O ports PO P6 Port 0 5 are 8 bit ports port 6 is 4 bit This gives a total of 52 I O pins Each port can be flexibly configured to meet application design requirements The CPU accesses ports by directly writing or reading port registers No special I O instructions are required All ports of the S3C8275 C8278 C8274 can be configured to input or output mode P2 P6 are shared with LCD signals Table 9 1 gives you a general overview of S3C8275 C8278 C8274 I O port functions Table 9 1 53C8275 C8278 C8274 Port Configuration Overview Configuration Options 1 bit programmable port Schmitt trigger input or push pull open drain output and software assignable pull ups Alternatively PO 0 P0 2 can be used as input for external interrupts INT and P0 3 P0 7 can be used as TAOUT TBOUT CLKOUT BUZ 1 bit programmable 1 port Schmitt trigger input or push pull open drain output and software assignable pull ups Alternatively P1 3 P1 7 can be used as input for external interrupts INT and P1 0 P1 2 can be used as SCK SO and SI 1 bit programmable
147. d register 02H from OFH to 10H NOTE A system malfunction may occur if you use a Zero Z flag FLAGS 6 result together with an INCW instruction To avoid this problem we recommend that you use INCW as shown in the following example LOOP INCW RRO LD R2 R1 OR R2 RO JR NZ LOOP ELECTRONS 6 45 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec IRET Interrupt Return IRET Operation Flags Format Example NOTE IRET Normal IRET Fast FLAGS SP PC IP SP SP 1 FLAGS lt FLAGS PC SP FIS 0 SP SP 2 SYM 0 lt 1 This instruction is used at the end of an interrupt service routine It restores the flag register and the program counter It also re enables global interrupts A normal IRET is executed only if the fast interrupt status bit FIS bit one of the FLAGS register OD5H is cleared 0 If a fast interrupt occurred IRET clears the FIS bit that was set at the beginning of the service routine All flags are restored to their original settings that is the settings before the interrupt occurred IRET Bytes Cycles Opcode Hex Normal opc 1 10 internal stack BF 12 internal stack IRET Bytes Cycles Opcode Hex Fast opc 1 6 BF In the figure below the instruction pointer is initially loaded with 100H in the main program before interrupts are enabled When an interrupt occurs the program counter and instruction pointer are swapped
148. data register a I Port 1 data register Port 2 data register v w I J Port 3 data register 71 A AR R Tl A am E Port 4 data register v AR a E Port 5 data register 246 External interrupt pending register EXTIPND 247 External interrupt control register high byte EXTICONH 248 External interrupt control register low byte EXTICONL 249 E z Port 6 data register J T aJ z Pon 2 data enter I 2 J Locations FAH are not mapped Locations FCH are not mapped Locations FEH are not mapped interrupt priority register FH w 4 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER Table 4 3 Set 1 Bank 1 Registers LCD control Register Watch timer control register Timer A counter Timer B counter Timer A data register Timer B data register Timer 1 A control register Timer B control register Clock output control register 32 E8H R W Port 4 control ase a 9 RW Por 4 contol register ow by pacon zw ow Fon em Port 5 contol register qow ye aw Pore convois Locations EEH EFH are not mapped Locations E5H FFH are not mapped NOTES 1 An means that the bit value is undefined
149. de Hex dst src 6 53 r Ir opc src dst 3 6 54 R R 55 R IR opc dst src 3 6 56 R IM Given R1 12H R2 register 01H 21H register 02H register OAH AND R1 R2 gt R1 02H R2 03H AND R1 R2 gt R1 02H R2 03H AND 01H 02H gt Register 01H 01H register 02H 03H gt gt ll AND 01H 02H Register 01H OOH register 02H AND 01H 25H Register 01H 21H In the first example destination work ing register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET BAND Bit AND BAND BAND Operation Flags Format Examples dst src b dst b src dst 0 lt dst 0 src b or dst b lt dst b src 0 The specified bit of the source or the destination is logically ANDed with the zero bit LSB of the destination or source The resultant bit is stored in the specified bit of the destination No other bits of the destination are affected The source is unaffected C Unaffected Z Set if the result is 0 cleared otherwise S Cleared to 0 V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src Opc dst b 0 src 3 6 67 ro Rb opc dst 3 6 67 Rb ro NOT
150. e byte programming and to make the flash memory into a hard lock protection Flash Memory Control Register FMCON FOH Set 1 Bank 1 R W Flash operation start bit 0 Operation stop 1 Operation start Flash memory mode selection bits This bit will be cleared automatically just 0101 Programming mode after the corresponding operation 1010 Erase mode completed 0110 Hard lock mode others Not available Not used for S3F8275 F8278 F8274 Sector erase status bit 0 Success sector erase 1 Fail sector erase Figure 16 1 Flash Memory Control Register FMCON The bit 0 of FMCON register 0 is a start bit for Erase and Hard Lock operation mode Therefore operation of Erase and Hard Lock mode is activated when you set FMCON 0 to 1 Also you should wait a time of Erase Sector erase or Hard lock to complete it s operation before a byte programming or a byte read of same sector area by using LDC instruction When you read or program a byte data from or into flash memory this bit is not needed to manipulate The sector erase status bit is read o nly If an interrupt is requested during the operation of Sector erase the operation of Sector Erase is discontinued and the interrupt is served by CPU Therefore the sector erase status bit should be checked after executing Sector Erase The Sector Erase operation is success if the bit is logic 0 and is failure if the bit is logic 1 NOTE When the
151. e 1CH in that same register The next example shows the effect an INC instruction has on register 00H assuming that it contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET INCW Increment Word INCW dst Operation dst dst 1 The contents of the destination which must be an even address and the byte following that location are treated as a single 16 bit value that is incremented by one Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 0 RR 8 Al IR Examples Given RO R1 02H register 02H OFH and register OFFH INCW RRO gt RO 1AH R1 03H INCW QHR1 gt Register 02H register 03 OOH In the first example the working register pair RRO contains the value 1AH in register RO and 02H in register R1 The statement INCW RRO increments the 16 bit destination by one leaving the value in register R1 In the second example the statement NCW R1 uses Indirect Register IR addressing mode to increment the contents of general register 03H from OFFH to 00H an
152. e of 127 to 128 ELECTRONS 6 31 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CPIJNE Compare Increment and Jump on Non Equal CPIJNE Operation Flags Format Example dst src RA If dst src 0 PC PC Ir e Ir 1 The source operand is compared to subtracted from the destination operand If the result is not 0 the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the CPIJNE instruction is executed In either case the source pointer is incremented by one before the next instruction No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src sre dst RA 3 12 D2 r Ir NOTE Execution time is 18 cycles if the jump is taken or 16 cycles if it is not taken Given R1 02H R2 and register 04H CPIJNE R1 R2 SKIP gt R2 04H PC jumps to SKIP location Working register R1 contains the value 02H working register R2 the source pointer the value 03H and general register 03 the value 04H The statement CPIJNE R1 R2 SKIP subtracts 04H 00000100B from 02H 00000010B Because the result of the comparison is non equal the relative address is added to the PC and the PC then jumps to the memory location pointed to by SKIP The source pointer register R2 is also incremented by one leaving a value of 04H Remem
153. e result is the same as the sign of the source cleared otherwise D Always set to 1 H Cleared if there is a carry from the most significant bit of the low order four bits of the result set otherwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 33 r Ir opc SIC dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Examples Given R1 10H R2 1 register 01H 20H register 02H and register O3H OAH SBC R1 R2 SBC R1 R2 SBC 01H 02H SBC 01H 02H R1 OCH R2 03H R1 05H R2 register 03H OAH Register 01H 1CH register 02H 03H Register 01H 15H register 02H register gt E 4 SBC 01H 8AH Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and the C flag value 1 from the destination 10H and then stores the result OCH in register R1 ELECTRONS 6 77 INSTRUCTION SET SCF set Carry Flag SCF Operation Flags Format Example 6 78 Ce 1 The carry flag C is set to logic one regardless of its previous value C Setto 1 No other flags are affected Bytes Cycles The statement SCF sets the carry flag to logic one 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Opcode Hex DF ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F
154. ecific interrupt level has more than one vector address the vector priorities are established in hardware A vector address can be assigned to one or more sources Levels Interrupt levels are the main unit for interrupt priority assignment and recognition All peripherals and I O blocks can issue interrupt requests In other words peripheral and I O operations are interrupt driven There are eight possible interrupt levels IRQOARQ7 also called level O4evel 7 Each interrupt level directly corresponds to an interrupt request number IRQn The total number of interrupt levels used in the interrupt structure varies from device to device The S3C8275 C8278 C8274 interrupt structure recognizes eight interrupt levels The interrupt level numbers 0 through 7 do not necessarily indicate the relative priority of the levels They are just identifiers for the interrupt levels that are recognized by the CPU The relative priority of different interrupt levels is determined by settings in the interrupt priority register IPR Interrupt group and subgroup logic controlled by IPR settings lets you define more complex priority relationships between different levels Vectors Each interrupt level can have one or more interrupt vectors or it may have no vector address assigned at all The maximum number of vectors that can be supported for a given level is 128 The actual number of vectors used for S3C8 series devices is always much smaller If an interrupt leve
155. ector location Fetch the service routine s low byte address from the vector location Rw Branch to the service routine specified by the concatenated 16 bit vector address NOTE 16 bit vector address always begins at an even numbered ROM address within the range of OOH FFH NESTING OF VECTORED INTERRUPTS It is possible to nest a higher priority interrupt request while a lower priority request is being serviced To do this you must follow these steps Push the current 8 bit interrupt mask register IMR value to the stack PUSH IMR Load the IMR register with a new mask value that enables only the higher priority interrupt Execute an El instruction to enable interrupt processing a higher priority interrupt will be processed if it occurs PO NS When the lower priority interrupt service routine ends restore the IMR to its original value by returning the previous mask value from the stack POP IMR 5 Execute an IRET Depending on the application you may be able to simplify the procedure above to some extent INSTRUCTION POINTER IP The instruction pointer IP is adopted by all the S3C8 series microcontrollers to control the optional high speed interrupt processing feature called fast interrupts The IP consists of register pair DAH and DBH The names of IP registers are IPH high byte IP15 IP8 and IPL low byte IP 7 IPO FAST INTERRUPT PROCESSING The feature called fast interrupt processing allows
156. ed by software by writing 0 to the timer 1 interrupt pending bit TACON O Timer 1 A Control Register TACON E6H Set 1 Bank 1 R W One 16 bit timer or Two 8 bit timers Timer 1 interrupt pending bit mode 0 No interrupt pending when read 0 Two 8 bit timers mode Timer A B Clear pending bit when write 1 One 16 bit timer mode Timer 1 1 Interrupt is pending when read No effect when write Timer 1 clock selection bits Timer 1 interrupt enable bit 000 fxx 512 0 Disable interrupt 001 fxx 256 1 Enable interrupt 010 fxx 64 011 fxx 8 Timer 1 counter enable bit 100 fxx 0 Disable counting operation 101 fxt sub clock 1 Enable counting operation 110 T1CLK external clock Timer 1 counter clear bit 111 Not available 0 No affect 1 Clear the timer 1 A counter when write Figure 11 1 Timer 1 A Control Register TACON 11 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec TIMER 1 0 6 4 Data Bus TACON 3 x XIN or XTIN MSB NT R TBCNT TAC TACON O Buffer Buffer Match Signal TBDATA TADATA Data Bus NOTE When one 16 bit timer mode TACON 7 lt 1 Timer 1 Figure 11 2 Timer 1 Block Diagram One 16 bit Mode ELECTRONICS 11 3 TIMER 1 63 8275 8275 8278 8278 8274 8274 Preliminary Spec TWO 8 BIT TIMERS MODE TIMER A and B OVERVIEW The 8 b
157. egister pointer to identify a specific 8 byte working register space in the internal register file and a specific 8 bit register within that space n Even address Figure 2 10 16 Bit Register Pair ELECTRONICS 2 15 ADDRESS SPACES 2 16 Special Purpose Registers General Purpose Register Pt Bank 1 Bank 1 Control Registers System Registers CFH Register Each register pointer RP can independently point to one of the 24 8 byte slices of the register file other than set 2 After a reset RPO points to locations COH C7H and RP1 to locations C8H CFH that is to the common working register area NOTE Inthe S3C8275 C8278 C8274 microcontroller pages 0 2 are implemented Pages 0 2 contain all of the addressable registers in the internal register file Page 0 Page 0 S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Indirect Register Register Addressing Only All Addressing Modes Can be Pointed by Register Pointer Figure 2 11 Register File Addressing Indexed Addressing Modes Addressing Modes e Can be Pointed to By register Pointer ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES COMMON WORKING REGISTER AREA COH CFH After a reset register pointers RPO and RP1 automatically select two 8 byte register slices in set 1 locations COH CFH as the active 16 byte working register block RPO
158. egisters TADATA and TBDATA The match signal generates corresponding match interrupt TAINT vector FOH TBINT vector F2H and clears the counter If for example you write the value 10H to TBDATA 0 to TACON 7 and OEH to TBCON the counter will increment until it reaches 10H At this point the TB interrupt request is generated the counter value is reset and counting resumes Timer A and B Control Register TACON TBCON You use the timer A and B control register TACON and TBCON to Enable the timer A interval timer mode and B operating interval timer mode Select the timer A and B input clock frequency Clear the timer A and B counter TACNT and TBCNT Enable the timer A and B interrupt Clear timer A and B interrupt pending condition 11 4 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec TIMER 1 TACON and TBCON are located in set 1 bank 1 at address E6H and E7H and is read write addressable using register addressing mode A reset clears TACON to 00H This sets timer A to disable interval timer mode selects an input clock frequency of fxx 512 and disables timer A interrupt You can clear the timer A counter at any time during normal operation by writing a 1 to TACON 3 A reset clears TBCON to 00H This sets timer B to disable interval timer mode selects an input clock frequency of fxx 512 and disables timer B interrupt You can clear the timer B counter at any time during nor
159. elative addressing mode Immediate addressing mode Immediate long addressing mode ELECTRONS See list of condition codes in Table 6 6 Rn n 0 15 Rn b n 0 15 b 0 7 Rn n 0 15 RRp p 0 2 4 14 reg or Rn reg 0 255 n 0 15 reg b reg 0 255 b 0 7 reg or RRp reg 0 254 even number only where 0 2 14 addr addr 0 254 even number only Rn n 0 15 Rn or reg reg 0 255 0 15 RRp p 0 2 14 RRp or reg reg 0 254 even only where 0 2 14 reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where p 0 2 14 addr RRp addr range 0 65535 where p 0 2 14 addr addr range 0 65535 addr addr number in the range 127 to 128 that is an offset relative to the address of the next instruction data data 0 255 data data range 0 65535 6 9 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 6 5 Opcode Quick Reference OPCODE MAP LOWER NIBBLE HEX DEC DEC ADD ADD ADD ADD ADD BOR R1 IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM r0 Rb RLC RLC ADC ADC ADC ADC ADC BCP R1 IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM r1 b R2 INC INC SUB SUB SUB SUB SUB BXOR R1 IR1 r1 r2 r1 lr2 R2 R1 IR2 R1 R1 IM r0 Rb SRP 0 1 SBC SBC IM j r1 lr2 IR2 R1 OR OR r1 Ir2 IR2 R1 rO POP POP AND AND AND AND AND BITC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 b COM
160. equest IRQ or an external reset operation In application programs a IDLE instruction must be immediately followed by at least three NOP instructions This ensures an adeguate time interval for the clock to stabilize before the next instruction is executed If three or more NOP instructons are not used after IDLE instruction leakage current could be flown because of the floating state in the internal bus Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F The instruction IDLE stops the CPU clock but not the system clock NOP NOP NOP ELECTRONES 6 43 INSTRUCTION SET INC Increment INC Operation Flags Format Examples 6 44 dst dst dst 1 The contents of the destination operand are incremented by one C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred cleared otherwise D Unaffected H Unaffected Bytes dst opc 1 opc dst 2 Cycles Opcode Hex 4 rE r OtoF 4 20 4 21 Given RO 1BH register OOH OCH and register 1BH OFH INC RO E RO 1CH INC 00H gt Register OOH ODH INC RO gt RO 1BH register 01H 10H 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Addr Mode dst r In the first example if destination working register RO contains the value 1BH the statement INC RO leaves the valu
161. eramic Oscillator fxt for Low Current XTIN XTouT Figure 7 6 External Oscillator fxt ELECTRONICS 3C8275 C8278 C8274 F8275 F8278 F8274 Preliminary Spec CLOCK CIRCUIT CLOCK STATUS DURING POWER DOWN MODES The two power down modes stop mode and Idle mode affect the system clock as follows In stop mode the main oscillator is halted Stop mode is released and the oscillator started by a reset operation or an external interrupt with RC delay noise filter In Idle mode the internal clock signal is gated to the CPU but not to interrupt structure timers and timer counters Idle mode is released by a reset or by an external or internal interrupt Stop Release Main System Sub system Oscillator Oscillator Circuit Circuit Watch Timer LCD Controller Selector 1 OSCCON 2 STOP OSC 1 1 1 4096 inst Basic Timer Timer Counters Frequency Watch Timer Dividing LCD Controller Circuit SIO 12 1 8 1 16 System Clock CPU Clock IDLE Instruction Figure 7 7 System Clock Circuit Diagram ELECTRONICS 7 3 CLOCK CIRCUIT 3C8275 C8278 C8274 F8 275 F8278 F8274 Preliminary Spec SYSTEM CLOCK CONTROL REGISTER CLKCON The system clock control register CLKCON is located in the set 1 address D4H It is read write addressable and has the following functions Oscillator IRQ wake up function enable disable Oscillator frequency divide by value CLKCON register settings co
162. erwise indicating a borrow Format Bytes Cycles Opcode Addr Mode Hex dst src 6 23 r Ir opc src dst 3 6 24 R R 25 R IR opc dst src 3 6 26 R IM Examples Given R1 12H R2 register 01H 21H register 02H register 03H OAH SUB R1 R2 gt R1 OFH R2 08H SUB R1 R2 gt R1 08H R2 03H SUB 01H 02H gt Register 01H 1EH register 02H 03H SUB 01H 02H gt Register 01H 17H register 02H 03H SUB 01H 90H gt Register 01H 91H C S and V 1 SUB 01H 65H Register 01H C and 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 6 82 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET SWAP swap Nibbles SWAP Operation Flags Format Examples dst dst 0 3 dst 4 7 The contents of the lower four bits and upper four bits of the destination operand are swapped C Undefined Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Undefined D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 FO R F1 IR Given Register OOH register 02H 03H and register 03H OA4H SWAP gt Register OOH
163. execution in the tool program mode or user program mode In terms of user program mode the procedure of setting Hard Lock Protection is following that Whereas in tool mode the manufacturer of serial tool writer could support Hardware Protection Please refer to the manual of serial program writer tool provided by the manufacturer The Program Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User Programming Enable Register FMUSR to 00000000B 557 PROGRAMMING TIP Hard Lock Protection SB1 LD FMUSR 0A5H User program mode enable LD FMCON 01100001B Hard Lock mode set amp start NOP Dummy instruction this instruction must be needed LD FMUSR 0 User program mode disable ELECTRONES 16 11 EMBEDDED FLASH MEMORY INTERFACE 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NOTES 16 12 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ELECTRICAL DATA OVERVIEW ELECTRICAL DATA In this chapter S8C8275 C8278 C8274 electrical characteristics are presented in tables and graphs The information is arranged in the following order Absolute maximum ratings D C electrical characteristics Data retention supply voltage in Stop mode Stop mode release timing when initiated by an external interrupt Stop mode release timing when initiated by a Reset I O ca
164. fected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise a 0 is stored Flags C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir opc src dst 3 6 44 R R 45 R IR opc dst src 3 6 46 R IM Examples Given RO 15H R1 2AH R2 01H register OOH 08H register 01H 37H and register 08H 8AH OR RO R1 gt RO 3FH R1 2AH OR RO R2 E RO 37H R2 OtH register 01H 37H OR 00H 01H gt Register OOH register 01H 37H OR 01H 00H gt Register OOH O8H register 01H OBFH OR 00H 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 the value 2AH the statement OR RO R1 logical ORs the RO and R1 register contents and stores the result in destination register RO The other examples show the use of the logical OR instruction with the various addressing modes and formats 6 62 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET POP Pop From Stack POP Operation Flags Format Examples dst dst SP SP lt SP 1 The contents of the location addressed by the stack pointer are loaded into the destination The stack pointer
165. ft through Carry 6 72 Inter Mrro pM mE 6 73 Rotate Right through Carry nennen 6 74 Select Bank 0 editio e hd dice m e pera endis hour n e pee rates 6 75 Select Bank nee tate dE hemisferio 6 76 Subtract with toos te ied Er et ront e RISE ua RE IR RARE M 6 77 Set Carry Flag einer ep ect tpe ee suns delaras 6 78 Shift Right 224 ee een eee 6 79 Set Register Pointer corsi ie Deed ate dehy 6 80 Stop Operations i ER pepe S Bc eed epo od Hast crede Lund dde deba 6 81 SUbIFact s nie dr o e E us D Ee D ee Dacos Ps 6 82 SwWap NIDbIeS epu Red BI Sad egere aes 6 83 Test Complement under 6 84 Test under Mask rettet Pe EM eerte aeai 6 85 Wait for Interr pE uei ertet Rl RU eR 6 86 Logical Exclusive OR 4 eie nte bel xxi OR IE ee eee 6 87 3C8275 F8275 C82 78 F8278 C827 4 F8274 MICROCONTROLLER 53 8275 8275 8278 8278 8274 8274 Preliminary Spec PRODUCT OVERVIEW PRODUCT OVERVIEW S3C8 SERIES MICROCONTROLLERS Samsung s S3C8 series of 8 bit single chip CMOS microcontrollers offers a fast and efficient CPU a wide range of integrated peripherals and var
166. gisters TADATA and TBDATA The match signal generates a timer 1 match interrupt and clears the counter If for example you write the value 32H and 10H to TADATA and TBDATA respectively and 8EH to TACON the counter will increment until it reaches 3210H At this point the timer 1 interrupt request is generated the counter value is reset and counting resumes ELECTRONICS 11 1 TIMER 1 3C8275 F8275C8278 F8278 C8274 F8274 Preliminary Spec Timer 1 Control Re gister TACON You use the timer 1 control register TACON to Enable the timer 1 operating interval timer Select the timer 1 input clock frequency Clear the timer 1 counter TACNT and TBCNT Enable the timer 1 interrupt Clear timer 1 interrupt pending conditions TACON is located in set 1 bank 1 at address E6H and is read write addressable using register addressing mode A reset clears TACON to 00H This sets timer 1 to disable interval timer mode selects an input clock frequency of fxx 512 and disables timer 1 interrupt You can clear the timer 1 counter at any time during the normal operation by writing a 1 to TACON 3 To enable the timer 1 interrupt IRQ 0 vector FOH you must write TACON 7 TACON 2 and TACON 1 to 1 To generate the exact time interval you should write TACON 3 0 to which cleared counter and interrupt pending bit When the T1INT sub routine has been serviced the pending condition must be clear
167. gram Memory or 1 of 4 Data Memory address LSB Selects Program Memory points to or program Data Memory memory or data eh Value used in OPERAND Instruction Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to Program or Data Memory 3 6 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESSING MODES INDEXED ADDRESSING M ODE X Indexed X addressing mode adds an offset value to a base address during instruction execution in order to calculate the effective operand address see Figure 3 7 You can use Indexed addressing mode to access locations in the internal register file or in external memory Please note however that you cannot access locations COH FFH in set 1 using Indexed addressing mode In short offset Indexed addressing mode the 8 bit displacement is treated as a signed integer in the range 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to that base address see Figure 3 9 The only instruction tha
168. h timer INT clear frequency dividing circuits 1 Enable watch timer Buzzer signal selection bits 00 0 5 kHz 01 1 kHz 10 2 kHz 11 4 kHz Watch timer speed selection bits 00 Set watch timer interrupt to 1 s 01 Set watch timer interrupt to 0 5 s 10 Set watch timer interrupt to 0 25 s 11 Set watch timer interrupt to 3 91 ms Figure 12 1 Watch Timer Control Register WTCON 12 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec WATCH TIMER WATCH TIMER CIRCUIT DIASGRAM WTCON S 5 WTCON 4 WTCON 3 WTCON 1 1 WTCON 0 Pending Bit ELECTRONICS WT INT Enable BUZ P0 7 WTCON 6 6 fw 64 0 5 kHz Wine M fw 16 5 fw 8 4 kHz Dividing 32 768 kHz Circuit Clock Selector fLcD 2048 Hz fx 128 fx Main clock where fx 4 19 MHz fxt Sub clock 32 768 Hz fw Watch timer frequency Figure 12 2 Watch Timer Circuit Diagram 12 3 WATCH TIMER 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NOTES 12 4 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LCD CONTROLLER DRIVER LCD CONTROLLER DRIVER OVERVIEW The S3C8275 C8278 C8274 microcontroller can directly drive an up to 128 dot 32 segments x 4 commons LCD panel Its LCD block has the following components LCD controller driver Display RAM 00 of page 2 for storing dis
169. hen read Clear pending bit when write Interrupt is pending when read ELECTRONICS 4 41 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SPH stack Pointer High Byte D8H Set 1 Reset Value X X X X X x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address High Byte The high byte stack pointer value is the upper eight bits of the 16 bit stack pointer address SP15 SP8 The lower byte of the stack pointer value is located in register SPL D9H The SP value is undefined following a reset SPL stack Pointer Low Byte D9H Set 1 Reset Value X X X x X X x Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 Stack Pointer Address Low Byte The low byte stack pointer value is the lower eight bits of the 16 bit stack pointer address SP7 SPO The upper byte of the stack pointer value is located in register SPH D8H The SP value is undefined following a reset 4 42 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER STPCON Stop Control Register FBH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 0 STOP Control Bits 10100101 Enable stop instruction Other values Disable stop instruction NOTE Before execute the STOP instruction set this STPCON
170. ination register 01H contains the value 03H 00000011 and the source working register R1 the value 07H 00000111B The statement BOR 01H 2 R1 logically ORs bit two of register 01H destination with bit zero of R1 source This leaves the value 07H in register 01H ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET BTJ RF Bit Test Jump Relative on False BTJRF Operation Flags Format Example dst src b If src b is a 0 then PC PC dst The specified bit within the source operand is tested If it is a 0 the relative address is added to the program counter and control passes to the statement whose address is now in the PC otherwise the instruction following the BTJRF instruction is ex ecuted No flags are affected Bytes Cycles Opcode Addr Mode Note 1 Hex dst src opc dst 3 10 37 RA rb NOTE the second byte of the instruction format the source address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H BTJRF SKIP R1 3 gt PC jumps to SKIP location If working register R1 contains the value 07H 000001 11B the statement BTJRF SKIP R1 3 tests bit 3 Because it is O the relative address is added to the PC and the PC jumps to the memory location pointed to by the SKIP Remember that the memory location must be within the allowed range of 127 to 128 ELECTRONS 6 23 INSTRUCT
171. individual port 1 pins Port 1 Interrupt Control gisters EXTICONL 7 6 EXTIPND 7 3 To process external interrupts at the port 1 pins two additional control registers are provided the port 1 interrupt control register EXTICONH EXTICONL 7 6 F8H F9H set 1 bank 0 the port 1 interrupt pending bits EXTIPND 7 3 F7H set 1 bank 0 The port 1 interrupt pending register bits lets you check for interrupt pending conditions and clear the pending condition when the interrupt service routine has been initiated The application program detects interrupt requests by polling the EXTIPND 7 3 register at regular intervals When the interrupt enable bit of any port 1 pin is 1 a rising or falling edge at that pin will generate an interrupt request The corresponding EXTIPND bit is then automatically set to 1 and the IRQ level goes low to signal the CPU that an interrupt request is waiting When the CPU acknowledges the interrupt request application software must the clear the pending condition by writing a to the corresponding EXTIPND bit ELECTRONICS 9 7 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Port 1 Control Register High Byte P1CONH E7H Set 1 Bank 0 R W P1 7 INT7 P1 6 INT6 P1 5 INT5 P1 4 INT4 P1CONH bit pair pin configuration settings Schmitt trigger input mode N channel open drain output mode Push pull output mode Not available Figure 9 7 Port 1 High
172. ings 0 No interrupt pending when read clear pending bit when write 1 Interrupt is pending when read Figure 9 6 External Interrupt Pending Register EXTIPND 9 6 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORTS PORT 1 Port 1 is an 8 bit I O port with individually configurable pins Port 1 pins are accessed directly by writing or reading the port 1 data register P1 at location F1H in set 1 bank 0 1 0 1 7 can serve as inputs with or without pull up as outputs push pull or open drain or you can be configured the following functions Lownibble pins P1 0 P1 3 SCK SO SI INT3 High nibble pins 1 4 1 7 INTA INT7 Port 1 Control Register P1CONH P1CONL Port 1 has two 8 bit control register PI CONH for P1 4 P1 7 and P1CONL for P1 0 P1 3 A reset clears the P1CONH and P1CONL registers to configuring P1 3 P1 7 pins to input mode with interrupt and 1 0 1 2 input mode You use control register setting to select input or output mode push pull or open drain and enable the alternative functions When programming this port please remember that any alternative peripheral I O function you configure using the port 1 control register must also be enabled in the associated peripheral module Port 1 Pull up Resistor Control Register P1PUR Using the port 1 pull up resistor control register P1 PUR E9H set 1 bank 0 you can configure pull up resistors to
173. ion 2 0 V 3 6 V 32 32 768 35 kHz TUN frequency OSCCON 7 0b co 2 2 V 3 6V 32 32 768 35 OSCCON 7 1b External XT y input 20 3 6 32 100 clock XTIN frequency XT OUT 17 10 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec ELECTRICAL DATA Table 17 10 Main Oscillation Stabilization Time TA 25 C to 85 Vpp 20 V to 3 6 V 7 min 7 We ws Ceramic Oscillation stabilization occurs when Vpp is 10 ms equal to the minimum oscillator voltage range External clock Xy input high and low width t4 ty 1250 VDD 0 1 V Figure 17 7 Clock Timing Measurement at ELECTRONICS 17 11 ELECTRICAL DATA 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 17 11 Sub Oscillation Stabilization Time TA 25 C to 85 Vpp 2 0 V to 3 6 V Test Condition XTy input high and low width tx VDD 0 1 V Figure 17 8 Clock Timing Measurement at XT iN 17 12 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec ELECTRICAL DATA Instruction Clock fx Main Sub oscillation frequency 2 MHz 8 MHz 1 05 MHz 4 2 MHz 6 25 kHz main 8 2 kHz sub 400 kHz main 32 8 kHz sub i 4 2 5 3 6 Supply Voltage V Instruction Clock 1 4n x oscillator frequency n 1 2 8 16 Figure 17 9 Operating Voltage Range Table 17 12 AC Electrical Characteristics for Internal
174. ion format was used The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed Assuming that the contents of the program counter and stack pointer are the same as in the first example if program address 0040H contains 35H and program address 0041H contains 21H the statement CALL 40H produces the same result as in the second example ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET CCF Complement Carry Flag CCF Operation Flags Format Example C e NOT The carry flag C is complemented If 1 the value of the carry flag is changed to logic zero if C O the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given The carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one ELECTRONS 6 27 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CLR clear CLR dst Operation dst lt 0 Flags Format Examples 6 28 The destination location is cleared to 0 No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 BO R 4 B1 IR Given Register OOH 4FH register 01H 02H and register 02H CLR OOH gt Register OOH OOH CLR Q01H
175. ions and read write characteristics of all mapped registers in the S8C8275 C8278 C8274 register file are listed in Table 4 1 The hardware reset value for each mapped register is described in Chapter 8 RESET and Power Down Table 4 1 Set 1 Registers Locations DOH D2H are not mapped Basic timer control register BTCON 211 D3H RAN Re tM Stack pointer high byte 206 RW instruction pointer high byte as DM RW wu n System mode register Register page pointer Pe 23 216 218 ma m xm 223 ELECTRONICS 4 1 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 4 2 Set 1 Bank 0 Registers Register Name Address OSCCON SIOCON SIODATA SIO pre scaler register SIOPS Port 0 control register high byte POCONH Port 0 control register low byte POCONL POPUR Port 1 control register high byte P1CONH Port 1 control register low byte P1CONL 232 Port 1 pull up resistor enable register P1PUR 233 Port 2 control register high byte P2CONH 234 Port 2 control register low byte P2CONL 235 Oscillator control register SIO control register SIO data register Port 0 pull up resistor enable register k Port 2 pull up resistor enable register Port 3 control register high byte Port 3 control register low byte Port 3 Pull up resistor enable register Tl J Port 0
176. ious mask programmable ROM sizes Among the major CPU features are Efficient register oriented architecture Selectable CPU clock sources 1 and Stop power down mode release by interrupt or reset Built in basic timer with watchdog function A sophisticated interrupt structure recognizes up to eight interrupt levels Each level can have one or more interrupt sources and vectors Fast interrupt processing within a minimum of four CPU clocks can be assigned to specific interrupt levels 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER S3C8275 F8275 C8 278 F8278 C8274 F8274 single chip CMOS microcontrollers are fabricated using the highly advanced CMOS process based on Samsung s latest CPU architecture S3C8275 C8278 C8274 is a microcontroller with 16 8 4K byte mask programmable ROM embedded The S3F8275 F8278 F8274 is a microcontroller with a 16 8 4K byte flash ROM embedded Using a proven modular design approach Samsung engineers have successfully developed the 53 8275 8275 8278 8278 8274 8274 by integrating the following peripheral modules with the powerful SAM8 core Seven programmable I O ports including six 8 bit ports and one 4 bit port for a total of 52 pins Eight bit programmable pins for external interrupts One 8it basic timer for oscillation stabilization and watchdog function system reset Two 8 bit timer counter with selectable operating modes
177. ir pin configuration settings Input mode N channel open drain output mode Push pull output mode Alternative fumction SEG16 SEG19 Figure 9 16 Port 3 High Byte Control Register PSCONH ELECTRONICS 9 13 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Port Control Register Low Byte P3CONL EEH Set 1 Bank 0 R W P3 3 SEG20 P3 2 SEG21 P3 1 SEG22 P3 0 SEG23 P3CONL bit pair pin configuration settings Input mode N channel open drain output mode Push pull output mode Alternative function SEG20 SEG23 Figure 9 17 Port 3 Low Byte Control Register P3CONL Port 3 Pull up Control Register P3PUR EFH Set 1 Bank 0 R W P3 7 P3 6 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 P3PUR bit configuration settings 0 Disable pull up resistor Enable pull up resistor NOTE A pull up resistor of port is automatically disabled when the corresponding pin is selected as push pull output or alternative function Figure 9 18 Port Pulkup Control Register P3PUR 9 14 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORTS PORT 4 Port 4 is an 8 bit I O port with individually configurable pins Port 4 pins are accessed directly by writing or reading the port 4 data register P4 at location in set 1 bank 0 P4 0 P4 7 can serve as inputs with or without pull up as push pull output or you can be configured the following functions Low nibble pins 4 0 4 3 SEG
178. is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction ELECTRONS 6 13 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADC Add with carry ADC dst src Operation dst dst src c The source operand along with the setting of the carry flag is added to the destination operand and the sum is stored in the destination The contents of the source are unaffected Two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried into the addition of high order operands Flags C Setif there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is 0 cleared otherwise S Setif the result is negative cleared otherwise V Setif arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise D Always cleared to O H Setif there is a carry from the most significant bit of the low order four bits of the result
179. is then incremented by one No flags affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 8 50 R 51 IR Given Register OOH 01H register 01 1BH SPH 0D8H OOH SPL 0D9H OFBH and stack register OFBH 55H POP 00H gt Register OOH 55H SP OOFCH POP 00H gt Register OOH 01H register 01H 55H SP OOFCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location OOFBH 55H into destination register OOH and then increments the stack pointer by one Register 00H then contains the value 55H and the SP points to location OOFCH ELECTRONS 6 63 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec POPUD Pop User Stack Decrementing POPUD Operation Flags Format Example dst src dst lt src IR lt IR 1 This instruction is used for user defined stacks in the register file The contents of the register file location addressed by the user stack pointer are loaded into the destination The user stack pointer is then decremented No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc src dst 3 8 92 R IR Given Register OOH 42H user stack pointer register register 42H 6FH and register 02H 70H POPUD 02H Q00H Register OOH 41H register 02H 6FH register 42H 6FH If general register 00H contains the value 42H and register 42H the value 6FH the statement
180. ister 16 bytes Figure 2 4 Internal Register File Organization S3C8278 C8274 ELECTRONICS ADDRESS SPACES 3C8275 F8275 C8278 F8278C8274 F8274 Preliminary Spec REGISTER PAGE POINTER PP The S3C8 series architecture supports the logical expansion of the physical 256 byte internal register file using an 8 bit data bus into as many as 16 separately addressable register pages Page addressing is controlled by the register page pointer PP DFH In the 53 8275 8278 8274 microcontroller a paged register file expansion is implemented for LCD data registers and the register page pointer must be changed to address other pages After a reset the page pointer s source value lower nibble and the destination value upper nibble are always 0000 automatically selecting page 0 as the source and destination page for register addressing Register Page Pointer PP DFH Set 1 R W Source register page selection bits 0000 Source Page 0 0001 Source Page 1 Not used for the S3C8278 C8274 0010 Source Page 2 others Not used for the S3C8275 C8278 C8274 Destination register page selection bits 0000 Destination Page 0 0001 Destination Page 1 Not used for the S3C8278 C8274 0010 Destination Page 2 others Not used for the S3C8275 C8278 C8274 NOTES 1 In the S3C8275 microcontroller the internal register file is configured as three pages Pages 0 2 The pages 0 1 are used for general purpose
181. ister P6CON Port 6 has a 8 bit control register 6 for P6 0 P6 3 A reset clears the P6CON register to configuring all pins to input mode You use control registers setting to select input with or without pull up or push pull output mode and enable the alternative functions Port 6 Control Register PECON EDH Set 1 Bank 1 R W 6 6 2 2 P6 1 COM1 P6 0 COMO P6CON bit pair pin configuration settings Input mode Input with pull up resistor Push pull output mode Alternative function Figure 9 23 Port 6 Control Register ELECTRONICS 9 17 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec NOTES ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec BASIC TIMER BASIC TIMER OVERVIEW Basic timer BT can be used in two different ways As a watchdog timer to provide an automatic reset mechanism in the event of a system malfunction To signal the end of the required oscillation stabilization interval after a reset or a stop mode release The functional components of the basic timer block are Clock frequency divider fx divided by 4096 1024 128 or 16 with multiplexer 8 bit basic timer counter BTCNT Get 1 bank 0 read only Basic timer control register BTCON Get 1 read write ELECTRONICS 10 1 BASIC TIMER 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec
182. it rotated from the least significant bit position bit zero was 1 Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO R 4 E1 IR Given Register OOH register 01H 02H and register 02H 17H RR 00H gt Register 00H 98H C 1 RR 01H gt Register 01H 02H register 02H 8BH C 1 In the first example if general register 00H contains the value 31H 00110001B the statement RR 00H rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are also set to 1 ELECTRONS 6 73 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RRC Rotate Right Through Carry RRC dst Operation dst 7 C lt dst 0 dst n lt dst n 1 06 The contents of the destination operand and the carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of the carry flag replaces bit 7 MSB Flags C Setif the bit rotated from the least significant bit position bit zero
183. it timer A and B are the 8 bit general purpose timers Timer A and B have the interval timer mode by using the appropriate TACON and TBCON setting respectively Timer A and B have the following functional components Clock frequency divider with multiplexer fxx divided by 512 256 64 8 or 1 fxt and T1CLK External clock for timer A fxx divided by 512 256 64 or 8 and fxt for timer B 8 counter TACNT TBCNT 8 bit comparator and 8 bit reference data register TADATA TBDATA Timer A have I O pin for match output TAOUT Timer A match interrupt IRQ 0 vector FOH generation Timer A control register TACON set 1 bank 1 E6H read write Timer B have pin for match output TBOUT Timer B match interrupt IRQ 0 vector F2H generation Timer B control register TBCON set 1 bank 1 E 7H read write FUNCTION DESCRIPTION Interval Timer Function The timer A and B module can generate an interrupt the timer A match interrupt TAINT and the timer B match interrupt TBINT TAINT belongs to the interrupt level IRQ 0 and is assigned a separate vector address FOH TBINT belongs to the interrupt level IRQ 0 and is assigned a separate vector address F2H The TAINT and TBINT pending condition should be cleared by software after they are serviced In interval timer mode a match signal is generated when the counter value is identical to the values written to the TA or TB reference data r
184. ite sign cleared otherwise D Always cleared to O H Setif a carry from the low order nibble occurred Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir opc SIC dst 3 6 04 R R 6 05 R IR opc dst src 3 6 06 R IM Given R1 12H R2 register 01H 21H register 02H register OAH ADD R1 R2 ADD R1 R2 ADD 01H 02H ADD 01H 02H ADD 01H 425H R1 15H R2 R1 1CH R2 03H Register 01H 24H register 02H 03H Register 01H 2BH register 02H 03H Register 01H 46H 4 4 ld In the first example destination working register R1 contains 12H and the source working register R2 contains The statement ADD R1 R2 adds to 12H leaving the value 15H in register R1 ELECTRONS 6 15 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec AND Logical AND AND Operation Flags Format Examples dst src dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a O bit value is stored The contents of the source are unaffected C Unaffected Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Always cleared to 0 D Unaffected H Unaffected Bytes Cycles Opcode Addr Mo
185. its of the register address 011 are provided by the three low order bits of the 8 bit instruction address The five address bits from RP1 and the three address bits from the instruction are concatenated to form the complete register address OABH 10101011B Selects RPO or Address These address 1 bits indicate 8 bit 8 bit logical working register address addressing Register pointer Three low order bits provides five high order bis bits HHHH 8 bit physical address Figure 2 15 8 Bit Working Register Addressing 2 20 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES 8 bit address Register form instruction 10101 address LD R11 R2 OABH Specifies working register addressing Figure 2 16 8 Bit Working Register Addressing Example ELECTRONICS 2 21 ADDRESS SPACES S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SYSTEM AND USER STACK The S3C8 series microcontrollers use the system stack for data storage subroutine calls and returns The PUSH and POP instructions are used to control system stack operations Th e S3C8275 C8278 C8274 architecture supports stack operations in the internal register file Stack Operations Return addresses for procedure calls interrupts and data are stored on the stack The contents of the PC are saved to stack by a CALL instruction and restored by the RET instruction When an interrupt occu
186. l has more than one vector address the vector priorities are set in hardware S3C8275 C8278 C8274 uses twelve vectors Sources A source is any peripheral that generates an interrupt A source can be an external pin or a counter overflow Each vector can have several interrupt sources In the S3C8275 C8278 C8274 interrupt structure there are twelve possible interrupt sources When a service routine starts the respective pending bit should be either cleared automatically by hardware or cleared manually by program software The characteristics of the source s pending mechanism determine which method would be used to clear its respective pending bit ELECTRONICS 5 1 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec INTERRUPT TYPES The three components of the S3C8 interrupt structure described before levels vectors and sources are combined to determine the interrupt structure of an individual device and to make full use of its available interrupt logic There are three possible combinations of interrupt structure components called interrupt types 1 2 and 3 The types differ in the number of vectors and interrupt sources assigned to each level see Figure 5 1 Type 1 One level IRQn one vector V4 one source S4 Type 2 One level IRQn one vector V4 multiple sources Sn Type 3 One level IRQn multiple vectors V 4 Vp multiple sources 4 95 Snem In the S3C827
187. lation 17 10 17 10 Main Oscillation Stabilization 17 11 17 11 Sub Oscillation Stabilization 17 12 17 12 AC Electrical Characteristics for Internal Flash 17 13 19 1 Descriptions of Pins Used to Read Write the Flash 19 4 19 2 Comparison of 53 8275 8278 8274 S3C8275 C8278 C8274 Features 19 4 19 3 Operating Mode Selection 19 5 19 4 D C Electrical 19 6 20 1 Power Selection Settings for 8275 8 4 20 4 20 2 Main clock Selection Settings for 8275 8 4 20 4 20 3 Select Smart Option Source Setting for 8275 8 4 20 5 20 4 Smart Option Switch Settings for 8275 8 4 20 5 20 5 Device Selection Settings for TB 8275 8 4 20 6 20 6 The SMDS2 Tool Selection 20 6 xvi 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER List of Programming Tips Description Page Number Chapter 2 Address Spaces Using the Page Pointer for RAM Clear Page 0 1 2 9 Setting the Register
188. lation Then after a certain number of machine cycles has elapsed select the main clock by setting OSCCON O to 0 59 PROGRAMMING Switching the CPU clock 1 This example shows how to change from the main clock to the sub clock MA2SUB LD OSCCON 01H Switches to the sub clock Stop the main clock oscillation RET 2 This example shows how to change from sub clock to main clock SUB2MA AND OSCCON 07H Start the main clock oscillation CALL DLY16 Delay 16 ms AND OSCCON 06H Switch to the main clock RET DLY16 SRP 0COH LD R0 4 20H DEL NOP DJNZ RO DEL RET ELECTRONICS 7 7 CLOCK CIRCUIT 3C8275 C8278 C8274 F8 275 F8278 F8274 Preliminary Spec STOP Control Register STPCON FBH Set 1 Bank 0 R W STOP control bits Other values Disable STOP instruction 10100101 Enable STOP instruction NOTE Before execute the STOP instruction set this STPCON register as 10100101B Otherwise the STOP instuction will not execute as well as reset will be generated Figure 7 12 STOP Control Register STPCON 7 8 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RESET and POWER DOWN RESET and POWER DOWN SYSTEM RESET OVERVIEW During a power on reset the voltage at Vpp goes to High level and the nRESET pin is forced to Low level The nRESET signal is input through a schmitt trigger circuit where it is then synchronized with the CPU clock This procedure brings the S3C8275 C8278 C
189. lears the pending bit to 0 This type of pending bit is not mapped and cannot therefore be read or written by application software Pending Bits Cleared by the Service Routine The second type of pending bit is the one that should be cleared by program software The service routine must clear the appropriate pending bit before a return from interrupt subroutine IRET occurs To do this a 0 must be written to the corresponding pending bit location in the source s mode or control register 5 14 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INTERRUPT STRUCTURE INTERRUPT SOURCE POLLING SEQUENCE The interrupt request polling and servicing sequence is as follows 1 A source generates an interrupt request by setting the interrupt request bit to 1 The CPU polling procedure identifies a pending condition for that source The CPU checks the source s interrupt level The CPU generates an interrupt acknowledge signal Interrupt logic determines the interrupt s vector address The service routine starts and the source s pending bit is cleared to 0 by hardware or by software The CPU continues polling for interrupt requests INTERRUPT SERVICE ROUTINES Before an interrupt request is serviced the following conditions must be met Interrupt processing must be globally enabled El SYM O 1 The interrupt level must be enabled IMR register The interrupt level must have the highest
190. lock is generated by watch timer clock fw The watch timer should be enabled when the LCD display is turned on LCD Control Register LCON EOH Set 1 Bank 1 R W Internal LCD dividing register bits 1 display control bit 0 Enable internal LCD dividing resistors 0 Turn display off 1 Disable internal LCD dividing resistors Turn off the P Tr Turn display on LCD clock selection bits Not used cee 00 fw 2 64 Hz 01 fw 28 128 Hz LCD duty and bias selection bits 10 fw 2 256 Hz 000 1 4 duty 1 3 bias 11 fw 2 512 Hz 001 1 3 duty 1 3 bias 010 1 3 duty 1 2 bias 011 1 2 duty 1 2 bias 1xx static NOTE X means don t care Figure 13 4 LCD Control Register LCON 13 4 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LCD VOLTAGE DIVIDING RESISTOR Static and 1 3 Bias 3C8275 8 4 _o lt LCON 0 LCON 7 0 Enable internal resistors Voltage Dividing Resistor Adjustment 3C8275 8 4 LCON 7 1 Disable internal resistors LCD CONTROLLER DRIVER 1 2 Bias 3C8275 8 4 lt LCON 0 LCON 7 0 Enable internal resistors 1 Internal LCD dividing resistors The resistors can be disconnected by LCON 7 2 R External LCD dividing resistors Figure 13 5 Internal Voltage Dividing Resistor Connection ELECTRONS 13 5 LCD CONTROLLER DRIVER 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec COMMON COM SIGNALS The
191. lue 33H NOTE A system malfunction may occur if you use a Zero flag FLAGS 6 result together with a DECW instruction To avoid this problem we recommend that you use DECW as shown in the following example LOOP DECW RRO LD R2 R1 OR R2 RO JR NZ LOOP 6 36 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET DI Disable Interrupts DI Operation Flags Format Example SYM 0 lt 0 Bit zero of the system mode control register SYM 0 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F Given SYM 01H DI If the value of the SYM register is 01H the statement DI leaves the new value 00H in the register and clears SYM 0 to 0 disabling interrupt processing Before changing IMR interrupt pending and interrupt source control register be sure DI state ELECTRONS 6 37 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec DIV Divide Unsigned DIV Operation Flags Format Examples 6 38 dst src dst src dst UPPER REMAINDER dst LOWER lt QUOTIENT The destination operand 16 bits is divided by the source operand 8 bits The quotient 8 bits is stored in the lower half of the destina
192. ly an 8 bit address is supplied in the instruction the upper bytes of the destination address are assumed to be all zeros Program Memory Next Instruction LSB Must be Zero Current OPCODE Instruction Lower Address Byte Program Memory Upper Address Byte Locations 0 255 Sample Instruction CALL 40H The 16 bit value in program memory addresses 40H and 41H is the subroutine start address Figure 3 12 Indirect Addressing 3 12 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESSING MODES RELATIVE ADDRESS MODE RA In Relative Address RA mode a twos complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result is the address of the next instruction to be executed Before this addition occurs the PC contains the address of the instruction immediately following the current instruction Several program control instructions use the Relative Address mode to perform conditional jumps The instructions that support RA addressing are BTJRF BTJRT DJNZ CPIJE CPIJNE and JR Program Memory Next OPCODE Program Memory Address Used Z Loo PC Value 7 Displacement Current Instruction Signed la Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 13 Relative Addressing FI ADDRESSING MOD
193. mal operation by writing a 1 to TBCON 3 To enable the timer A interrupt TAINT and timer B interrupt TBINT you must write TACON 7 to 0 TACON 2 TBCON 2 and TACON 1 TBCON 1 to 1 To generate the exact time interval you should write TACON 3 TBCON 3 and 0 0 which cleared counter and interrupt pending bit When the TAINT and sub routine has been serviced the pending condition must be cleared by software by writing a 0 to the timer A and B interrupt pending bit 0 and 0 Timer A Control Register TACON E6H Set 1 Bank 1 R W One 16 bit timer or Two 8 bit timers mode Timer A interrupt pending bit 0 No interrupt pending when read 0 Two 8 bit timers mode Timer A B 1 One 16 bit timer mode Timer 1 Timer A clock selection bits 000 fxx 512 001 fxx 256 010 fxx 64 011 fxx 8 100 fxx 101 fxt sub clock 110 T1CLK external clock 111 Not available Clear pending bit when write 1 Interrupt is pending when read No effect when write Timer A interrupt enable bit 0 Disable interrupt 1 Enable interrupt Timer A counter enable bit 0 Disable counting operation 1 Enable counting operation Timer A counter clear bit 0 No affect 1 Clear the timer 1 A counter when write Figure 11 3 Timer 1 A Control Register TACON ELECTRONICS TIMER 1 63 8275 8275 8278 8278 8274 8274 Preliminary Spec
194. mart Option is selected Select Smart Option Source by external smart option Internal jee External TB8275 8 4 switch SW1 this selection is not available dict smart The Smart Option is selected Option Source Taroet by internal smart option area internal aO Exora TB8275 8 4 003EH 003FH of ROM But Table 20 4 Smart Option Switch Settings for TB8275 8 4 Smart Opting Settings Comments Smart Option The Smart Option is selected by this switch when the Smart Option Low 0 source is selected by external The 2 0 are comparable to the iln High t 003EH 2 0 The B7 B5 are comparable to the 003EH 7 5 The B8 is comparable to the 003FH 0 The B4 B3 is not connected N a ELECTRONES 20 5 DEVELOPMENT TOOLS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 20 5 Device Selection Settings for TB 8275 8 4 Device Selection Operating Mode Comments Settings Operate with TB8275 Device Selection S3F8278 4 2 53 8275 TB8275 E Operate with 8278 4 evice Selection S3F8278 4 e of S3F8275 Target TB827814 1 system SMDS2 SELECTION 8 In order to write data into program memory that is available in SMDS2 the target board should be selected to be for SMDS2 through a switch as follows Otherwise the program memory writing function is not available Table 20 6 The SMDS2 Tool Selection Setting JP2 Setting Operating Mode JP2 SMDS2 ee SMDS2 R
195. ms intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product 3C8275 F8275 C8278 F8278 C8274 F8274 8 Bit CMOS Microcontrollers User s Manual Revision 0 Publication Number 20 S3 C8275 F8275 C8278 F8278 C8274 F8274 022005 2005 Samsung Electronics All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics microcontroller business has been awarded full ISO 14001 certification BSI Certificate No FM24653 All semiconductor products are designed and manufactured in accorda
196. nable Bit Disable pull up resistor BE Enable pull up resistor 0 P3 0 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor NOTE A pull up resistor of port is automatically disabled only when the corresponding pin is selected as push pull output or alternative function ELECTRONICS 4 33 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec P4CONH Port 4 Control Register High Byte E9H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 7 SEG8 Configureation Bits 0 Input mode 0 o i Input mode with pull up resistor Push pull output mode Alternative function SEG8 5 4 P4 6 SEG9 Configureation Bits Push pull output mode 0 Input mode 1 Input mode with pull up resistor Alternative function SEG 3 2 Input mode 1 Input mode with pull up resistor Push pull output mode 1 0 Input mode Input mode with pull up resistor Push pull output mode Alternative function SEG11 4 34 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER P4CONL Port 4 Contro Register Low Byte EAH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P4 3 SEG12 Configureation Bits 0 Input mode 0 EREN Input mode with pull up resist
197. nce with the highest quality standards and objectives Samsung Electronics Co Ltd San 24 Nongseo Ri Giheung Eup Yongin City Gyeonggi Do Korea C P O Box 37 Suwon 449 900 TEL 82 031 209 1934 FAX 82 331 209 1889 HomePage URL Http www samsungsemi com Printed in the Republic of Korea Preface S3C8275 F8275 C8278 F8278 C8274 F8274 Microcontroller User s Manual is designed for application designers and programmers who are using the S8C8275 F8275 C 82 78 F8278 C8274 F8274 microcontroller for application development It is organized in two main parts Part Programming Model Part Il Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Struc ture Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3C8275 F8275 C8278 F8278 C8274 F8274 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack operations
198. nd Jump on eee 6 31 CPIJNE Compare Increment and Jump on 6 32 DA Decimal eq en EP HU Mee cd eed ie 6 33 DEC Pe EET 6 35 DECW Decrement Word nea oti eden t e rete t eR Rd seen ater deo 6 36 DI Disable Initerr pts aoi orae cto tt pedo oeste ede 6 37 DIV Divide Unsignedy t imt eoe owe eae Ends 6 38 DJNZ Decrement and Jump if Non Zero mme emere 6 39 Enable eet erdt ir edere e setae Gana Er rad ruga rich 6 40 ENTER uU cc 641 EXIT Exit sos ERR 6 42 IDLE 1016 iei ideas pet teet 6 43 Increment T ee 6 44 INCW Increment Word teen SO pic HR M 6 45 IRET Interrupt RETIN zoe ice E tet tee tue e ntn niece sent ti et nce ede ceed 6 46 JP SJU ae ires teer dc adobe Ce ee a 647 JR irse Rie EE e UR RIPE D nee US HERR ER RICE MAR 6 48 LD L 080 edet ce dae ebd eue 649 LDB Erte kei 1 6 51 3C8275 F8275 C8278 F8278 C8274 F8274 MICROCONTROLLER xxi Instruction Mnemonic LDC LDE LDCD LDED LDCI LDEI LDCPD LDEPD LDCPI LDEPI LDW
199. nd register 01H 01H R1 01H 1 gt R1 07H register 01H 01H If destination working register R1 contains the value 07H 00000111B and the source register 01H contains the value 01H 00000001B the statement BCP R1 01H 1 compares bit one of the source register 01H and bit zero of the destination register R1 Because the bit values are not identical the zero flag bit Z is cleared in the FLAGS register OD5H ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET BITC Bit Complement BITC Operation Flags Format Example dst b dst b lt NOT dst b This instruction complements the specified bit within the destination without affecting any other bits in the destination Unaffected Set if the result is 0 cleared otherwise Cleared to 0 Undefined Unaffected Unaffected Bytes Cycles Opcode Addr Mode Hex dst NOTE Inthe second byte of the instruction format the destination address is four bits the bit address b is three bits and the LSB address value is one bit in length Given R1 07H R11 gt R1 05H If working register R1 contains the value 07H 00000111B the statement BITC R1 1 complements bit one of the destination and leaves the value 05H 00000101B in register R1 Because the result of the complement is not 0 the zero flag Z in the FLAGS register 0D5H is cleared ELECTRONS 6 19 INSTRUC
200. ng the following events occur 1 The contents of the instruction pointer and the PC are swapped 2 The FLAG register values are written to the FLAGS FLAGS prime register 3 The fast interrupt status bit in the FLAGS register is set 4 The interrupt is serviced 5 Assuming that the fast interrupt status bit is set when the fast interrupt service routine ends the instruction pointer and PC values are swapped back The content of FLAGS FLAGS prime is copied automatically back to the FLAGS register m The fast interrupt status bit in FLAGS is cleared automatically Relationship to Interrupt Pending Bit Types As described previously there are two types of interrupt pending bits One type that is automatically cleared by hardware after the interrupt service routine is acknowledged and executed the other that must be cleared by the application program s interrupt service routine You can select fast interrupt processing for interrupts with either type of pending condition clear function by hardware or by software Programming Guidelines Remember that the only way to enable disable a fast interrupt is to set clear the fast interrupt enable bit in the SYM register SYM 1 Executing an El or DI instruction globally enables or disables all interrupt processing including fast interrupts If you use fast interrupts remember to load the IP with a new start address when the fast interrupt service routine ends ELECTRONI
201. nter 2 8 2 6 Set 1 Set 2 Prime Area Register and LCD Data Register 2 11 2 7 8 Byte Working Register Areas 2 12 2 8 Contiguous 16 Byte Working Register 2 13 2 9 Non Contiguous 16 Byte Working Register Block 2 14 2 10 16 Bit Register vel ERE ded 2 15 2 11 Register File 2 16 2 12 Common Working Register 2 17 2 13 4 Bit Working Register 0 2 19 2 14 4 Bit Working Register Addressing Example cesse 2 19 2 15 8 Bit Working Register m 2 20 2 16 8 Bit Working Register Addressing 2 21 2 17 Stack Operations tree LU Lee pel tea P fides we 2 22 3 1 Register Addressing is ke ede fic aie ix a e e ptor te 3 2 3 2 Working Register Addressing 3 2 3 3 Indirect Register Addressing to Register 1 3 3 3 4 Indirect Register Addressing to Program Memory
202. ntrol Register Low Byte EEH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P3 3 SEG20 Configureation Bits 0 Input mode 0 o i N channel open drain output mode Push pull output mode 5 4 P3 2 SEG21 Configureation Bits Alternative function SEG20 Push pull output mode 0 Input mode 1 N channel open drain output mode Alternative function SEG21 3 2 fo y 1 N channel open drain output mode Push pull output mode Alternative function SEG22 1 0 4 32 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER P3PUR Port3 Pull up Control Register EFH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 P3 7 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 6 P3 6 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 5 P3 5 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P3 4 s Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 3 P3 3 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P3 2 s Pull up Resistor Enable Bit 0 1 Disable pull up resistor Enable pull up resistor 41 P3 1 s Pull up Resistor E
203. ntrol whether or not an external interrupt can be used to trigger a stop mode release This is called the IRQ wake up function The IRQ wake up enable bit is CLKCON 7 After the main oscillator is activated and the fxx 16 the slowest clock speed is selected as the CPU clock If necessary you can then increase the CPU clock speed to 8 fxx 2 or fxx 1 System Clock Control Register CLKCON D4H Set 1 R W Oscillator IRQ wake up ede bit Not used for S3C8275 C8278 C8274 0 Enable IRQ for main wake up in must keep always 0 power down mode 1 Disable IRQ for main wake up in power down mode Divide by selection bits for CPU clock frequency 00 16 Not used for S3C8275 C8278 C8274 01 fxx 8 must keep always 0 10 fxx 2 11 fxx 1 non divided Figure 7 8 System Clock Control Register CLKCON 7 4 ELECTRONICS 3C8275 C8278 C8274 F8275 F8278 F8274 Preliminary Spec CLOCK CIRCUIT CLOCK OUTPUT CONTROL REGISTER CLOCON The clock output control register CLOCON is located in set 1 bank 1 address E8H It is read write addressable and has the following functions Clock output frequency selection After a reset fxx 64 is select for clock output frequency because the reset value of CLOCON 1 0 is 00b Clock Output Control Register CLOCON E8H Set 1 Bank 1 R W Not used for S3C8275 C8278 C8274 Must keep always 0 Clock Output Frequency Selection Bits 00 Select fxx 64 01 Sele
204. o Section 2 Address Spaces ADDRESSING MODES There are seven explicit addressing modes Register R Indirect Register IR Indexed X Direct DA Relative RA Immediate IM and Indirect IA For detailed descriptions of these addressing modes please refer to Section 3 Addressing Modes ELECTRONS 6 1 INSTRUCTION SET Mnemonic Load Instructions CLR LD LDB LDE LDC LDED LDCD LDEI LDCI LDEPD LDCPD LDEPI LDCPI LDW POP POPUD POPUI PUSH PUSHUD PUSHUI 6 2 Operands dst dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst src dst dst src dst src src dst src dst src 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 6 1 Instruction Group Summary Instruction Clear Load Load bit Load external data memory Load program memory Load external data memory and decrement Load program memory and decrement Load external data memory and increment Load program memory and increment Load external data memory with pre decrement Load program memory with pre decrement Load external data memory with pre increment Load program memory with pre increment Load word Pop from stack Pop user stack decrementing Pop user stack incrementing Push to stack Push user stack decrementing Push user stack incrementing ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET Table 6 1 Ins
205. ochange CLR RPO RPO lt lt nochange LD RP1 0F8H RPO lt nochange RP1 lt OF8H Register File Contains 32 8 Byte Slices 00001XXX 8 Byte Slice 16 Byte Contiguous Working RPO Figure 2 8 Contiguous 16 Byte Working Register Block ELECTRONICS 2 13 ADDRESS SPACES S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec 8 Byte Slice Register File 16 Byte Contains 32 Contiguous 11110 XXX 8 Byte Slices working Register block RPO 00000 XXX 8 Byte Slice RP1 Figure 2 9 Non Contiguous 16 Byte Working Register Block PROGRAMMING Using the RPs to Calculate the Sum of a Series of Registers Calculate the sum of registers 80H 85H using the register pointer The register addresses from 80H through 85H contain the values 10H 11H 12H 13H 14H and 15H respectively SRPO 80H RPO lt 80H ADD RO R1 RO lt RO ADG RO R2 RO RO R2 C ADC RO R3 RO RO ADC RO R4 RO RO R4 C ADG RO R5 RO lt RO R5 C The sum of these six registers 6FH is located in the register RO 80H The instruction string used in this example takes 12 bytes of instruction code and its execution time is 36 cycles If the register pointer is not used to calculate the sum of these registers the following instruction sequence would have to be used ADD 80H 81H lt 80H 81H ADC 80H 82H lt 80H 82H C ADC 80H 83H 80H lt
206. ode disable TM FMCON 00001000B Check sector erase status bit JR NZ reErease Jump to reErase if fail 16 8 ELECTRONES 53 8275 F8275 C8278 F8278 C8274 F8274 Freliminary Spec EMBEDDED FLASH MEMORY INTERFACE PROGRAMMING A flash memory is programmed in one byte unit after sector erase And for programming safety s sake must set FMSECH FMSECL to flash memory sector value The write operation of programming starts by LDC instruction You Can Write until 128 byte because this flash sector s limits is 128 byte So if you written 128 byte must reset FMSECH FMSECL The Program Procedure in User Program Mode 1 QU ED XO Te uei Must erase sector before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 01010000B Set Flash Memory Sector Register FMSECH FMSECL to sector value of write address Load a transmission data into a working register Load a code memory upper address into upper register of pair working register Load a code memory lower address into lower register of pair working register Load transmission data to code memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 00000000B PROGRAMMING TIP Program SB1 LD FMSECH 17H LD FMSECL 80H Set sector address 1780 17FFH LD R2 17H Set a ROM address in the same
207. of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then decremented The contents of the source are unaffected LDCD references program memory and LDED references external data memory The assembler makes Irr an even number for program memory and odd number for data memory No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src Given R6 10H R7 33H R8 12H program memory location 1033H and external data memory location 1033H LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is decremented by one R8 R6 10H R7 32H RR6 RR6 1 LDED R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET LDCI LDEI Loaa Memory and Increment LDCI LDEI dst src Operation dst lt src r err 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address of the memory location is specified by a working register pair The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of the sou
208. ommonly used for stack operations 2 10 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES PRIME REGISTER SPACE The lower 192 bytes QOH BFH of the S3C8275 C8278 C82 74 s two or one 256 byte register pages is called prime register area Prime registers can be accessed using any of the seven addressing modes see Chapter 3 Addressing Modes The prime register area on page 0 is immediately addressable following a reset In order to address prime registers on pages 0 1 or 2 you must set the register page pointer PP to the appropriate source and destination values CPU and system control General purpose Peripheral and I O Register Area L LCD data register LCD Data NOTE In case of S3C8278 C8274 there are page 0 and page 2 Page 2 is for LCD display register 16 bytes Figure 2 6 Set 1 Set 2 Prime Area Register and LCD Data Register Map ELECTRONICS 2 11 ADDRESS SPACES S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec WORKING REGISTERS Instructions can access specific 8 bit registers or 16 bit register pairs using either 4 bit or 8 bit address fields When 4 bit working register addressing is used the 256 byte register file can be seen by the programmer as one that consists of 32 8 byte register groups or slices Each slice comprises of eight 8 bit registers Using the two 8 bit register pointers RP1 and RPO two working register slices can be selected at any
209. or 1 EN Push pull output mode Alternative function SEG12 5 4 P4 2 SEG13 Configureation Bits Push pull output mode 1 Alternative function SEG13 3 2 P4 1 SEG14 Configureation Bits Input mode 0 1 Input mode with pull up resistor 1 0 Push pull output mode Alternative function SEG14 0 Input mode 1 Input mode with pull up resistor 1 0 P4 0 SEG15 Configureation Bits Input mode Input mode with pull up resistor 1 0 Push pull output mode 1 1 Alternative function SEG15 ELECTRONICS 4 35 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec P5CONH Port 5 Control Register High Byte EBH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 5 7 5 0 Configureation Bits 0 0 Input mode Input mode with pull up resistor EN Push pull output mode Alternative function SEGO Push pull output mode Alternative function SEG3 4 36 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER P5CONL Port 5 Control Register Low Byte ECH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P5 3 SEG4 Configureation Bits 0 Input mode 0 EREN Input mode with pull up resistor ifo Push pull output mode Alternative function SEG4 5 4 P5 2 S
210. or SB1 are used to address one bank or the other A hardware reset operation always selects bank 0 addressing The upper two 32 byte areas bank 0 and bank 1 of set 1 contains 48 mapped system and peripheral control registers The lower 32 byte area contains 16 system registers DOH DFH and a 16 byte common working register area You can use the common working register area as a scratch area for data operations being performed in other areas of the register file Registers in set 1 locations are directly accessible at all times using Register addressing mode The 16 byte working register area can only be accessed using working register addressing For more information about working register addressing please refer to Chapter 3 Addressing Modes REGISTER SET 2 The same 64 byte physical space that is used for set 1 locations COH FFH is logically duplicated to add another 64 bytes of register space This expanded area of the register file is called set 2 For the S3C8275 the set 2 address range COH FFH is accessible on pages 0 1 S3C8278 C8274 the set 2 address range COH FFH is accessible on page 0 The logical division of set 1 and set 2 is maintained by means of addressing mode restrictions You can use only Register addressing mode to access set 1 locations In order to access registers in set 2 you must use Register Indirect addressing mode or Indexed addressing mode The set 2 register area is c
211. ort 5 control register high byte 235 EBH o jo Jojo 0 0 0 Port 5 control register low byte P5CONL 236 ECH mum EI Flash memory control register FMCON 240 Fon 0 0 0 0 0 O Flash memory user programming enable register FMUSR 241 FH Jo Flash memory sector address register high byte FMSECH 242 Fen o o o o o Jo o Flash memory sector address register low byte FMSECL 243 F3H 00 O 0 Battery level detector control register BLDCON 244 OO Locations F5H FFH are not mapped 8 4 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RESET and POWER DOWN POWER DOWN MODES STOP MODE Stop mode is invoked by the instruction STOP opcode 7FH In Stop mode the operation of the CPU and all peripherals is halted That is the on chip main oscillator stops and the supply current is reduced to less than 3 uA All system functions stop when the clock freezes but data stored in the internal register file is retained Stop mode can be released in one of two ways by a reset or by interrupts for more details see Figure 7 3 NOTE Do not use stop mode if you are using an external clock source because Xy or XTj input must be restricted internally to V es to reduce current leakage Using nRESET to Release Stop Mode Stop mode is released when the nRESET signal is released and returns
212. ou can program the basic timer overflow signal BTOVF to generate a reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function A reset clears BTCON to 00H automatically enabling the watchdog timer function A reset also selects the CPU clock as determined by the current CLKCON register setting divided by 4096 as the BT clock A reset whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and the accompanying reset operation from occurring To do this the BTCNT value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter BTCNT is always broken by a BTCNT clear instruction If a malfunction does occur a reset is triggered automatically Oscillation Stabilization Interval Timer Function You can also use the basic timer to program a specific oscillation stabilization interval following a reset or when stop mode has been released by an external interrupt In stop mode whenever a reset or an internal and an external interrupt occurs the oscillator starts The BTCNT value then starts increasing
213. ource Register Page Selection Bits 0 Source page 0 1 Source page 1 Not used for the S8C8278 C8274 Fo o 1 0 source paoe 2 Not used for the 3C8275 C8278 C8274 NOTES 1 Inthe S3C8275 microcontroller the internal register file is configured as three pages Pages 0 2 The pages 0 1 are used for general purpose register file and page 2 is used for LCD data register or general purpose registers 2 Inthe S3C8278 C8274 microcontroller the internal register file is configured as two pages Pages 0 2 The page 0 is used for general purpose register file and page 2 is used for LCD data register or general purpose registers ELECTRONICS 4 39 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RPO Register Pointer 0 D6H Set 1 Bit Identifier o7 6s 5s 4 3 2 J 1 o Reset Value 1 1 0 0 0 Read Write R W R W R W R W R W Addressing Mode Register addressing only 7 8 Register Pointer 0 Address Value Register pointer 0 can independently point to one of the 256 byte working register areas in the register file Using the register pointers RPO and RP1 you can select two 8 byte register slices at one time as active working register space After a reset RPO points to address COH in register set 1 selecting the 8 byte working register slice COH C7H 2 0 Not used for the 53C8275 C8278 C8274 Register Pointer 1 D7H Set 1 Reset Value 1 1 0 0 1 Read Write R W R W
214. ow Byte FMSECL 16 4 ELECTRONES 53 8275 F8275 C8278 F8278 C8274 F8274 Freliminary Spec EMBEDDED FLASH MEMORY INTERFACE ISP ON BOARD PROGRAMMING SECTOR ISP sectors located in program memory area can store on board program software boot program code for upgrading application code by interfacing with I O pin The ISP sectors can not be erased or programmed by LDC instruction for the safety of On Board Program software The ISP sectors are available only when the ISP enable disable bit is set 0 that is enable ISP at the Smart Option If you don t like to use ISP sector this area can be used as a normal program memory can be erased or programmed by LDC instruction by setting ISP disable bit 1 at the Smart Option Even if ISP sector is selected ISP sector can be erased or programmed in the Tool Program mode by Serial programming tools The size of ISP sector can be varied by settings of Smart Option You can choose appropriate ISP sector size according to the size of On Board Program software Decimal 16 383 Decimal 8 191 16K bytes Internal Program Memory Area Decimal 4 095 8K bytes Internal Program Memory Area d 4K bytes Internal Program Memory Area Interrupt Vector Area Interrupt Vector Area 53 8275 53 8278 53 8274 Figure 16 5 Program Memory Address Space ELECTRONES 16 5 EMBEDDED FLASH MEMORY INTERFACE 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 16 2 I
215. p Resistor Enable Bit 0 1 Disable pull up resistor Enable pull up resistor 41 P2 1 s Pull up Resistor Enable Bit Disable pull up resistor B Enable pull up resistor 0 P2 0 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor NOTE A pull up resistor of port 2 is automatically disabled only when the corresponding pin is selected as push pull output or alternative function LI 4 30 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER P3CONH Port Control Register High Byte EDH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode 7 6 ELECTRONICS Register addressing mode only P3 7 SEG16 Configureation Bits 0 Input mode 0 EREN N channel open drain output mode 1 EN Push pull output mode Alternative function SEG16 P3 6 SEG17 Configureation Bits Push pull output mode 1 Alternative function SEG17 P3 5 SEG18 Configureation Bits Input mode 0 1 N channel open drain output mode 1 0 Push pull output mode Alternative function SEG18 0 Input mode BH N channel open drain output mode EAE ENEN P3 4 SEG19 Configureation Bits Input mode N channel open drain output mode 1 0 Push pull output mode 1 1 Alternative function SEG19 4 31 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec P3CONL Port 3 Co
216. pacitance A C electrical characteristics Input timing for external interrupts Input timing for RESET Serial data transfer timing Oscillation characteristics Oscillation stabilization time Operating voltage range ELECTRONICS 17 1 ELECTRICAL DATA 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 17 1 Absolute Maximum Ratings Ta 25 C Parameter E Conditions Rating Unit Supply voltage 0 3 to 4 6 Input voltage E Ports 0 6 0 3 to Vpp 0 3 B Output current High One pin active All O pins active a uM Output current Low One I O pin active 30 Peak value Total pin current for ports 100 100 Peak value value Operating temperature TA 25 to 85 Storage temperature Tera 65 to 150 Table 17 2 D C Electrical Characteristics Ta 25 C to 85 2 0 V to 36V Parameter Symbol Conditions Mex Unit fx 0 4 2MHz fxt 32 8kHz 20 V J 25 38 Input high voltage All input pins except for Vino 0 7 Vpp Vpp V ST Vis Xn XTn XTour AN Output high Vpp 2 7 to 3 6 V All output ports lop Output low voltage Vpp 2 7 to 3 6 V lo 15mA Ports 0 1 Vpp 2 7 to 3 6 V loL 10mA All output ports except for Voy 4 Input high leakage Vpp current d pins except for Vpp XT iN XT our 17 2 ELECTRONICS 53 8275 8
217. play data 32 segment output pins SEGO SEG31 4 common output pins COMO COM3 Three LCD operating power supply pins Vi LCD bias by Internal External register Bit setting in the LCD control register LCON determine the LCD frame duty and bias The LCD control register LCON is used to turn the LCD display on or off to select LCD clock frequency to select bias and duty and switch the current to the dividing resistor for the LCD display Data written to the LCD display RAM can be transferred to the segment signal pins automatically without program control When a sub clock is selected as the LCD clock source the LCD display is enabled even during main clock stop and idle modes VicoVic2 LCD Controller o 0 Driver c m D U c 42 SEGO0 SEG31 Figure 13 1 LCD Function Diagram ELECTRONS 13 1 LCD CONTROLLER DRIVER LCD CIRCUIT DIAGRAM 17 LCD Display RAM 200H 20FH 2 m c L 13 2 Timing Controller Figure 13 2 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SEG Port Driver COM Port Driver LCD Voltage Controller LCD Circuit Diagram SEG31 P2 0 SEG16 P3 7 SEG15 P4 0 SEGO P5 7 COMS P6 3 COM2 P6 2 COMO P6 0 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LCD CONTROLLER DRIVER LCD RAM ADDRESS AREA RAM addresses of page 2 are used as LCD data memory When the bit value of a dis
218. play segment is 1 the LCD display is turned on when the bit value is 0 the display is turned off Display RAM data are sent out through segment pins SEGO SEG31 using a direct memory access DMA method that is synchronized with the cp signal RAM addresses in this location that are not used for LCD display can be allocated to general purpose use Figure 13 3 LCD Display Data RAM Organization Table 13 1 LCD Clock Signal Frame Frequency LCDCK Frequency f Static 1 2 Duty 1 3 Duty 1 4 Duty ELECTRONS 13 3 LCD CONTROLLER DRIVER 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LCD CONTROL REGISTER LCON ALCON is located set 1 bank 1 at address and is read write addressable using register addressing mode It has the following control functions LCD duty and bias selection LCD clock selection LCD display control nternal External LCD dividing resistors selection The LCON register is used to turn the LCD display on off to select duty and bias to select LCD clock and control the flow of the current to the dividing in the LCD circuit Following a RESET all LCON values are cleared to 0 This turns off the LCD display select 1 4 duty and 1 3 bias select 64Hz for LCD clock and Enable internal LCD dividing resistors The LCD clock signal determines the frequency of COM signal scanning of each segment output This is also referred as the LCD frame frequency Since the LCD c
219. port Input or push pull open drain output and software assignable pull ups Alternatively P2 can be used as outputs for LCD segment signals 1 bit programmable 1 port Input or push pull open drain output and software assignable pull ups Alternatively P3 can be used as outputs for LCD segment signals 1 bit programmable port Input or push pull output and software assignable pull ups Alternatively P4 can be used as outputs for LCD segment signals 1 bit programmable 1 port Input or push pull output and software assignable pull ups Alternatively P5 can be used as outputs for LCD segment signals 1 bit programmable 1 port Input or push pull output and software assignable pull ups P6 0 P6 3 can alternately used as outputs for LCD common signals PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORT DATA REGISTERS Table 9 2 gives you an overview of the register locations of all seven S3C8275 C8278 C8274 I O port data registers Data registers for ports 0 1 2 3 4 5 and 6 have the general format shown in Figure 9 1 Table 9 2 Port Data Register Summary Register Name Mnemonic Decimal Hex Location AW Foib wargse mo SeiBak0 RW Rm Sat Genk 7 Port 4 data Vind Set 1 Bank 0 ES alee 6 8 Port 6 data Port 6 data register 25 Fe Set 1 Bank 0 3C8275 C8278 C8274 I O Port Data Register Format 0 6 Pn 7 Pn 6 Pn5 Pn4
220. pt Request Priority 5 11 5 8 Interrupt Priority Register 5 12 5 9 Interrupt Request Register 5 13 6 1 System Flags Register 5 6 6 7 1 Crystal Ceramic Oscillator 7 2 7 2 External Oscillator deadlier eet teed cand 7 2 7 3 exe elrdup EI 7 2 7 4 Crystal Ceramic Oscillator fxt 7 2 7 5 Crystal Ceramic Oscillator fxt for Low Current 7 2 7 6 External Oscillator fxt 2 2 tee et nune Tonto EE d ces OR 7 2 7 7 System Clock Circuit 7 8 7 8 System Clock Control Register 7 4 7 9 Clock Output Control Register 7 5 7 10 Clock Output Block 7 5 7 11 Oscillator Control Register 5 7 6 7 12 STOP Control Register 7 8 9 1 3C8275 C8278 C8274 I O Port Data Register 9 2 9 2 Port 0 High Byte Control Register 9 4 9 3 Port 0 Low Byte Control Register 9 4 9 4 Port 0 Pull up Control Register 9 5 9 5 External Interrupt Control
221. r 9 15 9 21 Port 5 High Byte Control Register 9 16 9 22 Port 5 Low Byte Control Register 9 16 9 23 Port 6 Control Register mnm mnes 9 17 10 1 Basic Timer Control Register 10 2 10 2 Basic Timer Block 10 4 11 1 Timer 1 A Control Register 11 2 11 2 Timer 1 Block Diagram One 16 bit 11 8 11 8 Timer 1 A Control Register 11 5 11 4 Timer B Control Register 11 6 11 5 Timer A Block Diagram Two 8 bit Timers Mode 11 7 11 6 Timer B Block Diagram Two 8 bit Timers Mode 11 8 12 1 Watch Timer Control Register 12 2 12 2 Watch Timer Circuit 12 3 13 1 EGD Function Diagram 52 i oett rto a dote m Ono ke E HER da ERR 13 1 13 2 LCD Circuit cL 13 2 13 3 LCD Display Data RAM Organization mme 13 3 13 4 LCD Control Register 13 4 13 5 Internal Voltage Dividing Resistor 13 5 13 6 Select No Select Signals in Static Display 13 6 13 7 Select
222. r 1 Enable pull up resistor 5 P1 5 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 4 P1 4 s Pull up Resistor Enable Bit Disable pull up resistor Enable pull up resistor 1 3 P1 3 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 2 P1 2 s Pull up Resistor Enable Bit 0 Disable pull up resistor 1 Enable pull up resistor 41 P1 1 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor 0 P1 0 s Pull up Resistor Enable Bit Disable pull up resistor 1 Enable pull up resistor NOTE A pull up resistor of port 1 is automatically disabled only when the corresponding pin is selected as push pull output or alternative function ELECTRONICS 4 27 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec P2CONH Port 2 Control Register High Byte EAH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P2 7 SEG24 Configuration Bits 0 0 Input mode N channel open drain output mode EN Push pull output mode Alternative function SEG24 5 4 3 2 N channel open drain output mode Push pull output mode 1 0 4 28 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER P2CONL Port 2 Control Register Low Byte EBH Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R
223. r Low Byte etre due 4 42 Stop Control RegiSter 3 2 rcr Dre e rex Dre e ERE EISE 4 43 System Mode Register 000 4 44 Timer 1 Control Register 4 45 Timer B Control Register coti rer itp ee Lone es vate 4 46 Watch Timer Control Register 2 20 2008 4 47 xix List of Instruction Descriptions Instruction Full Register Name Page Mnemonic Number ADC Add With Cany Teaia ttd ue tog poe e E E DOR Dead sedate us 6 14 ADD Addi oor btc tile fae 6 15 AND Logical DRE 6 16 BAND BAND wee 6 17 BCP E A E E TA E 6 18 BITC Bit a ied 6 19 BITR MEILLEURS 6 20 BITS IIS MP J 6 21 BOR BIUOBi ens ttes hee E eee cete 6 22 BTJRF Bit Test Jump Relative on 6 23 BTJRT Bit Test Jump Relative on 6 24 BXOR Bi XOR S e c He e Tte p edem m EU tnis 6 25 CALL Calb Proced te 5e te eset ceo test decet eet tentatus decet 6 26 CCF Complement Carty Flag inc ot de e ed e ERR RC tease 6 27 CLR CIE Ar tras ETE 6 28 COM eue LEE 6 29 CP Uni ie E a oean AANSIEN S EENE Aaea IAT 6 30 CPIJE Compare Increment a
224. r open drain When programming this port please remember that any alternative peripheral I O function you configure using the port 2 control register must also be enabled in the associated peripheral module Port 2 Pull up Resistor Control Register P2PUR Using the port 2 pull up resistor control register P2PUR ECH set 1 bank 0 you can configure pull up resistors to individual port 2 pins Port 2 Control Register High Byte P2CONH EAH Set 1 Bank 0 R W P2 7 SEG24 P2 6 SEG25 P2 5 SEG26 P2 4 SEG27 P2CONH bit pair pin configuration settings Input mode N channel open drain output mode Push pull output mode Alternative function SEG24 SEG27 Figure 9 13 Port 2 High byte Control Register P2CONH ELECTRONICS 9 11 PORTS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Port 2 Control Register Low Byte P2CONL EBH Set 1 Bank 0 R W P2 3 SEG28 P2 2 SEG29 P2 1 SEG30 P2 0 SEG31 VBLDREF P2CONL bit pair pin configuration settings Input mode N channel open drain output mode Push pull output mode Alternative function SEG28 SEG31 VBLDREF Figure 9 14 Port 2 Low byte Control Register P2CONL Port 2 Pull up Control Register P2PUR ECH Set 1 Bank 0 R W P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 P2PUR bit configuration settings 0 Disable pull up resistor 1 Enable pull up resistor A pull up resistor of port 2 is automatically disabled when the corresponding pin is selected as pu
225. ram counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to the original program flow RET pops the top of the stack back into the program counter No flags are affected Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR opc dst 2 14 D4 Given RO 35H R1 21H 1A47H and SP 0002H CALL 3521H gt SP 0000H Memory locations 0000H 1AH 0001H 4AH where 4AH is the address that follows the instruction CALL RRO gt SP 0000H 0000H 1AH 0001H 49H CALL 40H gt SP 0000H 0000H 0001H 49H In the first example if the program counter value is 1A47H and the stack pointer contains the value 0002H the statement CALL 3521H pushes the current PC value onto the top of the stack The stack pointer now points to memory location OOOOH The PC is then loaded with the value 3521H the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that the 49H is stored in stack location 0001H because the two byte instruct
226. ram memory location 0105H 01H RR2 RO 6DH R2 04H R3 04H LDE RO 01H RR2 RO lt contents of external data memory location 0105H 01H RR2 RO 7DH R2 01H R3 04H LDC note 01 H RR2 RO 11H contents of RO is loaded into program memory location 0105H 01H 0104H LDE 01H RR2 RO 11H contents of RO is loaded into external data memory location 0105H 01H 0104H LDC RO 1000H RR2 RO lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H LDE RO 1000H RR2 RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H 04H LDC R0 1104H RO lt contents of program memory location 1104H RO 88H LDE R0 1104H RO lt contents of external data memory location 1104H RO 98H LDC note 1105 0 11H contents of RO is loaded into program memory location 1105H 1105H lt LDE 1105H RO 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices ELECTRONS 6 53 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LDCD LDED Load Memory and Decrement LDCD LDED Operation Flags Format Examples dst src dst lt src r e m 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file The address
227. rce are unaffected LDCI refers to program memory and LDEI refers to external data memory The assembler makes Irr even for program memory and odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src Examples Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 OCDH R6 10H R7 34H LDEI R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H ELECTRONS 6 55 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec LDCPD LDEPD Load Memory with Pre Decrement LDCPD LDEPD Operation Flags Format Examples dst src r m 1 dst lt src These instructions are used for block transfers of data from program or data memory from the register file The address of the memory location is specified by a working register pair and is first decremented The contents of the source location are then loaded into the destination location The contents of the source are unaffected LDCPD refers to program memory LDEPD refrs to external data memory The assembler makes Irr an even number for program memory
228. register R W Controls the relative processing priorities of the interrupt levels The seven levels of S8C8275 C8278 C8274 are organized into three groups A B and C Group A is IRQO and IRQ1 group B is IRQ2 IRQ3 and IRQ4 and group is IRQ5 IRQ6 and IRQ7 Interrupt request register This register contains a request pending bit for each interrupt level System mode register SYM R W This register enables disables fast interrupt processing and dynamic global interrupt processing NOTE Before IMR register is changed to any value all interrupts must be disable Using DI instruction is recommended 5 6 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec INTERRUPT STRUCTURE INTERRUPT PROCESSING CONTROL POINTS Interrupt processing can therefore be controlled in two ways globally or by specific interrupt level and source The system devel control points in the interrupt structure are Global interrupt enable and disable by El and DI instructions or by direct manipulation of SYM O Interrupt level enable disable settings IMR register Interrupt level priority settings IPR register Interrupt source enable disable settings in the corresponding peripheral control registers NOTE When writing an application program that handles interrupt processing be sure to include the necessary register file address register pointer information El Interrupt Request Register Polling Read only Cycle
229. register as 10100101b Otherwise the STOP instruction will not execute as well as reset will be generated ELECTRONICS 4 43 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SYM System Mode Register DEH Set 1 Bit Identifier 7 5 s 4 3 2 3 9 Reset Value 0 X X X 0 0 Read Write R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 This bit must remain logic 0 6 5 Not used for the S3C8275 C8278 C8274 4 2 Fast Interrupt Level Selection Bits 1 Enable fast interrupt processing 0 Global Interrupt Enable Bit 9 Disable all interrupt processing 1 Enable all interrupt processing NOTES 1 Youcan select only one interrupt level at a time for fast interrupt processing 2 Setting SYM 1 to 1 enables fast interrupt processing for the interrupt level currently selected by SYM 2 SYM 4 3 Following a reset you must enable global interrupt processing by executing an El instruction not by writing a 1 to SYM O 4 44 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER TACON Timer 1 A Control Register E6H Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode ELECTRONICS Register addressing mode only Timer 1 Operating Mode Selection Bit 0 Two 8 bit timers mode timer A B One 16bit timer mode timer 1 Timer 1 A Clock Selection Bits ofo fms
230. register file and page 2 is used for LCD data register or general purpose register 2 Inthe S3C8278 C8274 microcontroller the internal register file is configured as two pages Pages O 2 The pages 0 is used for general purpose register file and page 2 is used for LCD data register or general purpose register 3 Ahardware reset operation writes the 4 bit destination and source values shown above to the register page pointer These values should be modified to address other pages Figure 2 5 Register Page Pointer PP 2 8 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESS SPACES PROGRAMMING Using the Page Pointer for RAM Clear Page 0 Page 1 LD PP 00H Destination lt 0 Source 0 SRP 0COH LD RO 0FFH 0 RAM clear starts RAMCLO CLR RO DJNZ RO RAMCLO CLR RO RO 00H LD PP 10H Destination lt 1 Source 0 LD RO 0FFH Page 1 RAM clear starts RAMCL1 CLR RO DJNZ RO RAMCL1 CLR RO RO 00H NOTE You should refer to page 6 39 and use DJNZ instruction properly when DJNZ instruction is used in your program ELECTRONICS 2 9 ADDRESS SPACES S3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec REGISTER SET 1 The term set 1 refers to the upper 64 bytes of the register file locations The upper 32 byte area of this 64 byte space EOH FFH is expanded two 32 byte register banks bank 0 and bank 1 The set register bank instructions SBO
231. remented stack pointer The operation then adds the new value to the top of the stack No flags are affected Bytes Cycles Opcode Addr Mode Hex dst Opc src 2 8 internal clock 70 R 8 external clock 8 internal clock 8 external clock 71 IR Given Register 40H 4FH register 4FH SPH and SPL PUSH 40H gt Register 40H 4FH stack register OFFH 4FH SPH OFFH SPL OFFH PUSH 40H gt Register 40H 4FH register 4FH OAAH stack register OFFH OAAH SPH OFFH SPL OFFH In the first example if the stack pointer contains the value OOOOH and general register 40H the value 4FH the statement PUSH 40H decrements the stack pointer from 0000 to OFFFFH It then loads the contents of register 40H into location OFFFFH and adds this new value to the top of the stack ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET PUSHUD Push User Stack Decrementing PUSHUD Operation Flags Format Example dst src IR IR 1 dst lt src This instruction is used to address user defined stacks in the register file PUSHUD decrements the user stack pointer and loads the contents of the source into the register addressed by the decremented stack pointer No flags are affected Bytes Cycles Opcode Addr Mode Hex dst src opc dst src 3 8 82 IR R Given Register OOH 03H register 01H 05H and register 02H PUSHUD 00H 0
232. rite R W R W R W R W Addressing Mode Register addressing mode only 7 Sub Oscillator Circuit Selection Bit 0 Select normal circuit for sub oscillator Select power saving circuit for sub oscillator Automatically cleared to 0 when the sub oscillator is stoppen by OSCCON 2 or the CPU is entered into stop mode in sub operating mode 6 4 Not used for 53 8275 8278 8274 43 Main Oscillator Control Bit 0 Main Oscillator RUN 1 Main Oscillator STOP 2 Sub Oscillator Control Bit 0 Sub oscillator RUN Sub oscillator STOP 4 Not used for the 53C8275 C8278 C8274 0 System Clock Selection Bit Select main oscillator for system clock 1 Select sub oscillator for system clock NOTE A capacitor 0 1uF should be connected between Vpgg and GND when the sub oscillator is used to power saving mode OSCCON 7 1 ELECTRONICS 4 21 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec POCONH Port 0 Control Register High Byte E4H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 P0 7 BUZ Configuration Bits 0 Schmitt trigger input mode 0 o i N channel open drain output mode afo Push pull output mode Alternative function BUZ 5 4 P0 6 CLKOUT Configuration Bits 0 Schmitt trigger input mode 1 N channel open drain output mode Push pull output mode Alternative function
233. rol Register Table 15 1 BLDCON Value and Detection Level Other values Not available 15 2 ELECTRONICS 53 8275 F8275 C8278 F8278 C8274 F8274 Reliminary Spec EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE OVERVIEW The S3F8275 F8278 F8274 has an on chip flash memory internally instead of masked ROM The flash memory is accessed by LDC instruction and the type of sector erase and a byte programmable flash a user can program the data in a flash memory area any time you want The S3F8275 s embedded 16K byte memory has two operating features and the S3F8278 F8274 s embedded 8 4K byte memory respectively has one operating feature as below Tool program mode S3F8275 F8278 F8274 User program mode S3F8275 only Tool Program Mode This mode is for the erase and programming full area of flash memory by external programming tools The 6 pins of S3F8275 F8278 F8274 are connected to a programming tool and programmed by serial OTP MTP tolls SPW2 plus single programmer or GW PRO2 gang programmer The other modules except flash memory module are at a reset state This mode doesn t support the sector erase but chip erase all flash memory erased at a time and two protection modes Hard lock protection Read protection Table 16 1 Descriptions of Pins Used to Read Write the Flash in Tool Program Mode Normal ECT During Programming Peter P Name Serial data pin Output poet when reading and input port when
234. rs the contents of the PC and the FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address value is always decreased by one before a push operation and increased by one after a pop operation The stack pointer SP always points to the stack frame stored on the top of the stack as shown in Figure 2 17 High Address Top of stack Top of sack P Stack contents Stack contents after a call after an instruction interrupt Low Address Figure 2 17 Stack Operations User Defined Stacks You can freely define stacks in the internal register file as data storage locations The instructions PUSHUI PUSHUD POPUI and POPUD support user defined stack operations Stack Pointers SPL SPH Register locations D8H and D9H contain the 16 bit stack pointer SP that is used for system stack operations The most significant byte of the SP address SP15 SP8 is stored in the SPH register D8H and the least significant byte SP7 SPO is stored in the SPL register After a reset the SP value is undetermined Because only internal memory space is implemented in the 53C8275 C8278 C8274 the SPL must be initialized to an 8 bit value in the range OOH FFH The SPH register is not needed and be used as general purpose register if necessary When the SPL register contains the only stack pointer value that is when it points to a system stack in
235. rupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 41 P0 1 INT1 Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending 0 PO O INTO Interrupt Pending Bit Interrupt request is not pending pending bit clear when write 0 1 Interrupt request is pending ELECTRONICS 4 11 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec FLAGS System Flags Register D5H Set 1 Reset Value x x x X X X 0 0 Read Write R W R W R W R W R W R W R R W Addressing Mode Register addressing mode only 7 Carry Flag Lo Operation does not generate a carry or borrow condition Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Lo Operation result is a non zero value Operation result is zero 5 Sign Flag S Operation generates a positive number MSB 0 Operation generates negative number MSB 1 4 Overflow Flag V 0 Operation result is lt 127 or gt 128 Operation result is gt 127 or lt 128 3 Decimal Adjust Flag D 0 Add operation completed Subtraction operation completed 2 HalfCarry Flag H No carry out of bit 3 or no borrow into bit 3 by addition or subtraction Addition generated carry out of bit 3 or subtraction generated borrow into bit 3 41 Fast Interrupt Status Flag FIS Interrupt return IRET progress when
236. rupts ELECTRONICS 5 11 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec Interrupt Priority Register IPR FFH Set 1 Bank 0 R W Group priority Group A 0 IRQO gt IRQ1 1 IRQ1 gt IRQO 0 Undefined Group B 1 gt gt 0 IRQ2 gt IRQ3 IRQ4 0 A gt B gt C 1 IRQ3 IRQ4 gt IRQ2 1 B gt A gt C Subgroup B 0 C gt A gt B 0 IRQ3 gt IRQ4 1 gt gt 1 IRQ4 gt IRQ3 0 gt gt Group 1 Undefined 0 IRQ5 gt IRQ6 IRQ7 1 IRQ6 IRQ7 gt IRQ5 Subgroup C 0 IRQ6 gt IRQ7 1 IRQ7 gt IRQ6 0 0 0 0 1 1 1 1 Figure 5 8 Interrupt Priority Register IPR 5 12 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INTERRUPT STRUCTURE INTERRUPT REQUEST REGISTER IRQ You can poll bit values in the interrupt request register IRQ set 1 DCH to monitor interrupt request status for all levels in the microcontroller s interrupt structure Each bit corresponds to the interrupt level of the same number bit 0 to IRQO bit 1 to IRQ1 and so on A 0 indicates that no interrupt request is currently being issued for that level A 1 indicates that an interrupt request has been generated for that level IRQ bit values are read only addressable using Register addressing mode You can read test the contents of the IRQ register at any time using bit or byte addressing to determine the current interrupt request status of spe
237. ry flag replaces bit zero Flags C Setif the bit rotated from the most significant bit position bit 7 was 1 Z Setif the result is 0 cleared otherwise S Setif the result bit 7 is set cleared otherwise V Setif arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared otherwise D Unaffected H Unaffected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 R Examples Given Register OOH OAAH register 01H 02H and register 02H 17H C 0 RLC 00H gt Register OOH 54H C 1 RLC 01H gt Register 01H 02H register 02H 2EH C 0 In the first example if general register OOH has the value OAAH 10101010B the statement RLC 00H rotates OAAH one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of the C flag replaces bit zero of register OOH leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag 6 72 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET RR Rotate Right RR Operation dst C lt dst 0 dst 7 lt dst 0 dst dst 1 06 The contents of the destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB and also replaces the carry flag C Flags Format Examples C Set if the b
238. s and 12 interrupt sources e Fast interrupt processing feature 8 Bit Basic Timer e Watchdog timer function e kinds of clock source Two 8 Bit Timer Counters e Programmable interval timer e External event counter function e Configurable as one 16 bit timer counters 1 2 3C8275 F8275 C8278 F8278C8274 F8274 Preliminary Spec Watch Timer e Interval time 3 91mS 0 255 0 55 and 15 at 32 768 kHz e 0 5 1 2 4 kHz Selectable buzzer output LCD Controller Driver e 32 segments and 4 common terminals e Static 1 2 duty 1 3 duty and 1 4 duty selectable e Internal resistor circuit for LCD bias 8 bit Serial I O Interface e 8 bittransmit receive mode e 8 bit receive mode e LSB first or MSB first transmission selectable e Internal or External clock source Battery Level Detector e 3 creteria voltage selectable 2 2V 2 4V 2 8V e En Disable by software for current consumption source Low Voltage Reset LVR e Creteria voltage 2 2V e En Disable by smart option ROM address Two Power Down Modes e Idle only CPU clock stops e Stop selected system clock and CPU clock stop Oscillation Sources e Crystal ceramic or RC for main clock e Main clock frequency 0 4 MHz 8 MHz e 32 768 kHz crystal for sub clock Instruction Execution Times e 500nS at 8 MHz fx minimum Operating Voltage Range e 20Vt03 6 V at 0 4 4 2 MHz e 2 5 V to 3 6 V at 0 4 8 0 MHz Operating Temperature Range 25 C to 85 C P
239. s that are stored in program memory are fetched for execution using the program counter Instructions indicate the operation to be performed and the data to be operated on Addressing mode is the method used to determine the location of the data operand The operands specified in SAM88RC instructions may be condition codes immediate data or a location in the register file program memory or data memory The S3C8 series instruction set supports seven explicit addressing modes Not all of these addressing modes available for each instruction The seven addressing modes and their symbols are Register R Indirect Register IR _ Indexed X Direct Address DA Indirect Address Relative Address RA Immediate IM FLFCTRONICS 3 1 ADDRESSING MODES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec REGISTER ADDRESSING MODE R In Register addressing mode R the operand value is the content of a specified register or register pair see Figure 3 1 Working register addressing differs from Register addressing in that it uses a register pointer to specify an 8 byte working register space in the register file and an 8 bit register within that space see Figure 3 2 Program Memory Register File 8 bit Register File Address Point to One Register in Register One Operand File Instruction Example Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the
240. s three low order bits Register pointer provides five high order bits LP CERE Together they create an 8 bit register address Figure 2 13 4 Bit Working Register Addressing RPO RP1 Selects RPO R6 OPCODE Register Instruction 01110 110 address 0110 1110 Were 76H Figure 2 14 4 Bit Working Register Addressing Example ELECTRONICS ADDRESS SPACES 3C8275 F8275 C8278 F8278C8274 F8274 Preliminary Spec 8 BIT WORKING REGISTER ADDRESSING You can also use 8 bit working register addressing to access registers in a selected working register area To initiate 8 bit working register addressing the upper four bits of the instruction address must contain the value 1100B This 4 bit value 1100B indicates that the remaining four bits have the same effect as 4 bit working register addressing As shown in Figure 2 15 the lower nibble of the 8 bit address is concatenated in much the same way as for 4 bit addressing Bit 3 selects either RPO or RP1 which then supplies the five high order bits of the final address the three low order bits of the complete address are provided by the original instruction Figure 2 16 shows an example of 8 bit working register addressing The four high order bits of the instruction address 1100B specify 8 bit working register addressing Bit 4 1 selects RP1 and the five high order bits in RP1 10101B become the five high order bits of the register address The three low order b
241. sector 1780 17FFH LD R3 84H LD R4 78H Temporary data LD FMUSR 0A5H User program mode enable LD FMCON 01010001B Start program LDC RR2 R4 Write the data to a address of same sector 1784H NOP Dummy instruction this instruction must be needed LD FMUSR 0 User program mode disable ELECTRONES 16 9 EMBEDDED FLASH MEMORY INTERFACE 53 8275 8275 8278 8278 8274 8274 Preliminary Spec READING The read operation of programming starts by LDC instruction The Program Procedure in User Program Mode 1 Load a flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Loadreceive data from flash memory location area on LDC instruction by indirectly addressing mode 55 PROGRAMMING Reading LD R2 3H Load flash memory upper address To upper of pair working register LD R3 0 Load flash memory lower address To lower pair working register LOOP LDC RO RR2 Read data from flash memory location Between 300H and 3FFH INC R3 CP R3 0H JP NZ LOOP 16 10 ELECTRONES 53 8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec EMBEDDED FLASH MEMORY INTERFACE HARD LOCK PROTECTION User can set Hard Lock Protection by write 0110 in FMCON 7 4 If this function is enabled the user cannot write or erase the data in a flash memory area This protection can be released by the chip erase
242. sh pull output or alternative function Figure 9 15 Port 2 Pultup Control Register P2PUR 9 12 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PORTS PORT 3 Port is an 8 bit I O port with individually configurable pins Port pins are accessed directly by writing or reading the port 3 data register P3 at location F3H set 1 bank 0 P3 0 P3 7 can serve as inputs with or without pull up as outputs push pull or open drain or you can be configured the following functions Low nibble pins P3 0 P3 3 SEG23 SEG20 High nibble pins P3 4 P3 7 SEG19 SEG16 Port 3 Control Register PSCONH P3CONL Port has two 8 bit control register PSCONH for P3 4 P3 7 and PSCONL for P3 0 P3 3 A reset clears the and P3CONL registers to 00H configuring all pins to input mode You use control register setting to select input or output mode push pull or open drain When programming this port please remember that any alternative peripheral I O function you configure using the port 3 control register must also be enabled in the associated peripheral module Port 3 Pull up Resistor Control Register P3PUR Using the port 3 pull up resistor control register PSPUR EFH set 1 bank 0 you can configure pull up resistors to individually port 3 pins Port Control Register High Byte EDH Set 1 Bank 0 R W P3 7 SEG16 P3 6 SEG17 P3 5 SEG18 P3 4 SEG19 P3CONH bit pa
243. structure are stored in the vector address area of the internal 16 Kbyte ROM OH 3FFFH or 8 4 Kbyte see Figure 5 3 You can allocate unused locations in the vector address area as normal program memory If you do so please be careful not to overwrite any of the stored vector addresses Table 5 1 lists all vector addresses The program reset address in the ROM is 0100H Decimal 16 383 16 Kbyte 4 Kbyte Internal Program Memory ROM Area Reset Address Interrupt Vector Address Area Figure 5 3 ROM Vector Address Area 5 4 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec INTERRUPT STRUCTURE Table 5 1 Interrupt Vectors Interrupt Source Request Reset Clear Value Value Level Level 242 F2H Timer B match aa 0 P1 7 external interrupt IRQ7 3 P1 6 external interrupt 2 P1 5 external interrupt P1 4 external interrupt 0 NOTES 1 Interrupt priorities are identified in inverse order 0 is the highest priority 1 is the next highest and so on 2 If two or more interrupts within the same level contend the interrupt with the lowest vector address usually has priority over one with a higher vector address The priorities within a given level are fixed in hardware 1 1 ELECTRONICS 5 5 INTERRUPT STRUCTURE 3C8275 F827 5 C8278 F8278 C8274 F8274 Preliminary Spec ENABLE DISABLE INTERRUPT INSTRUCTIONS El DI Executing the Enable Interrupts El ins
244. t 1 Bank 0 Register Values After RESET 3C8275 C8278 C8274 Set 1 Bank 1 Register Values After RESET 3C8275 C8278 C8274 Port Configuration Port Data Register LCD Clock Signal Frame BLDCON Value and Detection Descriptions of Pins Used to Read Write the Flash in Tool Program Mode ISP Sector 9126 n HU ieee Beta Reset Vector Address ati ATE A RR ERR 53 8275 8275 8278 8278 8274 8274 MICROCONTROLLER Page Number XV List of Tables continued Table Title Page Number Number 17 1 Absolute Maximum 17 2 17 2 D C Electrical 17 2 17 3 Data Retention Supply Voltage in Stop 17 5 17 4 Input Output 17 6 17 5 A C Electrical 17 7 17 6 Characteristics of Battery Level Detect 17 9 17 7 LVR Low Voltage Reset Circuit Characteristics 17 9 17 8 Main Oscillation 17 10 17 9 Sub Oscil
245. t 1 Control Register High 4 25 Port 1 Control Register Low Byte 4 26 Port 1 Pull up Control 10 0 4 27 Port 2 Control Register High Byte 4 28 Port 2 Control Register Low Byte 4 29 Port 2 Pull up Control 4 30 Port Control Register High Byte 4 31 Port Control Register Low Byte sssses eee 4 32 Port 3 Pull up Control mene 4 33 Port 4 Control Register High 4 34 Port 4 Control Register Low Byte 4 35 Port 5 Control Register High 4 36 Port 5 Control Register Low Byte 4 37 Port 6 Coritrol Register 4 38 Register Page Pointer onec cie eer 4 39 Register Pointer p CE 4 40 Register Pointer ete LE 4 40 SIO Gorntrol Register ccs irte e int eR 4 41 Stack Pointer High Byte coincides ertet ate un ea coser vaa 4 42 Stack Pointe
246. t Carry Flag RCF Operation Flags Format Example RCF 0 The carry flag is cleared to logic zero regardless of its previous value C Cleared to 0 No other flags are affected Bytes Cycles Opcode Hex opc 1 4 CF Given 1 or 0 The instruction RCF clears the carry flag to logic zero ELECTRONS 6 69 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RET Return RET Operation Flags Format Example 6 70 PC SP SP e SP 2 The RET instruction is normally us ed to return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement that is executed is the one that is addressed by the new program counter value No flags are affected Bytes Cycles Opcode Hex 1 8 internal stack AF 10 internal stack Given SP OOFCH SP 101AH and PC 1234 RET gt PC 101AH SP OOFEH The statement RET pops the contents of stack pointer location OOFCH 10H into the high byte of the program counter The stack pointer then pops the value in location OOFEH 1AH into the PC s low byte and the instruction at location 101AH is executed The stack pointer now points to memory location OOFEH ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET
247. t enable bit SIOCON to 1 When you transmit data to the serial buffer write data to SIODATA and set SIOCON 3 to 1 the shift operation starts When the shift operation transmit receive is completed the SIO pending bit SIOCON 0 are set to 1 and SIO interrupt request is generated ELECTRONS 14 1 SERIAL I O INTERFACE SIO CONTROL REGISTERS SIOCON The control register for serial I O interface module SIOCON is located at E1H set 1 bank 0 It has the control setting for SIO module 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Clock source selection internal or external for shift clock Interrupt enable Edge selection for shift operation Clear 3 bit counter and start shift operation Shift operation transmit enable Mode selection transmit receive or receive only Data direction selection MSB first or LSB first A reset clears the SIOCON value to 00H This configures the corresponding module with an internal clock source at the SCK selects receive only operating mode and clears the 3 bit counter The data shift operation and the interrupt are disabled The selected data direction is MSB first Serial I O Module Control Register SIOCON E1H Set 1 Bank 0 R W SIO shift clock selection bit 0 Internal clock P S Clock 1 External clock SCK Data direction control bit 0 MSB first mode 1 LSB first mode SIO mode selection bit 0 Receive onl
248. t pin is tied to Ves A reset enables access to the 16 8 4 Kbyte on chip ROM The external interface is not automatically configured NOTE To program the duration of the oscillation stabilization interval you make the appropriate settings to the basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON ELECTRONICS 8 1 RESET and POWER DOWN 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec HARDWARE RESET VALUES Table 8 1 8 2 8 3 list the reset values for CPU and system registers peripheral control registers and peripheral data registers following a reset operation The following notation is used to represent reset values 1 0 shows the reset bit value as logic one or logic zero respectively x means that the bit value is undefined after a reset dash means that the bit is either not used or not mapped but read 0 is the bit value Table 8 1 S3C8275 C8278 C8274 Set 1 2 and Values After RESET Locations DOH D2H are not mapped Basic timer eroon zn o oJ of ojoj System clock conto register 212 omn o Sen osa ee p ee Register pointero pointer 0 Reo 214 1 Regis
249. t supports Indexed addressing mode for the internal register file is the Load instruction LD The LDC and LDE instructions support Indexed addressing mode for internal program memory and for external data memory when implemented Register File RPO or Selected RP Value used in points to Instruction start of working register block Program Memory Base Address bis eel peran dst src x L Instruction Point to One of the Example OPCOD Woking Register 1 of 8 Sample Instruction LD BASE R1 Where BASE is an 8 bit immediate value Figure 3 7 Indexed Addressing to Register File FLFCTRONICS 3 7 ADDRESSING MODES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INDEXED ADDRESSING M ODE Continued Register File oan es RPO or RP1 Soe RPO or RP1 Selected i RP points to start of working Program Memory register camcn e 4 bit Working uk Renee Register Address Point to Working Pair Bo cM m 1 of 4 16 Bit Pp address added to bea ot p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits aes Instruction Sample Instructions LDC R4 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 04H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory
250. t therefore be written to their required settings by the initialization routine When more than one interrupt sources are active the source with the highest priority level is serviced first If two sources belong to the same interrupt level the source with the lower vector address usually has the priority This priority is fixed in hardware To support programming of the relative interrupt level priorities they are organized into groups and subgroups by the interrupt logic Please note that these groups and subgroups are used only by IPR logic for the IPR register priority definitions see Figure 5 7 Group A IRQO IRQ1 Group B IRQ2 IRQ3 IRQ4 Group C IRQ5 IRQ6 IRQ7 B21 C21 IRQ1 IRG2 IRQ6 Figure 5 7 Interrupt Request Priority Groups As you can see in Figure 5 8 IPR 7 IPR 4 and IPR 1 control the relative priority of interrupt groups A B and C For example the setting 001B for these bits would select the group relationship B gt C gt A The setting 101B would select the relationship C gt B gt A The functions of the other IPR bit settings are as follows PR 5 controls the relative priorities of group C interrupts Interrupt group C includes a subgroup that has an additional priority relationship among the interrupt levels 5 6 and 7 IPR 6 defines the subgroup C relationship IPR 5 controls the interrupt group C PR 0 controls the relative priority setting of IRQO and IRQ1 inter
251. tabilization Y Time 31 Stop Mode 4 Normal Data Retention Mode gt 4 Operating Mode Execution of STOP Instrction nRESET NOTE is the same as 16 1 BT clock Figure 17 2 Stop Mode Release Timing When Initiated by a RESET Table 17 4 Input Output Capacitance 25 C 85 Vp OV Input Cin f 1 MHz unmeasured pins 10 pF capacitance are connected to Vas Output Cour capacitance capacitance 17 6 ELECTRONICS 53 8275 8275 8278 8278 8274 8274 Preliminary Spec ELECTRICAL DATA Table 17 5 A C Electrical Characteristics TA 25 to 85 C 2 0 V to 3 6 V Symbol Conditions Min Typ Max Internal SCK source 1 000 SI setup time to SCK high taik Internal SCK source SI hold time to SCK high External SCK source i Output delay for SCK to SO tkso External SCK source Internal SCK source Interrupt input High Low width 1 All interrupt Vpp 3 V nRESET input Low width inar pp 3V External Interrupt NOTE The unit t CPU means one CPU clock period Figure 17 3 Input Timing for External Interrupts ELECTRONICS 17 7 ELECTRICAL DATA 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec tRSL nRESET 0 2 VDD Figure 17 4 Input Timing for RESET 17 8 tKL tKH SCK 0 8VDD 0 2VDD tSIK tKSI 0 8V DD 0 2V DD 5 SO 4 Output Data Figure 17 5 Serial Dat
252. ter pointer 1 215 D7H Stack 5 high byte Stack Stack pointer low byte low byte 217 7 D9H x x x x xxi x E REOR ER ER EA EDERER E Interrupt request register Ra 220 DCH o o 0 O 221 o x x x x x x x System mode register 1 sym 222 DEH 0 x x x 0 0 Regter page pomer P 23 fo oo 8 2 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec RESET and POWER DOWN Table 8 2 53C8275 C8278 C8274 Set 1 Bank 0 Register Values After RESET Register Name Address Bit Values After RESET me z e s s 2 1o oslawcwoegse osocon zw o 9 9 Cr rc e 80000010 SOswamse 29 EM 0 0 28 Port 0 contol register igh bys zm Por 0 control register ow bye Pocont ze ew o o o o Port 0 pul up resistor enable register Poeun 29 een Por contol register igh bye zm o o o o Port 1 control register e A P1CONL Port 1 pull up resistor enable rasa Porr 2 contol register tign bye 234 o o o o 2 contol register byte Pecon zs een Pon 2 pulp resistor erabe register 2 0 0 0 0 Port control register high byte PSCONH 237 eon 0 0 0 0
253. ternal Interrupt PO 1 Not pending 1 Pending 3 Level 3 IRQ3 Request Pending Bit External Interrupt 0 0 Not pending Pending 2 Level 2 IRQ2 Request Pending Bit Watch Timer Overflow Not pending Pending Level 1 IRQ1 Request Pending Bit SIO Interrupt Not pending le Pending 0 Level 0 IRQ0 Request Pending Bit Timer 1 A Match Timer B Match Not pending Pending ELECTRONICS 4 19 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec cb Contro Register EOH Set 1 Bank 1 Reset Value 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 Internal LCD Dividing Resistors Enable Bit 0 Enable internal LCD dividing resistors Disable internal LCD dividing resistors 6 5 LCD Clock Selection Bits o o wsmm 4 o t wBemuy SSCS S fw 2 512 HZ 4 2 LCD Duty and Bias Selection Bits o o o idy bias 0 polo tust toes o 1 o duy Maias o t rwy ums 0 NOTE x means don t care 4 Not used for the 53C8275 C8278 C8274 0 LCD Display Control Bit 0 Turn display off Turn off the P Tr Turn display on Turn on the P Tr 4 20 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER OSCCON oscillator Control Register EOH Set 1 Bank 0 Bit Identifier 7 5s 2 3 o Reset Value 0 0 0 B 0 Read W
254. terrupt input noise filters interrupt enable and pending control E 4 P2 0 I O port with bit programmable pins SEGS1 Vgi pner P2 1 P2 7 Input or push pull open drain output and H 8 SEG30 SEG24 software assignable pull ups 0 7 I O port with bit programmable pins SEG23 SEG 16 Input or push pull open drain output and software assignable pull ups SEG 15 SEG8 SEG7 SEGO COMO0 COMS3 P4 0 P4 7 I O port with bit programmable pins P5 0 P5 7 Input or push pull output and software P6 0 P6 3 assignable pull ups 1 6 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec PRODUCT OVERVIEW Table 1 1 S3C8275 F8275 C8278 F8278 C8274 F8274 Pin Descriptions Continued names nece Type o _ Type Description Type Functions Wco VC2 LCD power supply pins 68 INTO INT2 lO External interrupts input pins 18 20 P0 0 PO0 2 meas o eee f E meer 16 TmertiAexemaldockinp Pos TAQUT 10 Timer 1 A clock output E4 22 Pos TROUT Timer B clock Timer B clock output E4 5 CLKOUT System clock output E 4 6 SEGO SEG15 LCD segment signal outputs 1 64 50 P5 7 P4 0 SEG16 SEG30 49 35 34 7 2 1 VBLDREF Battery level detector reference voltage 34 P2 0 SEG31 needed 0 1uF nRESET t_ systemresetpin B t x
255. the write operation the BTCON 1 value is automatically cleared to 0 2 When you write a 1 to BTCON O the corresponding frequency divider is cleared to Immediately following the write operation the 0 value is automatically cleared to 3 Thefxxis selected clock for system main OSC or sub OSC 4 6 ELECTHONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER System Clock Control Register D4H Set 1 Reset Value 0 0 0 Read Write R W R W R W Addressing Mode Register addressing mode only 7 Oscillator IRQ Wake up Function Bit 0 Enable IRQ for main wake up in power down mode Disable IRQ for main wake up in power down mode 6 5 Not used for the S3C8275 C8278 C8274 4 3 CPU Clock System Clock Selection Bits 1016 oppe 1 0 fxx 2 1 1 2 0 Not used for the S3C8275 C8278 C8274 NOTE After a reset the slowest clock divided by 16 is selected as the system clock To select faster clock speeds load the appropriate values to CLKCON 3 and CLKCON 4 ELECTRONICS 4 7 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CLOCON clock Output Control Register E8H Set 1 Bank 1 Reset Value 0 0 Read Write R W R W Addressing Mode 7 2 4 8 Register addressing mode only Not used for 5308275 C8278 C8274 Clock Output Frequency Selection Bi
256. tion The remainder 8 bits is stored in the upper half of the destination When the quotient is gt 28 the numbers stored in the upper and lower halves of the destination for quotient and remainder are incorrect Both operands are treated as unsigned integers C Set if the V flag is set and quotient is between 28 and 29 1 cleared otherwise Z Set if divisor or quotient 0 cleared otherwise S Set if MSB of quotient 1 cleared otherwise V Set if quotient is gt 280r if divisor 0 cleared otherwise D Unaffected H Unaffected Bytes Cycles Opcode Addr Mode Hex dst src src dst 3 26 10 94 RR R 26 10 95 RR IR 26 10 96 RR IM NOTE Execution takes 10 cycles if the divide by zero is attempted otherwise it takes 26 cycles Given RO 10H R1 R2 40H register 40H 80H DIV RRO R2 gt RO Ri 40H DIV RRO R2 gt RO R1 20H DIV RRO 20H gt RO R1 80H In the first example destination working register pair RRO contains the values 10H R0 and 03H R1 and register R2 contains the value 40H The statement DIV RRO R2 divides the 16 bit RRO value by the 8 bit value of the R2 source register After the DIV instruction RO contains the value 03H and R1 contains 40H The 8 bit remainder is stored in the upper half of the destination register RRO RO and the quotient in the lower half R1 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec
257. truction Group Summary Continued Mnemonic Operands Instruction Arithmetic Instructions ADC dst src Add with carry ADD dst src Add CP dst src Compare DA dst Decimal adjust DEC dst Decrement DECW dst Decrement word DIV dst src Divide INC dst Increment INCW dst Increment word MULT dst src Multiply SBC dst src Subtract with carry SUB dst src Subtract Logic Instructions AND dst src Logical AND COM dst Complement OR dst src Logical OR XOR dst src Logical exclusive OR ELECTRONS 6 3 INSTRUCTION SET 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec Table 6 1 Instruction Group Summary Continued Mnemonic Operands Instruction Program Control Instructions BTJRF dst src Bit test and jump relative on false BTJRT dst src Bit test and jump relative on true CALL dst Call procedure CPIJE dst src Compare increment and jump on equal CPIJNE dst src Compare increment and jump on non equal DJNZ r dst Decrement register and jump on non zero ENTER Enter EXIT Exit IRET Interrupt return JP cc dst Jump on condition code JP dst Jump unconditional JR cc dst Jump relative on condition code NEXT Next RET Return WFI Wait for interrupt Bit Manipulation Instructions BAND dst src Bit AND BCP dst src Bit compare BITC dst Bit complement BITR dst Bit reset BITS dst Bit set BOR dst src Bit OR BXOR dst src Bit XOR TCM dst src Test complement under mask TM dst src Test under mask 6 4 ELECTRONES 3C8
258. truction globally enables the interrupt structure All interrupts are then serviced as they occur according to the established priorities NOTE The system initialization routine executed after a reset must always contain an El instruction to globally enable the interrupt structure During the normal operation you can execute the DI Disable Interrupt instruction at any time to globally disable interrupt processing The El and DI instructions change the value of bit 0 in the SYM register SYSTEM LEVEL INTERRUPT CONTROL REGISTERS In addition to the control registers for specific interrupt sources four system level registers control interrupt processing The interrupt mask register IMR enables un masks or disables masks interrupt levels interrupt priority register IPR controls the relative priorities of interrupt levels The interrupt request register IRQ contains interrupt pending flags for each interrupt level as opposed to each interrupt source The system mode register SYM enables or disables global interrupt processing SYM settings also enable fast interrupts and control the activity of external interface if implemented Table 5 2 Interrupt Control Register Overview Control Register wm RW Function Description Interrupt mask register IMR RAN Bit settings in the IMR register enable or disable interrupt processing for each of the eight interrupt levels IRQ0 IRQ7 Interrupt priority
259. ts 9 1 Select fxx 8 Select 004 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec CONTROL REGISTER EXTICONH external Interrupt Control Register High Byte F8H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 1 7 External Interrupt INT7 Configuration Bits 0 0 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge 0 Disable interrupt 1 Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge Disable interrupt Enable interrupt by falling edge 0 Enable interrupt by rising edge Enable interrupt by both falling and rising edge Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by both falling and rising edge ELECTRONICS 4 9 CONTROL REGISTERS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec EXTICONL external Interrupt Control Register Low Byte F9H Set 1 Bank 0 Reset Value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W Addressing Mode Register addressing mode only 7 6 1 3 External Interrupt INT3 Configuration Bits 0 0 Disable interrupt Enable interrupt by falling edge Enable interrupt by rising edge Enable interrupt by
260. ue of the program counter is taken to be the address of the first instruction byte following the JR statement No flags are affected Bytes Cycles Opcode Addr Mode 1 Hex dst cc opc dst 2 6 ccB RA cc Oto F NOTE Inthe first byte of the twebyte instruction format the condition code and the opcode are each four bits Given The carry flag 1 and LABEL X 1FF7H JR C LABEL X PC 1FF7H If the carry flag is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR would be executed ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec INSTRUCTION SET LD Load LD dst src Operation dst lt src The contents of the source are loaded into the destination The source s contents are unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc SIC 2 4 r IM r8 r R r 0toF dst src 2 C7 r Ir D7 Ir r src dst 3 6 E4 R R E5 R IR dst src 3 6 E6 R IM D6 IR IM src dst 3 6 F5 IR R opc dst src 3 6 87 r x r opc src dst 3 6 97 x r r ELECTRONES 6 49 INSTRUCTION SET LD Load LD Continued Examples Given RO 01H R1 register 02H 02H LOOP LD RO 10H gt LD R0 01H gt LD 01H RO gt LD R1 RO gt LD R0 R1 gt LD 00H 01H gt LD 02H 900H gt LD 00H 0AH gt LD 00H 10H
261. ve number and a logic one indicates a negative number Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 It is also cleared to 0 following logic operations Decimal Adjust Flag FLAGS 3 The DA bit is used to specify what type of instruction was executed last during BCD operations so that a subsequent decimal adjust operation can execute correctly The DA bit is not usually accessed by programmers and cannot be used as a test condition Half Carry Flag FLAGS 2 The H bit is set to 1 whenever an addition generates a carry out of bit 3 or when a subtraction borrows out of bit 4 It is used by the Decimal Adjust DA instruction to convert the binary result of a previous addition or subtraction into the correct decimal BCD result The H flag is seldom accessed directly by a program Fast Interrupt Status Flag FLAGS 1 The FIS bit is set during a fast interrupt cycle and reset during the IRET following interrupt servicing When set it inhibits all interrupts and causes the fast interrupt return to be executed when the IRET instruction is executed Bank Address Flag FLAGS 0 The BA flag indicates which register bank in the set 1 area of the internal register file is currently selected bank 0 or bank 1 The BA flag is cleared to 0 select bank 0 when you execute the SBO instruction and is set to 1 select bank 1 when you execute the SB1
262. with Short Offset 3 8 ELECTRONICS 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec ADDRESSING MODES INDEXED ADDRESSING M ODE Concluded Register File ee RPO or gt 1 e mem or RP1 i Selected i RP points Program to start of i Y working register i block NEXT 2 Bits 4 bit Working prc LM e Register Address 1 Point to Working e Register Pair 16 Bit Pp address added to poscere p Program Memory offset LSB Selects or Data Memory 8 Bits 16 Bits OPERAND Value used in 16 Bits Instruction Sample Instructions LDC R4 1000H RR2 The values in the program address RR2 1000H are loaded into register R4 LDE R4 1000H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 9 Indexed Addressing to Program or Data Memory FLFCTRONICS 3 9 ADDRESSING MODES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec DIRECT ADDRESS MODE DA In Direct Address DA mode the instruction provides the operand s 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address that is loaded into the PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or to external d
263. y Spec WATCH TIMER WATCH TIMER OVERVIEW Watch timer functions include real time and watchtime measurement and interval timing for the system clock To start watch timer operation set bit 1 of the watch timer control register WTCON 1 to 1 And if you want to service watch timer overflow interrupt IRQ 2 vector F6H then set the WTCON 6 to 1 The watch timer overflow interrupt pending condition WTCON 0 must be cleared by software in the application s interrupt service routine by means of writing to the WTCON O interrupt pending bit After the watch timer starts and elapses a time the watch timer interrupt pending bit WTCON O is automatically set to 1 and interrupt requests commence in 3 91ms 0 25 0 5 and 1 second intervals by setting Watch timer speed selection bits WTCON 3 2 The watch timer can generate a steady 0 5 kHz 1 kHz 2 kHz or 4 kHz signal to BUZ output pin for Buzzer By setting WTCON 3 and WTCON 2 to 11b the watch timer will function in high speed mode generating an interrupt every 3 91 ms High speed mode is useful for timing events for program debugging sequences Also you can select watch timer clock source by setting the WTCON 7 appropriately value The watch timer supplies the clock frequency for the LCD controller fj Therefore if the watch timer is disabled the LCD controller does not operate Watch timer has the following functional components Real Time and Watch Time
264. y mode 1 Transmit receive mode Shift clock edge selection bit 0 tx at falling edeges rx at rising edges 1 tx at rising edeges rx at falling edges SIO interrupt pending bit 0 No interrupt pending when read Clear pending bit when write 1 Interrupt is pending when read SIO interrupt enable bit 0 Disable SIO interrupt 1 Enable SIO interrupt SIO shift operation enable bit 0 Disable shifter and clock counter 1 Enable shifter and clock counter SIO counter clear and shift start bit 0 No action 1 Clear 3 bit counter and start shifting Figure 14 1 Serial I O Module Control Register SIOCON 14 2 ELECTRONES 3C8275 F8275 C8278 F8278 C8274 F8274 Preliminary Spec SIO PRE SCALER REGISTER SIOPS The prescaler register for serial I O interface module SIOPS are located at in set 1 bank 0 The value stored in the SIO pre scaler register SIOPS lets you determine the SIO clock rate baud rate as follows Baud rate Input clock fxx 4 Prescaler value 1 or SCK input clock SIO Pre scaler Register SIOPS E3H Set 1 Bank 0 R W Baud rate f xx 4 SIOPS 1 SERIAL I O INTERFACE Figure 14 2 SIO Prescaler Register SIOPS SIO BLOCK DIAGRAM SIOCON 7 sck Bn SIOPS E3H set 1 bank 0 fxx 2 8 bit P S Pending 3 Bit Counter Clear SIOCON 3 SIOCON 1 Interrupt Enable SIOCON 4 Edge Select SIOCON 2 Shift Enable SIOCON 5

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