Start-Up Considerations for 56F8300 and 56F8100 Family Devices
Contents
1. Peripherals on __ sw Reset i 56800E Pulse Shaper Delay blocks assert immediately and CORE_RST a waada T d Peripherals that interface directly to the core may need both reset signals Figure 3 2 56F8x4x 56F8x5x amp 56F8x6x Sources of System Reset Figure 3 2 illustrates reset circuitry for the remaining members of the 56F8300 and 56F8100 families In this case the POR signal is dependent only upon the 1 8V core supply sensor If RESET is a logic zero upon power up then it is assumed that an external power supervisor is controlling the process and the POR_Delay is set to 32 clock cycles If RESET is high then it is assumed that the internal circuit is responsible for delaying deassertion of reset by a period long enough for supplies to hit their nominal operating range In this case POR_Delay is set to 2 21 clock cycles Assuming an 8MHz clock cycle that works out to a little over 1 4 second If an external power supervisor is used it must delay deassertion of reset for a period equaling the sum of the supply ramp up time plus oscillator start up time The oscillator start up time is specified in the device data sheet and is different for ceramic resonators versus crystals Start Up Considerations Rev 1 Freescale Semiconductor 5 Minimum Voltage Requirements 4 Minimum Voltage Requirements Freescale recommends that application start up code which normally occurs before main requires2. Sys clocks COP active low SW Reset Pulse Shaper Delay blocks assert immediately and deassert only after the programmed number of clock cycles gt 56800E Delay 32 Sys clocks Pulse Shaper CORE_RST Figure 3 1 56F8x2x Sources of System Reset Figure 3 1 is a block diagram illustrating the various sources of system reset for the 56F8x2x devices Note how release of the reset signal is phased sequentially through the clock generation circuit peripheral set and finally the core The POR signal from the power supervisor is released only after the POR and both LVI sensors have cleared It does not assert again until the core logic supply drops below approximately 1 8V This ensures that the core is released from reset only after the supplies have ramped to acceptable levels while taking advantage of the low voltage interrupts to give the system sufficient time to shut down in a controlled manner during power down Start Up Considerations Rev 1 4 Freescale Semiconductor POR in the 56F8x4x 56F8x5x and 56F8x6x 3 2 POR in the 56F8x4x 56F8x5x and 56F8x6x Used for latching values of EXTBOOT and EMI_MODE External upon start up TRST Pulse Shaper active low MODE_RST POR_Delay TRST to internal JTAG circuitry Power On Reset active low POR Calculate POR Delay Feeds delay value to External all POR_Delay blocks RESET in active low Subsystem
3. Freescale Semiconductor AN1994 Application Note Rev 1 9 2005 Start Up Considerations for Contents 56F8300 and 56F8100 E A i Family Devices A Stare O i Michael Stanley 3 Reset TIMMINS srconipneriesii ee 3 3 1 POR in the 56F8x2x cc eee 4 3 2 POR in the 56F8x4x 56F8x5x and l Introduction N The 56F8300 and 56F8100 families of devices contain a number of features designed to ensure reliable start up from a power off condition This application note provides the 7 Troubleshooting qcicchinsienienann 6 background you need to best take advantage of these features 6 Minimum Voltage Requirements 6 i 8 CONCLUSIONS wees eccsseves cescstesteccenresaesesueees 7 Issues which must be considered include Oscillator start up times TL Referentes ei bee0Sexivess vids iveaeitioseeeceenss 7 e Reset timing e Minimum voltage requirements for high speed e Supply ramp times Note For brevity and clarity when referring to both the 56F8300 and 56F8100 versions of a device or device family the term S6F8xxx will be used For example S6F8x2x refers to both 56F832x and 56F812x devices 2 Oscillator Start up 56F8300 and 56F8100 devices fall into two categories with respect to clock generation The 56F832x devices boot from an internal relaxation oscillator The relaxation oscillator s start up time is negligible and can be ignored The 56F8x4x 56F8x5x and 56F8x6x devices boot from an on chip os
4. IO_C_PUR 1 0 Are the XTAL and EXTAL pins still programmed for use by the oscillator and not by the GPIO in GPIO_C_PER 1 0 Is the CLKMODE bit in the OSCTL set to Logic zero It defaults to one If you have the ability to monitor the supply currents do they match expected values See the application note Controlling Power Consumption AN1991 for expected values Do you have at least 4 4uF total of capacitance or more on the V cap pins when using the internal regulator If not the internal supply could droop when switching to a high core frequency Monitor the Vcap pins with your scope For devices which have EXTBOOT and EMI_MODE pins are they set to the correct values If booting from external memory do you see address bus activity Contact Freescale Technical Support for assistance http www freescale com Conclusions The 56F8300 and 56F8100 devices are designed to be robust and should start reliably By observing the simple suggestions given in Section 2 through Section 4 you should be able to avoid any problems with your application And if you do have problems the troubleshooting procedure outlined in Section 5 will allow you to quickly spot and correct the problem Te References The following references can be found on the Freescale web site at http www freescale com 1 2 3 56F8300 Peripheral User Manual MC56F8300UM 56F83xx S6F81xx Technical Data document specific to the device you re implem
5. cillator which is designed to work with either an external crystal or an external ceramic resonator The oscillator has two power modes low and high and boots in the high mode Use of the high power mode at start up ensures that 1 A recommended circuit is included in the device s data sheet Freescale Semiconductor Inc 2005 All rights reserved 2 freescale semiconductor e ae ae Ca Oscillator Start up oscillations begin reliably regardless of whether a crystal or resonator is connected to the oscillator pins Systems which utilize crystals connected to these pins must switch the oscillator mode to low power immediately upon exiting reset Failure to do so could result in long term damage to the crystal Figure 2 1 and Figure 2 2 illustrate Vpp and the XTAL signal from the oscillator during the power up sequence Note that systems utilizing ceramic resonators begin oscillating much faster than those utilizing crystals However crystals tend to provide for tigher control over the oscillation frequency 1mS per divisio Figure 2 1 Oscillator with Crystal Start Up Over Time the XTAL trace is badly aliased at 1mS per division the actual oscillation is at 8MHz Figure 2 2 Oscillator with Resonator Start Up Over Time Start Up Considerations Rev 1 Freescale Semiconductor 3 Reset Timing The power supervisor for the 56F8300 and 56F8100 families include sensors which trigger at the fo
6. enting DSP56800E Reference Manual DSP56800ERM Start Up Considerations Rev 1 Freescale Semiconductor 7 How to Reach Us Home Page www freescale com E mail support freescale com USA Europe or Locations Not Listed Freescale Semiconductor Technical Information Center CH370 1300 N Alma School Road Chandler Arizona 85224 1 800 521 6274 or 1 480 768 2130 support freescale com Europe Middle East and Africa Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen Germany 44 1296 380 456 English 46 8 52200080 English 49 89 92103 559 German 33 1 69 35 48 48 French support freescale com Japan Freescale Semiconductor Japan Ltd Headquarters ARCO Tower 15F 1 8 1 Shimo Meguro Meguro ku Tokyo 153 0064 Japan 0120 191014 or 81 3 5437 9125 support japan freescale com Asia Pacific Freescale Semiconductor Hong Kong Ltd Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po N T Hong Kong 800 2666 8080 support asia freescale com For Literature Requests Only Freescale Semiconductor Literature Distribution Center P O Box 5405 Denver Colorado 80217 1 800 441 2447 or 303 675 2140 Fax 303 675 2150 LDCForFreescaleSemiconductor hibbertgroup com Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products There are no express or implied co
7. is the clock signal present on XTAL and is EXTAL grounded If using an external power supervisor was RESET asserted until after the oscillator was operating Does the RSTO signal deassert on devices in which it is pinned out This signal represents the reset state of the 56800E It should take approximately 1 4 second to deassert when using the internal power supervisor It should deassert less than 1 5usec assuming an 8MHz clock source after an external power supervisor deasserts Modify your pre main startup code to enable the CLKO pin for devices in which it is present then monitor this pin to ensure your internal clocks are active Try updating your Metrowerks stationery A corrupted start up routine can make a part appear to be inoperative when in fact there is a software issue For all but the 56F8x22 devices is the OCR_DIS pin set to ground when utilizing the internal core logic regulator Set to Vpp so when utilizing an external regulator For the 56F8x4x 56F8x5x and 56F8x6x devices is the CLKMODE pin set to ground for devices using an external resonator or crystal Set to Vpp jo when using an external clock source Start Up Considerations Rev 1 Freescale Semiconductor 15 16 17 18 19 20 6 POR in the 56F8x4x 56F8x5x and 56F8x6x For the 56F8x2x devices did things go astray after switching to an external resonator or crystal If so ensure that internal pull ups are still disabled via GP
8. llowing voltages 1 8V POR on the core logic supply e 2 2V LVI on the core logic supply e 2 7V LVI on the IO supply The core logic supply must be within the range of 2 25 to 2 75 for normal operation and the IO supply must be 3 0 to 3 6V for normal operation It is assumed that the core supply rises in lockstep with the IO supply This happens naturally when using the internal core regulator Deriving the 2 5V rail from the 3 3V rail externally should also work The 56F8300 and 56F8100 families of devices give the designer the choice of relying on the internal power supervisor circuit or providing an external signal to reset the part When using the internal power supervisor to reset the device the external RESET pin should be tied resistively to Vpp Operation of the 56F8x2x devices is different from the other devices in the family Both configurations are discussed in the following sections 1 POR Power On Reset 2 LVI Low Voltage Interrupt 3 For all but the 56F8x22 which do not support the option of an external regulator Start Up Considerations Rev 1 Freescale Semiconductor 3 Reset Timing 3 1 POR in the 56F8x2x External TRST active low D JTAG POR Power Pulse Shaper Supervisor Delay 32 Extended_POR Memory Subsystem active low OSC clocks CLKGEN_RST OCCS PERIP_RST Peripherals External active low OSC clocks Pulse Shaper Delay 32
9. pyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document Freescale Semiconductor reserves the right to make changes without further notice to any products herein Freescale Semiconductor makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Typical parameters that may be provided in Freescale Semiconductor data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts Freescale Semiconductor does not convey any license under its patent rights nor the rights of others Freescale Semiconductor products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use Freescale Semiconducto
10. r products for any such unintended or unauthorized application Buyer shall indemnify and hold Freescale Semiconductor and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part ey 2 freescale semiconductor Freescale and the Freescale logo are trademarks of Freescale Semiconductor Inc All other product or service names are the property of their respective owners This product incorporates SuperFlash technology licensed from SST Freescale Semiconductor Inc 2005 All rights reserved AN1994 Rev 1 9 2005
11. that both low voltage interrupts have cleared prior to enabling the Phase Locked Loop PLL and proceeding into main application The start up code should oversample the LVI bits several times to eliminate any effects of system noise The LVI check is somewhat redundant as the conditions put forth in the prior sections usually ensure that core and IO voltages have reached legal limits prior to releasing the 56800E core to begin operation but it does provide an extra degree of safety Finally make sure that both PLL lock bits indicate that the PLL has locked onto the desired frequency prior to switching the system clock source to use the PLL output Switching to the PLL output prior to acheiving lock will result in inconsistent and probably incorrect operation over time and between multiple devices 5 Troubleshooting If you encounter start up problems check the following l O me NDA FR wD k So 11 12 13 14 Confirm 3 3V is present on Vpp jo and Vppa osc pLL and Vppa apc Confirm 2 5V is present on the Vcap pins How long are the ramp rates for the supply pins If using an external power supervisor did RESET deassert and how long was it asserted If using the internal power supervisor was RESET high during the power up sequence If using a crystal or resonator are the XTAL and EXTAL pins oscillating Does your oscillator circuit match that suggested in the device data sheet If using an external clock source
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