Home

V850E/IA1, V850E/IA2 32-Bit Single-Chip Microcontrollers AC Motor

1. Target speed and position update processing kokckckck ckckckckckckckckckckckckckckckckckck ckck ck ck ckck ck kckck KK RK KK ck ko KR ck kk if cont mode SPEED O position o speed Sa position o position e now position if anit flag OFF if abs sa position gt SA POSI MAX POERO 0 PWM output off error flag ERR NO2 Sets to 1 position error j j if cont mode POSITION sa position sa position kp KPGETA j Application Note U14868EJ2VOAN 113 CHAPTER 8 PROGRAM LISTS Speed control processing YX XX X X X X xxx xk dk ok ok ok ok ok ok AKAN d speed sa position wrm O iqp ksp d speed o iq o iqp i speed gt gt KSIGETA if i speed gt IS MAX i speed IS MAX else if i speed lt IS MAX l speed IS MAX else i speed ksi d speed j Current control processing X XX X X X X X x xxx x ck ck ek ek ek ek ek eoe oko oko oko J iu ADCROO amp Ox3ff 0x200 u phase current value Ly e CC ADCRIO GS OxSff 9 0x200 4 v phase current value ADSCMOO 0x9801 Starts A D conversion for speed volume if abs iu gt MAX I abs iv gt MAX I POERO 0 PWM output off error flag ERR NOL Sets to 1 overcurrent error 2 iv sin tre iu sin tre 6667 gt gt SGETA ig iv sin tre 2500 iu sin tr
2. Target position pulses signed int now speed Current speed pulses ms signed int o speed Target speed pulses ms signed Imt i speed Speed integral value area signed int O EEBD S Target position for initialization 110 Application Note U14868EJ2VOAN CHAPTER 8 PROGRAM LISTS 8 3 Main Routine 8 kk ke ke ke ke ke khe khe ke khe coke khe kc coke kc kc kc ck kc III I I kckckckckckckckckckckckck ck ck I ck ck ck ck ckckckckckckckckckckck kk Program for 3 phase motor ud ty sy J FECE kk KAKAK ke khe khe khe khe khe che che coke kc KKK kc kc kc kc kc kckckckckckckckckckckck ck ckck ck ck ck ck ck ck ck ck ckckckckckckckck ck ko void main void hinit void ainit void led_out int y ey unsigned char sw proc_no sw mode signed int i speed Initialization processing Y XX X X X X X X X X X x xk ck I e e eek ek ok oko oko E ok ok ek ek e IO IO IO ke POG 5 Hardware initialization ainit Initialization of area used ee xa eee Interrupt enabled while stop flag OFF Wait for origin detection Lor i 40000 i 0 i 2 DEC 3 Interrupt disabled annie 5 Re initialization of area to be used init flag s OFF 3 Clears to 0 initialization flag POERO Ox3f Allphases active proe no e 0 Initialization of current processing No SBI 7 Interrupt enabled whil
3. 61 TOMO a 62 uei m a eee 72 TOMO c 79 U UDC mode sss 74 UDOMmode A a 74 76 Up down counter mode ssssess 74 Use of encoder counter in application circuit GXAITIDIG seres A dd inani uet DS RUM RN 76 Use of PWM timer in application circuit GXample se ee 55 120 Application Note U14868EJ2VOAN APPENDIX A INDEX W ee ee eee 89 Wait timer interrupt servicing 103 115 PTT 87 Watchdog timer circuit block 40 Watchdog timer output pp 38 Application Note U14868EJ2VOAN 121 APPENDIX B REVISION HISTORY The history of revisions up until now is shown below The Applied to column indicates the chapters in each edition Throughout e For V850E IA1 the following product has been deleted uPD703117 e For V850E IA1 the following products have been added uPD703116 uPD703116 A uPD703116 A1 uPD70F3116 uPD70F3116 A uPD70F3116 A1 e The following products V850E 1A2 have been added uPD703114 uPD70F3114 e The status of the following product has changed from under development to development complete uPD70F3116 e Bits defined as reserved words in the device file have been specified bits whose bit numbers are in angle brackets lt gt CHAPTER 1 Addition of Differences Between V850E IA1 and V850E IA2 NLIS Addition of Pin configuration top view Addition of Internal block diagram CHAP
4. Addition of cautions to Figure 5 21 Timer Control Register 10 TMC10 Modification of values in Table 6 2 List of Constants The mark shows major revised points 6 Application Note U14868EJ2VOAN Target Readers Purpose Organization How to Use This Manual INTRODUCTION This application note is intended for users who understand the functions of the V850E IA1 V850E IA2 and who design application systems that use these microcontrollers The applicable products are shown below e V850E IA1 Standard products PD703116 70F3116 Special products PD703116 A 703116 A1 70F3116 A 70F3116 A1 e V850E IA2 uPD703114 70F3114 The purpose of this application note is help users understand the use and composition of the V850E IA1 V850E IA2 timer counter functions real time pulse unit The system example presented here is a 3 phase servo motor control application circuit which features vector operation based on PWM output encoder input and A D converter input This application note is divided into the following sections e Introduction e Functions of V850E IA1 V850E IA2 e Functions in application circuit example e Program configuration e Hardware configuration e Flow chart e Control system e Program list lt is assumed that the reader of this application note has general knowledge in the fields of electrical engineering logic circuits and microcontrollers Cautions 1 Application examples in this manual a
5. Two power supplies one for the internal CPU and one for the peripheral interface are not necessary A5 V single power supply system can be configured by connecting an N ch transistor 28D1950 VL standard product surface mount type or 2SD1581 independent type is recommended If a 3 3 V power supply is available it can be directly connected to the REGIN pin Multiplication function x1 x2 5 x5 x10 using PLL clock synthesizer Divide by 2 function using external clock input HALT IDLE and software STOP modes 100 pin plastic LQFP fine pitch 14 x 14 All static circuits Application Note U14868EJ2VOAN 21 CHAPTER 1 INTRODUCTION 1 3 2 Pin configuration top view e 100 pin plastic LQFP fine pitch 14 x 14 uPD703114GC xxx 8EU uPD70F3114GC 8bEU INTP4 TOSOFF P05 ADTRG1 INTP3 P04 O ADTRGO INTP2 P03 ESO1 INTP1 P02 ANIO5 AVbp1 AVss1 ANI10 ANI11 ANI12 ANI13 ANI14 ANI15 ANI16 ANI17 MODEO Vsss HV np REGOUT REGIN X1 X2 RESET CVss ESOO INTPO PO1 NMI POO TCLR10 INTP101 P12 TCUD10 INTP100 P1 1 TIUD10 TO10 P10 PCM1 CLKOUT PCMOAWAIT PCT6 ASTB PCT4 RD PCT1 UWR PCTO LWR V DD Vsss MODE1 VPPNote PDH5 A21 PDH4 A20 PDH3 A19 PDH2 A18 PDH1 A17 PDHO A16 CONDO AO N 22 CKSEL SIO P40 SO0 P41 SCKO P42 RXDO P30 Note uPD70F3114 only Vss O Vpop O TXDO P31 O SI1 RXD1 P32 O S01 TXD1 P33 O PDLO ADO PDL1 AD1 PDL2 AD2 PDL3 AD3 PDL4 AD4 PDL
6. Vpps Positive power Supply 3 3 V ae Ground potential Vss5 Remark H High level L Low level 30 Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION Table 3 1 V850E IA1 Pin Assignment 3 4 O Mode Setting Signal Name 81 PCSO Input Not used IM o 89 VPP Flash write power supply Ground potential Positive power supply Not used o o TUI 105 TIUD10 Input Encoder A phase input TCUD10 Encoder B phase input L TCLR10 Encoder Z phase input L TIUD11 Not used TCUDI TCLR11 11 POO ESO0 PWM output stopped F 113 P Not used 02 m m ws re 116 P05 S ll 119 TOOOO Output U phase output H TO00 U phase output 121 TOO02 Output V phase output T0003 V phase output Remark H High level L Low level Application Note U14868EJ2VOAN 31 CHAPTER 3 HARDWARE CONFIGURATION Table 3 1 V850E IA1 Pin Assignment 4 4 VO Mode Setting Signal Name 123 TO004 Output W phase output H 0 toon fJ 131 TO012 TO013 TO014 139 ANIO1 Input Speed volume value input 0 to 5 V ANIO2 Notused ANIOS C a m ws Du we Remark H High level L Low level 32 Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION Table 3 2 V850E IA2 Pin Assignment 1 3 VO Mode Setting Signal Name Not used EE eT Positive power supply to A D converter 8 favs
7. 117 LED OUPO o et 36 EEL QUIDUT DIO CK dct cress scinntwe eden eden tices ines 40 M Main PGT de 91 111 MAX ld ee 89 MAXPBLESE iun eo a ees 88 Memory MaD eoira E N 27 Application Note U14868EJ2VOAN 119 APPENDIX A INDEX Microcontroller and microcontroller peripheral block 40 MOda E ee E 76 Motor control constants pp 90 Motor control Interrupt sees eee ee eee 113 Motor control interrupt Servicing 97 113 MOTOR CODITTOIlGT oen Do cele ier elastin ae 40 Motor rotation indicator pp 40 Motor specifications pp 47 N Ae E Eo ATA A 78 O ODOSNON eu ee 87 O SHEGO a ed 87 eN n ETT 87 OEP OE I e aan eee 88 OperallOWm we eb 25 Operation mode switch block 40 Operating mode switch input 38 Overcurrent ertO sse Te eei PE Fa Pha epos 25 P E Ph cepacia oes i SL EU EDI E MEER ESI 88 Peripheral Pod 36 Peripheral MO initialization processing 104 116 Pulse SSIG MING S mee iente aioe teen eerie 29 PORRO Se ooa fe Tres 68 POSINOM COMUO Se en om ect oec use 46 48 POSITIONING Cli Ol Sm a dux mea P aS 25 Prescaler mode register 10 80 msi O Z oe a HR ORAE MUNERE 61 PIM O2 socii n erp ne d ciu artum d s 77 ETIT m aie aoe amen 80 Program configurationm pp 84 PFOORAIM NSS se on oan de ne on nh 109 55 T6900 TT 64 PWM conversion pp 47 50 PINNE OUOU C ORT 3
8. 3 ON Request sent OFF No request stop_flag unsigned char Stop motor rotation see 4 ON Stopped OFF Rotating init_flag unsigned char Rotating to detect motors origin see 1 ON Rotating to detect motor s origin OFF Normal rotation cont_mode unsigned char Motor s control method see 2 POSITION Position control SPEED Speed control error flag unsigned char Error 0 No error ERR NO1 Overcurrent ERR NO2 Position error ERH NOS Drive error unsigned short Wait time measurement counter Set value timeout occurs at zero Unit 10 ms mms wa a O O Description of main common areas 1 init flag The motor is rotated twice at a constant torque to detect the Z phase so that the absolute positions of the motor s axes can be determined init flag is set to ON during this rotation to detect the origin and it is used for origin detection rotations as motor control processing 2 cont mode In the application circuit example s motor control processing either the speed or the position is controlled cont mode is used to select the control method 3 stop req If the operation mode is changed during operation in either the clockwise or counter clockwise direction operation is temporarily stopped before starting again in the newly set operation mode 86 Application Note U14868EJ2VOAN 4 5 6 7 8 9 CHAPTER 6 PROGRAM CONFIGURATION stop flag This flag is used to report the end of origin detection
9. KCKCK kk ee ke ke ke khe ke ke ke ke khe khe kc kc I kc III III I FO FO FO I I I ck ckckck I I I ck ck I I Ie de de de ae x CC30 interrupt servicing 10 ms interval x ag x f Kk kk kk kk ee I kk kk kk kk I I FI FI FI FF ck ckckckckckckck ckckckckokckokckokckokckokckokckokckokckokckok I I x x fl interrupt word Lb oe 0 vored Lf tamer count l e 4 timer count 1 Application Note U14868EJ2VOAN 115 CHAPTER 8 PROGRAM LISTS 8 6 Peripheral I O Initialization Processing Et t Hardware peripheral lO initialization x a FCKCK kk ke ke ke khe ke ke khe khe khe khe khe khe khe ke kc KKK KK KK KKK KAK KKK KK KKK KAKAK void hinit void vord led outi unu 5 Port mode register initialization XY X X X X X x Xx RK KK k k KK RK k e KK e ke KK RK KKK RK KK kk KK KK k k KK e ke ke ke e ke ke x J PMC1 0x07 Selects encoder input PMC2 0x00 PM2 0x00 Sets LED s low order port PMC3 0x00 PM3 0x00 Sets LED s high order port P4 0x00 Watchdog timer low output PMC4 0x00 PM4 0x04 led out 0x0000 LED output OFF Timer 3 mode setting eR RR A
10. MSB most significant bit Output to LED1 to LED16 EXIT 106 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS 7 7 sin Calculation Processing Figure 7 7 illustrates the flow of sin calculation processing Figure 7 7 sin Calculation Processing See 8 9 Calculation Processing Input value unit pulse for calculating sin x as multiplied by 2 4 oe Yes x 10 000 x ee Yes oc p sins x See Figure 7 8 Subroutine Processing for sin Calculation EXIT sins 5 000 x See Figure 7 8 Subroutine Processing for sin Calculation sins x 5 000 See Figure 7 8 Subroutine Processing for sin Calculation sinx 10 000 x See Figure 7 8 Subroutine Processing for sin Calculation Application Note U14868EJ2VOAN 107 CHAPTER 7 FLOW CHARTS 7 8 Subroutine Processing for sin Calculation Figure 7 8 illustrates the subroutine processing for the sin calculation Figure 7 8 Subroutine Processing for sin Calculation See 8 9 Calculation Processing Yes Calculate the sine value using Taylor series approximation 2 000 x Calculate the cos value using Taylor series approximation 108 Application Note U14868EJ2VOAN CHAPTER 8 PROGRAM LISTS This chapter presents program lists from the application circuit example using the V850E IA1 8 1 Definition of Constants pragma ioreg Peripheral I O register definition pragma interrupt INTCC3
11. ss eee 64 Buffer Registers CMOO to CMO3 BFCMOO to BFCM03 pp 66 Dead time timer Reload Register 0 DTRRO sss ese 67 PWM Output Enable Register 0 POERO sese eee 68 Timer Control Register 00 TMGCO0 4 69 Timer Unit Control Register 00 TUCOO en 72 Block Diagram ot Timer TO CEMO se oim oe enero tonius 73 Mode J 76 Timer 1 Timer 2 Clock Selection Register PRMO2 se 77 Timer 10 Noise Elimination Time Selection Register NRC10 pp 78 Timer Unit Mode Register O TUMO nnm 79 Prescaler Mode Register 10 PRM10 80 Signal Edge Selection Register 10 SESA10 sa de 81 Timer Control Register 10 TMCT10 4 83 ONCE 84 MAN OLEO aot o ab ota lao atout A ou loue dau a 91 Motor Control Interrupt Servicing 0 4 ms Interval sees eee eee 98 Wait Timer Interrupt Servicing 10 ms Interval pp 103 Peripheral I O Initialization Erocess DR 104 Common Area Initialization ProcesSsing pp 105 Application Note U14868EJ2VOAN LIST OF FIGURES 2 2 Figure No Title Page Figure 7 6 LED DISplay OUDDUET TOCOSSID T 106 Figure 7 7 sin Calculation Processing pp 107 Figure 7 8 Subroutine Processing for sin Calculation pp 108 Application Note U14868EJ2VOAN 13 Table No Table 1 1 Table 3 1 Table 3 2 Table 3 3 Table 4 1 Table 5 1 Table 6 1 Table 6 2 Table 6 3 14 LIST OF TABLES Title Page Differences Between V850E IA1 and V850E IA2 i 15 V850E IA1 Pin Assignment 4 29 Ur DO
12. 2 List of Constants oF mop HT sop swmm 00 9 semp aeaa OOOO ones CM3_DATA Timer 00 TMOO CM003 setting value see 9 65 BFCM DATA Timer 00 TMOO BFCM maximum setting value see 10 65 Description of main constants 1 P This is the number of poles per motor rotation as used in this application circuit example One rotation of the motor equals the waveform for four electrical rotations 2 MAXPULSE This indicates the number of encoder pulses per motor rotation 1 rotation 2 500 pulses x 4 10 000 pulses 3 OFFSET This indicates the offset between the motors Z phase and the coil position 88 Application Note U14868EJ2VOAN 4 5 6 7 8 9 CHAPTER 6 PROGRAM CONFIGURATION SPEED MAX This is the maximum rotation speed of motor as used in this application circuit example 100 x 60 0 4 ms 10 000 pulses 1 500 rpm VMAX This is the amount of voltage that is applied when PWM reaches 100 The applied voltage corresponding to 100 PWM remains the same even if the calculated VMAX value is greater than that IS MAX This is the maximum speed integral value This value is the highest value possible for 15 MAX MAX I This is the maximum current value An overcurrent occurs if the MAX value is exceeded SA POSI MAX This is the maximum position displacement value If the position displacement exceeds the SA POSI MAX value a position error occurs CM3_ DATA This
13. 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 4 1 Figure 4 2 Figure 5 1 Figure 5 2 Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 Figure 5 7 Figure 5 8 Figure 5 9 Figure 5 10 Figure 5 11 Figure 5 12 Figure 5 13 Figure 5 14 Figure 5 15 Figure 5 16 Figure 5 17 Figure 5 18 Figure 5 19 Figure 5 20 Figure 5 21 Figure 6 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 Figure 7 5 12 LIST OF FIGURES 1 2 Title Page LED SIS VAY OL MIDBSSIQF Ss aan tala leeches tale dnte cunt de 26 Hardware Configuration DiagramM sse eee eee ee eee 26 WIG TORY WIAD Ni HT eo eo oe co 27 Memory Map GOO NAZ ea 28 LED Display V850E IA1 sse 37 BREST 0E 2124 c 37 runelons or Tort 4 CV8bOE DAT scaduta cutem natat ont ea 37 Functions of Port VO a TA sese 38 Circuit Diagram of Application Circuit Example pp 41 EdilvalenbGItoulis sa iiio ito b ooa pe toa ace pe cef tg 43 Control BIOC sc s sees 46 Block Diagram of Timer 00 TMOO PWM Mode 0 Symmetric Triangular Wave 52 Operation Mode Seti a dn de 56 Operation Timing in PWM Mode 0 Symmetric Triangular Wave sessesee 59 Overall Operation Image of PWM Mode 0 Symmetric Triangular Wave 60 Timer O Clock Selection Register PRMOT 61 TOMR Write Enable Register 0 SPECO 4 61 Timer Output Mode Register 0 TOMRO pp 62 PWM Software Timing Output Register 0 PSTGOO
14. 5 gt 4 3 2 1 TMCOO0 TMOCEO ISTINTO CULO2 CULO1 CULOO PRMO2 PRMO1 PRMOO 0 o TMoCEDO BFTE3 BFTEN MBFTE MODO1 MOD00 FFFFF57AH 0508H 15 TMOCEO Specifies the operation of TMOO 0 Count disabled stops after all count values are cleared 1 Count enabled Caution When TMOCEO 0 TO000 to TO005 outputs become high impedance 14 STINTO Specifies interrupt occurrence during TMOO timer start 0 Interrupt does not occur at operation start 1 Interrupt occurs at operation start When STINTO bit 1 an interrupt occurs immediately after the rising edge of the TMOCEO signal When MOD01 bit 0 triangular wave mode the INTTMOO interrupt occurs and when the MOD01 bit 1 sawtooth wave mode the INTCM003 interrupt occurs Caution Changing the STINTO bit during TMOO operation TMOCEO bit 1 is prohibited 13 to 11 CULO to Specifies the interrupt culling ratio oe ofofo w oo joo o w Lo nr ol Z w oo Jot o o wo o jojo J gJ We Other than above Culling not performed Cautions 1 The INTTMOO interrupt and INTCMOO3 interrupt can be culled with the same culling ratio 1 1 1 2 1 4 1 8 1 16 Even when BFTE3 bit 1 BFTEN bit 1 settings to transfer data from BFCMOO to BFCMO3 registers to CM000 to CMO0OS registers transfer is not performed with the generation timing of culled INTTMOO and INTCMOOS interrupts if MBFTE bit 0 If the culling ratio is changed during a count operation
15. ARR RR ck ck ke I I I I I II I I I I IO ke ko ke ko ke ke ke ke ke e ke e ke e PRMO3 0 fclk2fxx 2 TMCS3OQ 0x31 50 MHz 2 16 0 64 us TMC31 0x09 Selects compare mode CC30 15625 nt cc30 10 ms interval TMC30 0x33 Starts timer COSTOO 25 034 Resets cc30 interrupt mask Timer 4 mode setting FRR RR I RR I I I I I kk koe kc kc kc kc koc kc ck kk kc I I ke ke ke ke ke ke ke e ke e ke e TMC4 0x31 50 MHz 2 32 0 64 us CMA 625 int cm4 0 4 ms interval TMC4 0x33 Starts timer CMAICO 0x02 Clears cm4 interrupt mask Initial settings for ADCO and ADC1 Kk RR KK RR ckck RR RK KK RR KK RRR KR RK RR KK KR k k k ckckckck KK KK KK RK k k KK KKK ADSCMOO O0x0000 ADSCMO1 O0x0000 Initial setting for ANI10 ok ckckckck RRR k k KKK RR KR KK RK ckckckckck ckckckckckckckck ckck RK k RK KR RR ckck ck kckck ck ko k k KK ck kk ADSCM10 0x0000 ADSCM11 0x0000 Timer 00 TMOO initialization XX X X X X XX Xx xk ok k k RK RK e ke KK RK KK RK KKK RK KK RK J PRMO1 0 fclk fxx 2 SPECO 0x0000 TOMRO write enabled TOMRO 0x03 Output mode setting PSTOO 0x00 Real time output prohibited BFCMOO0 BFCM DATA 2 Sets 50 duty BFCMO1 BFCM DATA 2 Sets 50 duty BFCMO2 BFCM DATA 2 Sets 50 duty BFCMO3 CM3 DATA Sets PWM cycle DTRRO 50 Deadtime 2 us POERO Ox3f All phases
16. Ground potential for A D converter ov ANI10 Input V phase current input O to 45V 4 Not used E 8 ANI Ld NI15 Operation mode 0 Ground potential Positive power Supply to regulator REGOUT Output Regulator input REGN Regulator output Input System clock H Drive error input Em m mu mee 00 LIr e Em ear m 98 IY Ground potentia 9 lv Positive power supply Remark H High level L Low level Application Note U14868EJ2VOAN 33 CHAPTER 3 HARDWARE CONFIGURATION Table 3 2 V850E IA2 Pin Assignment 2 3 VO Mode Setting Signal Name PDLO Output LED1 output POL LED output E PDL2 LED3 output Output LED4 output a PDL4 LEDS output Ea PDLS LEDS output i PDL6 Output LED7 output L e PDL LEDS output PDL8 Output LEDO9 output L La mu oma ibwama o m ea qom Dm E LED12 output m mus owe a O E ma i94 Mad s CO ON 4 2 LED15 2 S PDLB 5 Output LED16 LED16 output 0 HE PDHO Input Not used TCUD10 Input Encoder B phase input L em TCLR10 Encoder Z phase input mim p mem a ua SOS PWM output stopped Not used Remark H High level L Low level 34 Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION Table 3 2 V850E IA2 Pin Assignment 3 3 TOOOO Output U phase output ax lt Output V phase output L Fw xw omu O E MD I LE
17. Ld Positive power SEDE AVppo Positive power supply to A D converter 5V s ne Ground potential for A D converter ANIOO Input U phase current value sell 0to 45V Not used ANIO3 wo mw EE NN Remark H High level L Low level Application Note U14868EJ2VOAN 35 CHAPTER 3 HARDWARE CONFIGURATION 3 3 3 Peripheral I O The following types of peripheral I O functions are used in this application circuit Table 3 3 List of Peripheral I O Functions Peripheral I O Function Peripheral I O Function o Description V850E IA1 V850E IA2 P20 to P27 PDLO to PDL15 LED output P30 to P37 P40 P41 P30 P31 Operation mode switch input Watchdog timer output Timer 00 TMOO PWM output 1 Description of peripheral I O functions a LED output LED output uses P20 to P27 and P30 to P37 for the V850E IA1 and PDLO to PDL15 for the V850E IA2 e LED display method LEDs light to indicate when a bit value is O zero For the V850E IA1 pins P20 to P27 LED1 to LED8 and pins P30 to P36 LED9 to LED15 indicate absolute numerical values and P37 LED16 indicates the minus sign For theV850E IA2 pins PDLO to PDL14 LED1 to LED15 indicate absolute numerical values and PDL15 LED16 indicates the minus sign 0 Lit ON 1 Not lit OFF LED displays Rotation when operation mode is STOP operation mode Indicates differential between target position and current position Rotation when operation mode is clo
18. PWM PFOM setting maximum value define KPGETA 10 kpoffset define KSIGETA 8 ksioffset define KIGETA 12 kioffset define SGETA 14 sin offset Motor constants kkk kk kk kk k k k k k k k k k k k k k k kk kk k k kk kk kk kk kk kk kk I ko kk ke ke e ke n ke x pragma section const begin signed int kp 500 Position proportional gain signed int ksp 100 Speed proportional gain signed int ksi 100 Speed integral gain signed int ki 11 Current conversion constant pragma section const end Application Note U14868EJ2VOAN 109 CHAPTER 8 PROGRAM LISTS 8 2 Common Area 8 He He ek ek heck KKK khe khe che che kk kk ck kc kc kc ck kc kc ck kc kc kc ck kc IR I I I I I I ckck ckckckckckck A Common area x FCKCK kk ek ke ke khe khe khe khe khe khe che khe che khe khe ck I kc kc kc kc kc III I II I ck ckckckckckckck ck ckckck ck KAKAK unsigned char init flag Initial flag unsigned char cont mode Control mode 0 Speed mode 1 Position mode unsigned char stop req Stop request flag unsigned char stop flag Stop flag unsigned char error flag Error flag unsigned short timer count Counter for measurement of detection time unsigned short volume Speed setting volume value signed short before enc Previous encoder value signed int now position Current position pulses signed int o position
19. RLEN ENMD CLR1 CLRO FFFFF5ECH OOH TM1CEO Enables disables TM10 operation 0 Disable TM10 count operation 1 Enable TM10 count operation 3 RLEN Enables disables transfer from CM100 to TM10 0 Disable transfer 1 Enable transfer Cautions 1 When RLEN 1 the value set to CM100 is transferred to TM10 upon occurrence of TM10 underflow 2 When the CMD bit of the TUMO register 0 general purpose timer mode the RLEN bit setting becomes invalid 3 The RLEN bit is only valid for UDC mode A TUMO register CMD bit 1 MSEL bit 0 In the general purpose timer mode CMD bit 0 and UDC mode B CMD bit 1 MSEL bit 1 the transfer operation is not performed even though the RLEN bit is set to set 1 Enables disables clearing of TM10 in general purpose timer mode CMD bit of TUMO register 0 0 Clear disable free running mode Clearing is not performed even when TM10 and CM100 values match 1 Clear enable Clearing is performed when TM10 and CM100 values match Caution When the CMD bit of the TUMO register 1 UDC mode the ENMD bit setting becomes invalid 1 0 CLR1 CLRO Controls TM10 clear operation in UDC mode A 9 9 _ Gearon by ens TRR 8 3 Gear upon math of TMIO count value and CMTOO set valve C ce and CM100 set value Cautions 1 Clearing by match of the TM10 count value and CM100 set value is valid only during TM10 up count operation TM10 is not cleared during TM10 down count operation W
20. active TMCOO O0x8018 Starts TMOO timer Timer 10 TM10 initialization XX X X X X xxx KKK k k k k KKK e ke KK ek KK RK KKK RR KR RK KKK RR KK RK KK ck ck kk KK PRMO2 0 fclk fxx 4 NRC10 0x03 Selects noise elimination clock TUMO 0x80 Selects UDC mode PRM10 0x07 Select operation mode 4 SESA10 0x00 Selects falling edge TMC10 Ox40 Starts count 116 Application Note U14868EJ2VOAN CHAPTER 8 PROGRAM LISTS 8 7 Common Area Initialization Processing 8 kk ek ee ke ke ke ke khe khe ke ke khe ce kc kc kc I kc kc ck kc kc kc ck IC I kckckckckckckckck ck ckckck I I ck ck ck ck I I I de de de ae 1 4 Common area initialization ag Sg f KKCk kk kc kc kk kk kk kk kk ce kk cock ck kc kckckckckckckckckckck ck ck ck ck ckckckckckckckckokckokckokckokckokckokckokckokckokckok kk ck ke ke e ke x ke x x x f void ainit void init flag ON Sets to 1 initial flag stop flag OFF Clears to 0 stop flag stop req OFF Clears to 0 stop request flag error flag 0 Clears to 0 error flag cont mode POSITION Sets position control as control mode now position 0 Sets 0 as current position o position e 945 Sets 0 as target position o Speed 0 Sets 0 as target speed before enc TM10 Sets previous encoder values i speed 0 Set 0 as speed integral value S Eo Eso 7 Clears to 0 th
21. certain use conditions Further Renesas Electronics products are not subject to radiation resistance design Please be sure to implement safety measures to guard them against the possibility of physical injury and injury or damage caused by fire in the event of the failure of a Renesas Electronics product such as safety design for hardware and software including but not limited to redundancy fire control and malfunction prevention appropriate treatment for aging degradation or any other appropriate measures Because the evaluation of microcomputer software alone is very difficult please evaluate the safety of the final products or system manufactured by you Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances including without limitation the EU RoHS Directive Renesas Electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations This document may not be reproduced or duplicated in any form in whole or in part without prior written consent of Renesas Electronics Please contact a Renesas Electronics sales office if you have any questions regarding the information contained in this document or Renesas Elect
22. is the value of timer 00 TMOO s compare register 003 CMO03 The CM3 DATA value determines the 20 kHz carrier frequency 10 BFCM DATA This is the maximum value when 100 V has been specified for timer 00 TMOO s buffer registers CMOO to CMO02 BFCMOO to BFCM02 11 KPGETA KSIGETA KIGETA SGETA These are offsets for various operations For example in 2 the n indicates the offset Application Note U14868EJ2VOAN 89 CHAPTER 6 PROGRAM CONFIGURATION 6 4 Motor Control Constants The motor control constants that are used in this application circuit example are listed below Table 6 3 List of Motor Control Constants Description of constants 1 kp This is the proportional gain used to convert from the position differential to speed The offset value is 2 2 ksp This is the proportional gain used to convert from speed to current 3 ksi This is the speed s integral gain The offset value is 2 4 ki This is the gain used to convert from current to voltage The offset value is 2 90 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS This chapter presents flow charts of various processing in the application circuit example using the V850E IA1 7 1 Main Routine Figure 7 1 illustrates the flow of the main routine Figure 7 1 Main Routine 1 6 START o Peripheral I O s initialization processing hinit see Figure 7 4 Peripheral I O s Initialization Processing BEEN NN Common are
23. phase or negative phase active width is 0 or a negative value in the above formula the TOO00 to TO005 pins output a waveform fixed to the inactive level waveform with active width 0 Remark m 0Oto2 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Figure 5 3 Operation Timing in PWM Mode 0 Symmetric Triangular Wave CM003 d CM003 e TMOO count value 0000H CMOOx CMOOx CMOOx CMOOx match match match match BFCMOx CMOOx BFCMO3 CM003 Interrupt request INTCM003 INTTMOO INTCM003 INTTMOO Positive phase TO000 TO002 TO004 Negative phase TO001 TO003 TO005 Remarks 1 The above figure shows the timing chart when BFTE3 and BFTEN of the TMCOO register are 1 and transfers from BFCMO3 to CM003 and from BFCMO to CMOOx are enabled Transfer is not performed when BFTES 0 BFTEN O x 0to2 t Dead time DTRRO 1 fcLk fcLk Base clock To not use dead time set the TMOCEDO bit of the TMCOO register to 1 The above figure shows an active high case Shee oco ober Figure 5 4 shows the overall operation image Application Note U14868EJ2VOAN 59 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Figure 5 4 Overall Operation Image of PWM Mode 0 Symmetric Triangular Wave e e e z O O gt cC 2 Q O TO000 output TO001 output TO002 output TO003 output TO004 output TO005 output Without dead time TOOOO ou
24. rotation and motor stoppage during normal rotation that occurs after a monitoring stop request has been issued volume The speed setting volume s A D value is stored and the following equation is used to calculate the speed setting Speed pulse 0 4 ms SPEED MAX x volume 1 024 1 before enc The previous encoder value is stored in this area and the following equation is used to calculate the differential speed variation sa enc differential current encoder value previous encoder value When the absolute value of sa enc is greater than 1 rotation encoder 2 it is regarded as beyond the zero point in which case sa enc is compensated accordingly e Sa enc lt 0 Sa enc sa enc Encoders per rotation e Sa enc 20 sa enc sa enc Encoders per rotation o position When in position control mode STOP mode the control function uses this position as the return position o speed When in speed control mode during clockwise or counter clockwise operation the speed is controlled at this setting The speed setting volume calculates and sets this speed setting o trm This area is used to set the target transfer position for origin detection rotation This value sets the amount of rotation needed to reach the second full rotation 20 000 pulses Application Note U14868EJ2VOAN 87 CHAPTER 6 PROGRAM CONFIGURATION 6 3 Constant Definition Constants used in the application circuit example are listed below Table 6
25. to BFCMO3 register e When TMOCEO bit of TMCOO register 1 Value of BFCMOS register is transferred to CM003 register upon occurrence of INTTMOO At this time transfer enable or disable is controlled by the BFTE3 bit of the timer control register TMC00 2 Setting the BFCMOS3 register to 0000H is prohibited Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 5 1 2 Use of PWM timer in application circuit example 1 Determination of PWM frequency The following factors are taken into consideration when determining the PWM frequency for motor control e Drive circuit s switching time e Dead time dead frequency band e Choke coil noise Cautions 1 If the drive circuit s switching response is poor it cannot be used for high frequencies 2 The portion occupied by dead time may be a problem when attempting to achieve high precision motor control 3 When a choke coil is used noise is heard if the PWM cycle is within the audible frequency range 4 If a very high frequency is selected it becomes difficult to achieve good resolution based on the timer setting The PWM timer s cycle is determined based on the timer s input clock basic clock and the frequency division ratio count clock The PWM timer s cycle setting is performed using the timer 00 clock select register PRMO1 and timer control register 00 TMCOO Once the count clock has been determined use the BFCMOS3 register to set the CMOOS comparison
26. up down counter mode UDC mode is used in this application circuit example a Up down counter mode UDC mode In the UDC mode TM10 functions as a 16 bit up down counter counting based on the TCUD10 and TIUD10 input signals Two operation modes the UDC A and UDC B modes can be set with the MSEL bit of the TUMO register for this mode The UDC mode A is used in this application circuit example e UDC mode A when CMD bit 1 MSEL bit 0 TM10 can be cleared by setting the CLR1 and CLRO bits of the TMC10 register When the TM1CEO bit of the TMC10 register is 1 TM10 counts up down when the operation mode is the UDC mode The conditions for clearing the TM10 are classified as follows Table 5 1 Timer 1 TM10 Clear Conditions TMC10 Register TM10 Clear CLR1 Bit CLRO Bit LO a g l Cleared upon match with CM100 set value during up count operation o ome cd Cleared by TCLR10 input or upon match with CM100 set value during up count operation 74 Application Note U14868EJ2VOAN 2 3 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Compare register 100 CM100 CM100 is a 16 bit register that always compares its value with the value of TM10 When the value of a compare register matches the value of TM10 an interrupt signal is generated In UDC mode A MSEL bit of TUMO register 0 an interrupt signal INTCM100 is always generated upon occurrence of a match Caution When the TM1CEO bit of the TMC10 register is 1
27. you for your kind support Taiwan NEC Electronics Taiwan Ltd Fax 886 2 2719 5951 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 465 250 3583 Japan NEC Semiconductor Technical Hotline Fax 481 44 435 9608 would like to report the following error make the following suggestion Document title 1 1 1 4 2 222 0 Document number If possible please fax the referenced page or drawing Document Rating Clarity Technical Accuracy Organization Excellent n n n Page number
28. 0 int cc30 Register to interrupt handler address pragma interrupt INTCM4 int cm4 Register to interrupt handler address FECE kk ek ke khe ke ke ke khe khe khe khe coke ce kc ck kc kc ck ck kc kc kc kc kc kc kckckckckckckck ck ck ckckck ck ck J Constant definitions 8K kk kc kk kk kk kk kk kk kk kk I cock ck kckckckckckckck ck ck ckckckck ck ck ckckckckckokckokckokckokckokckokckokckokckokckokckok kk ke ke ke e ke x ke x x x f define ON 1 define OFF define CW define CCW define STOP define SPEED define POSITION define ERR_NO1 Clockwise rotation operation mode Counter clockwise rotation operation mode Stop mode Speed control mode Position control mode Overcurrent error define ERR NO2 Position error define ERR NO3 Drive error Motor constants Xx XX XX X X XX ok oko KK KK ke e ke ke kk ke kk kk RK KK KR KK KK KK KK ch ke k ke ck ke KK ke ke ke ke ke ke ke ke ke k SWF A O GO KD LA O define P 4 No of poles define MAXPULSE 10000 Pulses per rotation define OFFSET 800 Origin offset define SPEED MAX 100 Maximum speed pulse 0 4 ms define VMAX 100 Maximum voltage 100 V define IS MAX 2000000 Maximum speed integral value define MAX I 400 Current maximum value define SA POSI MAX 5000 Maximum position differential pulse define CM3 DATA 625 PWM CMOOS setting value 20 kHz define BFCM DATA 625
29. 0 to CM002 PWM mode 0 Up down INTTM00 INTTM00 Symmetrical triangular waves Caution Changing of the MODO1 and MODOO bits is prohibited while TMOO is operating while the TMOCEO bit 1 Although PWM mode 0 symmetrical triangular wave mode is used in this application circuit example the optimum operation mode for the target system can be selected The next section describes the output waveform widths that correspond to the PWM mode 0 operation and settings 56 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Operation In PWM mode 0 TMOO performs up down count operations When TMOO 0000H during down counting an underflow interrupt INTTMOO is generated and when TMOO CM003 during up counting a match interrupt INTCMOO3 is generated Switching from up counting to down counting is performed when TMOO and CMO03 match INTCMO03 and switching from down counting to up counting is performed when TMOO underflow occurs after TMOO becomes 0000H The PWM cycle in this mode is BFCMOS value x 2 x TMOO count clock Concerning setting of data to BFCMOS3 the next PWM cycle width is set to BFCMO3 The data of BFCMOS3 is automatically transferred by hardware to CMOOS upon generation of the INTTMOO interrupt Furthermore calculation is performed by software processing started by INTTMOO and the data for the next cycle is set to BFCMOS3 Data setting to CM000 to CM002 which control the P
30. 1 When mode 4 is specified as the operation mode of TM10 the valid edge specifications for pins TIUD10 and TCUD10 are not valid If the TIUD10 pin edge and TCUD10 pin edge are input simultaneously in mode 4 TM10 continues the same count operation up or down it was performing immediately before the input In this application circuit example mode 4 is used so that the 2 500 pulses per rotation is multiplied by four to become 10 000 pulses To obtain the positions along the motor axes the count value is cleared whenever TCLR10 Z phase is input 2 Operation in UDC mode A In UDC mode A the encoder counter operates as a 16 bit up down counter The count clock input to TM10 in UDC mode A CMD bit of TUMO register 1 can only be external input from the TIUD10 and TCUD10 pins Up down count judgment in UDC mode A is determined based on the phase difference of the TIUD10 and TCUD10 pin inputs according to the PRM10 register setting In mode 4 the up down count is automatically judged by the detection of both edges of the TIUD10 and TCUD10 inputs In UDC mode A the TM10 clear cause can be selected as only external clear input TCLR10 a match signal between the TM10 count value and the CM100 set value during up count operation or logical sum OR of the two signals using bits CLR1 and CLRO of the TMC10 register TM10 can transfer the value of CM100 upon occurrence of TM10 underflow 76 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS
31. 2 1 0 Address After reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address After reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address After reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Address After reset 66 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 6 Dead time timer reload register 0 DTRRO settings In this application circuit example the DTRRO register is set as shown below Dead time 2 us In the case of the V850E IA2 the DTRRO resister is set as shown below Dead time 2 us Figure 5 10 Dead time timer Reload Register 0 DTRRO 14 13 Address After reset 15 12 1110 9 8 7 6 5 4 3 2 1 0 pmRo oj0j0J0 jJ yj j FEFEEFS7on XFFFH Application Note U14868EJ2VOAN 67 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 7 PWM output enable register 0 POERO In this application circuit example the POERO register is set as follows POERO Ox3f all phases active When an error occurs output is disabled by writing 00H to the POERO register Figure 5 11 PWM Output Enable Register 0 POERO 1 Address After reset 7 6 lt 5 gt lt 4 gt lt 3 gt lt 2 gt 0 POERO o o OE210 OE200 OE110 OE100 OE010 OE000 FFFFF57FH 00H OE210 Specifies the output status of the TOO05 pin 0 TOOO05 output status is high impedance 1 TOO05 output status is controlled by TMOCEO bit of TMCOO register and TORTOO bit of PSTOO register and ESOO p
32. 3 interrupt Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Figure 5 12 Timer Control Register 00 TMCO0 3 3 BFTEN Specifies transfer of data from the BFCMOO to BFCMO 2 registers to the CMOO0 to CMOO2 registers 0 Transfer disabled Transfer enabled BFTEN TMO00 Operation Mode BFCMOO to BFCMO2 CM000 to CMOO2 Transfer 777 f E All Almdes sd No Notanser PWM mode 0 symmetric INTTMOO triangular wave When the BFTEN bit 1 the values of the BFCMOO to BFCMO registers are transferred to the CMOOO0 to CMOO 2 registers upon occurrence of an INTTMOO or INTCMOOS3 interrupt MBFTE When culling of the INTTMOO and INTCMO003 interrupts is set with the CULO2 to CULOO bits specifies whether enable or disable the BFTE3 and BFTEN bit settings upon occurrence of an interrupt for culling 0 Disable the set values of BFTE3 BFTEN bits upon occurrence of a culling interrupt 1 Enable the set values of BFTE3 BFTEN bits upon occurrence of a culling interrupt The various combinations are as follows MBFTE Operation upon Occurrence of Interrupt for Culling NEM NNNM DNE Co BFTEN BFCMOO to BFCMO2 CM000 BFCMOO to BFCMO2 CMOOO to CMOO 2 transfer disabled to CMOO 2 transfer disabled 1 BFCMOO to BFCMO2 CM000 BFCMOO to BFCMO2 CM000 to CMOO 2 transfer disabled to CMOO 2 transfer enabled BFTE3 BFCM03 CM003 transfer BFCM03 CM003 transfer disabled disabled 1 BFCM03 CM003 tran
33. 43 A20 PDH4 apres FFF a N ar ar VR2 R82 47 P34 34 SORTA A ED 75 P75 R83 47 1K 12V R8447 P35 35 R85 47 Res R87 R88 47 a 2 CRXD P46 A17 PDH1 z4 ca R89 47 CTXD P47 o A16 PDHO 1 CCW raat 0 CB 3 E BE ANNER 0 1u film a4 so BSRNRAREL nu duca er C9 C40 Ci C12 C13 C14 C15 O599g90gbaEEEEZOD 6505506665579099 0 1uF O tuF 0 1uF 0 1uF 0 1uF 0 1uF O tuF MHS131 aPpaPdraPatzzzz eF lt l lt J lt J lt J lt J ee e R90 AGND SSzcxag 25ass 2 o0095050205000000006 qdoxuo T T i 1 1 t QOROAS CAO SAN RATE SAONDHNOASTAHDPHOOROSr C CC C 2 2K A xX S X OxxmOdoooooeoQoooaQ0QGaaaaagooaaaaaaanog Operation mode switch crKcH TH REEECERERA XXX uauu4XuX4X44 Tl LL EU T Spo oo OD AY CD St LO CO oe SO CU CD oe OI e CO St LO TN oo e CV a lled c xr LO CO NJ aai 9 cy OJ O cy c xt LO COP o i e AGND co 69 SF xt St SH St SH St n Lo LOJ LO LF GO CO col eol J co co co CHO N N N 0 1uF 0 1uF 0 1uF Ojo A G GU a G G DL n G J Q G DL OL G GU OL a G DL G DL Qu T OA ee le TTT TT TT BEEN TT Tt tt tf U6A 2_RN 1 R91 2 1 330 DS1 LED U6B 74ACT14 Z 2 KM 1 R100 4 3 330 Z Z U6C DS3 LED U6D 74ACT14 2 AM 1 R110 8 lt 9 330 DS4 LED 74ACT14 U6E 2 FM 1 R111 10 11 R107R102R103R104R105R106R 107108 1 330 47 47 47 47 47 47 47 47 45V 5 V 12V 47V 45V 3 3V DS5 LED U6F 74ACT14 R92 R93 R94 R95 R96 R97 R98 R99 2 RN 1 R112 12 13 47 47 47
34. 47 47 47 47 47 930 R113 DS6 LED 74ACT14 USA 2 FN 1 Bits So 1 TOK DS7 LED U8B 74ACT14 74ACT14 V 74HC123 A LRE RE a BASIS Watchdog timer circuit block 330 S DS10 LED 74ACT14 USE oe LED 74ACT14 U9A Power supply connector 2 1 R120 2 1 T W330 DS13 LED U9B 74ACT14 2_RN 1 R121 to 3 E L 330 pei LED 74ACT14 U9C 2 1 R122 6 5 V vago DS15 LED U9D 74ACT14 2 KM 1 R123 84 9 330 DS16 LED 74ACT14 T7 LED output block Application Note U14868EJ2VOAN 41 CHAPTER 4 CONTROL SYSTEM 4 1 Overview 4 1 4 Control principles Typically when controlling a 3 phase motor voltage and current are indicated as 3 phase AC However 2 phase AC is easier to represent than 3 phase AC Also control is even simpler when representing biaxial DC rather than 2 phase AC When converting biaxial DC d q axes numerous armature coils are connected to the commutator and wound in the radial direction similar to a DC motor such as is shown in part c of Figure 4 1 below Two voltage values vd d axis voltage and vq q axis voltage are applied and two currents id d axis current and iq q axis current flow across the brush that is situated along the d q axis which rotates at the same speed as the electromagnetic field In the application circuit example the current and voltage are controlled along the d q axis in the same way as in DC motors Figure 4 1 Equivalent Circuits 1 3 a Equivalent circuit of 3 phase b Equivalent cir
35. 5 AD5 PDL6 AD6 PDL7 AD7 PDL8 AD8 PDL9 AD9 O PDL10 AD10 NTP20 P20 NTP21 P21 NTP22 P22 NTP23 P23 NTP24 P24 NTP25 P25 TOS INTP31 P27 TI2 SCK1 ASCK1 P34 O TO21 TO22 TO23 TO24 TCLR2 TIS INTPSO TCLRS3 P26 O Application Note U14868EJ2VOAN PDL15 AD15 PDL14 AD14 PDL13 AD13 PDL12 AD12 PDL11 AD11 CHAPTER 1 INTRODUCTION 1 3 3 Internal block diagram MEMC wu a queue INTP2 INTP3 ve Re INTPO ESOO 32 bit INTP4 TO3OFF INTP1 ESO1 barrel l Multiplier INTP20 TI2 shifter 32x 325 64 INTP21 TO21 to INTP24 TO24 Be a INTP25 TCLR2 TMOO TMO1 INTP30 TI3 TCLR3 etre gt i A16 to A21 General 3 Ti 2 INTP100 TCUD10 Tm oo C p 22 btts x 32 INTP101 TCLR10 Timer 3 TM3 TO000 to TO00S M a T0010 to T0015 ST E TM TIUD10 TO10 RPU System registers C ADO to AD15 CKSEL RXDO CLKOUT SO1 TXD1 SH RXD1 SCK1 ASCK1 MODE1 VPPNote 2 RESET controller VDD Vss Vss3 PCT4 PCT6 PCM0 PCM1 lt gt P40 to P42 lt gt PDHO to PDH5 lt gt PCT0 PCT1 PDLO to PDL15 lt gt Notes 1 PD703114 128 KB mask ROM uPD70F3114 128 KB flash memory 2 uPD70F3114 only Application Note U14868EJ2VOAN 23 CHAPTER 2 FUNCTIONS IN APPLICATION CIRCUIT EXAMPLE This chapter describes a 3 phase servo motor control application circuit which features vector operation based on P
36. 9 PWM output enable register O 68 PWM software timing output register O 64 PWM timer function i 51 R Register settings Timer 00 61 Register settings Timer 10 77 S 89 SE O TEES 81 EE 1 E t a 89 Signal edge selection register 10 81 sin calculation processing 107 EC Oe ee 61 Speed eels 46 48 Speed specification volume value input 39 SPEED MAX ase ee ne 89 STOPODeraloN ne oe eei d 25 SIOD Nas ee 87 SIOP FOG eerror 86 Subroutine processing for sin calculation 108 System configuration pp 26 T Three phase voltage conversion 49 Timer 0 clock selection register 61 inse Mm 51 53 Timer 1 timer 2 clock selection register 77 Timer 10 HEP 13 74 Timer 10 noise elimination time selection FeClStO TTT 78 Timer control register OO pp 69 Timer control register 10 83 Timer output mode register O 62 Timer unit control register OO 72 Timer unit mode register O 79 TOO EUER 51 53 EMIO iouis tette qvae Dto E e euo ent ds 73 74 NI se r 69 iue m he 83 TOMR write enable register 0
37. AN 101 CHAPTER 7 FLOW CHARTS Figure 7 2 Motor Control Interrupt Servicing 0 4 ms Interval 5 5 Origin detection rotation processing Set to 1 initial flag Yes Set target position 10 as target position Set to 1 voltage values for d and q axes Target position 2 turns No Yes Set to 1 the stop flag PWM output off Calculate voltage values of U V and W phases PWM conversion output processing Drive error PWM output off Set error flag to ERR NO3 drive error Watchdog timer pulse output Set U V and W phases to PWM register Read volume value A D result EXIT u u SS u xer 102 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS 7 3 Wait Timer Interrupt Servicing 10 ms Interval Figure 7 3 illustrates the flow of wait timer interrupts 10 ms interval Figure 7 3 Wait Timer Interrupt Servicing 10 ms Interval int_cc30 See 8 5 Wait Timer Interrupt Servicing 10 ms Interval Is detection time 0 Detection time 1 Application Note U14868EJ2VOAN 103 CHAPTER 7 FLOW CHARTS 7 4 Peripheral I O Initialization Processing Figure 7 4 illustrates the flow of peripheral I O initialization processing Figure 7 4 Peripheral I O Initialization Processing See 8 6 Peripheral I O Initialization Processing TIUD10 TCUD10 TCLR10 Encoder input mE P20 to P27 P30 to P37 LED output Initialize port mode P40 P41 Opera
38. B ALVVB ALVWB TOSP 0 TOEDG1 TOEDGO FFFFF57DH 00H 7 ALVTO Specifies the active level of the TO000 TO002 and TO004 pins 0 Active level is low level 1 Active level is high level Caution Changing the ALVTO bit during TMOO operation TMOCEO 1 is prohibited ALVUB Specifies the active level of the TOO01 pin 0 Inverted level of active level set by ALVTO bit 1 Active level set by ALVTO bit When the ALVUB bit is 1 the TO001 output active level is the same level as TOOOO Caution Changing the ALVUB bit during TMOO operation TMOCEO 1 is prohibited 5 ALVVB Specifies the active level of the TOO03 pin 0 Inverted level of active level set by ALVTO bit 1 Active level set by ALVTO bit When the ALVVB bit is 1 the TO003 output active level is the same level as TOOO2 Caution Changing the ALVVB bit during TMOO operation TMOCEO 1 is prohibited 4 ALVWB Specifies the active level of the TO005 pin 0 Inverted level of active level set by ALVTO bit 1 Active level set by ALVTO bit When the ALVWB bit is 1 the TO005 output active level is the same level as TO004 Caution Changing the ALVWB bit during TMOO operation TMOCEO 1 is prohibited 3 TOSP Controls TOOO0 to TOOO05 pin output stop through ESOO pin input 0 Enables ESOO pin input 1 Disables ESOO pin input Cautions 1 The output stop status can be released by writing 1 to the TORSO bit of the TUCOO register The operation continues even if output is prohibited for
39. D703116 256 KB mask ROM 10 KB 256 KB flash memory O Interrupts exceptions External interrupts 20 including NMI Internal interrupts 45 sources Exceptions 1 source 8 levels of priority can be specified O Memory access control SRAM controller O DMA controller 4 channel configuration Transfer unit 8 bits 16 bits Maximum transfer count 65 536 2 Transfer type 2 cycle transfer Transfer modes Single transfer single step transfer block transfer Transfer subjects Memory lt Memory Memory o I O I O e I O Transfer requests On chip peripheral I O software Next address setting function O I O lines Input ports 8 I O ports 75 O Real time pulse unit 16 bit timer for 3 phase sine wave PWM inverter control 2 channels 16 bit up down counter timer for 2 phase encoder input 2 channels General purpose 16 bit timer counter 2 channels General purpose 16 bit timer event counter 1 channel 16 bit interval timer 1 channel 16 Application Note U14868EJ2VOAN CHAPTER 1 INTRODUCTION O Serial interface SIO Asynchronous serial interface UART 3 channels Clocked serial interface CSI 2 channels FCAN Full Controller Area Network 1 channel O NBD Non Break Debug function 1 channel UPD70F3116 only RAM monitoring Event detection O A D converter 10 bit resolution A D converter 8 channels x 2 units O Clock generator Multiplication function x1 x2 5 x5 x10 using PLL clock synthesizer Divide by 2 function using external cl
40. DO RXDO TXD1 RXD1 ASCK1 CVpp CVss lt 4 MODEO to MODE2 RESET V DDS Vss5 Vpps SS3 V ppNote 4 CLK_DBG SYNC we Note 2 ADO DBG to AD3 DBG lt NBD K gt TRIG_DBG controller PDLO to PDL15 PDHO to PDH7 PCSO to PCS7 PCTO to PCT7 Notes 1 PD703116 256 KB mask ROM uPD70F3116 256 KB flash memory Incorporated in u PD70F3116 only As follows in the PD703116 TRIG_DBG IC1 ADO DBG to AD3 DBG IC2 SYNC IC3 CLK DBG IC4 UuPD70F3116 only UuPD70F3116 only In the uPD703116 the Ver pin is assigned as the IC5 pin Application Note U14868EJ2VOAN 19 CHAPTER 1 INTRODUCTION 1 3 V850E IA2 1 3 1 Features Number of instructions 83 O Minimum instruction execution time 25 ns internal 40 MHz operation General purpose registers 32 bits x 32 registers Instruction set V850E1 CPU Signed multiplication 32 bits x 32 bits 64 bits 1 or 2 clocks Saturated operation instructions with overflow underflow detection function 32 bit shift instruction 1 clock Bit manipulation instructions Long short format load store instructions Signed load instructions O Memory space 4 MB linear address space shared by program and data Memory block division function 2 MB block Programmable wait function Idle state insertion function O External bus interface 16 bit data bus address data multiplexed 16 8 bit bus sizing function External wait function Part Number Internal ROM
41. E AZ RINASSION Ne a 33 LiSt OF Peripheral rrie iel T 36 Motor Specifications nt 47 Timer d ENO Gs eke Vag eT Teen 74 COMMON Area LIS 86 List of Constants SRM 88 SONGOIORCONUTGLOTRS eo vasalaannnadmaudsandaandanadaandaantuanseanteancaananauts 90 Application Note U14868EJ2VOAN CHAPTER 1 INTRODUCTION The V850E IA1 and V850E IA2 are products in NEC s V850 Series of single chip microcontrollers for real time control 1 1 Outline The V850E IA1 and V850E IA2 are 32 bit single chip microcontrollers that realize high precision inverter control of motors due to high speed operation They use the V850E1 CPU of the V850 Series and have on chip ROM RAM a bus interface DMA controller a variety of timers including a 3 phase sine wave PWM timer for motors serial interfaces and peripheral functions such as A D converters SRAM or ROM can be connected as memory The V850E IA1 has an FCAN Full Controller Area Network controller peripheral function Table 1 1 lists the differences between the V850E IA1 and V850E 1A2 Table 1 1 Differences Between V850E IA1 and V850E IA2 Maximum operating frequency Timers 00 01 Provided Buffer register compare register and compare match interrupt added Timers 10 11 Provided Timer 10 Provided Timer 11 Not provided Timers 20 21 Provided Provided Timer 3 Provided TOS output buffer off function by INTP4 input added Provided pins shared with CSI1 Provided Not provided Debug support NBD Pro
42. FFFA DOT 46k AGND an lt EEEEEEEZ 0 Reset circuit 2222222 Q GZ ZZ iV GOUOOO DC C 0 0 m m uu rm LT og FE P1 R31 47 es SAD za BE AVDD TCLR10 INTP101 P12 O E S S D ras 5MHz ANI10 PCM4 ww R3447 Y O 103 P103 R35 47 CN 3P C4 R36 47 p7 7 ANI11 HLDRQ PCMS 102 P102 H37 47 0 1u film Wea 47 pa g ANI12 HLDAK PCM2 H101 P101 W S Motor encoder WW ae ANI13 CLKOUT PCM1 ANV c5 R40 47 P ANA WATPCMO 190 100 R41 47 33p Ww Pr 10 ANI5 E 99 P99 R43 47 R44 47 L Pii A ASTB PCT6 29 P98 R45 47 Oscillator AAAvvR4747 Ele 12 ANI17 PCT5 ar Ear E 2 ERE E TRIG_DEG RD PCT4 3 AWW P14 14 AD3 DBG BITS P95 R51 47 ww Rs247 Bi5 d5 Ap2 DBG PeT 94 P94 R53 47 HPS 5 AS 412 V Was44 Pt 18 51 pec Gwaper es Po3 R55 47 AN Rear Pi a7 Api bBG MaS cro 92 P92 R57 47 AGND R58 47 5 SN TE BE Si O i N ANN 1 512 18 1 ctk pea VSS5 22 90 4 EE p21 21 RESET 9 88 Pss R61 47 4 CKSEL R62 47 B22 22 cvsS mE EEC 87 P87 R63 47 5V v BOB 29 CS6 86 P86 R64 47 C6 R65 P24 24 X1 CS5 PSC5 85 P85 R66 47 Driver 7 0 1u film WW 4 R67 P25 25 2 84FSC4 84 Pea VVRGB 47 AGND 12V R71 LM324 NVV CKSEL CS3 PSC3 AWW to b tb R69 47 P26 26 MODE0 Gas peco B8 P83 R70 47 to be set by user uc pa NODE CSUPSC er pa R74 47 le 10 R L 80 P80 A R75 47 MODE EE Ii E 62 Rd E e 5V H p31 31 SRDE T A22 PDH6 e pvp STR 35 ok SCKO P42 A21 PDH5 R80 47 Hea e 3 SI1 P
43. H2 CRXD P46 O O A ERRI CTXD P47 16 PDHO Vpp3 O Vss3 O Vss5 O VDD5 O ADO PDLO O 3 4 5 RXDO P30 O TXDO P31 O RXD1 P32 O TXD1 P33 O ASCK1 P34 O RXD2 P35 O TXD2 P36 O ASCK2 P37 O NTP20 P20 O NTP21 P21 O NTP22 P22 O NTP23 P23 O NTP24 P24 O NTP25 P25 O AD1 PDL1 O AD2 PDL2 O AD3 PDL3 O AD4 PDL4 O AD5 PDL5 O AD6 PDL6 O AD11 PDL11 O AD12 PDL12 AD13 PDL1 AD14 PDL1 AD15 PDL1 TO3 INTP31 P27 O TI2 TO21 TO22 TO23 TO24 TCLR2 TIS INTPSO TCLR3 P26 O Notes 1 On chip in uPD70F3116 only As follows in the uPD703116 TRIG_DBG IC1 ADO DBG to AD3 DBG IC2 SYNC IC3 CLK DBG IC4 2 uPD703116 IC5 uPD70F3116 VPP Cautions 1 When using the wPD70F3116 in normal mode connect the Vpp pin to Vsss 2 When using the PD703116 the processing when pins IC1 to IC5 are not used is as follows Pins IC1 to IC4 Leave open Pin IC5 Independently connect to Vsss via a resistor 18 Application Note U14868EJ2VOAN CHAPTER 1 INTRODUCTION 1 2 3 Internal block diagram INTP20 to INTP25 HLDRQ INTP30 INTP31 mm OLDAR INTP100 INTP101 gt C80 to CS7 barrel NH INTP110 INTP111 RPU shifter AS ESO0 ESO1 TMo 2ch TO000 to TO005 lt 4 TMn 2ch prec UWA TOO010 to TOO15 TM2 2ch TIUD10 TO10 lt gt TM3 tch gt A16 to A23 TM4 1ch TCUD10 TCLR10 General lt Z gt ADO to AD15 TIUD11 TO11 purpose TCUD11 TCLR1 1 lt __ A registers TI2 TCLR2 TO21 to TO24 i TIS TCLR3 TO3 TX
44. Internal RAM O Internal memory uPD703114 128 KB mask ROM uPD70F3114 128 KB flash memory O Interrupts exceptions External interrupts 16 including NMI Internal interrupts 42 sources Exceptions 1 source 8 levels of priority can be specified Memory access control SRAM controller O DMA controller 4 channel configuration Transfer unit 8 bits 16 bits Maximum transfer count 65 536 25 Transfer type 2 cycle transfer Transfer modes oingle transfer single step transfer block transfer Transfer subjects Memory lt Memory Memory o I O MO e I O Transfer requests On chip peripheral I O software Next address setting function O VO lines Input ports 6 IO ports 47 O Real time pulse unit 16 bit timer for 3 phase sine wave PWM inverter control 2 channels 16 bit up down counter timer for 2 phase encoder input 1 channel General purpose 16 bit timer counter 2 channels General purpose 16 bit timer event counter 1 channel 16 bit interval timer 1 channel O Serial interface SIO Asynchronous serial interface UART 2 channels 20 Application Note U14868EJ2VOAN O O A D converter Regulator Clock generator Power saving function Package CMOS technology CHAPTER 1 INTRODUCTION Clocked serial interface CSI 2 channels Of the four channels two channels are used for both CSI and UART and therefore one or the other function must be selected 10 bit resolution A D converter 6 channels 8 channels 2 units
45. OF V850E IA1 AND V850E IA2 5 2 3 Register settings 1 Timer 1 timer 2 clock selection register PRMO02 settings In this application circuit example the PRMO2 register is set as follows clk fxx 4 In the case of the V850E IA2 the PRMO 2 register is set as shown below fclk fxx 2 Figure 5 16 Timer 1 Timer 2 Clock Selection Register PRMO02 Address After reset 7 6 5 4 3 2 1 0 PRM2 Specifies the base clock Tous of timer 1 TM10 and timer 2 TM20 0 fxx 4 when fxx gt 32 MHz 1 fxx 2 when fxx lt 32 MHz Note This is for the V850E IA1 It is 40 MHz for the V850E lA2 Remark fx Internal system clock Application Note U14868EJ2VOAN 77 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 2 Timer 10 noise elimination time selection register NRC10 settings In this application circuit example the NRC10 register is set as follows NRC10 0x03 noise elimination clock selection Figure 5 17 Timer 10 Noise Elimination Time Selection Register NRC10 Address After reset 7 6 5 4 3 2 1 0 NRc1o 5 o o o o o 0 NRC101 NRC100 FFFFFSFBH 00H 1 0 NRC101 Selects the TIUD10 TO10 TCUD10 INTP100 and TCLR10 INTP101 pin noise NRC100 elimination clocks s o9 ms o o ma a o9 mm O Remark fci Base clock 78 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 3 Timer unit mode register 0 TUMO settings In this ap
46. OO 1 software output enabled to TMOCEOO 1 timer operation enabled TORTOO 0 software output disabled the TOOO0 to TOOO5 pins continue to perform software output until the occurrence of the first F F set reset due to a match between TMOn and the compare register after the TORTOO bit setting changes The relationship between the settings of the TORTOO and TMOCEn bits when ALVTO 1 and the output of TOO00 negative phase side is shown on the following pages the positive phase side TO001 TOO03 and TO005 is dependent on the ALVUB ALVVB and ALVWB bits so refer to the explanations of each of these bits Application Note U14868EJ2VOAN 65 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 5 Buffer registers CMOO to CM03 BFCMOO to BFCMO3 settings In this application circuit example the BFCMOO to BFCMO3 registers are set as shown below BFCMOO Initial value 50 duty BFCMO1 Initial value 5096 duty BFCM02 Initial value 50 duty BFCMO3 20 kHz BFCMOO nitial value 50 duty BFCMO1 nitial value 50 duty BFCM02 nitial value 50 duty BFCM03 20 kHz The transfer operation from the BFCMOO to BFCMO3 registers to the CMOO to CMO3 registers is performed during the operation of TMOO TMOCEO bit of TMCOO register 1 so it is performed when an underflow interrupt INTTMOO occurs Figure 5 9 Buffer Registers CM00 to CM03 BFCMOO0 to BFCM03 15 14 13 12 11 10 9 8 7 6 5 4 3
47. ORSO bit After reset be sure to write 1 to the TORSO bit prior to starting TO000 to TO005 pin output A 0 is read when the TORSO bit is read TOSTAO TOO000 to TO005 pin output status flag through ESOO pin input 0 Output enabled status 1 Output disabled status 72 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 5 2 Encoder Counter Functions Timer 10 TM10 The V850E IA1 includes a 2 channel 1 channel for the V850E IA2 16 bit up down counter that can be used as a In this application circuit example timer 10 TM10 uses one of 2 phase encoder input or general purpose timer these channels as a timer for 2 phase encoder input The following settings are made in the application circuit example e UDC mode A Counter is cleared at the falling edge of TCLR10 Uses x4 frequency multiplication mode 4 5 2 4 General This section shows block diagrams and provides general descriptions of registers Figure 5 14 Block Diagram of Timer 10 TM10 Lj bus Edge detector Edge r detector detector INTP101 9 TCUD10 Edge INTP 1 009 fxx 2 ee 1 2 1 4 1 8 1 16 1 32 1 64 1 128 External clock SELCLK fxx 4Note 2 ee fcrk e Lwe y TM1UBDO CMD CM101 ELE m Internal bus TCLR TM10 Clear Clear controller ww om Output control ENMD MSEL ALV
48. Processing beyond the Z phase is performed by software with 32 bit position control see 7 2 Motor Control Interrupt Servicing 0 4 ms Interval 50 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 This chapter describes the use of the timer that is used for PWM output and encoder input 5 1 PWM Timer Function Timer 00 TMOO The V850E IA1 and V850E IA2 include a 2 channel 3 phase PWM output function that uses an optimum dead time for motor control applications This function can be used to control two motors at the same time It features three waveform modes as comparative waveforms for PWM generation e PWM mode 0 Symmetrical triangular waves e PWM mode 1 Asymmetrical triangular waves e PWM mode 2 Saw tooth waves In this application circuit example timer 00 TMOO is used on one channel in PWM mode 0 symmetrical triangular waves Only one motor is used in this case Application Note U14868EJ2VOAN 51 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 5 1 1 General This section shows a block diagram of each mode and provides general descriptions of registers Figure 5 1 Block Diagram of Timer 00 TMOO PWM Mode 0 Symmetric Triangular Wave INTCMOO3 fxx fxx 2 INTTMOO gt 1 Output control by 6 external input ESOO 1 TMOO timer operation i Selector Underflow TO000 U phase TO002 V phase TO003 OV phas
49. T10 INTP100 INTCC100 INTP101Nete 1 INTCC101 TM1OVFO TM1UDFO TO10 INTCM100 INTCM101 Notes 1 The INT101 interrupt is the signal of the interrupt from the INTP101 pin or the interrupt from the INTP100 pin selected by the CSLO bit of the CSL10 register 2 V850E IA1 only Remarks 1 fxx Internal system clock 2 fcuc Base clock V850E IA1 16 MHz MAX V850E IA2 20 MHz MAX Application Note U14868EJ2VOAN 73 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 1 Timer 10 TM10 TM10 functions as a 2 phase encoder input up down counter and general purpose timer Cautions 1 Writing to TM10 is enabled only when the TM1CEO bit of the TMC10 register is 0 count operation disabled 2 lt is prohibited to set the CMD bit general purpose timer mode and the MSEL bit UDC mode B of the TUMO register to 0 and 1 respectively 3 Continuous reading of TM10 is prohibited If TM10 is continuously read the second read value may differ from the actual value If TM10 must be read twice be sure to read another register between the first and the second read operation Correct usage example Incorrect usage example TM10 read TM10 read TM11 read TM10 read TM10 read TM11 read TM11 read TM11 read TM10 start and stop is controlled by the TM1CEO bit of timer control register 10 TMC10 The TM10 operation consists of two modes the general purpose timer mode and the up down counter mode UDC mode The
50. TER 5 Addition of cautions to Timer Unit Control Register 00 TUC00 V850E IA1 V850E IA2 FUNCTIONS Modification of setting values in Timer 1 timer 2 clock selection register PRM02 settings Modification of Block Diagram of Timer 10 TM10 Modification of the description on Signal Edge Selection Register 10 SESA 10 Addition of cautions to Timer Control Register 10 TMC10 CHAPTER 6 Modification of values in List of Constants PROGRAM CONFIGURATION 122 Application Note U14868EJ2VOAN From Name Company Tel FAX Message NEC Although NEC has taken all possible steps to ensure that the documentation supplied to our customers is complete bug free and up to date we readily accept that errors may occur Despite all the care and precautions we ve taken you may encounter problems in the documentation Please complete this form whenever you d like to report errors or suggest improvements to us Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Market Communication Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 455 11 6462 6829 Hong Kong Philippines Oceania NEC Electronics Hong Kong Ltd Fax 852 2886 9022 9044 Korea NEC Electronics Hong Kong Ltd Seoul Branch Fax 82 2 528 4411 P R China NEC Electronics Shanghai Ltd Fax 86 21 6841 1137 Thank
51. To our customers Old Company Name in Catalogs and Other Documents On April 1 5 2010 NEC Electronics Corporation merged with Renesas Technology Corporation and Renesas Electronics Corporation took over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electronics website http www renesas com April 1 2010 Renesas Electronics Corporation Issued by Renesas Electronics Corporation http www renesas com Send any inquiries to http www renesas com inquiry 24 NE S AS 8 10 11 12 Notice All information included in this document is current as of the date this document is issued Such information however is subject to change without any prior notice Before purchasing or using any Renesas Electronics products listed herein please confirm the latest product information with a Renesas Electronics sales office Also please pay regular and careful attention to additional and different information to be disclosed by Renesas Electronics such as that disclosed through our website Renesas Electronics does not assume any liability for infringement of patents copyrights or other intellectual property rights of third parties by or arising from the use of Renesas Electronics products or technical information described in this document No license express implied or otherwise
52. WM duty is explained next Setting of data to CM000 to CMOO2 consists in setting the duty output from BFCMOO to BFCMO2 The values of BFCMOO to BFCMO2 are automatically transferred by hardware to CMOOO to CMOO2 upon generation of the INTTMOO interrupt Furthermore software processing is started up and calculation performed and set reset timing of the F F for the next cycle is set to BFCMOO to BFCMO2 The PWM cycle and the PWM duty are set in the above procedure The F F set reset conditions upon match of CMOOO to CMOO are as follows e Set CMO000 to CM002 match detection during TMOO up count operation e Reset CM000 to CM002 match detection during TMOO down count operation In this mode the F F set reset timing is performed in the same timing right left symmetric control The values of DTRRO are transferred to the corresponding dead time timers DTMOO to DTMO2 in synchronization with the set reset timing of the F F and down counting is started DTMOO to DTMO2 count down to 000H and stop when they count down further to FFFH DTMOO to DTMO2 can automatically generate a width dead time at which the active levels of the positive phase TO000 TO002 TO004 and negative phase TOOO1 TO003 TO005 do not overlap In this way software processing is started by an interrupt INTTMOO that occurs once during every PWM cycle after initial setting has been performed and by setting the PWM cycle and PWM duty to be used in the next cycle it is pos
53. WM output encoder input and A D converter input as an application example of the timer counter function real time pulse unit of the V850E IA1 and V850E IA2 The main functions of this application circuit are listed below e Performs clockwise rotation counter clockwise rotation and STOP operation Enables rotation speed to be changed using speed volume e An array of 16 LEDs displays rotation speeds and positional differences e Errors such as overcurrent are monitored and indicated via LED display 24 Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION This chapter describes the hardware configuration of the application circuit example 3 1 Operation The application circuit s main functions are described below In this example when the power is turned on the application circuit detects the origin position by activating the motor for two rotations After that the motor s operation mode is controlled via the operation switches 1 Clockwise or counter clockwise rotation e The rotor s rotation speed rpm varies as indicated by the speed volume indicator e The rotation speed ranges from 15 to 1 500 rpm e When the rotor is turning the LED display shows the differential compared to the specified rpm e When the operation mode has been changed the rotor stops turning waits for 10 ms then is restarted according to the newly set operation mode see Figure 6 1 Program Structure 2 STOP operation e The rotor is kep
54. YSTEM 4 2 Position Control The following equation expresses the conversion from position to speed Oo speed kp x o position now position Remark o speed Target speed kp Position proportional gain O position Target position now position Current position 4 3 Speed Control In the application circuit example PI Proportion Integral control is used in the speed control block The equations used for speed control are shown below d speed o speed now speed Oo iqp kspxd speed o iqdi n 0 iqi n 1 ksi x d speed n 1 oO iq 0 iqp o iqi n Remark d speed Differential between target speed and current speed O speed Target speed now speed Current speed O iqp Speed proportional component current value ksp Speed proportional gain O idi Speed integral component current value ksi Speed integral gain O iq Target current value n Current component n 1 Previous component 48 Application Note U14868EJ2VOAN CHAPTER 4 CONTROL SYSTEM 4 4 Current Control For current control the d axis current id and q axis current iq are converted via the following equations to obtain a target voltage for each axis o vd ki x id o vq kix o iq iq Remark o vd Target d axis voltage Current proportional gain d axis current value Target q axis voltage Target q axis current value q axis current value id and iq are obtained by converting current values for the u and v phases to d q ax
55. a s initialization processing see Figure 7 5 Common Area s Initialization Processing Interrupt enabled Initializing rotation end E Dummy rotation to detect origin Yes Wait for detection of origin Interrupt prohibited ainit Common area s initialization processing see Figure 7 5 Common Area s Initialization Processing Clear to 0 initial flag Active output of all phases U V and W phases Set current processing No as 0 Interrupt enabled Application Note U14868EJ2VOAN 91 CHAPTER 7 FLOW CHARTS Figure 7 1 Main Routine 2 6 A Read switches Is operation mode switch set to clockwise rotation S operation mode switch set to counter clockwise rotation No Set operation mode to stop Set operation mode to Set operation mode counter clockwise rotation to clockwise rotation Decide processing No Store in SPEED area 92 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS Figure 7 1 Main Routine 3 6 B Stop processing Processing No 0 Is operation mode set to clockwise rotation Is operation mode set to counter clockwise rotation Yes Interrupt prohibited Interrupt prohibited Clear to 0 stop flag Clear to 0 stop flag Set target speed Set target speed Set to SPEED Set control mode to speed control Set control mode to speed control Interrupt enabled Interrupt enabled Set processing No 2 counter clockwise Position differential is displ
56. al en Espa a Fax 01908 670 290 Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 e Succursale Francaise V lizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 Application Note U14868EJ2VOAN NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seoul Branch Seoul Korea Tel 02 528 0303 Fax 02 528 4411 NEC Electronics Shanghai Ltd Shanghai P R China Tel 021 6841 1138 Fax 021 6841 1137 NEC Electronics Taiwan Ltd Taipei Taiwan Tel 02 2719 2377 Fax 02 2719 5951 NEC Electronics Singapore Pte Ltd Novena Square Singapore Tel 253 8311 Fax 250 3583 J02 4 Major Revisions in This Edition Throughout e For V850E IA1 the following product has been deleted uPD703117 e For V850E IAT the following products have been added uPD703116 uPD703116 A uPD703116 A1 uPD70F3116 uPD70F3116 A uPD70F3116 A1 e The following products V850E IA2 have been added uPD703114 uPD70F3114 e The status of the following product has changed from under development to development complete uPD70F3116 e Bits defined as reserved words in the device file have been specified bits whose bit numbers are in angle brackets lt gt Modification of setting values for the PRM02 register in 5 2 3 1 Timer 1 timer 2 clock selection register PRM02 settings Modification of description on Figure 5 20 Signal Edge Selection Register 10 SESA 10
57. all timers and counters Before changing the ESOO pin input status from disable to enable changing TOSP bit from 1 to 0 write 1 to the TORSO bit of the TUCO register to reset the ESOO pin input status 62 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Figure 5 7 Timer Output Mode Register 0 TOMRO 2 2 TOEDG1 These bits select the valid edge or level when setting forcible stop of TO000 to TOOOS TOEDGO output through ESOO pin input with the TOSP bit a o9 eem Cautions 1 Changing the TOEDG1 and TOEDGO bits during TMOO operation TMOCEO 1 is prohibited 2 Before changing the settings of the TOEDG1 and TOEDGO bits write 1 to the TORSO bit of the TUCOO register to reset the ESOO pin input status Data setting to timer output mode register 0 TOMRO is done in the following sequence 1 Prepare the data to be set to timer output mode register 0 TOMRO in a general purpose register 2 Write data to TOMR write enable register 0 SEPCO 3 Set timer output mode register 0 TOMRO performed with the following instructions e Store instruction ST SST instructions e Bit manipulation instruction SET1 CLR1 NOT1 instructions Description Example 1 Mov 0x04 310 2 ST B r10 SPECO r0 lt 3 gt ST B r10 TOMRO r0 To read the TOMRO register no special sequence is required Cautions 1 Prohibit interrupts between SPECO issuance 2 and TOMRO register write t
58. as during normal timer operation 1 VPORTO Specifies the TO002 V phase TO003 VPORTO Operation Inverted level of ALVTO bit setting Level of ALVTO bit setting Caution f the VPORTO bit setting value is changed when TORTOO 1 the dead time setting becomes valid for the TO002 TO003 output signal in the same way as during normal timer operation Remark ALVTO bit Bit 7 of the TOMRO register ALVUB bit Bit 6 of the TOMRO register ALVVB bit Bit 5 of the TOMRO register 64 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Figure 5 8 PWM Software Timing Output Register 0 PSTOO 2 2 Bit Position Function WPORTO Specifies the TO004 W phase TO005 W phase pin output value Inverted level of ALVTO bit setting Inverted level of ALVTO bit setting Inverted level of ALVTO bit setting TOO005 Inverted level of ALVTO bit setting Caution If the WPORTO bit setting value is changed when TORTOO 1 the dead time setting becomes valid for the TO004 TOO005 output signal in the same way as during normal timer operation Remark n 0 1 ALVTO bit Bit 7 of the TOMRO register ALVWEB bit Bit 4 of the TOMRO register The TOOO0 to TOOO5 pins can be set to timer output by a match between TMOO and the compare register or to software output using the PSTOO register TORTOO bit 2 1 Software output has priority over timer output Consequently when the setting changes from TMOCEO 1 timer operation enabled TORT
59. ayed as LED output led out see Figure 7 6 LED Display Output Processing Set processing No 1 clockwise Application Note U14868EJ2VOAN 93 CHAPTER 7 FLOW CHARTS Figure 7 1 Main Routine 4 6 Clockwise rotation processing processing No 1 Reset target speed Is op ranon mode set to counter clockwise rotation or stop Yes Set target speed to 0 Set to 1 the stop request flag No Set processing No 3 during deceleration led out Speed differential is displayed as LED output 9 see Figure 7 6 LED Display Output Processing Gg Counter clockwise rotation processing processing No 2 Reset target speed Is operat on mode to clock WISG rotation or stop No Yes Set target speed to 0 Set to 1 the stop request flag Set processing No 3 during deceleration led out Speed differential is displayed as LED output S see Figure 7 6 LED Display Output Processing 94 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS Figure 7 1 Main Routine 5 6 O Processing during deceleration processing No 3 Set to 1 stop flag Yes Set detection time Set processing No 4 wait for detection Speed differential is displayed as LED output see Figure 7 6 LED Display Output Processing Q Detection wait processing processing No 4 Is detection time 0 No Yes Interrupt prohibited Set control mode to position control Clear t
60. ck ck KK k k RK ck kck KK KKK case 2 o speed speed Sets target speed if sw mode CW sw mode STOP o speed 0 Clears to 0 target speed stop req ON Sets to 1 stop request flag proc no 3 4 Sets processing No during deceleration j led out abs o speed aba now speed break Processing during deceleration KK RK KK kk KKK k ke k KK RK k ke KK k k KK RK KR KK RR KK KKK KK ke ke ke ke e ke KKK C 3 if stop flag ON timer count 10 Sets detect time as 100 ms proe no e 4 Sets detection wait processing No j led out abs o speed aba now speed break Detection wait processing kokckckckckckckck ck ckckckckckckckckck ck ckckckckckckck ckck ck ckckckckckckck ckck ckckckck ck kckck KK RK KK KK KK kk Case 4 if timer count 0 DE 4 cont mode POSITION Sets position control mode stop req OFF Clears to 0 stop request flag stop flag OFF Clears to 0 stop flag proc no T Sets stop processing No O position now position BLA g j led out abs o speed abs now speed break j Error processing FR RR RRR I KAAKA ke ke e ke e ke if error flag 4 while 1 led out 0x0000 tiner cownt BO 3 while timer count led out error flag timer count 50 3j while timer count 112 Application Note U14868EJ2VOAN CHAPTER 8 PROGRAM LISTS 8 4 Motor Control Interrupt Servici
61. ckwise or counter clockwise operation mode Indicates pulse count changed by 0 4 ms interrupt speed differential 36 Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION Figure 3 5 LED Display V850E IA1 LED LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 7 6 5 4 3 2 1 0 P3 LED LED16 LED15 LED14 LED13 LED12 LED 11 LED10 LED9 Figure 3 6 LED Display V850E IA2 14 13 12 11 PDL LED LED16LED15 LED14 LED13 LED12 LED11LED10 LED9 LED8 LED7 LED6 LED5 LED4 LED3 LED2 LED1 b Operating mode switch input watchdog timer output drive error input These I O use port 4 in the V850E IA1 and port 3 in the V850E IA2 The function of each of the bits of port 4 or port 3 is shown below Figure 3 7 Functions of Port 4 V850E IA1 Operation mode switch input Watchdog timer output Drive error input Application Note U14868EJ2VOAN 37 CHAPTER 3 HARDWARE CONFIGURATION Figure 3 8 Functions of Port 3 V850E IA2 Operation mode switch input Watchdog timer output Drive error input e P41 and P40 V850E IA1 or P31 P30 V850E IA2 Operation mode switch input Bit 1 Pn1 and bit 0 PnO specify the operation mode 090 4 Clockwise rotation operation ala Counter clockwise rotation operation e P42 V850E IA1 or P32 V850E IA2 Watchdog timer output By setting bit 2 Pn2 pulses that are generated every 0 4 ms using timer 4 TM4 are output by software to
62. cuit using 2 phase AC synchronous motor Remark vu u phase voltage value 0 axis voltage value vv v phase voltage value Baxis voltage value vw w phase voltage value Angle of rotation 0r Angle of rotation N pole N N pole S pole o S pole Angular velocity wr Angular velocity Application Note U14868EJ2VOAN 43 CHAPTER 4 CONTROL SYSTEM Figure 4 1 Equivalent Circuits 2 3 c Equivalent circuit of biaxial DC type d Relationship between 3 phase and d q axes 2 phase AC coordinates Remark u u phase Remark v phase w phase Angle of rotation N pole S pole d axis id d axis current value d axis voltage value q axis iq q axis current value vq q axis voltage value 44 Application Note U14868EJ2VOAN Remark P d q CHAPTER 4 CONTROL SYSTEM Figure 4 1 Equivalent Circuits 3 3 e Relationship between 2 phase AC and biaxial DC coordinates 0 axis p axis d axis q axis Angle of rotation Application Note U14868EJ2VOAN 45 CHAPTER 4 CONTROL SYSTEM 4 1 2 Control block In the application circuit example processing of timer interrupts in 0 4 ms units is used to calculate control along the d q axis as is shown in Figure 4 2 and final output of the u v and w phase voltage values is performed by the PWM timer function timer 00 TMOO of V850E IA1 or V850E IA2 Figure 4 2 Control Block AD AD converter E Current controller Coordinate conv
63. e TO004 W phase TO005 Ow phase Remarks 1 TMOO Timer register CMO000 to CMOO3 Compare registers BFCMOO0 to BFCMO3 Buffer registers DTRRO Dead time timer reload register ALVUB Bit 6 of TOMRO register ALVVB Bit 5 of TOMRO register ALVWB Bit 4 of TOMRO register DIMOO to DIMO2 Dead time timers ALVTO Bit 7 of TOMRn register S R Set Reset 2 fxx Internal system clock 3 fcu Base clock 40 MHz MAX 52 Application Note U14868EJ2VOAN 1 2 3 4 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Timer 00 TMOO The TMOO register operates as a 16 bit up down timer or up timer The cycle is controlled by compare register 003 CMO003 TMOO register start stop is controlled by the TMOCEO bit of timer control register 00 TMCOO Division by the prescaler is set for the count clock of this application circuit example to fcLk with the PRMO 2 to PRMOO bits of the TMCOO register fcLk base clock see 5 1 3 1 Timer 00 clock selection register PRMO1 settings The conditions when the TMOO register becomes 0000H are as follows e Reset input e TMOCEO bit 0 e Immediately after overflow or underflow Dead time timers 00 to 02 DTMOO to DTMO2 The DTMOO to DTMO2 registers are dedicated 12 bit down timers that generate dead time suitable for inverter control applications DTMOO to DTMO2 operate as one shot timer Counting by a dead time timer is enabled or disabled by th
64. e 9167 gt gt SGETA o vd ki id gt gt KIGETA o vg ki o iq iq gt gt KIGETA if o vd gt VMAX o vd VMAX else if o vd lt VMAX oO vd VMAX j if o vq gt VMAX o vq VMAX else if o vq lt VMAX o vq VMAX Three phase voltage conversion processing kokckckckckckckck ck ck RR KR RR RR ckckckck ckckckckckck ck kckck ck ck RR KK ck k kk kk RK if init flag ON o_trm 10 tre o trm P MAXPULSE o vd 0 O vq 5 Lf 8G erm c 209000 4 Checks for completion of initial two rotations stop flag ON POERO 0 PWM output off j j GV amp cb UL ovd co sint tre 2500 9 Q wq ere tre J o k gt 5 SGETA o vy sO ov Sil bre p S467 To L vq sint tre 6667 VI JI s2 SETA O VW 2 90 O VE PWM conversion output processing KR RR RK KR KK RR KR KR KKK RR KR ck kckckckckckck ckck ck kckck ck ko kock kk KK if Pa amp 0xos 4 POERO 0 PWM output off error flag ERR NO3 Sets to 1 drive error j if error flag d P4 20 P4 0x04 Watchdog timer pulse output BFCMOO0 o vu BFCM DATA 2 BFCMOl o vv BFCM DATA 2 BFCMO2 o vw BFCM DATA 2 volume ADCRO1 Speed volume value input 114 Application Note U14868EJ2VOAN CHAPTER 8 PROGRAM LISTS 8 5 Wait Timer Interrupt Servicing 10 ms Interval J
65. e 1 Read SW eR A AR A I I I I I I I RI I I IAAI AAJ Sw P4 amp 0x03 if sw ss sw mode CW else if sw 2 sw mode CCW else sw mode STOP j speed SPEED MAX volume 1024 1 sSwiteht proc n 1 otop processing ek kk kk k k k k k k k k k k k k k k k k kk kk kk kk kk ok kok kkk e ke e ke v kx case 0 if sw mode CW 2 i DEC stop flag OFF Clears to 0 stop flag o speed speed Sets target speed cont mode SPEED Sets speed control mode NOUO proc noce d Sets clockwise processing No else if sw mode CCW pub 3 stop flag OFF Clears to 0 stop flag o speed speed Sets target speed cont mode SPEED Sets speed control mode 2 529 proe Ho 2 3 Sets counter clockwise processing No j led out o position now position break Application Note U14868EJ2VOAN 111 CHAPTER 8 PROGRAM LISTS Clockwise processing XY XX XX X X xx xk ok ok ek ok ok ok ok ok kk I IO IO IO IO IO IO IO IO IO IO IO J Case x o speed speed Sets target speed if sw mode CCW sw mode STOP o speed 0 Clears to 0 target speed stop req ON Sets to 1 stop request flag proc no 3 34 Sets processing No during deceleration j led out abs o speed abs now speed break Counter clockwise processing kokckckckck KR RK KR RR KK KK RK KR RR KK RK RR ck
66. e TMOCEDO bit of timer control register 00 TMCOO and cannot be controlled through software Dead time timer count start and stop is controlled through hardware A dead time timer starts counting down when the value of dead time timer reload register 0 DTRRO is transferred in synchronization with the compare match timing of compare registers 000 to 002 CMOOO to CMO002 When the value of a dead time timer changes from 000H to FFFH the dead time timer generates an underflow signal and the timer stops at the value FFFH If the value of a dead time timer matches the value of the corresponding compare register before underflow of the dead time timer takes place the value of the DTRRO register is transferred to the dead time timer again and the timer starts down counting The count clock of the dead time timer is fixed to the base clock fcLr and the dead time width is set value of DTRRO register 1 base clock fci If TMOO operates in PWM mode O0 with the dead time timer count operation disabled an opposite signal without dead time is output to TO000 and TO001 TO002 and TO003 and TO004 and TOO05 Dead time timer reload register 0 DTRRO DTRRO register is a 12 bit register used to set the values of the three dead time timers DTMOO to DTMO2 registers However a value is transferred from the DTRRO register to each dead time register independently DTRRO can be read written in 16 bit units All Os are read for the higher 4 bits when 16 b
67. e khe khe ke che che che che kc kc kc kc ck kc kc kc kc kc kc kck ck ck ckckckckck ck ck ck ck ck ck ck ck ckckckckckckckckck ck k Z2 Z3 Z4 int sins int x short zl 118 If X lt zl x return else MAXPULSE 8 lt lt SGETA 12868 z1 x MAXPULSE 4 x Zl x lt lt SGETA Z2 zi zi gt gt SGETA z4 z2 z2 gt gt SGETA return 268432772 z5 MAXPULSE 8 Z2 s zl zi gt gt SCETA 23 21 z2 s SGETA z5 z2 z3 gt gt SGETA 1322 z3 40 z5 gt gt SGETA MAXPULSE 8 5050 z2 252 z4 gt gt SGETA Application Note U14868EJ2VOAN APPENDIX A QA Tn nteryal or 97 113 0 4 ms timer interrupt pp 39 VOM er Ya em 103 115 10 ms timer interrupt pp 39 B Se NT IT NT 87 BEG IDA m 89 BFCM00 to BFCM02 pe 54 BFCMOO to BFCMO8 cccccccceeeeeeeeeeeeeeeeeees 66 BFGMOS M Tp 54 Buffer register CMOS pp 54 Buffer registers CMOO to CMOQ2 54 Buffer registers CMOO to CMO3 66 C Calculation processing ss 118 Circuit diagramM i 40 Clockwise FOLATION is cast nt ee Y Cr FEE RUE 25 CMO000 to CM002 pp 53 IO OB aarti UNS 54 CMTOO ee a 75 NIDI Td E 75 IST 89 COMMON TT 86 110 Common area initialization processing 105 117 Compare register 003 pp 54 Compare register 100
68. e target value for initialization 8 8 LED Display Output Processing 8 kk ek check ke ke KKK KKK che che kc kc kc ck kc kc kc kc I kckckckckckckckckckckckck ck ck ck ck ck ck ck ck ckckckckckckckckckckckck k hs l4 LED display sub routine data display data du 8K kk kk kk kk kk kk ck kk ck kk kk kc kckckckckckckckck ck ckckck ck ckck ck ckckckckckckokckokckokckokckokckokckokckokckokckokckok kk ke e ke e ke x ke x x x fl void led out int data int dispd D dispd abs data if dispd gt 32767 4 dispa e 32767 3 j if data lt 0 4 dispa 0x8000 5 j P3 dispd gt gt 8 s P2 dispd j Application Note U14868EJ2VOAN 117 8 9 Calculation Processing CHAPTER 8 PROGRAM LISTS ee eee ck kc kc kc kc ck kc kc kc ee ee ck ck ck ck ck ee ee sin x data pulse unit Returned value sign value 16384 E S M 37 ty XL K J FCKCK kk KAKAK KKK KKK KKK KKK kc ck kc kc ck ck kc kc ckckckckckckckckck IO ck ck ck ck ck ck ck ck ckckckckckckck ko int Sin int x xX lf X return S x MAXPULSE bf x lt 0 x MAXPULSE MAXPULSE 4 ins x 1 else if x MAXPULSE 2 ins MAXPULSE 2 x else if x lt MAXPULSE 3 4 sins x MAXPULSE 2 return return else return S sins MAXPULSE X s FCKCK kk ek ke ke khe khe khe kh
69. ed with Note in the text Information requiring particular attention Supplementary information Binary XXXX Or xxxxB Decimal XXXX Hexadecimal xxxxH K kilo 2 1 024 M mega 2 1 0247 G giga 2 1 024 Word 32 bits Halfword 16 bits Byte 8 bits Application Note U14868EJ2VOAN Related documents The related documents indicated in this publication may include preliminary versions However preliminary versions are not marked as such Documents related to V850E IA1 aie 14 70F3114 Data Sheet To be DU V8S0E IA2 Hardware Users Manual Hardware User s Manual ulstesE V850E IA1 V850E IA2 AC Motor Inverter Control Using Vector This manual Operation Application Note Documents related to development tools User s Manuals CA850 Ver 2 30 or Later C CA850 Ver 2 40 C Compiler Assembly Language U15027E ID850 Ver 2 40 Integrated Operation Windows Based ER E Debugger SM850 Ver 2 40 System Operation Windows Based U15182E Simulator SM850 Ver 2 00 or Later System External Part User Open U14873E Simulator Interface Specifications RX850 Ver 3 13 or Later Real RX850 Pro Ver 3 13 Real Time os Application Note U14868EJ2VOAN 9 t Y CONTENTS CHAPTER 1 INTRODUCTION cssss sss sss ssc ss essen enen ennenen eenn eenn ee 15 une 15 2257 N TTT 16 1 2 1 IIT c 16 1 2 2 P
70. ee 75 Compare register 101 ee 75 Compare registers 000 to 002 53 Constant definition se n eer i 88 COLL suele B escasa on 86 COMO DIOCK sii tud VETE D Lt ened EUER TPREEEKA EMEN 46 Gonirol principles ooo tt eto aeos 43 Control system pp 43 Coordinate conversion pp 47 Counter clockwise rotation 25 CPU DIOCK NER 27 CULPEME ece 47 49 Current value Input eee eee eee 39 D Dead time timer reload register O 53 67 Dead time timers 00 to 02 53 Determination of operation mode 56 Determination of PWM frequency 55 INDEX Drive circuit block pp 40 BIQ Te REST O 25 39 Drive error input pp 37 DTMOO to DTM02 pe 53 EEE se visas 53 67 E Encoder counter functions 73 Encoder inpuUt et 39 50 EGUIVAICTIE CIRCUINS oessa E 43 ETO ee eei ee es 25 F POW CHATI T 91 Functions in application circuit example 24 Functions of V850E IA1 and V850E IA2 51 H Hardware configuration pp 25 Mit WAG rU 86 Tet serere e getestet 15 OMAA TT 89 K EI X 90 KIGE 89 dm 90 PGE TA eo ee Ede iE M e E 89 ji M oD T RR A 90 ESI TA ES So t Di 89 Kop ved M E MR DRM 90 L WED GIS DIY d H 26 LED display output processing 106
71. ench and floor should be grounded The operator should be grounded using wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken for PW boards with semiconductor devices on it 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin should be connected to Voo or GND with a resistor if it is considered to have a possibility of being an output pin All handling related to the unused pins must be judged device by device and related specifications governing the devices 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note Power on does not necessarily define initial status of MOS device Production process of MOS does not define the initial operation status of the device Immediately after the power source is turned ON the devices with reset function have not yet been initialized Hence power on does not guarantee out pin levels I O settings or contents of registers Device is not initialized until the reset signal is received Reset operation must be executed immediately after power on for devices having reset fu
72. erter Oi L vg 9 pum L o 9 o gt gt oc c o O O o9 O Target Position position controller Target speed 4x frequency multiplier or V850E IA2 Remark All processing enclosed in the solid line is internal to the V850E IA1 or V850E IA2 Processing enclosed in the broken lines is performed by software In the application circuit example the motor is controlled by entering a target position or target speed 1 Position control If a target position has been set speed conversion is performed based on the differential between the target position and the current position 2 Speed control The target current value is calculated based on the differential between the target speed previously set or calculated and the current speed 46 Application Note U14868EJ2VOAN CHAPTER 4 CONTROL SYSTEM 3 Current control The target voltage for the d q axis is calculated based on the current return value converted for the d q axis and the target current value 4 Coordinate conversion The voltage along the d q axis is converted to 3 phase AC voltage 5 PWM conversion The on chip PWM function of the V850E IA1 or V850E IA2 is used to perform PWM output of the calculated 3 phase AC voltage 4 1 3 Motor specifications The specifications for the motor used in the application circuit example are listed in Table 4 1 Table 4 1 Motor Specifications Application Note U14868EJ2VOAN 47 CHAPTER 4 CONTROL S
73. ge specifications for pins TIUD10 and TCUD10 bits TESUDO1 and TESUDOO are not valid CESUD01 Specifies valid edge of TCLR10 pin o me o of Ree 0000000000000 The set values of bits CESUDO1 and CESUDOO and the TM10 operation are related as follows 00 TM10 cleared after detection of rising edge of TCLR10 01 TM10 cleared after detection of falling edge of TCLR10 10 TM10 cleared status held while TCLR10 input is low level 11 TM10 cleared status held while TCLR10 input is high level Caution The set values of the CESUDO1 and CESUDOO bits are valid only in UDC mode A Application Note U14868EJ2VOAN 81 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Figure 5 20 Signal Edge Selection Register 10 SESA10 2 2 IES101 1 Specifies the valid edge of the pin INTP101 INTP100 that is selected by the CSLO bit IES1010 of the CSL10 register IES101 1 IES1010 Valid Edge Both rising and falling edges 1 0 IES1001 Specifies the valid edge of the INTP100 pin ES TOQ IES1001 IES1000 Valid Edge 9 o Ffalingedge Both rising and falling edges Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 6 Timer control register 10 TMC10 settings In this application circuit example the TMC10 register is set as follows TMC10 0x40 count start Figure 5 21 Timer Control Register 10 TMC10 Address After reset 7 lt 6 gt 5 4 3 2 1 0 TMC10 0 TM1CEO 0 o
74. hat immediately follows 3 2 The data written to the SPECO register is dummy data use the same register as the general purpose register used to set the TOMRO register 3 in the above example for SPECO register write lt 2 gt in the above example The same applies when using a general purpose register for addressing 3 Do not write to the SPECO register or TOMRO register via DMA transfer Application Note U14868EJ2VOAN 63 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 4 PWM software timing output register 0 PSTOO In this application circuit example the PSTOO register is set as follows PSTOO 0x00 real time output prohibited Figure 5 8 PWM Software Timing Output Register 0 PSTOO 1 2 lt 1 gt lt Address After reset lt gt 6 5 4 3 lt 2 gt 0 karon rortoo o o o o UPORTo VPORTO WPORTO FFFFFS7EH OOH Bit Position Function 7 TORTOO Specifies TO000 to TO005 output control 0 Timer output 1 Software output The change of the TOOO00 to TO005 signals during software output occurs when the TORTOO bit is set to 1 and a value is written to the UPORTO VPORTO and WPORTO bits A dead time timer can also be used 2 UPORTO Specifies the TO000 U phase TOO01 U phase pin output value Operation Inverted level of ALVTO bit setting Caution Ifthe UPORTO bit setting value is changed when TORTOO 1 the dead time setting becomes valid for the TO000 TOO001 output signal in the same way
75. hen the CMD bit of the TUMO register 0 general purpose timer mode the CLR1 and CLRO bit settings are invalid When the MSEL bit of the TUMO register 1 UDC mode B the CLR1 and CLRO bit settings are invalid When clearing by TCLR10 has been enabled with bits CLR1 and CLRO clearing is performed whether the value of the TM1CEO bit is 1 or 0 Application Note U14868EJ2VOAN 83 CHAPTER 6 PROGRAM CONFIGURATION This chapter describes the program configuration used for the application circuit example This chapter CHAPTER 7 FLOW CHARTS and CHAPTER 8 PROGRAM LISTS describe application circuit examples using the V850E IA1 When using the V850E IA2 perform design making allowances for differences in functions between the V850E IA1 and V850E IA2 such as port timer and timing settings 6 1 Program Structure The program structure is shown in Figure 6 1 Figure 6 1 Program Structure a Operations during each operation mode Operation mode change Operation mode change Counter clockwise rotation processing Processing during deceleration Clockwise rotation processing Detection time processing Counter clockwise rotation operation Clockwise rotation operation STOP processing b Motor control processing c Wait timer processing Wait timer processing Motor control processing 10 ms interval interrupt 0 4 ms interval interrupt 84 App
76. iagram Application circuit RUN signal Error signal op signa Speed volume b p Sig timer circuit Operation mode switch 2 6 Current value 2 Encoder signal 3 3 Display LED 6 UV850E IA1 or V850E IA2 5MHz CJ Note Under development 26 Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION 3 3 CPU Block In this application circuit example the PD70F3116 is used in single chip mode 0 with an external 5 MHz clock internal 50 MHz When using the uPD703116 replace it with no change When using the V850E IA2 set the external 4 MHz internal 40 MHz single chip mode 3 3 1 Memory map The memory map is illustrated below Figure 3 3 Memory Map V850E IA1 FFFFFFFFH V850E IA1 internal peripheral I O area 4 KB FFFFFOOOH FFFFEFFFH FFFFE800H FFFFE7FFH V850E IA1 internal RAM area 10 KB Common area used by this program 36 bytes FFFFCOOOH FFFFBFFFH Access prohibited 00040000H 0003FFFFH V850E IA1 internal ROM area 256 KB Program area used by this program 2 988 bytes Constants used by this program 16 bytes 000008COH ss 000003BFH 00000000H Interrupt exception table Application Note U14868EJ2VOAN 27 CHAPTER 3 HARDWARE CONFIGURATION Figure 3 4 Memory Map V850E 1A2 FFFFFFFFH FFFFFOOOH FFFFEFFFH FFFFD800H FFFFD7FFH FFFFCO00H FFFFBFFFH 00020000H 0001FFFFH 00000460H 0000045FH 00000000H 28 V850E IA2 internal peripheral I O area 4 KB V850E IA2 i
77. ice equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots High Quality Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems medical equipment or systems for life support e g artificial life support devices or systems surgical implantations or healthcare intervention e g excision etc and any other applications or purposes that pose a direct threat to human life You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics especially with respect to the maximum rating operating supply voltage range movement power voltage range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges Although Renesas Electronics endeavors to improve the quality and reliability of its products semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under
78. iconductor products developed based on a customer designated quality assurance program for a specific application The recommended applications of a semiconductor product depend on its quality grade as indicated below Customers must check the quality grade of each semiconductor product before using it in a particular application Standard Computers office equipment communications equipment test and measurement equipment audio and visual equipment home electronic appliances machine tools personal electronic equipment and industrial robots Special Transportation equipment automobiles trains ships etc traffic control systems anti disaster systems anti crime systems safety equipment and medical equipment not specifically designed for life support Specific Aircraft aerospace equipment submersible repeaters nuclear reactor control systems life support systems and medical equipment for life support etc The quality grade of NEC semiconductor products is Standard unless otherwise expressly specified in NEC s data sheets or data books etc If customers wish to use NEC semiconductor products in applications not intended by NEC they must contact an NEC sales representative in advance to determine NEC s willingness to support a given application Note 1 NEC as used in this statement means NEC Corporation and also includes its majority owned subsidiaries 2 NEC semiconductor products means any semiconductor pr
79. in OE200 Specifies the output status of the TO004 pin 0 TOO004 output status is high impedance 1 TOO004 output status is controlled by TMOCEO bit of TMCOO register and TORTOO bit of PSTOO register and ESOO pin 3 OE110 Specifies the output status of the TO003 pin 0 TO003 output status is high impedance 1 TO003 output status is controlled by TMOCEO bit of TMCOO register and TORTOO bit of PSTOO register and ESOO pin OE100 Specifies the output status of the TOO02 pin 0 TO002 output status is high impedance 1 TOO002 output status is controlled by TMOCEO bit of TMCOO register and TORTOO bit of PSTOO register and ESOO pin OE010 Specifies the output status of the TOO01 pin 0 TOOO1 output status is high impedance 1 TOO001 output status is controlled by TMOCEO bit of TMCOO register and TORTOO bit of PSTOO register and ESOO pin 5 4 2 1 OEO000 Specifies the output status of the TO000 pin 0 TOOOO output status is high impedance 1 TOOOO output status is controlled by TMOCEO bit of TMCOO register and TORTOO bit of PSTOO register and ESOO pin 68 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 8 Timer control register 00 TMCOO settings In this application circuit example the TMCOO register is set as follows TMCOO 0x8018 IMOO timer start Figure 5 12 Timer Control Register 00 TMCO0 1 3 lt 15 gt lt 14 gt 13 1 0 Address After reset 2 11 10 9 8 7 6 lt
80. in COMTOUI e e VIEW se rE E 18 1 2 3 ntermnalblock GIA AN ETT TE EO OS ee 19 MeV OOO AN E E E E E E E 20 1 3 1 Fo OS E A 20 1 3 2 Pin configuration top VieW tratte nenne nnn nennen erre 22 1 3 3 Iniermalolock DIS 23 CHAPTER 2 FUNCTIONS IN APPLICATION CIRCUIT EXAMPLE 24 CHAPTER 3 HARDWARE CONFIGURATION 25 SA Operaen a a aa G E a E E E E A a 25 3 2 System Configuration mi 26 39 CPU BOCK oo Eaa 27 3 3 1 Moma e 27 3 3 2 Pm assiognmente se a a e a e e E ee E aE EEEa 29 3 3 3 PEDAS E e E E Q P 36 SAE e rod DRAG e Ee 40 CHAPTER 4 CONTROL SYSTEM ahaha 43 AT Or 43 4 1 1 Control OPIN S sssini S OL EP 43 c E e c e ees CREE Uu m 46 4 1 3 Motor specihicaloNS PM EIS RE RE E T T Tm 47 AMEN oi COMMON e m 48 AS OCCU COT 48 AA Cen CORTON asrni ia 49 4 5 Three Phase Voltage Conversion ee 49 2E MEE QU OT 1111 15 10 neiii a a a aiia 50 AY Encoder Input Processing i 50 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 ee 51 5 1 PWM Timer Function Timer 00 TM00 ee 51 5 1 1 TI 52 5 1 2 Use of PWM timer in application circuit example eee eee eee eee 55 5 1 3 Register settingSs Eom 61 5 2 Encoder Counter Functions Timer 10 TM10 esee 73 5 2 1 Ce ge M 73 5 2 2 Use of encoder counter in application circ
81. is coordinates The equations are shown below id iv x cos r iu x cos 0r 2773 iq ivxsinar iu x sin Or 2773 Remark id d axis current value q axis current value u phase current value v phase current value 0r Angle of rotation 4 5 Three Phase Voltage Conversion The equations used to convert voltage values vd and vq calculated for the d q axis to 3 phase coordinates are shown below O VU 2 0 vdxcos r o vqxsin x Or O Vv 20 vd xcos 0r 2272 o_vq x sin 0r 2773 O VW O VU O VV Remark o vu Target u phase voltage Oo vv Target v phase voltage Oo vw Target w phase voltage o vd Target d axis voltage O vq Target q axis voltage Or Angle of rotation Application Note U14868EJ2VOAN 49 CHAPTER 4 CONTROL SYSTEM 4 6 PWM Conversion The calculated target voltage is output by a 16 bit timer TMOO that is used for the 3 phase sine wave PWM inverter of the V850E IA1 or V850E IA2 see 5 1 PWM Timer Function Timer 00 TMOO 4 7 Encoder Input Processing For x4 frequency multiplication the encoder uses a 16 bit up down counter TM10 that can be used for 2 phase encode input general timer functions in the V850E IA1 or V850E IA2 See 5 2 Encoder Counter Functions Timer 10 TM10 In the control system used in the application circuit example absolute positions along the motor axes must be detected so encoder values are cleared in the Z phase and absolute positions are detected
82. is granted hereby under any patents copyrights or other intellectual property rights of Renesas Electronics or others You should not alter modify copy or otherwise misappropriate any Renesas Electronics product whether in whole or in part Descriptions of circuits software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples You are fully responsible for the incorporation of these circuits software and information in the design of your equipment Renesas Electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits software or information When exporting the products or technology described in this document you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations You should not use Renesas Electronics products or the technology described in this document for any purpose relating to military applications or use by the military including but not limited to the development of weapons of mass destruction Renesas Electronics products and technology may not be used for or incorporated into any products or systems whose manufacture use or sale is prohibited under any applicable domestic or foreign laws or regulations Renesas Electronics has used reasonable care in preparing the information included in this docume
83. it is prohibited to overwrite the value of the CM100 register Compare register 101 CM101 CM101 is a 16 bit register that always compares its value with the value of TM10 When the value of a compare register matches the value of TM10 an interrupt signal is generated In UDC mode A MSEL bit of TUMO register 0 an interrupt signal INTCM101 is always generated upon occurrence of a match Caution When the TM1CEO bit of the TMC10 register is 1 it is prohibited to overwrite the value of the CM101 register Application Note U14868EJ2VOAN 75 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 5 2 2 Use of encoder counter in application circuit example Four types of count operation modes are available in UDC mode when CMD bit of TUM10 register 1 In this application circuit example mode 4 is used when counting A phase and B phase encoders Mode 4 and operations in UDC mode A are described below 1 Mode 4 PRM12 1 PRM11 1 PRM10 1 In mode 4 when a 2 phase signal 90 degrees out of phase is input to the TIUD10 and TCUD10 pins an up down operation is automatically judged and counting is performed according to the timing shown in Figure 5 15 In mode 4 counting is executed at both the rising and falling edges of the 2 phase signal input to the TIUD10 and TCUD10 pins Therefore TM10 counts four times per cycle of an input signal x4 count Figure 5 15 Mode 4 TIUD10 TCUD10 Up count Down count Cautions
84. it read access is performed to the DTRRO register Cautions 1 Changing the value of the DTRRO register during TMOO operation TMOCEO bit of TMCOO register 1 is prohibited 2 Be sure to write 0 in the higher 4 bits Compare registers 000 to 002 CM000 to CM002 The CMO0OO0 to CM002 registers are 16 bit registers that always compare their own values with the value of the TMOO register If the value of a compare register matches the value of TMOO the compare register outputs a trigger signal and changes the contents of the flip flop F F connected to the compare register Each of the CMO000 to CM002 registers is provided with a buffer register BFCMOO to BFCMO2 so that the contents of the Application Note U14868EJ2VOAN 53 54 5 6 7 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 buffer are transferred to the CMOO0 to CMOO2 registers at the following base clock fcLk Transfer is enabled or disabled by the BFTEN bit of the TMCOO register Compare register 003 CM003 The CM003 register is a 16 bit register that always compares its value with the value of TMOO If the values match CMO03 outputs an interrupt signal INTCMOO3 The CM003 register controls the maximum count value of the TMOO register and if the values match it performs the following operations at the next timer count clock e In PWM mode 0 Switches TMOO operation from up count to down count The CM003 register also has a buffer register BFCMO3 and
85. lication Note U14868EJ2VOAN CHAPTER 6 PROGRAM CONFIGURATION Description of structure 1 2 3 During the main processing the operation mode switch status is monitored and the status changes between clockwise rotation operation counter clockwise rotation operation and stop operation modes are controlled As the motor is controlled its status is indicated via 0 4 ms interval interrupts The motor can be controlled in the following three ways e Origin detection rotation Detects origin using constant torque and constant rotation speed e Speed control Rotation speed rpm is maintained at the specified speed e Position control The specified position is maintained Read A D values A D conversion of the U phase current value ANIOO and V phase current value ANI10 begins at the start of 0 4 ms interval interrupt servicing and the converted values are input and used in current feedback processing A D conversion of the volume value input ANIO1 begins after the current value is input and input of converted values occurs after conversion processing The values are set to the volume area and are used in main processing Application Note U14868EJ2VOAN 85 CHAPTER 6 PROGRAM CONFIGURATION 6 2 Common Areas The common areas used in the application circuit example are described in Table 6 1 Table 6 1 Common Area List Symbol Application Setting Value stop_req unsigned char Request to monitor motor rotation stop see
86. nction V850 Series V850E IA1 and V850E IA2 are trademarks of NEC Corporation Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and or other countries Application Note U14868EJ2VOAN 3 The export of this product from Japan is regulated by the Japanese government To export this product may be prohibited without governmental license the need for which must be judged by the customer The export or re export of this product from a country other than Japan may also be prohibited without a license from that country Please call an NEC sales representative License not needed uPD70F3114 70F3116 70F3116 A 70F3116 A1 The customer must judge the need for license uPD703114 703116 703116 A 703116 A1 e The information in this document is current as of March 2002 The information is subject to change without notice For actual design in refer to the latest publications of NEC s data sheets or data books etc for the most up to date specifications of NEC semiconductor products Not all products and or types are available in every country Please check with an NEC sales representative for availability and additional information e No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC NEC assumes no responsibility for any errors that may appear in this document e NEC does not assume any liability for infringement of patents c
87. ng 0 4 ms Interval 8 kk ek ee heck heck KKK khe khe khe ck ck ck kc ck ck ck kc kc kc kc FI I kckckckckckckckckckckck ck ck ckckck ck ck I I Ie a ckck ck ck k oko du y TM4 interrupt servicing 0 4 ms Interval x p FCKCK kk ek ke khe ke ke khe khe khe khe che che khe ck kc kc kc kc kc kc kc kc kc kckckckckckckckckckckckckck ck ck ck KAKAK Amberrupt void int cm4 void int sin int PER signed short 34 GB signed short now enc sa enc sa position Signed int wrm wre trm tre Signed int d speed o iqp O iq id iq signed int o vd o va0 Vdy o cvuq 7 signed int OCWUS VV OVW 3 ADSCM00 0x9800 Starts A D conversion for u phase current ADSCM10 0x9800 Starts A D conversion for v phase current Encoder processing Kk RK KK RR RR RK RR KK RK RR ckck ck ck ckckckckckckckck ck ck ckckckckckckckck ck ck ckck ck ck k k k ck RK KK KR KK kk k now enc TMIO sa enc now enc before enc if abs sa enc gt MAXPULSE 2 if saenc lt 0 Sa enc MAXPULSE else Sa enc MAXPULSE before enc now enc wrm now speed sa enc Sets current speed wre wrm P now position sa enc Updates current position if now enc lt 0 now enc MAXPULSE j trm now enc j tre trm P OFFSET MAXPULSE if stop req ON amp amp abs sa enc 0 stop flag ON Sets to 1 the stop flag j
88. nput ANIO1 is used to input a value from 0 to 1 023 Application Note U14868EJ2VOAN 39 CHAPTER 3 HARDWARE CONFIGURATION 3 4 Circuit Diagram 40 Figure 3 9 shows a diagram of the application circuit example This application circuit diagram includes the V850E IA1 wPD70F3116GJ UEN a reset circuit oscillator a pin handling microcontroller peripheral block operation mode switch block LED output block watchdog timer circuit block drive circuit block motor controller and motor rotation indicator 1 2 3 4 5 6 7 Microcontroller and microcontroller peripheral block The V850E IA1 includes a reset circuit an oscillation circuit that uses a 5 MHz resonator and handling of a MODE pin and unused pins A 4 MHz oscillator is used for the V850E IA2 Operation mode switch block This includes switches that set the operation mode as clockwise or counter clockwise operation LED output block This block includes 16 LEDs which are used to indicate rotation speeds rpm errors etc Watchdog timer circuit block This block uses the PD74HC123A to output stop signals when pulse output from the V850E IA1 stops for at least one ms Drive circuit block The 6 phase outputs from TOOO0 to TOOO06 are converted to U V and W phase output for the motor driver This drive circuit is not shown in detail in this example since it varies depending on the motor s specifications Motor controller This block include
89. nt but Renesas Electronics does not warrant that such information is error free Renesas Electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein Renesas Electronics products are classified according to the following three quality grades Standard High Quality and Specific The recommended applications for each Renesas Electronics product depends on the product s quality grade as indicated below You must check the quality grade of each Renesas Electronics product before using it in a particular application You may not use any Renesas Electronics product for any application categorized as Specific without the prior written consent of Renesas Electronics Further you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas Electronics product is Standard unless otherwise expressly specified in a Renesas Electronics data sheets or data books etc Standard Computers off
90. nternal RAM area 6 KB Common area used by this program 36 bytes Access prohibited V850E IA2 internal ROM area 128 KB Program area used by this program 2 988 bytes Constants used by this program 16 bytes Interrupt exception table Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION 3 3 2 Pin assignments The pin assignment table for the V850E IA1 is shown below Table 3 1 V850E IA1 Pin Assignment 1 4 O Mode Setting Signal Name Not used a m Positive power supply to A D converter 3 favs Ground potential for A D converter Reference voltage input for A D converter 1 AD2_DBG ADIDBG 17 ADO DBG SYNC CLK DBG Reset input CKSEL Input Clock ae operation mode L JB a a c1 Operation mode 2 Operation mode switch input T Output oa timer output H L 2 me m formaa o Input Not used _ Em m oma LEDS output RE se P3 Output LED 10 output REN Remark H High level L Low level Application Note U14868EJ2VOAN 29 CHAPTER 3 HARDWARE CONFIGURATION Table 3 1 V850E IA1 Pin Assignment 2 4 VO Mode Setting Signal Name Output LED11 output Le m om LED12 output 1 o LED13 output Output LED14 output Le me omu LED15 output O I LED16 output m Output LED1 output L a m joe LED2 output Output LED3 output L ie em om LEDA output C RN LEDS output ee LED6 output
91. o 0 the stop request flag Clear to 0 the stop flag Target position is set as current position Set processing No 0 stop Interrupt enabled Speed differential is displayed as LED output see Figure 7 6 LED Display Output Processing Application Note U14868EJ2VOAN 95 96 CHAPTER 7 FLOW CHARTS Figure 7 1 Main Routine 6 6 a Error processing Set to 1 error flag LED display OFF see Figure 7 6 LED Display Output Processing Waited 0 5 seconds Error No is displayed as LED output see Figure 7 6 LED Display Output Processing Waited 0 5 seconds Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS 7 2 Motor Control Interrupt Servicing 0 4 ms Interval Figure 7 2 illustrates the flow of motor control interrupt servicing 0 4 ms interval Application Note U14868EJ2VOAN 97 CHAPTER 7 FLOW CHARTS Figure 7 2 Motor Control Interrupt Servicing 0 4 ms Interval 1 5 See 8 4 Motor Control Interrupt Servicing 0 4 ms Interval Start A D conversion for current Overflow or underflow processing of encoder counter Read encoder value Calculate differential vs previous encoder Is differential absolute value lt one half rotation No Yes Is differential lt 0 Set differential 1 rotation as differential in previous area Motor s current speed and position calculation Electrical rotation speed Differential x Number of pole
92. ock input O Power saving function HALT IDLE and software STOP modes O Power supply voltage Internal units 3 3 V A D converter 5 V External pins 5V O Package 144 pin plastic LQFP fine pitch 20 x 20 O CMOS technology Full static circuits Application Note U14868EJ2VOAN 17 CHAPTER 1 INTRODUCTION 1 2 2 Pin configuration top view e 144 pin plastic LQFP fine pitch 20 x 20 UPD703116GJ xxx UEN 703116GJ A xxx UEN 703116GJ A1 xxx UEN UPD70F3116GJ UEN 70F3116GJ A UEN 70F3116GJ A1 UEN O ADTRG1 INTP3 P04 O ADTRGO INTP2 P03 O ESO1 INTP1 P02 O ESOO INTPO P01 O TCLR11 INTP111 P15 O TCUD11 INTP110 P14 O INTP6 P07 O INTP5 P06 O INTP4 P05 O NMI PO0 ANIO7 O 1 8 O TIUD1 1 TO11 P13 AVDD O 2 7 O TCLR10 INTP101 P12 AVss O 3 6 O TCUD10 INTP100 P1 1 AVREF1 O 4 5 O TIUD10 TO10 P10 ANI10 O 5 4 O PCMA ANI11 O 6 3 O HLDRQ PCM3 ANI12 O 7 2 O HLDAK PCM2 ANI13 O 8 O CLKOUT PCM1 ANI14 O 9 O WAIT PCMO ANI15 O 10 O PCT7 ANI16 O 11 O ASTB PCT6 ANI17 O 12 T5 TRIG DBG O 13 O RD PCT4 AD3_DBG O 14 O PCT3 AD2_DBG O 15 O PCT2 Note 1 AD1 DBG O 16 O UWR PCT1 ADO DBG O 17 O LWR PCTO SYNC O 18 O VDD5 CLK DBG O 19 O VSS5 RESET O 20 O Note 2 CVDD O O CS7 PCS7 CVss O O CS6 PCS6 x10 O CS5 PCS5 x2 O O CSA PCSA CKSEL O O CS3 PCS3 MODEO O O CS2 PCS2 MODE1 O O CS1 PCS1 MODE2 O O CSO PCSO SIO P40 O O A23 PDH7 SO0 P41 O O A22 PDH6 SCKO P42 O O A21 PDH5 SI1 P43 O O A20 PDH4 SO1 P44 O O A19 PDH3 SCK1 P45 O O A18 PD
93. oduct developed or manufactured by or for NEC as defined above M8E 00 4 Application Note U14868EJ2VOAN Regional Information Some information contained in this document may vary from country to country Before using any NEC product in your application please contact the NEC office in your country to obtain a list of authorized representatives and distributors They will verify e Device availability e Ordering information e Product release schedule e Availability of related technical literature e Development environment specifications for example specifications for third party tools and components host computers power plugs AC supply voltages and so forth e Network requirements In addition trademarks registered trademarks export restrictions and other legal issues may also vary from country to country NEC Electronics Inc U S Filiale Italiana Santa Clara California Milano Italy Tel 408 588 6000 Tel 02 66 75 41 800 366 9782 Fax 02 66 75 42 99 Fax 408 588 6130 800 729 9288 e Branch The Netherlands Eindhoven The Netherlands NEC do Brasil S A Tel 040 244 58 45 Electron Devices Division Fax 040 244 45 80 Guarulhos SP Brasil Tel 11 6462 6810 Fax 11 6462 6829 e Branch Sweden Taeby Sweden Tel 08 63 80 820 NEC Electronics Europe GmbH Tax 08 63 80 388 Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 e United Kingdom Branch Milton Keynes UK Tel 01908 691 133 Sucurs
94. opyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products No license express implied or otherwise is granted under any patents copyrights or other intellectual property rights of NEC or others e Descriptions of circuits software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples The incorporation of these circuits software and information in the design of customer s equipment shall be done under the full responsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire containment and anti failure features e NEC semiconductor products are classified into the following three quality grades Standard Special and Specific The Specific quality grade applies only to sem
95. plication circuit example the TUMO register is set as follows TUMO 0x80 UDC mode selection Figure 5 18 Timer Unit Mode Register 0 TUMO Address After reset 7 6 5 4 3 2 1 0 7 CMD Specifies the TM10 operation mode 0 General purpose timer mode up count 1 UDC mode up down count 3 TOE10 Specifies timer output TO10 enable 0 Timer output disabled 1 Timer output enabled Caution When CMD bit 1 UDC mode timer output is not performed regardless of the setting of the TOE10 bit At this time timer output consists of the negative phase level of the level set by the ALVT10 bit 2 ALVT10 Specifies the active level of timer output TO10 0 Active level is high level 1 Active level is low level Caution When CMD bit 1 UDC mode timer output is not performed regardless of the setting of the TOE10 bit At this time timer output consists of the negative phase level of the level set by the ALVT10 bit MSEL Specifies the operation in UDC mode up down count 0 UDC mode A TM10 can be cleared by setting the CLR1 CLRO bits of the TMC10 register UDC mode B TM10 is cleared in the following cases e Upon match with CM100 during TM10 up count operation e Upon match with CM101 during TM10 down count operation When UDC mode B is set the ENMD CLR1 and CLRO bits of the TMC10 register become invalid Application Note U14868EJ2VOAN 79 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 4 Prescaler mode regi
96. re intended for the standard quality models for general purpose electronic systems When using an example in this manual for an application that requires the special quality grade evaluate each component and circuit to be actually used to see if they satisfy the required quality standard 2 To use this manual for special grade products read the part numbers as follows uPD703116 uPD703116 A 703116 A1 uPD70F3116 uPD70F3116 A 70F3116 A1 For details of hardware functions especially register functions setting methods etc See the V850E IA1 Hardware User s Manual V850E IA2 Hardware User s Manual For details of instruction functions See the V850E1 Architecture User s Manual When register format diagrams show values of 0 or 1 in each register do not set values other than 0 or 1 to those registers Application Note U14868EJ2VOAN 7 Conventions Data significance Active low representation Memory map address Note Caution Remark Numeric representation Prefix indicating the power of 2 address space memory capacity Data Type Bit numbers in the register format drawing for each of the registers that are enclosed in angle brackets lt gt are defined as reserved words in the device file Higher digits on the left and lower digits on the right Xxx Overscore over pin or signal name Higher addresses on the top and lower addresses on the bottom Footnote for item mark
97. ronics products or if you have any other inquiries Note 1 Renesas Electronics as used in this document means Renesas Electronics Corporation and also includes its majority owned subsidiaries Note 2 Renesas Electronics product s means any product developed or manufactured by or for Renesas Electronics 424 NE S AS Application Note V850E IA1 V850E IA2 32 Bit Single Chip Microcontrollers AC Motor Inverter Control Using Vector Operation V850E IA1 V850E IA2 uPD703116 uPD703114 uPD703116 A uPD70F3114 uPD703116 A1 uPD70F3116 uPD70F3116 A uPD70F3116 A1 Document No U14868EJ2VOANOO 2nd edition Date Published July 2002 N CP K NEC Corporation 2000 2002 Printed in Japan MEMO 2 Application Note U14868EJ2VOAN NOTES FOR CMOS DEVICES D PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note Strong electric field when exposed to a MOS device can cause destruction of the gate oxide and ultimately degrade the device operation Steps must be taken to stop generation of static electricity as much as possible and quickly dissipate it once when it has occurred Environmental control must be adequate When it is dry humidifier should be used It is recommended to avoid using insulators that easily build static electricity Semiconductor devices must be stored and transported in an anti static container static shielding bag or conductive material All test and measurement tools including work b
98. s Current position Current position current speed NO Set differential 1 rotation as differential Is encoder value 0 Absolute angle calculation processing Yes Set encoder 1 rotation as encoder value Set the mechanical angle and Electro mechanical angle Mechanical angle x No of poles Origin offset electro mechanical angle Does encoder differential 0 after setting to 1 the stop request flag No Yes Set to 1 stop flag 98 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS Figure 7 2 Motor Control Interrupt Servicing 0 4 ms Interval 2 5 A Position control processing Speed conversion Is speed control set as control mode Confirm target position Target position target position target speed Calculation of differential Differential vs target position target position current position vs target position Clear to 0 initial flag Yes Position differential gt SA POSI MAX Yes PWM output off Set error flag to ERR_NO2 position displacement Is position control set as control mode Yes icc Bos d Target speed Position difference x kp KPGETA Application Note U14868EJ2VOAN 99 CHAPTER 7 FLOW CHARTS Figure 7 2 Motor Control Interrupt Servicing 0 4 ms Interval 3 5 Speed control processing current conversion Calculate speed differential Speed differential vs target target speed c
99. s the HPS 5 AS LM324 and other devices that are used to measure the motor s drive currents U and V via A D conversion Motor rotation indicator This block includes a volume adjuster and the LM324 for setting the motor s rotation speed rpm Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION Figure 3 9 Circuit Diagram of Application Circuit Example 5 V 7 V R1A VR 4 R3 R4 R5 R6 R7 R19 R20 R21 R22 U1A 47 47 47 47 47 47 47 47 47 3 3 LM324 R13 R14 R15 R16 R17 R18 R8 R9 R10 R11 R12 1 P139 47 47 47 47 47 47 47 47 47 47 47 2 1K E Z TP1 TP2 TP3 Motor rotation indicator STOP LC 2 G LC 2 G LC 2 G Ww U V W 9 5V Wj i d a MW MOT OUT Vj Ji PERE DDS D ooo 7 U inl U v 2 CTT m Ht pn D1 icy T Ti w NEN CN 3P LB V sii T 5V PSSA 12 V Motor connector U2A 1 2 3 4 st o al o o co NJ ol ol l 9 a adr ol o t eel vl 9 a oN co Lo oal olo CT1 i SE YH Ee eaa e ee Ee e e E EE STS ES eE Ea EREE 0 1u film RESET SW 74ACT14 74ACT14 3SS YA FSF 58 S ayaa gays SIN E 4 a7 S83885900092 9r989022388585823895g0z ey ial Z22222202258858889999888885552 amp 5CRRRR bu y Swi tttettt tS ITILIE EEEE
100. sfer BFCM03 CM003 transfer disabled enabled Specifies the operation mode of TMOO Operation Mode i BFCM03 BFCM00 to Operation Clear CM003 BFCM02 Timing CM000 to CM002 Timing PWM mode 0 Up down INTTMOO INTTM00 symmetric triangular wave Other than above Setting prohibited Caution Changing the value of the MOD01 MODOO bits during TMOO operation TMOCEO bit 1 is prohibited Application Note U14868EJ2VOAN T1 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 9 Timer unit control register 00 TUCOO settings In this circuit example the TUCOO register is set as shown below Figure 5 13 Timer Unit Control Register 00 TUC00 lt 1 gt 0 Address After reset 7 6 5 4 3 2 1 TORSO Flag that restarts the output of the TO000 to TO005 pins which was forcibly stopped through ESOO pin input Output is resumed by writing 1 to the TORSO bit Cautions 1 If the level is the ESOO pin input level setting TOMR register TOEDG1 bit 1 TOEDGO bit 0 or 1 the output disabled state is not released TOSTAO bit 1 even if 1 is written to the TORSO bit while the level is the output disable state TOSTAO bit 0 The output disabled state is released when the input level becomes the inactive level TOSTAO bit 0 When the ESOO pin input is the edge setting TOEDG1 bit 0 TOEDGO bit 0 or 1 the output disabled state TOSTAO bit 1 is released TOSTAO bit 0 by writing 1 to the T
101. sible to automatically output a PWM waveform to TOOO0 to TOOO05 pins taking into consideration the dead time width in case of interrupt culling ratio of 1 1 Application Note U14868EJ2VOAN 57 58 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Output waveform width in respect to set value e PWM cycle BFCMOS x 2 x Trwoo e Dead time width Tbom DTRRO 1 fcLk Active width of positive phase TO000 TO002 TO004 pins CM003 CMOOXup CM003 CMOOXaown x TTMoo T pom e Active width of negative phase TO001 TO003 TOO005 pins CMOOXdown CMOOXup x TTMoo T pom e In this mode CMOOXup CMOOXaown However within the same PWM cycle Since CMOOXup and CMOOXaown in the negative phase formula are prepared in a separate PWM cycle CMOOXup z CMOOXaown fcLk Base clock T Too TMOO count clock CMOOXup Set value of CM000 to CMOO2 while TMOO is counting up CMOOXaow Set value of CM000 to CM002 while TMOO is counting down The pin level when the TO000 to TOOOS pins are reset is the high impedance state When the control mode is selected thereafter the following levels are output until the TMOO is started e OO00 TO002 TO004 When low active High level When high active Low level e O001 TO003 TOO05 When low active Low level When high active High level The active level is set with the ALVTO bit of the TOMRO register The default is low active Caution f a value such that the positive
102. ster 10 PRM10 settings In this application circuit example the PRM10 register is set as follows PRM10 0x07 operation mode 4 selection Figure 5 19 Prescaler Mode Register 10 PRM10 Address After reset 2to 0 PRM12 to Specifies the up down count operation mode during input of the clock rate when the PRM10 internal clock of the TM10 is used or AE 2 external clock AN UON 0 input PRM12 PRM11 PRM10 CMD 0 0 CMD t Count Clock Count Up Down Clock Count MON NEN NN Setting prohibited prohibited Setting PIOS the SESA10 register S o r o fe Remark fci Base clock 80 Application Note U14868EJ2VOAN CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 5 Signal edge selection register 10 SESA10 settings In this application circuit example the SESA10 register is set as follows SESA10 0x00 falling edge selection Figure 5 20 Signal Edge Selection Register 10 SESA10 1 2 7 6 5 4 3 2 1 0 Address After reset SESA10 JTESUDO01 TESUDO0O CESUDO1 CESUDOO IES1011 IES1010 IES1001 IES1000 FFFFF5EDH OOH TIUD10 TCUD10 TCLR10 INTP101 INTP100 7 6 TESUDO 1 Specifies valid edge of pins TIUD10 TCUD10 o mm aaas Tamanna Cautions 1 The set values of the TESUDO1 and TESUDOO bits are only valid in UDC mode A and UDC mode B If mode 4 is specified as the operation mode of TM10 specified with PRM12 to PRM10 bits of PRM10 register the valid ed
103. t at the position where it stops e While the rotor is stopped the LED display shows the differential compared to the stopped position e When the mode is changed from STOP mode to clockwise or counter clockwise rotation the rotor starts turning 3 Errors e here are three types of errors Overcurrent error Error No 1 ERR NO1 Positioning error Error No 2 ERR NO2 Drive error Error No 3 ERR NO3 Caution This application circuit example performs watchdog monitoring which turns off PWM output via hardware when a program loop occurs due to errors other than those listed above e When an error has occurred the current operation mode is stopped and the corresponding error number is displayed via blinking LED indicators For example if a drive error error No 3 occurs LED1 and LED2 both start blinking To clear the error display perform a reset Application Note U14868EJ2VOAN 25 CHAPTER 3 HARDWARE CONFIGURATION 4 LED display e f the rotor s rpm differential or the position differential is a negative value LED16 is lit to indicate a minus sign see 3 3 3 1 a LED output Figure 3 1 LED Display of Minus Sign LED16 LED15 LED14 LED3 LED2 LED1 O O O e O O O LED16 is lit to indicate a minus sign e When an error is displayed the displayed error No blinks at a 0 5 second interval 3 2 System Configuration The hardware configuration is shown in the following figure Figure 3 2 Hardware Configuration D
104. the new culling ratio is applied after an interrupt has occurred with the culling ratio prior to the change Application Note U14868EJ2VOAN 69 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 Figure 5 12 Timer Control Register 00 TMCO0 2 3 10 to 8 PRMO2 to Specifies the count clock for TMOO iL PRMO2 PRMO1 PRMOO Count Clock Other than above Setting prohibited Caution The divide ratio switch timing is after the TMOO value has become 0000H and an INTTMOO interrupt has occurred Therefore in the timing that corresponds to interrupt culling the divide ratio is not switched Remark For the base clock Gu see 5 1 3 1 Timer 0 clock selection register PRM01 5 TMOCEDO Specifies the operation of the DTMOO to DTM02 timers 0 DTMOO to DTMO2 perform count operation 1 DTMOO to DTMO2 stopped Cautions 1 Changing the TMOCEDO bit during TMOO operation TMOCEO 1 is prohibited 2 If TMOO is operated when TMOCEDO bit z 1 a signal without dead time is output to the TO000 to TO005 pins 4 m l BFTE3 Specifies transfer of data from the BFCM03 register to the CM003 register 0 Transfer disabled 1 Transfer enabled The transfer timing from the BFCM03 register to the CM003 register is as follows BFTE3 TMOO Operation Mode BFCM03 CMO003 Transfer Timing 1 PWM mode 0 symmetric INT T MOO triangular wave When BFTES bit 1 the value of the BFCMOS register is transferred to the CM003 register upon occurrence of an INTTMOO or INTCMO0
105. the watchdog timer circuit If a pulse is not output after 1 ms or more the watchdog timer circuit sends a PWM stop instruction to the ESOO pin of the V850E IA1 or V850E IA2 38 Application Note U14868EJ2VOAN CHAPTER 3 HARDWARE CONFIGURATION e P43 V850E IA1 or P33 V850E IA2 Drive error input Bit 3 Pn3 indicates the driver error input status Drive error When an error signal occurs in the driver i e when the Pn3 bit 1 PWM is stopped and notification is sent to the CPU Remark V850E IA1 n 4 V850E IA2 n 3 c PWM output Timer 00 TMOO is used to output PWM waveforms In this application circuit example the settings are as shown below e 20 kHz symmetrical triangular waveform mode e Dead time 20 us TOOO0 to TOO05 Log active e When ESOO pin input is at high level PWM output is stopped d bd Encoder input Encoder input is counted using timer 10 TM10 In this application circuit example the settings are as shown below e Up down counter mode s UDC mode A e Counter is cleared after falling edge of TCLR10 is detected e x4 frequency multiplication mode 4 is used e 10 ms timer interrupt Timer 3 TM3 is used to issue interrupts at a 10 ms interval f 0 4 ms timer interrupt Timer 4 TM4 is used to issue interrupts at a 0 4 ms interval g Current value input ANIOO U phase current value 5 to 5 A ANI10 V phase current value 5 to 5 A h Speed specification volume value i
106. tion mode switch input P42 Watchdog timer output P43 Drive error input Set timer 3 TM3 to 10 ms interval Set timer 4 TM4 to 0 4 ms interval Set ANIOO and ANIO1 Input U phase current value and speed volume value Set ANI10 Input V phase current value Set timer 00 TMOO PWM output Set timer 10 TM10 Encoder counter 104 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS 7 5 Common Area Initialization Processing Figure 7 5 illustrates the flow of common area initialization processing Figure 7 5 Common Area Initialization Processing See 8 7 Common Area Initialization Processing Set to 1 initial flag Clear to 0 stop flag Clear to 0 stop request flag Clear to 0 error flag Set position control as control mode Set 0 as current position Set 0 as target position Set 0 as target speed Read previous encoder values from TIUD10 TCUD10 and TCLR10 then set to 1 Set 0 as speed integral value Clear to 0 the target position for initialization EXIT Application Note U14868EJ2VOAN 105 CHAPTER 7 FLOW CHARTS 7 6 LED Display Output Processing Figure 7 6 illustrates the flow of LED display output processing Figure 7 6 LED Display Output Processing See 8 8 LED Display Output Processing Set displayed data as absolute values Displayed data gt 32 767 Yes Set displayed data as 32 767 Original data is negative Yes Set to 1 the displayed data s
107. tput TO001 output TO002 output TO003 output TO004 output TO005 output With dead time Application Note U14868EJ2VOAN 60 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 5 1 3 Register settings 1 Timer 0 clock selection register PRMO1 settings In this application circuit example the PRMO 1 register is set as follows Caution Always set this register before using the timer PRMO1 0x00 fclk fxx 2 In the case of the V850E IA2 the PRMO1 register should be set as follows PRMO1 0x01 fclk fxx Figure 5 5 Timer 0 Clock Selection Register PRM01 Address After reset PRM1 Specifies the base clock Gus of timer 00 TMOO 0 fxx 2 When 0 gt 40 MHz 1 fxx When 0 lt 40 MHz Remark fxx Internal system clock 2 TOMR write enable register 0 SPECO settings In this application circuit example the SPECO register is set as follows SPECO 0x0000 IOMRO write enable Figure 5 6 TOMR Write Enable Register 0 SPECO Address After reset SPECO FoTeToToToToIeToToTe eIsloIolsle FFFFF580H 0000H Application Note U14868EJ2VOAN 61 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 3 Timer output mode register 0 TOMRO settings In this application circuit example the TOMRO register is set as follows TOMRO 0x03 output mode setting Figure 5 7 Timer Output Mode Register 0 TOMRO 1 2 Address After reset 7 6 5 4 3 2 1 0 TOMPO ALVTO ALVU
108. transfers the buffer contents in the next base clock fcLk cycle to the CMO03 register Transfer enable or disable is controlled with the BFTES bit of the TMCOO register Buffer registers CMOO to CM02 BFCMOO to BFCMO2 The BFCMOO to BFCMO 2 registers are 16 bit registers that transfer data to the compare register CMOOO to CMO002 corresponding to each buffer register when an interrupt request signal INTCMOOS INTTMOO is generated BFCMOO to BFCMO 2 can be read written in 16 bit units Caution The set values of the BFCMOO to BFCMO 2 registers are transferred to the CM000 to CM002 registers at the following timing e When TMOCEO bit of TMCOO register 0 Transfer at next operation timing after write to BFCMOO to BFCM02 register e When TMOCEO bit of TMCOO register 1 Value of BFCMOO to BFCM02 registers is transferred to CM000 to CM002 registers upon occurrence of INTTMOO or INTCMOO3 At this time transfer enable or disable is controlled by the BFTEN bit of the timer control register TMCOO Buffer register CM03 BFCMO3 The BFCMO3 register is a 16 bit register that transfers data to the compare register at any timing Transfer enable or disable is controlled by the BFTES bit of the TMCOO register BFCMO3 can be read written in 16 bit units Cautions 1 The set value of the BFCMO3 register is transferred to the CMO003 register at the following timing e When TMOCEO bit of TMCOO register 0 Transfer at next operation timing after write
109. uit example pp 76 5 2 3 Sal n e E 77 CHAPTER 6 PROGRAM CONFIGURATION ee 84 10 Application Note U14868EJ2VOAN Gl Progran SWwoctremm 84 562 eel e E 86 6 3 Constant Definition sss ssss sss sss sees esse esse esse eee 88 6 4 Motor Control ConstantS 90 CHAPTER 7 FLOW CHARTS nn 91 Tail ANE ROUTING HH 91 7 2 Motor Control Interrupt Servicing 0 4 ms Interval es 97 7 3 Wait Timer Interrupt Servicing 10 ms Interval jt 103 7 4 Peripheral I O Initialization Processing ee 104 7 5 Common Area Initialization Processing ee 105 7 6 LED Display Output Processing ee 106 7 7 sin Calculation Processing ee 107 7 8 Subroutine Processing for sin Calculation ee 108 CHAPTER 8 PROGRAM LISTS e eiieeeliieeeniiee eee h nnn n annua anu n sanus sas s asas s asas sa nnnm 109 8 1 Definition of Constants 0 109 8 2 Common Bw c Ferner a a a PP eer VD ANDE ee eee rene reer eer ere 110 03 MiM lt e T 111 8 4 Motor Control Interrupt Servicing 0 4 ms Interval 113 8 5 Wait Timer Interrupt Servicing 10 ms Interval 0 115 8 6 Peripheral I O Initialization Processing ee 116 8 7 Common Area InitialiZation Processing ee 117 8 8 LED Display Output Processing ee 117 8 9 Calculation Processing css ssss sss sss esse esse esse esen enen 118 APPENDIX A INDEX i 119 APPENDIX B REVISION HISTORY sm OD OO 122 Application Note U14868EJ2VOAN 11 Figure No Figure
110. urrent speed vs target Calculate current value Current value ksp x velocity difference velocity integral value KSIGETA Velocity integral value gt IS_MAX Velocity integral value lt IS_MAX Velocity integral value IS MAX Velocity integral value IS MAX Update velocity integral value Update velocity integral value Velocity integral value ksi x speed differential 100 Application Note U14868EJ2VOAN CHAPTER 7 FLOW CHARTS Figure 7 2 Motor Control Interrupt Servicing 0 4 ms Interval 4 5 G Current control processing voltage conversion Read current values for U and V phases Speed volume conversion A D conversion starts Current value gt MAX I Yes PWM output OFF Set error flag to ERR NO overcurrent NO Convert from U and V phase current values to current values Calculate current values for d and q axes Calculate voltage value for d axis Calculate voltage value for q axis No for d and q axes Voltage value for d axis ki x d axis current value KIGETA Voltage value for q axis ki x target current value for q axis current value for q axis KIGETA d axis voltage VMAX Yes d axis voltage VMAX d axis voltage VMAX No d axis voltage lt VMAX No q axis voltage gt VMAX Yes q axis voltage VMAX Yes q axis voltage VMAX q axis voltage lt VMAX No Application Note U14868EJ2VO
111. value This comparison value is one half of the cycle for PWM mode 0 symmetrical triangular wave mode In this application circuit example the PWM cycle is 20 kHz and the dead time is 2 us Therefore the following values are determined when the system clock frequency is 50 MHz Input clock basic clock selection fxx 2 PRM1 bit of PRMO1 register 0 Division ratio 1 1 PRMO2 to PRMOO bits of TMCOO register 000 Count clock 25 MHz CM003 value Count clock frequency PWM frequency x 1 2 625 In the case of the V850E IA2 to set the PWM frequency to 20 kHz and the dead time to 2 ws the following values are used with the system clock set to 40 MHz Input clock basic clock selection fxx 2 PRM1 bit of PRMO 1 register 1 Division ratio 1 1 PRMO2 to PRMOO bits of TMCOO register 000 Count clock 40 MHz CMO003 value Count clock frequency PWM frequency x 1 2 1000 Application Note U14868EJ2VOAN 55 CHAPTER 5 FUNCTIONS OF V850E IA1 AND V850E IA2 2 Determination of operation mode The TMCOO register is used to set the operation mode for the PWM timer TMOO as is shown in Figure 5 2 Figure 5 2 Operation Mode Setting lt 15 gt lt 14 gt 13 1 Address After reset 2 1 10 9 8 7 6 c 4 3 2 1 TMCOO TMOCEO SH EUS CULO GU Pawo Pror Prvo O O TMICEDO BEEN TEN veFTE voor wob FFFFF57AH 0508H Operation mode TMOO Timer clearing Timing of Timing of operation factor BFCMOS BFCMOO to CM003 BFCM02 CM00
112. vided Not provided function A D converter Analog input Total of two circuits 16 ch Total of two circuits 14 ch A D converter 0 8 ch A D converter 0 6 ch A D converter 1 8 ch A D converter 1 8 ch AVop AVrer pins Independent pins Alternate function pins Supply voltage Vons 3 38 V 0 3V Vpop Rvo 5 0 V 0 5 V Voos 5 0V 0 5 V Internal regulator 144 pin plastic LQFP 100 pin plastic LQFP Remark For details refer to the hardware user s manual of each product Application Note U14868EJ2VOAN 15 1 2 V850E IA1 1 2 1 Features O Number of instructions 83 O Minimum instruction execution time CHAPTER 1 INTRODUCTION 20 ns internal 50 MHz operation O General purpose registers 32 bits x 32 registers O Instruction set V850E1 CPU Signed multiplication 32 bits x 32 bits 64 bits 1 or 2 clocks Saturated operation instructions with overflow underflow detection function 32 bit shift instruction 1 clock Bit manipulation instructions Long short format load store instructions Signed load instructions O Memory space 256 MB linear address space shared by program and data Chip select output function 8 spaces Memory block division function 2 4 or 8 MB block Programmable wait function Idle state insertion function O External bus interface 16 bit data bus address data multiplexed 16 8 bit bus sizing function Bus hold function External wait function Product Name Internal ROM Internal RAM O On chip memory uP

V850E/IA1, V850E/IA2 32-Bit Single-Chip Microcontrollers AC Motor

Contents

Download Pdf Manuals

Related Search

Related Contents