AN4207 - STMicroelectronics
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1. v AN4207 YI Application note Getting started with STM32F37x 38x SDADC Sigma Delta ADC Introduction The STM32F37x series of microcontrollers combines a 32 bit ARM Cortex M4 core with a DSP and FPU instructions running at 72 MHz with advanced analog peripherals This series introduces the combination of a Cortex M4 core with a precise 16 bit Sigma Delta ADC This document outlines the main features of the SDADC and shows how the SDADC can be used in various application cases By way of example four application cases are presented in this document 1 Temperature measurement using PT100 2 Pressure measurement using MPX2102A 3 Wave recorder 4 ElectroCardioGram ECG acquisition To help you get started quickly the four application cases are implemented in C language and are available as part of the STM32F37x DSP and standard peripherals library package stm32f37x dsp stdperiph lib and the STM32373C EVAL demonstration firmware package stm32373c eval fw Please note that this document is not intended to replace the Sigma Delta Analog to Digital Converter SDADC section in the STM32F37xx STM32F38xx reference manual RM0313 All values given in this document are guidance only Please refer to the related datasheet to get guaranteed and up to date values Table 1 Applicable products Type Part numbers Microcontrollers STM32F37X STM32F38x December 2012 Doc ID 023945 Rev 1 1 28 www st com Co2. 2 Perform conversion and store result in internal register configuration register 3 Subtract automatically the calibration value from conversion value during standard conversion It is recommended to run calibration at least once after SDADC configuration Figure 6 Offset error in SDADC Digital value Positive offset Analog input Negative offset Null offset MSv31132V1 Gain calibration Another error source is the gain error As illustrated in Figure 7 the gain error is the deviation of the SDADC s transfer function from the ideal straight line It is due to the built in programmable amplifier According to the device datasheet the typical analog gain error is 2 7 which means there can be 884 counts at maximum voltage due to gain error So reducing the gain error is mandatory when performing accurate measurements Doc ID 023945 Rev 1 11 28 Overview of 16 bit SDADC AN4207 Note 12 28 Figure 7 Gain error in SDADC Positive gain error Digital value g Null gain error Analog input MSv31133V1 Two types of gain are implemented in the SDADC Analog gain x1 2 x1 x2 x4 x8 Digital gain x16 and x32 Only the analog gains are considered in gain calibration Gain calibration requires an external accurate reference and it is performed by applying the accurate reference voltage AccRef at the SDADC input and getting the SDADC output The gain is computed as fol
3. 72 MHz Audio l l DN AOP LA 1st buffer 2nd buffer I MSv31139V1 The flowchart of this application is given in Figure 13 22 28 Doc ID 023945 Rev 1 ky AN4207 Application examples Figure 13 Flowchart of wave recorder application Wave recorder Create a wave file on MicroSD Write SDADC sample in selected buffer Init SDADC Init TIM13 used as trigger Is selected buffer full Write selected buffer in MicroSD Stop recording Switch selected buffer Clear TIM4 interrupt Generate TIM4 interrupt Stop recording Disable SDADC Disable TIM13 Close the wave file Clear TIM13 interrupt Exit application MSv31140V1 Doc ID 023945 Rev 1 23 28 Application examples AN4207 4 4 Note 24 28 ElectroCardioGram ECG acquisition This application shows how to use the 16 bit Sigma Delta Analog to Digital converter to acquire a human ECG using two ECG electrodes TS1 and TS2 installed on the STM32373C EVAL evaluation board The application source code is available in the Project STM32373C EVAL src applications c file in the STM32373C EVAL demonstration firmware package stm32373c eval_fw Two ECG electrodes TS1 and TS2 are connected to SDADC1 channel 0 PE12 through an ECG amplifier filter The SDADC is configured in Single Ended Zero Refer
4. Table 7 Document revision history 0 ee hr 27 ky Doc ID 023945 Rev 1 3 28 List of figures AN4207 List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 4 28 Block diagram of a sigma delta analog to digital converter 5 Input signal range in differential mode 0 0 00 eee 7 Typical connection of differential sensor to differential channels 8 Input signal range in single ended offset mode 0 eee eee 9 Input signal range in single ended zero reference mode 0 0 eee0ee 10 Offset error in SDADC 0 20 cc tetas 11 Gain errorin SDADC 2 0 00 eee 12 Gain calibration using the accurate reference voltage a 13 SDADC software calibration sequence eee 14 Equivalent input circuit for input channel 0 0 eee ee 15 ADC architecture vs resolution and sampling rate e eee eee 17 Block diagram of voice recorder nh 22 Flowchart of wave recorder application 0 0 0 cece ee 23 Block diagram of the electrocardiogram ECG acquisition application 24 Flowchart of ECG acquisition application llle 25 Three phase power meter application using STM32F37x 38x devices 26 Doc ID 02394
5. a voltage drop across it because of the current flowing into the pin In SDADC the channel input impedance depends on 1 SDADC clock 2 Analog gain 0 5 8 The figure below shows the equivalent input circuit for input channel where R is the input impedance of SDADC analog input and can be calculated using the formula below 1 EE ou m 2 fox C Figure 10 Equivalent input circuit for input channel C 0 543 pF 0 152 pF gain chclkz chclkz chclk C 0 543 pF 0 152 pF gain l Rain The impedance of the analog signal source Vain The signal source MSv31137V1 Table 3 Typical SDADC input channel input impedance Frequency Gain RiN 1 5 MHz 0 5 540 KO 6 MHz 0 5 135 KO 6 MHz 8 47 KO Doc ID 023945 Rev 1 15 28 Overview of 16 bit SDADC AN4207 2 1 6 Low power modes The 16 bit SDADC combines both high resolution and low power consumption making it suitable for battery powered products If the SDADC is left powered up continuously it consumes 1 2 mA maximum typically 800 pA The SDADC has three main modes for reducing power consumption 1 Slow mode In this mode the SDADC consumes 600 HA maximum but the sampling rate is limited to 12 5 Ksps maximum 2 Standby mode In this mode the SDADC consumes a maximum of about 200 pA but a stabilization time of 300 SDADC clock cycles 50 us 6 MHz is required each time it exits from Standby mode 3 Power down mode In
6. complete transfer interrupt MSv31142V1 Doc ID 023945 Rev 1 25 28 Application examples AN4207 4 5 26 28 Power meter application The analog to digital converter is the most important part of a power meter application and the SDADC embedded in STM32F37x 38x devices meets the requirements of this type of application Typically a class B power meter requires 1 5 current measurement accuracy which means a 14 bit Effective Number Of Bits ENOB ADC For the voltage measurement there are no strict requirements and therefore the SAR ADC can be used for voltage measurement synchronized with the SDADC that is used for measuring the current Another constraining parameter of the Analog to Digital Converter is the sampling rate For power meter applications a sampling rate of up to 12 8 ksps is sufficient for harmonic spectrum analysis As shown in Figure 16 in the power meter application the phase measurement consists of measuring voltages Va Vb and Vc in single ended mode using the SAR ADC while currents la Ib and Ic are converted in differential mode using the SDADC All are triggered by the same timer for example TIM19 Figure 16 Three phase power meter application using STM32F37x 38x devices e seyd q eseud o eseud jeanaN JANE Resistor divider 7 ADC_INO g HE Resistor divider Resistor divider L STM32F37x Ic SDADC3_AINOP Current sensor 3 SDADC3_AINOM lb SDAD
7. ksps when selecting a single channel and 16 6 ksps when multiplexing between different channels 2 For SDADC the input impedance depends on the selected gain and the selected operating frequency 1 5 MHz or 6 MHz For SAR ADC the input impedance depends on used sampling frequency 0 05 1 MHz and sampling capacitor 8pF a 18 28 Doc ID 023945 Rev 1 AN4207 Application examples 4 Application examples This section presents how the 16 bit SDADC embedded in STM32F37x 38x devices can be used in application examples such as temperature measurement pressure measurement three phase power meter voice recorder 4 1 Temperature measurement This purpose of this application is to show how to use the 16 bit resolution Sigma Delta Analog to Digital converter to perform accurate temperature measurement using the PT100 sensor connected to PE7 in the STM32373C EVAL evaluation board The application source code is available in are available in the Project STM32F37x_StdPeriph_Examples SDADC folder in the STM32F37x DSP and standard peripherals library package stm32f37x dsp stdperiph lib A current source circuit available on the STM32373C EVAL board is used to provide a fixed 1 mA current when Vpp 3 3 V to the temperature sensor PT100 which is connected to SDADC1 channel 3P PE7 through a reference resistor 1K8 labeled R33 The SDADC is configured in single ended offset mode The input range is from O V to Vner 2 gain In
8. 5 Rev 1 ky AN4207 Basics of sigma delta converters Basics of sigma delta converters Sigma delta converters also known as oversampling converters consist of two basic circuits a modulator and a digital filter Figure 1 In the modulator the input signal is added to the negative feedback signal from the digital to analog converter DAC The signal s difference after passing through the integrating circuit reaches the input of the comparator 1 bit ADC where it is compared to the reference voltage the comparator works as a 1 bit quantizer The input signal from the comparator 1 bit ADC controls the 1 bit converter and reaches the input of the digital filter which decreases flowability and transforms the 1 bit stream into 16 bit words The used filter topology that ensures the low pass stage is Sinc Figure 1 Block diagram of a sigma delta analog to digital converter 1 bit stream Digital filter 16 bit data amp Decimator 1 bit ADC 1 bit DAC MSv31135V1 Doc ID 023945 Rev 1 5 28 Overview of 16 bit SDADC AN4207 2 2 1 Note 6 28 Overview of 16 bit SDADC Main features STM32F37x 38x devices have three embedded Sigma Delta Analog to Digital Converters SDADC They can be synchronized together and each has the following main features e Effective number of bits ENOB equal to 14 bits e b differential input pairs or 9 single ended inputs or a comb
9. C2 AINOP SDADC2 AINOM la SDADC1 AINOP Current sensor 2 Current sensor 1 SDADC1 AINOM MSv31143V1 Doc ID 023945 Rev 1 ky AN4207 Revision history 5 Revision history Table 7 Document revision history Date Revision Changes 13 Dec 2012 1 Initial release Doc ID 023945 Rev 1 27 28 AN4207 Please Read Carefully Information in this document is provided solely in connection with ST products STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections modifications or improvements to this document and the products and services described herein at any time without notice All ST products are sold pursuant to ST s terms and conditions of sale Purchasers are solely responsible for the choice selection and use of the ST products and services described herein and ST assumes no liability whatsoever relating to the choice selection or use of the ST products and services described herein No license express or implied by estoppel or otherwise to any intellectual property rights is granted under this document If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or service
10. SP and standard peripherals library package stm32f37x_dsp_stdperiph_lib On the STM32373C EVAL board The MPX2102A sensor is connected to SDADC1 channel 8P PE8 and channel 8N PE9 The MPX2102A sensitivity when powered by 3 3 V is 3 3 V 40 mV 10 V 18 2 mV 1000 mB 13 2 microV mB To increase the sensitivity an external 45 1 gain is applied using the TVS632 operational amplifier installed on the STM32373C EVAL The same operational amplifier is used to shift down the input voltage by 3 3 V 10 2 0 33 V Table 6 Pressure sensor voltage range Vpp 3 3V Pressure HPa 800 1000 Differential voltage on sensor outputs 10 56 mV 13 2 mV Differential voltage on SDADC inputs 146 256 mV 265 32 mV 1200 15 84 mV 384 384 mV Refer to STM32373C EVAL user manual for more details about how the MPX2102A is connected to PE8 and PE9 The SDADC channel 8 is configured in differential mode The external reference VREF set to 3 3 V on STM32373C EVAL is used as reference for SDADC The conversion is triggered by the TIM19 timer with interrupt enabled on End of Injected Conversion The input voltage is calculated using the formula below inputvoltage InjectedConvData SDADC VREF SDADC RESOL SDADC GAIN OFFSET VOLTAGE Where InjectedConvData The digital value read from SDADC data register SDADC VREF is the sigma delta converter voltage reference set externally to 3 3V SDADC RESOL is th
11. annel must stay within the electrical limits of the device The input range is Vref 2 gain Vref 2 gain and the conversion value is in the range 32767 432767 Doc ID 023945 Rev 1 ky AN4207 Overview of 16 bit SDADC Example For a 1 22V reference voltage and a gain set to 1 the input range is 0 61V The formula is Vin SDADC xx AINyP SDADCx AINyM ReadData Vref 2 x gain x 32767 with ReadData is two s complement read data from the SDADC data register SDADCx_JDATAR or SDADCx RDATAR Figure 2 Input signal range in differential mode SDADCx AINyP SDADCx AINyM Vref 2xgain Vref 2xgain MSv31128V1 Figure 3 shows how to connect a bridge type sensor to the 16 bit SDADC As shown below both positive SDADCx AINyP and negative SDADCx AINyM inputs are connected to sensor outputs Doc ID 023945 Rev 1 7 28 Overview of 16 bit SDADC AN4207 8 28 Figure3 Typical connection of differential sensor to differential channels SDADC_VREF SDADCx_INyP Bridge Sensor SDADCx_INyM STM32F37x MSv31129V1 Single ended offset mode In single ended offset mode conversions are performed by connecting the negative input to O V internally leaving the corresponding pin for the negative input SDADCx_AINyM free to be used for other purposes The signal to be measured is applied to the positive input SDADCx_AINyP This mode of operation is simi
12. e channel p 1 can not be used in single ended mode zero reference mode or offset mode When channel 4 is configured in differential mode channel 5 is automatically used as minus input and therefore channel 5 can not be used either in single ended offset mode or in single ended zero reference mode SDADC voltage references The SDADC reference voltage is selectable among four sources 1 VREFINT1 A 1 2V embedded reference voltage 2 VREFINT2 A 1 8V embedded reference voltage 3 VDDSD The SDADC analog supply voltage It ranges from 2 2 V to 3 6 V 4 VREFSD The external SDADC reference voltage It ranges from 1 1 V to VDDSD The table below shows the voltage weights per bit step size using three possible references Table 2 Voltage step sizes VREFSD pV bit VREINT1 1 2 18 46 VREINT2 1 8 27 69 3 3V 50 35 Doc ID 023945 Rev 1 ky AN4207 Overview of 16 bit SDADC 21 4 Note Calibration In order to get the best performance from the SDADC two parameters should be calibrated These parameters are offset and gain Offset calibration The offset error is a constant value that is added to the ideal conversion value Figure 6 illustrates the offset error The SDADC embedded in STM32F37x 38x devices provides automatic offset calibration without adding external components Its principle can be summarized in the following steps 1 Short internally both channel inputs positive and negative
13. e sigma delta converter resolution 2e16 1 SDADC GAIN is the internal SDADC gain In this example it is set to 4 OFFSET VOLTAGE The offset voltage added by the operational amplifier TVS632 approximately 3 3 V 10 0 33 V And the pressure is calculated using the formula below PressuremB 1000000 inputvoltage MPX2102 SENSITIVITY EXTERNGAIN Doc ID 023945 Rev 1 21 28 Application examples AN4207 4 3 Wave recorder This application shows how to use the 16 bit Sigma Delta Analog to Digital converter to record the human voice using the electric condenser microphone installed on the STM32373C EVAL evaluation board The application source code is available in the Project STM32373C E VAL src waverecorder c file in the STM32373C EVAL demonstration firmware package stm32373c eval fw A microphone is connected to SDADC1 channel 6 PBO through an audio amplifier filter The SDADC is configured in Single Ended Zero Reference mode and voice recording is triggered by TIM13 at a sampling rate of 8 KHz The wave recorder application uses a ping pong buffer one buffer is actively being written in the MicroSD memory card while the second buffer is filled with the new samples Writing access to the MicroSD memeory card uses the open source file system FatFS Figure 12 shows the block diagram of the voice recorder application Figure 12 Block diagram of voice recorder EUR STM32F37x Samisk CPU wth FPU oo nas KO MPU
14. ence mode and conversion is triggered by the TIM3 timer at a sampling rate of 480 Hz The ECG acquisition application uses a ping pong buffer one buffer is actively being filtered using a bandpass filter and then displayed on the LCD while the second buffer is filled with the new ECG samples ECG samples are filtered using the ARM DSP library Figure 14 below shows the block diagram of the electrocardiogram acquisition application Figure 14 Block diagram of the electrocardiogram ECG acquisition application Cortex M4 CPU wth FPU m CA deo AE STM32F37x ECG i i AOP I I 1st buffer 2nd buffer I n TIM13 480 sec MSv31141V1 Doc ID 023945 Rev 1 ky AN4207 Application examples q The flowchart of this application is given in the figure below Figure 15 Flowchart of ECG acquisition application ECG acquisition Init SDADC TIM3 used as trigger DMA Init SDADC Init TIM13 used as trigger Buffer pointer reset Filter the SDADC samples using a BandPass FIR filter Display filtered samples on LCD Reset buffer pointer Stop acquisition Disable acquisition Disable SDADC Disable TIM3 Exit application DMA half complete transfer IRQ Write SDADC sample in selected buffer Is Half Transfer flag set Set buffer Set buffer pointer at 2nd pointer at 1st half half Clear DMA half
15. ent This calibrates the gain The PT100 is not connected in this phase 2 Temperature measurement this phase is performed with JP18 fitted in 1 2 PT100 position The PT100 sensor is connected to PE7 which is connected to VREF through the reference resistor The SDADC converter measures the analog voltage applied on PE7 and then computes the temperature which is given by the following formula TemperaturePT100 DoeffCorrection AvrgRegularConvData SDADC GAIN REFERENCE RESISTOR 2 SDADCRESOL RESISTANCE ZERODEGRE RESISTANCE COEFFICIENT where AvrgRegularConvData is the average value of 256 samples SDADC GAIN is the internal SDADC gain In this example it is set to 8 CoeffCorrection is the correction coefficient computed in phase 1 REFERENCE RESISTOR is the reference resistor 1K8 labeled R33 on STM32373C EVAL SDADCRESOL is the sigma delta converter 2e16 1 RESISTANCE ZERODEGRE is the resistance of PT100 at 0 C RESISTANCE COEFFICIENT is the coefficient of PT100 sensor 20 28 Doc ID 023945 Rev 1 ky AN4207 Application examples 4 2 Note Pressure measurement This application is intended to show how to use the 16 bit sigma delta analog to digital converter to perform pressure measurement using the absolute pressure sensor MPX2102A mounted on the STM32373C EVAL evaluation board The application source code is available in the Project STM32F37x_StdPeriph_Examples SDADC folder in the STM32F37x D
16. ination e High performance data throughput 16 6 ksps input sampling rate when multiplexing between different channels BOksps input sampling rate for single channel operation e Programmable gain x0 5 x1 X2 x4 x8 x16 and x32 e Selectable reference voltage Vppsp 1 22 V 1 8 V and Vpep Clock selection The SDADC clock is supplied by SDADCCLK which divides the system clock SYSCLK by a selectable prescaler 2 4 6 8 10 12 14 16 20 24 28 32 36 40 44 and 48 The typical operating frequency of SDADC is 6 MHz in fast mode and 1 5 MHz in slow mode Example If SYSCLK is set to 72 MHz the SDADC divider should be set to SYSCLK Typical Frequency Fast speed mode prescaler 72 MHz 6 MHz 12 Low speed mode prescaler 72 MHz 1 5 MHz 48 Input modes The SDADC has three possible input modes that can be combined e Differential mode e Single ended offset mode e Single ended zero reference mode Differential mode It is recommended to use differential mode when the sensors being used produce very small signals that are very susceptible to noise This is especially the case when using thermocouple and bridge type sensors pressure sensors In differential mode the SDADC converts the difference between SDADCx AINyP and SDADCx AINyM The result can be either positive or negative depending on which input is at higher voltage The SDADC can not measure negative voltages and the input voltage on each ch
17. lar to differential mode except that the output data is only from O to 432767 and not from 32767 to 32767 therefore half the dynamic range is lost consequently the SNR is degraded The formula is Vin SDADC xx AINyP ReadData Vref 2 x gain x 32767 with ReadData is two s complement read data from SDADC data register SDADCx_JDATAR or SDADCx_RDATAR Doc ID 023945 Rev 1 ky AN4207 Overview of 16 bit SDADC Figure 4 Input signal range in single ended offset mode SDADCx AINyP Vref 2xgain MSv31130V1 Single ended zero reference mode The signal is applied to the positive input SDADCx AINyP and the negative input is set to the signal reference normally O V This mode injects an input common mode of half scale to the ADC thus maintaining the dynamic range the same as in differential mode 32767 to 1432767 In this mode the injected common mode is dependent on gain variations The formula is Vin SDADCx_AINyP ReadData 32767 Vref gain x 65535 with ReadData is two s complement read data from SDADC data register SDADCx_JDATAR or SDADCx RDATAR Doc ID 023945 Rev 1 9 28 Overview of 16 bit SDADC AN4207 Note 10 28 Figure 5 Input signal range in single ended zero reference mode SDADCx AINyP Vref gain MSv31131V1 When channel p with p is even is used in differential mode the channel p 1 is automatically used as minus input SDADCx AINyM and therefor
18. lowing AccRef Output x Vref 65535 The computed gain can be stored in non volatile memory Flash memory and used during acquisition phase Before running gain calibration it is mandatory to run offset calibration Doc ID 023945 Rev 1 ky AN4207 Overview of 16 bit SDADC 4 Figure 8 Gain calibration using the accurate reference voltage Vref SDADC_VREF Sensor Accurate Reference Acquisition phase SDADCx_INyP L I O control Gain calibration phase STM32F37x SDADC_VREF MSv31134V1 Doc ID 023945 Rev 1 13 28 Overview of 16 bit SDADC AN4207 Software procedure for offset and gain calibration The flowchart below shows a typical SDADC application using both offset and gain calibration Figure 9 SDADC software calibration sequence Input voltage acquisition Configure SDADC gain conversion mode channel Run offset calibration Convert the accurate reference Calculate the exact gain value Store the exact gain value in non volatile memory or back up registers Acquire the SDADC input sensor outpout Calculate the input voltage using the exact gain value Stop conversion MSv31136V1 14 28 Doc ID 023945 Rev 1 ky AN4207 Overview of 16 bit SDADC 2 1 5 Matching impedance The impedance of the analog signal source or series resistance Ray between the source and the MCU pin may lead to
19. ntents AN4207 Contents 1 Basics of sigma delta converters eee 5 2 Overview of 16 bit SDADC 0 cece eee 6 2 1 Main features 0 000 6 24 1 Clock selection 2 esee reeet a Oe ene Bw POR RR 6 2 1 2 Input modes Rr nn 6 2 1 3 SDADC voltage references leere 10 2 1 4 Calibration 2 4 244 vede bec ador enc edi DAANAN Pak 11 2 1 5 Matching impedance eren 15 2 1 6 Low power modes e rn 16 3 Sigma delta SD vs successive approximation register SAR analog to digital converters 17 4 Application examples eeeeelleeeeeese 19 4 1 Temperature measurement 00000 e eee eee 19 4 2 Pressure measurement 0c eee ee eens 21 4 3 Wave recorder 2 sardaccks dene pack RR REIP REN AG digas Fenda 22 4 4 ElectroCardioGram ECG acquisition 0 cee eee eee 24 4 5 Power meter application llli 26 5 REVISION history aa a a RR eee ee a ee DR D eo 27 2 28 Doc ID 023945 Rev 1 ky AN4207 List of tables List of tables Table 1 Applicable products suse sex see BA NA KIRA icm PT e doa acce re 1 Table 2 Voltage step sizes el urn 10 Table 3 Typical SDADC input channel input impedance a 15 Table 4 SDADC vs SAR ADC feature comparison liliis ees 18 Table 5 Temperature sensor voltage range 20 Table 6 Pressure sensor voltage range rn 21
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22. tectures comparing their resolution and sampling rate Figure 11 ADC architecture vs resolution and sampling rate 24 Sigma Delta g c 2 3 9 16 0 Y 12 8 100k 5M 5G Sample rate sample s MSv31138V1 The STM32F37x 38x devices have two types of embedded ADCs 12 bit SAR ADC and 16 bit SDADC The Table 4 summarizes the differences between the two types of ADC Doc ID 023945 Rev 1 17 28 Sigma delta SD vs successive approximation register SAR analog to digital converters Table 4 SDADC vs SAR ADC feature comparison Feature SDADC SAR ADC Max sampling rate 50 Ksps 1 Msps Resolution 16 bits 12 bits Input mode Single ended differential Single ended Embedded gains 0 5x to 32x No 5 differential input pairs or 9 single ended inputs 16 single ended inputs Number of channels Number of instances 3 with synchro capability 1 Automatic Offset calibration Yes Yes Analog watchdog No Yes Ti Software Software Aa KA Start of conversion of another Embedded timers conversion SDADC External events Software Trigger sources for injected Einbeddea timers aware conversion External events Embedded timers Start of conversion of another External events SDADC Input range Vrer VREF 1 22 V Reference voltage oy V g VDDSD REF VREFSD Input impedance 47 KQ to 540 KQ 125 KQ to 2500 KQ 1 The sampling rate is 50
23. this application the SDADC internal gain is set to 8 so the range is from 0 V to Vpgp 16 The external reference Vpep set to 3 3V on STM32373C EVAL is used as reference for SDADC using JP17 so the measurement ranges between 0 V and Vpgp 16 0 20625V The conversion is performed in continuous mode with interrupts enabled on End o Regular Conversion The temperature is computed using the formula below Rpt100 100 0 385 T T Rpt100 100 0 385 Vpt100 Rpt100 Ipt100 Rpt100 VDD ANA 2 Rref Rpt100 Vpt100 1800 2 VDD ANA T Vpt100 1800 2 VDD ANA 100 0 385 where Rpt100 is the resistance of the PT100 sensor Vpt100 is the voltage measured on PT100 sensor Ipt100 is 1mA current crossing the PT100 sensor VDD ANA is the analog voltage Rref is the reference resistor 1K8 labeled R33 on STM32373C EVAL Doc ID 023945 Rev 1 19 28 Application examples AN4207 Table 5 Temperature sensor voltage range Vpp 3 3V Temperature Resistance C Voltage mV 0 100 91 667 Rref 1 8K 20 107 7 98 725 50 119 2 109 2667 The temperature measurement is performed in two steps 1 Temperature sensor calibration this phase is performed with JP18 fitted in 2 3 REF position A 100 Ohm resistor is connected to PE7 which is connected to VREF through the reference resistor The SDADC converter measures the analog voltage applied on PE7 and then computes the correction coeffici
24. this mode the SDADC consumes a maximum of about 2 5 pA but a stabilization time of 600 SDADC clock cycles 100 us 6 MHz is required each time it exits from Standby mode 16 28 Doc ID 023945 Rev 1 ky AN4207 Sigma delta SD vs successive approximation register SAR analog to digital convert 3 Sigma delta SD vs successive approximation register SAR analog to digital converters Analog to digital converters come in different architectures to be able to address the needs of different applications The main types available in the market are Successive approximation register SAR ADC Successive approximation register SAR analog to digital converters ADCs are frequently used in embedded systems with sample rates of less than 5 megasamples per second Msps Their resolution ranges from 8 to 16 bits This type of ADC is used in industrial control applications Sigma delta ADC SDADC Sigma Delta analog to digital converters ADCs are used in lower speed applications requiring high resolution The resolution may attain 24 bits by oversampling but the sampling rate is limited to only a few ksps Flash ADC Flash analog to digital converters are the fastest type of analog to a digital converter They are suitable for applications requiring a very high sampling rate However flash converters have low resolution 12 bits This type of ADC is used in oscilloscopes The Figure 11 gives an overview of the different ADC archi
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