TLV320DAC3202 - Texas Instruments
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1. 0 5 10 100 1000 10000 100000 f Frequency Hz f Frequency Hz Figure 7 Figure 8 Copyright 2010 2012 Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Link s TLV320DAC3202 TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 Audio Interface The audio interface for data communication with application processor or modem supports multiple formats such as 125 left justified right justified or the short frame sync PCM formats The default interface format is 125 at 48 kHz sampling rate and 16 bit data size The clock input selection module within PLL block also supports multiple input frequency options The input clock must be in standard square wave format hence a clock squarer is not DIGITAL INTERFACE TEXAS INSTRUMENTS www ti com necessary The following tables shows the details of audio interface configuration through I C register controls Table 4 Audio Interface Format Configuration Register INTF_MODE 1 0 INTERFACE FORMAT TYPE 0 0 Standard 125 0 1 Left justified 125 1 0 Right justified 125 1 1 Short PCM Table 5 Audio Interface BCLK to WCLK Ratio Setting Register INTF FRAME SIZE 2 0 INTF SIZE 1 0 SI2. TEXAS INSTRUMENTS TLV320DAC3202 www ti com SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 LOW POWER HIGH FIDELITY 5 INPUT HEADSET IC Check for Samples TLV320DAC3202 FEATURES 32 Step Volume Control from 4 59 dB Ground Referenced Free Class G e Clocking Internal Clock Derived from 5 Stereo Headset Driver BCLK Capable of Driving 1 VRMS at the Headset Package WCSP 0 5 mm Pitch 2 mm x 2 5 mm Driver Output Per Channel in Phase Power Supply Direct Battery and IO Supply 100 dB A Channel SNR With 6 5 mW of Quiescent Power Dissipation APPLICATIONS Built In Short Circuit Protection for Preventing Smart Phones and Music Phones Supply Rails Overload Portable Navigation Supports 8 11 025 12 16 24 32 44 1 Personal Media Players and 48 kHz Sample Rates PDAs 1 Interface for Digital Control Portable Game Consoles Supports 16 20 24 and 32 Bit Data Width HDD and Flash Based Portable Audio Players Supports Standard 125 PCM Left and Right Justified Formats Supports Data Mixing With Gain Options DESCRIPTION The TLV320DAC3202 is a high fidelity and low power headphone amplifier with integrated DAC and power rails The small solution size and highly efficient operation maximizes battery life and performance The digital audio interface supports industry standard formats such as 125 and PCM Many features of this device such as volume setting
3. DIN MSB LSB 45 LEFT CHANNEL RIGHT CHANNEL PCM Short Frame Sync E 1 fs Figure 9 Interface Format Supporting Four Different Options WCLK short WCLK long 4 Tbcik gt lt Tbclkh gt 4 gt BCLK DIN Figure 10 Interface Timing for 125 Long or PCM Short WCLK Options 10 Submit Documentation Feedback Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 TEXAS INSTRUMENTS TLV320DAC3202 www ti com SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 AUDIO Channel Performance The receive channel of TLV320DAC3202 converts the digital signal to analog for the headset amplifier through a highly efficient low power DAC The signal in stereo 125 format with configurable data size drives the Class G amplifier after the conversion The channel gain is implemented in two segments in digital and analog domains In digital domain the gain steps have finer resolution whereas in the analog domain the amplifier gain steps are defined at 2 dB resolution The detail of volume control is shown in the register map description The mixing feature allows the left and right channels to be combined in digital domain prior to conversion and then routed to either channel The audio signal can be disabled either by soft mute feature in the digital domain or by disabling the output amplifier DIN HSOUTL WCLK BCLK HSOUTR HSRDAC Figure 11 Audio Path Diagram Volume
4. HIZ_L HIZ_R 0x00 WR 0x04 ASICREV ASICID 3 0 VERSION 3 0 0x00 R 0x05 I2CID I2CID 7 0 0x34 R HS LP2HP HS BYPASS 0x06 swt HS LP MODE CUR SW HSL_CUR_THRD 1 0 HSR_CUR_THRD 1 0 0x00 WR 0x07 CODEC_EN HSL_DRV_EN HSR_DRV_EN CP_EN PLL_EN REF_EN DACL_EN DACR_EN 0x00 w 0x08 CODEC CTRL HSL FIR EN HSR FIR EN dui d HSL MIX CTRL 1 0 MIX CTRL 1 0 0x00 WR 0x09 INTF INTF MODE 1 0 INTF DATA SIZE 1 0 INTF FRAME SIZE 2 0 0x00 WR 0x0A FIR CLK MODE 3 0 INTERPOLATION 1 0 OxA3 WR 0x0B CP CP_OPEN CP_HPMODE CP_ENCLAMP CP_FET_SIZE 2 0 0x00 WR 0x0C REF REF_CM_HIGH_SWING 1 0 REF_CUR 3 0 0x00 WR 0x0D DAC DAC_INV_CLK 1 DACR_SWING DACL_SWING DACR_LP DACL_LP 0x00 WR HS_LP2HP HP_LOW HS_BYPASS OxOE swe IBIAS HS_SW_OVER_SPEED 1 0 HS_AMP_SW_OVER 1 0 HS_HIGHAMP_SW_OVER 1 0 0x80 WR 0x11 PM_EN REFSYS_EN SPARE_W VANA_EN VPOW_EN 0x00 w 0x12 PM_LDO VPOW_OUT 1 0 VANA_OUT 1 0 0x00 WR 0x18 UNLOCK_PM UNLOCK_PM 0x00 WR TEST_REFSYS EEPROM TEST_VANA TEST_VPOW EEPROM DIEID 0x19 BG _BYPASS SPARE _ 2 _HIZ _PROGRAM _PROGRAM 0x00 WR TEST HSL TEST HSL TEST ISUM TEST HSR TEST HSR Ox1A HS TEST SPARE SPARE TMI OCDIS TEST DC2DAC DETECT _TM1 _OCDIS 0x00 WR 0x1B CODEC_TEST1 CODEC_TEST_MUX 3 0 TEST_BYP_FIR TEST_CP_CLK 2 0 0x00 WR TEST_BYP TEST TEST PLL 0x1C CODEC_TEST2 MOD _ RANDOMIZER OVERRIDE EN PLL PRE DIV OVR 4 0 0x00 WR 0
5. 16 44 100 1411 2 2822 4 64 16 48 000 1536 3072 80 20 8 000 320 640 80 20 11 025 441 882 80 20 12 000 480 960 80 20 16 000 640 1280 80 20 22 050 882 1764 80 20 24 000 960 1920 80 20 32 000 1280 2560 80 20 44 100 1764 3528 80 20 48 000 1920 3840 96 24 8 000 384 768 96 24 11 025 529 2 1058 4 96 24 12 000 576 1152 96 24 16 000 768 1536 96 24 22 050 1058 4 2116 8 96 24 24 000 1152 2304 96 24 32 000 1536 3072 96 24 44 100 2116 8 4233 6 96 24 48 000 2304 4608 128 32 8 000 512 1024 128 32 11 025 705 6 1411 2 128 32 12 000 768 1536 128 32 16 000 1024 2048 128 32 22 050 1411 2 2822 4 128 32 24 000 1536 3072 128 32 32 000 2048 4096 128 32 44 100 2822 4 5644 8 128 32 48 000 3072 6144 Copyright 2010 2012 Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link s TLV320DAC3202 TLV320DAC3202 2 UMEN SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 www ti com Q WCLK LEFT CHANNEL RIGHT CHANNEL ow X X Left Justified Mode wcLK LEFT Q2 f DIN MSB X X X_LSB MSB Right Justified Mode WCLK id in n 4 RIGHT CHANNEL 2527272 a DIN MSB X M X ts n MSBX X OC SN S Mode WCLK N LaS A
6. 3 V to 4 8 V battery input close to the ball Minimize the resistance path with adequate decoupling very NEON Gr BBO pulpit close to the ball Connect to separate GND plane for noisy signals i e PLL DVSS Digital ground and interfaces Connect the two planes in a single point to avoid GND loop CFLYN FLY capacitor terminal Connect to negative side of output capacitor with lt 10 mQ 2 Keep this away from clean quite signal paths over the digital SDA I C data GND plane 2 Keep this away from clean quite signal paths over the digital SCL CLK in GND plane Trace impedance must be very small lt 60 mQ This is HSOUTG HS feedback ground important for cross talk reduction Connection to GND plane must be at IC ball HSVDD HS positive supply Decouple this path to DVSS with trace impedance of 20 mQ Must be routed in differential pair with GNDHS to the HSOUTL HS output left connector Match the impedances and as small as possible DIN 25 downlink data Keep this trace away from quite GND signal traces WCLK 25 word clock Keep this trace away from quite GND signal traces BCLK 125 bit clock Keep this trace away from quite GND signal traces Must be routed differential pair with GNDHS to the HROUTR HS output right connector Match the impedances and as small as possible HSVSS HS negative supply 2 this path to DVSS with trace impedance of Copyright 2010 2012 Texas Instruments Incorporated Submit Documentation Fe
7. 32 0 HEADSET TIME ms Figure 3 TOTAL HARMONIC DISTORTION NOISE vs HEADPHONE OUTPUT POWER WITH 32 0 HEADSET 10 20 30 40 50 60 70 80 90 0 5 10 15 20 Headphone Output Power mW Figure 5 Submit Documentation Feedback TEXAS INSTRUMENTS www ti com DAC TO HEADSET FFT AT 3 dBFS WITH 16 HEADSET o 20 40 t 60 o 5 E 80 120 140 0 5000 10000 15000 20000 f Frequency Hz Figure 2 CLICK AND POP PERFORMANCE WITH 16 HEADSET 1 0 75 0 5 N a o N a Amplitude mV a o a a 7 5 0 5 10 TIME ms Figure 4 TOTAL HARMONIC DISTORTION NOISE vs HEADPHONE OUTPUT POWER WITH 16 Q HEADSET 10 20 30 40 50 60 70 80 90 0 5 10 15 20 Headphone Output Power mW THDN dB Figure 6 Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 TEXAS INSTRUMENTS TLV320DAC3202 www ti com SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 FREQUENCY RESPONSE SAMPLING FREQUENCY 48 kHz CHANNEL SEPARATION 0 5 0 4 0 3 0 2 0 1 Amplitude dB 0 1 0 2 0 3 Right Channel Amplitude dBr 0 4
8. Control The volume control module is implemented with combination of digital and analog gain settings for optimum performance The total gain range is from 4 dB to 59 dB with variable steps The gain for the amplifiers is from 4 dB to 12 dB in 2 cB steps Table 8 Volume Control Register Decoding REGISTER VALUE GAIN dB GAIN ANALOG dB GAIN DIGITAL dB 31 4 4 0 30 3 4 1 29 2 2 0 28 1 2 1 27 0 0 0 26 1 0 1 25 2 2 0 24 3 2 1 23 4 4 0 22 5 4 1 21 6 6 0 20 7 6 1 19 8 8 0 18 9 8 1 17 10 10 0 16 11 10 1 15 13 12 1 14 15 12 3 13 17 12 5 12 19 12 7 11 21 12 9 Copyright 2010 2012 Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link s TLV320DAC3202 TLV320DAC3202 gi SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 www ti com Table 8 Volume Control Register Decoding continued REGISTER VALUE GAIN dB GAIN_ANALOG dB GAIN_DIGITAL dB 10 23 12 11 9 25 12 13 8 27 12 15 7 31 12 19 6 35 12 23 5 39 12 27 4 43 12 31 3 47 12 35 2 51 12 39 1 55 12 43 0 59 12 47 SYSTEM AND CONTROL Power Up Sequence The power up sequence of the IC is initiated by asserting the CHIP EN bit to logic 1 It is expected that Vgar and Vio are powered up prior to assertion of this bit The
9. HSL R amplifiers are then enabled by writing to their perspective control bits in register address 0x01 125 clock must be present prior to power up sequence and maintain its activity during active mode The figure below shows the typical power up sequence of the IC The IC power up state machine updates 2 register bits corresponding to enabled modules register control can subsequently be used to turn OFF unused circuits The power down sequence is initiated by de asserting the CHIP EN bit in CODEC EN register It is expected that the CHIP EN bit is de asserted prior to turning OFF the Vio supply The HS driver power on off sequence is designed to be click pop free AVDD Wake up Time HSL R EN 1 Figure 12 Power Up Sequence Timing Active State 12 Submit Documentation Feedback Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TL V320DAC3202 PT I DENTS TLV320DAC3202 www ti com SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 Dual Supply Charge Pump The charge pump on TLV320DAC3202 has dual supply capability module with automatic selection which can be either from Vgat or depending on the input signal range and load current that is detected Charge pump generates both the positive and negative rails for low and high headset rails For typical listening range where the signal level is low the supply is expected to be from and headset rail is 0 9 V For higher signal leve
10. data width and sampling rate are configurable for optimum flexibility and efficiency The headset power control automatically adjusts the rail voltage based on the input signal to maximize efficiency and performance The control interface uses an industry standard 1 C controller for ease of operation and reduction in device pin count Table 1 ORDERING INFORMATION TA PACKAGE ORDERABLE PART NUMBER Tape and reel of 250 TLV320DAC3202CYZJT 30 C to 85 C YZJ Tape and reel of 3000 TLV320DAC3202CYZJR 1 Forthe most current package and ordering information see the Package Option Addendum at the end of this document or see the TI web site at www ti com 2 While this part number includes the YZJ package designator it does not conform to the standard YZJ footprint Only the drawings below should be used for system design and not the YZJ drawing available from the TI Packaging website Top View Bottom View 1 2 3 4 5 5 4 3 2 1 OOO aoo 60161910 Please be aware that an important notice concerning availability standard warranty and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet PRODUCTION DATA information is current as of publication date Copyright 2010 2012 Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warr
11. 0 times over 7 years lifetime RECOMMENDED OPERATING CONDITIONS over operating free air temperature range unless otherwise noted MIN NOM MAX UNIT Ta Operating free air temperature 30 85 Tstg Storage temperature 55 150 ELECTRICAL CHARACTERISTICS AVDD 3 7 V DVDD 1 8 V T 25 C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD Functional only 2 3 4 8 Vear Parametric performance 2 3 4 8 DVDD Vio 1 65 1 8 1 95 Vins 0 65 x digital Vio 0 35 digital Vo V Enabled 1 5 1 5 HSOUTL R Voltage V Disabled HiZ 1 8 Power consumption from No load 6 5 all supplies with internal mW PLL 0 1 mW channel 1 kHz 32 Q 9 7 SNR 100 dBA 1 CHIP EN 1 HSLEN 1 HSREN 1 active S idle channel amplifiers muted Copyright O 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 Submit Documentation Feedback 3 TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 www ti com ELECTRICAL CHARACTERISTICS continued AVDD 3 7 V DVDD 1 8 V T 25 C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AVDD GND mode 2 2 DVDD GND mode 2 Shutdown current 3 uA AVDD HiZ mode 1 DVDD mode 1 Fr
12. Dimension designed to accommodate the component thickness Y Overall width of the carrier tape Pitch between successive cavity centers Reel Width W1 QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE O O O 0 O O 00 O Sprocket Holes Q1 Q2 Q1 Q2 Q3 Q4 Q3 Q4 User Direction of Feed Pocket Quadrants All dimensions are nominal Device Package Pins SPQ Reel Reel AO BO KO P1 w Pin1 Pack Materials Page 1 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 17 Jun 2015 TAPE AND REEL BOX DIMENSIONS All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length mm Width mm Height mm TLV320DAC3202CYZJR DSBGA YZJ 20 3000 182 0 182 0 20 0 Pack Materials Page 2 MECHANICAL DATA YZJ R XBGA N20 DIE SIZE BALL GRID ARRAY L PIN A1 INDEX AREA 919 0 0156 c sex t 4205061 E 07 13 NOTES All linear dimensions are in millimeters B This drawing is subject to change without notice C NanoFree package configuration NanoF ree is a trademark of Texas Instruments 35 TEXAS INSTRUMENTS www ti com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections enhancements improvements and other changes to its semiconductor products and services per JESD46 latest issu
13. Input VIO 25 downlink data 2 Submit Documentation Feedback Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 TEXAS INSTRUMENTS www ti com Table 3 TERMINAL FUNCTIONS continued TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 TERMINAL VOLTAGE DESCRIPTION NAME NO LEVEL V HSOUTR D4 Output 1 5 Headset output right HSVSS D5 Input Output 1 95 Headset negative supply ABSOLUTE MAXIMUM RATINGS All voltages values are with respect to GND Over operating free air temperature range unless otherwise noted VALUE UNIT AVDD Vaan DC 0 3 to 5 V 0 3 to 5 5 DC 0 3 to 2 1 DVDD Tac 0 3 to 2 2 Ta Operating free air temperature 40 to 85 C Ty Maximum junction temperature 125 C Tstg Storage temperature 65 to 150 C Lead temperature 115 C Human Body Model 2000 to 2000 ESD rating all pins 7 V Charged Device Model 500 to 500 1 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied Exposure to absolute maximum rated conditions for extended periods may affect device reliability 2 For spike duration of 1 ms 10 00
14. TERFACE The control interface for programming the registers on TLV320DAC3202 is done using a standard interface with the IC operating in slave mode The 2 modes of operation as defined in Ref 1 2 are a Standard mode up to 100 kbit s and b Fast mode up to 400 kbit s The IC defaults to fast mode A 7 bit slave addressing is used The device 2 slave address is fixed to 0011010X with 00110100 for master write cycle TLV320DAC3202 reads and 00110101 for master read cycle TLV320DAC3202 writes For data and clock lines pull up resistors are required and are expected to be provided as defined in section 7 of Ref 1 References 1 UM10204 I C Bus Specification and user manual Rev 03 19 June 2007 2 The PC BUS SPECIFICATION VER 2 1 January 2000 3 25 Bus specification Phillips Semiconductors June 1996 Copyright O 2010 2012 Texas Instruments Incorporated Submit Documentation Feedback 13 Product Folder Link s TLV320DAC3202 TLV320DAC3202 P ie omens SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 www ti com Register Map Table 10 Register Map Designation for I C Interface INITIAL ACCESS ADDRESS REGISTER D7 D6 D5 D4 D3 D2 D1 DO VALUE R W WR 0x00 0x01 EN HSL_EN HSR_EN THERMAL CHIP_EN 0x00 R 0x02 VOL_CTRL HSL_MUTE HSR_MUTE VOLCTRL 4 0 0xCO WR 0x03 HIZ_CTRL SPARE SPARE
15. ZE 0 0 0 0 0 2x 16x Fs 0 0 1 0 1 2 x 20x Fs 0 1 0 1 0 2 x 24 x Fs 0 1 1 1 1 2 x 32 x Fs 1 0 0 0 0 4x 16 x Fs 1 0 1 0 1 4 x 20 x Fs 1 1 0 1 0 4 x 24 x Fs 1 1 1 1 1 4 x 32 x Fs Table 6 Audio Sampling Rate Setting Register CLK_MODE 3 0 INTERFACE SAMPLING RATE WCLK kHz 0 0 0 0 8 0 0 0 1 11 025 0 0 1 0 12 0 0 1 1 0 1 0 0 16 0 1 0 1 22 05 0 1 1 0 24 0 1 1 1 1 0 0 0 32 1 0 0 1 44 1 1 0 1 0 48 1 0 1 1 1 1 0 0 Table 7 Detailed Configuration of Interface Including PLL Setup Registers BCLK WCLK DATA SIZE F WCLK F x DATA BCLK PLL INPUT 32 16 48 000 1536 1536 40 20 48 000 1920 1920 48 24 48 000 2304 2304 64 32 48 000 3072 3072 8 Submit Documentation Feedback Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 TEXAS INSTRUMENTS www ti com TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 Table 7 Detailed Configuration of Interface Including PLL Setup Registers continued BCLK WCLK DATA SIZE F WCLK F x DATA BCLK PLL INPUT 32 16 44 100 1411 2 1411 2 40 20 44 100 1764 1764 48 24 44 100 2116 8 2116 8 64 32 44 100 2822 4 2822 4 64 16 8 000 256 512 64 16 11 025 352 8 705 6 64 16 12 000 384 768 64 16 16 000 512 1024 64 16 22 050 705 6 1411 2 64 16 24 000 768 1536 64 16 32 000 1024 2048 64
16. anty Production processing does not necessarily include testing of all parameters TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 FUNCTIONAL BLOCK DIAGRAM TEXAS INSTRUMENTS www ti com SCL SDA HSLOUT HSOUTG DIN WELK HSROUT BCLK HSRDAC Internal Clocks VANAG VANA T LTT TTT TTT I o az 0 5 EZ 28228 a gt oor PIN ASSIGNMENTS Table 2 PIN ASSIGNMENTS TOP VIEW 1 2 3 4 5 A AVSS VANAG VANA CFLYP CFLYN B VREF AVDD VPOW DVDD DVSS SDA SCL HSOUTG HSVDD HSOUTL D BCLK WCLK DIN HSOUTR HSVSS Table 3 TERMINAL FUNCTIONS TERMINAL VOLTAGE 1 0 DESCRIPTION NAME NO LEVEL V AVSS Al Input 0 Analog ground VANAG A2 Input 0 Leave floating VANA A3 Output 1 55 Analog LDO output CFLYP A4 Input Output 1 95 FLY cap terminal CFLYN 5 Input Output 1 95 FLY cap terminal VREF B1 Output 0 75 Analog reference output AVDD B2 Input VBAT 2 3 V to 4 8 V battery input VPOW B3 Output 1 95 VPOW LDO output DVDD B4 Input VIO 1 8 V IO digital supply DVSS B5 Input 0 Digital ground SDA Input Output VIO Data SCL C2 Input VIO CLK in HSOUTG C3 Input 0 Headset feedback ground HSVDD C4 Input Output 1 95 Headset positive supply HSOUTL C5 Output 1 5 Headset output left BCLK D1 Input VIO 25 bit clock WCLK D2 Input VIO 125 word clock DIN D3
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19. edback 15 Product Folder Link s TLV320DAC3202 TLV320DAC3202 Ip TEXAS INSTRUMENTS SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 www ti com TYPICAL CIRCUIT CONFIGURATION S wi o o 8 a Figure 13 Typical Circuit Table 12 External Component List PIN NAME DESCRIPTION AVDD 2 2 UF 6 3 V tolerance VPOW 2 2 UF 6 3 V tolerance VREF 2 2 UF 6 3 V tolerance VANA 1 uF 6 3 V tolerance HSVDD 2 2 UF 6 3 V tolerance HSVSS 2 2 uF 6 3 V tolerance CFLYP N 2 2 UF 6 3 V tolerance DVDD 2 2 UF 6 3 V tolerance 1 The headset amplifiers output power and distortion are characterized using the nominal capacitance for the supply ground output loads and the charge pump fly cap as shown in the above application diagram To meet the stated performance with discrete component variations it is recommended that the external components be chosen to account for manufacturing tolerance voltage and temperature de rating 16 Submit Documentation Feedback Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 ip TEXAS PACKAGE MATERIALS INFORMATION INSTRUMENTS www ti com 17 Jun 2015 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS Mpapa Reel Diameter Dimension designed to accommodate the component width BO Dimension designed to accommodate the component length
20. ls where higher current drains from are not possible the IC uses an automatic input voltage and load current threshold based algorithm to switch ON the Vpow regulator and use Vpow which is powered from It is designed to power the left and right headset drivers up to rated full scale output The threshold point to transition between the low and high power range can be programmed through 2 interface There are two threshold points controlled by register bits one for each of left and right channels The threshold monitor mechanisms for each channel can be independently enabled and programmed The load current threshold settings can be 10 5 mA 11 5 mA 12 5 mA default or 13 5 mA per channel Output Impedance In order to share the output connector between audio and other signals such as video output a high impedance option is implemented that can be enabled through I C controller In this mode the output impedance is increased while the signal is muted As shown in below table the output impedance is large enough to avoid an unwanted attenuation of other signal connected to the jack contact Table 9 Output Impedance in Various Mode Settings CHIP EN HiZ HS EN IMPEDANCE MODE 0 0 0 1500 Shut down 0 0 1 1500 Shut down 8 5 O at 40 kHz 0 1 0 600 O at 6 MHz HiZ 400 at 13 MHz 0 1 1 Invalid 1 0 0 1500 Active HS off 1 0 1 Active 1 1 0 Invalid 1 1 1 Invalid IN
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22. om CHIP_EN assertion to Florin reaching Standby Startup time state clock and power supplies available 198 ME From HSL R EN assertion to Florin reaching Active Wake up time state during which the system is completely 3 ms powered up with headset drivers enabled AUDIO PATH ELECTRICAL PERFORMANCE Maximum amplitude at 0 dB PCM 1 kHz THD 1 ball 32 Q load 4 dB gain 1 09 Vrms 32 0 load 0 7 Amplitude across load Vrms 16 Q load 0 45 0 5 Dynamic range 1 kHz 60 dBFs A weighted 97 100 dB A Pour 20 mW 68 1 kHz 16 Q load in series THD N with 10 Rey Pour 12 mW 70 74 dB Pour 4 mW 72 Frequency response 20 Hz to 20 kHz 0 25 0 25 dB Channel separation 1 kHz full scale input 90 95 dB PSRR 217 Hz 500 mVpp ripple on AVDD 80 90 dB Pop noise specification Maximum DC value after power up 05 mV RECEIVE CHANNEL DIGITAL FILTER PERFORMANCE F 44 1 kHz or 48 kHz HPF 3 dB corner 0 8 Hz LPF pass band corner frequency 10 dBF 5 0 42 F Hz LPF pass band ripple 0 25 0 25 dB LPF 3 dB corner 0 48 Hz LPF interpolation 8 multiplier LPF magnitude response lt 0 16 Fs 0 05 0 05 dB LPF stop band corner frequency 0 6 Fs Hz LPF stop band attenuation lt 2Fs 70 dB Filter only at 1 kHz without HPF Absolute delay Excludes interface compute latency 7 AUDIO INTERFACE TIMING PARAMETERS Audio clock period Variable BCLK 1 BCLK ns 0 35 x Tbcikh BCLK high duration BCLK ns period 0 35 x Teck BCLK low duration BCLK n
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24. s period Data hold time following BCLK falling edge ed ER CHIP EN 0 HIZ L2 0 HIZ R 0 CHIP EN 0 HIZ L 1 HIZ 1 The maximum board resistance should be less than 250 mQ between the HSOUTL HSOUTR pins and the HSOUTG pin Maximum slew rate AV At 5 V s after A weighting GEGE Submit Documentation Feedback Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 TEXAS INSTRUMENTS www ti com TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 ELECTRICAL CHARACTERISTICS continued AVDD 3 7 V DVDD 1 8 V T 25 C unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP UNIT Sample clock setup time Trs following BCLK falling 10 ns edge 0 2 x Data set time before Tas BCLK rising edge d ns Data hold time after BCLK 02x Tan rising edge 2 i Short frame sync pulse Toss idih ync p 1 BCLK ns Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 Submit Documentation Feedback 5 TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 TYPICAL PERFORMANCE CHARACTERISITICS Amplitude dBr Amplitude mV THDN dB 0 75 0 5 0 25 0 0 25 0 5 0 75 1 5 0 5 10 DAC TO HEADSET FFT AT 3 dBFS WITH 32 0 HEADSET 10000 f Frequency Hz Figure 1 CLICK AND POP PERFORMANCE WITH
25. x1D CODEC_TEST3 SPARE PLL FB LOOP OVR 6 0 0x00 WR Ox1E CODEC_TEST4 CP TEST 1 0 PLL TEST MODE 1 5 0 0x30 WR Ox1F CODEC_TEST5 PLL TEST MODE H 7 0 0x00 WR 14 Submit Documentation Feedback Copyright 2010 2012 Texas Instruments Incorporated Product Folder Link s TLV320DAC3202 TEXAS INSTRUMENTS www ti com TLV320DAC3202 SLAS726B SEPTEMBER 2010 REVISED MARCH 2012 PCB DEVELOPMENT The following table explains the PCB recommendations In addition it is recommended to split the ground plane into analog and digital segment for clean and noisy signals They should be connected only in a single point to avoid ground loop Table 11 PCB Recommendations BALL NAME DESCRIPTION LAYOUT RECOMMENDATIONS AVSS Analog ground VANAG Connected to VANA via capacitor Connect to output capacitor with lt 10 mQ VANA Analog LDO output Connect to output capacitor with lt 10 mO 2 Minimize the resistance path with adequate decoupling very DVDD IO Digital supply close to the ball CFLYP FLY capacitor terminal Connect to positive side of output capacitor with lt 10 mQ Connect to AVSS via output capacitor The capacitor trace on the AVSS side of the capacitor should not be connected to Analog reference output GND plane directly but at the AVSS pin See application diagram _ Minimize the resistance path with adequate decoupling very AVDD 2
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