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ST2205U Integrated Microcontroller

1. 64 18 Universal Serial Bus USB ac 66 18 2 USB Control Status Registers sico ains ceda ciencias 67 192 1 USB Nae ENT 67 18 22 USB Interrupt Control Register aieo oim deese casos oir aires 67 18 2 3 USB Interrupt Request Register 68 18 2 4 USB Buller Status Reg ds 68 19 2 5 Control Regist ecserin E 69 18 2 6 EndpointO OUT Buffer Data Length Register ccccccccooconcccnnnccccononncnnnnnnnnnonnnnnnnnononnnnnnnnnnnnnnnnnnnnnnnnnnnnnannnennnnnns 69 18 2 7 Bulk IN OUT Endpoints Control Register oooocccccccccccconnccnnnccnononnnonnnnnonononnnnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnonnnnnnnnnnnnnnns 69 18 2 8 Bulk OUT Endpoint Data Length RFegister 5 lean aO aida ninia 70 19 DIRECT MEMORY ACCESS iia 71 71 192 Vel OMIA Pointer Registar m 71 DMA Bank Register iria 71 191 3 DMA ED RN 72 19 1 4 DMA Register Select 00 sanas
2. 9 919 A AA 9 1 9 m 9 6 09 A 6 Y A A TD O ED A X A X _ t0 eo m fte 0 FIGURE 15 2 LCD Interface Timing for 1 4 Bit Data 50 87 ST2205U and 4 bit are supported for most monochrome LCD panels Refer to FIGURE 15 2 for both 1 and 4 bit interface timing ST2205U 15 4 Control Registers 15 4 1 LCD Screen Starting Address Register The LCD screen starting address register LSSA 15 used to inform the starting address of current display buffer Different LCD frames be switched quickly by simply modifying content of LSSA The LCD controller will start fetching pixel data from system memory at this address TABLE 15 3 LCD Screen Starting Address Register Address R W Bit 7 15 Bit 6 14 Bit 5 13 Bit 4 12 Bit 3 11 Bit 2 10 Bit 1 9 Bit0 8 Default 040 LSSAL SSA 6 SSA b SSA 3 SSA 0 0000 0000 041 LSSAH W SSA 15 SSA 14 SSA 13 SSA 12 SSA 11 SSA 10 SSA 9
3. LEN LEN S LEN 2 LEN 1 LEN O 000 0000 Note 1 Undefined bytes and bits should not be used Do not use read modify write instructions RMBx and SMBx to register bits with different functions of read and write operations 7 3 Interrupt Bank Register Logical addresses of interrupt vectors are all in the banked is met That is the interrupt vectors and service routines will all area of PRR Usually several program banks share the same runs in an interrupt bank and then back to the original program interrupt routines The IRR is another bank register which has bank after current interrupt is finished Operation of IRR is the same banked area of PRR and takes place of PRR when controlled by IRREN of SYS Like PRR does IRR can also an interrupt occurs This replacement lasts until instruction RTI refer to internal 16KB RAM by setting bit15 TABLE 7 3 Bank Registers and Addressable Range 30 IRRL RW IRR 7 IRR 6 IRR 5 IRR 4 IRR S IRR 2 IRR 1 IRR O 0000 0000 31 RW IRRIS IRR H IBRR T0 IRR 9 IRR 8 0 0000 Bit 0 11 IRR 0 11 12 bit IRR bank register Bit 15 IRR 15 Internal RAM mapping control O IRR refers to banked area 1 IRR refers to the internal 16kB RAM TABLE 7 4 System Control Register SYS 030 R XSEL OSTP XSTP IRREN HIGH 0000 0001 W XSEL OSTP XSTP
4. R W Bit7 Bit6 Bit5 Bits Bit2 BitO Default 18 VOLO VOLSO VOLO 5 VOLO 4 VOLO 3 VOLO 2 VOLO 1 VOLO O 0 00 0000 19 RW VOLS1 VOL1 5 VOL1 4 VOL1 3 VOL1 2 VOL1 1 VOL1 O 0 00 0000 1B VOL3 VOLS3 VOL3 5 VOL3 4 VOL3 3 VOL3 2 VOL3 1 VOL3 0 0 00 0000 VOLx 5 0 Channel x Volume Control 000000 Level O Minimum 000001 Level 1 111111 Level 63 Miximum VOLSx Volume value valid control 0 New volume value is valid only when Timerx interrupt occur 1 New volume value is valid in time TABLE 14 7 Volume Control Register 2 1C VOLMOR W VOLMO S VOLMOI4 VOLMO 3 VOLMO 2 VOLMO 1 VOLMO O 000 0000 1D CLIP 00 0000 CLIP To amplify the mixed signal of 4 channel PSG 0 Disable amplify function 1 Enable amplify function VOLMO 5 0 Volume control of mixed channel of Channel0 and Channel VOLM1 5 0 Volume control of mixed channel of Channel2 and Channels 000000 Level O Minimum 000001 Level 1 111111 Level 63 Miximum 42 87 ST2205U m Multiplicator ST2205U build in a 16x8 multiplicator for wave table the answer s bit23 8 can be read from MULH and MULL operation We just write twice to that first is the bit7 0 is ignored Besides the answer was reloaded to multiplicand low byte then
5. NM MESI ren ET W PBPULL 7 6 PBPULLIS PBPULLI3 PBPULL 1 PBPULL O 1111 1111 pow R PO Poll Pelt Pobl PC N Pew e FER Poou RW Poe POS timimi 8 00 PRI peel CIS rot IET Pew peal ee Pe 07 PSE RW PSE 7 PSE 6 PSE 5 PSE 4 PSE S PSE 2 PSE 1 PSE O 1111 1111 0E RXDO TXDO SRDY 55 MOSI MISO SCK __ 0000 000 0F __ __ RW RXDi TXD cse 055 054 053 CS2 51 10000 0000 R W PULL PDBN INTEG CSM1 CSMO PFE 2 PFE 1 PFE O 1000 0000 04 BR PLI PL O 0000 0000 UA 0000 0000 4F PCL RW 7 PCL 6 5 2 Each single pin can be programmed to be input or output This is controlled by port direction control registers PCx Setting bit Input Mode of PCx makes respective pin to output and clearing this bit for In case of input function port data registers Px reflect the input There are two options pull up down for inputs of values on associated pins
6. 25 jm elec GENERATOR 6 27 12 COUNTER RPP 31 A A 31 vel Fonction 6119 DERE om 31 tala PRE MN OR 32 A o OO Pe o OO e O 33 AA NE E A A 39 12 2 2 Base Timer Control Status Registers occccccccooconnccnnncoconnonncnnnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnononnnnnncnnnnnnss 33 IPSI A 35 Or 35 12 3 2 Timer Clock T A 35 4 I 37 Dal 38 INE Function Desc WP T M 38 OS NERO Lc 40 Ig 40 A A 40 14 5 PWM DAC Output Mode 000000000000000 44 14 5 1 Single Pin Mode 8 bit 44 14 5 2 Two Pin Two Ended Mode 8 bit annes nna ann nnn 45 14 5 3 Two Pin Push Pull Mode 8 bit 46 ao e
7. Pwi Pwo IREN 00 000 Bit 7 RXINV Receive data inversion bit 0 Receive data is normal 1 Receive data is inverted Bit6 TXINV Transmit data inversion bit 0 Transmit data is normal 1 Transmit data is inverted Bit 2 1 PW 1 0 IrDA pulse width selection bits PW 1 0 Pulse Width 0 1 6 O 0 IREN IrDA mode control bit 0 Normal mode NRZ 1 IrDA mode 62 87 ST2205U 17 4 3 UART Status Control Register TABLE 17 4 UART Status Control Register USR __1 8 120000001 Write any value to clear USR Bit6 FER Received data frame error status bit 0 Current received data is normal 1 Frame error occurs PER Parity error status bit 0 Current received data is normal 1 Parity error occurs OER Overrun error status bit 0 Current received data is normal 1 Overrun occurs RXBZ Receiver busy bit 0 Receiver is not busy 1 Receiver 15 busy RXRDY Receiver ready control bit 0 Receiver 15 not ready 1 Receiver 15 ready TXBZ Transmitter busy bit 0 Transmitter is not busy 1 Transmitter is busy Transmitter control bit 0 Transmitter is not empty 1 Transmitter is empty 17 4 4 UART Data Register TABLE 17 5 UART Data Register Address Name RW Bite Bts Bito Det Write Write character d
8. 5 0 PFE 2 PFE 1 1000 0000 Bit6 PDBN Enable Port A interrupt de bounce 1 De bounce for Port A interrupt 0 No de bounce for Port A interrupt 23 87 9 2 External Interrupts Input signals of 2 play another function of external external interrupts Triggered by falling or rising edge 15 edge sensitive interrupt sources 2 should be set to inputs controlled by INTEG PMCR 5 Steps and program example and function bits of Port F should be 1 before turning on are shown below ST2205U TABLE 9 9 Port Miscellaneous Control Register PMCR Address RW Bit6 Bits 34 RW PULL PDBN INTEG CSMo PFE 2 1000 0000 5 INTEG Edge options of external interrupt 1 External interrupt is rising edge triggered 0 External interrupt is falling edge triggered Bit 2 PFE 2 PE2 function select bits 0 GPIO Output 1 Enable BCO function Input 1 Enable External interrupt source INTX2 Bit 1 PFE 1 PE1 function select bits 0 GPIO Output 1 Enable OSCN function Input 1 Enable External interrupt source INTX1 Bit 0 PFE O PEO function select bits 0 GPIO Output 1 Enable TCOO function 1 Enable External interrupt source INTXO _TABLE 9 10 External Interrupt Request Register XREQ R _ __
9. T2C 11 T2C 10 T2C 9 T2C 8 0000 0000 26 T3CL RW TSC 7 T3C 6 T3C 5 T3C 3 T3C 2 T3C 1 T3C 0 0000 0000 PAB SIS PRSI PASI PERSIO 00000000 W SRES SENA MD 00 2A R W 7 BTENS 2 BTENO 0000 0000 2B A A 0000 0000 _ 2D T4C T4C 6 T4C 5 T4C 4 T4C 3 T4C 2 T4C 1 0000 0000 IREQL PR RLCD IRBT IRPT IRTS IRT2 IRTO IRX 0000 0000 3E R W IELCD IEPT IETS IET2 IET IEX 00000000 3F R W IERTC IEPCM IEUSB IEURX IEUTX IESRX IESTX 00 00000 PRES gt 3 TIMER 0 SYSCK A096 SYSCK gt CK SYSCK 1024 m SIA OUTPUT SYSCKI8 o SENA ENABLE LL SYSCK 4 SRES PULSE 4 CLEAR SYSCK 2 1 2 INTX OSCX TIMER 3 FIGURE 12 1 Structure Of Two Prescalers 31 87 12 1 2 PRES The prescaler PRES is an 8 bits counter as shown in FIGURE 12 1 Which provides six clock sources for 12bit up counting timer it is controlled by register PRS The instruction read toward PRS will bring out the content of
10. If Rv12Rv221MO Cv1 0 1uF Then the detection voltage is 2 6V Start LDA 00000111 STA lt enable detector select detection source to VIN Select detection level to 1 3V Wait 30 us SEC 0 LVCTR 43 0 LVCTHR Normal Voltage Low Voltage CLC Normal Voltage LVCTR disable detector LDA 018 STA lt turn off external bias 78 87 ST2205U TABLE 24 2 Low Voltage Detector Control Register LVCTR Wf LVI O LVDS LVDEN 0000 LR _ HICH 000001 3 2 LVD 1 0 Select detection level of LVD If LVDS LVD 1 0 LVD 1 0 LVD 1 0 LVD 1 0 the detection level of LVD is VDD 2 4V the detection level of LVD is VDD 2 6V the detection level of LVD is VDD 2 8V the detection level of LVD is VDD 3 0V 0 0 1 1 3 5 the detection level of LVD 15 VIN 1 2V the detection level of LVD 15 VIN 1 3V the detection level of LVD is VIN 1 4V the detection level of LVD is VIN 1 5V Bit 1 LVDS Low Voltage Detector input signal selection bit 0 System power VDD 1 External input VIN Bit LVDEN Low voltage detector control bit W 0 Disable detector W 1 Enable detector Bit 0 HIGH Low voltage detector result R O Voltage is low R 1 Voltage is normal Note Every step of LVD 79 87 ST2205U 25 LOW VO
11. PCm t Pcm io PCM 9 PCM 8 0000 0000 6E MULL R W MUL 7 MUL 6 MUL 5 MUL 4 MUL S MUL 2 MUL 1 MUL O 0000 0000 6F R W MUL 15 MUL 14 MUL 13 MUL 12 MUL 11 MUL 10 MUL 9 MUL 8 0000 0000 39 87 Si 14 2 Tone Generator The tone frequency 15 decided by Timer and the volume 15 controlled by DAC data output register PSGxA Besides DAC data can be used to adjust volume the two level volume control VOLx VOLMx are effective too So it s very flexible to generate any tone sound which you want For example If the 1KHz tone sound want to be generated 14 3 PCM DAC A built in PWM DAC is for analog sampling data or voice signals There is an interrupt signal which is controlled by Timer form DAC to CPU whenever DAC data update is needed and the same signal will decide the sampling rate of voice Each channel has a 16 byte FIFO When the FIFO 14 4 ADPCM DAC ADPOM is a kind of encode of voice compression The compression data usually is an index It s through the index to get an offset value of the present voice sample data In ADPCM DAC mode we just store the offset value to ST2205U ChannelO and the volume is maximum First the TimerO must be set up 2KHz and write FFH to DAC data PSGAO Second the two level volume control are adjusting to maximum Refer to TABLE 14 2 TABLE 14 5 TABLE 14 4 TABLE 14 6 amp TABLE 14 7 empty byte is more than 8
12. LMOD O LCK s LCK 2 LCK i LCK O 00 0000 49 W FRA 2 FRA O 00 0000 4A WW 00000 C HW 9 LPAL4 LPAL S LPAL 2 LPAL O 0000 0000 ee RCE 2209 2099 552 SPIEN RXIEN ERIEN MEREN DRINV SMOD 0000 0000 553 SCKR RW SCK 2 SCK 1 SCK 0 BC 3 BC 2 BC 1 BC O 0000 0000 sse RXRDY SBZ MDERR OERR BCERR 000 000 p Write any value to clear SSR 55 5 0 RW J REP DELAY TOGGLE ACTIVE 0000 0000 wos Hien 50 559 DPTRH RW DPTR 12 DPTR 11 DPTR 10 DPTR 9 DPTR S 000 0000 55 DBKRL R W DBKR 7 DBKR 6 DBKR 5 DBKR 4 DBKR 3 DBKR 2 DBKR 1 DBKR O 9000 0000 658 DBKRH RW DEKR IS __ ___ DBKR 10 DBKR S DBKR S 0 000 _ 650 DCNT 14 DONT 13 DCNT 12 DCNT 11 DCNT 10 DCNT 9 DCNT 8 000 0000 5E DSEL RW DMSELJO 00 _ 5 DMOD RW FUNCH FUNCIO DMDD 1 DMDD 9 DMDs 1 DMDSJO 00 0000 60 JUCTR RW RXN PEN PMOD UMOD BRK 000000 sm FER
13. 7 PRR 6 PRRIS PRR 4 PRR 2 0000 0000 33 __ 11 PRR 10 PRR S PRR 8 0 0000 34 DRRL DRR 6 DRR S DRR 4 DAR s DRR 2 DRR O 0000 0000 35 DRRH RW DRR S _ DRR IO DRR 8 0 000 36 BRRL RW BRR S BRAS BRR 4 BRR S BRR 2 BRR O 0000 0000 37 BRRH RW BRAS BRR 12 11 BRR tO BRR e BRR 8 1 0 0000 e a Dems rt W PULL PDBN INTEG CSM CSMO PFE 2 1000 0000 XREQ2 XREQO 000 XCLR2 XCLRO 000 sac R IRLCD IRBT IRT3 IRT2 IRTO IRX 0000 0000 Reon HR HERIC ee 3E ENAL IELCD EBT IETO 0000 0000 3F RW IERTC IEPCM IEUSB IEURX IEUTX IESRX IESTX 00 0 0000 42 LVPW W VP 4 0000 0000 43 LXMAX XM 7 XM XM 2 XM OJ 0000 0000 45 PANS PAN 2 0000 0000 47 LPWR BLNK REV Gl 0 100 0000 48 LCKR W
14. R JOLRRTC CLRUSBCLRURX CLRUTX CLRSRX CLRSTX 0 0 0000 W_ CLRATC CLRUSBCLRURX CLRUTX CLRSRX CLRSTX 0 00000 3F RW ____ IEUTX IESRX IESTX 0000 16 3 1 SPI Data Registers TABLE 16 3 SPI Data Registers Address Name R W Bit 7 15 Bit 6 14 Bit 5 13 Bit 4 12 Bit 3 11 Bit 2 10 Bit 1 9 Bit0 8 Default 051 SDATAH RW SD 15 SD 14 SD 13 SD 12 SD 11 SD 10 SD 9 SD 8 0000 0000 Bit 7 0 Write Write low byte data to transmit buffer clear status bit TXEMP trigger an data exchange Read Read low byte data from receive buffer clear status bit RXRDY Bit 15 8 Write Write high byte data to transmit buffer Read Read high byte data from receive buffer 16 3 2 SPI Control Register TABLE 16 4 SPI Control Register Address Name R W Bit7 Bit6 Bits Bits Bit2 BitO Default 052 SCTR R W SPIEN RXIEN MEREN DRINV POL PHA SMOD 0000 0000 Bit 7 SPIEN SPI control bit 0 SPI disable 1 SPI enable RXIEN Receive buffer ready interrupt control bit 0 Receive buffer ready interrupt disable 1 Receive buffer ready interrupt enable ERIEN Two error interrupts control bit 0 Two error interrupts disable 1 Two error interrupts enable MEREN Mode fault detection control bit 0 Mode fault detection disable 1 Mode fault detection enable DRINV DATA RE
15. 0000 0000 22 Rw Tio TiC 0 0000 28 RW LOAD TICK TiCK Ticor Ticis 0000 24 Rw 72061 Tecta teca Teci 0000 0000 25 RW LOAD TeCKp Teci 120 Tacte 0000 0000 26 rack Rw Tacie Tacl 7304 Tach Tacto 0000 0000 Ps Past RS Prsia PRS PRS 00000000 w 8 SENA o 2A BTEN RW BTEN7 BTENG BTENS BTENS BTEN2 BTENi BTENO 0000 0000 A 7 6 BTREOS BTREO4 BTREQS BTREQ2 BTREO1 BTREQO 0000 0000 W BTOLRT BTOLR6 BTOLRS BTCLR4 BTOLRG BTCLR2 BTCLRI BTCLRO 0000 0000 20 RW Taciz Taca 0000 0000 TABLE 7 2 Control Registers Summary 14 87 ST2205U HR 2 RSEL o ______ ALMIRQ DAYIRQ HRIRQ 0000 0000 2F HIC RTC 2 1 00 0000 A 1 0000 0000 31 IRRIS _ _ IRR 10 IRR e 1888 0 0000 32 PRRL RW
16. 55 16 1 2 Transmit Buffer and Receive 56 16 1 3 Master Slave Modes and The Shift 2 000020000 0001100000000000 00 56 AS PPP ________ ___ 57 162 ca A _ _ 57 16 3 SPI Control Status ACUISTA A 58 O yq A 58 DG 2 A A 58 16 9 9 SPI Status Register ibn 59 o A 59 17 UNIVERSAL ASYNCHRONOUS 0 24 000 60 TZ UART 8 ee ee eee ee 60 Ter ME S ad 60 NMOS 60 14238 Tran S mute E Opera ati iii osa 61 17 24 Receiver 61 61 17 4 UART Control Status Registers npa ERR adn Esa Mia 62 174 1 UART Control Register NT m 62 17 4 2 UART Status Control Register uenisse e ein 63 17 4 3 IrDA Control Register iria 62 17 44 UART Data aie RENE m uu r RO 63 17 5
17. 0000 76 BKCON R W STALL mu TXZERO STALL FLUSH 000 00 77 BKOLEN R W LEN 6 LEN 5 LEN 3 LEN O 000 0000 66 87 Sitronix ST2205U 18 2 USB Control Status Registers 18 2 1 USB Control Register TABLE 18 3 TER Control m Nm X Address Name R W Bit6 BitS 70 usBCON USBEN SEN PLL 1 T RWAKE PULL cp T 0000 00 USBEN USB enable control bit O Disable 1 Enable Write 1 to reset whole USB SIE PLLEN PLL ON OFF control bit O Disable PLL 1 Turn on PLL PLLRDY PLL clock status O PLL clock 15 not stable 1 PLL clock 15 stable PLL 1 0 Select input clock of PLL 00 4Mhz 01 6Mhz 10 8Mhz 11 Reserved RWAKE Remote wake up control bit 0 Keep in suspend state 1 Device issues a remote wake up to host PULL D pull up resister control bit 0 No pull up resister for D 1 Enable D pull up resister 18 2 2 USB Interrupt Control Register TABLE 18 4 USB Interrupt Control Register Address Name R W 7 Bit6 Bits Bit2 Bito Default 71 JUSBIEN R W BRIEN RESIEN SUSIEN BKIIEN 0 10 0000 BUFEN USB buffer access control bit 0 Turn off access to USB buffer Turn on access to internal SRAM 1 Turn on access to USB buffer Turn off access to internal SRAM BRIEN USB bus reset interrupt control bit RESIEN USB resume interrupt control b
18. 72 19 1 5 DMA Mode Selection Register 0000 0000011 72 20 A APP A 73 20 1 Nand Flash quoil __________ ___ ___ _ _____ _ 6___ 73 20 2 Error Correction Code ECO E 73 20 3 Nand Flash Interface Control Registers 00000 0000110006 nennen 74 21 elige E ebil je S 75 23 MN RR acs 75 sl Iv NT 75 SA 75 22 o TIME R An n 76 A 76 23 Real TIME ore 77 24 LOW VOLTAGE DETECTOR XE ave ua axe coc in 78 29 LOW VOLTAGE HESET LVR coccion ii ps 80 26 ELECTRICAL CHARACTERISTIGS 5 81 eo A ee PU O 81 26 2 DO Ma AC i 4 15 55 E mE 81 0 AA 81 27 APPLICATION CIRCUITS Ann PP OS 84 28 REVISIONS o PP eee EE 85 2 87 Sironi 1 GENERAL
19. Address Bit7 Bit6 Bits Bit Bit 2 PFE 2 Clocking output BCO control bit sourced from BGRCK 0 Disable clocking output of BCO 1 Enable clocking output of BCO Bit 1 PFE 1 Clocking output OSCN control bit sourced from OSCN 0 Disable clocking output of OSCN 1 Enable clocking output of OSCN Bit 0 PFE O Clock signal output TCO2 control bit sourced from 0 Disable clock signal output of TCOO 1 Enable clock signal output of TCOO TABLE 13 3 BGR Control Register BCTR Address R W Bit7 Bit6 Bits Bit2 Bit BitO Default 063 BCTR RW TEST JoscNfiloscN oj BSTR BMOD 0 00 000 Bit 5 4 OSCN 1 0 Two bit divider for OSC clock output 00 OSCN OSC 1 01 OSCN OSC 2 10 OSCN OSC 4 11 OSCN OSC 8 37 87 Sironi 14 PSG 14 1 Function Description The built in four channel Programmable Sound Generator PSG is controlled by register file directly Its flexibility makes it useful in applications such as music synthesis sound effects generation audible alarms and tone signaling In order to generate sound effects while allowing the processor to perform other tasks the PSG can continue to produce sound after the initial commands have been given by the CPU The structure of ST2205U PSG was shown in FIGURE 14 1 and
20. 00 0000 Bit 4 LMOD LCD data bus mode selection 00 1 bit mode 01 4 bit mode 10 8 bit mode 11 1 bit mode for LCD driver ST2101C Bit 3 0 LCKR 3 0 LCD clock selection LCKR 3 0 SYSCK 2 Syska ___ 4 5 5 6 8 a ip SYSCK A2 16 1 SYSCK 16 18 SYSCK 4 109 SYSCK 20 9 SYSCK 22 100 SYSCK 24 1101 SYSCK 26 mo 2 9 lt 24 SYSCK 28 1111 SYSCK 30 29 87 ST2205U TABLE 11 4 BGR Control Register BCTR Address R W Bit6 Bits Bits Bit2 Bit BitO Default 063 BCTR RW TEST _ 5 05 BSTR BMOD Bit 7 TEST Test bit must be 0 Bit 5 4 OSCN 1 0 Two bit divider for OSC clock output 00 OSCN OSC 1 01 OSCN OSC 2 10 OSCN OSC 3 11 OSCN OSC 4 Bit 2 BSTR Modulation strength selection bit 0 Full modulation strength recommended 1 Half modulation strength Bit 1 BMOD Modulation mode selection bit 0 Coarse modulation mode 1 Fine modulation mode recommended Bit 0 BGREN BGR enable disable bit 0 Disable BGR 1 Enable BGR TABLE 11 5 BGR Configuration Registers BRS BDIV Address Bit7 Bit6 Bits Bits Bit2 Bito D
21. IN6 D Flip Flop INTX OSCX IN7 5 5 SEL SYSCK FIGURE 12 3 Timer Structure 12 3 2 Timer Clock Source Control Several clock sources be chosen from for Timer It s very stays active Refer to TABLE 12 7 important that Timer can keep counting as long as SYSCK TABLE 12 7 Timer Counter High Byte Register TxCH Address R W Bit6 Bits BitO Default 21 TOCH RW LOAD TOCK 2 TOCK 1 TOC 11 TOC 9 0000 0000 23 TICH LOAD T1CK 2 T1CK 1 T1C 11 TIC 10 T1C 9 T1C 8 0000 0000 25 T2CH LOAD T2CK 2 T2CK 1 T2C 11 T2C 10 T2C 9 T2C 8 0000 0000 LOAD Automatic reload control bit 0 No auto reload 1 auto reload Bit6 4 TxCK 2 0 Clock Selection bit 000 SYSCK 2 001 SYSCK 4 010 SYSCK 8 011 SYSCK 32 100 SYSCK 1024 101 SYSCK 4096 110 BGRCK 111 INTX Timer0 2 OSCX Timer1 3 Bit 3 0 TxC 11 8 High byte of Timer counter 35 87 TABLE 12 8 Timer1 Register ST2205U AR NITO 22 T1C 5 4 2 TIC 1 0 0000 0000 24 T2CL Rw T2C 7 T2C 6 T2C 5 T2C 4 2 T2C 2 T2C 1 2 0 0000 0000 26 T3CL Rw T3C 7
22. T3C 6 T3C 5 T3C 4 T3C 3 T3C 2 T3C 1 T3C 0 0000 0000 2D RW T4C 7 T4C 6 T4C 5 T4C 4 4 T4C 2 T4C 1 0000 0000 Bit 7 0 Note Timer activate only when this register be write TxC 7 0 Low byte of Timer counter TABLE 12 9 Timer Counter Enable Control R W Bit6 28 TIEN RW T4CK 2 TACK 1 T3EN TOEN 00000000 TACK 2 0 Timer4 clock selection bits 000 Clock source is SYSCK 2 001 Clock source is SYSCK A 010 Clock source is SYSCK 8 011 Clock source is SYSCK 32 100 Clock source is SYSCK 1024 101 Clock source is SYSCK 4096 110 Clock source is BGRCK 111 Clock source is OSCK 4 Timer4 counter enable control bit 0 Timer4 counter stop 1 Timer4 counter start Timer3 counter enable control bit O Timer3 counter stop 1 Timer3 counter start 2 Timer2 counter enable control bit O Timer2 counter stop 1 Timer2 counter start T1EN Timer1 counter enable control bit O Timer1 counter stop 1 Timer1 counter start TOEN TimerO counter enable control bit 0 TimerO counter stop 1 TimerO counter start 36 87 Sironi 13 CLOCKING OUTPUTS Three clocking outputs PEO PE1 and PE2 are supported by the ST2205U These signals are very useful for outputs of high frequency such as PW
23. m Transmission Format PHA 1 In this mode both master and the communicating slave will be ready after the falling edge of SS The two output MSB at the first edge of SCK Then the second edge will be the capture strobe If POL 0 the first edge is rising edge if POL 1 it will be a falling one 55 87 Sironi ST2205U Rem ee AULA CX 55 From Master E FIGURE 16 2 Transmission Format PHA 0 NV N NI N VS ANN MOS SS From Master FIGURE 16 3 Transmission Format 1 16 1 2 Transmit Buffer and Receive Buffer Operations of transmit and receive buffers are discussed below m Transmit Buffer The transmit buffer is 16 bit long and is write only This buffer 15 empty after the was enabled at the beginning In the meantime the transmit buffer empty flag TXEMP SSR 5 will be set to indicate the status of buffer Up to 16 bits of data can be filled with writes to SPI data registers SDATAL and SDATAH TXEMP will be cleared after SDATAL is wrote a value Writing SDATAH will not affect TXEMP Once the shift register proceeds to exchange data in buffer will be loaded into shift register and TXEMP will be set again Meanwhile a SPI transmitter interrupt will be issued and the transmit buffer can be filled with new data for next transmission 16 1 3 Master Sl
24. 32 Hz interrupt control bit 0 Disable 32 Hz interrupt 1 Enable 32 Hz interrupt 2 BTEN 2 64 Hz interrupt control bit 0 Disable 64 Hz interrupt 1 Enable 64 Hz interrupt Bit 3 BTENS 128 Hz interrupt control bit 0 Disable 256 Hz interrupt 1 Enable 256 Hz interrupt Base Timer Status Register 256 Hz interrupt control bit 0 Disable 256 Hz interrupt 1 Enable 256 Hz interrupt BTENS 512 Hz interrupt control bit 0 Disable 512 Hz interrupt 1 Enable 512 Hz interrupt 6 2048 Hz interrupt control bit 0 Disable 2048 Hz interrupt 1 Enable 2048 Hz interrupt BTEN7 8192 Hz BTC interrupt control bit 0 Disable 8192 Hz BTC interrupt 1 Enable 8192 Hz BTC interrupt TABLE 12 5 Base Timer Status Register BTSR Address R W Bit7 Bit6 Bits W BTCLR7 BTCLR6 BTCLR5 BTCLR4 BTCLR3 BTCLR2 BTCLR1 BTCLRO 0000 0000 0 BTREQO 2 Hz interrupt status bit 0 No2Hz interrupt occurred 1 2 Hz interrupt occurred Write 1 to clear bitO status bit 1 32 Hz interrupt status bit 0 No 32 Hz interrupt occurred 1 32 Hz interrupt occurred Write 1 to clear status bit 2 64 Hz interrupt status bit 0 No 64 Hz interrupt occurred 1 64 Hz interrupt occurred Write 1 to clear bit2 status bit 3 BTREQ3 128 Hz interrupt status bit 0 No 128 Hz interrupt occurred 1 128 Hz interrupt oc
25. 0000 0000 50 DCNTH RW DCNT 14 DCNT 13 DCNT 12 DCNT 11 DCNT 10 DCNT 9 DONT 8 000 0000 DCNT 14 0 DMA Length register Read write the 15 bit DMA length register DMA starts after a write to 19 1 4 DMA Register Select Bits Address Name RW Bit7 Bit6 Bits Bit2 BitO Default _ 5 RW __ 5 00 DMSEL 1 channel select bit Select also mode register 0 Select channelO 1 Select channel1 DMSEL 0 source destination select bit 0 Select source pointer and bank registers 1 Select destination pointer and bank registers 19 1 5 DMA Mode Selection Register There are two DMA mode registers for both channel which 15 selected by DMSEL 1 Pointer modes and channel functions are controlled by this register 5F_ DMOD RW FUNC 1 FUNC O DMDD 1 DMDD O DMDSTO 00 0000 DMDST 1 0 DMA source pointer mode selection bit 00 Continue mode Source pointer continues when next DMA starts 01 Reload mode Source pointer restore its original value when next DMA starts 1x Fixed mode Source pointer 15 fixed DMDD 1 0 DMA destination pointer mode selection bit 00 Continue mode Destination pointer continues when next DMA starts 01 Reload mode Destination pointer restore its original value when next DMA starts 1x Fixed mode Destination poin
26. 43 51 52 8 4 20 33 25 11 12 35 14 15 39 ST2205U DATE 2005 5 24 2005 5 23 2005 3 15 2005 3 2 2005 2 7 2004 10 20 2004 10 14 2004 8 30 2004 6 5 2004 3 29
27. DBKR DMSEL 0 1 moved Only single instruction is needed for a repeated 15 bit data length register DONT transfer It can the one of three as below a STZ zp 3 cycles b SMB7 zp 5 cycles c RMB7 zp 5 cycles There are three modes for manipulation of both pointers a Continue b Reload and c Fixed Pointer increases one DMA works only on the logical address of 8000 FFFF after each transfer in continue mode and becomes 8000 combines with source and destination bank registers all after FFFF is reached At this time DBKR also increases physical memory can be accessed including whole 32KB one to map to the next bank Reload mode acts like internal RAM if bit16 of bank register is set continue mode except pointer and bank registers will back to their original values when each transfer stops In case of Note Fixed mode pointer keeps the same value always If bit16 of bank register is set 8000 807F will refer to control registers Excepting normal operation there is one special function for each channel and is controlled by There are two DMA channels and are selected by FUNC 1 0 DMOD 5 4 DMA channelO can help image DMSEL 1 DCTR 1 After selecting a channel source or data operations AND OR and XOR logic operations can be destination registers are then chose by DMSEL 0 DCTR O0 done between source and destination data being moved to make further register access correct Regarding channel1 double data transfer speed is pos
28. Divider SPICK IN OUT 5 2 4 8 256 SCKR 6 4 PSGCK 5 2 5 2 4 8 16 CLK32 LCDCK Divider LCDCK IN OUT OSCK OSCK 2 4 30 LCKR 4 0 MUX2 ien SYSCK XBAK sYst4 722 Warm up control SER XSTP SYS 5 SKP SYS 3 256 cycles 16 cycles XSEL SYS 7 XSEL SYSU CLK32 PLL PLLCK IN OUT OSC Divider 48Mhz PLL 1 0 OSCN OSC OSC 2 3 4 OSCN 1 0 FIGURE 11 1 Clock Generator Diagram 28 87 ST2205U ST2205U TABLE 11 2 Control Address _R W_ Bit6 _ Cu Doo 039 W XSEL OSTP XSTP XBAK WSKP WAIT IRREN 0000000 XSEL Source of system clock selection bit R O Current system clock is OSC R 1 2 Current system clock is OSCX W 0 Select OSC to be system clock W 1 Select OSCX to be system clock OSTP OSC stop control bit 0 Enable OSC 1 Disable OSC XSTP OSCX stop control bit 0 Enable OSCX 1 Disable OSCX XBAK OSCX driver heavy load bit 0 OSCX heavy load 1 OSCX normal load WSKP System warm up cycles selection bit 0 256 warm up cycles RC mode 0 32768 warm up cycles Crystal mode 1 16 warm up cycles RC mode 1 8192 warm up TABLE 11 3 LCD Clock Control Register Address R W Bit6 Bits Bit2 Bito Default 048 LCKR W _ LCK 3 LCK 2 LCK 1 LCK 0
29. PF 2 PF OJ 1000 0000 Bit 1 0 CSM 1 0 External chip select mode selection bits See TABLE 10 2 for more information 26 87 Sironi 11 CLOCK GENERATOR The ST2205U has two oscillators OSC and OSCX for both high and low frequency needed In case of resistor mode XMD connects to high level the high frequency oscillator OSC adopts only one external resistor to generate a high frequency clock OSCK which is used by almost every block in chip OSC can also change to be a resonator crystal oscillator by input low level to XMD Note In case of crystal oscillator mode OSCK will be half the frequency of the output of OSC If 4Mhz is desired for OSCK and SYSCK then use a 8Mhz crystal for the oscillation of OSC The low frequency oscillator OSCX needs a 32768Hz crystal and one capacitor to generator a precise frequency CLK32 for Base timer Timer1 3 and the reference clock of baud rate generator BGR Two modes heavy and normal load are supported by the OCSX for different oscillation gain After power on the default heavy load mode is selected for shorter start up time Note After an average time of 1 5 second then CLK32 is stable Please switch to normal load mode for power saving Other clocks are sourced from either OSCK or CLK32 and are listed below System clock SYSCK LCD controller clock LCDCK PSG and PWM DAC clock PSGCK BGR output clock BGRCK SPI transmission clock SPICK Divided clock of O
30. Refer to TABLE 10 2 for configurations of all chip selects in different modes Note Write 1 to bit of port direction control register PCD then to bit of port function select register PFD to activate the designated chip select signal ST2205U DISABLED Internal 16KByte B Emulation Mode FIGURE 10 1 Connections Of MMD CSO TABLE 10 2 Memory Configurations Of Chip selects Total Support First 16K Chip select Memory Range and Size of Chip selects pp Mode Memory Size Oso 1 0 csi 052 css cs css CS6 A8 0000000 4Mbyte 25 87 1M bytes 1M bytes 2M bytes 07FFFFF 08FFFFF 09FFFFF 41FFFFFF 8Mbyte 1M bytes 1 bytes 2M bytes AM bytes 16Mbytes 11FFFFF 13FFFFF 17FFFFF 1FFFFFF 2FFFFFF 16Mbyte 2M bytes 2M bytes AM bytes 8Mbytes 16 bytes 1000000 1800000 17FFFFF 1FFFFFF 8M bytes 8M 32M Bytes 8M bytes 000000 1FFFFFF 32M ETS 48M ST2205U TABLE 10 3 Port Function Select Registers 0F PFD cse CS5 CS4 CS3 CS2 51 0000 0000 _ Bit 7 0 PFD 5 0 Port function select bits 0 GPIO 1 Chip select signal is connected TABLE 10 4 Port Miscellaneous Control Register PMCR 3A RW PULL PDBN INTEG CSMO
31. ST2205U a Pin option LVRSEL O TUI mE Pin option LVRSEL Low Voltage Detect m Low Voltage Detectlevel_ Vivar 22 24 26 IntemalmodelVDS tO LVCTR 3 2 00 Low Voltage Detectlevel Vine 24 26 28 IntemalmodeLVDS t O LVCTR 3 2J 01 Low Voltage Detect level 26 28 3 0 Internal mode LVDS 1 0 LVCTR 3 2 10 Low Voltage Detect level Viv 28 30 32 Internal mode LVDS 1 0 LVCTR 3 2 Low Voltage Detect level 11 12 13 External mode LVDS 0 LVCTR 3 2 00 Low Voltage Detect level Vive 12 13 14 External mode LVDS 1 0 LVCTR 3 2 01 Low Voltage Detect level Vivaz 13 14 15 External mode LVDS 1 0 LVCTR 3 2 10 Low Voltage Detect level Vives 14 15 16 External mode LVDS 1 0 LVCTR 3 2 mw _ 08 5 32768 Crystal Heavy mode 15 S37680ysalNomalmode Wanne E Main reaveney 6182 worm up cde _ 112 ms LE frequency ROSC 19 wamap ece _____ ___ 80 uS MainfrequencyR OSC 256 warm up cycle 82 87 Sironi ST2205U AC Electrical Characteristics 23 0 D 7 0 A 23 0 CSx D 7 0 ISA tWLC ICLRL FIGURE 26 2 External Write Timing Diagram TABLE 26 1 Timing parameters for FIGURE 26 1 and FIGURE 26 2 Standard operation conditions VCC 3 0V GND Ta 25 CS L pulse width tWHCH Signal fall time tCLRL CS asserted to RD
32. WSKP WAIT IRREN LVDEN 0000 0000 Bit 1 IRREN Enable Disable Bank register IRR 0 Disable IRR 1 Enable IRR 16 87 Sf 7 4 RAM The internal 32KB static RAM can be divided into 3 parts in function First is the zero page memory 0000 00FF second is stack 0100 01FF and third can be used as LCD frame buffer 0200 7FFF or for general purpose m Zero Page Data RAM 0080 00FF Total 128 bytes of data RAM in zero page is very useful for programmers They provide short instruction codes and cycles Use zero page addressing mode on the variables in this area usually speeds up the overall performance Stack RAM 0100 01FF The ST2205U has 256 bytes stack from 0100 to 01FF It provides a maximum of 128 levels for subroutines By setting stack pointer carefully stack memory can also be used as data 17 87 ST2205U memory User Memory 0200 7FFF All internal RAM can be used as LCD frame buffer or user memory The range of LCD frame buffer will be fixed after initialization of LCD control registers Memory beyond is user memory Read and write operations can be applied to LCD frame buffer to maintain display content and almost none of the CPU time is affected This is contributed by one special memory transfer technique of display data from LCD frame buffer to the LCD controller Parts of the user memory can only be accessed via memory banks PRR can access the range from 4000 to 7FFF and BR
33. XM 2 XM 0 0000 0000 44 LYMAX RW YM 6 YMI5 L 45 LPAN _ 0000 0000 PAN 1 0000 0000 46 LBUF RW LBUF 7 LBUF 6 LBUF 5 LBUF 4 LBUF 3 LBUF 2 LBUF 1 LBUF O 0000 0000 47 LPWR REV 100 0000 ES ECKE W LMOD LMOD 0O LCK 3 LCK 2 LCK 1 LCK 0 00 0000 49 w 5 4 FRA 3 FRA 2 FRA O 00 0000 HN 4A LAC AC 2 00000 548 LPWM RW 4GPS 1 4GPS 0 LPWM 5 LPWM 4 LPWM 3 LPWM 2 LPWM 1 LPWM 0 0000 0000 4C W sae pL RW PU LPALI4 LPAL 3 LPAL 2 LPAL 1 LPAL O 0 0000 1111 1111 4F PCL w PCL 6 PCL B PCL 4 PCL 3 PCL 2 PCL 1 0000 0000 47 87 Si 15 1 LCD Specific Signals The following signals are generated by LCDC to connect the ST2205U and an LCD module Two of them are PL7 The LCD frame marker signal indicates the start of a new display frame FLM becomes active after the last line pulse of the frame and remains active until the next line pulse at which point it de asserts and remains inactive until the next frame B LP1 PL6 The LCD line pulse signal is used to latc
34. banked logical area in 2000 3FFF PRR is Program ROM Bank Register and is 12 bit long and its logical address is 4000 7FFF The third one DRR is Data ROM Bank Register of a length of 11 bits DRR control the last logical area ST2205U 8000 FFFF These three bank registers can refer to a maximum extended memory space of 48M bytes Note Only 44M 28M when 0 bytes is addressable by chip selects Besides extended memory the internal 32KB RAM can also be accessed by three bank registers by setting bit15 of each bank register With BRR 15 1 8KB internal RAM 2000 3FFF can be accessed And with PRR 15 1 16KB internal RAM 4000 7FFF can be accessed Moreover the whole 32KB internal RAM 8000 FFFF can be accessed by setting DRR 15 Refer to TABLE 7 1 for three bank registers Refer to FIGURE 7 1 for memory mapping of ST2205U TABLE 7 1 Bank Registers and Logical Range Address Name 7 Bit6 Bit5 Bit3 33 PRRH RW PRA PRRI9 8 0 0000 34 DRRL DRR 6 DRR 3 DARIO 0000 0000 35 RW j DRH IO DRR t0 DRR 9 DRR 8 0 000 36 BRRL BRR 6 BRAS BRR 3 BRR 0 0000 0000 BRRH BRR IS BRR 12 BRR 11 BRR 10 BRR 9 BRR 8 1 0 0000 BRR 0 11 13 bit BRR bank register Control logical banked area of 2000 3FFF PRR 0 11 12 bit PRR bank register Con
35. mode selection input Low Crystal mode One crystal or resonator should be connected between OSCI and XIO High Resistor oscillator mode One resistor should be connected between OSCI and VCC OSCXI OSCXO Connect one 32768Hz crystal between these two pins when using low frequency oscillator 29 31 WR RD External memory R W control signals External memory 41 60 22 0 External memory address bus bus signals 62 64 32 39 D 7 0 External memory data bus Current DAC PSGOB COUT Also 12 bit current DAC output by register control Keyboard scan port A signal return 106 113 7 0 line 6 87 ST2205U TABLE 3 2 Signal Function Groups continued Function Group Flash Data Bus 67 FD7 0 PF7 0 69 73 Flash read write 27 RXD1 FWR PD7 When function bits are set and I O direction is output and FEN 1 signals TXD1 FRD PD6 PD7 6 are flash control signals CS5 1 PD4 0 I O port D and chip select outputs 8 9 RXDO PC7 TXDO PC UART signals and 1 UART 28 6 RXD1 FWR PD7 TXD1 FRD PD6 DATA READY 5 SPI signals and l Os 3 7 SS PC4 SDO PC3 SDI PC2 SCK PC1 When function bits are set and I O direction is output these three BCO INTX2 PE2 can be clocking outputs OSCN INTX1 PE1 m When function bits are set and I O direction is input these three TCOO INTXO PEO can be external clock inputs or external interrupt sources When function bits are cleared they are
36. the Timer interrupt will be triggered Besides There are two steps volume control to adjust one channel integrate volume and a couple of channels integrate volume Refer to description of following TABLE register PSGxA to add to present voice sample data or store the offset value to register PSGxB to subtract to present voice sample data TABLE 14 2 DAC Data Register PSGxA Address Name Bit7 Bit6 Bit5 10 PSGOA R W PSGOA 7 PSGOA 6 PSGOA 5 PSGOA 4 PSGOA 3 PSGOA 2 PSGOA 1 PSGOA 0 0000 0000 12 PSG1A H W PSG1A 7 PSG1A 6 PSG1A 5 PSG1A 4 PSG1A 3 PSG1A 2 PSG1A 1 PSG1A 0 0000 0000 14 PSG2A RW PSG2A 7 PSG2A 6 PSG2A 5 PSG2A 4 PSG2A 3 PSG2A 2 PSG2A 1 PSG2A 0 0000 0000 16 PSG3A R W PSG3A 7 PSG3A 6 PSG3A S PSG3A 4 PSG3A 3 PSG3A 2 PSG3A 1 PSGSA 0 0000 0000 PSGxA 7 0 DAC output data In tone mode This byte is a volume control In PCM DAC mode This byte is normal DAC output data In ADPCM DAC mode This byte is offset value 40 87 TABLE 14 3 FIFO status register Address R W Bit6 Bit5 Bit4 ST2205U Bit2 BitO Default WRITE Bit 7 0 Address R W Bit7 Bit6 BitS Bit4 R PSG1A 8 FWRA FIFOS 4 FIFOS 3 FIFOS 2 FIFOS t FIFOS 0 0000 0000 R PSG2A 8 FWRA FIFOS 4 FIFOS 3 FIFOS 2 FIFOS 1 FIFOS 0 0000 0000
37. 5 Once the receiver is enabled it searches for a start bit qualifies it and then samples the succeeding data bits at the perceived bit center Jitter tolerance and noise immunity are provided by sampling 16 times per bit and using a voting circuit to enhance sampling While receiving the busy status of receiver can be read from RXBZ USTR 3 with logic level 1 Receiving activity will be complete after the stop bit is detected Then this data is sent to receiver from input buffer and input buffer will ready to receive next data At this time receiver is not empty and IRURX IREQ 11 will be set to issue the interrupt request The received data can be obtained by reading data register UDATA And receiver will empty again to wait to receive next data from input buffer after reading the data register Three kinds of errors may arise from illegal received data which are reported at 3 bits of status register USR 6 4 and are discussed below 17 3 Interface Signals Two sets of data lines can be enabled simultaneously for communication TXDO PC6 RXDO PC7 and the auxiliary pins TXD1 PD6 RXD1 PD7 Data can inputs and outputs from and to these pins With setting related bits of port function select registers PFC and PFD signals of the external devices can be connected Data in and from these communication I Os can be inverted by setting polarity control bit RXINV and TXINV IRCTR 7 6 Direction settings and function select bi
38. Besides read instruction for data of Port C E but only pull up for inputs of the other ports In case of signals input writing to register Px selects l O types of pins output there are open drain CMOS options for outputs of pull up or pull down Setting bits of all port data register Px to PortC E but only CMOS for the other ports Refer to TABLE select pull up type Clearing bits of only PC PE to select 9 2 pull down type for pins of Port C E There are no pull down TABLE 9 2 1 0 Types Of GPIO Ports resistors for Port A B D F and Port L thereby no pull down Types resistors will be enabled if clearing bits of PA PB PD PF and 2 Mode PortA B D F L Port C E PL Pull up resistors of Port A B D F L are also controlled by Input Pull uo Pure Pull up Pull down Pure PULL bit bit7 of port miscellaneous register PMCR 0 is to Output CMOS Open drain CMOS disable while 1 is to enable them The pull up pull down resistors of Port C E are further controlled by bits of port type 21 87 select registers PSC PSE They work in the same way with PULL bit of PMCR but only on single pin 0 is to disable while 1 is to enable PULL UP PORT CONTROL REGISTER DATA REGISTER PDR DATA INPUT RD_INP UT FIGURE 9 1 Configuration of Port A B D F L Output Mode In case of output function wite to port data registers Px makes pins to output desir
39. FIGURE 14 2 Each channel of PSG of the ST2205U has three playing type One for square type tone sound playing Second for DAC PCM playing The third sound playing type is DAC ADPCM playing The three type can be applied in the four channels and mixed to one output signal to make the PSG generates melody and voice at the same time DAC Data ___ 6 Byte VOLT ADPCM ADD SUB Operator Sampl Sync to Vol Controller a Channel x ate Volume Signal Control x Tone Timerx Tone Data Generator FIGURE 14 1 PSG One Channel Structure Block Channel 0 Signal Mixer 0 Volume Channel 1 3 Control of Signal Channel 0 PWM PSG Mixer 2 Clip Mixer 3 DAC Sienal Channel 2 f ontrol o Signal Cicer Mix Current MN Channel 1 DAC Channel3 Signal 12bit FIGURE 14 2 PSG Four Channel Mixer Structure Block 38 87 ST2205U TABLE 14 1 Summary Of DAC Registers Address R W Bit7 Bit6 Bit5 Bit2 BitO Default 10 PSGOA R W PSGOA 7 PSGOA 6 PSGOA 5 PSGOA 4 PSGOA 3 PSGOA 2 PSGOA 1 PSGOA 0 0000 0000 sit S S A FOOL 9000 0000 12 PSG1A PSG1A 7 PSG1A 6 PSG1A S PSG1A 4 PSG1A 3 PSG1A 2 PSG1A 1
40. PRES and the ST2205U Instruction write toward PRS will reset or enable PRES TABLE 12 2 Prescaler Control Register PRS Address R W Bit4 PRS 7 PRS e PRS 4 PRS 3 PRS 2 PRS 1 510 0000 0000 W SRES SENA mmu n oo READ 7 0 PRS 7 0 Value of PRES counter WRITE Bit 7 gt SRES Prescaler Reset bit Write 1 to reset the prescaler PRS 7 0 Bit6 SENA Prescaler enable bit O Disable prescaler counting 1 Enable prescaler counting 32 87 6722050 12 2 Base Timer The base timer supports one interrupt which occurs at seven real time applications may include digitizer sampling keyboard different fixed rates and one adjustable clock Applications base debouncing or communication polling Block diagram of base on the base timer interrupt can chose an appropriate interrupt timer is shown in FIGURE 12 2 rate from eight time bases for their specific needs These Frequency BTC 770 Base er Interrupt Control gt eg ister S120 Z 256H 2 12887 64H z 2H 7 Counter Counter Counter Counter Counter Counter FIGURE 12 2 Base Timer Block Diagram 12 2 1 Base Timer Oper
41. RWW PSGIB 7 PSG1B 6 PSGIB 5 36184 PSG1B 3 PSG1B 2 PSGTB 1 36180 0000 0000 14 PSG2A RW PSG2A 7 PSG2A 6 5 2 PSGeAI4 PSG2A 3 PSG2A 2 PSG2A 1 PSG2AJO 0000 0000 15 PSG2B HW PSGeB 7 PSG28 6 PSG2B 5 PSG2B A PSG2B 2 PSG2B1 PSG2BIO 0000 0000 16 PSG3A RW PSG3A 7 PSG3A 6 PSGSAI4 PSGGA 3 PSGSA 2 PSGBAL1 PSGBAJO 0000 0000 17 PSG3B RW PSG3B 6 PSG3B A PSG3B 3 PSG3B 2 PSG3B 1 PSG3B 0 0000 0000 18 VOLO RW voLeo voros VOLO VOLO VOLO Y VOLO O 0 00 0000 19 RW vost VOLI VOLI vorto 0 00 0000 RW VOLS2 votas voreja VOL2 0 00 0000 vors RW vorss voreja vorst VOLSIO 0 00 0000 sic RW VOLMO S VOLMO4 VOLMO S VOLMO 2 VOLMO 1 VOLMO O 00 0000 vom RW CUP VOLMIb5 VOLMI 4 VOLM1 3 VOLM1 2 VOLM1 1 VOLMI O 000 0000 PSGC RW PSEN 2 PIEN POEN PCMEN DACEN PSGO i PSGOJ0 0000 1000 PSGM RW PMD2 1 PMD1 1 PMD1 O PMDO 1 0000 0000 20 Rw 70061
42. T1 interrupt will execute and interrupt mask flag will be cleared Hardware will push PC P Register to stack and set 19 87 interrupt mask flag 1 Program counter will be loaded with the T3 vector from locations 7FFO and 7FF1 m PT Interrupt The IRPT Port A interrupt request flag will be set while Port A transition signal occurs With IEPT PT interrupt enable being set the PT interrupt will be execute and interrupt mask flag will be cleared Hardware will push PC P Register to stack and set interrupt mask flag 1 Program counter will be loaded with the PT vector from locations 7FEE and 7FEF BT Interrupt The IRBT Base timer interrupt request flag will be set when Base Timer overflows The BT interrupt will be executed once the IEBT BT interrupt enable is set and the interrupt mask flag is cleared Hardware will push P Register to stack and set interrupt mask flag 1 Program counter will be loaded with the BT vector from locations 7FEC and 7FED m LCD Buffer Interrupt The IRLCD LCD buffer interrupt request flag will be set when LCDC are scanning the first line of the LCD buffer This interrupt is very useful for software gray level design and also the flexible utilization of display memory The LCD buffer interrupt will be executed once the IELCD LCD frame interrupt enable is set and the interrupt mask flag is cleared Hardware will push PC and P registers to stack and set i
43. a data exchange starts and the transmit buffer is empty This status can be read from status bit TXEMP SSR 5 Receive buffer ready interrupt happens when a data exchange completes and the receive buffer is filled with one new data This interrupt is enabled by setting control bit RXIEN SCTR 6 The status is reported at status bit RXRDY SSR 6 The other two interrupts are error interrupts and are both enabled by control bit ERIEN SCTR 5 Receive buffer overrun interrupt and bit count violation interrupt share the 16 2 Interface Signals Five multiplexed signals are used to interface with other SPI devices With setting related bits of port function select register PFC these signals can be activated Direction and function select bits should be ascertained before they are used Refer to section 9 for these settings Hg SCK PC1 This is a bidirectional synchronous clock I O which is multiplexed with PC1 SCK is output in master mode and input in slave mode MISO 2 Master In Slave Out bidirectional signal which is multiplexed with PC2 External data 15 inputted to this pin to the shift register in master mode In slave mode it is an output of shift register B MOSI PC3 Master Out Slave In bidirectional signal which is multiplexed with PC3 Data in shift register is outputted from this pin in master mode In slave mode it is an input of external data to the shift register ST2205U while DATA RE
44. are still working On the other hand up but not entering interrupt service routine If interrupt CPU and the related instruction execution stop All registers disable flag is cleared 0 the corresponding interrupt RAM and pins will retain the same states as those vector will be fetched and the service routine will be before the MCU entered power down mode WAI 0 mode executed The sample program is shown below LDA 500 STA SYS WAI WAI 0 mode 21 2 1 Mode If WAIT is set WAI instruction makes MCU enter WAI 1 wake up procedure is the same as for WAI 0 The mode In this mode CPU stops but the PSG timer counter difference is that the warm up cycles occur when waking keep running if their clock sources are from OSCX The from WAI 1 Sample program is shown as following LDA 04 STA lt SYS WAI WAI 1 mode 21 3 STP Mode STP instruction will force MCU to enter stop mode In this can only be waked up by hardware reset and the warm up mode MCU stops but PSG timer counter won t stop if the cycles occur at the same time clock source is from OSCX In power down mode MCU FIGURE 21 1 Status Under Power Down Modes SYSCK source is OSC oo RAM RES 10 Wake up conto Retain Reset An interrupt PA 77 WAI 1 Stop Stop Stop Stop Reset Any interrupt STP Stop Stop Stop Stop Retan Reset SYSCK source is OSCX Reset Any inte
45. asserted O O O 5 83 87 Sironi ST2205U 27 APPLICATION CIRCUITS VUBS VDD Rp 170 20 3 4V VDD IOVDD AVDD PSGVDD VOUT3 3 PLLVDD 4 7uF 0 1uF 0 1uF 0 1uF 240x240 LCD 240x120 160x80 MM E VDD MODULE 160x160 112x48 la le P S le BRE a TEST1 4 en 1 5 XMD MMD CSO SUBSTRATE E 100pF CONNECTS TO GND A D converter L 332768Hz Touch Panel Controller CXI CX2 25pF T 25pF VBAT 100K 100K 1 5 KEY MATRIX BUZZER E a 4 7uF 1 0uF 0 1uF 0 1uF VSS 10 88 AVSS PSGVSS USBVSS PLLVSS USBVSS Note 1 Keep the trace between oscillation resistor and the PCB pad as close as possible for a more stable clock 2 The OSCX can still work if remove CX1 and increase CX2 to 47pF 3 The capacitors that connect to VOUT3 3 PLLVDD USBVDD must as close as possible to reduce noises 4 Resister Rp and zenor diode ZD provide a solution for using host power when USB cable plugged in 84 87 ST2205U 28 ROM PROGRAMMING INTERFACE 28 1 INTERFACE DESCRIPTION In order to program OTP ROM several pins have to be 28 1 It just be used to connect writer to program OTP reserved on the PCB which is bounding with ST20P64 ROM These totals are 34 pins that includ
46. bytes of ECC buffer and also the counter for ECCO 1 control FSR 1 0 ECC generation enable bit 00 No error 01 Correctable error 10 ECC code error 11 Uncorrectable error ECC 23 0 3 byte ECC buffer Write to each register to make operation between the original data and the byte written into Write to high byte ECCH also triggers the error detection operation R Read from these registers to retrieve error bit position 74 87 ST2205U 21 POWER DOWN MODES ST2205U has three power down modes WAI 0 WAI 1 and STP will enable STP mode in the same manner WAI 0 and STP The instruction WAI will enable either 0 or WAI 1 WAI 1 modes can be waked up by interrupt However STP which is controlled by WAIT SYS 2 And the instruction mode can only be waked up by hardware reset TABLE 21 1 System Control Register SYS 030 XSEL OSTP XSTP XBAK WSKP IRREN HIGH 0000 0001 W XSEL OSTP XSTP XBAK WSKP WAIT IRREN LVDEN 0000 0000 Bit 2 WAIT 0 WAI 1mode select bit WAI instruction causes the chip to enter WAI 0 mode 1 WAI instruction causes the chip to enter WAI 1 mode 21 1 WAI 0 Mode If WAIT is cleared WAI instruction makes MCU enter WAI O can be waked up by reset or interrupt request even If user mode In the mean time the oscillator interrupts sets interrupt disable flag 1 In that case MCU will be waked timer counter and PSG
47. fast data transfer from market Both HID and hidden by clearing BUFEN Mass storage classes are supported as well as the firmware libraries and the Windows 98 driver Whole USB function is Double buffer scheme is applied to both BKI and BKO controlled by setting USBEN USBCON T7 After connects buffers to increase throughput and eases real time data to a USB host port 6 interrupts which share the same transfer interrupt vector play the main role of USB communication Proper routines responding to every host command should TABLE 18 1 Summary of USB Buffers be executed to generate the right answer into the endpoint Buffer Address buffers to be transferred back Three endpoints are supported including control endpoint 2407 27F bulk in endpoint and bulk out endpoint BKO EPO has a buffer of 8 bytes long while BKI and BKO each has a 64 bytes buffer which three range from 200 to 28F Refer to TABLE 18 1 for the memory mapping Write 1 to TABLE 18 2 Summary of USB Control Register Address Name R W Bit7 Bit6 Bit5 Bit2 1 BitO Default JUSEIEN AW ON BRIEN RESIEN SUSIEN SKOIEN EPOIEN 0 10 0000 USBBFS EPOIN 1010 EPocoN B w STALL FLUSH rus nero DRQ 1 DRQ O 000 0000 75 EPOLEN LEN 2 LEN O
48. is Rv2 Detection Voltage mU 1 2 Equation22 1 y If Rv12Rv22100kO Cv120 1uF Then the detection voltage is 2 4V Initialize LDA 11111111 STA lt Set I O to output mode STZ lt 5 Set I O to open drain Start LDA 00h STA lt PC on external bias Wait 40ms wait VIN stable LDA 00000011 STA lt LVCTR enable detector select detection source to VIN Select detection level to 1 2 Wait 30 us SEC 0 lt LVCTR 3 0 lt LVCTR Normal_ Voltage Low Voltage CLC Normal Voltage lt disable detector LDA 01h STA lt PC off external bias keeps on consuming power So it is important to write O to LVDEN and disable the detector after detection is completed In FIGURE 24 1 shows an application circuit for detecting battery voltage applied to VIN LVDS 1 Note that the DC current of two external resistors can be cut off by setting PCO to open Also add one capacitor to VIN to minimize noise and narrow the low voltage detection range In FIGURE 24 2 shows another application circuit It will consume a constant current but save the delay time for VIN to be stable If LVDS 0 and detecting VDD please leave VIN pin open ST2205U Rv1 VIN Rv2 Cv1 FIGURE 24 2 Application of LVD 2 Example2 If LVD 1 0 LVCTR 3 2 01 The detection voltage for FIGURE 24 2 is Rv2 Detection Voltage 13 Equation22 2
49. of ST2205U 13 87 Sitronix ST2205U 7 2 Control Registers Address 000 07F is for control registers Refer to TABLE 7 2 for the summary of all registers There are more details of registers in the related sections Address Name RW Bite Bis BRO Default 00 aw Pl PARI C NITE Pew Pen Pa Fes pa 59 Pei Pel ow t Poel Pol cal f Pcr Pob PCPULLIS POPUL PCPULL S POPULI PCPULLIT PCPULLO ft 1 PO OUM RW POR POBI ri por poa Pid rrr 04 emn Peje ets Pers EI rim zB EE EE EE BE EE EE EE Ww PFPULLI7 PFPULL S PFPULLS PFPULLS PFPULLIE PFPUL T PFPULLIO 1111 1111 07 PSE RW PSEjS PStis PSE 2 PSE PSEjO soe PFC Rw SHDY 55 mosi miso SCK 0000000 L 0F PFD RW RXDt TXD cse css cse csi 00000000 10 PSGOA HW PSGOA 7 PSGOA S PSGOA S PSGOAJA PSGOA S PSGOA 2 PSGOA 1 PSGOAJO 0000 0000 12 RW PSGIA 7 PSGtA 6 PSG1AI4 PSG1A 2 PSGIA 1 PSG1AIO 0000 0000 13 PSGiB
50. size 90um x 90um 2 Substrate GND 3 Chip size 3490um x 4070um 6 Si 8 Os 19650 9 PG 681 19650 650 19050 s o6 12550 19050 s RD 16980 16200 De 16 50 16000 Symbol 9 87 Do 16750 10004 0 2 8 9 17 16750 00 D D D A A A A A A A A 2 2 2 A A A 1550 5000 1550 8000 0 00 00 1 10 16750 19400 4 50 19650 2 19550 19650 TESTI 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 61 62 63 64 65 67 70 we 1 770 Pts 50 19650 77 50 19650 5450 19650 770 22 7450 19650 77 USEVSS 1438 0 19650 9 D 17647 9 D 1647 10 87 ST2205U AAA Sironi 6 CPU m Register Model 7 0 7 0 Lo Y 7 0 7 0 PCL Accumulator The Accumulator is a general purpose 8 bit register that stores the results of most arithmetic and logic operations In addition the accumulator usually contains one of the two data words used in these operations m Index Registers X Y There are two 8 bit Index Registers X and Y which may be used to count program steps or to provide and index value to be used in g
51. three GPIOs FLM PL7 LP1 PL6 LCD control signals AC PL5 CP PLA LCD control 12 16 20 LD 3 0 PL3 0 signals 74 82 Clocking output External clock input or interrupt sources 2 POFF BLANK VBUS Connect to USB bus power VBUS D D USB differential signal pins RPULL VOUT3 3 RPULL Add a resistor of 1 5 between this pin and D D D VOUT3 3 3 3V regulator output Connect to USBVDD to supply power for the analog transceiver of USB 97 99 101 102 7 87 ST2205U 4 PAD DIAGRAM dd Vid Sdd 94d Old ld Id V ld S ld 9 ld 330d SSA 21531 21531 Odd Lad cdd edd vdd 9 99 29 55 45 Y g gt ov CN O 2 Q 81518181519 9 9115 ARRE ERRE 5 81215 8 8 E E 5l 2 9 El 5 5 El 5 El 5 El 55 El lt 5122050 2 vdd edd Ladd Odd 944 Sid vd ldd OAd SSA 424 99d cod 09d 943 Sao EE E EJ EDS 19 ICE5 8 PSGVSS 1129 VBUS 2 XMD ICE3 2 ICE1 PSGO 24 RSE PSGOB PSGVDD 32 8 87 ST2205U 5 DEVICE INFORMATION 1 Pad
52. which 15 also the default value BLANK Contrast control The LCD blank signal is used to control the contrast of display by setting contrast level in LPWM 5 0 with 00000 default represents a maximum level and 11111 is for minimum The BLANK signal achieves this function by outputting a PWM signal according to the settings of contrast Refer to section 15 4 11 for more information Besides contrast control BLANK signal plays another role of turning display off This is controlled by register bit BLNK LCTR 6 Setting BLNK will make BLANK signal to output 0 to blank the display regardless of contrast control Setting BLNK bit will enable the PWM contrast control and of course the BLANK signal If LPWM 5 0 are all zeros BLANK signal will stay at high level with no PWM modulation LP2 7 When PWM gray level function is enabled by setting GL 1 0 LCTR 4 the PWM line pulse signal will be outputted from this pin When this function is LP2 outputs the identical signal with that of LP1 48 87 15 2 Mapping the Display Data The screen width and height of the LCD panel are programmable through software Although the maximum screen size can be up to 1024x512 the actual supported resolution is limited by the display buffer size which 15 also the internal RAM size and is 32K bytes Instead of screen size specified by control registers larger frame can also be displayed via th
53. 0 Empty byte of the FIFO are more than 4 FIFOC 3 0 The number of the filled byte of the 8X12 bit PCM FIFO 0000 There is no data in FIFO 0001 2 There is 1 data in FIFO 1000 here are 8 data in FIFO FIFO is full OUTS 9 0 The data that has mixed from each channel WRITE PCM 11 0 12 bit PCM data input 43 87 Sitronix ST2205U 14 5 PWM DAC Output Mode Options The PWM DAC generator has three modes Single pin DAC mode is controlled by PSGO 1 0 of register mode Two pin two ended mode and Two pin push pull PSGC 2 1 mode They are depended on the application used The 14 5 1 Single Pin Mode 8 bit Accuracy Single pin mode is designed for use with a single transistor high 50 of the time up to 100 high As the value goes amplifier It has 8 bits of resolution The duty cycle of the from 0 to 128 the duty cycle decreases from 50 high to PSGOB is proportional to the output value If the output 0 PSGO is inverse of PSGOB s waveform Figure 13 3 value is 0 the duty cycle is 50 As the output value shows the PSGOB waveforms increases from 0 to 127 the duty cycle goes from being 126 192 64 126 High PSGOB 128 64 192 Low DAC 0 DAC 64 DAC 64 FIGURE 14 3 Single Pin Mode Wave Form ST2205U 330 ohm FIGURE 14 4 Single Pin Application Circuit 44 87 ST2205U 14 5 2 Two Pin Two Ended Mode 8 bit Accuracy Two Pin Two Ended mode is designed for use with a si
54. 00 0000 20 R W TOC 5 TOC 3 TOC 2 TOC t 0000 0000 21 TOCH LOAD TOCK 1 TOCK 0 TOC 11 TOC 10 TOC S TOC 8 0000 0000 22 Rw TiC 6 TIC 5 T1C 3 T1C O 0000 0000 23 LOAD TtCK 1 T1CH1 1 10 T1C 9 T1C 8 0000 0000 24 2 T2C T2C 6 T2C 5 T2C 4 TaC 3 T2C 2 TaC t 0000 0000 25 2 LOAD T2CK 2 2 T2C 11 T2C 10 T2C 8 0000 0000 26 T3CL TSC T3C 5 T3C 4 T3C 3 T3C t T3C O 0000 0000 PRS 7 PRS 6 PRS 5 PRS 4 PRS 3 PRS 2 PRS 1 PRS O 0000 0000 W SRES SENA NNNM 00 2D T4C 6 T4C 5 T4C 4 T4C 3 T4C 2 T4C 1 0000 0000 AA A 3E H W IELCD IEBT IET3 IETO 00000000 3F R W IERTC IEPCM IEUSB IEURX IEUTX IESRX IESTX 00 0 0000 sec 2079 7 OUTS 6 OUTS 5 OUTS 4 OUTS 3 OUTS 2 OUTS 1 OUTS O 0000 0000 HEEM PEWA ga 0000 0000 _
55. 1 Signal Function Groups 11 61 83 84 100 VDD IOVDD AVDD Power PSGVDD USBVDD PLLVDD VPP 104 117 132 10 40 85 96 103 VSS IOVSS AVSS1 Ground i AVSS2 PSGVSS 2 USBVSS PLLVSS RESET 1 30 68 86 87 115 116 5 1 2 3 System control ERE ICE1 2 3 4 5 6 1 MMD CS0 LVRSEL 124 128 UIN XMD XIO OSCI OSCXO OSCXI 118 119 121 123 VDD Power supply for internal core IOVDD Power supply for AVDD Power supply for analog blocks PSGVDD Power supply for PSGO and PSGOB USBVDD Power supply for USB circuit PLLVDD Power supply for PLL circuit VPP Power supply for programming OTP ROM VSS Power ground for internal core IOVSS Power ground for AVSS Power ground for analog blocks PSGVSS Power ground for PSGO and PSGOB USBVSS Power ground for USB circuit PLLVSS Power ground for PLL circuit RESET Active low system reset signal input TEST1 2 3 ICE1 2 3 4 5 6 Leave them open when normal operation MMD CSO Memory modes selection pin Normal mode Enable internal ROM MMD CSO connects to GND Emulation mode Disable internal ROM MMD CSO connects to chip select pin of external ROM One resistor should be added between VCC and this pin After reset cycles MMD CSO changes to be an output and outputs signal CSO LVRSEL LVR active level selection input Low LVR active level is 2 1V High LVR active level is 2 8V VIN Input voltage level for Low Voltage Detection XMD High frequency oscillator OSC
56. 12 Bit 3 11 Bit 2 10 Bit 1 9 BitO 8 Default 03E IENAL RW IELCD IEBT IEPT IET3 IETO 0000 0000 03F R W IERTC IEPOM IEUSB IEURX IEUTX IESRX IESTX 0 0 0000 18 87 IEXXX Interrupt ON OFF control bit 1 Enable respective interrupt ST2205U 0 Disable respective interrupt 8 1 Interrupt Description B Brk Instruction BRK will cause software interrupt when interrupt disable flag I is cleared Hardware will push PC registers to stack and then sets interrupt disable flag 1 Program counter will be loaded with the BRK vector from locations 7FFE and 7FFF E Reset A positive transition of RESET pin will make an initialization sequence to begin After the system has been operating one low level signal on this line of at least two clock cycles will cease ST2205U activity When a positive edge is detected there is an initialization sequence lasting six clock cycles Then the interrupt disable flag is set the decimal mode is cleared and the program counter will be loaded with the reset vector from locations 7FFC low byte and 7FFD high byte This is the start location for program flow This input should be high in normal operation B INTX Interrupt The IRX INTX interrupt request flag will be set while INTX edge signal occurs The INTX interrupt will be active when IEX INTX interrupt enable is set and interrupt disable flag is clear
57. 31 2 01 0 57 3 11 N 49 55 61 19 21 23 26 29 33 2400 37 42 47 49 55 61 K 2 60 2 26 1 33 4 89 295 2 56 0 44 4 71 3 30 2 86 0 27 3 29 2 99 0 44 1 87 3 35 0 14 38400 1 33 4 28 3 72 010 4 00 477 414 0205 1 33 1 3 146 1 33 4 00 1 28 0 44 4 00 140 1 87 2 22 1 59 0 85 0 44 1 77 1244 1 33 CO C1 O1 O1 CO O1 O1 CO N gt 4800 19 21 23 26 29 112 1203 177 311 5122050 28 111196 171 044 56 24 393 341 044 29 _ 1 12023 177 311 54 12 379 329 4 00 68 29 477 414 005 57600 55 2 __ 386 395 222 E s 168 146 240 mo s 196 in o4 1 1379 829 400 203 177 ss t 386 335 222 5 zer jos nszo ss f Tas s s 226 138 0 sz t 4o 347 1397 42 o 2 256 04 Example 12 1393 1341 0 44 In case of Baud Rate 115200 BRS 58 and BDIV 1 the OSCK must be in the range of 4 07 to 3 54MHz Los a aes 057 65 87 ST2205U 18 UNIVERSAL SERIAL BUS USB The ST2205U incorporates one PLL a 3 3V regulator and BUFEN USBIEN 7 to enable these buffers There are still a full speed USB 1 1 device engine to satisfy the strong total 144 bytes of user RAM to use when USB buffer is demand of
58. 4 gray level and 16 gray level more smoothly than only FRC The ST2205U builds in 32K bytes SRAM so the maximum panel size can be 640x400 for B W 400x320 for 4 gray level and 160xRGBx120 for 16 gray level mode ST2205U LCDCK is for LCDC to generate timings and the pixel clock Refer to 0 for frequency settings of LCDCK The ST2205U supports 1 bit 4 bit and 8 bit data bus for the compatibility of most popular LCD drivers The LCD output signals are shared with Port L and are controlled by LCD power control bit LPWR LCTL 7 and data bus selection bits LMOD 1 0 In case of 1 bit mode PL2 1 can still be used for general purpose while only PLO outputs LCD data Note A The LCD signals will be disconnected and Port L will output values assigned by PL after setting LPWR B Set PL 00h to make Port L output zeros when LCDC is off Various functions are also supported to rich the display information including virtual screen panning scrolling contrast control and an alternating signal generator Control registers used by LCDC are listed below TABLE 15 1 Summary Of LCD Control Registers Address Name RW Bit7 Bit6 Bit5 Bit4 41 LSSAH W 554 15 SSA 14 SSA 13 55 12 55 11 SSA 10 55 9 SSA 8 0000 0000 42 LVPW w VP VP 6 VP 4 VP S VP 2 VP 1 VP O 0000 0000 343 LXMAX RW XM 7 XM 6 XM 5 XM 3
59. 5122050 Integrated Microcontroller User s Manual 5122050 Rev 1 0 06 2005 ST2205U CONTENTS s 2 GENERAL DESCRIPTION 3 2 FEATURES AP 5 SS crie me me ee 6 A 27 RN 8 LMaizluecwiieliqe m 9 M 11 7 MEMORY CONFIGURATION 12 Memory Map and BARKING Pe EE EE 12 72 1 E o 14 To terup Bank TETTE SEMESTER 16 TARAN 17 8 INTERRUPT CONTROLLER n XX SnSnX4 S4 A 18 mM isi isque A 19 ce 21 Transistion e e PE o UE EP ESE _____ T 23 9 121 io o 23 Y A ae 24
60. 6 x 5 bit array provides the mapping of value of display data to the gray that is shown on the screen Display data makes an option of one gray from the palette and then it is to be displayed on the screen It does not choose the gray we see directly actually it choose the gray that is defined by data filled into the palette register sequentially In FRC mode there are 16 grays produced by LCDC This means values of 0 to 15 can be put into the palette And in FRC PWM mode there can be 31 kinds of grays that can be seen but only 16 kinds in one frame at most Values of ST2205U 0 30 can be put into the palette in this mode In 16 gray level mode there are 16 grays need to be filled in The palette is defined by input proper values to the palette register LPAL by 16 times The may keep the last enough number of values with the original order if more are inputted In 4 gray level mode there are still 16 grays need to be filled in These 16 grays will then be divided into 4 palettes The operational one 15 selected by register 4GPST 1 0 LPWMI 7 6 TABLE 15 12 LCD Palet Register C PAL w LPAL 3 LPAL 2 LPAL 1 LPAL O 0 0000 Bit 4 0 LPAL 4 0 Write to the register by 16 times to fill in the whole palette 54 87 Sironi ST2205U 16 SERIAL PERIPHERAL INTERFACE The ST2205U contains one serial peripheral interface SPI module to interface with
61. ADY PC5 is not functional The exchange takes place only when SS inputs low level and ends when it returns to high On the falling edge of SS the shift register will be loaded with data in transmit buffer and then the exchange initiates During exchanging data is clocked by external clock from SCK and is shifted in and out the shift register Exchanged data will be ready when the exchanged bit number matches bit count setting After data is ready data transfer between shift register and two buffers will function automatically as it does in master mode So that the shift register can be ready for the succeeding clock edge If SS rises before enough data bits current exchange is over anyway but the bit count violation flag BERR SSR 0 will be set interrupt vector with receive buffer ready interrupt These three interrupts are OR together to generate an individual vector In master mode receive buffer overrun interrupt happens when moving new data from shift register to receive buffer with RXRDY equals 1 The overrun interrupt is issued and the status bit OERR SSR 1 will be set In slave mode old data in receive buffer will not be flushed while other operations are the same with those in master mode Bit count violation interrupt only happens in slave mode If SS input rises before enough data bits are reached current exchange is over anyway but the bit count violation flag BERR SSR 0 will be set and the interrupt i
62. ADY active level selection bit 0 Active level is high 1 Active level is low Bit 2 1 SPHA SPOL SPI clock polarity and phase control bits Refer to section 16 1 1 Bit 0 SMOD Master Slave modes selection bit 0 Select slave mode 1 Select master mode 58 87 ST2205U 16 3 3 SPI Status Register TABLE 16 5 SPI Status Register 054 PARDY TAEME 382 A 000 000 Write any value to reset SSR RXRDY Receive buffer status flag 0 Receive buffer is empty 1 Receive buffer 15 filled with new data and is ready TXEMP Transmit buffer status flag 0 Data in transmit buffer 15 waiting for exchanging 1 Transmit buffer is empty 582 SPI busy flag 0 SPI is idle 1 SPI is busy exchanging data MDERR Mode fault status flag 0 SS signal is at high level and is normal 1 SS signal inputs low level a mode fault status detected OERR Receive buffer overrun error flag 0 No receive buffer overrun error 1 Receive buffer overrun error occurs BERR Bit count violation flag 0 Exchanged data bit number matches bit count setting in slave mode 1 Exchanged data bit number is less than bit count setting in slave mode 16 3 4 SPI IIS interface Modify SS active level and types to support IIS TABLE 16 6 055 SMOD RW REP DELAY TOGGLE 0000 REP Repeat transmitting current data once 0 Repeat m
63. DESCRIPTION The ST2205U is a 8 bit integrated microcontroller designed with CMOS silicon gate technology The true static CPU core power down modes and dual oscillators design makes the ST2205U suitable for power saving and long battery life designs The ST2205U integrates various logic to support functions on chip which are needed by system designers This is also important for lower system complexity small board size and of course shorter time to market and less cost The ST2205U features the capacity of memory access of maximum 44M bytes which is needed by products with large data bases Six chip selects are equipped for direct connection to external ROM SRAM Flash memory or other devices Maximum one single device of 16M bytes is possible Two DMA channels make fast data transfer possible and easy Both source and destination pointers can refer to the whole memory space with 15 bit pointers and bank registers Besides normal operation two special modes are designed for double transfer speed of Nand Flash memory and also fast graphic operation between two display pictures Nand Flash is a low cost mass data storage solution for newly design The ST2205U equips a Nand flash interface to connect both Nand and And Flash memories Both ECC generating and checking functions are supported These are very important for Flash data management The ST2205U has 56 grouped into 7 ports Port A Port F and Port L Each pin can be progra
64. E 47 CAES NR A 48 13 2 Map lame Display Dalta arica 49 t93 A nn e E E OA 50 15 2 Control ts 51 15 4 1 LCD Screen Starting Address Register ccccccoocnnncccnnccconoonncnonnnonnnonnnnnnnnnononnnnnnnnnonnnnnnnnnnnnnnonnnnnnnnnnnononnannnennnnnns 51 15 4 2 LCD Virtual Page Width sucinta ida tb a rao dam 51 154 3LCD Screen Width Register di ns dazu ses ss 51 15 4 4 LCD Screen Height Register cccccccccooccnnnccnnncconononnnnnnnononnnnncnnnnnnonnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnninns 51 15 4 5 LCD Panning Offset FeCl ______ ___ 51 15 4 6 Buffer Size nice c TETTE 52 ri RR 52 15 4 8 LCD Frame Rate Adjust 52 15 4 9 LCD Frame Rate Adjust 52 15 4 10 LCD Signal Rate Register e deg e passa suse 53 15 4 11 LCD PWM Contrast Control Register ccccccooccnncccnncccononnncnonoconononnncnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnns 53 tod 12 LOD Gray Leve Rails 54 16 SERIAL PERIPHERAL INTERFACE 2 2 55 O lo lt c Lo A 55 ST2205U 16 11 Clock CONTO rason
65. LTAGE RESET LVR Power bouncing during power on is a major problem when to normal will output high and the system may recover its designing a reliable system The ST2205U equips Low original states and keeps working correctly Voltage Reset function to keep whole system in reset status when power 15 not stable Once low voltage status 15 The LVR circuit always works and it consumes very few detected an active low pulse will be output from pin current RESET to perform this protection After the power backs 80 87 ST2205U 26 ELECTRICAL CHARACTERISTICS 26 1 Absolute Maximum Rations Note Stresses above those listed under Absolute Maximum DC Supply Voltage 0 3V to 4 5V Ratings may cause permanent damage to the device All the Operating Ambient Temperature 10 to 60 ranges are stress ratings only Functional operation of this Storage Temperature 55 to 125 device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended Exposed to the absolute maximum rating conditions for extended periods may affect device reliability 26 2 DC Electrical Characteristics Standard operation conditions 3 0V GND Ta 25 C OSC 8MHz CPU clock 4MHz unless otherwise specified Operating Voltage EJ 24 f se V Operating Frequency OSC
66. M base signal or carrier of remote control 0 overflow signal 15 the clock source of PEO and m Clocking Output PEO The overflow signal of TimerO will be connected to toggle data of PE 0 when setting function selection bits Meanwhile PEO outputs clocked data of half the frequency of 0 After resetting TCOO the toggle operation ceases Then PEO return to the original logic level of PE O m Clocking Output PE1 Oscillation output of OSC will be the input of a 2 bit divider and then output to PE1 when PE1 function is on by setting PFE 1 ST2205U OSON is for PE1 while BGRCK is for PE2 Clocking outputs output specific signals when respective function bits are set and output original logic levels set by PE x after function bits are cleared The 2 bit divider is controlled by OSCN 1 0 BCTR 5 4 Refer to TABLE 13 3 for settings of OSCN m Clocking Output BGRCK will output through PE2 when setting function selection bit BCO PMCR 2 If BCO is cleared PE2 returns to the original logic level of PE 2 Summary of clocking outputs registers is shown in TABLE 13 1 The clocking outputs enable bits can be found in TABLE 13 2 TABLE 13 1 Summary Of Clocking Outputs Registers Address RW Bit7 Bit6 Bits 3 PMCR PULL PDBN INTEG CSMO PFE 2 PFE 1 PFE O 1000 000 TABLE 13 2 Port Miscellaneous Control Register PMCR
67. PER OER 1 xar TXEMP 400 0000 Write any value to clear 558 E 62 IRCTR RW RXNV TXNV Pw IREN 00 000 563 BCIR RW TEST OSCN H OSCNO BSTR BMOD BGREN 0 00 000 15 87 gt Sw from 77 FEN cose 0000 EcodR gt 1 0000 00 sc 8 outs oursi QUTSIOI 0000 cono frown ron Eroen rogo Oursia QUTSII 0000 cono O Poma PCM 0000 0000 MULL RW MUI MUL mULfs MUL 2 MUL t 0000 0000 Leer RW MULS MULT MUtjs 0000 0000 WC Pug wwe 570 usecow i o e oru rose o sri JUSBIEN RW BREN RESEN SUSEN BRIEN 0 10 0000 sm R ano meso susina Bruna Feo 00 0000 E Rw BK BKO 1010 74 STALL FLUSH TXZERO oo SETUP DRQ O 000 0000 75 EPOLEN 75 EPOLEN UW LENS LEN 2 0000 76 BKCON RW STALL FLUSH TXZERO STALL FLUSH 00000 77 BKOLEN R W
68. PSG1A 0 0000 0000 FWRA FIFOS 4 FIFOS 3 FIFOS 2 FIFOS 1 FIFOS 0 0000 0000 s sot Hy fpc Psae Pec SS Pete Pse 0000 0000 14 5 2 PSG2A 7 PSG2A 6 PSG2A 5 PSG2A 4 PSG2A 3 PSG2A 2 PSG2A 1 PSG2A 0 0000 0000 jPSG2A BB FWRA FIFOS 4 FIFOS 3 FIFOS 2 FIFOS 1 FIFOS 0 0000 0000 515 1 2 60 0000 0000 16 PSG3A R W PSG3A 7 PSG3A 6 PSG3A 5 PSG3A 4 PSG3A 3 PSG3A 2 PSG3A 1 PSG3A O 0000 0000 17 R FWRA FIFOS 4 FIFOS 3 FIFOS 2 FIFOS 1 FIFOS 0 0000 0000 18 VOLO Rw VOLSO VOLO 5 VOLO 4 VOLO 3 VOLO 2 VOLO 1 VOLO O 0 00 0000 19 Rw VOLS1 VOL1 5 VOL1 4 voL1 3 VOL1 2 VOL1 1 VOL1 0 0 00 0000 1A 2 RW VOLS2 VOL2 5 VOL2 4 VOL2 3 VOL2 2 VOL2 1 VOL2 0 0 00 0000 18 VOLS3 VOL3 5 VOL3 4 VOL3 3 VOL3 1 VOLS O 0 00 0000 1C VOLMO RW__ VOLMO 3 VOLMO 2 VOLMO 1 VOLMO O 00 0000 1D VOLMi R W VOLMi 5 VOLM1 4 VOLM1 3 VOLM1 2 VOLM1 1 VOLM1 0 000 0000 1E 5 H W P2EN POEN PSGO 1 PSGO 0 MUTE 0000 0000 1F PSGM PMD3 1 PMD3 0 PMD2 1 PMD2 0 PMD1 1 PMD1 0 PMDO 1 PMDO O 00
69. R PSG3AS FWRA FIFOS 4 FIFOS S FIFOS 2 FIFOS 1 FIFOS O 0000 0000 PSGxA 8 Bit 8 of the 9 bit FIFO register FWRA FIFO write available 1 Empty byte of the FIFO are less than 8 0 Empty byte of the FIFO are more than 8 FIFOS 4 0 The number of the filled byte of the FIFO 00000 There is no data in FIFO 00001 There is 1 data in FIFO 10000 here are 16 data in FIFO FIFO is full PSGxB 7 0 ADPCM offset value In ADPCM DAC mode This byte is offset value TABLE 14 4 DAC Control Register PSGC Bit 7 4 PxEN PSG channel enable bit O Disable channel x 1 Enable channel x PCMEN Current DAC mode selection bit O Disable 12 bit PCM channel 1 Enable 12 bit PCM channel PSGO 1 0 PSG output mode selection bit 00 Single Pin mode 7 bit resolution 01 Two Pin Two Ended mode 8 bit resolution 10 2 Two Pin Push Pull mode 8 bit resolution 11 Current DAC mode MUTE PSG mute bit O PSG is not mute 1 PSG 5 mute 41 87 ST2205U TABLE 14 5 PSG Mode Selection Register 5 R W PMD3 0 PMD2 1 PMD2 0 PMD1 1 PMD1 0 PMDO 1 PMDO O 0000 0000 PMD3 Channel 3 signal mode PMD2 Channel 2 signal mode PMD1 Channel 1 signal mode PMDO Channel 0 signal mode 00 PCM mode 01 11 ADPCM mode TABLE 14 6 Volume Control Register 1
70. R can only access 2000 3FFF while DRR can access the whole range 0000 7FFF Sironi 8 INTERRUPT CONTROLLER The ST2205U supports 16 hardware interrupts as well as one software interrupt Brk There are 17 exception vectors for these interrupts and another one for reset All interrupts are controlled by interrupt disable flag I bit2 of status register P Hardware interrupts are further controlled by interrupt enable register IENA Setting bits of IENA enables respective interrupts The interrupt controller owns one priority arbitrator When more than one interrupts happen at the same time the one with lower priority number will be executed first Refer to TABLE 8 1 for priorities of interrupts ST2205U Once an interrupt event was enabled and then happens the CPU wakes up if in either wait mode and associated bit of interrupt request register IREQ will be set If P flag is cleared the related vector will be fetched and then the interrupt service routine ISR will be executed Interrupt request flag can be cleared by two methods One is to write 0 to IREQ the other is to initiate related interrupt service routine Hardware will automatically clear the Interrupt request flag All interrupt vectors are listed in TABLE 8 1 TABLE 8 1 Interrupt Vectors 7 7 Software BRK operation vector RESET External 7FFD 7FFC __ INTX External S 7FF9 7FFB 9 Reset vector Reserv
71. SC OSCN SYSCK The system clock can be switched between OSCK and CLK32 by resetting or setting XSEL SYS 7 After XSEL is set or reset warm up cycles will be initiated at the same time The original clock is still connected until the end of warm up cycles Clock being used can be reported by reading XSEL back Note Test XSEL to confirm SYSCK is switched over successfully before turning down the original clock There are two options for warm up cycles 16 256 cycles which are controlled by WSKP SYS 3 Usually 16 cycles are enough for OSC and OSCX LCDCK The LCD controller has one four bit divider to generate LCDCK directly from OSCK for pixel clock and other operations This divider is controlled by LCKR 3 0 and the 27 87 5722050 data mode selection bit LMOD LCKR 4 Refer to 0 for settings of LCDCK E PSGCK PSGCK is the clock used by PSG and PWM DAC It is sourced from OSCK to make sure of one right and high enough base frequency and to keep it unchanged Bits of PSGC 6 4 control the options of PSGCK m BGRCK The ST2204 equips a baud rate generator BGR which is controlled by BGR control register BCTR locked frequency selection register BRS and divider control register BDIV The BGR utilizes digital PLL technique to lock a high frequency around OSCK 2 This high frequency is further scaled down via an integer divider to a desired frequency BGRCK The BGR uses CLK32 as reference clock
72. SSA 8 0000 0000 Bit 15 0 LSSA 15 0 16 bit starting address of display buffer Attention The LCD start byte must be set on even byte 15 4 2 LCD Virtual Page Width Register The LCD virtual page width register LVPW contains the width of a virtual screen that may be wider than real setting This field is used for calculating the starting point of next line TABLE 15 4 LCD Virtual Page Width Register Address Name R W Bit6 Bits Bits Bit2 BitO Default Bit 7 0 VP 7 0 Width of virtual page width Virtual page with LVPW 16 15 4 3 LCD Screen Width Register The LCD screen width register LXMAX 15 used to specify the width of the LCD panel in pixels Every bit of display data maps to one pixel of LCD panel LXMAX represents number of data in byte of each line TABLE 15 5 LCD Screen Width Register Address Name R W Bit6 Bits Bit2 BitO Default Bit 7 0 XM 7 0 LCD screen width LCD screen width LXMAX 8 15 4 4 LCD Screen Height Register The LCD screen height register LYMAX is used to specify the weight of the LCD panel in pixels TABLE 15 6 LCD Screen Height Register Address Name R W Bit6 Bit5 Bits Bit2 BitO Default Bit 7 0 YM 7 0 LCD screen height LCD screen height LYMAX 2 15 4 5 LCD Panning Offset Register The LCD panning offset register LPAN is used to con
73. T S IREN 00 000 BSTR BMOD BGREN 0 000 00A Pee aw PCC 7 PCCI6 PCCI5 4 3 2 PCC O 0000 0000 00B PCD 7 PCD 6 PCD 5 PCD 4 PCD 3 PCD 2 PCD 1 PCD O 0000 0000 00D RXDO TXDO SRDY MOSI MISO SCK 0000 000 00E PFD RW RXD1 TXD 056 55 CS4 CS3 CS2 CS 00000000 R IRRTC W CLRRTC CLRPCM 03D IRUSB IRURX IRUTX IRSRX IRSTX 00 0 0000 CLRUSB CLRURX CLRUTX CLRSRX CLRSTX 00 0 0000 IENAH RW IERTC IEPOM IEUSB IEURX IEUTX IESRX IESTX 00 0 0000 17 2 UART Operations The UART has two modes of operation NRZ and IrDA which represent data in different ways for serial 17 2 1 NRZ mode The non return to zero NRZ mode is primarily associated with RS 232 Each character is transmitted as a frame delimited by a start bit at the beginning and a stop bit at the end Data bits are transmitted least significant bit LSB first and each bit occupies a period of time equal to 1 full bit If parity is used the parity bit is transmitted after the most significant bit Data settings including data length stop bit number and parity are controlled by bit fields in UCTR FIGURE 17 2 illustrates a character S in NRZ mode communication protocols RS 232 and IrDA 17 2 2 IrDA mode IrDA mode uses character frames as NRZ mode does but instead of driving ones and ze
74. The 8 bit Processor Status Register contains seven status flags Some of these flags are controlled by program others may be also controlled by the CPU as well The instruction set contains a member of conditional branch instructions that are designed to allow testing of these flags Refer to TABLE 6 1 TABLE 6 1 Status Register P N Signed flag by arithmetic 1 Negative 0 Positive Bit6 Overflow of signed Arithmetic flag 1 Negative O Positive Bit 4 interrupt flag 1 BRK interrupt occur 0 Non BRK interrupt occur 11 87 D Decimal mode flag 1 Decimal mode 0 Binary mode Bit2 I Interrupt disable flag 1 Interrupt disable 0 Interrupt enable Bit1 Z Zero 1 Zero 0 Non zero Carry flag 1 Carry 0 Non carry Sironi 7 MEMORY CONFIGURATION 7 1 Memory Map and Banking The logical memory space of ST2205U is divided into 4 parts 0000 1FFF 8K 2000 3FFF 8K 4000 7FFF 16K and 8000 FFFF 32K First is for control registers stack and system memory The rest are three banked areas for physical memory space The physical memory space here can refer to two areas which are internal 32KB RAM area and extended 48MB memory area Logical address in banked areas combines one of three bank registers BRR PRR and DRR respectively and then be mapped to a continuous 26bit wide physical address BRR is a 13 bit Bios Program ROM Bank register and controls the 8KB
75. _ XREQH 000 XCLR XCLRI XCLRO 000 Bit 2 0 XREQ 2 0 External interrupt request bits R 0 2 No interrupt occurred R 1 2 An interrupt occurred Bit 2 0 XREQ 2 0 External interrupt request clear bits W 0 Do nothing W 1 Clear external interrupt request 24 87 Sironi 10 CHIP SELECT LOGIC CSL The ST2205U builds in one chip select signal CS0 for embedded 16K bytes mask ROM and six chip select signals multiplexed with PD5 0 of Port D which are used to select devices on the external bus There are two options for the first 16K bytes memory which are controlled by MMD pin Tie MMD to ground to select normal mode and enable internal ROM for the first 16K bytes memory Connect MMD to chip select of an external device to select emulation mode and disable internal ROM After reset cycles MMD changes to an output and outputs chip select signal CS0 Refer to FIGURE 10 1 for two connections of different modes Two bits CSM 1 0 of port miscellaneous register PMCR select four modes of CSL which define the memory size of each external chip select Chip select signal CS6 can change ST2205U ENABLED Internal 16KByte A Normal Mode ST2205U to be address signal A23 to make one single device of 16M bytes at CS5 possible The address range of CSx of higher number follows the range of previous one of lower number
76. al Interrupts Clocking 12 bit Timer0 3 Output 9 bit 4 channel Melody 12 bit PCM Buffer 12 bit Current DAC FIGURE 1 1 ST2205U Block Diagram FD 7 0 PF7 0 Flash Interface 16 Graylevel 5 bit palette FWR PD7 FRD PD6 LD 7 4 PE6 3 LP2 PE7 LD 3 0 PL3 0 CP PL4 AC PL5 LP4 PL6 FLM PL7 BLANK POFF LCD Controller Sironi 2 FEATURES Totally static 8 bit CPU ROM 16K x 8 bit OTP RAM 32K x 8 bit Stack Up to 128 level deep Operation voltage 2 4V 3 6V Operation frequency 4 0Mhz 2 4V Min 6 0Mhz 2 7V Min One 16x8 Signed Multiplier Low Voltage Reset LVR m Two levels of bonding options Low Voltage Detector LVD Programmable 4 levels System power or external battery level can be detected Flash Memory Interface On the fly ECC code generation and detection Fast data transfer with dedicated DMA channel Nand and And type Flash supported USB 1 1 device Integrate one PLL to produce 48Mhz clock Built in 3 3V regulator for transceiver Mass storage class supported Double buffering and direct buffer access increase throughput and ease real time data transfer Direct Memory Access DMA Two channels with special modes for Flash and display Three address generation modes Memory configuration a Four kinds of banks for bios program data interrupt and internal RAM 13 bit bank registers support
77. ata to transmitter Read Read character data from receiver 63 87 5722050 17 5 Settings For Standard Baud Rates One clock of 16 times of the communication baud rate 1 needed by the UART to perform data transmission receiving Note synchronization and parity error operations Settings of Before each communication detect OSCK and BRS BDIV and OSCK ranges for standard baud rates are make sure OSCK 15 in the legal range that listed in TABLE 17 6 Besides fine modulation mode and matches the settings of BRS and BDIV which 15 full modulation strength are suggested when using BGR to listed in TABLE 17 6 If OSCK drifts due to power generate clock for UART Store value of 03 to BCTR to becomes low please chose another settings for select these two options correct communication TABLE 17 6 Settings For Standard Baud Rates Baud Error Baud Error Rate d 96 Rate 2000 Min Min 19200 54 6 1379 329 400 _ INEF jatt 00 _ 55 16 _ 3 86 335 22 19 116 56 6 1393 341 0 44 _ 21 1 28 044 57 6 1400 347 1 33 _ 24 146 0 10 58 16 4 07 354 3 11 _ 27 165 0 17 59 6 414 360 489 30 1 83 0 39 33 207 0 05 1200 37 226 0 23 42 2 56 0 44 3 30 286 0 27 4 00 299 0 44 0 44 546 3285 0 14 3 11 E 3 72 0 10 2 81 116 4 14 0 05 0 44 135 1 6 1 33 4 30 1 28 0 44 4 00 140 1 87 28800 2 22 1 59 0 85 0 44 2 08 177 1 01 4 400 347 133 2
78. ations The base timer consists of eight sub counters and one divider interrupts should be serviced Write 1 to each bit of the to produce eight predefined rates The connections between register may clear each bit of the register respectively overflow signals of these sub counters and the base timer interrupt are controlled by respective bit fields of base timer Note Make sure BTSR is cleared after the interrupt enable register BTEN The enabled overflow signals are was serviced so that the request can be set next ORed to generate the base timer interrupt request Related bits time of base timer status register BTSR will show which rates of 12 2 2 Base Timer Control Status Registers Summary of base timer control status registers is shown in TABLE 12 3 TABLE 12 3 Summary Of Base Timer Control Registers 2 BTEN7 BTEN6 5 BTEN4 2 1 BTENO 0000 0000 528 BTREO R 6 5 4 2 1 BTREQO 0000 0000 3E IENAL RW IELCD JETS IET2 IET IETO IEX 00000000 33 87 Sironi Base Timer Control Register ST2205U TABLE 12 4 Base Timer Control Register BTEN Address R W Bit7 Bit6 Bit5 0 2 Hz interrupt control bit 0 Disable 2 Hz interrupt 1 Enable 2 Hz interrupt Bit 1 BTEN1
79. ave Modes and The Shift Register The SPI can operate in master or slave mode according to SMOD SCTR 0 These two modes and operations of the shift register for each are discussed below m Master Mode The SPI operates as a master device when setting SMOD In this mode communication clock is provided by ST2205U with SCK PC1 If there may have more than one master connected bus contention can be detected by setting mode fault detection bit MEREN SCTR 4 SS signal should be input and pulled high temporarily during this detection Once SS inputs low level a mode fault status can be reported at MDERR SSR 2 Receive Buffer The receive buffer is 16 bit long and is read only This buffer is empty after the was enabled first In the meantime the receive buffer ready RXRDY SSR 6 will be cleared to indicate status of buffer Two bytes of data can be read from SDATAL and SDATAH After completing exchange data in shift register will be loaded into receive buffer and then RXRDY will be set to indicate that the received data 15 available Next RXRDY should be cleared by one read instruction to SDATAL Reading SDATAH will not affect RXRDY In case of master mode if one completed data 15 moving into receive buffer and RXRDY 15 still set moving activity will no stop but the receive buffer overrun flag OERR SSR 1 will be set to indicate that an old data is overwrote If it is in slave mode the receive buffer w
80. curred Write 1 to clear bit3 status bit Base Timer Divide Bit 4 BTREQ4 256 Hz interrupt status bit 0 No 256 Hz interrupt occurred 1 2 256 Hz interrupt occurred Write 1 to clear bit4 status bit 5 BTREQ5 512 Hz interrupt status bit 0 No 512 Hz interrupt occurred 1 512 Hz interrupt occurred Write 1 to clear bit5 status bit BTREQ6 2048 Hz interrupt status bit 0 No 2048 Hz interrupt occurred 1 2048 Hz interrupt occurred Write 1 to clear bit6 status bit Bit 7 BTREQ7 8192 Hz BTC interrupt status bit 0 No 8192 Hz BTC interrupt occurred 1 8192 Hz BTC interrupt occurred Write 1 to clear bit7 status bit TABLE 12 6 Base Timer Divide Address R W Bit7 Bit6 Bits Bit4 Bit2 Bito Default _ The interrupt time of BTEN 7 8192 Hz 34 87 ST2205U 12 3 Timer 12 3 1 Function Description The Timer 15 a 12 bit up counter The low nibble of and be generated Timer will stop counting when system clock TxCL is a real time read write counter When an overflow from stops Please refer to FIGURE 12 3 FFF to 000 a timer interrupt request IRTO will MUX 8 1 SYSCK 4096 INO 12 Bit Up Counter SYSCK 1024 INI SYSCK 32 IN2 OUT IRTx PRES gt SYSCK 8 IN3 TxCH 7 SYSCK 4 IN4 OUT SYSCK 2 INS TIEN x Enable BGRCK
81. d Before Flash data transfer clear ECC codes and the counter by writing 1 to ECCCLR After write of 512 bytes is performed control ECCSEL and get the results from ECCO and In case of read transfer after reading 512 bytes retrieve two 3 byte ECC codes in the redundant area and write them into ECCO 1 respectively Each write to ECCL M H will make a XOR operation between the original data and the byte written into After ECCH is wrote a byte ECC checking starts The result will be reported at FSR 1 0 in one SYSCK cycle Meanwhile ECCL M H also report the error bit position if there is one 73 87 ST2205U 20 3 Nand Flash Interface Control Registers 55 Name R W 7 Bit6 Bit5 Bits Bit2 Default in ECCSEL E CCCLR E 0000 00 TYPE Flash type selection 0 Nand type Flash 1 And type Flash FEN Flash Interface enable bit 0 Disable Flash interface 1 Enable Flash interface ECCEN ECC function enable bit 0 Disable ECC generation and detection 1 Enable ECC generation and detection ECCSEL ECC channel selection bit 0 Select ECCO 1 Select ECC1 PFECC Port F ECC function control bit 0 Data of read write instruction to port F will not included by ECC function 1 Data of read write instruction to port F will join the generation of ECC ECC buffer clear bit W 0 No effect W 1 Clear all
82. e Virtual Page Width setting FIGURE 15 1 illustrates the relationship between the portion of a large graphic to be displayed on the screen and the actual area that can be seen ST2205U Each one or two even four bits in the display memory correspond to a pixel on the LCD panel TABLE 15 2 shows the mapping of the display data to the pixel on LCD When clear control bits GL 3 2 LCTR 3 2 and enable B W mode every bit of display buffer represents one pixel on the screen case of 4 gray level mode there needs two bits to present each pixel on the screen And there needs 4 bits for 16 gray level mode to display one pixel Virtual Page Width 4 LVPW 16 Starting Address LSSA Screen Height 2 Screen Width LXMAX 8 FIGURE 15 1 LCD Screen Format TABLE 15 2 Mapping Memory Data on the Screen EE 1 bit per pixel mode Bit Bits Bits Bio ia AE AE ae 0 a 0 a 0 a 0 a 0 0 0 aa 0 8 a 9 0 m 2 bit AN mode C 4 bit per pixel mode 49 87 Sironi 15 3 LCD Interface Timing The LCD controller continuously pumps the pixel data into the LCD panel via the LCD data bus The bus is timed by the CP LOAD and FLM signals Two kinds of data width 1 FLM LOAD LOAD CP LD3 LD2 LD1 LDO LDO d ee Line 1 Line 2 Line 3 Line Y 1 Line Y
83. e following list TABLE TABLE 28 1 PIN ASSIGNMENT OF INTERFACE High Voltage Power Supply 1 OTP Program Program Verify Test modes 9V 2 OTP Read VPP need connect to VDD Data 7 0 Address 13 0 85 87 Sironi 29 REVISIONS REVISION 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2a 0 1 DESCRIPTION Modify DC characteristics Add a new circuit in application circuit Specify DC characteristics Modify NAND Flash control pins configuration in FIGURE 20 1 Modify UART description Modify LVR description Modify TABLE 8 1 T1 amp T3 are internal only Modify PSG block diagram FIGURE 14 2 Modify PSG output mode configuration in TABLE 14 4 Modify section24 Modify LVD and power connect circuit Add section28 OTP information Modify LCDCK on TABLE 11 3 Add frame rate equation of FRC PWM mode Modify INTX interrupt input pin to PEO 1 2 on TABLE 8 1 Modify LCDCK on TABLE 11 3 Add Multiplicator description Add the LCD start byte setting attention on TABLE 15 3 Modify equation of LCD frame rate Modify names of ICE and test relocate MMD CS0 Modify PE1 function output is OSCN clock Add crystal mode warm up cycle in TABLE 11 2 Modify PCL initial value is 1111 1111 Modify register PCMH amp PCML R W function Add interrupt Add chapters of DMA and Nand Flash interface Change ROM size from 512KB to 16KB First release 86 87 PAGE 81 83 81 73 60 63 80 18 38 41 78 83 84 29 52 18 29
84. ed PE0 1 2 edge interrupt Internal External 7FF7 7FF6 _ 10 Timer0 interrupt 7FF5 S7FF4 11 Timertinterrupt Internal T Internal External 7FF3 7FF2 142 __ 7FF1 7FFO PT 7FERS7FEE 14 Timer2 interrupt 13 Timer3 interrupt Port A transition interrupt eT p emal S7FED S7FEC 15 Timer interrupt Internal 7FEB 7FEA LCD buffer interrupt L S 7FE9 7FE8 1 SRX 7FE7 7FE6 UTX 7FESS7FES 3 SPI transmit buffer empty interrupt 3 UART transmitter interrupt 1 receive buffer ready interrupt 4 URX 97 0 2 4 UART receiver interrupt USB External Reserved 7FE1 7FEO 7FDE 7FEDE 6 7FDD 7FDC 5 USB interrupt PCM interrupt S7FDB S7FDA 8 __ interrupt TABLE 8 2 Interrupt Request Register IREQ Address Name Bit 7 15 Bit 6 14 Bit 5 13 4 12 Bit 3 11 Bit 2 10 Bit 1 9 Bit0 8 Default 03C IREQL 03D IRRTC IRPCM W CLRRTC CLRPCM IRXXX Interrupt request bit R 1 2 An interrupt occurred R O 2 No interrupt occurred R IRLCD IRBT IRPT IRT3 IRT2 IRTO IRX 00000000 CLRXXX Clear interrupt request bit W 1 Do nothing W O Clear interrupt request bit TABLE 8 3 Interrupt Enable Register IENA Address R W Bit 7 15 Bit 6 14 Bit 5 13 Bit 4
85. ed 1 EPOOUT buffer 15 full a service 15 needed 68 87 ST2205U 18 2 5 Endpoint0 Control Register TABLE 18 7 Control Register RW Biz Bie Bts Bis Bia O UN er sere peo om or pU o STALL Endpoint0 stall command bit 0 EndpointO is normal 1 EndpointO is stalled FLUSH EndpointO buffer flush command bit Write 1 to flush endpointO IN and OUT buffers TXZERO Sending zero length data command bit Write 1 make endpoint0 IN buffer to send zero length data DIR Endpoint0 OUT buffer direction bit 0 OUT data received 1 IN data received SETUP OUT package type flag 0 Last OUT package 15 data package 1 Last OUT package 15 setup package DRQ 1 0 00 Adevice descriptor received 01 A configuration descriptor received 10 Astring descriptor received 11 A non standard descriptor received 18 2 6 Endpoint0 OUT Buffer Data Length Register TABLE 18 8 Endpoint0 OUT Buffer Data Length Register Address R W Bit7 Bite Bits Bits Bito Default 75 EPOLEN RW LENIS LENP LEN LEN 0000 LEN 3 0 Received data length of EndpointO OUT buffer 0 Zero data length 1 Data is one byte long 16 Data is 16 bytes long 18 2 7 Bulk IN OUT Endpoints Control Register TABLE 18 9 Bulk IN OUT Endpoints Control Register Address Name R W Bit7 Bi
86. ed Hardware will push PC P registers to stack and sets interrupt disable flag 1 Program counter will be loaded with the INTX vector from locations 7FF8 and 7FF9 m TO Interrupt The IRTO TIMERO interrupt request flag will be set while TimerO overflows With IETO TIMERO interrupt enable being set the TO interrupt will execute and interrupt mask flag will be cleared Hardware will push P Register to stack and set interrupt mask flag 1 Program counter will be loaded with the TO vector from locations 7FF6 and 7FF7 m 71 Interrupt The IRT1 TIMER1 interrupt request flag will be set while T1 overflows With IET1 TIMER1 interrupt enable being set the T1 interrupt will execute and interrupt mask flag will be cleared Hardware will push PC P Register to stack and set interrupt mask flag 1 Program counter will be loaded with the T1 vector from locations 7FF4 and 7FF5 m T2lnterrupt The IRT2 TIMER2 interrupt request flag will be set while TimerO overflows With IETO TIMER2 interrupt enable being set the T2 interrupt will execute and interrupt mask flag will be cleared Hardware will push P Register to stack and set interrupt mask flag 1 Program counter will be loaded with the T2 vector from locations 7FF2 and 7FF3 m T3lnterrupt The IRT3 TIMER3 interrupt request flag will be set while T3 overflows With IET3 TIMERS interrupt enable being set the
87. ed value This value can also be read back by read instruction Besides Port C E the output pins are CMOS type Port C E have two options of output types open drain and CMOS and is controlled by port type select registers PSC PSE Clearing bits of registers PSC PSE is for disabling PMOS of output stage and left only NMOS while setting bits is for CMOS ST2205U PORT TYPE SELECT REGISTER PORT CONTROL REGISTER PCR PORT DATA REGISTER PDR FIGURE 9 2 Configuration of Port C E Port A is designed for keyboard scan with de bounce and transition triggered interrupt while Port C D E F are multiplexed with other system functions and are controlled by PFC PFD FCTR and PMCR 2 0 Port L is shared with LCD specific signals of LCDC Turning off LCDC by setting LPWR LCTR 7 reserves Port L for GPIO Selecting respective pins to be GPIO or signals of system function will not affect original settings of directions and types This extends the flexibility of the usage of function signals Note All the properties of pins are still programmable and must be ascertained before they are assigned to system functions especially the direction of pins TABLE 9 3 Port Control Registers Address __ Bits Bit2 Bito Default Bit 7 0 PCx 7 0 Port x direction control bits 0 Input mode 1 Output mode TABLE 9 4 Port Data R
88. efault BGR output freguency settings See Equation9 1 9 3 TABLE 11 6 SPI Clock Control Register Address R W Bit7 Bits Bit2 Bit Bito Default 053 SCKRJRW 5 5 000 0000 Bit 6 4 SCK 2 0 SPI clock selection SCK 2 0 SPICK 000 SYSCK 2 30 87 ST2205U 12 COUNTER 12 1 Prescaler 12 1 1 Function Description The ST2205U has four 12 bit timers eight base timers with 7 generate 6 different clock soure to support the Timers counting fixed timer bases and one adjustable There is a prescaler that to interrupt Refer to TABLE 12 1 TABLE 12 1 Summary of Timer Registers Address Name R W Bit7 Bit6 Bits Bit2 Bit BitO Default 20 RW TOC 7 TOC 6 TOC 5 TOC 2 TOC O 0000 0000 21 TOCH RW LOAD TOCK 2 TOCK 1 TOC 11 TOC 9 TOC 8 0000 0000 22 RW T1C 6 T1C 5 4 T1C 2 0 0000 0000 23 RW LOAD T1CK 2 T1CK 1 T1C 8 0000 0000 24 720 RW T2C 7 T2C 6 T2C 5 T2C 4 T2C 3 T2C 2 T2C 1 T2C 0 0000 0000 25 T2CH RW LOAD T2CK 2 T2CK 1
89. egisters Address Bit6 Bit5 Bit4_ Bit 7 0 Px 7 0 Port data pull resistor control bits R W I O Modes Input Mode 0 Disable pull up resistor Write Select pull down resistor Port C only Output Mode Input data Output data 1 Select pull up resistor TABLE 9 5 Port Type Select Registers Address Bit6 Bit5 Bit 7 0 PSx 7 0 Port 1 O types selection bits Input Mode Output Mode 0 Disable pull up down resisters 0 Open drain 1 Enable pull up down resisters 1 CMOS 22 87 ST2205U TABLE 9 6 Port Function Select Registers Address R W 7 Bite Bits Bit2 Bito Default 0E PFC RW RXDO SRDY 55 MOSI MISO SCK 0000 000 __502 PFD RW RXD1 TXD cse CS5 CS4 053 52 51 0000 0000 PMCR RW PULL PDBN INTEG CSM1 CSMO PFE 2 1000 0000 Bit 7 0 PFC D 7 0 PFE 2 0 Port function select bits 0 GPIO 1 Indicated function signal is connected TABLE 9 7 Port Miscellaneous Control Register PMCR 3A RW PULL PDBN INTEG CSM1 CSMO PFE 2 PFE 1 PFE O 1000 0000 Bit 7 PULL Enable disable all pull up resisters of Port A F L 1 Enable pull up resisters 0 Disable pull up resisters 9 1 Port A Transistion In
90. enerating an effective address When executing an instruction which specifies indexed addressing the CPU fetches the OP code and the base address and modifies the address by adding the index register to it prior to performing the desired operation Pre or post indexing of indirect addresses is possible m Stack Pointer S The Stack Pointer is an 8 bit register which is used to control the addressing of the variable length stack It s range from 100H to 1FFH total for 256 bytes 128 level deep The stack pointer is automatically increment and decrement under control of the microprocessor to perform stack manipulations under ST2205U Accumulator A Index Register Y Index Register X Program Counter PC Stack Pointer S direction of either the program or interrupts IRQ The stack allows simple implementation of nested subroutines and multiple level interrupts The stack pointer 15 initialized by the user s software E Program Counter PC The 16 bit Program Counter register provides the address which step the microprocessor through sequential program instructions Each time the microprocessor fetches and instruction from program memory the lower byte of the program counter PCL is placed on the low order bits of the address bus and the higher byte of the program counter PCH is placed on the high order 8 bits The counter is increment each time an instruction or data is fetched from program memory m Status Register
91. external devices such as Flash memory analog to digital converter and other peripherals including another ST2205U The SPI consists of a master or slave configurable interface so that connections of both master and slave devices are allowable Five signals multiplexed with Port C are used by SPI With equipped DATA READY and SS slave select control signals and CPU Interface 16 bit Shift Register MSB First transmit receive buffers faster data exchange with fewer software interrupts is easy to be made Data length is widely supported from 7 bit up to 16 bit to satisfy various applications One clock generator is provided for the synchronous communication clock SCK which is sourced from OSCK FIGURE 16 1 illustrates the block diagram of SPI DATA_READY Interface Control FIGURE 16 1 SPI Block Diagram 16 1 SPI Operations The SPI contains one 16 bit shift register and two 16 bit buffers for transmission and receiving respectively Data with variable length from 7 bit to 16 bit can be exchanged with external devices through two data lines Data length is controlled by bit count register BC 3 0 bit3 0 of SPI clock control register SCKR The current exchange will be over while the exchanged bit number reaches bit count setting The synchronous communication clock SCK is used to synchronize two devices and transfer data in and out of the shift register Data is clocked by SCK with a programmable data rate which is as
92. for the modulation of OSCK There are two modulation modes which can be selected by BMOD BCTR 1 The modulation strength is also controllable by setting or resetting BSTR BCTR 2 The relation between locked frequency and BRS can be found in the following equation CLK32 BRS Equation9 1 OSCK and are close related Value of limits the frequency range of the OSCK applied which 15 also the locking range of BGR and is given by the following equation where is the modulation strength coefficient 1 2 lt Ficu a l Fuicu Equation9 2 Although the locked frequency is limited to be around OSCK lower frequency can still be obtained by one 8 bit integer divider which is assigned by BDIV Thus BGRCK can be expressed by Equation9 3 BGRCK FHIGH BDIV Equation9 3 SPICK The block has one three bit divider to generate SPICK directly from OSCK for transmission and other operations This divider is controlled by SCKR 6 4 Refer to TABLE 11 6 for settings of SPICK m 5 If PFE 1 is set and PE1 is output A divided clock of OSC is outputted from PE1 and the 2 bit divider is controlled by OSCN 1 0 BCTR 5 4 BGR BSR 7 0 BCTR 2 0 Target IN OUT REF ui Er PSGCK Divider INA PSGC 6 4 OUT XMD OSC OSTP SYS 6 8 1 2 16Mhz Integer Divider BGRCK CLK32 BRS BDIV BDIV 7 0 OSCK SPICK 4 6 8 Mhz
93. h PC via USB is becoming more and more popular The ST2205U features one PLL a 3 3V regulator and a USB 1 1 device engine to satisfy the strong demand of fast data transfer market Both and Mass storage classes are supported as well as the firmware libraries and the Windows drivers The built in four channels PSG and a 12 bit current DAC provide a nice quality voice together with a 4 channel wavetable melody in the background Both voice and melody functions have buffers to make program easier well structured and also a 16x8 multiplier is to control the volumn of each channel Besides hardware ADPCM algorithm and a MIDI converter Windows software are also provided to speed up the development In addition to current DAC two dedicated pins with large driving capacity can drive a buzzer speaker directly for minimum cost The ST2205 has one Low Voltage Detector LVD for power management The status of internal or external power can be detected and reported to the management software Power bouncing during power on is a major problem when designing a reliable system The ST2205U equips Low Voltage Reset LVR function to keep whole system in reset status when power is low After the power backs to normal the system may recover its original states and keeps working correctly Besides L VR Watch Dog Timer WDT is also built in and is an essential function for a good design Power consumption is another big issue for a bat
94. h a line of shifted data to the segment drivers outputs and is also used to shift the line enable signal of common driver All the driver outputs then control the liquid crystal to form the desired frame on panel B AC PL5 The LCD alternate signal toggles the polarity of liquid crystal on the panel This signal can be programmed to toggle for a period of 1 to 31 lines or one frame See section TABLE 15 10 for register settings m CP The LCD shift clock pulse signal is the clock output to which the output data to the LCD panel is synchronized Data for segment drivers is shifted into the internal line buffer at each falling edge of CP LD7 0 PE6 3 PL3 0 The LCD data bus lines transfer pixel data to the LCD panel so that it can be displayed Three kinds of data busses 1 4 and 8 bit are supported and are controlled by LMOD 1 0 LCKR 5 4 In case of 1 bit mode uses only LDO to transfer data LD3 1 can still be programmed to be normal inputs or outputs The output pixel data can be inverted through programming Setting REV LCTR will reverse the output data on data bus ST2205U dedicated output pins while the rest 13 pins are shared with Port L and Port E E POFF Power control The LCD power control signal is used to turn on off the external DC DC converter which generates a high voltage for driving liquid crystal outputs 1 when clearing LPWR LCTR and outputs 0 by setting this bit
95. high byte and MULL is multiplicand automatically when the answer has appeared multiplier After the multiplier is written and wait 6 OP cycle TABLE 14 8 Multiplicator Control Register Name R W Bit7 Bit6 Bit5 Bit2 BitO Default 6E MULL MUL 7 MUL 6 MUL 5 MUL 4 MUL 3 MUL 2 MUL 1 MUL O 0000 0000 6F RAW MUL 15 MUL 14 MUL 13 MUL 12 MUL 11 MUL 10 MUL 9 MUL 8 0000 0000 7 0 MULL 7 0 The multiplier of multiplication MULH 7 0 The multiplicand of multiplication While the multiplier is written the function will be active and the answer will appear MULL after 6 OP cycle TABLE 14 9 12 bit PCM FIFO Register Address R W Bit7 Bit6 Bit5 4 BitO Default sec OUTS 7 OUTS 6 OUTS 5 OUTS 4 OUTS 3 OUTS 2 OUTS 1 OUTS 0 0000 0000 W 6 PCM 5 PCM 4 PCM 2 PCM 1 PCM O 0000 0000 seo LA PFEM FIFOC 3 FIFOC 2 FIFOC 1 FIFOC 0 OUTS 9 OUTS 8 0000 0000 whee p Poms 0000 0000 READ PFEM 8X12 bit PCM FIFO empty indication 0 2 8X12 bit PMC FIFO is not empty 1 2 8X12 bit PCM FIFO is empty PFWA 8X12 bit PCM FIFO write available 1 Empty byte of the FIFO are less than 4
96. hour counter 1x0 Select alarm minute registers 1x1 Select alarm hour registers TABLE 23 2 Real Time Clock Data Register RTC Address Name R W Bit7 Bit6 Bit5 Bit2 Biti BitO Default 522 RW RTC 1 RTO O 00 0000 RTC 5 0 Read current counter value or write to set counter Second counter RSEL 000 counter 0 59 Minute counter RSEL 001 counter 0 59 Hour counter RSEL 010 counter 0 23 Alarm minute counter RSEL 1x0 counter 0 59 Alarm hour counter RSEL 1x1 counter 0 23 77 87 Sironi ST2205U 24 LOW VOLTAGE DETECTOR LVD ST2205U has a built in low voltage detector for power management Two voltage signals can be selected by the control bit LVDS LVCTR 1 First is the power applied to ST2205U and has four detection levels can be selected by LVD 1 0 LVCTR 3 2 Second is the signal applied to input pin VIN and has four detection levels can be selected too When LVDEN LVCTR 0 is set is enabled and the detection result will be outputted at the same bit after 30us Using read instruction twice can get this result first read will enable initial stableness control Second read equal 0 represents low voltage Once LVD is enabled it ST2205U VIN FIGURE 24 1 Application of LVD 1 Example1 If LVD 1 0 LVCTR 3 2 00 The detection voltage for FIGURE 24 1
97. ignal 1 LCD display off BLANK signal outputs low level Bit5 REV LCD display reverse 0 Normal display 1 Reverse display Bit 3 2 GL 3 2 LCD gray level selection bit 00 BW 01 4 10 16gray 11 GL 1 0 LCD gray level selection bit 00 FRC 01 FRC PWM1 10 FRC PWM2 11 FRC PWM3 15 4 8 LCD Frame Rate Adjust Register The LCD frame rate adjust register LFRA specifies the m 1 bit 4 bit 8 bit Mode extended time of each scan line Thus the frame rate slows FRC mode down to be the desired value LCDCK Frame Rate Note LFRA must be a number greater than 1 2LXMAX 4LFRA 5 2LYMAX Equation14 1 The adjusted frame rate for 1 4 and 8 bit modes can be FRC PWM mode found in the following equation LCDCK FrameRate 2LXMAX ALFRA4 5 ALYMAX Equation 14 2 15 4 9 LCD Frame Rate Adjust Register Address Name R W Bit7 Bits Bit2 Bit BitO Default 5049 FRA w FRAIS FRA 2 FRA O 00 0000 Bit 5 0 LFRA 5 0 Extended time of each scan line 52 87 S fronix ST2205U 15 4 10 LCD AC Signal Rate Register The LCD alternating signal rate register LAC specifies the time of horizontal lines the alternating signal toggles TABLE 15 10 LCD AC Signal Rate Register Address Name R W Bit7 Bits Bit2 Bi
98. ill not be overwrote while OERR equals 1 OERR can be cleared by reading SDATAL or by any write to SSR Some SPI devices have DATA READY output to suspend the incoming transmission Setting SRDY PFC 5 may include timing of DATA READY while clearing this bit to discard it Communication clock and data transmission only starts after DATA READY returns to low level The active level of DATA READY can be inverted to be high level active by setting inversion control bit DRINV SCTR 3 When transmission data in shift register will be shifted to master data output MOSI PC3 with most significant bit MSB first while data from serial data input MISO PC2 56 87 will be shifted in as well After the exchanged bits reach bit count setting current data is complete and then moves to receive buffer The exchange continues with auto reload function of shift register if TXEMP is cleared That is MSB of next data will be sent out and be received in right after the LSB of the previous one with no pause After the exchange was triggered the slave select signal SS outputs low level to enable the external slave device It keeps at low level during exchanges of data and data and returns to high when exchanges cease Slave Mode In slave mode SS PC5 SCK PC1 become input 16 1 4 SPI Interrupts Four interrupts are supported by SPI with two interrupt vectors Transmit buffer empty interrupt happens when
99. it SUSIEN USB suspend interrupt control bit BKIIEN USB Bulk In interrupt control bit BKOIEN USB Bulk Out interrupt control bit EPOIEN USB Endpoint 0 interrupt control bit 67 87 ST2205U 18 2 3 USB Interrupt Request Register TABLE 18 5 USB Request Register USBIRQ BRIRQ RESIRQ SUSIRQ BKOIRQ EPOIRQ 00 0000 BRCLR RESCLR SUSCLR BKICLR BKOCLR EPOCLR 00 0000 BRIRQ USB bus reset interrupt request bit RESIRQ USB resume interrupt request bit SUSIRQ USB suspend interrupt request bit BKIIRQ USB Bulk In interrupt request bit BKOIRQ USB Bulk Out interrupt request bit EPOIRQ USB Endpoint 0 interrupt request bit USB bus reset interrupt clear bit RESCLR USB resume interrupt clear bit SUSCLR USB suspend interrupt clear bit BKICLR USB Bulk In interrupt clear bit BKOCLR USB Bulk Out interrupt clear bit EPOCLR USB Endpoint 0 interrupt clear bit 18 2 4 USB Buffer Status Register TABLE 18 6 USB Buffer Status Register Address Name R W Bite Bits Bito Default BUFFER Status BKI BKI buffer status bit O BKI buffer 15 full no service 15 needed 1 BKI buffer is empty a service is needed BKO BKO buffer status bit 0 BKO buffer is empty no service 15 needed 1 buffer 1 full a service 15 needed EPOOUT EPOOUT buffer status bit 0 EPOOUT buffer is empty no service 15 need
100. med ECC codes will be ready at the end of transmission then they are to be written to Flash and stored in the redundant area In case of data read ECC codes calculated by MCU are to be compared with those in redundant area and check if there is any bit error even correct this error priority PD7 6 will be FWR FRD signals if FEN 1 regardless of settings of PFD Port F works the same way I O directions will not be controlled by but by read write access of data when Flash interface enabled It is floating when not being accessed output when write to port F and is input when read from port F ST2205U FIGURE 20 1 Connecting Nand and And Flash Memories 20 2 Error Correction Code ECC ECC code consists of 3 bytes per 256 bytes of data The XORed result of new and old ECC codes shows if there is a bit error between two 256 bytes of data even the location of the error bit Two sets of ECC codes ECCO and ECC1 are supported and are selected by ECCSEL So results of up to 512 bytes can be processed and stored Three bytes of each can be accessed at three registers ECCL M H There are two ways to trigger ECC calculation First is execute read write to PF when ECCEN 1 and PFECC 1 Second is moving Flash data DMA channel1 ECC of first 256 bytes will be calculated first in ECCO and then changes to ECC1 automatically for those after 256 The calculation stops after 512 bytes are reached even there are still more being move
101. mmed to input or output There are two options pull up down for inputs of Port C and only pull up for inputs of the other ports In case of output there are open drain CMOS options for outputs of PortC and only CMOS for other ports Port A is designed for keyboard scan with de bounce and transition triggered interrupt while Port C D E F L are shared with other system functions All the properties of I O pins are still programmable when they assigned to another function This enlarges the flexibility of the usage of function signals The internal 32K bytes RAM helps to drive large LCD panels up to 160xRGBx120 Together with 16 graylevel support the ST2205U can rich display information and the diversity of contents as well This is done with no need of external display RAM because of the special internal memory sharing design The variable display buffer technique also make large panel size with small internal RAM possible User may free major internal RAM for temporary computing or access while keeping the display content correct The ST2205U equips serial communication ports of one UART and one SPI to perform different communications ex RS 232 3 87 ST2205U and IrDA with system components or other products such as PC Notebook and popular PDA Two clocking outputs can produce synthesized PWM signals or high frequency carrier for IR remote control This helps products become more useful in our daily life Communication wit
102. ngle Figure 13 5 shows examples of DAC output waveforms with transistor amplifier lt requires two pin that PSGO and different output values Each pulse of the DAC is divided PSGOB When the DAC value is positive PSGOB goes into 128 segments per sample period For a positive output high with a duty cycle proportional to the output value while value x 0 to 127 PSGOB goes high for X segments while PSGO stays high When the DAC value is negative PSGO PSGO stays high For a negative output value x 0 to 127 goes low with a duty cycle proportional to the output value PSGO goes low for X segments while PSGOB stays low while PSGOB stays low This mode offers a resolution of 8 bits X DAC 32 DAC 96 DAC 127 Where X 0 to 127 DAC Where X 0 t X DAC 48 DAC 0 DAC 128 o 128 FIGURE 14 5 Two Pin Two Ended Mode Wave Form ST2205U SPK PSGO w 33K PSGOB FW VW 8050 IK FIGURE 14 6 Two Pin Two Ended mode Application Circuit 45 87 14 5 3 Two Pin Push Pull Mode 8 bit Accuracy Two Pin Push Pull mode 15 designed for buzzer It requires two pin that PSGO and PSGOB When the DAC value is 0 both pins are low When the DAC value 15 positive PSGOB goes high with a duty cycle proportional to the output value while PSGO stays low When the DAC value is negative goes high with a duty cycle proportional to the output value while PSGOB stays low This mode offe
103. nterrupt disable flag Program counter PC will be loaded with the LCD vector from locations 7FEA and 7FEB m SPlinterrupt There are two interrupts for SPI transmitter and receiver respectively IRSTX SPI transmitter interrupt request flag will be set when SPI transmit buffer is empty IRSRX receiver interrupt request flag will be set when SPI completes one receiving data and the receive buffer is ready The SPI interrupts will be executed once the related enable flag IESRX IESTX are set and the interrupt disable flag I is cleared Hardware will push PC P registers to stack and set I flag Program counter will be loaded with the SPI vector from locations 7FE7 7FE6 and 7FE9 7FE8 E UART Interrupts There are 2 interrupts for UART receiver interrupt URX and transmitter interrupt UTX URX happens when receive data is ready and the receiver needs to be serviced UTX happens when current transmission is completed Errors are indicated by bits of UART status register USTR Other sequences of UART interrupts are the same with those descriptions above USB Interrupts There are 6 interrupts for USB Bus Reset interrupt Resume interrupt Suspend interrupt Bulk only IN interrupt Bulk only OUT interrupt and EndpointO interrupt Write 1 to each interrupt enable bit of register USBIEN to turn on interrupts and read the request bits from USBIRQ Other sequences of UART Sironi interrup
104. o VCC 2 4V 3 6V CPU 6 2 Operating Frequency OSC rs m All I O port are input and pull up execute Operating Current instruction LCDC on All I O port are input and pull up 5 on LCDC on Standby Current gt ho I g lt lt lt lt lt gt gt gt gt gt gt WAITO mode SEG 240 CP SYS LFRA 30 All I O port are input and pull up OSCX on heavy load off WAIT1 mode LVR 2 8V Standby Current Isp All I O port are input and pull up on heavy load LCDC off WAIT1 mode LVR 2 1V All 1 O port are input and pull up OSCX on normal load off WAIT1 mode LVR 2 8V Standby Current 5 2 All port are input and pull up OSCX on normal load LCDC off WAIT1 mode LVR 2 1V All 1 O port are input and pull up OSCX off LCDC off WAIT1 mode LVR 2 8V Standby Current All port are input and pull up OSCX off off WAIT1 mode LVR 2 1V 0 7Vcc 0 Output high voltage Output low voltage SG DAC lou 40mA Input High Voltage 0 7Vcc LT Port A B C D E L Input Low Voltage Vi ES Port A B C D E L Pull up resistance 90 ___ Port A B C D E L input Voltage 0 7VCC Output high voltage om 0 7We Port A B C D L lon 4 5mA Output low voltage 0 3 V Port A B C D E L lo 6 5mA PSG DAG lo 40mA 81 87
105. ode is off 1 Repeat mode is on DELAY SS level delay one bit mode control bit 0 Delay mode is off 1 Delay mode is on TOGGLE SS level toggle mode control bit 0 Toggle mode is off 1 Toggle mode is on ACTIVE SS active level select bit 0 Active mode is off 1 Active mode is on 59 87 Sironi ST2205U 17 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER The ST2205U integrates one universal asynchronous receiver transmitter UART which can be used to communicate with external serial devices Serial data is transmitted and received at standard bit rates using the internal baud rate generator BGR which is controlled by CPU Interface Transmitter Receiver Baud Rate Generator 8bit Buffer 8bit Buffer BGR control register BCTR Settings of clock output of BGR BGRCK can be found in section 11 FIGURE 17 1 shows the block diagram of UART Summary of UART control registers is listed in TABLE 17 1 TXD1 RXD1 TXDO nterface IrDA dx FIGURE 17 1 UART Block Diagram TABLE 17 1 Summary Of UART Control Registers Address R W Bit6 Bit5 Bits Bit2 Bit BitO Default 60 RW TXEN PEN PMOD BRK 000000 USR R f FER OER RXBZ RXRDY TXBZ 000 0001 Write any value to clear USR 062 RW TXINV 063 BCTR E TES
106. ogical memory range as that of bank DRR and the banked size is also 32K bytes Besides mapping to physical memory DBKR can also map to whole internal 32K bytes RAM including control registers oet DBKR 15 to select internal RAM and clear it to back to the original DMA bank No push pull instruction is needed Address R W Bit7 Bit6 Bit5 5A DBKRL R W DBKR 7 DBKR 6 DBKR 5 DBKR 4 DBKR 3 DBKR 2 DBKR 1 DBKR O 0000 0000 358 DBKRH RW DBKR 15 DBKR t0 DBKR g DBKR 8 0 000 71 87 ST2205U DBKR 10 0 DMA Bank register Read write one of the four DMA bank registers which is selected by DMSEL 1 0 DBKR 15 DMA Bank switch bit 0 DBKR maps to physical memory 1 DBKR maps to internal RAM regardless of other bits 19 1 3 DMA Length Register The DMA length register has 15 bits therefore up to 32K bytes data can be moved in each transfer A write to high byte DCNTH may trigger DMA once After DMA starts DCNT 1 bytes of data will be moved from source location to destination Since DCNTH 55 readable two instructions SMB7 and RMB7 can be used as the trigger instruction of repeated transfers If DCTN is less than 256 STZ DCNTH is another instruction to trigger Address RW Bit7 Bit6 Bit5 Bits Bit2 BitO Default 5C DCNTL R W DCNT 7 DONT 6 DCNT 5 DCNT 4 DCNT 3 DCNT 2 DCNT 1 DCNT O
107. oth of these two pins which are multiplexed with PC6 and PD6 These pins connect to standard RS 232 or infrared transceiver modules 61 87 ST2205U B RXDO PC7 RXD1 PD7 gated with AND logic to produce one single signal These The UART receive data signal is input from one or both of pins also interface to standard RS 232 and infrared these two pins which are multiplexed with PC7 and PD7 If transceiver modules RXDO and RXD1 are enabled at a time both signals will be 17 4 UART Control Status Registers 17 4 1 UART Control Register TABLE 17 2 UART Control Register Address R W Bit7 Bits Bit2 Bit BitO Default 60 UCTR Rw TXEN PEN PMOD 00 0000 Bit 5 Receive enable control bit 0 Disable receiver 1 Enable receiver TXEN Parity control bit 0 Disable transmitter 1 Enable transmitter PEN Parity control bit 0 Disable parity 1 Enable parity PMOD Parity mode selection bit 0 Even parity 1 Odd parity UMOD 7 8 bit mode selection bit 0 7 bit mode the received data bit 7 will be set to zero 1 8 bit mode BRK Break character 0 Normal character 1 2 Transmit break character 17 4 2 IrDA Control Register TABLE 17 3 IrDA Control Register Address Name R W Bit7 Bit6 Bits Bit2 Bit BitO Default 062 IRCTR RW RXINV
108. r STN supported by internal buffer Hardware 4 16 gray levels with 5 bit palette up to 4096 colors supported Share system memory with display buffer and with no loss of the CPU time Support 1 4 8 bit LCD data bus Diverse functions including virtual screen panning scrolling contrast control alternating signal generator buffer switching and fast graphic data manipulation Programmable Sound Generator PSG Four channels with three playing modes 9 bit ADPCM 8 bit PCM and 8 bit melody One 16 byte buffer and 6 bit volume control per channel Wavetable melody support Two dedicated PWM outputs for direct driving 12 bit current DAC with two 4 word buffer Universal Asynchronous Receiver Transmitter UART Full duplex operation Baud rate generator with one digital PLL Standard baud rates of 600 bps to 115 2 kbps Both transmitter and receiver buffers supported Direct glueless support of IrDA physical layer protocol Two sets of I Os TX RX for two independent devices Serial Peripheral Interface SPI Inter IC sound 15 supported Master and slave modes Five serial signals including enable and data ready Both transmitter and receiver buffers supported Programmable data length from 7 bit to 16 bit Three power down modes WAIO mode WAI1 mode STP mode On chip ICE debug interface Sironi 3 SIGNAL DESCRIPTIONS ST2205U TABLE 3
109. reset occurred Reset WDT Bit 7 TEST These two bits should be both zero in normal operation Bit 1 0 TEST These two bits should be both zero in normal operation 76 87 ST2205U 23 REAL TIME CLOCK TABLE 23 1 Real Time Clock Control Register RCTR Address Name RW Bit7 Bit6 Bits Biti BitO Default ALMIRQ DAYIRQ HRIRQ 0000 0000 S2E RCTR wo Aus aL D RTCCLR ALMIEN DAYIEN MINIEN 0000 0000 MINIEN Minute interrupt 0 Disable minute interrupt 1 Enable minute interrupt HRIEN Hour interrupt 0 Disable hour interrupt 1 Enable hour interrupt DAYIEN 24 hour interrupt 0 Disable 24 hour interrupt 1 Enable 24 hour interrupt ALMIEN Alarm interrupt 0 Disable alarm interrupt 1 Enable alarm interrupt MINIRQ Minute interrupt request bit 0 No minute interrupt occurred 1 A minute interrupt occurred Hour interrupt request bit 0 No hour interrupt occurred 1 A hour interrupt occurred DAYIRQ 24 hour interrupt request bit 0 No 24 hour interrupt occurred 1 2 A 24 hour interrupt occurred ALMIRQ Alarm interrupt request bit 0 No alarm interrupt occurred 1 An alarm interrupt occurred RTCCLR Interrupt request clear bit write 1 to clear all RTC interrupt requests RSEL 2 0 Select one of the three counters 000 Select second counter 001 Select minute counter 010 Select
110. ros for a full bit time period zeros are transmitted as three sixteenth or less bit time pulses which is selected by PW 1 0 IRCTR 2 1 and ones remain low The polarity of transmitted pulses and expected receive pulses can be inverted so that a direct connection can be made to external IrDA transceiver modules that use active low pulses This is controlled by RXINV and TXINV IRCTR 7 6 IrDA mode is enabled by control bit IREN IRCTR 0 FIGURE 17 3 illustrates a character S in IrDA mode 60 87 Start Bit Parity Bit Stop Bit FIGURE 17 2 NRZ ASCII S with Odd Parity Two kinds of character 7 bit and 8 bit are supported by ST2205U This is controlled by mode selection bit UMOD UCTR 1 Parity options are controlled by enable bit 17 2 3 Transmitter Operation Transmitter operation is controlled by control bit TXEN UCTR 4 When transmitter is empty IRUTX IREQ 10 will be set to issue the interrupt request At this time we write a character to data register UDATA and transmitter accepts a character from the CPU bus Then this data is fetched to output buffer and transmitted immediately if the output buffer is empty At the moment the transmitter is empty again to wait next data When a character is available for transmission the start stop and parity if enabled bits are added into the character and then it is 17 2 4 Receiver Operation Receiver operation is controlled by control bit RXEN USTR
111. rrupt Reset Any interrupt a sos Retain f So Ree 75 87 Sironi 22 WATCHDOG TIMER The watchdog timer WDT is an added check that a program is running and sequencing properly When the application software is running it is responsible for keeping the 2 or 8 second watchdog timer from timing out If the 22 1 WDT Operations The WDT is enabled by setting the WDT enable flag WDTEN MISC 3 Two time settings 2 and 8 seconds are selectable with selection bit WDTPS MISC 2 WDT is clocked by the 2Hz clock from the base timer and therefore has 0 5 second resolution is recommended that the watchdog timer be periodically cleared by software once it is enabled Otherwise software reset will be generated ST2205U watchdog timer times out it is an indication that the software is no longer being executed in the intended sequence At this time the watchdog timer generates reset signal to the system when the timer reached a binary value of 4 or 16 Note The WDT can be reset by writing any value to MISC register After a system reset WDTEN is cleared Then the WDT returns to be idle TABLE 22 1 System Miscellaneous Register MISC Address R W Bit7 Bit6 Bits Ww E WDTPS WDT period selection bit 0 Timer period is 72ms 1 Timer period is 2s WDTEN WDT enable bit W 0 Disable WDT W 1 Enable WDT R 0 WDT reset did not occur R 1 WDT
112. rs a resolution of 8 bits ST2205U Figure 13 7 shows examples of DAC output waveforms with different output values Each pulse of the DAC is divided into 128 segments per sample period For a positive output value x 0 to 127 PSGOB goes high for X segments while PSGO stays low For a negative output value x 0 to 127 PSGO goes high for X segments while PSGOB stays low 32 24 1 2 High PSGO Low 128 96 High PSGOB one 32 X DAC 32 Where X 0 to 127 High PSGO Low High PSGOB Low DAG X DAC Where X 0 to 128 96 DAC 0 FIGURE 14 7 Two Pin Push Pull Mode Wave Form 5122050 ad Buzzer FIGURE 14 8 Two Pin Push Pull Application Circuit 46 87 Sironi 15 LCD The LCD controller LCDC provides display data and specific signals for external LCD drivers to drive the STN LCD panels The LCDC fetches display data directly from internal display buffer through one unique memory bus The special designed internal bus shares almost none of the CPU resources to make both fast display data process and high speed CPU operation possible ST2205U support three display modes including black and white 4 gray level and 16 gray level and is selected by GL 3 2 of control register LCTR Further it through PWM FRC technique that selected by GL 1 0 to generate 31 gray levels and provides one palette LPAL 4C to choose 16 gray levels which make the
113. s issued 55 SS is a bidirectional slave select signal which is multiplexed with PC4 In master mode SS is output to enable a slave device In slave mode SS is inputted a low level to trigger the exchange DATA_READY 5 DATA_READY 15 input signal which is multiplexed with PC5 It is used only in master mode and can be a GPIO in slave mode The operation of DATA READY can be enabled by setting PFC 5 The default active level is high and can be inverted by setting DRINV SCTR 3 Active level is inputted to indicate that the communicating slave is ready for data exchange 57 87 ST2205U 16 3 SPI Control Status Registers SPI control and status registers are summarized in TABLE 16 1 TABLE 16 2 Summary Of SPI Control Registers Address Name RW Bir 6 14 Bit 2 10 PROB Default SEIEN EXER RIEN DRINV SMOD 0000 0000 53 SCKR_ RW 5 SCK O 000 0000 A RXRDY SBZ MDERR BCERR 000 000 _________________ 5 ____ 6 __ _____ Write any value to reset SSR Ls pr DELAY 0000 0A RW PCC 7 PCC 6 PCC S 2 PCC O 0000 0000 soe Pre mW SADY SS mosi MISO SCK 0000000
114. sible while moving data from to Nand Flash via port F Registers for each channel are listed below Also refer to TABLE 19 1 DMA Control Registers Address RW Bit7 Bit6 Bits Bits Bit2 BitO Default 59 DPTRH R W DPTR 14 DPTR 13 DPTR 12 DPTR 11 DPTR 10 DPTR 9 DPTR 8 000 0000 5A JDBKRL R W DBKR 7 DBKR 6 DBKR 5 DBKR 4 DBKR 3 DBKR 2 DBKR 1 DBKR O 0000 0000 5B DBKRH R W DBKR IS DBKR 10 DBKR 9 DBKR 8 0 000 5D DCNTH RW DCNT 14 DCNT 13 DCNT 12 DCNT 11 DCNT 10 DCNT 9 DCNT 8 000 0000 5E DCTR RW DMSELft DMSEL O 00 5F DMOD RW FUNC DMDD 1 DMDD O DMDS 1 DMDSIO 00 0000 19 1 DMA Control Register 19 1 1 DMA Pointer Register The 15 bit pointer refer to the logical memory the range of 8000 FFFF i e the internal pointer has its bit15 always equals 1 Address RW Bit7 Bit6 Bits Bits Bit2 BitO Default 58 DPTR 7 DPTR 6 DPTR 5 DPTR 4 DPTR 3 DPTR 2 DPTR 1 DPTR O 0000 0000 59 DPTRH R W DPTR 14 DPTR 13 DPTR 12 DPTR 11 DPTR 10 DPTR 9 DPTR 8 000 0000 DPTR 14 0 DMA pointer register Read write one of the four DMA pointer registers which is selected by DMSEL 1 0 19 1 2 DMA Bank Register The DMA bank DBKR has the same l
115. signed by SCK 2 0 bit6 4 of SPI clock control register SCKR Refer to TABLE 11 6 for all clock rate settings 16 1 1 Clock Phase and Polarity Controls Four combinations of serial clock SCK phase and polarity are selectable by two control bits PHA and POL bit 2 1 of SPI control register SCTR FIGURE 16 2 and FIGURE 16 3 show the transmission format of two phase settings Transmission Format PHA 0 In this mode both master and the communicating slave should present MSB after the falling edge of SS Then the first edge of SCK will be the first capture strobe of input data If POL 0 this first edge is rising edge if POL 1 it will be a falling edge The SPI block is controlled by SPIEN SCTR 7 Setting SPIEN will enable SPI function and the clock divider Then the internal states of will be reset to initial values After that write data to SDATAL will initiate an exchange While exchanging the busy flag will be set and is reported in SBZ bit 4 of SPI status register SSR A slave select signal SS multiplexed with PC4 is used to identify individual selection of a slave SPI device Slave devices that are not selected do not interfere with SPI bus activities For a master SPI device SS can be used to indicate a multiple master bus contention which can be reported in mode fault bit MDERR bit3 of SPI status register SSR Note The clock settings should be identical for master and the communicating slave device
116. t6 Bits Bits BitO Default 76 R W STALL FLUSH TXZERO STALL FLUSH 000 00 STALL BKCON 7 3 Bulk IN OUT Endpoints stall command bit 0 Bulk IN OUT 1 normal 1 Bulk IN OUT 15 stalled FLUSH BKCON 6 2 Bulk IN OUT buffer flush command bit Write 1 to flush Bulk IN OUT buffers TXZERO Sending zero length data command bit Write 1 make Bulk IN endpoint to send zero length data 69 87 ST2205U 18 2 8 Bulk OUT Endpoint Data Length Register TABLE 18 10 Bulk OUT Endpoint Data Length Register Address Name R W Bit6 Bits Bits BitO Default 77 BKOLEN R W LEN S LENIS LEN 4 LEN S LEN 2 LEN O 000 0000 LEN 6 0 Received data length of buffer 0 Zero data length 1 Data is one byte long 64 Data 64 bytes lonc 70 87 ST2205U 19 DIRECT MEMORY ACCESS DMA To speed up the data transfer DMA works efficiently without TABLE 19 1 for more CPU involved and moves one byte of data in only two 15 bit source pointer DPTR DMSEL 0 0 SYSCK cycles After write to CPU pauses and 15 bit destination pointer DPTR DMSEL 0 1 then DMA starts Meanwhile the address and data bus is 11 bit source bank register DBKR DMSEL 0 0 freed for DMA job In each transfer up to 32KB data can be 11 bit destination bank register
117. ter 15 fixed FUNC Function control for DMA channel 0 1 DMAO FUNC 1 0 Three cycle mode enable 00 Normal mode 01 Enable DMA channel three cycle mode with XOR logic operation 10 Enable DMA channel three cycle mode with OR logic operation 11 Enable DMA channel three cycle mode with AND logic operation DMA1 FUNC 1 0 Single cycle mode enable either source or destination should be PF to make single cycle mode enable Ox Normal mode 1x Enable DMA channel Single cycle mode 72 87 Sironi 20 NAND FLASH INTERFACE The ST2205U has a simplified Nand Flash Flash for short in the following interface for both And and Nand types which only 9 or 10 specific signals are needed Combine other GPIOs this serial interface carries commands and data between MCU and Flash memory by CPU read write instructions or by DMA channel Data moved by DMA channel1 may has ECC codes 20 1 Nand Flash Interface Port F Flash memory is a serial accessed memory Typical interface signals for And and Nand types are listed in FIGURE 20 1 as well as the connection with ST2205U If FEN FCTR 7 is set port F will be the 8 bit serial data bus and PD7 FWR PD6 FRD will play write read signals while other control signals are controlled by GPIOs The And type flash interface needs only PD7 and further saves PD6 for GPIO Since Nand Flash interface has higher Nand Type ST2205U ST2205U generated at the same time When data write to Flash is perfor
118. terrupt Port A is designed for the return line inputs of keyboard scan Port A must be latched before transition and this can be done with transition triggered interrupt and de bounce option by one read instruction to Port A Steps and program example Difference between current value and the data kept previously are shown below of Port A will generate an interrupt request The last state of Operate Port A interrupt steps Example 1 Set input mode 2 Read Port A STZ PCA Set input mode 3 Clear interrupt request flag IRPT LDA 4 Set interrupt enable STA lt PA PA be PULL UP 5 Clear CPU interrupt disable 1 LDA lt PA Keep last state 6 Read Port A before instruction in ISR RMB4 lt IREQ Clear IRQ flag SMB4 IENA Enable INT CLI Interrupt subroutine LDA PA Keep last state RTI 9 1 1 Port A Interrupt De Bounce The ST2205U has a hardware de bounce block for Port A clock The de bounce time is OSCX x 512 cycles about 15 6 interrupt It is enabled with 1 and disable with 0 of PDBN ms Data filtered by de bounce presents a stable state then PMCR 6 The de bounce function is activated after first the interrupt can be issued Port A transition is detected It uses OSCX as the sampling TABLE 9 8 Port Miscellaneous Control Register PMCR Address Bit7 Bit6 Bit5 Bits Bit2 3A RW PULL PDBN INTEG
119. tery powered device The ST2205U has different power down modes and clock switch scheme to make the consuming power as low as possible The built in Real Time Clock RTC is not only for keeping time correctly but also an alternative of software timer with much lower working power The ST2205U equips an ICE debug interface for efficient development flow Besides hardware emulator a software simulator is also supported to save programmers setting up the system and makes programming be at anywhere With these integrated functions inside the ST2205U single chip microcontroller is a right solution for PDA translator databank and other consumer products ICE1 6 VIN RESET XMD OSCI XIO OSCXI OSCXO A 22 0 D 7 0 lt WR RD MMD CSO CS5 1 PD4 0 CS6 A23 PD5 INTX0 2 PE0 2 TCOO PEO OSCN PE1 BCO PE2 PSGO COUT PSGOB De bounce Port A 7 0 Transition 7 0 Debug SRAM ROM Detector EOW Interface 32K bytes 16K bytes PCO Voltage On Reset Reset ISO 5 MOSI PC3 s DMA 8 bit Static Bank Control KA 9 5 4 SS 0 1 Logic OSC DATA READY PC5 TXDO PC6 Clock KA RXDO PC7 Generator Baud Rate TXD1 PD6 OSCX Generator RXD1 PD7 VBUS RPULL 8 bit External 7 time base VOUT3 3 Memory Bus Base Timer oe USB 1 1 D Controller Multiplier D Timer4 Chip Extern
120. to Default 044 RW 0 0000 Bit 2 0 AC 4 0 Time of horizontal lines the AC signal toggles AC 4 0 AC signal 00000 11101 Every 59 lines 11110 Every 61 lines 11111 Every 63 lines 15 4 11 PWM Contrast Control Register The ST2205U achieves contrast control function by outputting PWM signal from BLANK The duty ratio of 22220 LPWM 2 1 E PWM Ratio 1 this PWM signal also is the contrast level is controlled by LXMAX LFRA 1 5 LPWMI 5 0 with up to 64 steps PWM ratio for both 1 4 bit Equation14 3 modes is shown in Equation14 3 If the PWM contrast control function is supported by LCD drivers the equivalent Original Duty duty of common waveforms may rise as the PWM ratio Equivalent Duty ENTER Equation14 4 decreases This is show in Equation14 4 Higher duty than the original number can lead to the contrast of LCD becomes lower TABLE 15 11 LCD PWM Contrast Control Register Address Name RW Bit7 Bit6 Bit5 Bit2 Biti BitO Default Bit 7 6 4GPS 1 0 4 gray level palet selection 00 1 4 level of Palet 01 5 8 level of Palet 10 2 9 12 level of Palet 11 2 13 16 level of Palet 5 0 LPWNM 5 0 LCD contrast control LPWM 5 0 Contrast Level 00000 00001 IA 11101 11110 11111 1 minimum 53 87 15 4 12 LCD Gray Level Palette The gray level palette is a 1
121. trol how many pixels the picture is shifted to the left Values from 0 to 7 can be filled into this register to denote the offset while O means no panning control TABLE 15 7 LCD Panning Offset Register Address Name RW __ Bra BRO 045 RW 2 000_ Bit 2 0 PAN 2 0 LCD panning offset from zero to 15 pixels max 51 87 Sitronix ST2205U 15 4 6 LCD Buffer Size Register The LCD buffer size register LBUF is used to specify how many lines of data is the display buffer TABLE 15 8 LCD Buffer Size Register Address Name R W Bit7 Bit6 Bits Bit2 Bit BitO Default Bit 7 0 LBUF 7 0 LCD buffer size LCD buffer size LBUF 2 LCD screen width 15 4 7 LCD Control Register The LCD control register LCTR controls the enabling switch of LCDC display panel on off or reverse and the PWM contrast control block TABLE 15 9 LCD Control Register Address R W Bit7 Bit6 Bits Bit2 Bit Bito Default 047 LCTR_ RW LPWR REV cus GLfi GL O 100 0000 Bit 7 LPWR enable disable bit 0 Enable POFF signal outputs high level 1 Disable LCDC POFF signal outputs low level Bit6 BLNK LCD display ON OFF bit 0 LCD display on BLANK signal outputs contrast control s
122. trol logical banked area of 4000 7FFF DRR 0 11 11 bit DRR bank register Control logical banked area of 8000 FFFF BRR 15 PRR 15 DRR 15 Internal RAM mapping control 0 Disable internal RAM mapping Banked area refers to extended memory space 1 Enable respective internal RAM mapping of each banked area 12 87 ST2205U ce Comareger 0080 8KB RAM User Memo 0100 Stack 2000 3FFF BRR 15 1 8KB RAM 2000 3FFF 8K Bytes DRR 15 1 01FF 0200 DBKR User Memory Display Buffer PRRI1SIEA 32K Bytes 1FFF 4000 7FFF IRR 2000 16KB RAM 4000 7FFF 16K Bytes BIOS Bank 000 1FEF N BRR 0000H PRR 000H BRR 0002000 E IRR 8 bytes 0003FFF 2 9 BRR 0001H DRR 000H E 0004000 DBKR 3FFF e 0005 BRR 0002H PRR 001H 4000 PA BRR 0003H IRR PRR 002H IRR Program Memory DRR 001H PRR DBKR 16K bytes aoe PRR 003H 000FFFF y IRR 7FFF 8000 2FF0000 P PRR BFCH IRR Data Memory EN DRR 5FEH 32K bytes PRR BFDH 2FF7FFF E 2FF8000 _ a E 2FF9FFF E BRR 17FCH PRR BFEH RS A000 2 J C7 DRR 5FFH 2 000 lt DBKR 2FFDFFF BRR T1 FEH 2FFE000 _ IRR 2 BRR 17FFH CPU Memory Mapping Physical Memory Mapping 32K Bytes 48M Bytes FIGURE 7 1 Memory Mapping
123. ts are the same with those descriptions above Interrupt The IRPCM interrupt request flag will be set while reload signal of timer occurs and data in 8X12bit FIFO 15 less than 4 word Then the interrupt will be executed if IEPCM interrupt enable is set and interrupt disable flag is cleared Hardware will push P Register to stack and set interrupt mask flag 1 Program counter will be loaded with 20 87 ST2205U the PCM vector from locations 7FDC and 7FDD Interrupts There 4 interrupts for RTC Minute interrupt Hour interrupt Day interrupt and Alarm interrupt Write 1 to each interrupt enable bit of register RCTR to turn on interrupts and read the request bits from the same register Other sequences of UART interrupts are the same with those descriptions above ST2205U 9 GPIO The ST2205U consists of 56 general purpose GPIO which are divided into seven ports Port A F and Port L Control registers of GPIO are shown as following and in TABLE 9 1 Port data registers PL Port direction control registers PCA PCF PCL Port type select registers PSC PSE Port function select registers PFC PFD Port miscellaneous control register PMCR TABLE 9 1 Summary Of Control Registers Of GPIO Address R W Bit7 Bit6 Bits Bit2 Bit Bito Default 209
124. ts should be ascertained ST2205U Start Bit Parity Bit Stop Bit FIGURE 17 3 IrDA ASCII 5 with Odd Parity PEN UCTR 3 and mode selection bit PMOD UCTR 2 Other operations for transmitter and receiver are described below serially shifted LSB first at the selected bit rate While transmitter is busy the busy status is reported at TXBZ USR 1 with logic value 1 If the transmitter is empty the transmitter outputs a continuous idle which 1 1 for normal polarity Moreover a continuous 0 can also be outputted as a break character by setting BRK bit UCTR 0 1 Buffer Overrun Error This error indicates that the receive trigger bit was not set and the receiver overwrote data in receive buffer i e the previous character was lost This also means the software is not keeping up with the incoming data rate Error is updated and reported by reading OER USR 4 for current received character 2 Parity Error If parity is enabled the parity bit of current received character is checked and the status is updated in register bit PER USR 5 3 Framing Error This error indicates that a framing error is detected and there may be corrupted data with missing stop bit Error is updated and reported by reading FER USR 6 for current received character before using signals Refer to section 9 for these settings TXDO PC6 TXD1 PD6 The UART transmit data signal is output to one or b
125. up to 44M bytes Six programmable chip selects with 4 modes Maximum single device of 16M bytes General Purpose I O GPIO ports 56 multiplexed CMOS bit programmable I Os Hardware de bounce option for Port A Bit programmable pull up down or open drain CMOS Timer Counter Four 12 bit and one 8 bit timers Seven fixed time bases Watchdog Timer WDT Two selectable time bases Programmable interrupt or reset Real time Clock RTC Full clock function second minute hour and day with three counters and interrupts One programmable alarm Three External Interrupt Sources Three clocking outputs Clock sources including 0 OSCN clock baud rate generator Prioritized interrupts with dedicated exception vectors External interrupts x3 edge triggered 5 87 ST2205U PortA interrupt transition triggered LCD buffer interrupt Base timer interrupt x8 Timer0 3 interrupts x4 SPI interrupts x2 UART interrupts x2 USB interrupts x6 POM interrupt RTC interrupts x4 Dual clock sources with warm up timer Low frequency crystal oscillator OSCX A UN C CU n UD n DR UR OUR 32768 Hz High frequency resistor or crystal resonator oscillator OSC selected by pin option 455 8 Hz LCD Controller LCDC Programmable display size COM 512 max SEG 1024 max 160xRGBx120 colo

ST2205U Integrated Microcontroller

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