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1. 1 Interrupt is enabled 0 disabled Interrupt source are 7 Reserved Reserved Underflow Overflow Empty Full Write Request Read Request FIFOn_IN_CLK This register selects the input clock to the FIFO At every positive edge of the input clock a word is read into the FIFO from the input source 15 5 4 0 CLOCK SEL 4 0 Field Description CLOCK SEL 4 0 Selects the input clock input to this FIFO channel Value definitions are PCI Write to FIFOn RW PORT PCI Read from FlIFOn RW PORT Prog Clock 3 Interrupt Prog Clock 2 Interrupt Prog Clock 1 Interrupt Prog Clock 0 Interrupt PWM1 Interrupt PW WMO Interrupt Reserved Reserved Incremental Encoder 1 Interrupt Incremental Encoder 0 Interrupt Reserved 82C54 Interrupt Advanced Interrupt 1 Interrupt Advanced Interrupt 0 Interrupt Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe Prog Clock 3 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 RTD Embedded Technologies Inc www rtd com 45 DMx820 User s Manual Accessing the Analog World Field Ci escription 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Heserved 25 MHz FIFOn OUT CLK This register selects the output clock to the FIFO At every positive edge of the output clock a new word available at the FIFO output 15 5 4 0 CLOCK SEL 4 0 CLOCK SEL 4 0 Selects the input clock input to this
2. Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex 0x0148 PRGCLK1 PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG CLK PERIOD 1 Ox014A PRGCLKi COUNT Programmable Clock 2 0x0180 PRGCLK2 ID b 15 0 ID Register 0x1000 0x0182 PRGCLK2 MODE b 15 2 Reserved b 1 0 00 Disabled 01 Continuous 10 Retrigger 11 One Shot 0x0184 PRGCLK2_CLK b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock Bus 15 0 0x0186 PRGCLK2_START_STOP b 15 13 Reserved b 12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x0188 PRGCLK2 PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG _CLK_ PERIOD 1 0x018A Programmable Clock 3 0x01CO PRGCLK3_ID b 15 0 ID Register 0x1000 0x01C2 PRGCLK3 MODE b 15 2 Reserved b 1 0 00 Disabled 01 Continuous 10 Retrigger 11 One Shot 0x01C4 PRGCLK3 SOURCE b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock Bus 15 0 0x01C6 PRGCLKS START STOP b 15 13 Reserved b 12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 nterrupt Bus 15 0 15 1 Clock Bus 15 1 0 Start Immediate
3. DM35820HR DM9820HR DM8820HR DM 820HR Versatile High Speed Digital I O User s Manual BDM 610010036 Rev D Ge dt UO UU ER D LI L g KA a D Lc d EE ET Mitte RTD Embedded Technologies Inc AS9100 and ISO 9001 Certified RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Ka V asooo lt V _1s09001 laa Accessing the Analog World Revision History Rev A Initial Release Rev B Better DREQ description Improved description of FIFO Improved description of FIFOn_CON_STAT Corrected PWM Period formula Added DM9820 information Rev C Added DM8820 Added AS9100 Rev D Changed to new manual format Added ability to retrigger programmable clocks Added register to read programmable clock current value Added FIFO empty flag as a peripheral output Added IDAN section Advanced Analog I O Advanced Digital I O aAIO aDIO a2DIO Autonomous SmartCal Catch the Express cpuModule dspFramework dspModule expressMate ExpressPlatform HiDANplus MIL Value for COTS prices multiPort PlatformBus and PC 104EZ are trademarks and Accessing the Analog World dataModule IDAN HiDAN RTD and the RTD logo are registered trademarks of RTD Embedded Technologies Inc formerly Real Time Devices Inc PS 2 is a trademark of
4. E 67 ONANI Dr c ee 67 RTD Embedded Technologies Inc www rtd com V DMx820 User s Manual Accessing the Analog World MA E E 69 WASTE EE 69 M R pee ei etter NR eee ee eee eee 70 DRAP EE 70 Tee 70 DONAA RE a 71 H al 71 IAD AN 73 peo mn 73 7 Troubleshooting 76 8 Additional Information 77 8 1 EE OE EE TT 0 2 POI and PODEXDIBSS Ee 61 er 16 meee pene ure Lectus EO MEI EE MEME EU ae eee een TT 8 3 PEA e 77 8 4 82054 Timer Counter EIERE 77 8 5 Mienrupt siters rz Hl Le TT 9 Limited Warranty 78 RTD Embedded Technologies Inc www rtd com vi DMx820 User s Manual Table of Figures Figure 1 DM7820HR and DM8820HR Connectors and Jumpers nnne nnn nnn nnn rnnt nnns narii 11 Figure 2 DM7820HR and DM8820HR Connectors and Jumpers sse nnn nnn nnn nnn tnnt tetra nita tnn nnn 12 Figure 3 Example le E 16 Figure 4 IDAN Belle 17 Figure 5 i BB Nie ce EE A omo 19 Figure 6 Example IDAN SYSTEM RE c 22 Fig re 7 DMX820HR Block DIT To Ih ME 23 Figure 8 Digital O Block Dig let 24 FIG S Tterapt FAQ E 25 Figure 10 Digital I O Block BID saatsuunctedtorcale O EE Ee E ete 40 Fig re 11 Incremental neller EE 53 Figure 12 PUM Eme 57 Figure 13 Counter latching executed for counter 1 Read Load 2 byte settmng 64 Table of Tables E Lee Ee e
5. sees an nent occurs Ox021E Reserved Advanced 1 0x0240 ADVINT1 ID b 15 0 ID Register 0x0001 ADVINT1 INT MODE b 1 0 Interrupt Mode 3 Event Mode 2 Match Mode 1 Strobe Mode O Disabled 0x0244 ADVINT1 CLK b 3 0 Sample Clock Source 15 0 Clock Bus 15 0 0x0246 0x0248 ADVINT1 PORTO MASK b 15 0 Port 0 Mask TER O Bit is used for match event 1 Bit is ignored 0x024A ADVINT1 PORT1 MASK b 15 0 Port 1 Mask e ONS O Bit is used for match event T Bit is ignored 0x024C ADVINT1 PORT2 MASK b 15 0 Port 2 Mask 0 Bit is used for match event 1 Bit is ignored LOxOME Reseved 0 T 0x0250 ADVINTi PORTO CMP 6 1510 Port 0 Compare Value used for interrupt on match L70x0252 ADVINTI PORTI CMP 6 15 0 Port 1 Compare Value used for interrupt on match L70x0254 ADVINTi PORT2 CMP b 15 0 Port 2 Compare Value used for interrupt on match RTD Embedded Technologies Inc www rtd com 33 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex 7 0x0256_ Reserved when an EIER occurs EE when an interrupt occurs when an interrupt occurs 0x025E Reserved E Dual Incremental Encoder 0 0x0280 INCENCO_ID b 15 0 ID Register 0x0002 0x0282 INCENCO INT b 11 8 Interrupt Status 1 Interrupt condition has occurred W
6. 1 DMAPADRn DMA PCI Address Description PCI Address Indicates from where in PCI Memory space DMA transfers reads or writes start Value is a physical address DMALAPADRn DMA Local Address Description DMA Channel Local Address Indicates from where in Local Memory space DMA transfers reads or writes start RTD Embedded Technologies Inc www rtd com 69 DMx820 User s Manual Accessing the Analog World DMASIZn DMA Transfer Size Transfer Size Bytes Indicates the number of bytes to transfer during a DMA operation Ring Management Valid When Ring Management Valid Mode is enabled DMAMODEO 20 1 indicates the validity of this DMA descriptor DMAPRn DMA Channel n Descriptor Pointer Description Write Descriptor Location Writing 1 indicates PCI Oh 1 Address space Writing O indicates Local Address space End of Chain Writing 1 indicates end of chain Writing O indicates not end of chain descriptor Same as DMA Block mode Interrupt after Terminal Count Writing 1 causes an interrupt to be asserted after the terminal count for this descriptor is reached Writing O disables interrupts from being asserted Direction of Transfer Writing 1 indicates transfers from the Local Bus to the PCI Bus Writing O indicates transfers from the PCI Bus to the Local Bus Next Descriptor Address XOh aligned DMADPRO 3 0 0h DMACSRn DMA Channel n Command Status uu
7. A Figure 13 Counter latching executed for counter 1 Read Load 2 byte setting Read Back Command Operation Use of the read back command enables the user to check the count value program mode output pin state and null count flag of the selected counter The command is written in the control word register and the format is as shown below For this command the counter selection occurs according to bits D3 D2 and D1 RTD Embedded Technologies Inc www rtd com 64 DMx820 User s Manual Accessing the Analog World Pa Tue COUNT STATUS CNT2 CNT1 CNTO NT CS 0 Ag A121 RD 1 WR 0 Ds 0 Selected counter latch operation D4 0 Selected counter status latch operation D3 1 Counter 2 selection Do 1 Counter 1 selection D4 1 Counter 0 selection Do U Fixed It is possible to latch multiple counters by using the read back command Latching of a read counter is automatically canceled but other counters are kept latched If multiple read back commands are written for the same counter commands other than the first one are ignored It is also possible to latch the status information of each counter by using the read back command The status of a certain counter is read when the counter is read The counter status format is as follows Bits D5 to DO indicate the mode programmed by the most recently written control word Bit D7 indicates the status of the output pin Use of this bit makes it possible t
8. E KH p a SS Ls p RENE EN 8s ND Pins 51 to 62 of the IDAN connector are not connected RTD Embedded Technologies Inc www rtd com 18 DMx820 User s Manual 44 688 Physical Characteristics e Weight Approximately 0 21 Kg 0 46 Ibs Accessing the Analog World e Dimensions 151 972 mm L x 129 978 mm W x 16 993 mm H 5 983 in L x 5 117 in W x 0 669 in H 1 339 RTD Embedded Technologies Inc www rtd com en e Pin 1 Pin 2 m i pin 68 68 pin Female Module Part Amphenol 5390378 7 Mating Part Amphenol 786090 7 Figure 5 IDAN Dimensions DMx820 User s Manual Accessing the Analog World 45 68S Connectors Table 7 CN10 Pin Assignments IDAN P2Pin CN10 IDAN P3 Pin CN11 Row1 Row2 Pin Row 1 Row 2 Signal Pin JL P27 TI DC P2 STROBE 2 2 STROBE 2 ERNSTER J B P21 50 enD 5 Pins 51 to 68 of the IDAN connector are not connected RTD Embedded Technologies Inc www rtd com 20 DMx820 User s Manual 4 6 Accessing the Analog World Bus Connectors PC 104 Express Bus Connectors DM9820HR Only The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the PC 104 Express Specification See PC 104 Specifications on page 77 This board is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector PC 1
9. and counts down to 0 com 50 DMx820 User s Manual RTD Embedded Technologies Inc www rtd Accessing the Analog World 6 3 6 ADVANCED INTERRUPT N Two Advanced Interrupt block are provided that can generate an interrupt on a match event or strobe The match and event interrupts are across all 48 digital I O The bits can be individually selected When an interrupt is generated the data on all of the ports is latched into the Capture registers Bits are tested regardless of if a pin is an input or output A Match interrupt is generated when all un masked bits in the Compare register match the input value of the port This is when the following expression is true for ALL ports x and bits y PORTx y xor ADVINTn_PORTx_CMPly and not ADVINTn_PORTx_MASK y 0 An Event interrupt is generated when any un masked input port bit changes This is when the following expression is true for ANY ports x and bits y Note that the Capture register is updated at every interrupt or event PORTx y xor ADVINTn_PORTx_CAPT y and not ADVINTn PORTx MASK y 1 ADVINTn_ID ID register to identify an Advanced Interrupt Block 15 0 ID Register15 0 Value of 0x0001 indicates Advanced Interrupt ADVINTn INT MODE Selects the mode for this interrupt Event mode will generate an interrupt when any selected input pin changes Match mode will generate an interrupt when the port s match a pre set value bits can be in
10. 0x01C8 PRGCLKS3 PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG CLK _ PERIOD 1 RTD Embedded Technologies Inc www rtd com 32 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex 0x01CA PRGCLK3 COUNT b 15 0 The current value of the clock counter Advanced Interrupt 0 0x0200 ADVINTO ID b 15 0 ID Register 0x0001 ADVINTO INT MODE b 1 0 Interrupt Mode 3 Event Mode 2 Match Mode 1 Strobe Mode O Disabled 0x0204 ADVINTO CLK b 3 0 Sample Clock Source 15 0 Clock Bus 15 0 0x0206 Reseved o 0x0208 ADVINTO PORTO MASK b 15 0 Port 0 Mask m TUER O Bit is used for match event 1 Bit is ignored 0x020A ADVINTO PORT1 MASK b 15 0 Port 1 Mask gd gtt 0 Bit is used for match event T Bit is ignored 0x020C ADVINTO PORT2 MASK b 15 0 Port 2 Mask e UE Bit is used for match event 1 Bit is ignored LOx020E Resewed T L0x0210 ADVINTO PORTO CMP b 160 Port 0 Compare Value used for interrupt on match L0x0212 ADVINTO PORTi CMP b 15 0 Port 1 Compare Value used for interrupt on match L0x0214 ADVINTO PORT2 CMP b 15 0 Port 2 Compare Value used for interrupt on match CQx0216 Resev T when an interrupt occurs E NE FORT e E when an interrupt occurs when an _
11. DATA 15 0 RW 0 Description DATA The read or write data to the FIFO 6 3 5 PROGRAMMABLE CLOCK N There are four programmable clocks on the DMx820HR They can be cascaded The Programmable Clocks use a master clock and divide it down by an integer An interrupt is generated at every positive edge of the clock output PROGCLKn ID ID register to identify a Programmable Clock Block 15 0 ID Register Description ID Register15 0 Value of 0x1000 indicates Programmable Clock PROGCLKn MODE Selects the mode that the Programmable Clock 15 2 1 0 MODE RW 00 Field Description Selects continuous or one shot mode The clock must be disabled when transitioning between modes 00 Disabled 01 Continuous The clock will generate a pulse train with the specified period After the Stop Trigger it will not retrigger 10 Retrigger The clock will generate a pulse train with the specified period After the Stop Trigger it will wait for another Start Trigger 11 One Shot The clock will generate a single pulse one period time after it is started Must be disabled and re enabled to produce a second pulse PRGCLKn CLK This register selects the master clock for the programmable clock The clock should be disabled before modifying this register 15 4 3 0 CLOCK_SEL 3 0 Field Desegppeon CLOCK SEL 3 0 Selects the master clock Value definitions are 15 Inverted St
12. Enable Writing 1 enables the channel to transfer data Writing O disables the channel from starting a DMA transfer and if in the process of transferring data suspends the transfer pause 1 Start Writing 1 causes the channel to start Yes transferring data if the channel is enabled Set RTD Embedded Technologies Inc www rtd com 70 DMx820 User s Manual Ol Accessing YL Analog World Abort Writing 1 causes the channel to abort Yes the current transfer The DMA Channel 0 Set Enable bit must be cleared DMACSRO 0 0 Sets the DMA Channel 0 Done bit DMACSRO 4 1 when the abort is complete Clear Interrupt Writing 1 clears DMA Yes Channel 0 interrupts Clr Done Reading 1 indicates the transfer is complete The transfer may be complete either because the DMA transfer finished successfully or that the DMA transfer was aborted when software set the Abort bit DMACSRO 2 1 Reading 0 indicates the Channel transfer is not complete Reserved 0006 DMAARB uu DMA Arbitration Reserved Do not vd DMA Channel Priority Writing 00b indicates a Yes Yes rotational priority scheme Writing 01b indicates Channel 0 has priority Writing 10b indicates Channel 1 has priority Value of 11b is reserved Reserved Do not 0000 0000 iain 0000 0011 001b 001b Description DMATHR DMA Threshold DMA Channel 0 PCI to Local Almost Full COPLAF Number of full Lword x 2 entries plus 1 times 2 in t
13. FIFO channel Value definitions are PCI Write to FIFOn RW PORT PCI Read from FlIFOn RW PORT Prog Clock 3 Interrupt Prog Clock 2 Interrupt Prog Clock 1 Interrupt Prog Clock O0 Interrupt PWM1 Interrupt PW MO Interrupt Reserved Reserved Incremental Encoder 1 Interrupt Incremental Encoder 0 Interrupt Reserved 82C54 Interrupt Advanced Interrupt 1 Interrupt Advanced Interrupt 0 Interrupt Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe Prog Clock 3 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved 25 MHz OO NW BOD N CO FlIFOn IN DATA DREQ This register selects the FIFO data input and PLX DMA Request source For the Write Request and Read Request signals internal buffers are monitored to signal when data can be sent into and read from the FIFO The Write Request is asserted when there are at least 256 words of space available in the FIFO and negated when there are less than 128 words available The Read Request is asserted when at least 256 words of data is in the FIFO and negated when there is less than 128 words of data Using these signals guarantees a burst of at least 128 words which provides for efficient communication over the PCI bus and robustly guards against over run and under run conditions However it does not allow for the FIFO to be completely filled of emptied RTD Embedded Technol
14. For these signals internal buffers are monitored to signal when data can be sent into and read from the FIFO The Write Request is asserted when there are at least 256 words of space available in the FIFO and negated when there are less than 128 words available The Read Request is asserted when at least 256 words of data is in the FIFO and negated when there is less than 128 words of data Using these signals guarantees a burst of at least 128 words which provides for efficient communication over the PCI bus and robustly guards against over run and under run conditions However it does not allow for the FIFO to be completely filled of emptied 15 10 9 8 7 1 0 WRITE_REQ READ REQ WRITE REQ Current Write Request Status O Not ready to receive data 1 Ready to receive data READ REQ Current Read Request Status 0 Not ready to send data 1 Ready to send data ENA FIFO Enable O FIFO is disabled and cleared 1 FIFO is enabled FIF n RW PORT This register provides the PCI bus access to the FIFO Reads from this register return the current data that is available at the output of the FIFO and can be programmed to clock the next data out of the FIFO Writes to this register can be programmed to write data into the FIFO Accesses to this register must be word 16 bit or larger RTD Embedded Technologies Inc www rtd com 4T DMx820 User s Manual Accessing the Analog World 15 0
15. Mail techsupport rtd com Be sure to check the RTD web site http www rtd com frequently for product updates including newer versions of the board manual and application software RTD Embedded Technologies Inc www rtd com He DMx820 User s Manual 8 1 8 2 8 3 8 4 8 9 Accessing the Analog World Additional Information PC 104 Specifications A copy of the latest PC 104 specifications can be found on the webpage for the PC 104 Embedded Consortium WWW pc104 org PCI and PCI Express Specification A copy of the latest PCI and PCI Express specifications can be found on the webpage for the PCI Special Interest Group WWW pcisig com PLX PCI9056 For more information about the PLX PCI9056 PCI Accelerator contact PLX Technologies at www plxtech com 82054 Timer Counter Programming For more information about programming the MSM82C54 Timer Counter Chips contact Oki Semiconductor at wwwz okisemi com Interrupt Programming For more information about interrupts and writing interrupt service routines refer to the following book Interrupt Driven PC System Design by Joseph McGivern ISBN 0929392507 RTD Embedded Technologies Inc www rtd com TT DMx820 User s Manual Accessing the Analog World 9 Limited Warranty RTD Embedded Technologies Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for on
16. Master during a Master or Target Abort Reading 0 indicates that the PCI 9056 asserted a Yes Target Abort after 256 consecutive Master Retries to a Target Heading 1 indicates that the PCI Bus wrote data to MBOXO Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 29 Reading 1 indicates that the PCI Bus wrote data to MBOX1 Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 30 Reading 1 indicates that the PCI Bus wrote data un to MBOX2 Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 Reading 1 indicates that the PCI Bus wrote data to MBOX3 Enabled only if the Mailbox Interrupt Enable bit is set INTCSR 3 1 RTD Embedded Technologies Inc www rtd com 19 DMx820 User s Manual Accessing the Analog World 7 Troubleshooting If you are having problems with your system please try the following initial steps e Simplify the System Remove modules one at a time from your system to see if there is a specific module that is causing a problem Perform you troubleshooting with the least number of modules in the system possible e Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is configured incorrectly If problems persist or you have questions about configuring this product contact RTD Embedded Technologies via the following methods Phone 1 814 234 8087 E
17. PWM1_B FIFO1_Out 11 PWM1_C FIFO1 Out 12 PWM1 C FIFO1 Out 13 PWM1 D FIFO1 Out 14 PWM1 D FIFO1 Out 15 STROBE STATUS This register can be used to check the status of the strobe signals as well as configure the strobes as outputs 15 10 9 8 STR2 TRI STR TRI R 0000 00 7 6 3 2 1 0 5 4 STR2 OUT STR1 OUT STR2 IN STR1 IN Field Description STR1 IN Current State of Strobe 1 0 Low 1 High STR2 IN Current State of Strobe 2 um 1 z Hit 1 High STR1 OUT Value to drive on Strobe 1 when an output Mull A Hit 1 High RTD Embedded Technologies Inc www rtd com 42 DMx820 User s Manual Accessing the Analog World Feld _ Description STR2 OUT Value to drive on Strobe 2 when an output 0 Low 1 High STR1_TRI Selects Input or Output for strobe 1 0 Input 1 Output STR2_TRI Selects Input or Output for strobe 2 0 Input 1 Output 6 3 3 82C54 TIMER COUNTER CONTROL The Timer Counter Control section is used to select the clock gates and interrupt sources for the 82C54 Timer Counters The actual Timer Counter registers are found in the 82C54 Timer Counter n section on page 58 IC ID ID register to identify the Timer Counter Block 15 H ID Register Field Deseiption ID Register15 0 Value of 0x1001 indicates Timer Counter Control Block TC INT Enable and status for the interrupts generated by
18. RW30 Bai RW 0 RW 0 RW30 Bai RW 0 ma Feld Descipion Px 15 0 Bit mask Bit definitions are O Bit is used for match event T Bit is ignored ADVINTn PORTx CMP The compare register is used for the Match interrupt When all selected bits in this register match all selected bits on the input ports an interrupt is generated 15 14 13 12 11 10 9 8 Px15 Px14 Px13 Px12 Px11 Px10 Px9 Px8 RW30 RW 0 RW 0 man gw RW 0 RW 0 Wa 7 6 5 4 3 2 1 0 Px7 P6 Px5 Px4 Px3 Px2 P1 PxO RW30 RW 0 RW 0 man gw RW30 RW 0 Wa Field _ A fDescipion Px 15 0 Compare Value Bit definitions are 0 Interrupt when this bit is 0 when selected 1 Interrupt when this bit is 1 when selected ADVINTn PORTx CAPT The Capture register latches the input ports when an interrupt is generated All values are latched regardless of the Mask register or if the port is an input or output 15 14 13 12 11 10 9 8 Px15 Px14 Px13 Px12 Px11 Px10 Px9 P R30 RO RO RO RHO R0 R0 RO RTD Embedded Technologies Inc www rtd com 52 DMx820 User s Manual Accessing the Analog World 7 6 5 4 3 2 1 0 Field Description Px 15 0 Captured Value Bit definitions are 0 Input was 0 at last inte
19. Rollover 0 Encoder A Positive Rollover 0x02C4 INCENC1 CLOCK b 3 0 Master Clock Source 15 0 Clock_Bus 15 0 RTD Embedded Technologies Inc www rtd com 34 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex 0x02C6 INCENC1 MODE b 15 8 Phase Filter Writing a 1 to a specific bit masks out a phase transition b 7 6 Reserved b 5 Differential Mode 1 Pseudo differential mode 0 Single ended mode b 4 Input Filter 1 Enable Input Filter 0 Disable Input Filter b 3 Join 1 Operate as single 32 bit Encoder 0 Operate as two 16 bit Encoders b 2 0 External Index is disabled 1 External Index is enabled b 1 Hold Register 1 Hold values register 0 Allow value register to change b 0 Count Enable 1 Encoder is enabled 0 Encoder is cleared 0x02C8 INCENC1 VALUEA b 15 0 Value for Encoder A 0Ox02CA INCENC1 VALUEB b 15 0 Value for Encoder B Pulse Width Modulator 0 0x0300 PWMO ID b 15 0 ID Register 0x0003 0x0302 PWMO MODE b 0 1 Enable PWM 0 Disable PWM 0x0304 PWMO CLK b 7 4 Period Clock Source 15 0 Clock_Bus 15 0 b 3 0 Width Clock Source 15 0 Clock Bus 15 0 0x0306_ Reserved od 0x0308 PWMO PERIOD b 15 0 Period of PWM Cycle is Width _ Clock _ Fr
20. UO Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage lou 24mA lot 24mA 1 DIO Vin DC overshoot must be limited to either 5 5V or 10mA and DC undershoot must be limited to either 0 5V or 10mA 2 DIO pins may be driven to 2 0V or 7 0V provided these voltages last no longer than 11ns with a forcing current no greater than 100mA 3 Inputs are terminated with 33O resistors and protection diodes 4 DlO inputs should not be tied to voltages when the board is not powered RTD Embedded Technologies Inc www rtd com 10 DMx820 User s Manual Accessing the Analog World 3 Board Connection 3 1 Board Handling Precautions To prevent damage due to Electrostatic Discharge ESD keep your board in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and handling of your hardware 3 2 Physical Characteristics e Weight Approximately 100 g 0 22 Ibs e Dimensions 90 17 mm L x 95 89 mm W 3 550 in L x 3 775 in W AA Connectors and Jumpers 3 3 1 DM7820HR AND DM8820HR The following diagram shows the location of all connectors and jumpers on the DM7820HR and DM8820HR The DM7820HR and DM8820HR are identical except that the DM8820HR does not have the PC 104 ISA connector po
21. World Mode definition Mode 0 e Application Event counter e Output operation The output is set to L level by the control word setting and kept at L level until the counter value becomes 0 e Gate function H level validates the count operation and L level invalidates it The gate does not affect the output e Count value load timing after the control word and initial count value are written the count value is loaded to the CE at the falling edge of the next clock pulse The first clock pulse does not cause the count value to be decremented In other words if the initial count value is N the output is not set to H level until the input of N 1 the clock pulse after the initial count value writing e Count value writing during counting The count value is loaded in the CE at the falling edge of the next clock and counting with the new count value continues The operation for 2 byte count is as follows e The counting operation is suspended when the first byte is written The output is immediately set to L level No clock pulse is required e After the second byte is written the new count value is loaded to the CE at the falling edge of the next clock e For the output to go to H level again N 1 clock pulse are necessary after new count value N is written e Count value writing when the gate signal is L level The count value is also loaded to the CE at the falling edge of the next clock
22. arrives the new count value is loaded to the CE at the end of the current counting operation cycle In mode 2 count value of 1 is prohibited RTD Embedded Technologies Inc www rtd com 60 DMx820 User s Manual Accessing the Analog World Mode 3 e Application Baud rate generator square wave generator e Output operation Same as mode 2 except that the output duty is different The output is set to H level by control word setting When the count becomes half the initial count value the output is set to L level and kept at L level during the remainder of the count Mode 3 repeats the above sequence periodically If the initial count value is N the output becomes a square wave with a period of N e Gate operation H level validates counting and L level invalidates it If the gate signal is set to L level when the output is L level the output is immediately set to H level The initial count value is reloaded at the falling edge of the clock pulse succeeding the next gate trigger The gate can be used for counter synchronization in this way e Count value load timing After the control word and initial count value are written the count value is loaded to the CE at the falling edge of the next clock pulse Counter synchronization by software is possible in this way e Count value writing during counting The count value writing does not affect the current counting operation When the gate tr
23. b 7 4 Reserved b 3 0 Input Data Select 3 FIFOO Output 2 Port2 1 Port 0 0 PCI Data b 15 10 Reserved b 9 Write Request non sticky b 8 Read Request non sticky te 1 Reserved T Enable 0 Clear 0x00CC FIFOO RW PORT IIS 0 Read Write Port Word access onl FIFO Channel 1 0x00D0 FIFO1 ID b 15 0 ID Register 0x201 1 i i 8 0x00D8 FIFO1 IN DATA DREQ RTD Embedded Technologies Inc www rtd com b 15 8 Interrupt Status Write 1 to clear b 7 0 Interrupt Enable T Interrupt source are Reserved Reserved Underflow Overflow Empty Full Write Request Read Request b 15 5 Reserved b 4 0 Input Clock Select 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 b 15 5 Reserved b 4 0 Input Clock Select 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 b 15 10 Reserved b 9 8 DREQ1 Source 3 Not Full 2 Write Request 1 Not Empty 0 Read Request Reserved Input Data Select 3 Incremental Encoder B1 2 Incremental Encoder BO 1 0 1 Interrupt condition has occurred Interrupt is enabled 0 disabled b 7 4 b 3 0 Port 1 PCI Data 30 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex OxOODA FIFO1 CON STAT b 15 10 Reserved b 9 Write Request non sticky b 8 Read Request non
24. initially set to H level When the counter value becomes 0 after triggering by the rising edge of the gate pulse the output goes to L level during one clock pulse and then restores H level e Count value load timing Even after the control word and initial count value are written loading to the CE does not occur until the input of the clock pulse succeeding the trigger For the clock pulse for CE loading the count value is not decremented If the initial count value is N therefore the output is not set to L level until N 1 clock pulses are input after triggering e Gate function The initial count value is loaded to the CE at the falling edge of the clock pulse succeeding gate triggering The count sequence can be retriggered The gate pulse does not affect the output RTD Embedded Technologies Inc www rtd com 61 DMx820 User s Manual Accessing the Analog World e Count value writing during counting The count value writing does not affect the current counting sequence If the gate trigger is generated after the new count value is written and before the current counting ends the new count value is loaded to the CE at the falling edge of the next clock pulse and counting continues using the new count value The various roles of the gate input signals in the above modes are summarized in the following table e HM Gate l iB Mode _ L Level Falling Edge Rising Edge H Level 0 Counting not possible BEER Coun
25. period The width clock is used to decrement the counter When the counter reaches zero it will wait for the next period clock to re load the counter with the period value In a typical PWM implementation the same clock is used for width and period By using separate clocks a high resolution can be achieved with low duty cycle outputs For example if a 1 MHz clock is used for the period clock and the PERIOD register is set to its maximum value and a 10 MHz clock is used for the width clock the duty cycle range is 0 to 10 with a full 16 bit resolution across that range Note that if the PERIOD register is set to its maximum value a duty cycle of 100 cannot be achieved An interrupt is generated at the beginning of every period The width register is checked at the beginning of every period If the width register is modified in the middle of a period the output will not be affected until the next period PWMn ID ID register to identify this block 15 H ID Register Feld Deseiption ID Register15 0 Value of 0x0003 indicates Pulse Width Modulator PWMn MODE This register is used to enable and disable the Pulse Width Modulator When disabled all non inverted outputs are low and all inverted outputs are high and interrupts are not generated 15 1 0 Reserved Ka Field _ Desergton Enables or disabled the PWM O Disabled 1 Enabled PWMn CLK This register selects the c
26. redeo e 9 TaBe 2 Operaning CoNdNONS MER 10 Table 3 Electrical Characteristics cccccsssssssssssssssssssssssscsssssesscssessesesscessesesacsesssesavscsesesasacsssesesacacsssesasacsssesesacacessesavacesessesacauessesavacessesavasasessesas 10 Table 4 CN10 Pin Assignments ccccccccscsssssscsessesssesscscsesessesssessesesessesesassesassesesassssessesesassssesaesesassesesaesesessusesassesesaesesassusasaesesassusesaesesassusesaseesas 12 Tables CN ST IN PAS SUC NNN o aos iusta mer ure csc aap gece CM En pA LE DG DEM pcan ese eee ee eee UE MU MEUS 13 MOC INTO IN Pa SUIS EISE OT TESTER 18 Table 7 CN10 Pin Assignments cccccsscsssssscsessssssesscscsesessessessesesessesessssesessesesassesessesesassesesausesassssesassesassusesassesesaesesassusesausesassusesaueesassusesasensas 20 Table 8 PCI Configuration KT 27 Taole S DMX 0RR Memon MaD reris ran E eee mr R E O ER O E OE 28 Table 10 Cn bes EE 41 Table 11 Incremental Encoder e TEEN 53 Table 12 Select Counter SC 1 0 Selection of set counter nnnm nnne 59 Table 13 Read Load RL 1 0 Count Value Reading Loading format Setting 59 Table 14 Mode M 2 0 Operation waveform mode seitng tnter tnnn nnns 59 Table 15 BCD Operation count mode setting EE 59 Table 16 PLX DMx820HR Memory Map 67 Table Wit RN Nels Wuel ET 72 Accessing the Analog World RTD Embedded Technologies Inc www rtd com vii DMx820 User s Manual Accessing the Analog World 1
27. sticky aid Reserved b 0 1 Enable 0 Clear OxOODC FIFO1 RW PORT b 15 0 Read Write Port Word access onl Programmable Clock 0 0x0100 PRGCLKO ID b 15 0 ID Register 0x1000 PRGCLKO MODE b 15 2 Reserved b 1 0 00 Disabled 01 Continuous 10 Retrigger 11 One Shot 0x0104 PRGCLKO CLK b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock Bus 15 0 0x0106 PRGCLKO_START_STOP b 15 13 Reserved b 12 8 Stop Clock 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate 0x0108 PRGCLKO_PERIOD b 15 0 Period of Clock Output frequency is Master _ Clock _ Frequency PRG _CLK _ PERIOD 1 0x010A Programmable Clock 1 0x0140 PRGCLK1 ID b 15 0 ID Register 0x1000 PRGCLK1 MODE b 15 2 Reserved b 1 0 A 00 Disabled 01 Continuous 10 Retrigger 11 One Shot 0x0144 PRGCLK1_CLK b 15 4 Reserved b 3 0 Master Clock Source 15 0 Clock Bus 15 0 0x0146 PRGCLK1 START STOP b 15 13 Reserved b 12 8 Stop Clock 31 16 nterrupt Bus 15 0 15 1 Clock Bus 15 1 0 No Stop Clock b 7 5 Reserved b 4 0 Start Trigger 31 16 Interrupt_Bus 15 0 15 1 Clock_Bus 15 1 0 Start Immediate RTD Embedded Technologies Inc www rtd com 31 DMx820 User s Manual Accessing the Analog World
28. the middle of a period the output will not be affected until the next period Note that with PWMn_PERIOD set to the maximum value and the period clock and width clock set to the same source a 100 duty cycle is not possible 15 0 WIDTH 15 0 RW 0 _Field Desogpgon WIDTH 15 0 The width of the output WIDTH Width _ Clock _ Frequency 6 3 9 82C54 TIMER COUNTER N The following section is taken from the MSM82C54 Datasheet from Oki Semiconductors For information on programming the 82C54 timer counters please consult the datasheet DESCRIPTION OF OPERATION MSM82C54 2 functions are selected by control words from the CPU In the required program sequence the control word setting is followed by the count value setting and execution of the desired timer operation Control Word and Count Value Program Each counter operating mode is set by control word programming The control word format is outlined below RTD Embedded Technologies Inc www rtd com 98 DMx820 User s Manual D7 De Ds D4 D3 Do D4 Do a G IL Select Counter Read Load Mode BCD CS 0 Ao A421 1 RD 1 WR 0 Table 12 Select Counter SC 1 0 Selection of set counter SC 1 0 Set Contents Counter 0 Selection LOG 7 Counter 1 Selection Counter 2 Selection Table 13 Read Load RL 1 0 Count Value Reading Loading format setting RL 1 0 Set Contents Counter Latch Operation 01 Reading Loading of Least Significant B
29. tnnt trinis ratis ra istas nist tan 11 3 2 Be Ee 11 3 3 Beileed 11 3 3 1 DM7820AR and RUET TN 11 3 3 1 DM35820HR and DMIG20HR E 12 3 9 2 EENHEETEN 12 Connector CN10 Digital Input Output 12 Connector CN11 Digital Input Output 13 3 9 9 BOSC NNE IO scdeeccem iii E eee Inu UEM DEM DNE M DUERME DA E 14 PC 104 Express Bus Connectors DM9820HR Only nnns 14 PC 104 Plus Ge Keele 14 PC 104 ISA Connectors DM7820HR Ombhy essent 15 3 4 Seoane En ee ne en enn en ae en ne er enn nT 16 4 DAN Connections 17 4 1 Module Handling Precautions cccccccscssscsssscsscsssscsssecsssscsecsssecsesessesessesaesesaecessesasseseesassesassesaesassesaesesaesaseesateasaesassasaneesaesass 17 4 2 62D Physical Eer 17 4 3 DS let 18 4 4 68S ale een 19 4 5 BETEN 20 4 6 Bus tere 21 PC 104 Express Bus Connectors DM9820HR On ee 21 PGE PIOUS POI GORI MEER n 21 PC 104 ISA Connectors DM7820HR Omhy sss nnnm nnn tnnt nnn tnnt nns 21 4 7 Seel e NIRE EE tm 22 5 Functional Description 23 5 1 BECK Riet 23 5 2 Jai gr ACO E U OR E EE 24 5 3 le 24 5 4 BOA D E 25 5 5 Advanced Triggering ln 25 6 Board Operation and Programming 27 6 1 SS E 27 RTD Embedded Technologies Inc www rtd com IV DMx820 User s Manual Accessing the Analog World 6 2 WICH MEMON T 27 6 2 1 Eier 27 6 3 Detailed Register Description EE 36 6 3 1 SE Ce 36 FPGA VERSION
30. 04 Plus PCI Connector The PC 104 Plus connector carries the signals of the PC 104 Plus PCI bus Refer to PC 104 Plus Specification for the pinout of this connector The DM9820HR connects to the power and ground pins only and does not use any of the signals The DM7820HR uses this connector for communication with the CPU PCI Configuration Options DM7820HR Only See PCI Configuration Options DM7820HR Only on page 14 PC 104 ISA Connectors DM7820HR Only The PC 104 connectors carry the signals of the PC 104 Plus ISA bus Refer to PC 104 Plus Specification Revision 1 0 for the pinout of this connector This is a pass through connector The DM7820HR connects to the power and ground pins only and does not use any of the signals RTD Embedded Technologies Inc www rtd com 21 DMx820 User s Manual Accessing the Analog World 4 Steps for Installing Always work at an ESD protected workstation and wear a grounded wrist strap Turn off power to the IDAN system Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busses used by the peripheral cards are connected to the couModule Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack Gently and evenly press the module onto the IDAN system If any boards are to be stacked above this module install them Finis
31. 20 User s Manual Table 4 CN10 Pin Assignments Signal Pog P 0 0 00 Po 90 IIEIEIDIEI IEOjIO jco jfco jco jr 5 jrojrojrofjrojj cof O01f Of JON FOpot ON ojojy oN HIB BR ER FB PO JO J WFO FO FM FNM FNM TMT hw gt COFOFLIMOFOLO OI AINI OI oDi AINO OO zzz U UJUjuju Z O Pal Lee lagen ri Pll nn UO UJUUuIUu Q Z O P rs Uu See Table 10 on page 41Table 10 and Table 11 on page 53 for peripheral pin assignments Connector CN11 Digital Input Output Accessing the Analog World Connector CN11 provides 24 digital input output lines along with a 5V pin and ground pins The pin assignments for CN11 are shown in Table 2 Table 5 CN11 Pin Assignments P2 15 P2 14 P2 13 P2 12 P2 11 P2 10 P2 9 P2 8 P1 15 P1 14 P1 13 P1 12 P111 P1 10 P1 9 P1 8 P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 5V 2A max Pin Pin Pin 5 L 7 8 9 fio Signal O See Table 10 on page 41Table 10 and Table 11 on page 53 for peripheral pin assignments RTD Embedded Technologies Inc www rtd com 13 DMx820 User s Manual Accessing the Analog World 3 3 3 BUS CONNECTORS PC 104 Express Bus Connectors DM9820HR Only The PCle connector is the connection to the system CPU The position and pin assignments are compliant with the PC 104 Express Specification See PC 104 Specificat
32. BE 36 OVNER ON ME 36 39i E ccc T 37 BRD NN erent tener ree E erty oe area ene ee ere ere cee nee ere eee eee eee ee 37 NT E 37 UN ee 38 6 3 2 elle le o tet Tet nett ert ee er ee ene eer re ee eT 39 FU GA 40 ge dpa 40 epp cP t c eee 40 zo pao 40 PORTX PERIPH SEL L ico atus ER um MUNI UU HMM MUEAU UM NUMEN UEM IU UEM E 41 PORTA PERIPH SEL RP 41 ROBE RE 42 6 3 3 02054 Timer Counter COMPO aisssisssoisuiecauersnedcoraniuanunatveiinetticttontsiseswssditcaientd iesdii tied agat ivio th E RU 43 Ep ecc 43 Dez e 43 Der R65 0m x 43 6 3 4 WISEN 44 dd 44 giat pc 45 FIFO m RECS Ce 45 mt EOD MON C 46 FIFROn IN DATA el 46 OMON Kont E 47 lei 47 6 9 5 giis napoli oe d EE 0 E LO ee 48 FS IN MH 48 PROGCLKA MODE T 48 ECEE E RE 48 PPTL STARI OTOP oreren ant a O O O O O 49 PROGCE
33. International Business Machines Inc PCI PCI Express and PCle are trademarks of PCI SIG PC 104 PC 104 Plus PCI 104 PCle 104 PCI 104 Express and 104 are trademarks of the PC 104 Embedded Consortium All other trademarks appearing in this document are the property of their respective owners Failure to follow the instructions found in this manual may result in damage to the product described in this manual or other components of the system The procedure set forth in this manual shall only be performed by persons qualified to service electronic equipment Contents and specifications within this manual are given without warranty and are subject to change without notice RTD Embedded Technologies Inc shall not be liable for errors or omissions in this manual or for any loss damage or injury in connection with the use of this manual Copyright 2013 by RTD Embedded Technologies Inc All rights reserved RTD Embedded Technologies Inc www rtd com ii DMx820 User s Manual Accessing the Analog World Table of Contents 1 Introduction 8 1 1 Breil 8 1 2 Bio WEE 8 1 3 Bi U c i REIR OT oec cese meet I eee 9 1 4 Contact eene ca secto au Nee er ra MR IMEEM 9 1 4 1 odlas SUD DOM egene 9 1 4 2 MGC NGA SU OI EE 9 2 Specifications 10 2 1 poring Cona ONE oai DIS MMC E MEMINI 10 2 2 Electical CharacieriSlCS NRI EET 10 MIS CNN TT Uu e c cc cc uUum 10 3 Board Connection 11 3 1 Board Handling Precautions tnmen nnnm nnne
34. Interrupt Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe Prog Clock 3 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved Start Immediate 49 DMx820 User s Manual Field Descipin STOP TRGIA 0 PROGCLKn PERIOD Selects the stop trigger Value definitions are 31 FIFO1 Interrupt FIFOO Interrupt Prog Clock 3 Interrupt Prog Clock 2 Interrupt Prog Clock 1 Interrupt Prog Clock 0 Interrupt PWM1 Interrupt PW MO Interrupt Reserved Reserved Incremental Encoder 1 Interrupt Incremental Encoder 0 Interrupt Reserved 82C54 Interrupt Advanced Interrupt 1 Interrupt Advanced Interrupt 0 Interrupt Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe Prog Clock 3 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved Do Not Stop OO nm CO P OO CO O Sets the period of the programmable clock Accessing the Analog World 15 PERIOD 15 0 RW 0 Field Descipion PERIOD 15 0 The frequency of the output clock is Master _ Clock _ Frequency PERIOD 1 PROGCLKn_COUNT The current value of the clock counter 15 9 COUNT 15 0 RW 0 Field Description _ COUNT 15 0 The current value of the clock counter This starts at a value of PERIOD
35. Interrupt Enabled DW MO Interrupt from Pulse Width Modulator block at 0x0300 0 Interrupt Disabled 1 Interrupt Enabled PWM1 Interrupt from Pulse Width Modulator block at 0x0340 0 Interrupt Disabled 1 Interrupt Enabled PClkO Interrupt from Programmable Clock block at 0x0100 0 Interrupt Disabled 1 Interrupt Enabled Interrupt from Programmable Clock block at 0x0140 0 Interrupt Disabled 1 Interrupt Enabled PClk2 Interrupt from Programmable Clock block at 0x0180 0 Interrupt Disabled 1 Interrupt Enabled PCIK3 Interrupt from Programmable Clock block at 0x01CO 0 Interrupt Disabled 1 Interrupt Enabled FIFOO Interrupt from FIFO block at OxX00CO 0 Interrupt Disabled 1 Interrupt Enabled FIFO1 Interrupt from FIFO block at 0x00D0 oe 0 Interrupt Disabled 1 Interrupt Enabled INT STATUS This register shows if any of the interrupt conditions has occurred This is a sticky register bits remain set until cleared by writing a 1 Interrupts do not have to be enabled in INT ENABLE in order for status bits to be set 15 14 13 12 11 10 9 8 FIFO1 FIFOO PCIk3 PCI PCIK1 PCIKO PWM PWMO 7 6 5 4 3 2 1 0 82C54 Agut Advinto Feld Description AdvInt0 Interrupt from Advance Interrupt block at 0x0200 Uz Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Advint1 Interrupt from Advance Interrupt block at 0x0240 0 I
36. Interrupt has occurred Write 1 to clear ENA B NEG Enables interrupt when channel B transitions from 0x0000 to OxFFFF Negative rollover 0 Interrupt is disabled 1 Interrupt is enabled ENA B POS Enables interrupt when channel B transitions from OxFFFF to 0x0000 Positive rollover 0 Interrupt is disabled 1 Interrupt is enabled ENA A NEG Enables interrupt when channel A transitions from 0x0000 to OxFFFF Negative rollover 0 Interrupt is disabled 1 Interrupt is enabled ENA A POS Enables interrupt when channel A transitions from OxFFFF to STAT A POS Indicates channel A has transitioned from OxFFFF to 0x0000 Positive rollover O Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear 0x0000 Positive rollover 0 Interrupt is disabled 1 Interrupt is enabled RTD Embedded Technologies Inc www rtd com 54 DMx820 User s Manual Accessing the Analog World INCENCn_CLK This register selects the clock source for sampling the encoder inputs 15 4 3 0 CLOCK SEL 3 0 Field _ JDescrption CLOCK SEL 3 0 Selects the master clock Value definitions are Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe 1 Prog Clock 3 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved 25 MHz OoO NWHRODN CO KO INCENCn MODE This register
37. Introduction 1 1 Product Overview The DM7820HR DM8820HR DM9820HR is designed to provide high speed digital I O for PC 104 Plus PCI 104 PCI 104 Express and PCle 104 Systems It interfaces with the PCI or PCI Express bus and uses large FIFOs and DMA transfers to allow for efficient data management Several peripherals including Pulse Width Modulators Incremental Encoders and Programmable Clocks are also provided 1 2 Board Features e Digital I O o 48 Diode protected l O lines o 24 mA source and sink current o Compatible with DMR and DOP expansion boards e Deep FIFOs with DMA o Two2M Word FIFOs Each FIFO is attached to a separate DMA channel 25 MHz bursted throughput 12 5 MHZ continuous throughput FIFO can be looped e Pulse Width Modulators Eight PWM outputs Single ended or Differential Outputs 16 bit resolution Separate period and width clocks provide full resolution at low duty cycles o Optional Interrupt generations e Incremental Encoders o Four Incremental Encoder channels Single ended or Pseudo differential Inputs Variable frequency input filtering Max input speed of 40ns per transition 16 bit resolution Two channels can be combined for 32 bit resolution o Connect to FIFO for position sampling e Advanced Interrupts o Two Advanced Interrupt Modules o Interrupt on Match Change or Strobe o Al 48 bits are captured when the interrupt is generated o Any combination of the 48 bits can be monitored e Programmable Clocks o Four pr
38. KA Ee 50 Wel gue KREE 50 6 3 6 ENEE EIERE 51 ROVINTA ID EE 51 PAIN gg IN RTE 51 BAT UNNI OA EE 51 ADVINTn_POR X_MASK NERO cc 52 ABUTERE EE M E E 52 ADVINMEPOR PO OAP c 52 6 3 7 Dual Incremental Encoder ME 53 juez pp 53 lez e 54 IT EIN Ge CUK C esate 95 leed MODE C XX 55 jede Ei ae 56 6 3 8 Quad Pulse Width Modulator n esee nnne nennen nnne tnnt tnnt rnnt tenerent 56 SOT Alf KEE 57 iln 9o 57 PPM e BE 57 mcd Dm 58 PING VV NDT FN EN 58 6 3 9 OG MINE eI RO 58 DESCRIPTION OF OPERATION st 58 Control Word and Count Value Prograin csssssssscssssssssssssscsssssessesssssesesscssessesscsesssesasscessesevaceeeesesaraeeesesavaeasersesasess 58 Mode AENOR E 60 Reading geen 63 6 4 Kb el 67 6 4 1 Memory Map Overview ccccccsscscsscscsssscsssesscsesececsesessssesessesesessesessssesessesesessesesaesesasaesesassesasaesesassesasaesesassesasass 67 6 4 2 DMA Register Description M E
39. OOOO x28 Reen T 0x30 Resewd T 0x34 Ieselen 0x3 Resewd O T 6 2 Device Memory The DMx820HR is a memory mapped device The address for the memory mapped registers can be found in Base Address Register 2 Generally the registers are 16 bits wide However they can be read and written as 8 16 or 32 bits There are a few exceptions as noted in the memory map 6 2 1 Memory MAP OVERVIEW Table 9 shows the memory map of the DMx820HR digital I O registers These are found at the offset from BAR2 RTD Embedded Technologies Inc www rtd com 27 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex Board Control 0x0000 FPGA_VERSION b 15 8 Type ID b 7 0 Version 0x0002 SVN VERSION b 15 0 Extended Version 0x0004 BOARD RESET Write OxA5AB to reset board 0x0006 Reserved 00 ooo 0x0008 BRD STAT b 15 1 Reserved bO MSTR 0 PCI Master Capable 1 Not PCI Master Capable Read Only 0x0010 INT ENABLE b 15 0 Interrupt Enable Set to 1 to enable a specific interrupt ae bus b 15 0 Interrupt Status Reading a 1 indicates interrupt condition has occurred Write a 1 to clear an interrupt bit bid 4 Mni NN 0x003E Standard UO 7 0x0052 PORT2 INPUT 15 0 Read only value from Eat 0x0058 STROBE_STATUS b 9 STR2 THI 0 strob
40. Px8 R30 RO RO RO RO RO RO RO 7 6 5 4 3 2 1 0 P7 P6 Px5 Px4 Px3 Px2 Px1 PxO R30 RO RO RO RO RO RO RO Field Description Px_ 15 0 Current pin value Uz Pin is Low 1 Pin is High PORTx TRISTATE This register selects if each bit in Port 0 Port 1 or Port 2 is an input or an output 15 14 13 12 11 10 9 8 Px15 Px14 Px13 Px12 Pxit Px10 Px9 P RW30 Bai RW 0 RW 0 RW30 Bai gw m 7 6 5 4 3 2 1 0 Px7 P6 Px5 Px4 Px3 Px2 P1 PxO RW30 RW 0 RW 0 man RW 0 RW30 RW 0 Wa Px 15 0 Select input or output 0 Input 1 Output PORTx MODE Selects if each pin in Port 0 Port 1 or Port 2 is a standard UO controlled by PORTx TRISTATE or a peripheral output controlled by PORTx PERIPH SEL RTD Embedded Technologies Inc www rtd com 40 DMx820 User s Manual Accessing the Analog World 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Field Description Px 15 0 Port Mode Uz Standard UO controlled by PORTx_ TRISTATE 1 Peripheral controlled by PORTx PEHIPH SEL PORTx PERIPH SEL L This register selects the peripheral for Port 0 Port 1 or Port 2 when it is a peripheral output i e PORTx_MODE 1 This register selects the peripheral for bits 7 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PORTx PERIPH SEL H This regis
41. al encoder channel When INCENCx_MODE JOIN 1 INCENCx VALUEB contains the most significant word and INCENCx_VALUEA contains the least significant word A 16 bit read should be used to read this register when not joined INCENCx_MODE JOIN 0 and a 32 bit read should be used when joined INCENCx MODE JOIN 1 Otherwise the value can change between read operations Another option is to set INCENCx MODE HOLD 1 read the contents of the register and then set INCENCx MODE HOLD 0 This register can only be written to when INCENCx_MODEJENA 0 This allows the counter to be pre loaded with a known position value 15 0 VALUE 15 0 R W 0 Field Description VALUE 15 0 The current value of this incremental encoder channel 6 3 8 QUAD PULSE WIDTH MODULATOR N The Pulse Width Modulator block provides four PWM outputs Each output consists of a non inverted and inverted signal These signals are available on select pins as peripheral outputs The period and width of the output is set with 16 bit resolution PERIOD 1 Width_Clock_Freq WIDTH Width_Clock_Freq Period_Clock Edge Output Output Interrupt RTD Embedded Technologies Inc www rtd com 96 DMx820 User s Manual Accessing the Analog World Figure 12 PWM Output All of the PWM outputs have the same period The pulse width of each of the four outputs is individually adjustable The PWM can use separate clocks for width and
42. and negative rollover Positive rollover occurs when the counter is at its maximum value and receives a signal to count up Negative rollover occurs when the counter is at 0 and receives a signal to count down Because separate interrupts are generated the counter can be easily expanded in software The Incremental Encoder inputs are show in Table 11 below Table 11 Incremental Encoder Inputs EE AC CRannd B B Poro S Por tt Pom Pom INCENCn ID ID register to identify this block RTD Embedded Technologies Inc www rtd com 53 DMx820 User s Manual Accessing the Analog World 15 0 ID_Register ID Register15 0 Value of 0x0002 indicates Dual Incremental Encoder INCENCn_INT This register provides the status and enables for the encoder interrupts 15 14 11 10 9 8 STAT_B_NEG STAT B POS STAT A NEG STAT A POS 7 4 3 2 1 0 ENA B NEG ENA B POS ENA A NEG ENA A POS Field Description STAT B NEG Indicates channel B has transitioned from 0x0000 to OxFFFF Negative rollover O Interrupt has not occurred 1 7 Interrupt has occurred Write 1 to clear STAT B POS Indicates channel B has transitioned from OxFFFF to 0x0000 Positive rollover O Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear STAT A NEG Indicates channel A has transitioned from 0x0000 to OxFFFF Negative rollover O Interrupt has not occurred 1 7
43. andling Precautions To prevent damage due to Electrostatic Discharge ESD keep your module in its antistatic bag until you are ready to install it into your system When removing it from the bag hold the module by the aluminum enclosure and do not touch the components or connectors Handle the module in an antistatic environment and use a grounded workbench for testing and handling of your hardware 4 2 62D Physical Characteristics e Weight Approximately 0 21 Kg 0 46 Ibs e Dimensions 151 972 mm L x 129 978 mm W x 33 934 mm H 5 983 in L x 5 117 in W x 1 339 in H A ANY AN 1u AAS AK WAN i NN N NN NS 62 pin High Density D female Module Part Adam Tech HDT62SD Mating Part Adam Tech HDT62PD Figure 4 IDAN Dimensions RTD Embedded Technologies Inc www rtd com 17 DMx820 User s Manual Accessing the Analog World 43 62D Connectors Table 6 CN10 Pin Assignments IDAN P2 Pin CN10 IDAN P3 Pin FERE CN11 Row1 Row2 Row3 Signal Pin Rowit Row2 Row3 Signal Pin 01 E A o C ee e LL STROBE2 2 J STROBE2 2 4 Re 3 J Eoo S R Pa 3 WE 2 LN Ji LL PR Je oD 6 a EO E PR a 124 GND 4 PI 9 4 oD o LL LB n 6 JND 2 5 Jo J P9 B 28 DND 4 4 P8 Im 6 X IoD i O a ES 17 4 oD 8 ILL 19 8 ND oo Ia oD NENNEN p SS p NEN p LS
44. ar Interrupt from FIFO block at 0x00C0 Uz Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Interrupt from FIFO block at OxX00DO 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear A diagram of the standard I O is shown in Figure 10 Each digital I O pin can be an input output or peripheral output The peripheral outputs are the Pulse Width Modulators FIFO Timer Counters etc Peripheral 3 Peripheral 2 b Peripheral 1 Peripheral 0 E po D Q J D Q i d D Q d PORTx_OUTPUT PORTx_PERIPH_SEL PORTx_TRISTATE E Q PORTx MODE Peripheral Q D lt Data Readback PORTx_INPUT RTD Embedded Technologies Inc www rtd com 39 DMx820 User s Manual Accessing the Analog World Figure 10 Digital I O Block Diagram PORTx_OUTPUT Sets the value for Port 0 Port 1 or Port 2 when it is a standard output 15 14 13 12 11 10 9 8 Px15 Px14 Px13 Px12 Px11 Px10 Px9 P RW30 RW 0 RW 0 mat wa nat RW 0 Bai 7 6 5 4 3 2 1 0 P7 P6 Px5 Px4 Px3 Px2 Ip P RW30 Bai RW 0 RW 0 RW30 Bai RW 0 ma Px 15 0 Value to output 0 Low 1 High PORTx_ INPUT Returns the current value of Port 0 Port 1 or Port 2 15 14 13 12 11 10 9 8 Px15 Px14 Px13 Px12 Px11 pn Px9
45. are limited to the duration of this warranty In the event the product is not free from defects as warranted above the purchaser s sole remedy shall be repair or replacement as provided above Under no circumstances will RTD Embedded Technologies be liable to the purchaser or any user for any damages including any incidental or consequential damages expenses lost profits lost savings or other damages arising out of the use or inability to use the product Some states do not allow the exclusion or limitation of incidental or consequential damages for consumer products and some states do not allow limitations on how long an implied warranty lasts so the above limitations or exclusions may not apply to you This warranty gives you specific legal rights and you may also have other rights which vary from state to state RTD Embedded Technologies Inc www rtd com 78 DMx820 User s Manual RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Represents all cpu s pres In systems capable of hotp as new cpu s are detected method such as ACPI for Wi cpumask t cpu present map EXPORT SYMBOL cpu _ present Ee Us ifndef CONFIG SMP Represents all cpu s that Kg Ze wv As9100 V 1s0 9001 Copyright 2013 by RTD Embedded Technologies Inc All rights reserved
46. d it is necessary to stop the counting by a gate input signal or to interrupt the clock input temporarily by an external circuit to ensure that the counter value is correctly read Counter latching In this method the counter value is latched by writing counter latch command thereby enabling a stable value to be read without effecting the counting in any way at all The output latch OL of the selected counter latches the count value when a counter latch command is written The count value is held until it is read by the CPU or the control word is set again If a counter latch command is written again before reading while a certain counter is latched the second counter latch command is ignored and the value latched by the first counter latch command is maintained The MSM82C54 2 features independent reading and writing from and to the same counter When a counter is programmed for the 2 byte counter value the following sequence is possible 1 Count value LSB reading 2 New count value LSB writing 3 Count value MSB reading 4 New count value MSB writing An example of a counter latching program is given below MVI A 0100xxxx Denotes counter latching OUT n3 Write in control word address n3 The counter value at this point is latching IN n1 Reading of the LSB of the counter value latched from counter 1 n1 Conter 1 address MOV B A IN n1 Reading of MSB from counter 1 MOV C
47. d Request is asserted when at least 256 words of data is in the FIFO and negated when there is less than 128 words of data Using these signals guarantees a burst of at least 128 words which provides for efficient communication over the PCI bus and robustly guards against over run and under run conditions However it does not allow for the FIFO to be completely filled of emptied There is a total of 45 M words per second of available bandwidth for the entire FIFO system This bandwidth is allocated between all input and output sources This is assuming that at least 256 Words stay in the FIFO at all times to maximize bursting Le the Read Request and Write Request are used for DREQ If only one word is available in the FIFO i e Not Empty is used as for DREQ the available bandwidth drops to 3 75 M words per second When a FIFO is looped the data must be read and written The table below shows examples of configurations and their maximum data rate Note that for uniform sampling samples are taken at uniform sampling intervals the data rate must be an integer divisor of the 25 MHz overall clock RTD Embedded Technologies Inc www rtd com 24 DMx820 User s Manual 9 4 9 9 Accessing the Analog World Description EE _ Max Data Rate 6 25 MHz non uniform sampling 11 MHz Board Interrupts There are three levels of interrupt sources for this board the interrupt sources generated in the PLX chip the interrupt sourc
48. d by a register table The first row of the table lists the bits D15 through DO The second row lists the field name for each bit The third row lists the properties of that bit R bit can be read W bit can be written to and C bit can be cleared The last row lists the value of the bit after reset The register table is then followed by a description of each of the fields where applicable An N A for the reset value indicates that the reset value is not applicable read the field descriptions for more information Bits marked as Reserved in the field name are unused and reads will always return their reset value These bits should not be modified during writes for future compatibility 6 3 1 SYSTEM BLOCK FPGA_VERSION This register provides the version and type ID of the Digital WO FPGA The version can be used to identify the specific build of the board The type ID can be used to identify a particular feature set 15 8 7 0 TYPE ID VERSION Field A Bescripion TYPE ID FPGA Type Identifier 0x10 Standard FPGA VERSION FPGA Version Identifier SVN_VERSION This register provides the source code revision control version It is updated every time the FPGA is compiled 15 0 VERSION RTD Embedded Technologies Inc www rtd com 36 DMx820 User s Manual Accessing the Analog World VERSION FPGA Source Version Identifier BOARD_RESET Writing a value of 0xA5A6 to this register resets t
49. dividually selected or masked Strobe mode will generate an interrupt on the rising edge of the Strobe1 or Strobe2 signal 15 2 1 0 MODE 1 0 Field Descripion MODE 1 0 Interrupt Mode Value definitions are 3 Event Mode 2 Match Mode 1 Strobe Mode O Disabled ADVINTn_CLK This register selects the clock source for sampling the ports when in Match or Compare mode In Strobe mode this register selects the actual strobe signal and the 25 MHz clock always serves as the sampling clock 15 4 3 0 CLOCK SEL 3 0 Field A BDescipion CLOCK SEL 3 0 Selects the master clock Value definitions are 15 Inverted Strobe2 14 Inverted Strobe1 13 Strobe2 RTD Embedded Technologies Inc www rtd com 91 DMx820 User s Manual Accessing the Analog World Field 12 Strobe 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Reserved 25 MHz ADVINTn PORTx MASK This register determines if a bit is checked for the match and event interrupts OO nm Go P OO CO O Note If Match mode is selected and all bits are masked an interrupt will be generated immediately 15 14 13 12 11 10 9 8 Px15 Px14 Px13 Px12 Px11 Px10 Px9 P RW30 RW 0 RW 0 mat RW30 RW30 RW 0 Ba 7 6 5 4 3 2 1 0 Px7 P6 Px5 Px4 Px3 Px2 P1 P
50. e year following the date of shipment from RTD Embedded Technologies Inc This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period RTD Embedded Technologies will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to RTD Embedded Technologies All replaced parts and products become the property of RTD Embedded Technologies Before returning any product for repair customers are required to contact the factory for a Return Material Authorization RMA number This limited warranty does not extend to any products which have been damaged as a result of accident misuse abuse such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by RTD Embedded Technologies acts of God or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth above no other warranties are expressed or implied including but not limited to any implied warranties of merchantability and fitness for a particular purpose and RTD Embedded Technologies expressly disclaims all warranties not stated herein All implied warranties including implied warranties for merchantability and fitness for a particular purpose
51. e2 is input 1 srobe2 is output b 8 STR1 THI 0 strobe is input 1 srobe1 is output b 5 STR2_OUT Value for strobe2 when an output b 4 STR1 OUT Value for strobe1 when an output b 1 STR2 IN Current value of Strobe2 b 0 STR1 IN Current value of Strobe1 0x005E 0x0060 PORTO PERIPH SEL L b 15 14 PortO 7 Periph Select b 13 12 PortO 6 Periph Select b 11 10 PortO 5 Periph Select b 9 8 Port0 4 Periph Select b 7 6 X PortO 3 Periph Select b b 4 XPortO 2 Periph Select b 3 2 X PortO 2 Periph Select b 1 0 X PortO O Periph Select 0x0062 PORTO PERIPH SEL H b 15 14 PortO 15 Periph Select b 13 12 PortO 14 Periph Select b 11 10 Porto 13 Periph Select b 9 8 X PortO 12 Periph Select b 7 6 PortO 11 Periph Select b 5 4 X PortOo 10 Periph Select b 3 2 X PortO 9 Periph Select b 1 0 X PortO 8 Periph Select 0x0064 PORTi PERIPH SELL 0x0066 PORTI PERIPH SELH 0x0068 PORT2 PERIPH SELLE S o RTD Embedded Technologies Inc www rtd com 28 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex Ox006A_ PORT2_PERIPH_SELH 0x0070 Reserved wre S O Po 82054 Timer Counter Control gt So ner Counter Control or aaao 0 ID Register equals 0x1001 b 15 14 Reserved b 13 8 Interrupt Status 1 Interrupt condition has occurred Write 1 t
52. emory MAP OVERVIEW Table 16 shows the memory map of the DMx820HR DMA registers These are found at the memory offset from BARO or the UO offset from BARI Table 16 PLX DMx820HR Memory Map 0x90 DMADPRO DMA Channel 0 Descriptor Pointer 0x94 DMAMODE DMA Channel 1 Mode m OxAO DMALADRi DMA Channel 1 Local Address ToxAo 0x98 DMASIZ1 DMA Channel 1 Transfer Size Byles OxA4 DMADPRT DMA Channel 1 Descriptor Pointer OxA9 DMAGSR1 DMA Channel 1 Command Status Upper Address Upper Address interrupt INTCSR Interrupt Control Status Where two addresses are given the left column is the address when DMAMODEn 20 0 and the right column is the address when DMAMODEn 20 1 6 4 DMA REGISTER DESCRIPTION DMAMODEn DMA Mode MENSEM Accessing the Analog World Local Bus Data Width Writing of the following values Yes Yes 11b 11b indicates the associated bus data width 00b 8 bit 01b 16 bit 10b or 11b 32 bit DMx820 User s Manual RTD Embedded Technologies Inc www rtd com 67 Accessing the Analog World Internal Wait State Counter Address to Data Data to Data 0 to 15 Wait States TA READY Input Enable Writing 1 enables READY input Writing 0 disables READY input 7 Continuous Burst Enable When bursting is enabled Yes Yes 1 DMAMODEO 8 1 writing 1 enables Continuous Burst mode and writing 0 enable
53. equency PWMx _ PERIOD 1 0x030A Reserved Kee 0x0310 PWMO_WIDTHA b 1 0 Width of output A pulse in Period Clock cycles 0x0312 Reserved o 0x0314 PWMO WIDTHB RI Width of output B pulse in Period Clock cycles Ox0316 Reserved OxX031A Reserved o OxO31E Reserved TI Pulse Width Modulator 1 b 15 0 ID Register 0x0003 0x0342 PWM i MODE b 0 1 Enable PWM 0 Disable PWM 0x0344 PWM1 CLK b 7 4 X Period Clock Source 15 0 Clock Bus 15 0 b 3 0 Width Clock Source 15 0 Clock_Bus 15 0 0x0346 Reserved 0x0348 PWM1 PERIOD b 15 0 Period of PWM Cycle is Width _ Clock _ Frequency PWMx _ PERIOD 1 0x034A Reserved 0x034E 0x0350 PWM1 WIDTHA b 15 0 Width of output A pulse in Period Clock cycles RTD Embedded Technologies Inc www rtd com 35 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex OOOO Dasz Reserved L0x0354 PWMi WIDTHE LBE Width of output B pulse in Period Glock cycles fass Reseved le Tox0s5A Reseved T COx035E Resewed O OOS U ox1010 TCB COUNTER 0 oo Counter Regster Dag TCB_COUNTER 1 b 7 0 CounteriRegister 6 3 Detailed Register Description The following sections provide a detailed description of the individual registers In the following register description sections each register is describe
54. er to PC 104 Plus Specification Revision 1 0 for the pinout of this connector This is a pass through connector The DM7820HR connects to the power and ground pins only and does not use any of the signals RTD Embedded Technologies Inc www rtd com 15 DMx820 User s Manual laa Accessing the Analog World 3 4 Steps for Installing 10 11 12 13 14 15 16 RTD Embedded Technologies Inc Always work at an ESD protected workstation and wear a grounded wrist strap Turn off power to the PC 104 system or stack Select and install stand offs to properly position the module on the stack Remove the module from its anti static bag Check that pins of the bus connector are properly positioned Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack Gently and evenly press the module onto the PC 104 stack If any boards are to be stacked above this module install them Attach any necessary cables to the PC 104 stack Re connect the power cord and apply power to the stack Boot the system and verify that all of the hardware is working properly elie S LT LA SA NC A lir de Figure 3 Example 104 Stack www rtd com 16 DMx820 User s Manual Accessing the Analog World 4 IDAN Connections 4 1 Module H
55. es generated by the modules in the Control Block and the interrupt sources within the modules Each level must be enabled in the previous level Figure 9 shows a block diagram of the interrupt sources Note that there are some other sources in the PLX bridge chip consult the datasheet for more details DMA Channel 0 Done D Q Se Ww D Q DMAMODEO 10 DMA Channel 0 TC x STATI INTCSRI18 oH DMAMODEQ 17 53 gt gt KINA DMAPRO 2 x ENA Ps DMA Channel 1 Done4 D Q E D Q DMAMODE1 10 5G DMAMODE 1 17 INT STAT 16 0 DMAPR1 2 gt D Q INT ENA 16 0 CNTRL 20 Modules Control Block PLX Figure 9 Interrupt Diagram Advanced Triggering Examples The modules on the DMx820HR can be combined to generate a broad range of complex sampling scenarios The following example shows how to use the Advanced Interrupt and 4 counters to capture N words before and M words after an event Programmable Clock 0 is the sample clock and is used to clock data into the FIFO It is started after all of the other Programmable clocks are initialized As soon as it starts Programmable Clock 1 starts counting samples to be captured before the triggering event This is also kn
56. functionally the same as writing two separate read back commands at the same time If counter status latching is carried out multiple times before each reading other than the first one is ignored here again The example is shown below Command Content Counter 2 Dz AAA em Count gg BE Count Status Read back status and count perm 0 m 1 u ha ba ba ba b laa Read back status counter 1 back status counter 1 L L l lrt i DDDDDDDE eee SES i 1 1 0 1 1 0 0 0 Read back status counter 2 Read back status counter 2 L Read back status and count SCC acai ie spo L all el ng vaer sans camera t A e ft Note The latch command at this time point is ignored and the first latch command is valid If both the count and status are latched the status latched in the first counter read operation is read The order of count latching and status latching is irrelevant The count s of the next one or two reading operations is or are read RTD Embedded Technologies Inc www rtd com 66 DMx820 User s Manual 64 PLX Registers The PLX9056 PCI Accelerator on the DMx820HR contains several registers to control interrupts and the two DMA engines These engines allow data to be transferred on demand with no load on the processor The following sections describe the registers used for programming the DMA engines This information is taken from PLX PCI9065BA Datasheet For more information please consult the datasheet 6 4 1 M
57. g Clock 3 Post Capture clock a Period M samples after event b Master Clock Prog Clock 0 c Start Event AdvintO d One Shot 6 FIFOO a Data In any b Data in clock Prog Clock 0 c Data out clock Prog Clock 2 before Advint0 d Data out clock PCI Read after Adv Int0 e DReq0 Read Ready RTD Embedded Technologies Inc www rtd com 26 DMx820 User s Manual Accessing the Analog World 6 Board Operation and Programming 6 1 PCI Interface This board attaches to the PCI bus using a PLX PCI9056 The PCI9056 is operating in C Mode Most of the registers in the PLX chip are automatically programmed at power up by the on board EEPROM or by the system BIOS The only PLX registers that the user needs to access are the DMA registers found on page 67 and the Configuration Registers found in Table 8 below For more information on the PLX PCI9056 bridge chip contact PLX Technologies www plxtech com Table 8 PCI Configuration Registers PCI Config Register Name Register Address Hex oo PeDe Dor POlVendorID OxidBb 0x04 POlSaus POlCommand ai Por Base Address Register 0 Memory Access fo PLX9056 Registers at Por Base Address Register 1 1 0 Access to PLX9056 Registers Oxi8 PCiBase Address Register 2 Memory Access to Digital lO Registers SCS 0x20 Resewd T oa Resewed
58. gister bits that caused the interrupt also clears the interrupt DMA Channel 0 Interrupt Enable Writing 1 Yes Yes enables DMA Channel 0 interrupts Used in conjunction with the DMA Channel 0 Interrupt Select bit DMAMODEO 17 Setting the DMA Channel 0 Clear Interrupt bit DMACSRO 3 1 also clears the interrupt DMA Channel 1 Interrupt Enable Writing 1 Yes Yes enables DMA Channel 1 interrupts Used in conjunction with the DMA Channel 1 Interrupt Select bit DMAMODE1 17 Setting the DMA Channel 1 Clear Interrupt bit DMACSR1 3 1 also clears the interrupt indicates the Local Doorbell interrupt is active indicates the DMA Channel 0 interrupt is active indicates the DMA Channel 1 interrupt is active Built In Self Test BIST Interrupt Active Yes Reading 1 indicates the BIST interrupt is active The BIST interrupt is enabled by writing 1 to the PCI Built In Self Test Interrupt Enable bit 1 x D o 0 1 co Co esch 20 21 22 23 O PCIBISTR 6 1 Clearing the Enable bit PCIBISTR 6 0 also clears the interrupt Note Refer to the PCIBISTR register for a description of the self test RTD Embedded Technologies Inc www rtd com 74 DMx820 User s Manual Accessing the Analog World Bus Master during a Master or Target Abort W Reading 0 indicates that DMA Channel 0 was the elek Bus Master during a Master or Target Abort 0 indicates that DMA Channel 1 was the
59. gital I O Block Diagram FIFOs The DMx820HR provides two FIFOs to buffer data going into and out of the board Each FIFO is 16 bit wide and 2 097 661 Words deep The input strobe output strobe and data input for each FIFO can be individually selected The output data is made available to the peripheral outputs and also the PCI interface Each FIFO is attached to a DMA Channel in the PLX chip FIFOO is attached to DMAO and FIFO1 is attached to DMA1 FIFOO can have its input data attached to its output data In this case the same data is repeated forever This is useful for some types of pattern generation Internally the FIFO system consists of a single 8MB SDRAM device with 255 word input and output buffers for each channel When data is available in the input buffer it is moved into the area of SDRAM device for that channel When data is in the SDRAM device and there is room available in the output buffer data is moved to the output buffer All of the internal data movement is handled automatically Greatest data efficiency is achieved when there are at least 128 words of data in the FIFO The FIFO also provides Write Request and Read Request signals For these signals the internal buffers are monitored to signal when data can be sent into and read from the FIFO The Write Request is asserted when there are at least 256 words of space available in the FIFO and negated when there are less than 128 words available The Rea
60. h assembling the IDAN stack by installing screws of an appropriate length Attach any necessary cables to the IDAN system Re connect the power cord and apply power to the stack Boot the system and verify that all of the hardware is working properly o oo St oe SS qux cx _ r Figure 6 Example IDAN System RTD Embedded Technologies Inc www rtd com 22 DMx820 User s Manual Accessing the Analog World 5 Functional Description 9 1 Block Diagram Below is a block diagram of the DMx820HR Primary board components are in bold while external I O connections and jumpers are italicized 48 Digital I O 25 MHz Clock Digital I O FPGA 82C54 Timer Counters PLX PCI9056 or PEX8311 Figure 7 DMx820HR Block Diagram RTD Embedded Technologies Inc www rtd com 23 DMx820 User s Manual 5 2 S Accessing the Analog World Internal Architecture A diagram of the standard I O is shown in Figure 10 Each digital I O pin can be an input output or peripheral output The peripheral outputs are the Pulse Width Modulators FIFO Timer Counters etc Peripheral 3 Peripheral 2 K Peripheral 1 Peripheral 0 E qr gt lt gt D Q P gt 2 MF PORTx_OUTPUT E PORTx PERIPH SEL PORTx TRISTATE B Q PORTx MODE Peripheral Q D lt Data Readback PORTx_INPUT Figure 8 Di
61. he FIFO before requesting the Local Bus for writes Nybble values Oh through Eh may be used Refer to Table 17 15 COPLAF COLPAE DMA Channel 0 Local to PCI Almost Empty COLPAE Number of empty Lword x 2 entries plus 1 times 2 in the FIFO before requesting the Local Bus for reads Nybble values Oh through Eh may be used Refer to Table 17 15 COPLAF COLPAE DMA Channel 0 Local to PCI Almost Full COLPAF Number of full Lword x 2 entries plus 1 times 2 in the FIFO before requesting the PCI Bus for writes Nybble values Oh through Eh may be used Refer to Table 17 RTD Embedded Technologies Inc www rtd com 71 DMx820 User s Manual Accessing the Analog World DMA Channel 0 PCI to Local Almost Empty COPLAE Number of empty Lword x 2 entries plus 1 times 2 in the FIFO before requesting the PCI Bus for reads Nybble values Oh through Eh may be used Refer to Table 17 DMA Channel 1 PCI to Local Almost Full C1PLAF Number of full Lword x 2 entries plus 1 times 2 in the FIFO before requesting the Local Bus for writes Nybble values Oh through Eh may be used Refer to Table 17 15 C1PLAF gt C1LPAE DMA Channel 1 Local to PCI Almost Empty C1LPAE Number of empty Lword x 2 entries plus 1 times 2 in the FIFO before requesting the Local Bus for reads Nybble values Oh through Eh may be used Refer to Table 17 15 C1PLAF gt C1LPAE DMA Channel 1 Local to PCI Alm
62. he PCI Bus The PCI 9056 supports Memory Write and Invalidate sizes of 8 or 16 Lwords The size is specified in the System Cache Line Size bits PCICLSR 7 0 If a size other than 8 or 16 is specified the PCI 9056 performs Write transfers rather than Memory Write and Invalidate transfers Transfers must start and end at cache line boundaries PCICR 4 must be set to 1 EOT Enable Writing 1 enables the EOT input pin Writing O disables the EOT input pin If DMAMODEO 14 and DUAMODE1 14 00b the EOT pin becomes the DMPAF pin Fast Slow Terminate Mode Select Writing 0 sets the PCI 9056 into Slow Terminate mode As a result BLAST is asserted on the last Data transfer to terminate the DMA transfer Writing 1 sets the PCI 9056 into Fast Terminate mode and indicates the PCI 9056 DMA transfer terminates immediately when EOT if enabled is asserted or during DMA Demand mode when DREQOXZ is de asserted Clear Count Mode Writing 1 clears the byte count in Yes Yes X each Scatter Gather descriptor when the corresponding DMA transfer is complete RTD Embedded Technologies Inc www rtd com 68 DMx820 User s Manual Accessing the Analog World Interrupt Select Writing 1 routes the interrupt to the PCI interrupt INTA Writing O routes the interrupt to the Local interrupt output LINTo DAC Chain Load When set to 1 enables the descriptor to load the PCI Dual Address Cycles value Otherwise the descriptor l
63. he PCI Bus writes to MBOXO through MBOXGS To clear a LINTo interrupt the Local Bus Master must read the Mailbox Used in conjunction with the Local Interrupt Output Enable bit INTCSR 16 Power Management Interrupt Enable Writing 1 enables a Local interrupt output LINTo to be asserted when the Power Management Power State changes Power Management Interrupt When set to 1 Yes Yes Clr indicates a Power Management interrupt is pending A Power Management interrupt is caused by a change in the Power Management Control Status register Power State bits PMCSR 1 0 Writing 1 clears the interrupt Writable from the PCI Bus only in the DO power state Direct Master Write Direct Slave Read Local Yes Yes Data Parity Check Error Enable Writing 1 enables a Local Bus Data Parity Error signal to be asserted through the LSERR pin INTCSR 0 must be enabled for this to have an effect Direct Master Write Direct Slave Read Local Yes Yes Clr Data Parity Check Error Status When set to 1 indicates the PCI 9056 has detected a Local data parity check error even if Parity Check Error is disabled INTCSR 6 0 Writing 1 clears this bit to O PCI Interrupt Enable Wing 1 enables PC interrupts INTA RTD Embedded Technologies Inc www rtd com 73 DMx820 User s Manual Accessing the Analog World PCI Doorbell Interrupt Enable Writing 1 Yes enables Local to PCl Doorbell interrupts Used in conjunction with t
64. he PCI Interrupt Enable bit INTCSR 8 Clearing the L2PDBELL register bits that caused the interrupt also clears the interrupt PCI Abort Interrupt Enable Value of 1 enables Yes Yes a Master Abort or Master detection of a Target Abort to assert a PCI interrupt INTA Used in conjunction with the PCI Interrupt Enable bit INTCSR 8 Clearing the Received Master and Target Abort bits PCISR 13 12 also clears the PCI interrupt Local Interrupt Input Enable Writing 1 enables Yes Yes a Local interrupt input LINTi assertion to assert a PCI interrupt INTA Used in conjunction with the PCI Interrupt Enable bit INTCSR 8 De asserting LINTi also clears the interrupt Retry Abort Enable Writing 1 enables the PCI Yes Yes 9056 to treat 256 consecutive Master Retries to a Target as a Target Abort Writing O enables the PCI 9056 to attempt Master Retries indefinitely NO zech CH Yes i indicates the PCI Doorbell interrupt is active 14 PCI Abort Interrupt Active When set to 1 Yes No indicates the PCI Master or Target Abort interrupt is active Local Interrupt Input Active When set to 1 Yes indicates the Local interrupt input LINTi is active Ye enables Local interrupt output LINTo 7 Local Doorbell Interrupt Enable Writing 1 Yes enables PCl to Local Doorbell interrupts Used in conjunction with the Local Interrupt Output Enable bit INTCSR 16 Clearing the P2LDBELL re
65. he board All internal registers are set to their default values Note The 82C54 Timer Counters are not affected by this register 15 0 RESET W 0000 0000 0000 0000 Write 0xA5A5 to reset the board All other writes are ignored Reads will return all zeros This register contains status information for the board BRD_STAT 15 1 H Reserved MSTR R 0 Feld Description Indicates if the board is PCI master capable based on the rotary switch and jumper settings O PCI Master 1 Not PCI Master INT ENABLE This register controls which interrupt sources are used to generate a local interrupt 15 14 13 12 11 10 9 8 FIFO FIFOO PCIk3 PCI PCIK1 PCIKO PWM PWMO 7 6 5 4 3 2 1 0 82C54 Advint AdvintO Feld X A A Desertptton AdviIntO Interrupt from Advance Interrupt block at 0x0200 0 Interrupt Disabled 1 Interrupt Enabled AdvInt1 Interrupt from Advance Interrupt block at 0x0240 0 Interrupt Disabled 1 Interrupt Enabled 82C54 Interrupt 82C54 Timer Counter block at 0x0080 0 Interrupt Disabled 1 Interrupt Enabled RTD Embedded Technologies Inc www rtd com 37 DMx820 User s Manual Accessing the Analog World IncEncO Interrupt from Incremental Encoder block at 0x0280 0 Interrupt Disabled 1 Interrupt Enabled IncEnc1 Interrupt from Incremental Encoder block at 0x02CO0 0 Interrupt Disabled 1
66. igger input arrives before the end of a half cycle of the square wave after writing the new count value the new count value is loaded in the CE at the falling edge of the next clock pulse and counting continues using the new count value If there is no gate trigger the new count value is loaded at the end of the half cycle and counting continues e Even number counting operation The output is initially set to H level The initial count value is loaded to the CE at the falling edge of the next clock pulse and is decremented by 2 by consecutive clock pulses When the counter value becomes 2 the output is set to L level the initial value is reloaded and then the above operation is repeated e Odd number counting operation The output is initially set to H level At the falling edge of the next clock pulse the initial count value minus one is loaded in the CE and then the value is decremented by 2 by consecutive clock pulses When the counter value becomes 0 the output is set to L level and then the initial count value minus 1 is reloaded to the CE The value is then decremented by 2 by consecutive clock pulses When the counter value becomes 2 the output is again set to H level and the initial count value minus 1 is again reloaded The above operations are repeated In other words the output is set to H level during N 1 2 counting and to L level during N 1 2 counting in the case of odd number counting M
67. ions on page 77 This board is a Universal board and can connect to either a Type 1 or Type 2 PCle 104 connector PC 104 Plus PCI Connector The PC 104 Plus connector carries the signals of the PC 104 Plus PCI bus Refer to PC 104 Plus Specification for the pinout of this connector The DM9820HR connects to the power and ground pins only and does not use any of the signals The DM7820HR uses this connector for communication with the CPU PCI Configuration Options DM7820HR Onl To install the DM7820HR into the stack the PCI Slot Number must be configured correctly This is done by the PCI Slot Selector located at SW There are four possible PCI Slot Numbers 0 3 Each PCI device PC 104 Plus or PCl 104 must a use a different slot number The slot number is related to the position of the board in the stack Slot 0 represents the PCI device closest to the CPU Slot 3 represents the PCI devices farthest away from the CPU NOTE In a PC 104 Plus or PCI 104 system all PCI devices should be located on one side of the CPU board above or below the add on cards The CPU should not be located between two PCI devices Switch SW1 PCI Slot Selector When the PC 104 Plus Specification was first introduced it only allowed for three PCI add on cards to be bus masters Version 2 0 of the PC 104 Plus specification was released in November 2003 This version of the specification which the DM7820HR is designed for adds support fo
68. lock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Heserved 5 MHz OO nm CO P OI O CO O 6 3 4 FIFO CHANNEL N The DMx820HR provides two FIFOs to buffer data going into and out of the board Each FIFO is 4MB in size The input strobe output strobe and data input for each FIFO can be individually selected The output data is made available to the peripheral outputs and also the PCI interface Each FIFO is attached to a DMA Channel in the PLX chip FIFOO is attached to DMAO and FIFO1 is attached to DMA1 FIFOn ID ID register to identify a FIFO Block 15 0 ID Register ID Register15 0 Value of 0x2011 indicates SDRAM FIFO Block RTD Embedded Technologies Inc www rtd com 44 DMx820 User s Manual Accessing the Analog World FIFOn_INT Enable and status for the interrupts generated by the FIFOs An Overflow condition occurs when the FIFO is full and it is written to It can also occur when the FIFO is written to too fast An Underflow occurs when the FIFO is empty and the output clock toggles or when the FIFO is read from too fast When the FIFO is disabled the Full Empty and both requests are asserted 15 8 7 0 Field BDescipion INT STAT 7 0 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear Interrupts are asserted on the positive edge of the clock INT ENA 7 0 Interrupt Enable
69. lock sources for the period and width of the PWM output 15 8 7 4 3 0 PER CLK 3 0 WIDTH CLK 3 0 Feld Description PER CLK 3 0 Selects the master clock for the period counter Value definitions are Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe1 Prog Clock 3 Prog Clock 2 Prog Clock 1 RTD Embedded Technologies Inc www rtd com of DMx820 User s Manual Accessing the Analog World Field Description Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Heserved 25 MHz WIDTH CLKT 3 0 Selects the master clock for the width counter See above for value definitions PWMn PERIOD Sets the maximum width of the PWM outputs If the period clock and width clock are the same PWMn CLK PER CLK PWMn CLK WIDTH CLK this will also set the PWM period See Figure 12 on page 57 for more details 8 H 6 5 4 3 2 1 0 15 0 PERIOD 15 0 RW 0 Field A Descrpton PERIOD 15 0 The period of the output is the next period clock after PERIOD 1 Width _ Clock _ Frequency PWMn_WIDTHx Sets the width of output x of the pulse width modulator The width is based on the clock selected in PWMn_CLK WIDTH_CLK The width is defined as the time that the non inverted output is high and the inverted output is low The width register is checked at the beginning of every period If the width register is modified in
70. nterrupt has not occurred 1 Interrupt has occurred Write 1 to clear 82C54 Interrupt 82C54 Timer Counter block at 0x0080 Uz Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear IncEncO Interrupt from Incremental Encoder block at 0x0280 O Interrupt has not occurred 1 7 Interrupt has occurred Write 1 to clear Interrupt from Incremental Encoder block at 0x02CO RTD Embedded Technologies Inc www rtd com 38 DMx820 User s Manual 6 3 2 STANDARD I O Accessing the Analog World O Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Interrupt from Pulse Width Modulator block at 0x0300 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Interrupt from Pulse Width Modulator block at 0x0340 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Interrupt from Programmable Clock block at 0x0100 O Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Interrupt from Programmable Clock block at 0x0140 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Interrupt from Programmable Clock block at 0x0180 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to clear Interrupt from Programmable Clock block at 0x01C0 0 Interrupt has not occurred 1 Interrupt has occurred Write 1 to cle
71. o clear Interrupts are asserted on the positive edge of the clock l 0x008E IC B2 CONTROL b 7 6 b 5 0 Reserved Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are TC B2 TC B1 TC BO TC A2 TC A1 TC AO b 15 13 Reserved b 12 8 Gate Select 31 16 Port 2 15 0 15 2 Clock Bus 15 2 1 0 b 7 4 b 3 0 q es t0 Reserved Clock Select 15 2 Clock_Bus 15 2 1 0 reserved 5 MHz FIFO Channel 0 0x00CO FIFOO ID b 15 0 ID Register 0x201 1 b 15 8 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear i 7 i RTD Embedded Technologies Inc www rtd com b 7 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are b 15 5 b 4 0 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 b 15 5 b 4 0 Reserved Reserved Underflow Overflow Empty Full Write Request Read Request Reserved Input Clock Select Reserved Input Clock Select 31 PCI Write 30 PCI Read 29 16 Interrupts 13 0 15 0 Clock_Bus 15 0 29 DMx820 User s Manual Accessing the Analog World Table 9 DMx820HR Memory Map Offset Register Name Register Function Hex b 15 10 Reserved b 9 8 0x00C8 FIFOO IN DATA DREQ 0Ox00CA FIFOO CON STAT DREQO Source Not Full Write Request Not Empty Read Request
72. o monitor the counter output so the corresponding hardware may be omitted d d d d d D D Do ourpUr NULE Ra Ro M2 Mf MO BCD COUNT D7 12 Output pin status is 1 0 Output pin status is 0 De 12 Null count 0 Count value reading is effective Ds Do Programmed mode of counter See the control word format Null count indicates the count value finally written in the counter register CR has been loaded in the counter element CE The time when the count value was loaded in the CE depends on the mode of each counter and it cannot be known by reading the counter value because the count value does not tell the new count value if the counter is latched The null count operation is shown below Operation Result A Control word register writing Null count 1 B Count register CR writing Null count 7 1 RTD Embedded Technologies Inc www rtd com 65 DMx820 User s Manual Accessing the Analog World C New count loading to CE CR gt CE Null count 0 Note The null count operation for each counter is independent When the 2 byte count is programmed the null count is set to 1 when the count value of the second byte is written If status latching is carried out multiple times before status reading other than the first status latch is ignored Simultaneous latching of the count and status of the selected counter is also possible For this purpose set bits D4 and D3 COUNT and STATUS bits to 00 This is
73. oads the DMADACO register contents EOT End Link Used only for DMA Scatter Gather transfers Value of 1 indicates that when EOT is asserted the DMA transfer ends the current Scatter Gather link and continues with the remaining Scatter Gather transfers Value of 0 indicates that when EOT is asserted the DMA transfer ends the current Scatter Gather transfer and does not continue with the remaining Scatter Gather transfers 20 Ring Management Valid Mode Enable Value of 0 indicates the Ring Management Valid bit DMASIZO 31 is ignored Value of 1 indicates the DMA descriptors are processed only when the Ring Management Valid bit is set DMASIZO 31 1 If the Valid bit is set the transfer count is 0 and the descriptor is not the last descriptor in the chain The DMA Controller then moves to the next descriptor in the chain Note Descriptor Memory fields are re ordered when this bit is set Ring Management Valid Stop Control Value of 0 indicates the DMA Scatter Gather controller continuously polls a descriptor with the Valid bit set to O invalid descriptor if Ring Management Valid Mode is enabled DMAMODEO 20 1 Value of 1 indicates the Scatter Gather controller stops polling when the Ring Management Valid bit with a value of 0 is detected DMASIZO 31 20 In this case the CPU must restart the DMA Controller by setting the Start bit DMACSRO 1 1 A pause clearing the Start bit DMACSRO 1 0 sets the DMA Done bit DMACSRO 4
74. ode 4 e Application Software trigger strobe e Output operation The output is initially set to H level When the counter value becomes 0 the output goes to L level during one clock pulse and then restores H level again The count sequence starts when the initial count value is written e Gate function H level validates counting and L level invalidates counting The gate signal does not affect the output e Count value load timing After the control word and initial count value are written the count value is loaded to the CE at the falling edge of the next clock pulse The clock pulse does not decrement the initial count value If the initial count value is N the strobe is not output unless N 1 clock pulses are input after the initial count value is written e Count value writing during counting The new count value is written to the CE at the falling edge of the next clock pulse and counting continues using the new count value The operation for 2 byte count is as follows o First byte writing does not affect the counting operation o After the second byte is written the new count value is loaded to the CE at the falling edge of the next clock pulse e This means that the counting operation is retriggered by software The output strobe is set to L level upon input of N 1 clock pulses after the new count value N is written Mode 5 e Application Hardware trigger strobe e Output operation The output is
75. ogies Inc www rtd com 46 DMx820 User s Manual Accessing the Analog World The Not Full and Not Empty request source should only be used if the amount of data in the FIFO is known or to finish filling emptying the FIFO The DMA engine on the PLX PCI9056 will complete an additional double word transfer after the request is negated Therefore using the Not Full and Not Empty request source will generally result in an over run under run condition whenever the signal is negated The DREQ signals are in an undefined state when the FIFO is disabled The DMA engine should only be enabled after the FIFO is enabled FIFOn_CON_STAT ENA 15 10 9 8 H 2 1 0 DREQ SRC 1 0 IN DATA 1 0 Field Description DREQ SRC 1 0 Selects the source for the DREQn signal to the PLX chip Value definitions are 3 Not Full 2 Write Request 1 Not Empty O0 Read Request IN DATA 1 0 Selects the FIFO Input Data Value definitions for FIFOO are 3 FIFOO Output 2 Port2 1 Port0O 0 PCI Data Value definitions for FIFO1 are 3 Incremental Encoder 1 Channel B Value 2 ncremental Encoder 1 Channel A Value 1 Port1 0 PCI Data FlIFOn CON STAT This register is used to enable the FIFO When the FIFO is disabled it is internally reset and all data is flushed from it This register also is used to read the current status of the Write Request and Read Request signals that are used for DMA Requests
76. ogrammable clocks o Maximum frequency of 25 MHz o Can be started and stopped by an interrupt or another clock o Continuous or One Shot Operation o Can be cascaded e 82C54 Timer Counters o Six Timer Counter Channels o Fully programmable o Input clock and gate driven from internal or external source o 10MHz maximum input O O O OQ O O 0 O O OOO RTD Embedded Technologies Inc www rtd com 8 DMx820 User s Manual Accessing the Analog World 1 3 Ordering Information The DMx820HR is available with the following options Table 1 Ordering Options Part Number Description DM 820HR DM7820HR The Intelligent Data Acquisition Node IDAN building block can be used in just about any combination with other IDAN building blocks to create a simple but rugged 104 stack This module can also be incorporated in a custom built RTD HIDAN or HiDANplus High Reliability Intelligent Data Acquisition Node Contact RTD sales for more information on our high reliability systems 14 Contact Information 1 4 1 SALES SUPPORT For sales inquiries you can contact RTD Embedded Technologies sales via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail sales rtd com 1 4 2 TECHNICAL SUPPORT If you are having problems with you system please try the steps in the Troubleshooting section of this manual on page76 For help with this product or any other produc
77. ost Full C1LPAF Number of full Lword x 2 entries plus 1 times 2 in the FIFO before requesting the PCI Bus for writes Nybble values Oh through Eh may be used Refer to Table 17 DMA Channel 1 PCI to Local Almost Empty C1PLAE Number of empty Lword x 2 entries plus 1 times 2 sin the FIFO before requesting the PCI Bus for reads Nybble values Oh through Eh may be used Refer to Table 17 Table 17 DMA Threshold Nybble Values Nybble Value Setting Nybble Value Setting Nybble Value Geng 3h 4h h h h 3h t6Lwortds h 120 words RTD Embedded Technologies Inc www rtd com 72 DMx820 User s Manual DMADAn DMA PCI Dual Address Cycle Upper Address Bl Description Read Accessing the Analog World Upper 32 Bits of the PCI Dual Address Yes Yes h X Cycle PCI Address during DMA Cycles If set to Oh the PCI 9056 performs a 32 bit address DMA access INTCSR Interrupt Control Status Register Writing 1 enables LSERR to be asserted upon detection of a Local parity error or PCI Abort es es Writing 1 enables LSERR to be asserted upon Y Yes detection of an SERR assertion in Host mode or detection of a PCI parity error or a messaging queue outbound overflow S Generate PCI Bus SERR Interrupt When set Ye to 0 writing 1 asserts the PCI Bus SERR interrupt Mailbox Interrupt Enable Writing 1 enables a Local interrupt output LINTo to be asserted when t
78. own as pre fill When it expires it starts Programmable Clock 2 which removes samples from the FIFO at the same rate that they are stored keeping a constant number of samples in the FIFO When the triggering event happens Programmable Clock 2 is stopped and the FIFO begins to fill Also the triggering event starts Programmable Clock 3 which counts the number of samples to be captured after the triggering event When Programmable Clock 3 expires it stops Programmable Clock 0 and data collection ends The triggering event can also generate an interrupt that changes the FIFO output to PCI Read and start DMA transfers This allows the data to be moved to system memory before data collection has ended 1 AdvintO a Setto event desired b During the Interrupt Service Routine i Change FIFO output clock to PCI Read ii Start DMA transfers 2 Prog Clock 0 Sample Input Clock a Period sample period RTD Embedded Technologies Inc www rtd com 25 DMx820 User s Manual Accessing the Analog World b Master Clock any C Start Event always d Stop Event Prog Clock 3 e Continuous operation 3 Prog Clock 1 Pre capture clock a Period N samples before event b Master Clock Prog Clock 0 C Start Event always d One shot 4 Prog Clock 2 Sample output clock a Period same as Prog Clock 0 b Master Clock same as Prog Clock 0 c Start Event Prog Clock 1 d Stop Event Advint 0 e Continuous 5 Pro
79. pulated For a description of each jumper and connector refer to the following sections PC 104 Plus Connector JP2 PCI Master Control uc E B1 Ed EXNXXXRXRNENARRRRRRENNE a X IEEE HEURE CHEN H Ge Force Three Master CN10 CN11 ut Digital I O Digital O ____ J R48 R57 TMA eet a A dese SW 7 PC 104 Connector Slot Selection DM7820 Only Figure 1 DM7820HR and DM8820HR Connectors and Jumpers RTD Embedded Technologies Inc www rtd com 11 DMx820 User s Manual Accessing the Analog World 3 9 1 DM35820HR AND DM9820HR The following diagram shows the location of all connectors and jumpers on the DM9820HR For a description of each jumper and connector refer to the following sections PC 104 Plus Connector DM9820HR only CN11 gt EI e CN10 Digital VO mec EE 4 Digital I O f LA LI LU LE LI LI mt Titi eg r ei em SS D C E MH A III VE Le ar ss HUTT PC 104 Express Connector Figure 2 DM7820HR and DM8820HR Connectors and Jumpers 3 3 2 EXTERNAL I O CONNECTORS NOTE Pin 1 can be identified by a square solder pad Pins 2 50 have round solder pads Connector CN10 Digital Input Output Connector CN10 provides 24 digital input output lines along with a 5V pin and ground pins The pin assignments for CN10 are shown in Table 1 Table 4 CN10 Pin Assignments RTD Embedded Technologies Inc www rtd com 12 DMx8
80. pulse in this case When the gate signal is set to H level the output is set to H level after the lapse of N clock pulses Since the count value is already loaded in the CE no clock pulse for loading in the CE is necessary Mode 1 e Application Digital one shot e Output operation The output is set to H level by the control word setting It is set to L level at the falling edge of the clock succeeding the gate trigger and kept at L level until the counter value becomes 0 Once the output is set to H level it is kept at H level until the clock pulse succeeding the next trigger pulse e Count value load timing After the control word and initial count value are written the count value is loaded to the CE at the falling edge of the clock pulse succeeding the gate trigger and set the output to L level The one shot pulse starts in this way If the initial count value is N the one shot pulse interval equals N clock pulses The one shot pulse is not repetitive e Gate function The gate signal setting to L level after the gate trigger does not affect the output When it is set to H level again from L level gate retriggering occurs the CR count value is loaded again and counting continues e Count value writing during counting It does not affect the one shot pulse being counted until retriggering occurs Mode 2 e X Application Rate generator real time interrupt clock e Output operation The out
81. put is set to H level by control word setting When the initial count value is decremented to 1 the output is set to L level during one clock pulse and is then set to H level again The initial count value is reloaded and the above sequence repeats In mode 2 the same sequence is repeated at intervals of N clock pulses if the initial count value is N for example e Gate function H level validates counting and L level invalidates it If the gate signal is set to L level when the output pulse is L level the output is immediately set to H level At the falling edge of the clock pulse succeeding the trigger the count value is reloaded and counting starts The gate input can be used for counter synchronization in this way e Count value load timing After the control word and initial count value is written the count value is loaded to the CE at the falling edge of the next clock pulse The output is set to L level upon lapse of N clock pulses after writing the initial count value N Counter synchronization by software is possible in this way e Count value writing during counting Count value writing does not affect the current counting operation sequence If new count value writing completes and the gate trigger arrives before the end of current counting operation the count value is loaded to the CE at the falling edge of next clock pulse and counting continues from the new count value If no gate trigger
82. r all 4 PCI slots to be bus masters There are two methods for compatibility with CPUs designed for the older PC 104 Plus Specification One method is to use slot positions 4 7 instead of the usual 0 3 The second is to short solder jumper B1 The PCI Slot Number can be configured as follows UMNELGMNEE I 7 ECH So 4 Jys Sot2 Kf yes 3 Sot yes 4 jShtO dcestoCPU 3 yes 55 Sot yes 6 a 3 4 WJP2 Jumper JP2 Bus Master Control Install JP2 to enable bus mastering when in Slot 2 or Slot 3 in three bus master mode RTD Embedded Technologies Inc www rtd com 14 DMx820 User s Manual Accessing the Analog World Solder Blob B1 Force Three Master The DM7820HR offers a configuration solder blob at location B1 If this solder blob is open the default the board supports bus mastering in all 4 PCI slots when SW1 is in position 0 3 If itis closed the board will work in a 3 bus master configuration If B1 is closed SW1 positions 0 3 will be identical to positions 4 7 NOTE The DM7820HR comes with solder blob B1 open by default This should be compatible with most PC 104 Plus CPUs There is no need to change this blob unless you are having compatibility problems with your specific CPU PC 104 ISA Connectors DM7820HR Only The PC 104 connectors carry the signals of the PC 104 Plus ISA bus Ref
83. rite 1 to clear b 3 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 3 Encoder B Negative Rollover 2 Encoder B Positive Rollover 1 Encoder A Negative Rollover 0 Encoder A Positive Rollover 0x0284 INCENCO CLOCK b 3 0 Master Clock Source 15 0 Clock Bus 15 0 0x0286 INCENCO MODE b 15 8 Phase Filter Writing a 1 to a specific bit masks out a phase transition b 7 6 Reserved b 5 Differential Mode 1 Pseudo differential mode 0 Single ended mode b 4 Input Filter 1 Enable Input Filter 0 Disable Input Filter b 3 Join 1 Operate as single 32 bit Encoder 0 Operate as two 16 bit Encoders b 2 0 External Index is disabled 1 External Index is enabled b 1 Hold Register 1 Hold values register 0 Allow value register to change b 0 Count Enable 1 Encoder is enabled 0 Encoder is cleared 0x0288 INCENCO VALUEA b 15 0 Value for Encoder A 0x028A INCENCO VALUEB b 15 0 Value for Encoder B Dual Incremental Encoder 1 0x02CO INCENC1 ID b 15 0 ID Register 0x0002 0x02C2 INCENC1 INT b 11 8 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear b 3 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are 3 Encoder B Negative Rollover 2 Encoder B Positive Rollover 1 Encoder A Negative
84. robe2 14 Inverted Strobe1 RTD Embedded Technologies Inc www rtd com 48 DMx820 User s Manual PRGCLKn START STOP OO nm GO P OI O 4 CO O 13 Strobe2 12 Strobel1 11 Prog Clock 3 10 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO Heserved 25 MHz Accessing the Analog World This register selects the Start and Stop Trigger for the programmable clock The clock will not begin generating an output until the first positive edge of the Start Trigger The first edge of the programmable clock output will occur one period after the Start Trigger edge If in continuous mode the clock will continue to run until the first edge of the Stop Trigger After the clock has stopped it must be disabled and re enabled for it to start again if in Continuous mode The clock should be disabled before modifying this register 15 13 12 8 H 5 4 0 STOP _TRG 4 0 START _TRG 4 0 START TRGIA 0 RTD Embedded Technologies Inc www rtd com OO nm CO P OO M CO O Selects the start trigger Value definitions are FIFO1 Interrupt FIFOO Interrupt Prog Clock 3 Interrupt Prog Clock 2 Interrupt Prog Clock 1 Interrupt Prog Clock 0 Interrupt PWM1 Interrupt PW MO Interrupt Reserved Reserved Incremental Encoder 1 Interrupt Incremental Encoder 0 Interrupt Reserved 82C54 Interrupt Advanced Interrupt 1 Interrupt Advanced Interrupt 0
85. rrupt 1 Input was 1 at last interrupt 6 3 7 DUAL INCREMENTAL ENCODER N Each Incremental Encoder block provides two encoder channels with 16 bit counters These two channels can be linked into a single 32 counter An Incremental Encoder is used to detect the relative position of a shaft or linear actuator A typical implementation is a slotted wheel with two optical sensors positioned such that when one sensor is positioned over a slot the other is positioned between slots The output of the optical sensors is shown in Figure 11 with one sensor named A and the other named B At every edge of the A or B input the counter either increments or decrements The direction can be interpreted from the state of the signals i e which signal leads Value 0 1 2 Figure 11 Incremental Encoder Signals The encoders include a Phase Filter that prevents the counter from counting on certain transitions This allows the encoders to count pulses and other specialized applications Encoder inputs can be configured as single ended or pseudo differential In pseudo differential mode the and inputs must be the inverse of each other in order for the encoder to see a change Digital filtering can be selected With digital filtering a transition on a line is only considered valid if it remains constant for four clock cycles The clock can be selected Separate interrupts are generated for positive
86. s Burst 4 mode Writing 1 additionally enables BTERM input which when asserted overrides the READY input state if READY is enabled DMAMODEO 6 1 Notes This bit is referred to as the BTERM Input Enable bit Refer to Section 4 2 5 of the PCI9056 datasheet for further details L t e m EUIS o Writing O disables Local bursting Scatter Gather Mode Writing 1 indicates DMA Scatter Gather mode is enabled For Scatter Gather mode the DMA source and destination addresses and byte count are loaded from memory in PCI or Local Address spaces Writing O indicates DMA Block mode is enabled Done Interrupt Enable Writing 1 enables an interrupt when done Writing O disables an interrupt when done If DMA Clear Count mode is enabled DMAMODEO 16 1 the interrupt does not occur until the byte count is cleared Local Addressing Mode Writing 1 holds the Local Yes Yes 1 Address Bus constant Writing 0 indicates the Local Address is incremented Demand Mode Writing 1 causes the DMA Controller to operate in Demand mode In Demand mode the DMA Controller transfers data when its DREQO input is asserted Asserts DACKO to indicate the current Local Bus transfer is in response to DREQO input The DMA Controller transfers Lwords 32 bits of data This may result in multiple transfers for an 8 or 16 bit bus 13 Memory Write and Invalidate Mode for DMA Transfers When set to 1 the PCI 9056 performs Memory Write and Invalidate cycles to t
87. selects the mode of operation for the Incremental Encoder 15 8 PHASE FLT 7 0 RW 0 7 6 5 4 Fied__ Descipion PHASE FLT 7 0 Phase Filter Selects if a particular state transition will cause the encoder counter to change For each bit Uz Transition will change counter 1 7 Transition will not change counter The bit assignments for the transitions are otate B A otate B A 7 Im 10 Selects single ended or differential mode 0 Single Ended Only inputs are used 1 Pseudo Differential RTD Embedded Technologies Inc www rtd com 55 DMx820 User s Manual Accessing the Analog World Pe Description FILTER Enable the input filter 0 Filter is disabled 1 Filter is enabled JOIN Used to join the two channels into a single 32 bit counter When the channels are joined only the Channel A inputs are used O Channels are independent 1 Channels are joined Index Enable When enabled a high input on the Index input clears the counter 0 Index Inputs Disabled 1 Index Input Enabled HOLD Register Hold When enabled the encoder continues counting in the background but the VALUE registers remain constant 0 VALUE registers are not held 1 VALUE registers are held ENA Enable for this incremental encoder O Encoder is disabled 1 Encoder is enabled INCENCn VALUEy Returns the current value of this increment
88. t made by RTD you can contact RTD Embedded Technologies technical support via the following methods Phone 1 814 234 8087 Monday through Friday 8 00am to 5 00pm EST E Mail techsupport grtd com RTD Embedded Technologies Inc www rtd com 9 DMx820 User s Manual Accessing the Analog World 2 Specifications 2 1 Operating Conditions Table 2 Operating Conditions Parameter 5V Supply Voltage p Operating Temperature of 85 C Ts Storage Temperature 55 d25 C _ RH Relative Humidity Non Condensing 0 9 MTBF Mean Time Before Failure 30 C Ground benign 3 292 579 S controlled 2 2 Electrical Characteristics Table 3 Electrical Characteristics dition P Power Consumption V s 50V o PCI Bus Vu Input High Voltage PCI Input Leakage PCI Hi Z Leakage Output High Voltage Output Low Voltage O1 c Ic CO 0 lt Vi lt VIO 0 lt Vi lt VIO Si no co rep N O O1 O oO OIO O1 PCle Bus NO lt Differential Output Voltage DC Differential TX Impedance Differential Inout Voltage 95 2 ech ech gt O A79 3 3 92 7 Impedance Electrical Idle Detect Threshold gta Input High Voltage 20 55 V Input Low Voltage 05 OB8 V Output High Voltage lon 24mA 24 ON Output Low Voltage ln 24mA 1 1 GAN 61 EN Lo aa DC Differential RX D N Co Digital
89. ter selects the peripheral for Port 0 Port 1 or Port 2 when it is a peripheral output i e PORTx_MODE 1 This register selects the peripheral for bits 15 8 Bu PORTx PERIPH SEL 10 t aS pu EE BN BEDS VEU HE PortO 6 M FIFO0 Out 6 FIFO1 Out 6 pO E E PP p p NENNEN FIFOO Out 7 FIFO1 Out 7 RTD Embedded Technologies Inc www rtd com 41 DMx820 User s Manual Accessing the Analog World Table 10 Peripheral Outputs PORTx PERIPH SEL 10 FIFO1 Out 14 FIFO1 Out 15 FIFO1 Out 0 FIFO1_Out 1 FIFO1 Out FIFO1 Out 3 FIFO1 Out 4 PortOo 14 PortO 15 Port1 O Port1 1 Port1 2 Port1 3 Port1 4 Port1 5 Port1 6 Port1 7 Port1 8 Port1 9 Port1 10 Port1 11 Port1 12 Port1 13 Port1 14 Port1 15 Port2 0 Port2 1 Port2 2 Port2 3 Port2 4 Port2 5 Port2 6 Port2 7 Port2 8 Port2 9 Port2 10 Port2 11 Port2 1 2 Port2 13 Port2 1 4 Port2 15 a SS SS po po e FIFOO Outf5 1 FIFO1_Out 5 JL FIFOO_Out 6 __ FIFO1_Oui 6 po FIFOO OUT FIFO1_Out 7 pC FIFOO_Out 8 __ FIFO1_Out 8 oS SS Po SS Po WG E Po po FIFOO Empty FIFO1 Empt FIFO1 Out 9 FIFO1 Out 10 FIFO1 Out 11 FIFO1 Out 12 FIFO1 Out 13 FIFO1 Out 14 FIFO1 Out 15 PWMO A FIFO1 Out O PWMO A FIFO1 Out 1 PWMO B FIFO1 Out 2 PWMO B FIFO1 Out 3 PWMO C FIFO1 Out 4 PWMO C FIFO1_Out 5 PWMO D FIFO1 Out 6 PWMO D FIFO1 Out 7 PWM1_A FIFO1 Out 8 PWM1_A FIFO1 Out 9 PWM1_B FIFO1_Out 10
90. the 82C54 Timer Counters 15 14 13 8 H 6 5 0 INT STAT 0 INT ENA 0 Field Descrpion INT STAT 5 0 Interrupt Status 1 Interrupt condition has occurred Write 1 to clear Interrupts are asserted on the positive edge of the clock INT ENA 5 0 Interrupt Enable 1 Interrupt is enabled 0 disabled Interrupt source are TC B2 TC B1 TC BO TC A2 TC A1 TC AO TC xy CONTROL This register selects the input clock and gate source for the 82C54 Timer Counters Note that the maximum input frequency to the Timer Counters is 10 MHz Also no provision is made in hardware to prevent a Timer Counter from using its own output clock as its input clock 15 13 12 8 H 4 3 0 GATE SEL 4 0 CLOCK SEL 3 0 Feld X Bescipion RTD Embedded Technologies Inc www rtd com 43 DMx820 User s Manual Accessing the Analog World Field A Bescipion GATE SEL 4 0 Selects the gate input to this channel of the Timer Counter Value definitions are Port2 15 Port2 0 Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe 1 Prog Clock 3 Prog Clock 2 Prog Clock 1 Prog Clock 0 82C54 TC B2 82C54 TC B1 82C54 TC BO 82C54 TC A2 82C54 TC A1 82C54 TC AO 7 o CLOCK SEL 3 0 Selects the clock input to this channel of the Timer Counter Value definitions are Inverted Strobe2 Inverted Strobe1 Strobe2 Strobe Prog Clock 3 Prog Clock 2 Prog C
91. ting possible 1 Start of counting 2 Retriggering 1 Counting not possible 2 Counter output forced to Hr level Start of counting Counting possible 1 Counting not possible 3 2 Counter output forced to Hr level Start of counting Counting possible 4 Counting not possible e Counting possible 1 Start of counting 2 Retriggering Mode 0 WR n 4 n 2 WR m9 14 9 5 4 o2 2 1 0 OUT GATE H J em WR mAl Mode 1 RTD Embedded Technologies Inc www rtd com 62 DMx820 User s Manual Accessing the Analog World JJ LI LELILILILIELIEUILLILILILIL WR n 4 n 2 4 3 2 1 4 3 2 1 2 1 2 OUT GATE H L L LJ Mode 2 nz4 n 3 4 OUT GATE D p fe 42 0 4 2 4 2 042 4 2 our M2 Mode 4 OUT GATE ap GATE L f OUT s m i i rn Mode 5 Note n is the value set in the counter Figures in these diagrams refer to counter values Reading Counter Values All MSM82C54 2 counting is down counting the counting being in steps of 2 in mode 3 Counter values can be read during counting by 1 direct reading 2 counter latching read on the fly and 3 read back command RTD Embedded Technologies Inc www rtd com 63 DMx820 User s Manual Accessing the Analog World Direct reading Counter values can be read by direct reading operations Since the counter value read according to the timing of the RD and CLK signals is not guarantee
92. yte LSB 10 Reading Loading of Most Significant Byte MSB Reading Loading of LSB followed by MSB Table 14 Mode M 2 0 Operation waveform mode setting bu Ee Value Value 001 x10 x11 100 Mode 4 Software Triggered Strobe 101 Mode 5 Hardware Triggered Strobe x denotes not specified Count value of 0 executed 0x10000 count Table 15 BCD Operation count mode setting Set Contents D Binary Count 16 bit Binary BCD Count 4 decade Binary Coded Decimal After setting Read Load Mode and BCD in each counter as outlined above next set the desired count value In some Modes the count value Is set first In next clock loading is performed and then counting starts This count value setting must conform to the Read Load format set in advance Note that the internal counters are reset to 0000H during control word setting The counter value 0000H can t be read The program sequence of the MSM82C54 2 is flexible Free sequence programming is possible as long as the two following rules are observed i Write the control word before writing the initial count value in each counter ii Write the initial count value according to the count value read write format specified by the control word Note Unlike the MSM82C53 2 the MSM82C54 2 allows count value setting for another counter between LSB and MSB settings RTD Embedded Technologies Inc www rtd com 99 DMx820 User s Manual Accessing the Analog

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