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HI5x60EVAL1 User Guide

1. Appendix D Schematic SMA1 EXT REF OPTIONAL VME CONNECTOR 96 PIN A30 LSB P1 30 C30 P1 94 A29 1 29 29 1 93 A28 P1 28 C28 P1 92 C27 P1 91 A26 P1 26 26 1 90 25 1 25 C25 P1 89 A24 P1 24 C24 P1 88 A23 MSB 1 23 02 14 R3 02 13 R31 00 12 R4 0Q 11 R32 0Q 10 R5 0Q 9 R33 0Q 8 R34 0Q 7 R6 00 6 R35 02 5 R7 00 4 R36 02 3 R8 0Q 2 R37 0Q 1 R9 0Q R38 NOTE ALL OTHER PINS ON THE 64 PIN VME CONNECTOR ARE DISCONNECTED ROW B WAS NOT USED NOTE 500 TERMINATION RESISTORS ARE NOT SHIPPED WITH BOARD R39 02 SMA6 CLK 14 502 616 4 113 500 R23 4 12 509 R15 3 11 500 R22 1 10 500 R14 g 500 R21 3 18 500 1 R13 3 1 Q 7 509 R20 3 16 500 R17 15 500 R10 14 500 R18 3 13 500 12 500 R12 3 11 502 R419 3 Ic 500 R30 4 NOTE JUMPERS SHOWN IN SHIPPED MODE J2 SLEEP IS UNINSTALLED E1 J1 EXTERNAL REFERENCE IS UNINSTALLED i J3 INTERNAL REFERENCE IS ENABLED 1 TP2 TM NOT NECESSARY DIGITAL ANALOG GROUND GROUND E2 PROTO AREA i 1 SMA5 1 a R29 1 02 1 m i a 2 NOTE BOARD IS RGND yw NOT SHIPPED WITH COREE POTENTIOMETER 1 2 14 5 1 12 Du o ig mz R28
2. 2d 500 SMA3 7109 00 Ti jour 1107 a 2 R24 1 1 U 6l 23 O 1uF O 24 Bie see i R26 2 18 26 SMA4 Rel 2 27 EE CLOCK 28 C5 R25 500 0 1uF R1 20kQ 3296W 1 R26 1009 0805 i R25 28 500 0805 i R10 23 30 500 1206 10uH es R3 9 24 27 29 31 39 00 0805 DVDD1 T1 1 1 TRANSFORMER 81 DVDD R2 2k 0805 9 7 1 10 Gaur PLANE 1 5 6 7 0 1UF 0805 C8 9 10UF CASE DIGITAL GROUND PLANE V7 I avoni Oe nag _ PCB MOUNT 1 64 PIN VME CONNECTOR E4 J1 3 1X2 HEADERS ACOM1 AVDD J2 1X3 HEADER ANALOG GROUND PLANE PLANE U1 HI5x601B NOTE EXTRA SMA5 AND PROTO ARE FOR OVERDRIVING COMP1 686 910N Application Note 9853 All Intersil semiconductor products are manufactured assembled and tested under 1509000 quality systems certification Intersil semiconductor products are sold by description only Intersil Corporation reserves the right to make changes in circuit design and or specifications at any time with out notice Accordingly the reader is cautioned to verify that data sheets are current before placing orders Information furnished by Intersil is believed to be accurate and reliable However no responsibility is assumed by Intersil or its subsidi
3. the bits from the data generator to the evaluation board preferably by using a male 64 or 96 pin VME Versa Module Eurocard connector that mates with the evaluation board Connect the clock source to the evaluation board also preferably through the VME connector Failure to make clean and short connections to the data input lines and clock source will result in a decrease in spectral performance Using a coaxial cable with the proper SMA connector attach the output of the converter I ur to the measurement equipment that will be evaluating the converter s performance Make sure that the jumpers are in their proper placement Consult the Voltage Reference section and the Sleep section of this document for a definition of the jumpers functionality HI5X60 EVALUATION BOARD HI5X60 DAC 5V SUPPLY FEMALE 64 PIN VME CONNECTOR SPECTRUM ANALYZER FIGURE 2 INTERSIL HI5x60 EVALUATION SYSTEM SETUP BLOCK DIAGRAM 3 3 intersil Application Note 9853 Appendix A Description of Architecture The segmented current source architecture has the ability to improve the converter s performance by reducing the amount of current that is switching at any one time In traditional architectures major transition points required the converter to switch on or off large amounts of current Ina traditional 10 bit R 2R ladder design for example the midscale transition required approximately equal amount
4. active high Connect to ground for normal mode Sleep pin has internal 20uA active pull down current 16 REFLO Connect to analog ground to enable internal 1 2V reference or connect to AVpp to disable internal reference 17 REFIO Reference voltage input if internal reference is disabled Reference voltage output if internal reference is enabled Use 0 1uF cap to ground unless overdriving with a waveform 18 FSADJ Full Scale Current Adjust Use a resistor to ground to adjust full scale output current Full scale output current louTFs 2 VEsADJ RSET maximum IOUTFS 20mA 19 COMP1 For use in reducing noise Recommended Connect 0 1uF from COMP1 to AVpp 20 25 ACOM Analog Ground 21 IOUTB The complementary current output of the device Full scale output current is achieved when all input bits are set to binary 0 22 IOUTA Current output of the device Full scale output current is achieved when all input bits are set to binary 1 23 COMP2 Connect to ACOM through a 0 1uF capacitor 24 AVpp Analog supply 3V to 5V 26 DCOM Digital ground 27 DVpp Digital supply 3V to 5V 28 CLK Input for clock Positive edge of clock latches data 3 4 intersil Application Note 9853 Appendix C Circuit Board Layout FIGURE 4 GROUND LAYER 3 VIEWED FROM BOTTOM 3 5 intersil Application Note 9853 Appendix C Circuit Board Layout continued FIGURE 6 TOP SIDE LAYER 1 VIEWED FROM BOTTOM 3 6 intersil
5. age is approximately 1 2 of the digital power supply voltage so reducing the power supply can make the DAC compatible to smaller levels The digital inputs data and clock cannot go 0 3V higher than the digital supply voltage else diode ESD protection can begin to turn on and performance could be degraded The clock source can be a sine wave with some degradation in performance The recommended clock is a square wave The timing between the clock and the data will affect spectral performance and functionality Minimum setup and hold times are specified in the datasheet to represent the point at which the DAC begins to lose bits Optimal setup and hold 3 2 intersil Application Note 9853 times vary with the clock rate to output frequency ratio A general rule is that the lower the Fc K Four ratio is the higher the setup time should be to achieve optimum spectral behavior Getting Started summary of the external supplies equipment and signal sources needed to operate the board is given below 1 5V to 3V supply for HI5x60 DAC 2 Pattern Generator 3 Square wave clock source usually part of the Pattern Generator 4 Spectrum Analyzer or Oscilloscope for viewing the output of the converter HP SMA TEST BOARD INTERSIL MADE HEWLETT PACKARD HP80000 PATTERN GENERATOR 2 2 gt Attach evaluation board to the power supply s Connect
6. aries for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries For information regarding Intersil Corporation and its products see web site www intersil com Sales Office Headquarters NORTH AMERICA EUROPE ASIA Intersil Corporation Intersil SA Intersil Ltd P O Box 883 Mail Stop 53 204 Mercure Center 8F 2 96 Sec 1 Chien kuo North Melbourne FL 32902 100 Rue de la Fusee Taipei Taiwan 104 TEL 321 724 7000 1130 Brussels Belgium Republic of China FAX 321 724 7240 TEL 32 2 724 2111 TEL 886 2 2515 8508 FAX 32 2 724 22 05 FAX 886 2 2515 8369 3 8 intersil
7. e Reference The HI5860 5960 has an internal 1 2V voltage reference with a 40ppm C drift coefficient over the industrial temperature range The REFLO pin 16 selects the reference Access to pin 16 is provided through the center pin of Jumper J3 This jumper is labeled INT and EXT for internal or external reference The REFIO pin 17 provides access to the internal voltage reference or can be overdriven if the user wishes to use an external source for the reference The internal reference was not designed to drive an external load Notice that a 0 1uF capacitor is placed as close as possible to the REFIO pin This capacitor is necessary for ensuring a noise free reference voltage If the user wishes to use an external reference voltage jumper J1 must be in place and an external voltage reference provided via SMA1 labeled EXT REF The recommended limits of the external reference are between 15mV and 1 2V Performance of the converter can be expected to decline as the reference voltage is reduced due to the reduction in LSB current size If the user wishes to amplitude modulate the DAC the REFIO pin can be overdriven with a waveform The input multiplying bandwidth of the REFIO input is approximately 1 4MHz when driving a 100mV signal into the REFIO pin biased at 0 6Vpc The BW reduces as this amplitude is increased It is necessary that the multiplying signal be DC offset so that the minimum and maximum peaks are positive and belo
8. even harmonic performance improvement due to the differential signaling 12 5Q Req loading to each output of the DAC drive impedance of 50Q for matching with a spectrum analyzer and 2x voltage gain The output of this configuration will be biased at zero volts and have an amplitude of 500mV Vout when the DAC is configured to drive IoyTFs of 20 HI5x60 Vout 2 x louTrs X REQ V 50Q PINA SPECTRUM PIN 22 5 IMPEDANCE FIGURE 1 Sleep The converter can be put into sleep mode by connecting pin 15 of the DAC to either of the converter s supply voltages The sleep pin has an active pulldown current so the pin can be left disconnected or be grounded for normal awake operation On the evaluation board jumper J2 is provided for controlling the sleep pin Remove the jumper from J2 for normal operation and replace it for sleep mode Power Supply s and Ground s The user can operate from either a single supply or from dual supplies The supplies can be at different voltages It is important to note that the digital inputs cannot switch more than 0 3V above the digital supply voltage The evaluation board contains two power supply connections analog AVDp1 and digital DVpp 7 each with their own ground wire Dual ground and power planes is the recommended configuration with the ground planes connected at a single point near the DAC Digital Inputs The DAC is designed to accept CMOS inputs The switching volt
9. intersil HI5x60EVAL1 User s Manual Application Note July 1999 AN9853 Description Features The HISx60EVAL1 evaluation board provides a quick and 125MSPS 12 or 14 Bit CMOS DAC easy method for evaluating the HI5860 5960 12 or 14 bit 125MSPS high speed DACs The board is configured so that Also Can Be Used to Evaluate the 8 and 10 Bit Versions the converter outputs differential current into a transformer Mi circuit to form an output voltage The amount of current out Transformer Coupled or Single Ended SMA Outputs of the DAC is determined by an external resistor and either ot e Easily Selectable Internal or External Reference an internal or external reference voltage The CMOS digital inputs have optional external termination resistors The Ordering Information evaluation board includes a VME digital interface that is compatible with all previous Intersil D A evaluation boards TEMP PART RANGE NUMBER CLOCK NUMBER C PACKAGE OF BITS SPEED HI5860SOICEVAL1 25 SOIC 12 125MHz HI5960SOICEVAL1 25 SOIC 14 125MHz Functional Block Diagram DCOM PLANE DVDD PLANE AVDD PLANE ACOM PLANE 14 BITS VME 64 OR 96 PIN B ROW NOT USED EXTERNAL REFERENCE OPTIONAL SMA1 3 1 1 888 INTERSIL or 321 724 7143 Intersil and Design is a trademark of Intersil Corporation Copyright Intersil Corporation 2000 Application Note 9853 Functional Descriptions Voltag
10. s of currents switching on and off In a segmented current source arrangement transitions such as midscale become one in which you simply have an additional intermediate current source turning on and several minor ones turning off In the case of the HI5760 there are 31 intermediate current segments that represent the 5 MSBs and five binary Appendix B Pin Descriptions weighted current sources representing each of the five LSBs See the Functional Block Diagram in the datasheet for a visual representation To relate the midscale transition example to the HI5760 consider the following The code 0111111111 would be represented by 15 intermediate current segments and each of the 5 LSB current sources all turned on To transition to code 1000000000 would simply require turning off the 5 LSB current sources and turning on the next intermediate current segment bringing the total amount of current switching at this major code transition equal to the same amount switching at 30 other code transition points in the code ramp from 0 to 1023 so that the total glitch energy is distributed more evenly PIN NO PIN NAME PIN DESCRIPTION 1 14 D13 MSB For the 14 bit HI5960 these are digital data bit 13 most significant bit through digital data bit 0 least significant Through DO LSB bit Pins 13 and 14 are NC for the 12 bit HI5860 15 SLEEP Control Pin for Power Down Mode Sleep mode is
11. w 1 2V For the external reference option Jumper J3 must be changed so that pin 16 of the DAC is tied to the supply voltage which is the EXT side of J3 The output current of the converter IOUTA and IOUTB is a function of the voltage reference used and the value of RsET R2 on the schematic Output Current The output current of the device is set by choosing RSET and Vesapy such that the resultant of the following equation is less than 20mA lout 32 x VFSADJ RSET REFIO PIN 17 and FSADJ PIN 18 of the DAC are the inputs to an operational amplifier The voltage at the FSADJ pin Vesapy will be approximately equal to the voltage at the REFIO pin which will either be the value of the internal or external reference For example using the internal reference of nominal 1 2V and an value of 1 91kQ results in an lout of approximately 20mA maximum allowed Choose the output loading so that the Output Voltage Compliance Range is not violated 0 3 to 1 25V If an external reference is chosen it should not exceed 1 2V The output can be configured to drive a load resistor a transformer an operational amplifier or any other type of output configuration so long as the output voltage compliance range and the maximum output current are not violated Transformer Output The evaluation board is configured with a transformer output configuration shown in Figure 1 This configuration was chosen because it provides

HI5x60EVAL1 User Guide

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