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ADAZI00 User`s Manual - RTD Embedded Technologies, Inc.

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1. 4 2 5 1 ADA2100 Board Layout eeeeeeeee eese e ee eren eene ener eee eene nante nean 5 1 iii 1 1 1 2 5 1 5 2 5 3 5 4 LIST TABLES Page ADA2100 Board Functions and 5 1 2 ADA2100 I O Map eere etin ree tnnt nennen 14 A D Converter Bit Weights eene enean eene nnne 5 3 A D Converter Readings for Gain 5 3 D A Converter Bit Weights Unipolar 54 D A Converter Bit Weights Bipolar 5 5 INTRODUCTION This manual shows you how to operate provides technical data for Real Time Devices ADA2100 12 bit high speed differential analog I O interface board This versatile interface allows your IBM PC XT AT or compatible computer to effectively operate in the real time environment of data acquisition and control to sense and generate both digital and analog signals Figure i 1 shows a typical laboratory setup using a PC for data collection LABORATORY WORKSTATION HARDWARE IBM PC or SOFTWARE Compatible Signal conditioning amp acquisition data reduction graphics analysis control data storage LABORATORY AUTOMATION Fig i 1 Typical Laboratory Setup The ADA2100
2. opa ie rene 0 5 typ 1 max Input options 10 volt range Option 1 Bipolar 5V Guaranteed linearity 5V 10 volt range Option 2 Unipolar 0 to 10V Guaranteed linearity 0 to 9 5V 20 volt range Option 3 Bipolar 10 V Guaranteed linearity 9 5 LT Jumper selectable Polarity Switch selectable Settling tie 3 usec max Common mode input voltage 10V Overvoltage protection 35 Vdc Erratic readings can occur beyond specified input voltage ranges Type A 98 406 80400000006000000 0900000600 6 6 Resolution 10 volt range 20 volt range Chip selectable conversion speed Option 0 Linearity Option 1 Option 2 9 680 004404 00600000640060 Sample and hold acquisition time Throughput SE ey Successive approximation 12 bits 2 44 mV bit 12 bits 4 88 mV bit 20 usec typ 25 usec max 12 usec typ 15 usec max 8 usec typ 9 usec 1 bit typ Three 16 bit 8 MHz down counters jumper selectable 16 TTL CMOS compatible 8 at I O connector amp 8 on board Analog Outputs eesessnssesnenennensenensanensa
3. 58 APPENDIX F tr reve eS ii LIST OF ILLUSTRATIONS Figure Page i 1 Typical Laboratory 8 2 2 2 2 4 0 4 0 1 1 1 1 ADA2100 Board 1 3 1 2 Base Address Header Connector 2 1 5 1 3 A D Conversion Word 1 0 4 0 0 0000 iene nen 1 10 2 1 ADA2100 Board Block 224 222 222 22 2 1 2 2 EOC Timing 2 2 3 1 ADA2100 Board 4 041 2 0 20004 1 110 3 1 3 2 pits seven teens este 3 2 3 3 PIT I O Header Connector ezio zeonerenioneo 3 3 3 4 PIT Functional Block Diagram 34 3 5 Interrupt Header Connector 5 3 5 3 6 Interrupt Header Connector P7 3 5 3 7 EOC Monitor Header Connector 6 3 5 3 8 A D Converter Voltage Range Header Connector P9 3 6 3 9 D A Converter Voltage Range Header Connector 10 3 6 4 1 PPI Mode 1 1 1 11 e en eere ean
4. 23124412 19 4 MODE 5 HARDWARE TRIGGERED STROBE RETRIGGERABLE OUT will initially be high Counting is triggered by a rising edge of GATE When the initial count has ex pired OUT will go low for one CLK pulse and then go high again After writing the Control Word and initial count the counter will not be loaded until the CLK pulse after a trigger This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until N 1 CLK pulses after a trigger A trigger results in the Counter being loaded with the initial count on the next CLK pulse The counting sequence is retriggerable OUT will not strobe low for N 1 CLK pulses after any trigger GATE has no effect on OUT If a new count is written during counting the current counting sequence will not be affected If a trigger occurs after the new count is written but before the current count expires the Counter will be loaded with the new count on the next CLK pulse and counting will continue from there CWs A 158 3 lefain Sse ales CWz1A LSB 3 i 3i2i olrelret s 4 231244 13 Figure 20 Mode 5 3 94 intel 82C54 Signal Low Status Or Going Rising Modes Low Disables Enables counting counting 1 1 Initiates counting 2 Resets output after next clock 1 Disables counting 2 Sets output immediately high Enables
5. If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between reading the first and second byte to another routine which also reads from that same Counter Otherwise an incorrect count will be read READ BACK COMMAND The third method uses the Read Back command This command allows the user to check the count value programmed Mode and current state of the OUT pin and Null Count flag of the selected coun ter s The command is written into the Control Word Reg ister and has the format shown in Figure 10 The command applies to the counters selected by set ting their corresponding bits D3 D2 D1 1 11 CS 0 RD 1 WA 0 D Ds D4 D D Di Do 1 count STATUS 2 1 o Ds 0 Latch count of selected counter s D4 O Latch status of selected counter s Da 1 Select counter 2 Do 1 Select counter 1 D4 1 Select counter 0 Do Reserved for future expansion must be 0 Figure 10 Read Back Command Format The read back command may be used to latch multi ple counter output latches OL by setting the COUNT bit D5 0 and selecting the desired coun ter s This single command is functionally equiva lent to several counter latch commands one for each counter latched Each counter s latched count is held until it is read or the counter is repro grammed That counter is automatically unlatched
6. Sample and Hold Circuitry A sample and hold S H amplifier is used between the gain control circuitry output and the A D input to ensure that dynamic analog signals are accurately digitized by the A D converter The 001 pF hold capacitor used in this circuit is apolystyrene type selected for its low dielectric absorption Its low value minimizes the acquisition time 6 microseconds typical and minimizes hold step voltage and droop The sample and hold time and rate are determined by the EOC signal generated by the A D converter and fed back into the S H circuit When the EOC signal is high logic 1 the amplifier samples the analog input when the EOC signal is low logic 0 the amplifier holds the input A D Converter The A D converter is a high speed 12 bit conversion IC which performs conversions in approximately 20 microseconds Eight bit conversions can also be performed when speed is more critical than resolution An eight bit conversion takes about 13 microseconds allowing rapid conversions of dynamic analog inputs The converter supports 10 or 20 volt analog input signals however it cannot support a 20 volt unipolar input range because its supply voltage in the ADA2100 application is only 12 volts The analog input voltage ranges supported by the ADA2100 are listed in the specifications in Appendix A Calibration circuitry is included for unipolar and bipolar calibration of the A D converter Calibration procedures are described in
7. 0 PORT STROBED OUTPUT PORT B STROBED INPUT 231256 17 Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 0 This functional configuration provides a means for com municating with a peripheral device or structure on a single 8 bit bus for both transmitting and receiving data bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions Used in Group A only e One 8 bit bi directional bus port Port A and a 5 bit control port Port C e Both inputs and outputs are latched e The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidirectional Bus 1 0 Control Signal Definition INTR interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data out to port A ACK Acknowledge A low on this input enables the tri state output buffer of Port A to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Flop Associated with Controlled by bit set reset of Input Operations STB Stro
8. 5 or 7 155 inp base_address 5 4 Read the most significant bit from base_address 4 or 6 msb inp base_address 4 5 Combine them into the 12 bit result by shifting the LSB four bits to the right The MSB must also be weighted correctly result msb 16 Isb 16 For a 12 bit conversion the A D data read is left justified in a 16 bit word with the least significant four bits equal to zero as shown in Figure 1 3 Because of this the two bytes of A D data read must be scaled to obtain a valid A D reading Once it is calculated the reading can be correlated to a voltage value by scaling it in the case of bipolar input ranges 5 or 10 volts and then multiplying by the appropriate bit weight as shown below Input Range Scale Factor Bit Weight 5 volts Subtract 2048 2 4414 mV 10 volts Subtract 2048 4 8828 mV 0 to 10 volts None 2 4414 mV MSB LSB D15 014 D13 D12 011 Dio D9 D8 D7 De DB DA D3 D D1 DO Fig 1 3 A D Conversion Word Format For example if the A D reading is 1024 and the input range used is 5 volts the analog input voltage is calculated as follows 1024 2048 bits 2 4414 mV bit 2 49999 volts For a 10 volt input range the voltage is calculated as follows 1024 2048 bits 4 8828 mV bit 4 99999 volts For a 0 to 10 volt input range no scaling is required and the voltage is calculated as follows 1024 bi
9. 200003 da gt O OO Om amn gt NOTE struction sequence is required Any programming sequence that follows the conventions above is ac ceptable A new initial count may be written to a Counter at any time without affecting the Counter s pro grammed Mode in any way Counting will be affected as described in the Mode definitions The new count must follow the programmed count format If a Counter is programmed to read write two byte counts the following precaution applies A program must not transfer control between writing the first and second byte to another routine which also writes into that same Counter Otherwise the Counter will be loaded with an incorrect count Control Word Counter 2 Control Word Counter 1 Control Word Counter 0 LSB of count Counter 2 MSB of count Counter 2 LSB of count Counter 1 MSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 gt Control Word Counter 1 Control Word Counter 0 LSB of count Counter 1 Control Word Counter 2 LSB of count Counter 0 MSB of count Counter 1 LSB of count Counter 2 MSB of count Counter 0 MSB of count Counter 2 2000203 2 In all four examples all counters are programmed to read write two byte counts These are only four of many possible programming sequences Figure 8 A Few Possible Programming Sequences Read
10. D Di Do M MODE M2 M1 MO Do To wes AA Medea i 9 ea e BCD o Binary Counter 16 bits 1 Binary Coded Decimal BCD Counter 4 Decades Figure 7 Control Word Format 3 87 intel 82 54 Write Operations The programming procedure for the 82C54 is very flexible Only two conventions need to be remem bered 1 For each Counter the Contro Word must be written before the initial count is written 2 The initial count must follow the count format specified in the Control Word least significant byte only most significant byte only or least sig nificant byte and then most significant byte Since the Control Word Register and the three Counters have separate addresses selected by the A1 Ag inputs and each Control Word specifies the Counter it applies to SCO SC1 bits no special in e Control Word Counter 0 LSB of count Counter 0 MSB of count Counter O Control Word Counter 1 LSB of count Counter 1 MSB of count Counter 1 Control Word Counter 2 LSB of count Counter 2 MSB of count Counter 2 2 O O 00 Control Word Counter 0 Counter Word Counter 1 Control Word Counter 2 LSB of count LSB of count Counter 1 LSB of count Counter 0 MSB of count Counter 0 MSB of count Counter 1 MSB of count Counter 2 Counter 2
11. counting Initiates counting 1 Disables counting Initiates Enables 2 Sets output counting counting immediately high Disables Enables counting counting Initiates counting Figure 21 Gate Pin Operations Summary i COUNT COUNT o 0 TATARA 1 0 is equival nt to 216 for binary counting and 104 for BCD counting Figure 22 Minimum and Maximum initial Counts Operation Common to All Modes Programming When a Control Word is written to a Counter all Control Logic is immediately reset and OUT goes to a known initial state no CLK pulses are required for this GATE The GATE input is always sampled on the rising edge of CLK in Modes 0 2 3 and 4 the GATE input is level sensitive and the logic level is sampled on the r sing edge of CLK Modes 1 2 3 and 5 the GATE input is rising edge sensitive in these Modes a rising edge of GATE trigger sets an edge sensi tive flip flop in the Counter This flip flop is then sam pled on the next rising edge of CLK the flip flop is reset immediately after it is sampled In this way a trigger will be detected no matter when it occurs a high logic level does not have to be maintained until the next rising edge of CLK Note that in Modes 2 and 3 the GATE input is both edge and level sensi tive In Modes 2 and 3 if a CLK source other than the system clock is used GATE should be pulsed immediately follo
12. Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one level by the internal bus hold devices see Figure 4 Note After the reset is removed the 82 55 can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in CMOS de signs During the execution of the system program any of the other modes may be selected by using a single output instruction This allows a single 82C55A to service a variety of peripheral devices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that their functional definition can be tailored to almost any I O structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group A could be programmed in Mode 1 to monitor a keyboard or tape reader on an interrupt driven basis pera 8 sjuvo POPC PAPA 8 1 0 PB PB CONTROL CONTROL PA OR 1 0 OR UO Ay fis c B et ME gt o 231256 5 Figure 5 Basic Mode Definitions and Bus Interface CONTROL WORD BOBBEB
13. Chapter 5 An 8 or 12 bit conversion is initiated by a write operation to the appropriate I O address Once a conversion is begun the conversion status can be monitored by reading the A D converter status STS signal which is output from the A D converter IC and inverted before being made available to other circuitry on the board as the end of convert EOC signal The EOC signal can be monitored by one of two digital input lines on the PPI PA7 or PC7 Note that if either line is selected as the EOC monitor a jumper must be installed for the selected line on P6 and that line must be configured as an input The EOC signal is factory set to be monitored through PA7 on P6 The EOC signal is low logic 0 during a conversion Figure 2 2 shows the EOC timing diagram Also the three state A D output buffers remain in a high impedance state and therefore data cannot be read While a conversion is in progress any transitions of the digital inputs which control the conversion will be ignored so that the conversion cannot be prematurely terminated or restarted Once the conversion is complete EOC is now high or logic 1 the A D data can be read in two bytes the MSB and the LSB in any order For a 12 bit conversion the data is left justified in a 16 bit word In the case of an eight bit conversion the data is completely contained in the eight bit MSB Refer to Chapter 1 Taking an A D Reading and the demo disk for more information about using t
14. Counter with the initial count on the next CLK pulse Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This allows the Counter to be synchronized by software also Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current half cycle of the square wave the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current half cycle Mode 3 is implemented as follows Even counts OUT is initially high The initial count is loaded on one CLK pulse and then is decremented by two on succeeding CLK pulses When the count expires OUT changes value and the Counter is re loaded with the initial count The above process is repeated indefinitely Odd counts OUT is initially high The initial count minus one an even number is loaded on one CLK pulse and then is decremented by two on succeed ing CLK pulses One CLK pulse affer the count ex pires OUT goes low and the Counter is reloaded with the initial count minus one Succeeding CLK pulses decrement the count by two When the count expires OUT goes high again and the Counter is reloaded with the initial count minus one The above process is repeated indefinitely
15. Operations It is often desirable to read the value of a Counter without disturbing the count in progress This is easi ly done in the 82C54 There are three possible methods for reading the counters a simple read operation the Counter 3 88 Latch Command and the Read Back Command Each is explained below The first method is to per form a simple read operation To read the Counter which is selected with the A1 AO inputs the CLK input of the selected Counter must be inhibited by using either the GATE input or external logic Other wise the count may be in the process of changing when it is read giving an undefined result intel 82C54 COUNTER LATCH COMMAND The second method uses the Counter Latch Com Like a Control Word this command is written to the Control Word Register which is selected when 4 Ag 11 Also like a Control Word the SCO SC1 bits select one of the three Counters but two other bits D5 and D4 distinguish this command from a Control Word Ay Ao 11 CS 0 RD 1 WR 0 D De Ds D4 D3 D Di Do sci sco o x X XJ X SC1 SCO specify counter to be latched SC1 SCO Counter Read Back Command D5 D4 00 designates Counter Latch Command X don t care NOTE Don t care bits X should be 0 to insure compatibility with future Intel products Figure 9 Counter Latching Command Format The selected Counter s output latch OL latches the count at
16. START GETTING YOUR ADA2100 RUNNING To get started using your ADA2100 interface board you must Select by jumper a base I O address which does not contend with any other peripheral device Install the board into your PC Connect a signal to one of the analog input channels Run the ADA2100 software Unless you have other requirements these steps are all that are necessary to use your ADA2100 board This chapter explains how to install your ADA2100 and use its basic functions You will learn how to Change the base I O address setting Install the board in your PC Initialize the board Select the analog input channel and gain Take an A D reading Generate analog outputs This chapter is designed to allow you to immediately start using the basic functions of your ADA2100 board for data collection applications This chapter does not explain how to control the more intricate board functions such as the programmable interval timer the digital I O configurations or interrupts nor does it explain how to change hardware controlled settings except for the base I O address The functions not covered in this chapter are described in Chapters 2 through 4 What Comes With Your ADA2100 The standard ADA2100 board package includes 1 ADA2100 6 1 2 inch 165mm interface board 1 ADA2100 demo disk 1 User s manual Additional items such as interface cables and SIGNAL MATH and ATLANTIS application software are av
17. STATED HEREIN ALL IMPLIED WARRANTIES INCLUDING IMPLIED WARRANTIES FOR MECHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE LIMITED TO THE DURATION OF THIS WARRANTY IN THE EVENT THE PRODUCT IS NOT FREE FROM DEFECTS AS WARRANTED ABOVE THE PURCHASER S SOLE REMEDY SHALL BE REPAIR OR REPLACEMENT AS PROVIDED ABOVE UNDER NO CIRCUMSTANCES WILL REAL TIME DEVICES BE LIABLE TO THE PURCHASER OR ANY USER FOR ANY DAMAGES INCLUDING ANY INCIDENTAL OR CONSEQUENTIAL DAM AGES EXPENSES LOST PROFITS LOST SAVINGS OR OTHER DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PRODUCT SOME STATES DO NOT ALLOW THE EXCLUSION OR LIMITATION OF INCIDENTAL OR CONSE QUENTIAL DAMAGES FOR CONSUMER PRODUCTS AND SOME STATES DO NOT ALLOW LIMITA TIONS ON HOW LONG AN IMPLIED WARRANTY LASTS SO THE ABOVE LIMITATIONS OR EXCLU SIONS MAY NOT APPLY TO YOU THIS WARRANTY GIVES YOU SPECIFIC LEGAL RIGHTS AND YOU MAY ALSO HAVE OTHER RIGHTS WHICH VARY FROM STATE TO STATE F 3 ADA2100 User Selected Options Base I O Address hex decimal IRQ Channel Selection A D EOC PIT OUTO PIT OUTI PIT 2 A D EOC PPI Bit Assignment A D EOC
18. So for odd counts 3 93 OUT will be high for N 1 2 counts and low for N 1 2 counts 231244 11 GATE transition should not occur one clock prior to termina count Figure 18 Mode 3 MODE 4 SOFTWARE TRIGGERED STROBE OUT will be initially high When the initial count ex pires OUT will go low for one CLK pulse and then go high again The counting sequence is triggered by writing the initial count GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not strobe low until 1 CLK pulses after the initial count is written If a new count is written during counting it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens intel 82054 1 Writing the first byte has no effect on counting 2 Writing the second byte allows the new count to be loaded on the next CLK pulse This allows the sequence to be retriggered by software OUT strobes low N 1 CLK pulses after the new count of N is written CW 18 58 3 0 10 0 0 FF aaa i s slel FE FD CW 16 158 3 CW ats 1583 58 2
19. analog input voltages supported by the A D converter Note that whenever the polarity is changed the A D converter circuitry should be calibrated as described in Chapter 5 The switch settings are clearly labeled on the board to eliminate errors when configuring S1 TYPE POL oOo em 1 4 S E DIFF Fig 3 2 DIP Switch 51 P2 Base O Address Header Connector Header connector P2 controls the 24 computer I O address locations used by the board The base I O address location is set by jumpering one of the eight positions on the P2 header connector The base I O address is factory set to 300 hex 768 decimal with the jumper installed across the pair of pins fifth from the left on the connector The base I O address setting is fully explained in Chapter 1 Base I O Address Setting and is not repeated here Note the importance of this setting with respect to the possibility of address contention with other devices in your computer Be sure to examine this possibility if you experience board failure when you first attempt to operate the board in your computer P3 Programmable Interval Timer PIT O Header Connector Header connector P3 shown in Figure 3 3 controls the programmable interval timer PIT The PIT contains three independent 16 bit timer counter circuits as described in Chapter 2 Each timer counter has three I O signals associated with it a clock a gate and an output P3 can be configured in a number of ways
20. board the analog input channel and gain selections taking an A D reading and controlling the D A converter are covered in Chapter 1 Digital I O control through the PPI and control of the programmable interval timer are more complex and are described in this chapter The demo disk which accompanies your ADA2100 contain examples in Turbo C Turbo Pascal and BASIC Nearly all modern MS DOS based PC languages have I O reference instructions These are the instructions to control the data transfers to and from the I O ports Consult your programming language reference to find these instructions for your favorite language Selecting an Analog Input Channel See this section in Chapter 1 Setting the Input Gai See this section in Chapter 1 Taki A D Readi See this section in Chapter 1 Controlling the D A Converter See this section in Chapter 1 P ing the P ble Peripheral Interf The programmable peripheral interface PPI has three eight bit parallel I O ports port A port B and port C which can be configured for a variety of applications The PPI has eight lines available at external 1 connector P8 and eight lines available on board for I O use the eight bits of port B PBO PB7 are used for channel selection and gain control and cannot be used for other functions The PPI ports can be operated in one of three modes The mode of operation and the signal direction of each port input or output are controlled by an eight bit control wor
21. features high resolution 12 bit analog to digital and digital to analog converters digital I O and timer counters that provide flexibility for many applications Its six layer construction including separate power and ground planes enhances board performance and low noise characteristics It plugs directly into any unused expansion slot in the computer All external I O including PC bus sourced power is connected through a 40 pin header connector accessible at the rear of the PC Several of the ADA2100 s functions can be readily adapted for your specific requirements Through programming and or jumper or switch settings made on the board you can Select the base I O address Choose four differential or eight single ended analog input channels Select the active channel Select the channel gain Select the analog input voltage range and polarity Select the analog output voltage range and polarity Control 16 TTL CMOS compatible digital I O lines Control three 16 bit 8 MHz timer counter circuits the programmable interval timer Monitor the A D conversion using the end of convert EOC signal Generate interrupt signals Many of these functions are set up at the factory based on typical data collection requirements and customer specifications when ordering Therefore you can successfully install and run the ADA2100 with minimal understanding about changing and controlling them On the other hand you may want to understand ev
22. function of this block is to manage all of the interna and external transfers of both Data and Control or Status words It accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Contro Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outputs a control word to the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the 82C55A Each of the Control blocks Group A and Group B accepts commands from the Read Write Control Logic receives control words from the internal data bus and issues the proper commands to its as sociated ports Contro Group A Port A and Port C upper C7 C4 Control Group B Port B and Port C lower C3 CO The control word register can be both written and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the contro word is read bit D7 will always be a logic 4 as this implies control word mode information Ports A B and C The 82C55A contains three 8 bit ports A B and C All can be configured in a wide variety of functional characteristics by the system software but each has its own special features or personality to further enhance the power and flexibi
23. jumper various signals generated by the ADA2100 circuitry to the PC s interrupt channels The interrupt channels available on the board are IRQ2 through IRQ7 Note that only one interrupt in the computer system can be connected to an interrupt channel at any given time Before attempting to use interrupts you should be familiar with the procedure for initializing the interrupt vectors and the PC s interrupt controller and setting up the interrupt handling routines These procedures are beyond the scope of this manual but must be understood to effectively use interrupts in you computer system Becareful to avoid contention when selecting the interrupt channels used both with the signals on the ADA2100 as well as with other devices within your computer To avoid contention use the table inside the back cover of this manual to record the interrupt channels you use with the ADA2100 board It is also very important to note that the ADA2100 interrupt sources are TTL totem pole push pull type outputs they are not open collector Therefore do not attempt to connect one of these interrupts to any other interrupt output The following paragraphs describe the interrupts available on your ADA2100 board P5 PIT Output Interrupts Header connector P5 shown in Figure 3 4 is used to jumper one of the three PIT outputs OUTO OUTI or OUT2 to one of the computer s interrupt channels IRQ2 through IRQ7 Two jumpers must be installed to connect a PIT output
24. low to high when the countdown is completed Mode 1 Re triggerable one shot A low level pulse triggered by the GT input is output on the OUT pin Mode 2 Rate generator Mode 3 Square wave generator Mode 4 Software triggered strobe Mode 5 Hardware triggered strobe re triggerable The timer counter count modes as well as the count type binary or BCD read write mode and counter timer selection mode are all part of the control word which is written to the PIT control register to initialize the circuit When the PC is powered up the timer counter circuits are not defined until the appropriate control words are written to the circuits to program them for operation Initialization is required only once after a power up reset occurs Detailed information about the PIT including the control word format is given in the data sheet in Appendix C The three timer counter circuits are independent However they can be cascaded for countdowns which are longer than one 16 bit field can support For example TCO s OUT signal can be connected to TC1 s CK signal and TC1 s OUT signal can be connected to TC2 s CK signal When configured this way the PIT can accommodate extremely long countdowns One of the three timer counter outputs TCO OUT TC1 OUT or TC2 OUT can also be used as a PC interrupt These signals are brought out to board header connector P5 where one and only one can be selected for connection to any one IRQ chann
25. on header connector P9 must be installed across the 10V pins If you are using the 10 to 10 volt range reposition the jumper on P9 across the 20V pins after you perform the calibration procedures below Two adjustments are necessary to calibrate the A D converter for bipolar voltage ranges one for offset and one for full scale To adjust the offset connect the voltage shown under the Offset heading in the table below to the channel 1 input of the multiplexer While continuously displaying 12 bit A D conversions adjust TR5 until the data flickers between the two values listed in the table under Offset Next connect the full scale voltage listed in the table to the channel 1 input and adjust TR6 until the data flickers between the two values in the table under Full Scale Bipolar Calibration 5 to 5 volts or 10 to 10 volts range Offset TRS Full Scale TR6 4 99878 volts 44 99634 volts 0000 0000 0001 1111 1111 1111 Table 5 1 provides a reference for the ideal input voltage for the A D converter for each bit weight in each voltage range This table shows the ideal full scale all ones value in the first line and decrements by one bit weight each line thereafter Note that these values are for 12 bit A D conversions and are not valid when using the converter to perform more rapid eight bit conversions Note that the voltage values in the table are in millivolts Table 5 1 A D Converter Bit Weights PA Idea
26. setting of 300 hex 768 decimal If you change this setting you must run the ADAINST program and reset the base address NOTE When using the ADAINST program you can enter the base address in decimal or hexadecimal notation When entering a hex value you must precede the number by a dollar sign for example 300 P3 8254 Timer Counter I O Configuration 8254 must be configured with the six jumpers placed between the pins as shown in Figure D 2 After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P3 header connector P5 amp P7 Interrupts XTAL ECO 45V EGO coo 600 XTAL EC1 45V EG1 coi coi CK2 XTAL 2 EG2 co2 2 119 OLNO OLD OND LINO 219 ZAO Fig D 2 8254 Timer Counter Jumpers P3 To select IRQ channels and interrupt sources for SIGNAL MATH you must install two jumpers on PS and one jumper on P7 First install a jumper on P5 OUT2 and a second jumper across the pair of PS pins for the IRQ channel you select Then install a jumper on the end of convert interrupt header P7 across the pins of your desired IRQ channel The IRQ selected on P7 must be different from the IRQ set on P5 Figure D 3 shows OUT2 jumpered to IRQ3 and EOC jumpered to IRQ4 P5 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 OUTO OUTI OUT2 P7 EOC IRQ NO ROO Fig D 3 Timer Counter Out amp En
27. the base I O address is factory set at 300 hex On the demo disk the base I O address is usually stored in the variable board Remember to use the correct base I O address in the demo disk programs or your own programs The demo disk explains how to change the base I O address in the programs The ADA2100 is initialized by simply writing a control byte to the PPI control register mapped at the I O location base address 3 hex The control byte must conform to this general form 1xxx x00x where x don t care This ensures that the eight I O lines making up port B of the which are used to control the multiplexer and gain circuitry are configured as outputs The don t care x positions control the direction of the remaining 16 digital I O lines available on the PPI These lines can be configured as inputs outputs or in other more complex configurations For example when the control byte bit pattern is 100000000 decimal 128 the ADA2100 is initialized as follows out base address 3 128 When this value is used to initialize the ADA2100 the eight port C lines will all be configured as outputs You can transfer data to these lines with the command out base_address 2 data If instead the decimal value 137 1000 1001 is used to initialize the ADA2100 the port C lines will be set up as inputs You can input data from port C with the command data inp base_address 2 Note that port A bit 7 PA7 is factory set t
28. the next CLK pulse When GATE goes high OUT will go high N CLK pulses later no CLK pulse is needed to load the Counter as this has already been done ele ele lll iio denise CW 10 18852 CW 10 L8B 3 LSB 2 GATE e E ERE nju 231244 8 The Following Conventions Apply To All Mode Timing Diagrams 1 Counters are programmed for binary not BCD counting and for Reading Writing least significant byte LSB only 2 The counter is always selected CS always low 3 CW stands for Control Word CW 10 means a contro word of 10 hex is written to the counter 4 LSB stands for Least Significant Byte of count 5 Numbers below diagrams are count values The lower number is the least significant byte The upper number is the most significant byte Since the counter is programmed to Read Write LSB only the most significant byte cannot be read N stands for an undefined count Vertical lines show transitions between count values Figure 15 Mode 0 intel 82 54 MODE 1 HARDWARE RETRIGGERABLE ONE SHOT OUT will be initially high OUT will go low on the CLK pulse following a trigger to begin the one shot pulse and will remain low until the Counter reaches zero OUT will then go high and remain high until the CLK pulse after the next trigger After writing the Control Word and initial count the Counter is armed A tri
29. the time the Counter Latch Command is received This count is held in the latch until it is read by the CPU or until the Counter is reprogrammed The count is then unlatched automatically and the OL returns to following the counting element CE This allows reading the contents of the Counters the fly without affecting counting in progress Multiple Counter Latch Commands may be used to latch more than one Counter Each latched Coun ter s OL holds its count until it is read Counter Latch Commands do not affect the programmed Mode of the Counter in any way If a Counter is latched and then some time later latched again before the count is read the second Counter Latch Command is ignored The count read will be the count at the time the first Counter Latch Command was issued With either method the count must be read accord ing to the programmed format specifically if the Counter is programmed for two byte counts two bytes must be read The two bytes do not have to be read one right after the other read or write or pro gramming operations of other Counters may be in serted between them Another feature of the 82C54 is that reads and writes of the same Counter may be interleaved for example if the Counter is programmed for two byte counts the following sequence is valid 71 Read least significant byte 2 Write new least significant byte 3 Read most significant byte 4 Write new most significant byte
30. to 150 C Supply Voltage 0 5 to 8 0V Operating Voltage 4V to 7V Voltage on any Input 2V to 6 5V Voltage on any Output GND 0 5V to Voc 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam age to the device This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the opera tional sections of this specification is not implied Ex posure to absolute maximum rating conditions for extended periods may affect device reliability Ta 0 C to 70 C 5V 10 GND OV TA 40 C to 85 C for Extended Temperture Parameter Vit Vin Input High Voltage VoL Output Low Voltage VoH he Input Leakage Current IDAR Darlington Drive Current IPHL Port Hold Low Leakage Current Port Hold Low Overdrive Current IPHLO IccsB Supply Current Standby NOTES 1 Pins Ay Ag CS WR RD Reset 2 Data Bus Ports B C 3 Outputs open 4 Limit output current to 4 0 mA Parameter mn Input Low voltage os os Be Output High Voltage 3 0 Vcc 0 4 loFL Output Float Leakage Current u i IPHH Port Hold High Leakage Current 350 Port Hold High Overdrive Current 4350 Voc Supply
31. to provide maximum versatility in applying this device to your particular application Each timer counter is factory set for XTAL clock input 5V gate input and COO output Figure 3 4 shows a functional block diagram of the PIT For ease in configuring this circuitry the header connector is partitioned into three functional groups TCO TC1 and TC2 which correspond to timer counter 0 timer counter 1 and timer counter 2 respectively These designations also correspond to the manufacturer s designations as shown on the data sheet included in Appendix C Starting from the top of P3 the first group of pins on the right side are labeled CKO GTO and OUTO the three I O signals for TCO The signals on the left side for TCO are labeled XTAL ECO 5V EGO COO and this signal has a bar over top of the signal name on the board as the inverse designation The groups of signals for and TC2 are identical to TCO except that each has a CK input on the left side of the header connector Note that each signal name on the right side of the connector CK GT and OUT spans a group of two or three pins Each group can have only one jumper installed at any time The following paragraphs describe how these signals be used in the PIT circuit An is used in place of 0 1 or 2 in the signal names whenever the application can be applied to any or all of the three timer counter circuits Counter Inputs XTAL This input to all t
32. to the specified port The OBF F F will be set by the rising edge of the WR input and reset by Input being low ACK Acknowledge Input A low on this input informs the 82C55A that the data from Port A or Port B has been accepted In essence a response from the peripheral device indicating that it has received the data output by the CPU INTR interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when ACK is a OBF is a one and INTE is a one It is reset by the falling edge of WR INTE A Controlled by bit set reset of PCs INTE B Controlled by bit set reset of 1 PORT CONTROL WORD D D Oy 0 0 D Dy BORO 9C s 1 INPUT 0 OUTPUT MODE 1 PORT B CONTROL WORD Dy Os 0 D 020 Do LX 231256 15 Figure 10 MODE 1 Output P ZAS tart 231256 16 Figure 11 MODE 1 Strobed Output 3 135 82C55A Combinations of MODE 1 Port A and Port B can be individually defined as input or output in Mode 1 to support a wide variety of strobed 1 0 applications CONTROL WORD D Dg D D D 0 Di Do BORO EDS 1 INPUT O OUTPUT WR eo PORT A STROBEO INPUT PORT STROBED OUTPUT CONTROL WORD D Dg D D Dz Dy D Dy BORO 1 INPUT D OUTPUT
33. toan interrupt channel First install a jumper horizontally across the pins of the PIT output selected Then install a second jumper across the pins of the interrupt channel selected Figure 3 5 shows jumpers installed so that OUT2 is connected to IRQ3 3 4 5 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 OUTO OUT1 OUT2 Fig 3 5 Interrupt Header Connector P5 P7 A D End of Convert EOC Interrupt Header connector P7 shown in Figure 3 6 is used to jumper the A D converter s end of convert EOC signal to one of the computer s interrupt channels IRQ2 through IRQ7 The EOC signal is connected to an IRQ channel by installing a single jumper horizontally across the pins of the IRQ channel selected Figure 3 5 shows the EOC signal connected to IRQ4 P7 IRQ EOC NO Fig 3 6 Interrupt Header Connector P7 As described above the A D converter end of convert EOC signal can be used to generate an interrupt If this signal is not used as an interrupt it can be used as a status monitor of the A D conversion process Header connector provides two lines through which the EOC can be monitored PPI PA7 or PC7 One of these two digital I O lines is selected for EOC monitoring by installing a jumper horizontally across the appropriate pair of pins The digital I O line selected PA7 must be configured as a mode 0 input see Chapter 4 Programming Your ADA2100 Figure 3 7 shows with a jumper ins
34. voltmeter to monitor the output voltage present between the appropriate P8 signal and ground pins Adjust the appropriate trimpot until the voltage equals the full scale voltage in Table 5 4 as measured by the voltmeter Table 5 4 lists the maximum D A bipolar output voltage for each bit weight in 12 bit conversion for 5 and 10 volt references Note that the voltage values in the table are in millivolts 5 4 Table 5 4 D A Converter Bit Weights Bipolar Ideal Output Voltage millivolts D A Bit Weight 10 Volts 4997 5 4095 full scale output 9995 1 2048 0000 0 0000 0 1024 2500 0 5000 0 512 3750 0 7500 0 256 4375 0 8750 0 128 4687 5 9375 0 64 4843 8 9687 5 32 4921 9 9843 8 4960 9 9921 9 4980 5 9960 9 4990 2 9980 5 4995 1 9990 2 4997 6 9995 1 5000 0 10000 0 APPENDIX A SPECIFICATIONS Typical at 25 C Interface Analog Input A D Converter Counter Timer Digital I O Lines D A Converter Analog Output ADA2100 SPECIFICATIONS IBM PC XT AT compatible Jumper selectable base address I O mapped Jumper selectable interrupts 4 differential or 8 single ended inputs switch selectable Input impedance each channel gt 10 megohms Gains software selectable 1 2 4 8 or 16 Gain eTfOE i
35. 0 C to 85 for Extended Temperature Symbol Parameter mn Max unte Testconditon Vu os vv 5 5 Via InputHighVottage 20 VWc os V Vor OwpttowVotaeg os V 244 ee EEE Fin mputoedCurem 20 Vn Vectoov Vout Vcc to 0 0V Voc Supply Current mA gt 8MHz 82C54 CikFreq 10MHz82C54 2 IccsB Vcc Suppiy Current Standby All Inputs Data Bus All Outputs Floating Iccse1 Vcc Supply Current Standby pA CLK Freq DC CS Vcc All Other Inputs Pins Vann Outputs Open Cw Input Capacitance 140 pr fe 1MPz I O Capacitance pF Unmeasured pins Cour Output Capacitano 20 pr rTetumedto GND A C CHARACTERISTICS TA 0 C to 70 C Voc 5V 10 GND 0V TA 40 C to 85 C for Extended Temperature BUS PARAMETERS Note 1 READ CYCLE parameter O wm max Min us Address Sine ssi ROL so steso iig o ma 7 Address Hold Time anert o 0 en RB Pusowiem aso __ 85 wo Data Detay tom AL tp Data Delay trom Adaress 20 18 te ROftoDwareang 5 90 5 6 tay CommandRecoverytime 20 145 NOTE 1 AC timings measured at 2 0V Vo 0 8V intel 82054 A C CHARACTERISTICS Continued WRITE CYC
36. 1 2 shows the base I O address header connector P2 with the jumper installed at the factory set location of 300 hex The jumper must be installed vertically across one of the eight pairs of pins on P2 The hexadecimal base I O address setting corresponding to each pair of pins from left to right is as follows 200 240 280 2C0 300 340 380 3 0 200 3CO P2 Fig 1 2 Base Address Connector P2 For example if the base address is changed to 280 hex then for the 24 operations listed in Table 1 2 BA equals 280 Thus to send the channel selection and gain data to port B of the PPI its address of BA 1 becomes 281 hex If the factory setting of 300 hex will cause contention in your system position the jumper to the desired base I O address setting Once you have set the base I O address make a note of its value on the table inside the back cover of this manual You will need to know this setting for use in your programs nstalling the ADA2100 in Your Com r Before installing the ADA2100 in your computer make sure that the base I O address has been properly selected and all the hardware settings have been configured to support your requirements This chapter explains how to control the base I O address Other hardware settings are set at the factory as listed in Table 1 1 and remain at their factory settings unless you change them The interrupts generated by your ADA2100 are disabled not connected when you receive your b
37. 10 0000 volts A full scale value all ones corresponds to the negative full scale output voltage 4 9976 volts or 9 9951 volts An algorithm for determining the bipolar output voltage is given by the following equation 1 12 Analog output voltage FS voltage D A value bit weight where FS voltage is the positive full scale voltage 5 or 10 volts D A value is the digital data converted by the D A converter Bit weight is either 2 44 mV or 4 88 mV The correlation of the D A data values to the output voltages is summarized below Analog Output D A Data 0 0000 0000 0000 0 5 0000 10 0000 1000 0000 0000 2 5000 5 0000 0 0 1111 1111 1111 4 9988 9 9976 4 9976 9 9951 1 13 CHAPTER 2 FUNCTIONAL DESCRIPTION This chapter describes the major functions of the ADA2100 interface board Figure 2 1 shows a block diagram of the board The functions discussed in the following sections are Analog to digital conversion circuitry Digital to analog conversion circuitry Programmable peripheral interface PPT Programmable interval timer PIT circuitry 8 ANALOG INPUTS 5V TO 10V 10V TO 10V 4 DIFF 8 SE GROUND Fig 2 1 ADA2100 Board Block Diagram to Digital rsi ircuitr One of the main functions of the ADA2100 interface board is to provide high speed analog to digital conversion capability for data acquisit
38. 2 Programmable Interval Timer PIT I O Header 3 2 PS and P7 Interrupt Header esee eese anth etn 34 PIF Output Interr pts 5u tete seen e un 3 4 P7 A D End of Convert EOC 44 4 0 0 00 3 5 End of Convert EOC Monitor Header Connector 1 1 4104 46 1000 P9 A D Converter Voltage Range Header 1 1 2 11 06 P10 D A Converter Voltage Range Header Connector eese CHAPTER 4 PROGRAMMING YOUR ADA2100 Selecting an Analog Input Channel eese esee seen seen nennen tentent nones nrbes Setting the Input Gain Taking an A D Reading Controlling the D A Converter m 44 4 444 0000000000000 0000000000000 00 eee erevsessosvoseececeosseseeoqoposesececcosorotsosooceovoveoceeseteosssoseecesssoccecccooao Programming the Programmable Peripheral Programming the Programmable Interval 1 eee eene eene enne Hardware Interrupts 44 4466
39. 31256 27 A C TESTING INPUT OUTPUT WAVEFORM 231256 29 231256 30 Testing inputs Are Driven At 2 4V For Logic 1 And 0 45 For A Logic 0 Timing Measurements Are Made At 2 0V For A Logic 1 And 0 8 For A Logic 0 VExT Is Set At Various Voltages During Testing To Guarantee The Specification C Includes Jig Capacitance 3 146 APPENDIX D CONFIGURING THE ADA2100 FOR SIGNAL MATH D 1 Jumper Settings When running SIGNAL MATH you have to change some of the ADA2100 s on board jumpers from their factory set positions Before using SIGNAL MATH on the ADA2100 board check the following jumpers P2 Base address P3 8254 timer counter I O configuration PS amp P7 Interrupts End of Convert Monitor The board layout is shown in Figure D 1 Uia C36 RI Utt C15 C14 A r Tr oe Pul odii eio n y Pa 19 bz p DD Tine eias Inc C18 n 05 O a P7 IRQ E RET g 7 7027 P6 CES Me TYPE POL 6 XTAL o PC7 gy ao DI DI a e Os ce 45V c SE x P EGO o 1 PS 417 8 y Uto XTAL IRO6 8 2 IRQS E IRQS 8 Yi EGI 2 IRQS 5 IRQ2 2 OUTO 3 OUT2 m 8 o EC2 014 9 45V o a El m pi CH 612 C10 Fig D 1 ADA2100 Board Layout P2 Base Address SIGNAL MATH assumes that the base address of your ADA2100 is the factory
40. 4280044400440664 6 A D End of Convert EOC 1 2 4 2 4 4 5 04 04090 siena PIT Interrupts CHAPTER 5 CALIBRATION PROCEDURES Required Equipment A D Calibration Unipolar Calibration Bipolar Calibration Gain Circuitry Calibration 444444 a 6 66 006000920000666 6 0 Berewsessv teoeeceececseseceseoveseeseseoceecvoeessscesceteeceoceceseooeeevosvevocceecceee wecetasseteseooeevuvesesceoveseceeecevveeeetesoveccososeveveveeececeecosevoscosesceveceeve Mhespssespssseoneveeetceeoeeeeceooseoeccoovsocesvtoscceceseceeceocetedonosececceceeoeecesesveceeccecoee De eresostossseseveoetevvovveceveosevereseveesreec eusesetseeeeoseceresooveveeeceescopsesesveceeceoccveec D A Calibration m Unipolar Calibration Gist nennen iia Bipolar Calibration me APPENDIX Specifications rire eee eni iii APPENDIX B Connector Pin APPENDIX C Component Data APPENDIX D Configuring the ADA2100 for SIGNAL MATH APPENDIX E Configuring the ADA2100 for
41. 44 7 Figure 6 82C54 System Interface OPERATIONAL DESCRIPTION General After power up the state of the 82C54 is undefined The Mode count value and output of all Counters are undefined How each Counter operates is determined when it is programmed Each Counter must be programmed before it can be used Unused counters need not be programmed i Control Word Format A 11 CS 0 RD 1 WR 0 D De 05 SC Select Counter Select Counter 0 Select Counter 1 Select Counter 2 Read Back Command See Read Operations Counter Latch Command see Read Operations Read Write least significant byte only Read Write most significant byte only 1 1 Read Write least significant byte first then most significant byte NOTE Don t care bits X should be 0 to insure compatibility with future Intel products D4 mo Programming the 82 54 Counters are programmed by writing Control Word and then an initial count The control word format is shown in Figure 7 All Control Words are written into the Control Word Register which is selected when Ay Ao 11 The Control Word itself specifies which Counter is being programmed By contrast initial counts are written into the Coun ters not the Control Word Register The Ay Ao in puts are used to select the Counter to be written into The format of the initial count is determined by the Control Word used
42. 54 and is a superset of the 8253 m Handles inputs from DC to 8 MHz 10 MHz for 82C54 2 Six programmable timer modes allow the 82C54 to be used as an event counter elapsed time indicator programmable one shot and in many other applications The 82C54 is fabricated on Intel s advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent HMOS product The 82C54 is available i in 24 pin DIP and 28 pin plastic leaded chip carrier PLCC packages ATA pns COUNTER BUFFER L JU TUTUTO OUT 1 OUTO GATEO GND NC OUT1GATE1 CLK1 231244 3 PLASTIC LEADED CHIP CARRIER CLK 2 GATE 2 REGISTER 231244 1 Figure 1 82C54 Block Diagram 231244 2 Diagrams are for pin reference only Package sizes are not to scale Figure 2 82C54 Pinout September 1959 3 83 Order Number 231244 005 intel 82054 Table 1 Pin Description PLCC connected to system data bus 1 1 GND 1 1 o I Gate 0 Gate input of Counter O GND Ground Power supply connection O Outt OutputotCountert 8 MG MED o BUE 8 0 1 2 3 15 Out 2 Output of Counter 2 Clock 2 Clock input of Counter 2 Address Used to select one of the three Counters or the Contro Word Register for read or write operations Normally connected to the system address bus Counter 0 Counter 1 Cou
43. ADA2100 User s Manual 17227 1509001 AS9100 Certified Real Time Devices Inc Accessing the Analog World ADA2100 User s Manual 17227 REAL TIME DEVICES INC 820 North University Drive Post Office Box 906 State College Pennsylvania 16804 Phone 814 234 8087 FAX 814 234 5218 Published by Real Time Devices Inc 820 N University Dr Box 906 State College PA 16804 Copyright 1992 by Real Time Devices Inc rights reserved Printed in U S A Rev B 9234 TABLE OF CONTENTS Page INTRODUCTION How to Use This inn 1 2 When You A sense cenare i 2 CHAPTER 1 QUICK START GETTING YOUR ADA2100 RUNNING What Comes With Your 2100 000 666 nana a nennen tren ener 1 1 The Hardware anscheinend nein weiten 1 1 Functions You Set sm t entr ette ct er HN EY Nee 1 1 Setting the Base I O 1 1 aa nao ee eee ee etna aea is 1 3 Installing the ADA2100 in Your eene nnne ennt nnne tense nnns 1 5 TNE SOftWAIE tes ua ee uod eee Parona 1 5 Demo DISK qr m 1 6 Backing Up Your Disk nn en FANTERIA oae SN 1 6 Initializing Your 2100 4000 eci cenere narici nisa iio 1 6 Selecting an Analog Input Channel uessse
44. AINS AIN4 16 GND 17 GND 18 GND 19 AOUTI 20 GND 21 AOUT2 22 GND 23 GND 24 GND 25 PC7 26 PC6 27 PCS 28 PC4 29 PC3 30 PC2 31 PCI 32 PCO 33 EXTCLK 34 GND 35 EXTGATE 36 CLKOUT 37 12 VOLTS 38 5 VOLTS 39 12 VOLTS 40 GND ADA2100 P8 Connector Mating Connector Fujitsu FCN 705Q040 AU M FCN 707B040 AU B 3M 3417 7040 Robinson Nugent IDS C40PK C SR TG MIL C 83503 83503 7 09 P8 Mating Connector 1 B 2 APPENDIX C COMPONENT DATA SHEETS Intel 82C54 Programmable Interval Timer Data Sheet Reprint intel 82C54 CHMOS PROGRAMMABLE INTERVAL TIMER m Compatible with all intel and most m Three independent 16 bit counters other microprocessors m Low Power CHMOS m High Speed Zero Wait State 10 mA 2 8 MHz Count Operation with 8 MHz 8086 88 and frequency 80186 188 Completely TTL Compatible Six Programmable Counter Modes m Available in EXPRESS Binary or BCD counting Standard Temperature Range Status Read Back Command Extended Temperature Range m Available in 24 Pin DIP and 28 Pin PLCC The Intel 82C54 is a high performance CHMOS version of the industry standard 8254 counter timer which is designed to solve the timing contro problems common in microcomputer system design It provides three independent 16 bit counters each capable of handling clock inputs up to 10 MHz All modes are software programmable The 82C54 is pin compatible with the HMOS 82
45. Address ATLANTIS assumes that the base address of your ADA2100 is the factory setting of 300 hex see Chapter 1 If you changed this setting you must run the ATINST program and reset the base address NOTE The ATINST program requires the base address to be entered in decimal notation E 3 P3 8254 Timer Counter I O Configuration The 8254 must be configured with the six jumpers placed between the pins as shown in Figure E 2 After setting the jumpers verify that each is in the proper location Any remaining jumpers must be removed from the P3 header connector x 3 gt E 1 119 M9 DINO OLD 049 4 a lt LINO lt 219 CHO P3 Fig E 2 8254 Timer Counter Jumpers P3 P5 amp P7 Interrupts To select an IRQ channel and an interrupt source for ATLANTIS you must install two jumpers on P5 the timer counter output interrupt header Jumpers must be installed across the OUT2 pins and across the pins of your desired IRQ channel Figure E 3 shows OUT2 jumpered to IRQ3 Make sure that no jumpers are installed across the IRQ pins on header connector P7 P5 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 OUTO OUT1 OUT2 Fig E 3 End of Convert Interrupt Jumper P7 P6 End of Convert Monitor When running ATLANTIS place a jumper between EOC and PA7 as shown in Figure E 4 P6 PA7 Fig E 4 End of Convert Monitor Jumper P6 E 4 AP
46. BE GROUPB PORT C LOWER MODE SELECTION 0 MODE 1 MODE 1 PORT C UPPER 15 INPUT O OUTPUT 2g z MODE SET FLAG 1 ACTIVE 231256 6 Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but after a cursory review of the complete device operation a simple logical 1 O approach will surface The design of the 82C55A has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Reset using a single OUTput instruction This feature re duces software requirements in Control based appli cations When Port C is being used as status control for Port A or B these bits can be set or reset by using the Bit Set Reset operation just as if they were data output ports 3 128 BIT SEY RESET 1 BIT SELECT 01112 3 4 516 7 BIT SET RESET FLAG 0 231256 7 Figure 7 Bit Set Reset Format 82C55A interrupt Control Functions When the 82C55A is programmed to operate in mode 1 or mode 2 control signals are provided that can be used as interrupt request inputs to the CPU The interrupt request signals generated fro
47. Current Test Conditions V 2 5 mA V 100 pA t1 Vin Voc to OV Note 1 10 Vin Voc to OV Note 2 A Ports A B C Rext 5000 A Vout 1 0V Port only Vout 3 0V Ports A B C pA Vout 0 8V pA Vout 3 0V mA Note 3 10 pA Voc 5 5V Vin Voc or GND Port Conditions If I P Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High pe m 3 141 intel 82C55A CAPACITANCE TA 25 C Voc GND OV Symbol Parameter Min Units Conditions Input Capacitance 10 pF Unmeasuredpis fc 1 2 5 NOTE 5 Sampled not 100 tested A C CHARACTERISTICS TA 0 to 70 C Voc 5V 10 GND OV TA 40 C to 85 C for Extended Temperature BUS PARAMETERS READ CYCLE han RB Puce wath mo Bata Dolaytom FB WRITE CYCLE me Address Stable Sete WAI 0 A ae ww T p Test Conditions Ports A 8 B Ports A amp B taw twa WE Pulse width Data Setup Time Before WR T two pers Data Hold Time After WR 3 142 intel 82C55A OTHER TIMINGS Units Conditions il twg WR 1 to Output te Peripheral Data Before R tua Peripheral Data After R Parameter 82C55A 2 ACK Pu
48. For unipolar operation remove the X D A Parameters Six D A board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity Resolution and number of channels are fixed For the ADA2100 DMA is not used and should be left blank Gain and loss are provided so that you can make adjustments for external gain or loss as described above for the A D parameters For a bipolar output range an X should be placed before Bipolar on the screen default setting For unipolar operation remove the X APPENDIX E CONFIGURING THE ADA2100 FOR ATLANTIS E 1 Jumper Settings When running ATLANTIS you have to change some of the ADA2100 s on board jumpers from their factory set positions Before using ATLANTIS on the ADA2100 board check the following jumpers P2 Base address P3 8254 timer counter I O configuration e PS amp P7 Interrupts P6 End of Convert Monitor The board layout is shown in Figure E 1 e 00 MA 07 3 Ts ea ml noe 2 IRO4 EN 8 Yi IRQS pa iRQe con OUTO our OUT meer C36 At R2 Utt fis TRH TRIO TRS TRA TRES P 2 2 2 ILA ADNE 00 3 5 AOUT AOUT2 q 42 BIT TA DIFFERENTIAL C19 o E OARD 62 23 Time Devices Inc aL C18 R15 R21 o LLLI id va Poole 2 POL Fig E 1 ADA2100 Board Layout P2 Base
49. K pulses after the trigger Thus the GATE input can be used to synchronize the Counter After writing a Control Word and initial count the Counter will be loaded on the next CLK pulse OUT goes low CLK Pulses after the initial count is writ ten This allows the Counter to be synchronized by software also CW 14 15643 CWz14 158 4 GATE transition should not occur one clock prior to terminal count Figure 17 Mode 2 intel 82 54 Writing a new count while counting does not affect the current counting sequence If a trigger is re ceived after writing a new count but before the end of the current period the Counter will be loaded with the new count on the next CLK pulse and counting will continue from the new count Otherwise the new count will be loaded at the end of the current counting cycle In mode 2 a COUNT of 1 is illegal MODE 3 SQUARE WAVE MODE Mode 3 is typically used for Baud rate generation Mode 3 is similar to Mode 2 except for the duty cycle of OUT OUT will initially be high When half the ini tial count has expired OUT goes low for the remain der of the count Mode 3 is periodic the sequence above is repeated indefinitely An initial count of N results in a square wave with a period of N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low while OUT is low OUT is set high immediately no CLK pulse is required A trigger reloads the
50. LE tow two tav Min Max EE CERE DEREN ENIM EGENT BE NS Ss OA 165 A a 100 30 3 5013 pn i Gate width High so i Gate Wiathtow tes Gate Setup Tine io GLK 9 Too OwmtDeayWomQK os Output Delay tom Gae wc GLK Delay for Loading 0 Gate Delay for Sampling 5 a 50 2 100 00 _ OUT Delay from Mode Write lt CLK Set Up for Count Latch NOTES 2 In Modes 1 and 5 triggers are sampled on each rising clock edge A second trigger within 120 ns 70 ns for the 82C54 2 of the rising clock edge may not be detected 3 Low going glitches that violate tpwH tpw may cause errors requiring counter reprogramming 4 Except for Extended Temp See Extended Temp A C Characteristics below 5 Sampled not 10096 tested TA 25 C 6 lf CLK present at min then Count equals N 2 CLK pulses Two max equals Count N 1 CLK pulse min to Twc max count will be either N 1 or N 2 CLK pulses 7 In Modes 1 and 5 if GATE is present when writing a new Count value at min Counter will not be triggered at Twa max Counter will be triggered 8 If CLK present when writing a Counter Latch or ReadBack Command at Tc min CLK will be reflected in count value latched at max CLK will not be reflected in the count value latched Writing a Counter Latch or ReadBack Command between Tc min an
51. NP BASE_ADDRESS 1 130 STATUS STATUS AND amp HOF 140 IF GAIN 1 GOTO 160 150 STATUS STATUS OR GAIN 8 160 OUT BASE_ADDRESS 1 STATUS Taki A D Readi After you have selected an analog input channel and set the gain you can take an A D reading It is important to note that once the gain and channel are set they stay at those settings until you change them that is they are latched You do not have to set the gain or channel every time you take a reading Each time an A D conversion is completed an end of convert EOC signal is generated to signify the end of the conversion This signal can be used in a number of ways One way is to use this line to monitor the A D conversion status Setting up the EOC signal to be monitored involves configuring bit 7 of PPI port A orport C as an input line and connecting the EOC signal to it This procedure is detailed in Chapter 3 Jumper Settings EOC signal is factory set to be monitored through PA7 on header connector P6 The general algorithm for taking an A D reading is 1 Start 12 bit conversion by writing to base address 4 or 6 out base 5 4 0 Note that the value you send is not important The act of writing to this I O location is the key to starting a conversion 2 Delay at least 20 microseconds or monitor Port A or C bit 7 for a transition Polling permits the fastest data acquisition 3 Read the least significant bit from base address
52. OUTPUT PORT A 1 INPUT 0 OUTPUT MODE SELECTION 00 MODE 0 01 MODE 1 1X MODE 2 MODE SET FLAG 1 Fig 4 1 PPI Mode Definition Format P ing the P ble In Ti The programmable interval timer PIT can be configured for a variety of timing and counting functions The PIT s versatility is supplemented by the use of header connector P3 for jumpering various I O options Chapter 3 Jumper Settings describes this connector The PIT consists of three independent 16 bit down counters The counters are initialized for operation in any of six modes by writing data to the appropriate control word for each counter Counter data is then written to or read from each of the counters by accessing three additional internal registers The data is set up in a two byte format each byte accessible on the data bus Your specific requirements will determine how the individual timer counters should be configured The data sheet included in Appendix C provides the information required to control the PIT The software included on the demo disk shows example programs for controlling some of the PIT operating modes In addition some typical applications are presented in the programmable interval timer application notes in Appendix D Included are examples requiring two or more counters to be cascaded The signals generated by the OUT pins for any of the counters may be connected to one of the PC s interrupt channels using jumpers inst
53. PENDIX F WARRANTY F 1 LIMITED WARRANTY Real Time Devices Inc warrants the hardware and software products it manufactures and produces to be free from defects in materials and workmanship for one year following the date of shipment from REAL TIME DE VICES This warranty is limited to the original purchaser of product and is not transferable During the one year warranty period REAL TIME DEVICES will repair or replace at its option any defective products or parts at no additional charge provided that the product is returned shipping prepaid to REAL TIME DEVICES replaced parts and products become the property of REAL TIME DEVICES Before returning any product for repair customers are required to contact the factory for an RMA number THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY PRODUCTS WHICH HAVE BEEN DAM AGED AS RESULT OF ACCIDENT MISUSE ABUSE such as use of incorrect input voltages improper or insufficient ventilation failure to follow the operating instructions that are provided by REAL TIME DEVICES acts of God or other contingencies beyond the control of REAL TIME DEVICES OR AS A RESULT OF SERVICE OR MODIFICATION BY ANYONE OTHER THAN REAL TIME DEVICES EXCEPT AS EX PRESSLY SET FORTH ABOVE NO OTHER WARRANTIES ARE EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE AND REAL TIME DEVICES EXPRESSLY DISCLAIMS ALL WARRANTIES NOT
54. PORT B PINS 0 7 An 8 bit data output latch buffer and an 8 24 28 bit data input buffer __ SYSTEM POWER 5V Power Supply 27 34 I O DATA BUS Bi directional tri state data bus lines connected to system data bus RESET A high on this input clears the control register and all ports are set to the input mode 40 WRITE CONTROL This input is low during CPU write operations 37 40 41 44 PORT A PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input latch NC 1 12 No Connect 23 34 3 125 218 jo 20 m WR 79 gt 3 gt intel 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems Its function is that of a general purpose 1 component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to inter face the 82C55A to the system data bus Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The
55. RM and CR for Count Register Both are normally referred to as one unit called just CR When a new count is written to the Counter the count is 82C54 stored in the CR and later transferred to the CE The Control Logic allows one register at a time to be loaded from the internal bus Both bytes are trans ferred to the CE simultaneously CR and CR cleared when the Counter is programmed in this way if the Counter has been programmed for one byte counts either most significant byte only or least significant byte only the other byte will be zero Note that the CE cannot be written into whenever a count is written it is written into the CR The Control Logic is also shown in the diagram CLK n GATE n and OUT n are all connected to the out side world through the Control Logic 82C54 SYSTEM INTERFACE The 82C54 is treated by the systems software as an array of peripheral 1 ports three are counters and the fourth is a control register for MODE program ming Basically the select inputs Ap A4 connect to the Ag A4 address bus signals of the CPU The CS can be derived directly from the address bus using a linear select method Or it can be connected to the output of a decoder such as an Intel 8205 for larger sys tems ADDRESS BUS 16 CONTROL BUS o Jede 0 07 RO WR 82054 A CS COUNTER COUNTER 0 1 o ora OUT GATE CLK OUT GATE CLK COUNTER 2 pere OUT GATE CLK 2312
56. UT 13 OUTPUT INPUT 1 INPUT INPUT INPUT OUTPUT INPUT INPUT INPUT INPUT MODE 0 Configurations CONTROL WORD 0 CONTROL WORD 2 0 0 0 5 0 0 D 0 0 0 D CONTROL WORD 1 CONTROL WORD 0 0 0 D 9 D D 0 0 D 0 0 D DI 231256 10 3 131 MODE 0 Configurations Continued CONTROL WORD 4 Dg Ds D 0 D D Dy CONTROL WORD 95 0 De 0 D D D D Do CONTROL WORD 6 0 O 0 0 Do Ds CONTROL WORD 7 Ds Ds D D D 82 55 3 132 CONTROL WORD 8 D D D Ds Ds 0 Di CONTROL WORD 09 D De Ds D D D D CONTROL WORD 10 D 0 D 0 5 Ds 0 D CONTROL WORD 811 0 0 0 0 0 PCy PC PEPE PB PB 231256 11 inte 82C55A MODE 0 Configurations Continued CONTROL WORD 12 CONTROL WORD 414 0 9 9 0 D 0 D Dy D D 0 0 Og CONTROL WORD 13 CONTROL WORD 15 Dy 0 0 0 Di 0 D 0 0 0 0 0 0 D D PAPA Pesto 231256 12 Mode 1 Basic functional Definitions Two Groups Group A and Group B MODE 1 Strobed Input Output This functional Each group contains one 8 bit data port and one configuration provides a means for transferring 1 4 bit control data port data to or from a specified port in conjunction with strobes or handshaking signals mode 1 Port The 8 bit data port can be either input or output Operat
57. ailable for this board and are included on an as ordered basis signals on your board are made easily accessible with Real Time Devices XB40 I O extender board and XC40 expansion cable The extender board has two 20 pin terminal strips anda prototype area to support any special circuitry you may require to condition the signals For example if you are prototyping solid state relays or optoisolators this can easily be done with an XB40 The expansion cable terminates in a 40 pin wire wrap header connector suitable for installation in standard 0 1 inch spacing perf board material available from most electronic distributors Real Time Devices also offers XC40 standard flat ribbon cable and TW40 twisted pair flat ribbon cable for increased noise immunity The TW40 cable is excellent for connecting the differential pair analog input signals to the ADA2100 Contact Real Time Devices for additional information about these accessories The Hardware The ADA2100 interface board is shown in Figure 1 1 A complete listing of the board specifications is contained Appendix A The ADA2100 has several features which are user controlled through hardware or software Most of the hardware controllable features are jumper controlled the remaining are switch controlled of the board components are mounted a 6 1 2 inch printed circuit board which fits in any unused full size expansion slot in an PC XT AT or compatible computer 40 pin
58. al Timer PI The programmable interval timer PIT can be configured for a variety of timing and counting functions This versatile IC contains three independently clocked 16 bit timer counter circuits TCO TC1 and TC2 which operate as down counters These down counters can resolve time increments down to 125 nanoseconds This circuit s most common application is to provide accurate time delays under software control Upon command the PIT can count out a programmed delay and interrupt the PC when it has finished its tasks Any one of the three counters can be brought out to the I O connector the other two remain available at an on board header The three 16 bit timer counters are each loaded by two one byte write operations to the appropriate I O location The bytesare latched intoa 16 bit internal count register where they are stored until the count sequence starts The countdown starts when the count register contents are transferred in parallel to the down counter The timer counter circuits can be programmed for binary or BCD countdowns A 5 MHz crystal oscillator on the ADA2100 can be used to clock any timer counter circuit Or the timer counter can beclocked by a source external to the board through external I O connector P8 Rates of dc to 8 MHz can be used to clock the timer counters Each timer counter can be configured for one of six modes of operation These modes are Mode 0 Interrupt on end of count The OUT signal changes from
59. alled at connector P5 Refer to the Hardware Interrupts section below for more information on using the OUT signals to generate interrupts Hardware Interrupts Two jumper connectors labeled P5 and P7 are provided on the ADA2100 to enable interrupts generated by the A D converter and the PIT to the PC s interrupt channels IRQ2 through IRQ7 Chapter 3 Jumper Settings explains how these header connectors can be configured Before you attempt to use interrupts be sure you are familiar with the procedure for initializing the interrupt vectors and the PC s interrupt controller and setting up the interrupt handling routines Reference 1 in Appendix E provides a good description of the PC s system interrupts A D Converter End of Convert EOC Signal The A D converter EOC signal can be used to generate an interrupt to the PC An interrupt will occur through the selected interrupt channel to indicate a conversion is complete approximately 20 microseconds after the conversion is initiated The EOC signal is inverted before being applied to the interrupt channel It makes a low to high transition at the completion of each conversion cycle and remains high until another conversion is initiated The timing of the EOC signal is shown in Figure 2 2 Chapter 2 PIT Interrupts One of the OUTO OUTI or OUT2 signals generated by the PIT can be jumpered to a PC interrupt channel using connector P5 When using a PIT OUT signal as an interru
60. be Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of PC4 3 136 intel 82C55A CONTROL WORD D D Ds D D D D PCza 4 INPUT 0 OUTPUT PORT 1 INPUT 0 OUTPUT GROUP MODE 0 MODEO 1 MODE 1 231256 18 Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 PERIPHERAL us 231256 20 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WR occurs before ACK and STB occurs before RD is permissible INTR IBF e MASK STB e RD OBF e MASK WR O A 3 137 ntel 82 55 MODE 2 AND MODE 0 INPUT MODE 2 AND MODE 0 OUTPUT CONTROL WORD CONTROL WORD 0 D Dg D Dz 0 D Do D D 05 D D3 0 D Do e fo Io rc 20 I INPUT MODE 2 AND MODE 1 OUTPUT MODE 2 AND MODE 1 INPUT CONTROL WORD CONTROL WORD D D Dg D O D D D D D D D D Do DS 231256 21 Figure 16 MODE Y Combinations 3 138 Mode Definition Summary Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the Port C lines are used for control or status The remaining bits are either inputs or outputs as
61. cally across either the unipolar pins or the bipolar pins for the corresponding channel Note that each channel must have one jumper installed in order to function properly The outputs are factory setto match the specified A D input polarity If you reconfigure the board for a different output range than that specified when the board was ordered then you must recalibrate the D A converter for the new range according to the instructions in Chapter 5 AOUT1 AOUT2 D T Fig 3 9 D A Converter Voltage Range Header Connector P10 4 PROGRAMMING YOUR ADA2100 All communication with the ADA2100 interface board is done by strobing data to and from the board using the I O reference instructions Most operations involve the transfer of data to or from the components internal registers However some operations require only that a particular I O address be written to the data written is irrelevant These T O locations are referenced to the ADA2100 base I O address BA determined by the jumper setting of connector P2 Chapter 1 describes the base I O address considerations and configuration The data collection and support functions controlled through software include the analog input channel selection and gain control of the the A D and D A conversions the programmable peripheral interface PPI and the programmable interval timer Because they are integral to the basic operation of the
62. ce 0 to 10 volts Digital Voltmeter 5 1 2 digit 4 Jumper Wire Small Screwdriver for trimpot adjustment Figure 5 1 shows the board layout The trimpots referenced in the following procedures are grouped in the upper left area of the board 00000008000 ADA2100 8 a y m Bu x 8 Ue DIFFERENTIAL Med ine te C18 Bax mmn c P7 IRQ R21 a d Py T XTAL w Co pm ths SI D ric eo 3 PS 417 Su ROB es 10 pi CH Fig 5 1 ADA2100 Board Layout A D Calibrati During this procedure connections must be made to some of the analog inputs on external I O connector P8 available at the rear panel of the computer The pin assignments for this connector are given in Appendix B Two adjustments are necessary to completely calibrate the A D converter for unipolar or bipolar operation These affect the offset and full scale performanceof the ADA2100 circuitry Both calibration steps are performed using trimpots TR5 and TR6 or TR6 and TR7 Trimpot TR5 or TR7 is used to zero the offset error of the A D converter and trimpot TR6 5 1 is used for full scale adjustment In the following procedure use analog input channel 1 and set it for gain of 1 This is accomplished by writing all zeroes to I O address location BA 4 1 Be certain that position 4 of switch S1 is set for the desired polarity and the jumper on connector P9 is set for 10V Un
63. channel to 8 Recall that the board s default channel setting is four differential channels Therefore only the channel select binary values for channels 1 through 4 apply Channels 5 through 8 are used in the single ended channel mode only Now your board is initialized and ready to operate The following sections describe how to select the analog inputchannel set the input gain take an A D reading and control the D A converter Mastering these operations will allow you to effectively use your board for data acquisition applications Selecting an Analog Input Channel After the ADA2100 has been initialized you can select the analog input channel The analog input channel is selected by writing to PPI port B mapped at I O location base address BA 1 The input channel and the input gain can be set individually by setting only the four LSBs channel select or only the four MSBs gain of the eight bit control word sent to port B Before you change either the input channel or the gain you MUST preserve the current state of port B Failure to do so will result in changing both the channel select and the gain when you intended to change only one of these two settings The general algorithm for setting the channel changing just the four LSBs of the control word while preserving the four MSBs is 1 Read the current state of port B current state inp base_address 1 2 Preserve the upper four bits since they contain gain data current sta
64. connector on the board P8 accommodates all of the board s external I O Functions You Can Set To allow the ADA2100 interface board to be adapted to your needs several functions can be set up to perform specific tasks by changing the hardware configuration or through software Table 1 1 lists each function you can control the factory or default setting if applicable and where in this manual you can find information about its settings Table 1 1 ADA2100 Board Functions and Settings FUNCTION FACTORY SETTING USER INFORMATION Base I O Address 300 hex 768 decimal To change this setting see Setting the Base I O Address Chapter 1 Analog Input Channel Type Adifferential channels To select 8 single ended channels see S1 discussion Chapter 3 Software controllable Analog Input Channel Selection See Selecting an Analog Input Channel Chapter 1 and demo disk Analog Input Gain Selection Software controllable See Setting the Input Gain Chapter 1 and demo disk Analog Input Voltage Range and Polarity User specified when ordering To change these settings see 51 and P9 discussions Chapter 3 Connected to PA7 End of Convert EOC Monitor See P6 discussion Chapter 3 Analog Output Voltage Range and Polarity Voltage range user specified when ordering factory set with same polarity as A D To change these settings see P10 discu
65. cribed The internal block diagram of a single counter is shown in Figure 5 The Counters are fully independent Each Counter may operate in a different Mode The Control Word Register is shown in the figure it is not part of the Counter itself but its contents de termine how the Counter operates 3 85 Figure 5 Internal Block Diagram of a Counter The status register shown in the Figure when latched contains the current contents of the Control Word Register and status of the output and null count flag See detailed explanation of the Read Back command The actual counter is labelled CE for Counting Ele ment It is a 16 bit presettable synchronous down counter Olm and OL are two 8 bit latches OL stands for Output Latch the subscripts M and L stand for Most significant byte and Least significant byte respectively Both are normally referred to as one unit and called just OL These latches normally fol low the CE but if a suitable Counter Latch Com mand is sent to the 82C54 the latches latch the present count until read by the CPU and then return to following the CE One latch at a time is enabled by the counter s Control Logic to drive the internal bus This is how the 16 bit Counter communicates over the 8 bit internal bus Note that the CE itself cannot be read whenever you read the count it is the OL that is being read Similarly there are two 8 bit registers called C
66. d Tw max will result a latched count vallue which is one least significant bit EXTENDED TEMPERATURE Ta 40 C to 85 C for Extended Temperature Min Max Min We GKOswiwiwmdy 5 5 we Gate BelayfrSarping 2 26 _ intel 82054 WAVEFORMS WRITE DATA BUS 231244 14 DATA BUS em c ae 231244 15 RECOVERY 231244 16 3 98 intel 82054 CLOCK AND GATE OUTPUT O 231244 17 Last byte of count being written A C TESTING INPUT OUTPUT WAVEFORM A C TESTING LOAD CIRCUIT INPUT OUTPUT DEVICE 2 0 UNDER TE gt TEST POINTS lt C 180 pF i 231244 18 T Testing Inputs are driven at 2 4V for a logic 1 and 0 45 for a logic 0 Timing measurements are made at 2 0V for a logic 231244 19 CL 150 pF 4 and 0 8V for a logic 0 C includes Jig capacitance 3 99 Intel 82C55A Programmable Peripheral Interface Data Sheet Reprint s intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most n Other Microprocessors High Speed Zero Wait State Operation with 8 MHz 8086 88 and 80186 188 m 24 Programmable 1 0 Pins n m Low Power CHMOS m Completely TTL Compatible Control Word Read Back Capability Direct Bit Set Reset Capability 2 5 mA DC Drive Capability o
67. d of Convert Interrupt Jumpers P5 amp P7 P6 End of Convert Monitor When running SIGNAL MATH place a jumper between EOC and 7 as shown in Figure D 4 P6 PC7 PA7 Fig D 4 End of Convert Monitor Jumper P6 4 Running ADAINST After the jumpers are set and the ADA2100 board is installed in the computer you are ready to configure SIGNAL MATH so that it is compatible with your board s settings This is done by running the ADAINST driver installation program After running the program open ADA2100 EXE from the Open a File menu You will see a screen similar to the screen shown in Figure D 5 below The factory default settings are shown in the illustration Your settings may or may not match the default settings depending on whether you have made changes to these settings before Base Address The board s base address setting is entered in the upper right block as shown in the diagram The factory setting for all Real Time Devices boards is 300 hex 768 decimal The base address can be entered as a decimal or hexadecimal value hex values must be preceded by a dollar sign for example 300 Refer to your board s manual if you need help in determining the correct value to enter EOC IT End of Convert Interrupt In this block enter the IRQ channel number which corresponds to your jumper setting on P7 Timer IT Timer Counter Interrupt In this block enter the IRQ channel number which corresponds to your jumpe
68. d written to an internal register Two bits define the mode selection mode 0 mode 1 or mode 2 Four bits configure the I O direction one bit to control PAO PA7 one bit to control PBO PB7 one bit to control PCO PC3 and one bit to control PC4 PC7 Port C is divided into two four bit fields so that it can provide status and control for port A if desired in your application The control word is defined in Figure 4 1 The PPI is configured by writing a control word to it s internal control register Upon power up all ports are configured as mode 0 inputs The PPI is written to during board initialization so that port B is set up as a mode 0 output to configure it for channel selection and gain control functions Chapter 1 Initializing Your ADA2100 describes this procedure Because the PPI can be configured for a wide range of operating modes and programming requirements it is heavily dependent on correctly understanding how to use the proper control byte to configure the PPI for your application The demo disk includes example programs that show how to select the common operating modes Reading the source code is highly recommended For more information about the operation of the PPI see the data sheet included in Appendix C 4 1 Lozl nel os pr vo PORT C LOWER 1 INPUT 0 OUTPUT PORT 1 INPUT 0 OUTPUT MODE SELECTION 0 MODE O 1 MODE 1 GROUP A PORT C UPPER 1 INPUT 0
69. defined by a Set Mode command During a read of Port C the state of all the Port C lines except the ACK and STB lines will be placed on the data bus In place of the ACK and STB line states flag status will appear on the data bus in the PC2 4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in a Mode 0 group be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in a Mode 1 group or to 82C55A GROUP A ONLY gt gt lt gt gt gt gt gt MODE 0 OR MODE 1 ONLY change interrupt enable flag the Set Reset Port C Bit command must be used With a Set Reset Port C Bit command any Port C line programmed as an output including INTR IBF and OBF can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including ACK and STB lines associated with Port C are not affected by Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK and STB lines with the Set Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Port A B or C can sink or source 2 5 mA This feature allows the 82C55A to
70. directly drive Darlington type drivers and high voltage displays that require such sink or source current 3 139 intel 82C55A Reading Port C Status INPUT CONFIGURATION In Mod Port C f f h 2 Ds Do ripheral device When the 82C55A is programmed to 24 ca Ming RITA ae function in Modes 1 or 2 Port C generates or ac cepts hand shaking signals with the peripheral de SEEN GROVES vice Reading the contents of Port C allows the pro OUTPUT CONFIGURATIONS grammer to test or verify the status of each pe D Ds D4 D3 Do D Do ripheral device and change the program flow ac SEE GROUP A GROUP B There is no special instruction to read the status in formation from Port C A normal read operation of Figure 17a MODE 1 Status Word Format Port C is executed to perform this function De 5 De D3 Di Do ACA I I 1 GROUP A GROUP Defined By Mode 0 or Mode 1 Selection Figure 17b MODE 2 Status Word Format Alternate Port C Pin Signal Mode ACKg Output Mode 1 or STBg Input Mode 1 STB Input Mode 1 or Mode 2 Output Mode 1 or Mode 2 Figure 18 Interrupt Enable Flags in Modes 1 and 2 Interrupt Enable Flag Position INTEB INTE A2 INTE A1 3 140 intel 82C55A ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias 0 Cto 70 C Storage Temperature 65 C
71. ed together to pin 35 on xternal I O connector P8 as shown in Figure 3 4 Counter Outputs COx One of these three outputs can be horizontally jumpered to the corresponding OUT pin on the right side of the connector so that the selected timer counter s clock output signal can be routed to pin 36 on external I O connector P8 Note that because all three outputs are connected together and routed to one external I O pin only one of the three counter timer outputs can be jumpered at a time the remaining two are available on board COO is factory set as the jumpered output COx This output can be horizontally jumpered to the corresponding OUT pin on the right side of the connector to provide the inverse of the clock output signal CKx This input connects the output of one timer counter to the clock input of the next timer counter CKx is provided for TC1 and TC2 only and is connected to the output of the previous timer counter TCO or TC1 by placing a jumper horizontally between the pins These connections are used to cascade the timer counters for longer time delays than are supported by a single timer counter circuit 8254 ata U5 Q C O O OUTO OO O 9 CKI O en O OUTI Cam e P8 17 2 8 18 0 en EXTGATE O P8 38 O CLKOUT 5 m lt OUT2 Fig 3 4 PIT Functional Block Diagram nd P7 Interr r Conn Header connectors P5 and P7 are used to
72. el IRQ2 through IRQ7 Chapter 3 Jumper Settings and Chapter 4 Programming Your ADA2100 describe these interrupts in more detail 2 4 CHAPTER 3 JUMPER SETTINGS This chapter describes the ADA2100 board settings you control DIP switch S1 and various header connectors Y ou can use this chapter to tailor your board s functions to your specific application before installing itin your computer orto change the board s configuration as you learn more about its operation and special features In this chapter you will learn about each setting and how to set switches or install jumpers to achieve the desired operation of your board Before changing any settings you should have a functional knowledge of the circuit you are setting up see Chapter 2 Remember that all of the settings described in this chapter have been factory set or as in the case of the interrupt signals are disabled Therefore you do not have to do any further set up of the board in order for it to operate in your system as described in Chapter 1 The descriptions in this chapter allow you to change factory settings or to tailor your board to take full advantage of its built in versatility There are one DIP switch and several header connectors which allow you to control various board functions as shown in the board layout in Figure 3 1 These are presented as follows 1 Analog Input Signal Type DIP Switch P2 Base I O Addre
73. erything about your board so that you can effectively use each feature With this in mind this manual provides basic information to get the board up and running as well as detailed information for a full understanding of each function W This Manual This manual is designed to help you install and get your ADA2100 running quickly while also including sufficient detail about each board function Begin by reading Chapter 1 in order to use your board as quickly as possible This chapter and the accompanying demonstration software included with your ADA2100 package will allow you to promptly use your interface To fully understand and control the ADA2100 functions read Chapters 2 through 4 Chapter 5 contains board calibration procedures The chapters and appendixes in this manual are described in detail below Chapter 1 Quick Start Getting Your ADA2100 Running provides the instructions necessary to install the board and use its basic functions The information contained in this chapter does not cover how to change the board setup except for the base I O address Chapter 2 Functional Description provides a block diagram and a functional discussion of the board Chapter 3 Jumper Settings describes each header or jumper circuit on the board and how it is controlled Chapter 4 Programming Your ADA2100 describes how the board can be programmed using the demonstration software Chapter 5 Calibration Procedures provides ins
74. for your board Each example program shows you how to control a particular board function such as selecting an input channel or input gain controlling the A D and D A converters controlling digital data transfers and setting the timer counter circuitry These programs should be used to become familiar with these functions Backing Up Your Disk The demo disk provided with the ADA2100 is a double sided format which can be read by all DOS versions 1 1 and above Before using the software included with your board make a backup copy of the disk You may make as many backups as you need To copy the original to any other DOS formatted disk insert the disk to be copied into drive A of your computer and from DOS enter COPY A B or other destination drive specifier Initializin r ADA21 Before you can operate the ADA2100 it must be initialized This step must be executed every time you start up reset or reboot the computer This sets up the PPI to properly communicate with the A D converter circuitry If the board is not initialized it will not respond to the software commands and will probably lock up requiring you to reboot your system As described earlier the ADA2100 uses 24 consecutive address locations in the computer s I O space These address locations start with the base I O address BA and go through BA 17 hex Table 1 2 provides the ADA2100 I O defining what function each of the 24 addresses controls Recall that
75. gger results in loading the Counter and setting OUT low on the next CLK pulse thus starting the one shot pulse An initial count of N will result in a one shot pulse N CLK cycles in dura tion The one shot is retriggerable hence OUT will remain low for N CLK pulses after any trigger The one shot pulse can be repeated without rewriting the same count into the counter GATE has no effect on OUT If a new count is written to the Counter during a one shot pulse the current one shot is not affected un less the Counter is retriggered In that case the Counter is loaded with the new count and the one shot pulse continues until the new count expires CW 12 LS823 CWz12 LSB 3 CW 12 158 2 paja 2 REP dem 231244 9 Figure 16 Mode 1 MODE 2 RATE GENERATOR This Mode functions like a divide by N counter It is typicially used to generate a Real Time Clock inter rupt OUT will initially be high When the initial count has decremented to 1 OUT goes low for one CLK pulse OUT then goes high again the Counter re loads the initial count and the process is repeated Mode 2 is periodic the same sequence is repeated indefinitely For an initial count of N the sequence repeats every N CLK cycles GATE 1 enables counting GATE 0 disables counting If GATE goes low during an output pulse OUT is set high immediately A trigger reloads the Counter with the initial count on the next CLK pulse OUT goes low N CL
76. h are written into the registers as described in Chapter 1 Controlling the D A Converter After the input registers are loaded an update command written to the D A converter starts the actual conversion process The output of the converter is a current value which accurately represents the 12 bit data word Both channels can be cleared by writing to the appropriate I O address location Output Amplifiers The D A converter s current output from each channel is fed through a high speed precision monolithic operational amplifier where it is converted into a proportional voltage for output on external I O connector P8 This voltage is either a unipolar or bipolar value depending on the configuration of the board Both op amps are contained in one IC package providing excellent slew rate and tracking characteristics Programmabl 2 The Programmable Peripheral Interface PPT provides 16 digital I O lines which can be configured in a number of ways to support user requirements The lines available for digital I O are port A and port C The 8255 PPI has a total of 24 digital I O lines eight of which are used to control the A D channel selection and gain circuitry and therefore are not available to the user Of the remaining lines eight are available at the external I O connector and eight are available at on board pads These lines are grouped into three eight bit ports port A port B and port C Port C is further subdivided into two f
77. he A D converter Fig 2 2 EOC Timing Diagram 2 2 Digital to Anal nversion Circuitr By providing a digital to analog D A conversion capability the ADA2100 interface board can output the digitized data as analog voltages to be displayed on strip charts oscilloscopes and other such devices The data can be output slow or fast to support specific requirements The D A conversion circuitry receives 12 bit digital words mapped into a right justified two byte data field in its two independent channels and converts them to voltage outputs D A Converter The D A converter consists of two closely matched 12 bit current output D A converters in one monolithic IC to provide twoanalog output channels available at external I O connector P8 By using dual converters in a single package excellent thermal tracking and monotonicity across the 12 bit range are maintained Both D A converter channels are internally double buffered and can be updated simultaneously to prevent voltage glitches on the outputs Both converters support a 5 or 10 volt unipolar or bipolar output voltage range depending on the board configuration The two converters are identical 12 bit multiplying D A converters each with two pairs of input registers to allow simultaneous updating of both channels A conversion is initiated by first loading data into the first pair of registers This data is contained in two bytes eight bits in the LSB and four bits in the MSB whic
78. hree timer counter circuits is from the 5 MHz crystal oscillator labeled Y 1 located near the center of the board By connecting XTAL to the CKx input on the right side of the connector with a jumper placed horizontally between the pins the 5 MHz clock is applied to the timer counter circuit If required by your application the XTAL frequency can be changed by installing a different crystal oscillator at Y1 Note however that the maximum frequency at which the PIT will operate is 8 MHz 3 2 XTAL 9 ECO e 45V 9 EGO COO COO 3 XTAL S EC1 45V CO1 2 XTAL EC2 3d 45V E EG2 co2 CO2 Fig 3 3 PIT I O Header Connector ECx This input allows an external clock other than the XTAL signal to control the timing of the corresponding timer counter circuit This pin can be horizontally jumpered to the CKx input on the right side of the connector in place of the XTAL source ECO and EC2 are tied together to pin 33 on external I O connector P8 as shown in Figure 3 4 Gate Inputs 5V This input if connected to the GTx input by placing a jumper horizontally between the two pins places the associated timer counter circuit in an enabled state at all times EGx This input can be horizontally jumpered to the GTx input on the right side of the connector to provide an external gate input instead of the 5 volts input EGO EG1 and EG2 are ti
79. ing Modes and Port B use the lines on Port C to generate or Both inputs and outputs are latched accept these handshaking signals The 4 bit port is used for control and status of the 8 bit data port 3 133 intel 82C55A input Control Signal Definition STB Strobe Input A low on this input loads MODE 1 PORT A data into the input latch CONTROL WORD D 0 0 0 Dz D D IBF Input Full F F mel A high on this output indicates that the data has pipa been loaded into the input latch in essence an ac knowledgement IBF is set by STB input being low and is reset by the rising edge of the RD input INTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service Bono on p A INTR is set by the STB is a one IBF is a LS and INTE is a one It is reset by the falling edge of DVD RD This procedure allows an input device to re quest service from the CPU by simply strobing its data into the port CONTROL WORD INTE A Controlled by bit set reset of PC4 INTE B Controlled by bit set reset of PCo Figure 8 MODE 1 Input INPUT FROM PERIPHERAL 231256 14 Figure 9 MODE 1 Strobed Input 3 134 intel 82 55 Output Control Signal Definition OBF Output Buffer Full F F The output will go low to indicate that the CPU has written data out
80. ion The analog to digital A D conversion circuitry receives inputs from four differential or eight single ended analog channels selects one active channel and performs an analog to digital conversion of the voltage value read at that channel The conversion throughput rate is typically 38 kHz Multiplexer An eight bit analog multiplexer is used to connect either one of eight single ended or one of four differential analog channels to the gain circuitry The leftmost three switches on DIP switch S1 setup the multiplexer to receive either single ended or differential inputs When these three switches are up the multiplexer is configured for single ended inputs and when they are down the multiplexer is configured for differential inputs Note that these three switches are always set as a group to the same position see 51 Switch Settings Chapter 3 A channel is selected through software control by writing to Port B of the PPI as described in Chapter 1 Gain Control Circuitry The programmable gain control circuitry can provide a gain factor of 1 2 4 8 or 16 The gain selection is made by writing to Port B of the PPI as described in Chapter 1 The gain factor is controlled by the setting of four analog switches For a gain of 2 4 8 or 16 this write operation will close one of the four switches for a gain factor of 1 all switches are open Note that programming gain factors other than the five listed here is not recommended
81. ipolar Calibration Two adjustments are necessary to calibrate the A D converter for the unipolar voltage range of 0 to 10 volts one for Offset and one for full scale To adjust the offset a very low analog input voltage shown under the Offset heading in the following table is connected to the channel 1 input of the multiplexer P8 1 The ground reference of this signal should be connected to P8 2 While continuously displaying 12 bit A D conversions adjust TR7 until the A D data flickers between the two values listed in the table under Offset After the offset adjustment is made then TR6 is used to adjust the full scale value While the full scale input voltage listed in the table is not the actual full scale voltage for an ideal 0 to 10 volt range it is the maximum voltage at which the A D conversion is guaranteed to be linear Any value above this voltage may not be linear and thus may adversely affect calibration After connecting the full scale voltage listed in the table to the channel 1 input adjust TR6 until the data flickers between the two values in the table under Full Scale 0 to 10 volts range Offet TR2 Full Scale TR6 0000 0000 0001 1111 0011 0011 Bipolar Calibration Whether you are selecting the bipolar input voltage range of 5 to 5 volts or 10 to 10 volts the following calibration procedure can only be performed with the board configured for a 5 to 5 volt input voltage range This means that the jumper
82. l 8 bit buffer is used to in terface the 82C54 to the system bus see Figure 3 231244 4 Figure 3 Block Diagram Showing Data Bus Buffer and Read Write Logic Functions READ WRITE LOGIC The Read Write Logic accepts inputs from the sys tem bus and generates control signals for the other functional blocks of the 82C54 and Ay select one of the three counters or the Contro Word Regis ter to be read from written into A low on the input tells the 82C54 that the CPU is reading one of the counters A low on the WR input tells the 82C54 that the CPU is writing either a Contro Word or an initial count Both RD and WR are qualified by CS RD and WR are ignored unless the 82C54 has been selected by holding CS low CONTROL WORD REGISTER The Control Word Register see Figure 4 is selected by the Read Write Logic when A4 Ag 11 If the CPU then does a write operation to the 82C54 the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters The Control Word Register can only be written to status information is available with the Read Back Command DATA Bus TER a GATE 0 BUFFER 422 n 2 2 a 12 Figure 4 Block Diagram Showing Contro Word Register and Counter Functions COUNTER 0 COUNTER 1 COUNTER 2 These three functional blocks are identical in opera tion so only a single Counter will be des
83. l Input Voltage millivolts A D Bit Weight 4095 Full Scale 4997 6 9997 6 2048 0000 0 5000 0 1024 2500 0 2500 0 512 3750 0 1250 0 4375 0 625 00 128 4687 5 312 50 4843 8 156 250 4921 9 78 125 4960 9 39 063 4980 5 19 5313 4990 2 9 7656 4995 1 4 8828 4997 6 2 4414 5000 0 0 0000 Four trimpots TR1 through TR4 are used to adjust the gain circuitry one for each of the gains 2 4 8 and 16 Tocalibrate this circuitry apply an input voltage 39 063 millivolts to the input of channel 1 Next by writing the correct word to the BA 1 T O location set the gain to 2 and adjust trimpot TRI to obtain the 12 bit A D converter output for your board s voltage range as listed in Table 5 2 below Then repeat this procedure for each of the remaining three gain settings adjusting the appropriate trimpot until achieving the correct value listed in the table Table 5 2 A D Converter Readings for Gain Calibration Gain Trimpot 10 Volts 0 to 10 Volts 2 1000 0010 0000 1000 0001 0000 0000 0010 0000 4 TR2 1000 0100 0000 1000 0010 0000 0000 0100 0000 8 TR3 1000 1000 0000 1000 0100 0000 0000 1000 0000 16 4 1001 0000 0000 1000 1000 0000 0001 0000 0000 D A Calibrati The D A converter can be used in either a unipolar or a bipolar configuration Each has a different calibration procedure Both D A converter channels are factory calibrated for outputs which are set to match the s
84. lity of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and pull down bus hold devices are present on Port A Port B One 8 bit data input output latch buffer Only pull up bus hold devices are present on Port B Port C One 8 bit data output latch buffer and one 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port A B and C 3 126 intel 82 55 POWE SUPPLIES GND BIDIAECTIONAL DATA BUS 231256 3 Figure 3 82C55A Block Diagram Showing Data Bus Buffer and Read Write Control Logic Functions EXTERNAL INTERNAL PORT A DATA PIN INTERNAL DATA OUT INTERNAL DATA lai 231256 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following a hardware reset Figure 4 Port A B C Bus hold Configuration 3 127 intel 82C55A 82C55A OPERATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selected by the system software Mode 0 Basic input output Mode 1 Strobed input output Mode 2
85. lse Width 100 tst STB Pulse Width DEBE o NEN O E cub A 200 NE eee 100 a NC ts Per Data Before STB High 20 nm PerDataAfterSTBHigh 50 ms ACK 0 to Output Ps Wo 1 250 ns p E E la ns E gu NEN le et PA NE MEE E nm O me 500 ne d twos WH 1t0BF O 150 STE RD 1 to IBF 0 RD Oto INTR 0 ACK 1 to INTR 1 WR OtoINTR 0 aes Reset Pulse Width NOTE 1 INTR may occur as early as WR I 2 Pulse width of initial Reset pulse after power on must be at least 50 Sec Subsequent Reset pulses be 500 ns minimum 150 200 160 175 150 see note 1 mo p 3 143 inte 82C55A WAVEFORMS MODE 0 BASIC INPUT 231256 22 MODE 0 BASIC OUTPUT 3 144 intel a WAVEFORMS Continued MODE 1 STROBED INPUT INPUT FROM PERIPHERAL 231256 24 231256 25 3 145 intel 82C55A WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8060 TO 8255 PERIPHERAL BUS DATA FROM DATA FROM PERIPHERAL 8255 8255 TO PERIPHERAL DATA FROM 8265 TO 8080 Note Any sequence where WR occurs before ACK AND STB occurs before RD is permissible INTR IBF e MASK STB RD OBF e MASK WR WRITE TIMING READ TIMING DATA BUS 2
86. m port C can be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port C This function allows the Programmer to disallow or allow a specific 1 device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET Interrupt disable Note All Mask flip flops are automatically reset during mode selection and device Reset 3 129 intel 82C55A Operating Modes Mode 0 Basic Functionai Definitions e Mode 0 Basic Input Output This functional con Two DE prs ano tuo M ports figuration provides simple input and output opera e Any port can be input or output tions for each of the three ports No handshaking Outputs are latched is required data is simply written to or read from a e Inputs are not latched specified port P 4 16 different Input Output configurations pos sible in this Mode MODE 0 BASIC INPUT O tao E tor 9 231256 8 MODE 0 BASIC OUTPUT tww m twa taw T AAA A 231256 9 3 130 intel 82C55A MODE 0 Port Definition GROUP A GROUP B PORT PORT B LOWER OUTPUT OUTPUT OUTPUT INPUT INPUT OUTPUT INPUT 1 OUTPUT INPUT OUTPUT INPUT 12 OUTPUT OUTPUT 13 INP
87. n all 1 0 Port Outputs Available in 40 Pin DIP and 44 Pin PLCC Available in EXPRESS Standard Temperature Range Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255A general purpose programmable 1 device which is designed for use with all Intel and most other microprocessors It provides 24 pins which may be individually programmed in 2 groups of 12 and used in major modes of operation The 82C55A is pin compatible with the NMOS 8255A and 8255 5 MODE 0 each group of 12 1 0 pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may be programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi directional bus configuration The 82C55A is fabricated on Intel s advanced CHMOS III technology which provides low power consumption with performance equal to or greater than the equivalent NMOS product The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages SY POWER SUPPLIES TETTO C i uw CONTROL Mi DMEC TIONAL DATA BUS Figure 1 82C55A Block Diagram 231256 1 231256 2 Figure 2 82C55A Pinout Diagrams are for pin reference only Package sizes are not to scale 3 124 September 1987 Order Number 231256 004 inte 82C55A Tabie 1 Pin De
88. n mode 2 port A is an eight bit bidirectional bus and port C is a five bit control port Port B cannot be used in this mode but is available for use in mode 0 or mode 1 while port A is in mode 2 Both inputs and outputs are latched 2 3 PPI is configured by writing a control word to the appropriate I O address location as described in Chapter 4 Programming Your ADA2100 The control word can also be used to individually set or reset the port C bits This feature allows any bit of port C to be set or reset without affecting the other port C bits The data sheet included in Appendix C explains this feature The PPI can also be used to generate interrupts in mode 1 or mode 2 operation In these modes the interrupt enable INTE mask is used to enable the INTRA and INTRB interrupt signals Note that the INTRB signal for PPI cannot be used since port B of this PPI is always configured as mode 0 output and is reserved for channel selection and gain control Interrupt functions are further explained in the data sheet in Appendix C The ADA2100 board provides a header connector which can jumper the A D converter end of convert EOC signal to a PPI bit where it can be monitored to provide A D conversion status The EOC signal can be jumpered to either PA7 port A bit 7 or PC7 port C bit 7 The default setting of the jumper is PA7 The port used to monitor the EOC signal must be configured as a mode 0 input port Programmable Interv
89. nd status of a counter are latched the first read operation of that counter will return latched status regardless of which was latched first The next one or two reads depending on whether the counter is programmed for one or two type counts return latched count Subsequent reads return un latched count Results Count and status latched for Counter 0 Read back status of Counter 1 Status latched for Counter 1 Read back status of Counters 2 1 Status latched for Counter 2 but not Counter 1 Read back count of Counter 2 Count latched for Counter 2 111 1 Read back count and status of Count latched for Counter 1 Counter 1 but not status Read back status of Counter 1 Command ignored status already latched for Counter 1 Figure 13 Read Back Command Example 3 90 CS WR Write into Countero 011 091011 Write into Counters lo 1 0 11 Write into Counter2 11 1 Write Control word 0 Read trom Counter 0 Lo o 1 0 1 Read trom Counter 1 lo Read from Counter 2_ el e 1 x X x x 3 State Lo 1 I 1 x x No Operation States Figure 14 Read Write Operations Mode Definitions The following are defined for use in describing the operation of the 82 54 CLK PULSE a rising edge then a falling edge in that order of a Counter
90. neneensnnennnene 2 Resolution 12 bits Relative accuracy 1 bit max Full scale accuracy 3 bits max Non linearity 1 bit max Channel to channel isolation 84 dB typ Chip selectable output range Option 1 0 to 45V jumper selectable to 5 Option 2 0 to 10V jumper selectable to 10V Settling time to 0 01 1 8 usec typ 3 3 usec max LETO CO GrP m 1 2 bit typ Crosstalk incurante 90 dB typ Output current 10 mA Miscellaneous I Os Power Requirements Connector Environmental Size 12V 5V PC bus sourced Ground PC bus sourced 5 Volti una ci la 240 mA 12 Vol 30 mA MIC RR m 35 mA 40 pin right angle shrouded header with ejector tabs Operating 0 to 70 C Storage 40 to 85 C H midity 01090 non condensing Height clear 3 875 99 mm RR RE 6 50 165 mm A 2 APPENDIX CONNECTOR PIN ASSIGNMENTS Pin No Signal Name Pin No Signal Name SE DIFF 1 AIN1 AINl 2 3 AINS AINI 4 GND 5 AIN2 AIN2 6 7 AIN6 AIN2 8 GND 9 AIN3 AIN3 10 GND 11 AIN7 AIN3 12 GND 13 AIN4 AINd 14 GND 15
91. nter 2 Control Word Register Chip Select A low on this input enables the 82C54 to respond to RD and WR signals RD and WR are ignored otherwise Read Control This input is low during CPU read operations 12 14 18 GATE 2 19 OUT 2 17 i cs 21 24 ve z operations 2 gt re 1 11 15 25 sired delay After the desired delay the 82 54 will FUNCTIONAL DESCRIPTION interrupt the CPU Software overhead is minimal and variable length delays can easily be accommodated General Some of the other counter timer functions common The 82C54 is a programmable interval timer counter to microcomputers which can be implemented with designed for use with Intel microcomputer systems the 82C54 are Itis a general purpose multi timing element that can be treated as an array of I O ports in the system software Real time clock Even counter Digital one shot Programmable rate generator Square wave generator Binary rate multiplier Complex waveform generator Complex motor controller The 82 54 solves one of the most common prob lems in any microcomputer system the generation of accurate time delays under software control In stead of setting up timing loops in software the pro grammer configures the 82C54 to match his require ments and programs one of the counters for the de 82 54 Block Diagram DATA BUS BUFFER This 3 state bi directiona
92. nto the least significant byte and data bits DB8 through DB11 are loaded into bits 0 through 3 of the most significant byte The setting of bits 4 through 7 of the most significant byte does not matter since they are not used A sample Turbo Pascal program for generating a channel AOUTI output is Begin board 300 Write Data for channel AOUTI Read In a amsb a div 256 alsb a amsb 256 Port Board 8 alsb Port Board 9 amsb Port Board C 0 end The I O locations that control the D A converter functions are listed below from Table 1 2 Program AOUT1 LSB Program AOUT1 MSB Program AOUT2 LSB Program AOUT2 MSB Convert Update AOUT1 AOUT2 C D E or F Clear AOUT1 AOUT2 10 11 12 or 13 The input registers for each D A converter are loaded by using the corresponding base address hex values listed above To start a D A conversion a write operation to I O location base address C D E or F select one of these locations must be executed It does not matter what is written the act of writing to one of these four I O locations will initiate a D A conversion in both channels To clear the outputs of both channels simply write to I O location base address 10 11 12 or 13 Again the act of writing to any one of these four locations will clear the outputs the data written is not important Note that these outputs are also cleared every time a hardware system reset occurs Outpu
93. o monitor the end of convert EOC signal The PPI must be programmed so that port A is an input if you are going to monitor the EOC signal through PA7 The control byte must then conform to the general form of 1xx1 00 where the underlined 1 is the data bit which sets up port A as an input A functional description of the PPI is contained in Chapter 2 Functional Description and hardware configurations are described in Chapter 3 Jumper Settings Information about how you can control the digital I O lines is contained in Chapter 4 Programming Your ADA2100 As mentioned earlier the eight lines of port B are used to select the analog input channel and gain The four LSBs PB for Port 0 through PB3 control the channel selection and the four MSBs through PB7 control the gain selection The bit assignment of this port is MSBs LSBs 7654 3210 PPI Base Address 1 Vo pr nn gain select channel select 0000 1x 0000 channel 1 0001 2x 0001 channel 2 0010 4x 0010 channel 3 0100 8x 0011 channel 4 1000 16x 0100 channel 5 0101 channel 6 0110 channel 7 0111 channel 8 1 7 After the ADA2100 is initialized the port register is loaded with the default setting of 0000 0000 This selects channel 1 as the input channel with a gain of 1 To change this value for example to a gain of 2x on channel 8 enter these commands BA 1 hex selects port B 0001 0111 sets gain to 2x and
94. o recognize that some of your computer s I O address locations will already be occupied by internal I O and other peripherals If your ADA2100 board tries to use I O address locations already in use by another device in your system address contention will result Hence the board will not operate or at best will operate erratically I O address contention is one of the most common problems encountered when adding an interface device to your computer system To avoid this problem a base I O address jumper circuit is provided on the ADA2100 board By changing the position of the jumper on the header connector labeled P2 located just left of center near the bottom of the board the base I O address setting can be changed to any one of eight locations 1 3 Table 1 2 ADA2100 Map FUNCTION uds 0 1 0 1 0 1 0 1 0 1 0 1 Programmable Peripheral Interface Port A Port B Channel Sel amp Gain Port C Control Word A D Conversion Circuitry Start 12 bit Conversion Start 8 bit Conversion Read MSB Read LSB D A Conversion Circuitry Program AOUT1 LSB Program AOUT1 MSB Program AOUT2 LSB Program AOUT2 MSB Convert Update AOUT1 AOUT2 Clear AOUT1 AOUT2 Programmable Interval Timer Counter 0 Counter 1 Counter 2 Control Word 8 9 A B C D E or F 10 11 12 or 13 cool un NOTE x don t care setting 14 Figure
95. oard If you intend to use the interrupts they must be configured appropriately before installing the board Information about these and other functions not covered in this chapter is provided in Chapters 2 through 4 Use these chapters as necessary to configure your board before installation To install your ADA2100 follow these step by step procedures 1 TURN OFF THE POWER TO YOUR COMPUTER FIRST Refer to the owner s manual for your computer and remove the top cover 2 Selectan unused expansion slot in which to install your board and remove its corresponding blank bracket from the rear panel of the computer by removing the screw at the top of the bracket 3 Orient the board inside the computer so that I O connector P8 is accessible at the rear panel opening and the card edge connector lines up with the expansion slot connector Then press down on the metal bracket tab and the top of the board until the board is firmly seated in the expansion slot connector 4 Secure the bracket back in place with the screw and put the cover back on your computer Now your board is ready to be connected via the external I O connector at the rear of the computer After this connection has been made the board is ready for operation The Software ADA2100 operates under software control Programming includes the analog input channel selection and gain control of the the A D and D A conversions the programmable peripheral interface PPI and the
96. our bit ports port C lower PCO PC3 and port C upper PC4 PC7 in certain modes of operation The PPI data sheet is included in Appendix C The eight bits of port B are reserved for A D channel selection and gain control and cannot be configured for I O use Ports A and C can be configured in any of the three operating modes described below Mode 0 Basic input output Provides simple input and output operations for each port Data is written to or read from a specified port Mode 1 Strobed input output Provides a means for transferring I O data to or from port A or port B in conjunction with strobes or handshaking signals Mode 2 Strobed bidirectional input output Provides a bidirectional means of communicating with another device ona single eight bit bus Handshaking signals are similar to mode 1 This mode applies to port only In mode 0 all four ports A B C lower and C upper are available as I O lines Sixteen configurations are possible in this mode and any port can be configured as an input or an output The outputs are latched but the inputs are not latched In mode 1 the four ports are grouped into two groups Each group contains one eight bit data port port A or port B and one four bit control data port port C lower or port C upper which is used for control and status of the eight bit port The eight bit data port in each group can be configured as an input or an output Both inputs and outputs are latched I
97. pecified A D input polarity If you are verifying unipolar output accuracy follow the unipolar calibration procedure below If you have bipolar outputs follow the bipolar calibration procedure below Unipolar Calibration Two adjustments are necessary to calibrate the D A converter for full scale unipolar operation one for each of the two converter channels This procedure uses trimpots TR8 and TR9 to make the adjustments The full scale adjustmentcalibrates the reference voltage used by the D A converter to compensate for the analog outputs Calibration is accomplished by monitoring the output voltage of each channel at external I O connector P8 and adjusting the appropriate trimpot The analog output its P8 pin assignment and its associated trimpot are 5 3 Output Trimpot P8 Pin Assignment AOUTI TR9 19 SIGNAL 20 GND AOUT2 TRS 21 SIGNAL 22 GND Program the D A converter to output a full scale voltage by writing XFFF to base I O address locations BA 8 and 9 for AOUTI and BA A and BA B for AOUT2 Use the digital voltmeter to monitor the output voltage present between the appropriate P8 signal and ground pins Using Table 5 3 adjust the appropriate trimpot until the voltage equals the full scale voltage in Table 5 3 as measured by the voltmeter Table 5 3 lists the maximum D A unipolar output voltage for each bit weight in a 12 bit conversion for 5 and 10 volt references Note that the voltage values in the
98. programmable interval timer The analog input channel and gain selections taking an A D reading and controlling the D A converter are covered in this chapter Digital I O control through the PPI and control of the programmable interval timer are more complex and are described in Chapter 4 Programming Your ADA2100 1 5 Regardless of what programming language you use you can write programs that control the ADA2100 board The demonstration disk which accompanies your ADA2100 contains examples in Turbo C Turbo Pascal and BASIC Nearly ali modern MS DOS based PC languages have I O reference instructions These are the instructions to control the data transfers to and from the I O ports Consult your programming language reference to find these instructions for your favorite language Listed below are the I O reference instructions used by some common languages BASIC TURBO PASCAL TURBO C input INP Port inportb output OUT Port outportb Demo Disk Included with your ADA2100 is a demo disk which provides programming instructions and example programs for controlling the functions of your interface board This demo disk is divided into directories each of which is named according to the language used to write the programs it contains The files within each directory contain example programs and a documentation file with general information In addition your demo disk contains a README DOC file which provides programming information
99. pt you must be very careful to ensure that the PC system s programmable interrupt controller PIC is properly configured to ignore interrupts on the selected interrupt channel immediately after power up This is necessary because the PIT must first be initialized to define the desired mode s of operation Prior to initialization the mode count and output of all counters are undefined If the system interrupts are not disabled the counter outputs may cause erratic system behavior 5 CALIBRATION PROCEDURES This chapter contains calibration procedures for the A D converter input voltage range the A D converter gain and the D A converter output voltage range The offset and full scale performance of the ADA2100 A D and D A converters are factory calibrated according to the specifications that were given when your order was placed The gain circuitry is also factory calibrated before the board is shipped The following procedure allows you to quickly verify the accuracy of these circuits This procedure should be done approximately every six months whenever inaccurate readings are suspected or whenever the voltage ranges are changed Calibration is performed with a properly configured ADA2100 installed in the PC Apply power to the computer and allow the ADA2100 circuitry to stabilize for 15 minutes Required Equi The following equipment is required for calibration Precision Voltage Sour
100. r board you wish to change the voltage reference for the analog outputs you must change the IC in location U15 Replace the IC with PMI REFO2 or equivalent to set up a 5 volt reference or PMI REF 01 to set up a 10 volt reference The analog output channels can be independently configured for unipolar or bipolar output ranges Jumpers installed on header connector P10 select the range desired for each output Both outputs are factory set to the same polarity as that specified for the A D inputs Chapter 3 Jumper Settings details how to change the polarity settings Note that only one jumper should be installed for each channel Whenever the voltage range or polarity is changed the D A converter should be recalibrated as described in Chapter 5 Calibration Procedures Loading the D A Converter Data Each D A channel has two eight bit internal input registers which receive the data for the D A conversion The channels are programmed independently by writing data to these registers The D A converters used on the ADA2100 board have a resolution of 12 bits Two write operations are required to load the 12 bit data field into these registers One register loads the least significant byte of the data field and the other register loads the most significant byte of the data field Each byte contains bits 0 through 7 with bit 0 being the least significant bit and bit 7 being the most significant bit in the byte Data bits DBO through DB7 are loaded i
101. r setting on PS LabTech SW IT LABTECH Software Interrupt This sets the software interrupt address where LABTECH NOTEBOOK s labLINX driver is installed The factory setting is 60 This setting can be ignored when running SIGNAL MATH A D Parameters Six A D board parameters are listed resolution number of channels active DMA channel gain loss and input voltage polarity End of Convert Timer Counter Interrupt Channel Interrupt Channel Base Address Software Interrupt Address A D DMA D A DMA Channel Channel Select Select External Gain External Gain amp Loss amp Loss X Bipolar A D Unipolar Bipolar Select D A Unipolar Bipolar Select Fig D 5 ADAINST EXE Screen D 5 Resolution and number of channels are fixed by the program for your board The DMA channel number block is not valid on the ADA2100 and should be left blank The next two blocks gain and loss are provided so that you can make adjustments for external gain or loss other than the programmable gain settings available on the board If your input signal is externally attenuated then you can adjust for this by setting a value other than 1 for loss If you have an external gain factor then you can adjust for this condition Numbers must be entered as whole decimal values The factory default setting for gain and loss is 1 For a bipolar input range an X should be placed before Bipolar on the screen default setting
102. s CLK input TRIGGER a rising edge of Counter s GATE in put COUNTER LOADING the transfer of a count from the CR to the CE refer to the Functional Descrip tion MODE 0 INTERRUPT ON TERMINAL COUNT Mode 0 is typically used for event counting After the Control Word is written OUT is initially low and will remain low until the Counter reaches zero OUT then goes high and remains high until a new count or a new Mode 0 Control Word is written into the Coun ter GATE 1 enables counting GATE 0 disables counting GATE has no effect on OUT After the Contro Word and initial count are written to a Counter the initial count will be loaded on the next CLK pulse This CLK pulse does not decrement the count so for an initial count of N OUT does not go high until N 1 CLK pulses after the initial count is written if a new count is written to the Counter it will be loaded on the next CLK pulse and counting will con tinue from the new count If a two byte count is writ ten the following happens 1 Writing the first byte disables counting OUT is set low immediately no clock pulse required 2 Writing the second byte allows the new count to be loaded on the next CLK pulse 3 91 This allows the counting sequence to be synchroniz ed by software Again OUT does not go high until N 1 CLK pulses after the new count of is written If an initial count is written while GATE 0 it will still be loaded on
103. scription Pin Number Symbol Dip PLCC Name and Function 1 4 PORT A PINS 0 3 Lower nibble of an 8 bit data output latch buffer and an 8 bit data input latch 5 READ CONTROL This input is low during CPU read operations M SELECT A low this input enables the 82C55A to respond to RD and WR signals RD and WR are ignored otherwise GND RR 1 0 ADDRESS These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers Ay Ao RD WA CS input Operation Read Pota DataBus o PotB Databus 0 Porc DataBus Petit 3 0 Control Word Data Bus 9 0 1 9 0 DaaBus Pona Lo Li o DaaBus Ponc Li 1 I s o o DataBus Controt x x 1 pataBus 3 state x x patabus 3 state PORT C PINS 4 7 Upper nibble of an 8 bit data output latch buffer and an 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports 4 10 13 11 13 15 VO A and B 14 17 16 19 PORT C PINS 0 3 Lower nibble of Port 7 18 25 20 22 YO
104. ss Header Connector P3 Programmable Interval Timer PIT I O Header Connector P5 and P7 Interrupt Header Connectors P6 End of Convert EOC Monitor Header Connector P9 A D Converter Voltage Range Header Connector P10 D A Converter Voltage Range Header Connector TR B OTR MIR IBSPP REP y m Un Tu E T DS 100 3 o je AOUT2 c 8 RESA m ts DIFFERENTIAL E EX Bed AUT Inc 3 C18 23 uss We pm 8 7 g 27027 P6 XTAL PC7 gy POL api 023 EGO Fig 3 1 ADA2100 Board Layout 3 1 S1 Analog Input Signal Type DIP Switch DIP switch 81 shown in Figure 3 2 configures the multiplexer for single ended or differential inputs and selects a unipolar or bipolar input voltage range The first three switches on S1 operate as a group When these are in the UP position the multiplexer is configured for single ended inputs when they are in the DOWN position the multiplexer is configured for differential inputs Note that these three switches must all be set to the same position UP or DOWN for the multiplexer to function properly The remaining switch 51 4 controls the input voltage polarity When this switch is in the UP position the input voltage range is unipolar when it is in the DOWN position the voltage range is bipolar This switch coupled with the voltage range selection set on header connector P9 determines the
105. ssion Chapter 3 Digital 16 1 O Lines from PPI Software controllable See Programming the PPI Chapter 4 and demo disk Programmable Inverval Timer PIT Circuitry Modes Software controllable See Programming the PIT Chapter 4 and demo disk Configuration Clock Input 5 MHz Gate Input 5 V Clock Output COO to P8 See P3 discussion Chapter 3 Interrupts Disabled See P5 and P7 discussions Chapter 3 and Interrupt Considerations Chapter 4 On PADAS 00 5 AOUT AOUT2 COR DIFFERENTIAL gt C 22 a a Inc y 28 j m IRO6 ros ili OUTO OUT2 Fig 1 1 ADA2100 Board Layout The functions which you can control through hardware are Base I O address Analog input channel type Analog input channel voltage range and polarity End of convert monitor Analog output voltage range and polarity PIT timer counters hardware and software Interrupts The functions which you can control through software are Analog input channel selection Analog input gain selection Digital I O PIT timer counters software and hardware Board initialization Setting the Base I O Address Starting with the base I O address BA the ADA2100 uses 24 consecutive address locations in your computer s I O space Table 1 2 lists the I O map for the ADA2100 Itis important t
106. ssssssesssnnssnonnnnnnsnnensnonsonensnannnnnesnnensnseensennssenesnenn 1 8 Setting the Input 1 9 Taking an A D Reading een 1 9 Controlling the D A Converter 2 1 11 Loading the D A Converter Data 12204441 40 42 4 1 Output Voltage Range and 0 1 12 CHAPTER 2 FUNCTIONAL DESCRIPTION Analog to Digital Conversion 2 1 h yes P 2 1 Gai Control Circ liry tert 2 2 Sample and Hold Circuitry MED 2 2 A A RN 2 2 Digital to Analog Conversion Circuitry eese eene einer en eene eene nente nnn ennae 2 3 Converter uses p 2 3 Output Amplifiers 2 3 Programmable Peripheral 2 3 Programmable Interval Timer PIT eoe eel Nene edu 24 CHAPTER 3 JUMPER SETTINGS S1 Analog Input Signal DIP 3 2 P2 Base I O Address Header esee eee eere 3
107. t Voltage Range and Resolution The voltage range and bit weight resolution of the analog outputs depend on the reference IC used and whether the channel is set up for unipolar or bipolar outputs The reference IC can be 5 or 10 volts for both channels depending on the IC type installed on the board Each channel can be individually controlled to have a unipolar or bipolar output depending on the setting of the jumpers on header connector P10 The reference voltage is customer specified when ordering and the output default setting for both channels is the same polarity as that specified for the A D converter The possible ranges and their corresponding bit weights are Range Bit Weight 0 to 4 9988 V 1 22 mV 0 to 9 9976 V 2 44 mV 4 9976 to 45 0000 V 2 44 mV 9 9951 to 10 0000 V 4 88 mV The data written to each pair of D A channel input registers represents a 12 bit digital value of the desired output voltage When the output is unipolar a data value of zero corresponds to zero volts and a full scale value all ones corresponds to the positive full scale voltage either 4 9988 volts or 9 9976 volts Intermediate voltage values are determined by multiplying the D A data by the appropriate bit weight 1 22 millivolts or 2 44 millivolts In bipolar operation the direction of the voltage changes from positive to negative as the data value increases data value of zero corresponds to the positive full scale output voltage 45 0000 volts or
108. table are in millivolts Table 5 3 D A Converter Bit Weights Unipolar MN Ideal Output Voltage millivolts D A Bit Weight 0 to 5 Volts 0 to 10 Volts 4095 full scale output 4998 8 9997 6 2048 2500 0 5000 0 1024 1250 0 2500 0 512 625 00 1250 0 256 312 50 625 00 128 156 250 312 50 64 78 125 156 250 32 39 063 78 125 19 5313 39 063 9 7656 19 5313 4 8828 9 7656 24414 4 8828 24414 0 0000 Bipolar Calibration Calibration of the D A outputs when configured for bipolar operation involves both a mid scale adjustment and a full scale adjustment for each output channel The trimpots associated with each adjustment and the analog output P8 pin assignments for measuring the output voltage are Output Mid Scale Full Scale P8 Pin Assignment Trimpot Trimpot AOUTI TR9 TR10 19 SIGNAL 20 GND AOUT2 TR8 TR11 21 SIGNAL 22 GND Program the D A converter to output a mid scale voltage by writing X800 to base I O address locations BA 8 and BA 9 for AOUT1 and BA A and BA B for AOUT2 Use the digital voltmeter to monitor the output voltage present between the appropriate P8 signal and ground pins Adjust the appropriate trimpot so that the output voltage is zero volts Next calibrate the full scale voltage output For full scale calibration program the D A converter to output a full scale voltage by writing to base I O address locations BA 8 and BA 9 for AOUTI and BA A and BA B for AOUT Use the digital
109. talled in the factory set position for EOC monitoring through PA7 P6 PC7 PA7 Fig 3 7 EOC Monitor Header Connector P6 3 5 P9 A D Converter Voltage Range Header Connector Header connector P9 shown in Figure 3 8 is used to select the analog input voltage range of the A D converter A jumper is installed vertically across the pins marked 10V to support a 10 volt range 0 to 10 volts or 5 to 5 volts or across the pins marked 20V to support a 20 volt range 10 to 10 volts The setting of this jumper coupled with the setting of DIP switch S1 4 which selects a unipolar or a bipolar range determines the input voltage range of the A D converter P9 is configured at the factory according to the customer s specifications for the input voltage range The valid settings of P9 and 51 4 are summarized in the table below Range P9 Setting S14 Setting 5 to 5 volts 10V right DOWN bipolar 0 to 10 volts 10V right UP unipolar 10 to 10 volts 20V left DOWN bipolar P9 N 2 2 Fig 3 8 A D Converter Voltage Range Header Connector P9 P10 D A Converter Voltage Range Header Connector Header connector P10 shown in Figure 3 9 is used to select the output voltage polarity of each of the two D A converter channels AOUT1 and AOUT2 Each channel can be independently configured as a unipolar output or a bipolar output To select the polarity for each channel install a jumper verti
110. te current state AND FO 3 Logically OR the current state with the desired channel number minus 1 current state current state OR channel 1 4 Write it back out to port B out base address 1 current state A BASIC program to select channel 2 is 100 BASE_ADDRESS 768 110 CHANNEL 2 120 STATUS INP BASE ADDRESS 1 130 STATUS STATUS AND amp HFO 140 STATUS STATUS OR CHANNEL 1 150 OUT BASE_ADDRESS 1 STATUS 1 8 Setting the Input Gai The gain is set by writing to the upper four bits of B at BA 1 The bit pattern foreach of the five gain values supported by the hardware are 0000 gain of 1 0001 gain of 2 0010 gain of 4 0100 gain of 8 1000 gain of 16 It is recommended that no other bit patterns be used when setting the gain The general algorithm for setting the gain is 1 Read the current state of port B current_state inp base_address 1 2 Preserve the lower four bits since they contain channel information current_state current_state AND 0F 3 Logically OR the current_state with a bit pattern that activates the desired gain current_state current_state OR gain bit pattern 1x bit pattern 0 2x bit pattern 16 4x bit pattern 32 8x bit pattern 64 16x bit pattern 128 4 Write the current_state back to port B base_address 1 current_state A BASIC program to set a gain of 2 is 100 BASE_ADDRESS 768 110 GAIN 2 120 STATUS I
111. the count value will not reflect the new count just written The operation of Null Count is shown in Figure 12 Command D Dg Ds D4 D3 D2 Di Read back count and status of Counter 0 Description THIS ACTION A Write to the control word register 11 B Write to the count register 121 C New count is loaded CAUSES Null count 1 Null count 1 into CE CR CE Null count 0 1 Only the counter specified by the control word will have its null count set to 1 Nuil count bits of other counters are unaffected 2 If the counter is programmed for two byte counts least significant byte then most significant byte null count goes to 1 when the second byte is written Figure 12 Null Count Operation If multiple status latch operations of the counter s are performed without reading the status all but the first are ignored i e the status that will be read is the status of the counter at the time the first status read back command was issued Both count and status of the selected counter s may be latched simultaneously by setting both COUNT and STATUS bits D5 D4 0 This is func tionally the same as issuing two separate read back commands at once and the above discussions ap ply here also Specifically if multiple count and or status read back commands are issued to the same counter s without any intervening reads all but the first are ignored This is illustrated in Figure 13 If both count a
112. tructions for board calibration Appendix A ADA2100 Specifications contains a complete listing of board specifications Appendix B Connector Pin Assignments contains the pinouts of the external I O connector Appendix C Component Data Sheets contains manufacturers data sheets for major board components Appendix D Configuring the ADA2100 for SIGNAL MATH contains information about setting board jumpers and and initializing the board to run the SIGNAL MATH acquisition and analysis program Appendix E Configuring the ADA2100 for ATLANTIS contains information about setting board jumpers to run the ATLANTIS data acquisition and real time monitoring program Appendix F Warranty contains board warranty information When You Need Help When you are working with the ADA2100 interface board this manual and the demo software included in your package will provide sufficient information to properly control all of the board s functions If however after carefully reviewing the manual you are unable to obtain proper responses from the board Real Time Devices technical staff is ready to assist you For assistance call 814 234 8087 during regular business hours eastern standard time or eastern daylight time or send a FAX requesting assistance to 814 234 5218 Be sure to include your company s name your name your telephone number and a brief description of the problem i 2 CHAPTER 1 QUICK
113. ts 2 4414 mV bit 2 49999 volts 1 10 The input voltage range and polarity are factory set according to customer specifications when ordering the board If after receiving your board you wish to change the input voltage see Chapter 3 Jumper Settings Whenever the voltage polarity is changed unipolar to bipolar or vice versa the A D converter should be recalibrated as described in Chapter 5 Calibration Procedures Note that eight bit A D conversions can also be performed This is accomplished by writing to I O location BA 5 or 7 While an eight bit conversion has lower resolution than the 12 bit conversion it is performed much more rapidly in about 13 microseconds A 12 bitconversion takes about 20 microseconds Therefore when speed is essential you can use the eight bit conversion capability Controlling the D A Converter The two analog output channels channel AOUTI and channel AOUT can be independently programmed by writing to internal registers of the AD7537 D A converter The outputs can be set to one of four possible output voltage ranges two unipolar and two bipolar These ranges are 0 to 5 volts 0 to 10 volts 5 volts or 10 volts The range of the full scale output voltage is controlled by the factory installed voltage reference at IC location U15 The voltage range is specified when ordering the board REF 01 provides a 10 volt reference and REF 02 provides a 5 volt reference If after receiving you
114. when read but other counters remain latched until they are read If multiple count read back commands are issued to the same counter without reading the intel 82C54 count all but the first are ignored the count which will be read is the count at the time the first read back command was issued The read back command may also be used to latch status information of selected counter s by setting STATUS bit D4 0 Status must be latched to be read status of a counter is accessed by a read from that counter The counter status format is shown in Figure 11 Bits D5 through DO contain the counter s programmed Mode exactly as written in the last Mode Control Word OUTPUT bit D7 contains the current state of the OUT pin This allows the user to monitor the counter s output via software possibly eliminating some hardware from a system D7 De Ds Dg D2 Di Do NULL f D7 t Out Pin is 1 0 Out Pin is O Dg 1 Null count 0 Count available for reading Ds Do Counter Programmed Mode See Figure 7 Figure 11 Status Byte NULL COUNT bit D6 indicates when the last count written to the counter register CR has been loaded into the counting element CE The exact time this happens depends on the Mode of the counter and is described in the Mode Definitions but until the count is loaded into the counting element CE it can t be read from the counter If the count is latched or read before this time
115. wing WR of a new count value COUNTER New counts are loaded and Counters are decre mented on the falling edge of CLK The largest possible initial count is 0 this is equiva lent to 216 for binary counting and 104 for BCD counting The Counter does not stop when it reaches zero In Modes 0 1 4 and 5 the Counter wraps around to the highest count either FFFF hex for binary count ing or 9999 for BCD counting and continues count ing Modes 2 and 3 are periodic the Counter reloads itself with the initial count and continues counting from there 3 95 intel 82054 ABSOLUTE MAXIMUM RATINGS Notice Stresses above those listed under Abso lute Maximum Ratings may cause permanent dam Ambient Temperature Under Bias 0 C to 70 C age to the device This is a stress rating only and Storage Temperature 65 to 150 C functional operation of the device at these or any Supply Voltage 0 5to 8 0V other conditions above those indicated in the opera Operating Voltage 4Vto 7V tional sections of this specification is not implied Ex Voltage on any GND 2Vto 6 5V to absolute maximum rating conditions for Voltage on any Output GND 0 5V to 0 5V extended periods may affect device reliability Power Dissipation 1 Watt D C CHARACTERISTICS Ta 0 C to 70 C Vec 5V 10 GND 0V TA 4

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