User Manual
Contents
1. LAYER J28 J22 J24 J26 J28 J38 J32 J34 ISSUE LI d d d d Pd Pd P P d P P P P Pod D1 D3 D5 D7 D9 D11 D13 D15 J18 J21 J23 J28 J27 J28 J31 J33 PL1 PLS 1 E E d o d oT LB DL POP RB bd dod b Eu ase vss Sw3 VOD m di vss swi voo D D2 D4 D6 OB D1B D12 D14 R44 Hes DITHA TWOC has R24 MULA A DITH1 nm ow ob n o ro 2m or mf mu PAG DITH2 TE c t ee et POT ee ee ee E gt wrt R47 DVSS MUL2 ions TP13 NSHAPE n48 i nd Men CKSEL ME R26 DVDD gt o sonont oono NFDS ND zz SHUF 1 DNHOSOKBORNRRRDODHODBOKOHAD T R55 t c Proc PG PC C C rfc R28 TEST IL PLZ 1 R28 vss VDD vss BESET nee TP15 TES si osca sws osc1 vss rai TER B UO Meas EST W2 VOR m7 7 ma2 VDD T TP7 LJ ros i os R43 12 TPB 1999 R35 vss lesa Ui TP9 Eod vai FUJITSU MICROELECTRONICS E HE Les EUROPE n3 ST6 sTe vss R55 CVSS BL Had R54 TP24 Jie lou1 MB8686802. EINER ia m 32 m T ise Js 35 ISSUE L doxes Te dX Qd Ww pod ooa xo Di 53 55 D7 Da Dri 013 Dis Bid 319 321 323 325 327 329 331 333 PL3 1 Lob I a ee hi x 1 SW1 E gs wise f Y SW3 vss sm voo DB B2 54 Ds 58 DTB D12 D14 Raa R23 one woe nz4 Ma ovss ve m c ERRE PL1 eis m PL3 me bare Bon egi me SSIBSSPISPSSISSSPS 1 ass Ber sur PEPPER EEE ES PE Ee BE ad TEST PR PL2 Ce swi SW2 V55 RESET SW4 TP15 Sus Tes Reif TPIS B dn von mr 1 SW5 PL ma T2 ser TPB 2 E 1999 vss u Tra c22 vm FUJITSU MICROELECTRONICS e na Ls EUROPE S a 55 me ryss CLK Ja MB85252 DAC TEST CARD 1 e TP24 uL deur 7 Clock Out Res cess CLK _ ISSUE 3 5 i O71 CVDD mes 3m Ji 1 v ces p ES VREF Fe Ba pa BB m Lal us Win c6 1 Se de no Css ake nz m RVDD m E re A 317 su RREF Teze mi De gt QUE ls TP25 TP26 T mor 17 314 IN pew hues AVES AVBD ge HE 7 LJ mioa CELKEM ll sra vop CMRR _ 7E zase 7 E M m ne SESE 3 ee a r 198 lig 3 Clock In Power Cavo s lg ue gt 515 ca Avoo lis LK7 T XIN XOUT y LPSAR IDUT sta C IDUTB oed B 5V cs aa DIFF Te pe ls Gut j il TP3 kz EN SES y5 oe m m EE EE aw aw lt gt Differential Out Figure 2 2 Evaluation Board Comp
3. Appendix C Connector Pin Functions Appendix D Prototype Area 002 2c eee eee eee eee Copyright 1999 Fujitsu Microelectronics Europe GmbH co FUJITSU Page 3 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board This page left intentionally blank Page 4 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board 1 Overview The DK86060 3 evaluation board allows users to evaluate and demonstrate the different operational modes of the MB86060 16 bit Interpolating DAC The evaluation board consists of a MB86060 device with support circuitry for single ended or differential analog output interfaces a clock input interface and a clock output interface This will enable simple connection of measurement equipment For convenience customer evaluation boards have been configured using soldered zero ohm links for transformer coupled differential output only The CMOS input data interface has a 40 way IDC header for connection via a flat ribbon cable Separate SMA SMB connectors for individual data bit connections are also available but not normally fitted SMA not recommended due to insufficient space to rotate the connectors body The setup of the device is controlled by on board DIP switches but these
4. 1 S om P 1 IN P4 D E D P IN FB P3 P2 FB AVSS PIZ PIBAPP vss 5 2V PB PS 5v lt gt un UD un TU Or MB86806598 VERSION 1 2 3 4 5 6 7 8 9 Figure B2 Component Overlay For Layer 4 Solder Side Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 21 of 28 co FUJITSU Appendix C Connector Pin Functions Page 22 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board Table C1 Data Connector PL2 Pin Functions Pin Function 1 Data Bit 15 MSB 3 Data Bit 14 5 Data Bit 13 7 Data Bit 12 9 Data Bit 11 11 Data Bit 10 13 Data Bit 9 15 Data Bit 8 17 Data Bit 7 19 Data Bit 6 21 Data Bit 5 23 Data Bit 4 25 Data Bit 3 27 Data Bit 2 29 Data Bit 1 31 Data Bit 0 LSB 33 XIN 35 XOUT 37 Not Used 39 Not Used 2 to 40 Even num bers only Data Ground DVSS Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board Table C2 Control Connector PL1 Pin Functions Pin Function 1 to 13 Digital Ground VSS 14 DITHO 15 DITH1 16 DITH2 17t SOUT O P 18 OVER O P 19 FILTS 20 FILTF 21 SHUFO 22 SHUF1
5. Not Linked LK8 CLK OUT biasing enabled Linked CLK OUT biasing disabled Not Linked Note Bold type indicates default jumper settings t Standard Evaluation Kits are not configured to use the optional supply LK1 and LK7 are not used i Standard Evaluation Kits are configured for Differential output LK2 is not used Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 11 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board This page left intentionally blank Page 12 of 28 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board 3 Getting Started This Chapter documents the basic steps to powering up and starting to use the DK86060 3 Evaluation Board Component references may be cross referenced with the component overlay in Appendix B Step 1 Configure the board The data input format must be configured to either Offset binary or 2 s Compliment Use configuration switch SW3 1 to select The device control signals should be set to the default conditions shown in Section 2 2 Use configuration switches SW1 SW2 and SW3 to select Jumper links LK3 to LK6 inclusive and LK8 should be Not linked Switch SW5 should be set to position A Step 2 Connect data input amp analog output connectors to the board The input data sh
6. Tokyo Japan Fujitsu Microelectronics Europe GmbH and Fujitsu Microelectronics Inc USA All Rights Reserved The information contained in this document has been carefully checked and is believed to be entirely reliable However Fujitsu and its subsidiaries assume no responsibility for inaccuracies The information contained in this document does not convey any license under the copyrights patent rights or trademarks claimed and owned by Fujitsu Page 2 of 28 Fujitsu Limited and its subsidiaries reserve the right to change products or specifications without notice No part of this publication may be copied or reproduced in any form or by any means or transferred to any third party without the prior consent of Fujitsu Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board 1 OVErVIEW D 2 Evaluation Board ii een sx ee 21 Power Supply 2352 2r eR DES ED EE sacs 2 2 Board And Interface Controls oooo CURES A dea da mad aa med ohm ad mis 2 2 2 Jumper Links lille elles 3 Getting Started 2 incio a a a ect i c Du E c CN 4 TWeSUNG curra edad Oe acea Appendix A Evaluation Board Circuit Diagrams A 1 Components Not Fitted to the PCB A 2 Changes to the PCB Schematics Appendix B Component Overlays
7. application For convenience the board has been configured using soldered zero ohm links as a transformer coupled differential output To enable single ended outputs changes to the soldered zero ohm links would be required For rise fall time tests the transformer coupled output should not be used since the transformer response will limit the dV dt The DAC current switches are designed to give the best possible differential performance at the expense of some single ended performance so there is a noticeable difference between the two configurations The revised analog output circuit uses an additional transmission line transformer to improve rejection of common mode distortion at the DAC output If a spectrum analyser is used to measure the output spectrum it should have a very good noise and distortion for example HP8562E or R amp S FSEA30 In addition the input attenuator setting should be chosen such that input mixer distortion does not limit the measurements e g 30dB RF attenuation This implies that narrow resolution bandwidths and or averaging are required to obtain low enough measurement noise floor Page 14 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board Appendix A Evaluation Board Circuit Diagrams Appendix A shows the circuit diagrams of the DK86060 3 evaluation board Note that these diagrams are
8. controls can be accessed and overridden via two 25 way male D type connectors if remote control is required The evaluation board has been designed to address requirements of both automatic and conventional bench testing Standard evaluation boards feature a simplified build state where certain components or connectors are omitted These omissions are documented in Appendix A with the evaluation board schematics This User Manual is intended to document the DK86060 3 Development Kit PCB titled MB86060 DAC TEST CARD ISSUE 3 only Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 5 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU 2 Evaluation Board DK86060 3 16 bit Interpolating DAC Evaluation Board 2 1 Power Supply The DK86060 3 evaluation board requires a 3 3V supply and a number of other low voltage DC supplies depending upon build configuration marked T A cable mounting socket suitable for mating with the PCB mounted power plug is supplied with the development board Additional sockets type Weidmuller BL3 6 16 may be obtained from RS Components http rswww com Stock no 216 2683 The power should be connected to the board via this connector as shown in Figure 2 1 Flexible cable of 16 28 AWG 0 5 1 5mm should be used The format of the power connector is common across Fujitsu s DAC Development Kit range The result is that there are some un necessary supplies marked These supp
9. linked to any other area of the PCB The prototype area layout is shown in Figure D1 Layer 2 would typically be used as the ground plane and layer 3 as the power plane with signals routed on layer 1 However the choice in the prototype area is free as the planes are entirely separate to the rest of the PCB O JO O O O O O O O O JO O O JO O O O O JO O ollol ol ollollollo lollo lol ollo lJollollolloljlolo llollo Layer 2 E M M U M eenen 1 E E E E E Layer 3 E E El El El El El Al A A A A A O O E ll NT ollo lolollollollo lollo lol o lo o lo ollol lol oj o o O opio opio ojo opio ojo ojo ojo ojo O O O O JO O O O O O O O O JO O O JO O O O O JO O olollo lo lo lollololollo ollollolollollo o ollo lo Layer 2 BBB El ll ll Al Al A A A A A A Al A AA Layer 3 RENI DI DT ll ll ll ll A D E I E E E E I olollo lo llo lollo ollol o lollo lo lo o lollo O ojo opio ojo opio ojo ojo opio opio Figure D1 Prototype Area Layout Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 25 of 28 Novembe
10. 23t TEST 24 OSCO 25 OSC1 t These pins are for factory test purposes only Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 23 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board Table C3 Control Connector PL3 Pin Functions Pin Function 1 to 13 Digital Ground VSS 141 Test Point 8 151 Test Point 7 161 Test Point 6 171 Test Point 5 18 RESETB 19 CKSEL 20 NSHAPE 21 LOCK O P 22 MUL2 23 MUL1 24 MULO 25 TWOC T These pins are connected to test points so that connections to the prototype area can be made via the control connector Page 24 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board Appendix D Prototype Area A prototype area has been introduced into the DK86060 3 development kit PCB This area takes the form of a matrix of pads with plated through holes on a 2 54mm pitch The pads are made square to allow for 0805 format surface mount devices to be fitted between adjacent pads The matrix area has four rows individually linked together to act as power rails These rows are arranged as two pairs with connections to the internal planes layers 2 and 3 made to each of the rows The internal plane regions only occupy the prototype area and are not
11. 90 co FUJITSU 4 Testing DK86060 3 16 bit Interpolating DAC Evaluation Board This section provides a brief introduction to testing with the DK86060 3 16 bit Interpolating DAC Evaluation Board MB86060 incorporates a 12 bit 400MSa s digital to analog converter core with a 16 bit interpolation filtering front end designed to give excellent SFDR performance The use of novel techniques for the converter architecture have allowed high speed operation consistent with BiCMOS or bipolar devices but with the low power consistent with CMOS In certain applications it is now possible to consider using the MB86060 s DAC core at a full 400MSa s DAC conversion rate even though the generated signal band may only be for example up to 40MHz or less Although in theory a 100MSa s converter would be sufficient to reproduce this desired signal band according to Nyquist converter performance will tend to limit due to step size and sinx x roll off as a result of the converters sample amp hold output stage 400MSa s operation significantly reduces effects due to both of these sinx x roll off is reduced from 4dB to 0 22dB and the increased oversampling DAC conversion rate signal rate reduces step sizes to give a direct improvement in spurious performance These issues should be considered when testing the MB86060 and measurements should be obtained at different conversion rates to establish the most appropriate operating conditions for the target
12. DAC TEST CARD ASE 1 m He clk TP23 aiii ISSUE 3 ia JAS 1 w2 CVDD R1 6 T3 Ji 1 m A3 a5 A c24 acil 5 2V VREF ur RB A 8 5 Lea Je a TPI zu 5 R7 ga sT1 TP2 4 TS i il beds J12 J eee O ALI p ss CLKB V R11 CLK 317 sT2 PREF Teee R12 C rsz 118 IN TP25 TP25 314 Ei lua AVSS AVDD yo Ne ee SE ES R198 CLKCM VDD a R96 R97 iE CMRR j S Ig amp T d LK1B 2 amp n ao 2 3m c2 CVDD ad LKIC jv J35 336 n Bure 238 E RYDD 32 ia LK1D i B AVDO 517 me n T4 XIN XOUT y Hesaan sTa OUTB IOUT J6 R18 C14 J18 5V Es ERN DIFF m lis Gut Tez LK2 e ins vaias 12V __ seout ss _ Sg as n cun n cu lt gt Figure B1 Component Overlay For Layer 1 Component Side Page 20 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board co FUJITSU DVSS DVDD VSS vss VOD VDD R58 vss C26 C25 ASE c17 EN C16 1 vss CUB C15 R2 Bom R38 has i cial Es R3 R5 N Smmms DOUSSEN R183 R1B1 a N E32 RATAS RVSS BD RVDD RIG Jar AVDD AVSS c30 R188 tars 2V P7 P5 AVDD avss pii m PS avss mE
13. Qo User Manual FUJITSU November 1999 DK86060 3 Version 3 2 16 bit Interpolating DAC Evaluation Board rwemsisepactum_1 4190 Fujitsus DK86060 3 16 bit Interpolating DAC Evaluation Board provides a simple and effective means of evaluating the MB86060 16 bit Interpolating DAC This enables faster device evaluation without incurring the time and cost penalties of in house PCB design and manufacture EVALUATION BOARD DAC device A selectable single ended or transformer coupled differential analog output interface is provided on board to source 16 bit data is input via a 40way IDC header or optional SMA SMB connectors The MB86060 device is a single 16 bit DAC enclosed in a 80 pin LQFP package with a 0 5mm pin pitch Features 16 bit data input via a choice of connectors Transformer coupled differential output via BNC amp SMA SMB Internal oscillator with optional on board crystal Transformer coupled RF clock input via BNC amp SMA SMB Requires DC power supply of 3 3V Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 1 of 28 co FUJITSU A November 1999 Version 3 2 FME MS SFDAC1 UM_1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board CAUTION ELECTROSTATIC DISCHARGE SENSITIVE DEVICE High electrostatic charges can accumulate in the human body and discharge without detection Ensure proper ESD procedures are followed when handling this device Copyright O 1999 Fujitsu Limited
14. RESET mode B Device in normal operating mode A Note SW1 2 amp 3 may appear to malfunction if pressure is placed on the slider when in either the left or right position In this case the DAC control pin will be floating Page 10 of 28 Copyright O 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board 2 2 2 Jumper Links Table 6 Jumper Links co FUJITSU Link Name Mode Function Setting LK1AT Optional supply used for VDD 1 to 2 linked SV Common supply used for VDD 2 to 3 linked LK1BT Optional supply used for CVDD 1 to 2 linked no Common supply used for CVDD 2 to 3 linked LK1CT Optional supply used for RVDD 1 to 2 linked ene Common supply used for RVDD 2 to 3 linked LK1DT Optional supply used for AVDD 1 to 2 linked NI Common supply used for AVDD 2 to 3 linked LK2t Select single ended output Linked ERU Select differential output Not linked LK3 Centre tap of T1 Pin 5 linked to AVSS Linked ee Centre tap of T1 Pin 5 decoupled toAVSS Not linked LK4 DIFF OUT Ground linked to AVSS Linked DIFF OUT Ground floating Not Linked LK5 CLK OUT Ground linked to VSS Linked CLK OUT Ground floating Not Linked LK6 CLK IN Ground linked to CVSS Linked CLK IN Ground floating Not Linked LK7T Power supply ripple rejection disabled Linked FSRR Power supply ripple rejection enabled
15. er 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board R6 1K RVDD L TCO4BCZM RVSS mncro omcro nr n oco zxm o Ocoo oo lt and R v S S T E S T R48 10K l R49 10K LE EE LE LE G 6 4 3 1 fo LA GE ca Ca U EE ETE i ai ai ai aicd 8 Copyright 1999 Fujitsu Microelectronics Europe GmbH 160R co FUJITSU CLA FUJITSU MICROELECTRONICS EUROPE NETWORK HOUSE NORREYS DRIVE MAIDENHEAD BERKSHIRE SL6 4FT O O O Title e Document Number V Date September 14 1999 Sheet 1 of 1 Page 17 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU A 1 Components Not Fitted to the PCB DK86060 3 16 bit Interpolating DAC Evaluation Board Table A1 Components Not Fitted Reference Value Description LK1a b c d Power supply selection jumper links LK2 Single ended output selection jumper link LK7 PSRR jumper link J2 to J6 J8 J10 J11 J13 SMA SMB connectors to J16 J18 to J36 J5 J9 BNC connectors D1 TCO4BCZM Reference diode RL1 RF103 12 Output selection relay X1 Crystal C2 150uF Optional power supply decoupling capacitor C14 C32 Analog output RC network capacitors C20 C21 22pF Crystal capacitors R1 OR Optional power supply PSRR series resistor R6 1K Reference current limit resistor R7 51R Reference series r
16. esistor R14 R16 OR Single ended output relay bypass resistors R18 OR CMRR jumper link bypass resistor R19 R109 Analog output RC network resistors R57 1M Crystal shunt resistor R63 R65 R67 R69 R71 OR Data input series resistors for SMA SMB connectors R73 R75 R77 R79 R81 R83 R85 R87 R89 R91 R93 R102 R104 51R Analog output termination resistors T4 Optional analog output circuit transformer Page 18 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM_1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board co FUJITSU A 2 Changes to the PCB Schematics Table A2 Schematic Changes Reference d New Value Description Value R100 51R Analog output RC network resistor C30 22pF Analog output RC network capacitor T1 a ADTT1 1 Mini Circuits 1 1 analog output transformer T1 b ADTL1 12 Mini Circuits transmission line transformer 1 lt L 6 ao To Output To DAC 3 Tib 4 Tia V 5 Figure A1 Replacement Schematic For T1 Pin Numbers Refer To T1 Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 19 of 28 co FUJITSU November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board Appendix B Component Overlays
17. for reference only and that some components fitted to the board may be of a different value to the schematics or not fitted at all Fujitsu has undertaken to document these changes where possible The schematic is divided over two pages for clarity Sheet 1 DAC support circuitry including analog output interfaces covers 2 pages Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 15 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board 1 9 R39 O OTP2 LK1D E OR O R38 E 5 2V O CVDD OEA OR D 2VS R D 2VF O DGND T D 3 3VF D 3 3VS 5 OPTS OPTF 3 3VS 5 3 3VF SGND 5 2VF 2VS 5V R6 1k 12V RVDD E RELAY TCO4BCZM RVSS Di m 51R C d R8 OR e Fo 1000 R9 qo Mil J amp Ei rd 7 zl 7 6 e e e Cag o o e 3 2 fi o 5 la s CAVSS RVBRSSFFAODVVNTVVDDE RRGVHHIISVSDS WDSIII J7 EEASUULLUEUDSCODSTT1 BNC FFPSFFTTBRB iG HHE 1 10FS S 21 5 RVSS T o RVDD E U AVDD Osco RI LS El osco S DOOR 4 T OSCi OSC1 AVDD AVSS IOUTB IOUTB AVSS AVDD OG NE APP GND jour i R53 R54 l SWS O sw4 R56 200R 200R ss 1PCO oZ C VSS TOK 75R 1 1 1 1 1 1 2 epppepen 11412 5 3 6 4 7 5 8 9 7 o 2 o 3 1 4 2 5 3 TP5 TP6 TP7 TP8 000000000000 PL3 DB25 CLKIN GND APP GND Je BNC APP GND Page 16 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH Novemb
18. ing SW2 1 2 Multiplier fastest mode VSS VSS OSCO 1 dido VDD VSS VSS VDD Multiplier slowest mode VDD VDD Table 3 Switch 3 Settings Switch Mode Function Setting SW3 1 Offset binary input data VSS TWOC 2 s Compliment input data VDD SW3 2 4 Clock multiplier bypass VSS VSS VSS MULO MUL 1 e MUL2 Clock multiplier x1 mode VDD VSS VSS Clock multiplier x2 mode VSS VDD VSS Clock multiplier x3 mode VDD VDD VSS Clock multiplier x4 mode VSS VSS VDD Clock multiplier x5 mode VDD VSS VDD Clock multiplier x6 mode VSS VDD VDD Clock multiplier x8 mode VDD VDD VDD SW3 5 Noise shaping disabled VSS NSHAPE Noise shaping enabled VDD SW3 6e t On board crystal VSS CKSEL External clock source VDD T Standard Evaluation Kits are not configured with an on board crystal Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 9 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board Table 4 Switch 4 Settings Switch Mode Function Setting SW3 1 amp SW4 Part Resett SW3 1 VSS Push to Reset Full Reset SW3 1 VDD Push to Reset t With SW3 1 set to Offset binary a Reset will not reset the Clock Multiplier or the Reference circuits i With SW3 1 set to 2 s compliment a Reset will reset the entire device Table 5 Switch 5 Settings Switch Mode Function Setting SW5 Device in forced
19. ly pins are connected to test points for convenience if the user requires extra supplies for the prototype area Cable Mounting PCB mounted Socket power header Standard Requirement m 5 2V t Data 2V Sense t a Data 2V Force i Data GND mad Data 3 3V Force Data 3 3V Sense Opt 3 3V Sense t n Opt 3 3V Force t mum 3 3V Sense xj a z pe E H 3 3V Force GND 2V Force f 2V Sense t 5V T 12V T Relay t Pin 16 Figure 2 1 Power Connections Page 6 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM_1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board co FUJITSU 2 2 Board And Interface Controls
20. onent Side Layout Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 7 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU 2 2 1 Switches DK86060 3 16 bit Interpolating DAC Evaluation Board There are several control switches on the evaluation board as shown in Figure 2 2 Switch idents are marked on the board silkscreen Table 1 Switch 1 Settings Switch Mode Function Setting SW1 1 3 Dither disabled VSS VSS VSS DITHO DITH1 DITH2 27 0 dBFS pk Dither amplitude VDD VSS VSS 21 0 dBFS pk Dither amplitude VSS VDD VSS 15 0 dBFS pk Dither amplitude VDD VDD VSS 9 0 dBFS pk Dither amplitude VSS VSS VDD 3 0 dBFs pk Dither amplitude VDD VSS VDD Factory use only VSS VDD VDD Factory use only VDD VDD VDD SW1 4 5 Disabled VSS VSS FILTS FILTF x2 Slow VDD VSS x2 Fast VSS VDD x4 VDD VDD SW1 6 7 Segment Shuffling disabled VSS VSS SHUFO SHUF1 Random every 4 cycles VDD VSS Random every 8 cycles VSS VDD Random every 16 cycles VDD VDD SW1 8 Factory use only VSS TEST Page 8 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM_1 4190 DK86060 3 16 bit Interpolating DAC Evaluation Board Table 2 Switch 2 Settings co FUJITSU Switch Mode Function Sett
21. ould be connected via the 40 way IDC header PL2 or if fitted the SMA SMB connectors J19 to J34 inclusive See Table C1 for the pin description of the IDC header The output is provided as a transformer coupled differential signal via a BNC connector Differential Output signal J7 504 source resistance The DAC is coupled to a single output connector using a transmission line and 1 1 balun transformer Signal swing is 0 5V with a high impedance load or 0 25V with an external 502 load For sinusoidal signals this corresponds to approximately 2dBm into a 509 external load Step 3 Connect clock The clock input is provided to the device through a transmission line transformer via a BNC connector RF clock J17 50Q input impedance The DAC is coupled to a single input connector using a transmission line transformer Sine wave or square wave input signals between 10dBm and 10dBm are acceptable depending on clock frequency and required output jitter phase noise Step 4 Connect power header to power supplies Ensure that the power supply is connected according to Figure 2 1 Connect the power header to the board and turn the power supply on Step 5 Press Reset Press the Reset button to ensure that the device is in the correct operating condition Press Reset every time a configuration change is made Copyright 1999 Fujitsu Microelectronics Europe GmbH Page 13 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 41
22. r 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board This page left intentionally blank Page 26 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH November 1999 Version 3 2 FME MS SFDAC1 UM 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board Notes Copyright O 1999 Fujitsu Microelectronics Europe GmbH Page 27 of 28 November 1999 Version 3 2 FME MS SFDAC1 UM_ 1 4190 co FUJITSU DK86060 3 16 bit Interpolating DAC Evaluation Board Worldwide Headquarters Japan Fujitsu Limited Asia Fujitsu Microelectronics Asia Pte Limited Tel 81 44 754 3753 1015 Kamikodanaka 4 1 1 Tel 65 281 0770 151 Lorong Chuan Fax 48144 754 3329 Nakahara ku Fax 65 281 0220 05 08 New Tech Park Kawasaki shi Singapore 556741 Kanagawa ken 211 88 Japan http www fujitsu co jp htip www fmap com sg USA Fujitsu Microelectronics Inc Eu rope Fujitsu Microlectronics Europe GmbH Tel 1408 922 9000 3545 North First Street Tel 49 6103 6900 Am Siebenstein 6 10 Fax 1 408 9229179 San Jose CA 95134 1804 fax 496103690122 D 63303 Dreieich Buchschlag USA Germany Tel 1 800 866 8608 Customer Response Center htip www fujitsu fme com Fax 1 408 9229179 Mon Fri 7am 5pm PST http www fujitsumicro com The contents of this document are subject to change without notice Customers are advised to consult with FUJITSU sales representatives before o
23. rdering The information and circuit diagrams in this document presented as examples of semiconductor device applications and are not intended to be incorporated in devices for actual use Also FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams FUJITSU semiconductor devices are intended for use in standard applications computers office automation and other office equipment industrial communications and measurement equipment personal or household devices etc CAUTION Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage or where extremely high levels of reliability are demanded such as aerospace systems atomic energy contro sea floor repeaters vehicle operating controls medical devices for life support etc are requested to consult with FUJITSU sales representatives before such use The company will not be responsible for damages arising from such use without prior approval Any semiconductor devices have inherently a certain rate of failure You must protect against injury damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy fire protection and prevention ofover current levels and other abnormal operating condition
24. s If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan the prior authorization by Japanese government should be required for export of those products from Japan FME MS SFDAC1 UM 1 4190 3 2 Page 28 of 28 Copyright 1999 Fujitsu Microelectronics Europe GmbH
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