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MB91F467BA/466BA/465BA/464BA preliminary datasheet

1. Co processor error trap 5 8 08 0x3DG 0x000FFFDC INTE instruction 9 09 0x3D8 0x000FFFD8 Instruction break 10 0 304 0x000FFFD4 Operand break trap 11 0B Ox3DO 0x000FFFDO Step trace trap gt 12 OG Ox3CC NMI interrupt tool 13 0D Ox3C8 0x000FFFC8 Undefined instruction 14 OE 0x3C4 0x000FFFC4 NMI request 15 fixed 0x3C0 External Interrupt 0 16 10 0x3BC 0 16 00 0 440 External Interrupt 1 17 11 0x3B8 0x000FFFB8 1 17 Page 101 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 External Interrupt 2 18 12 0 3 4 0x000FFFB4 2 18 ICR01 0x441 External Interrupt 3 19 13 0x3B0 0x000FFFBO 3 19 External Interrupt 4 20 14 20 ICR02 0x442 External Interrupt 5 21 15 0x3A8 0x000FFFA8 21 External Interrupt 6 22 16 0x3A4 0x000FFFA4 22 ICR03 0x443 External Interrupt 7 23 17 0x000FFFAO 23 External Interrupt 8 24 18 0x39G 0x000FFF9C ICR04 0x444 External Interrupt 9 25 19 0x398 0x000FFF98 External Interrupt 10 26 0 394 0x000FFF94 ICR05 0x445 External Interrupt 11 27 1B 0x390 0x000FFF90 External Interrupt 12 28 1C 0x38G 0x000FFF8C ICR06 0x446 External Interrupt 13 29 1D 0x388 0x000FFF8
2. 109 5 1 PASEO 109 6 2 I O Pins and their functions 111 6 2 1 MB91F467BA 466BA 465 464BA with MD 3 0 111 6 22 91 467 466BA 465BA 464BA with MD 3 1 116 63 aa eti AR GR 121 7 Electrical Characteristics 126 7 1 Absolute Maximum Ralingen 126 7 2 Operating Conditions 127 7 3 Converter Characteristics 129 Page of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 1 Overview The MB91F467BA 466BA 465BA 464BA are the body control flash MCU of the M91460 family The corresponding evaluation device is the MB91V460 1 1 Block Diagram FRTx8 ICU x 8 4 OCU x 8 4 32 KHz PPG x 16 8 PC x 2 R timer x 8 LIN UART 7 4 CAN x6 32 msq Core 1 8V Pre fetch 8KB INSTR DATA 10 3 3 5 0V a RTC ExtInt x 16 12 FLASH 467BA 1088 U DCnt x 2 0 NMI x1 466 832KB 465 544 Alarmx1 10bit ADC 522 464 416KB 16KB 3 BootROM
3. 001028 reserved do not use 70 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 004000 Direct mapped Instruction RAM 8kB cache 006000 reserved do not use 006FFCH FMCS RAN FMCR RAN FCHCR R W 4 01101000 0000 00 10000011 Flash Memory FMWT RW R W Cache 997094 11111111 11111111 000 Register FMAC R 007 0084 00000000 00000000 00000000 00000000 00700 eacheable 007010 0070149 reserved 007 MB91F467BA Boot ROM size is 4kB 0080001 OOBFF Cu Boot ROM instruction access is 1 waitcycle data access is 1 waitcycle 4 kB CTRLRO RW STATRO RW 2 00000000 00000001 00000000 00000000 Register R BTRO R W 00000000 00000000 00100011 00000001 T INTRO R TESTRO R W 00000000 00000000 00000000 X0000000 Page 71 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 R W 00C00Ch 00000000 00000000 CPSYNGO 2 Eom RW IF1CMSKO R W H 00000000 00000001 00000000 00000000 IF1MSK20 R W IF1MSK10 RW 00 014 41111111 11111111 411111
4. 00186 SGCRH RAN SGCRL RAN SGFR R W 0000 00 0 000 XXXXXXXX XXXXXXXX Sound Generator SGAR RAN SGTR RAN SGDR RAN 00019C4 00000000 res XXXXXXXX XXXXXXXX ADERH RAN ADERL R W B 00000000 00000000 00000000 00000000 EV ADCS1 R W ADCSO ADCR1 R ADCRO 8 00000000 00000000 000000XX BUBTAR ADCT1 R W ADCTO R W ADSCH R W ADECH R W 00010000 00101100 00000 00000 Alarm 0001 res res Comparator 0 1 360380 TMRLRO W TMRO R XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reload Timer 0 TMCSRH0 TMCSRL0 PPG 0 1 0001 4 reserved RW RW 00000 0 000000 TMRLR1 W TMR1 Reload 1 TMCSRH1 TMCSRL1 PPG 2 3 0001 reserved RAW RAW 00000 0 000000 TMRLR2 W TMR2 R 17 Timer XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX PPG 4 5 Page 47 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 TMCSRH2 TMCSRL2 0001C44 reserved RAW RAW 00000 0 000000 EE TMRLR3 MW XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reload Timer 3 TMCSRH3 TMCSRL3 PPG 6 7 0001 reserved RAW RAW 00000 0 000000 jonini TMRLR4 W TMR4 8 XXXXXXXX XXXXXXXX
5. ACRO 11 10 depends on Modevector fetch information buswidth TCR 3 0 INIT value 0000 keeps value after RST MODR W 0007 res XXXXXXXX res res Mode Register 000800 reserved DSU4 RTM 000 000 00 res Page 60 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000 04 5 reserved do not use 000000 PDRDOO R PDRDO1 R PDRD02 RI RI XXXXXXXX XXXXXXXX 000004 PDRD04 RI PDRDO5 R PDRDO6 R PDRDO7 XXXXXX XXXXXXXX XXXXXXXX 000008 PDRDO8 R PDRD09 R PDRD10 X X X XX x 00000004 000 0 424 1 PDRD14 PDRD15 R XXXXXXXX XXXXXXXX XXXXXXXX R bus 000010 PDRD16 R PDRD17 R PDRD18 R PDRD19 R Port Data XXXXXXXX XXXXXXXX XXX XXX XXX XXX Direct Read Register 000014 PDRD20 R PDRD21 R PDRD22 6 PDRD23 R 4 000018 PDRD24 R PDRD25IRI PDRD26 R PDRD27 R XXXXXXXX XXXXXXXX XXXXXXXX 000D1C PDRD28 R PDRD29 R PDRDB30JR PDRD31 R E XXXXXXXX XXXXXXXX XX9090000 000020 FANE 000024 reserved do not use 000D3Cu Page 61
6. Page 104 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 reserved 78 4E 0x2C4 0x000FFEC4 66 ICR31 0x45F reserved 79 4F 0x2C0 67 reserved 80 50 0x2BG 0x000FFEBC 68 ICR32 0x460 reserved 81 51 0x2B8 0x000FFEB8 69 reserved 82 52 0x2B4 0x000FFEB4 70 ICR33 0x461 reserved 83 53 0x2B0 0x000FFEBO 71 reserved 84 54 72 ICR34 0x462 reserved 85 55 0x2A8 0x000FFEA8 73 reserved 86 56 0x2A4 0x000FFEA4 74 ICR35 0x463 reserved 87 57 0 2 0 75 reserved 88 58 0x29C 0x000FFE9C 76 ICR36 0x464 reserved 89 59 0x298 0x000FFE98 77 reserved 90 0 294 0x000FFE94 78 ICR37 0x465 reserved 91 5B 0x290 0x000FFE90 79 Input Capture 0 92 5C 0 28 8 80 ICR38 0x466 Input Capture 1 93 5D 0x288 0x000FFE88 81 Input Capture 2 94 5E 0x284 0x000FFE84 82 ICR39 0x467 Input Capture 3 95 5F 0x280 0x000FFE80 83 Input Capture 4 96 60 0 27 0x000FFE7C 84 ICR40 0x468 Input Capture 5 97 61 0x278 0x000FFE78 85 Page 105 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Input Capture 6 98 62 0x274 0x000FFE74 86 ICR41 0x469 Input Capture 7 99 63 0x270
7. 00000000 00000000 res IF1DTA12 RW IF1DTA22 R W 00000000 00000000 00000000 00000000 Page 79 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 EE IF1DTB12 R W IF1DTB22 RW H 00000000 00000000 00000000 00000000 0082281 reserved 00 22 IF1DTA22 R W IF1DTA12 R W H 00000000 00000000 00000000 00000000 IF1DTB22 R W IF1DTB12 R W H 00000000 00000000 00000000 00000000 00 238 reserved 00 23 2 IF2CREQ2 RW IF2CMSK2 RAN 00 240 00000000 00000001 00000000 00000000 2 Register IF2MSK22 P W IF2MSK12 RW 000244 11111111 11111111 41111111 11111111 22 RW IF2ARB12 RW H 00000000 00000000 00000000 00000000 IF2MCTR2 RAN 00000000 00000000 res EN IF2DTA12 R W IF2DTA22 R W H 00000000 00000000 00000000 00000000 inedia IF2DTB12 R W IF2DTB22 R W 00000000 00000000 00000000 00000000 Page 80 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00 258 reserved 00 25 T IF2DTA22 R W IF2DTA12 R W H 00000000 00000000 00000000 00000000 EE IF2DTB22 R W IF2DTB12 R W H 00000000 00000000 00000000 00000000 00 268 reserved 00 27 2 TREQR22 8 2 R 00 280 00000000 00000000 0
8. 3 3 Clock Modulator settings The following table shows all possible settings for the Clock Modulator in a base clock frequency range from 32MHz up to 84MHz Fmax must not exceed the maximum specified frequency of 96MHz The flash access time settings see section 2 4 2 2 need to be adjusted according to Fmax while the PLL and clockgear settings see section 3 1 should be set according to base clock frequency Clock Modulator settings and frequency range Modulation Degree Random No Basecik k N MHz 1 3 026F 84 76 1 93 8 1 3 026F 80 72 6 89 1 1 5 02 80 68 7 95 8 2 3 046E 80 68 7 95 8 1 3 026F 76 69 1 84 5 1 5 02 76 65 3 90 8 2 3 046E 76 65 3 90 8 1 3 026F 72 65 5 79 9 1 5 02 72 62 85 8 1 7 02ED 72 58 8 92 7 2 3 046E 72 62 85 8 3 3 066D 72 58 8 92 7 1 3 026F 68 62 75 3 1 5 02 68 58 7 80 9 1 7 02ED 68 55 7 87 3 1 9 032 68 53 95 2 3 046E 68 58 7 80 9 2 5 04 68 53 95 3 3 066D 68 55 7 87 3 4 3 086 68 53 95 1 3 026F 64 58 5 70 7 1 5 02 64 55 3 75 9 1 7 02ED 64 52 5 82 1 9 032C 64 49 9 89 1 2 3 046E 64 55 3 75 9 2 5 04 64 49 9 89 1 3 3 066D 64 52 5 82 4 3 086 64 49 9 89 1 1 3 026F 60 54 9 66 1 1 5 02 60 51 9 71 1 7 02ED 60 49 3 76 7 1 9 032 60 46 9 83 3 1 11 0368 60 44 7 91 3 2 3 046E 60 51 9 71 2 04 60 46 9 83 3 Page 35 of 125 Eu
9. PFR08 RW PFR09 RW PFR10 RW PERELIBAN decise ll 1 00000000 PERA2 IRAN PERA2 IRAN PFR14 R W PFR15 RW B 00000000 00000000 00000000 00000000 PFR16 RW PFR17 RW PFR18 RW 19 RAY H 00000000 00000000 000 000 000 000 sagen PFR20 RW PFR21 RW PFR22 RW PFR23 RW H 000 000 00000000 00000000 EE PFR24 RW PER25 RAM PFR26 RW PFR27 RW 00000000 00000000 00000000 00000000 ER PFR28 RW PFR29 RW PER20 IRAV 24 H 00000000 00000000 00000000 00000000 000 PERSE 00000000 00000000 00000000 00000000 000 4 reserved 000DBCH EPEROHHRAM Fus Port 09090090 09909909 00000000 00000000 Extra Function Register EPERO4 IRAM EPER05 RAM EPEROG IRAN EPEROZIRAN 00000000 00000000 00000000 00000000 Page 63 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 EPEROS IRANI 94 8 00000000 00000000 a 00000000 421 434 EPFR14 RW EPFR15 RW H 00000000 00000000 00000000 00000000 ons EPFR16 R W 454 18 RW EPFR19 RW 1 0 00 00000000 000 000 000 000 daa EPFR20 R W EPFR21 RW 22 1
10. 4 0 96 P19_5 SOT5 4 0 o LIN USART clock 95 P19 4 SINS SIN LIN USART serial input 94 P19 2 SCK4 E 4 0 SOT LIN USART serial out EX CK Free Run Timer input 93 P19 1 SOT4 TP94 0 92 19 0 SIN4 3 4 0 43 P20 6 SCK3 ZIN1 CK3 4 0 _ TP04 0 SCK LIN USART clock I O 20 5 SOTS BIST SIN LIN USART serial input 41 P20 4 SIN3 AIN1 4 0 SOT LIN USART serial out Y TP04 0 CK Free Run Timer input 40 P20 2 SCK2 ZINO CK2 Up Down Counter up count input _ TP04 0 BIN Up Down Counter down count input 39 SOT2 BING ZIN Up Down Counter reset input 38 P20 0 SIN2 AINO E 4 0 17 P21 1 SOTO 4 0 SIN LIN USART serial input TP04 SOT LIN USART serial out 16 P210 SINO 04 0 63 22 7 SCL1 2 0 62 22 6 SDA1 INT15 2 0 0 SCL serial clock I O 81 P22_5 SCL0 s SDA 12C serial data 60 P22 4 SDA0 2 INT14 2 0 INT External Interrupt input 59 P22 3 TX5 4 0 TX CAN transmission 1 TP04 0 RX reception input 3 paare RXS INTIS INT External Interrupt input 57 P22 1 TX4 4 0 56 22 0 RX4 INT12 4 0 53 23 7 TX3 4 0 52 P23 6 RX3 INT 11 TP04 0 51 P23 5 TX2 4 0 50 P23 4 RX2 INT10 4 0 TX CAN transmission gt TP04 0 RX CAN reception input 49 P23_3 TX1 5 INT External Int
11. 6 ch 128 msg buffer 6 ch x 32 msg buffer LIN USART 16 ch 4 ch FIFO 7 ch 4 ch FIFO 4 ch 4 ch FIFO I2C 4 ch 2ch FR Sera bus 32 bit 32 bit External Interrupts 16 ch 16 ch 12 ch NMI 1 1 SMC 6 ch LCD 1 ch 40x4 ADC 10 bit 32 ch 32 ch 16 ch Alarm Comparator 2 ch 1 ch Low voltage detection yes yes Clock Supervisor yes yes Package BGA 660 LQFP 144 1 LIN USART CHO shared with external bus can be used for asynchronous mode only 2 FRT MD3 0 gt CH1 amp 0 can t select ext clock bit7 of TCCS1 0 MD3 1 gt CH3 2 1 amp 0 can t select ext clock bit7 of TCCS3 2 1 0 ICU MD3 1 gt Don t set 18 EPFR 1 for LIN Synch Field detect because there is not CH3 0 of LIN USART MD3 1 gt 7 6 5 4 can t select ext event PPG MD3 1 gt You can use 15 8 of PPG CH15 12 can t select ext trigger OCU MD3 1 gt You can t use ext out port but OCU function is active 4 5 6 Ext INT INT7 4 shared with external bus can be used for MD3 0 mode only 7 8 UDO MD3 1 You can use Timer mode only Page 9 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 2 Core Functionality Page 10 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 2 2 1 Memory Map 0001
12. 91 467 466 465 464 preliminary datasheet ver 0 27 Modulation Degree k N MHz Random No 7 3 0 69 48 32 8 89 1 1 3 026F 44 40 6 48 1 1 5 02 44 38 4 51 6 1 7 02ED 44 36 4 55 7 1 9 032 44 34 6 60 4 1 11 0368 44 33 66 1 1 13 44 31 5 73 1 15 03E9 44 30 1 81 4 2 3 046E 44 38 4 51 6 2 5 04 44 34 6 60 4 2 7 04 44 31 5 73 2 9 0528 44 28 9 92 1 3 3 066D 44 36 4 55 7 3 5 06 44 31 5 73 4 3 086 44 34 6 60 4 4 5 08 8 44 28 9 92 1 5 3 0 6 44 33 66 1 6 3 44 31 5 73 7 3 0E69 44 30 1 81 4 8 3 1068 44 28 9 92 1 1 3 026F 40 37 43 6 1 5 02 40 34 9 46 8 1 7 02ED 40 33 1 50 5 1 9 032 40 31 5 54 8 1 11 0368 40 30 59 9 1 13 40 28 7 66 1 1 15 03E9 40 27 4 73 7 2 3 046E 40 34 9 46 8 2 5 04 40 31 5 54 8 2 7 04 40 28 7 66 1 2 9 0528 40 26 3 83 3 3 3 066D 40 33 1 50 5 3 5 06 40 28 7 66 1 3 7 06E7 40 25 3 95 8 4 3 086 40 31 5 54 8 4 5 08 8 40 26 3 83 3 5 3 0 6 40 30 59 9 6 3 40 28 7 66 1 7 3 0E69 40 27 4 73 7 8 3 1068 40 26 3 83 3 9 3 1267 40 25 3 95 8 1 3 026F 36 33 3 39 2 1 5 02 36 31 5 42 1 7 02ED 36 29 9 45 3 1 9 032 36 28 4 49 2 1 11 0368 36 27 1 53 8 Page 37 of 125 European MCU Design Centre 91 467 466 465 464 preliminary data
13. 0 set to 1 not available FSV2 31 set to 0 set to 1 not available See section 2 4 2 1 for an overview about the sector organisation of the Flash Memory 2 4 4 4 Register description for Flash Security For a description of Flash Security registers please refer to Hardware Manual chapter 55 Page 32 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 3 Recommended Settings 3 1 PLL and Clockgear settings Please note that for MB91F467BA 466BA 465BA 464BA the core base clock frequencies are valid in the 1 8V operation mode of the Main regulator and Flash Recommended PLL divider and clockgear settings PLL Input Frequency CK Parameter Clockgear Parameter MHz DIVM DIVN DIVG MULG PLL Output 9 MHz Core base Clock MHz Keep REGSEL FLASHSEL 0 and REGSEL MAINSEL 0 at their initial value HWM Chapter 52 3 1 33 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 3 2 Flash interface settings Please refer to section 2 4 2 2 Flash access timing settings in CPU mode for the recommended Flash interface settings Page 34 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27
14. 234 000 000 00 00000000 00000000 dadas 24 TRAM 254 EPFR26 RW EPFR27 RW 00000000 00000000 00000000 00000000 EPER28IRAN EPER29 IRAN EPER30 IRAN 41 00000000 00000000 00000000 00000000 EPER221RAN EPER33 IRANI 44 EPER35 IRANI DOUDEUN 00000000 00000000 00000000 00000000 0000 4 000DFCu reserved do not use R bus Port PODRO00 R W PODRO1 R W PODRO2IRAN PODRO2IRAN 000 00000000 00000000 99099090 09090090 rer Register 000E04 29580412 5 R W PODRO6 R W PODR07 R W 00000008 000000 00000000 00000000 PODROS R W PODRO9 R W PODR10 R W 4 Bises 2 0 0 00000000 Page 64 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000 2 PODR14 R W PODR15 R W 90000000 90000000 00000000 00000000 000E10 PODR16 R W PODR17 R W PODR18 R W PODR19 R W 00000000 00000000 000 000 000 000 000 14 PODR20 R W PODR21 R W PODR22 R W PODR23 R W 000 000 00000000 00000000 000 18 PODR24 R W 2548 PODR26 R W PODR27 R W 00000000 90000000 00000000 00000000 000E1C PODR28 R W PODR29 R W PODR3O0IRAA 1 H 00000000 00000000 90000000 90000000 24 POD
15. 4to7 FA13 to FA16 4 to GP06 7 8to 11 FA17 to FA20 5 0 to GPO5 12 to 15 FA21 GP05 4 16 Set to 1 DQO to DQ7 DQ8 to DQ15 Internal data bus DQO to DQ7 0 to 7 28 to 35 DQ8 to DQ15 GP01 0 to GPO1 7 20 to 27 Page 27 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 44 Flash Security 2 4 4 1 Vector addresses Two Flash Security Vectors FSV1 FSV2 are located parallel to the Boot Security Vectors BSV1 BSV2 controlling the protection functions of the flash security module FSV1 0x14 8000 BSV1 0x14 8004 FSV2 0x14 8008 BSV2 0x14 800C 2442 Security Vector FSV1 The setting of the Flash Security Vector FSV1 is responsible for the read and write protection modes and the individual write protection of the 8 kB sectors 5 1 bits 31 to 16 The setting of the Flash Security Vector FSV1 bits 31 16 is responsible for the read and write protection modes Page 28 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Explanation of the bits in the Flash Security Vector FSV1 31 16 FSV1 18 FSV1 17 FSV1 16 FSV1 31 19 Write Protection Flash Security Mode Write Protection Read Protection Level Read Protection all device modes except INTVEC mode MD 2 0 000 Set all to 0 set t
16. Control Flash Memory Cache Control Boot ROM 4 kB CAN External Bus I Cache 4 kB or Instruction RAM 4 kB Data RAM 24 kB Instruction Data RAM 16 kB Flash Memory Area 768 kB 64 kB External Bus Area depending on ROMA setting External Bus Area External Bus Area m g 8 8 E 9 a Page 11 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 0001 FFFFh 0002 0000h 0002 FFFFh 0003 0000h 0003 FFFFh 0004 0000h 0005 FFFFh 0006 0000h 0007 FFFFh 000B FFFFh 000C 0000h 000D FFFFh 000E 0000h 0010 0000h 0013 FFFFh 0014 0000h 0017 FFFFh 0018 0000h 001B FFFFh 001C 0000h 001F FFFFh 0020 0000h 0027 FFFFh 0028 0000h 002F FFFFh 0030 0000h 0037 0038 0000h 0040 0000h 0047 FFFFh 0048 0000h 0050 0000h FFFF FFFFh Legend MB91V460A I O Byte Data Halfword Data Word Data VO Flash Control Flash Cache Control Boot ROM 4 kB 2 Ra 8 8 External Bus Cache 4 kB or Instruction RAM 4 kB Data RAM 64 kB Instruction Data RAM 64 kB Emulation SRAM Area max 4 864 kB External Bus Area depending on ROMA ROMS setting External Bus Area Memory available in this area Memory not available in this area available
17. gu au me 16bit read wite 32bit read Legend Merrory not available in this area Page 22 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 MB91F465BA Fl ash CPU node 2 0 00 addr 0014 FFFFh 0014 CD00h 8 SA7 8KB 0014 BFFFh 0014 8000h SAA 8KB SA5 8KB d d d id 16011 read dat 31 16 dat 15 0 dat 31 16 dat 15 0 32bi t read dat 31 0 dat 31 0 Legend Memory available in this area Merrory not available in this area MB91F464BA Fl ash CPU node 2 0 00 addr mimm d mU d rd id 0007 FFFFh 0006 0000h SALO 64KB SALL 64KB 0005 FFFFh 0004 0000h LUCIE SUE 16bit read wite dat 31 16 dat 15 0 dat 31 16 dat 15 0 32bit read dat 31 0 dat 31 0 Legend Memory available in this area Memory not available in this area Page 23 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 2 4 2 2 Flash access timing settings in CPU mode The Flash access timing settings described below are valid for MB91F467BA 466BA 465BA 464BA in the 1 8V operation mode of the Main regulator and Flash The following tables list all settings for a given maximum Core Frequency through the setting of CLKB or maximum clock modulation for Flash
18. set to 1 FSV1 8 0 set to 1 not available FSV1 9 0 set to 1 not available FSV1 10 0 set to 1 not available FSV1 11 set to 1 not available FSV1 12 set to 1 not available FSV1 13 0 set to 1 not available FSV1 14 set to 1 not available FSV1 15 set to 1 not available Remark It is mandatory to always set the sector where the Flash Security Vectors FSV1 and FSV2 are located to write protected here sector SA4 Otherwise it is possible to overwrite the Security Vector to a setting where it is possible to either read out the flash content or manipulate data by writing See section 2 4 2 1 for an overview about the sector organisation of the Flash Memory Page 30 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 4 4 3 Security Vector FSV2 The setting of the Flash Security Vector FSV2 bits 31 0 is responsible for the individual write protection of the 64 kB sectors It is only evaluated if write protection bit FSV1 17 is set Explanation of the bits in the Flash Security Vector FSV2 31 0 Enable Write Disable Write FSV1 bit Sector 1 Comment Protection Protection FSV2 0 set to 0 set to 1 FSV2 1 set to 0 set to 1 FSV2 2 set to 0 set to 1 FSV2 3 set to 0 set to 1 F
19. 0 TX 55 37 0x320 0x000FFF20 7 49 reserved 56 38 0x31C 0 000 8 50 20 0 454 reserved 57 39 0x318 0x000FFF18 9 51 Page 103 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 USART LIN 2 RX 58 3A 0x314 0x000FFF14 52 ICR21 0x455 USART LIN 2 TX 59 3B 0x310 0x000FFF10 53 USART LIN 3 RX 60 3C Ox30C 54 ICR22 0x456 USART LIN 3 TX 61 3D 0x308 0x000FFF08 55 System reserved 62 3E 0x304 0x000FFF04 ICR23 0 457 Delayed Interrupt 63 3F 0x300 0x000FFF00 System reserved 64 40 Ox2FC 0x000FFEFC ICR24 0 458 System reserved 65 41 Ox2F8 0x000FFEF8 USART LIN FIFO 4 RX 66 42 Ox2F4 0x000FFEF4 10 56 ICR25 0 459 USART LIN FIFO 4 TX 67 43 Ox2FO 0x000FFEFO 11 57 USART LIN FIFO 5 RX 68 44 Ox2EC 12 58 ICR26 0 45 USART LIN FIFO 5 TX 69 45 Ox2E8 Ox000FFEE8 13 59 USART LIN FIFO 6 RX 70 46 0 2 4 0x000FFEE4 60 ICR27 0x45B USART LIN FIFO 6 TX 71 47 Ox2EO 0x000FFEEO 61 USART LIN FIFO 7 RX 72 48 Ox2DC 0x000FFEDC 62 ICR28 0 45 USART LIN FIFO 7 TX 73 49 0x2D8 0x000FFED8 63 20 0 74 4A 0 204 0x000FFED4 ICR29 0x45D 12 1 75 4B 0x2D0 0x000FFEDO reserved 76 4 0 2 64 ICR30 0x45E reserved 77 4D Ox2C8 0x000FFEC8 65
20. 11111 11111 11111 000478 ICR56 R W ICR57 RAN ICR58 RAN ICR59 RAN titi 11111 11111 11111 00047C ICR60 RW ICR61 RW ICR62 RW ICR63 RAW 11111 11111 tili 11111 000480 RSRR RW STOR RW TBCR RM CTBR W 10000000 00110011 00XXXX00 XXXXXXXX OC Control Unit 000484 CLKR RW WPR W DIVRO R W DIVR1 R W 0000 XXXXXXXX 00000011 00000000 Page 56 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000488 res res res d i PLLDIVM RAW PLLDIVN RW PLLDIVG R W PLLMULG RAN 0000 000000 0000 00000000 PLL Clock Gear Unit PLLCTRL R W 0004901 222 0000 res res res Main Sub OSCC1 RAY OSCS1 R W OSCC2 RAW OSCS2 RW Oscillator H 5 010 00001111 gt gt 010 00001111 Control do not use PORTEN R W Port Input 000498 00 res res res Enable Control WTCER RAN WTCR R W 0004 0 5 00 00000000 000 00 0 Real Time WTBR RW 0004 4 res XXXXX XXXXXXXX XXXXXXXX Clock Watch Timer WTHR RW WTMR RW WTSR RM 0004 8 00000 000000 000000 Clock CSVTR RW CSVCR RW CSCFG RW CMCFG R W Supervisor 00010 011100 0X000000 00000000 Selector Monitor CUCR RW CUTD R W POS seem es 0 00 10000000 00000000 Calibration
21. CMOS Schmitt trigger input 0 8Vcc 0 2Vcc with standby control If standby assert CH input keeps previous value CMOS Schmitt trigger input 0 7Vcc 0 3Vcc with standby control If standby assert CCH input keeps previous 5 value 02 0 gt D gt Ghlinput CMOS Automotive Schmitt trigger input Standby control 0 8Vcc 0 5Vcc with standby control If standby assert AM input keeps previous value Standby control TTL input 2 0V 0 8V with standby control If standby assert TTL input becomes L Pull up control CCH input AM input Standby control Standby contrl AD combined use General Purpose I O Pull up Resistor 50 kQ with control Pull Up control Pull down Resistor 50 kQ with control P Output trigger Pch lon 2 5 lo 2 5 CMOS Schmitt trigger input 0 8Vcc 0 2Vcc with standby control If standby assert CH input keeps previous N N Output trigger Nch value CMOS Schmitt trigger input 0 7Vcc 0 3Vcc Pull Down control with standby control If standby assert CCH input keeps previous value pepe CH input CMOS Automotive Schmitt trigger input 0 0 8 0 5 with standby control Standby control If standby assert AM input keeps previous CCH input value input 2 0V 0 8V with standby control Standby control If standby assert input becomes L AM
22. ECCROO 000044 AM IRW R W res 00000XX 000048 7 7 USART LIN 4 00004 res SCRO2 R W W SMRO2 R W W 55802 R W R H 00000000 00000000 00001000 4 2 ECCR02 000054 geek RW RW res 00000 000058 SCRO3 RAW SMRO3 55803 RAR H 00000000 00000000 00001000 one 3 ECCRO3 00005 res 00000XX SCRO4 RW W SMRO4 R W W 58804 ia os LIN H 00000000 00000000 00001000 BED Page 41 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000064 FSCRO4 RW AWW FSR04 R FCR04 RW 00000X00 00000 0001 000 000068 SCROS RW W SMROS RW W 55805 RW RI 00000000 00000000 00001000 00000000 USART LIN 5 with FIFO 000080 ESCROS RW FSRO5 FCR05 RW 00000X00 00000 0001 000 000070 50806 RW W SMROS RWMW SSRO6 i 00000000 00000000 00001000 00000000 USART LIN 6 with FIFO 000074 FSCRO6IRW FSRO6 R FCR06 RW 00000X00 00000 0001 000 SCRO7 RW W SMRO7 R W W SSRO7 R W R 00000000 00000000 00001000 00000000 USART LIN 7 with FIFO 000070 ESCRO7 R W aE FSRO7 8 FCRO7 RW 00000 00 00000 0001 000 BGR100 R W BGROO0 R W 0000804 0
23. H 00000000 00000000 00000000 00000000 00 438 00C43CH CAN 4 T IF2CREQ4 RW IF2CMSK4 R W 00000000 00000001 00000000 00000000 Page 87 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 1 2 24 R W IF2MSK14 R W 000444 11111111 11111111 11111111 11111111 EN IF2ARB24 R W IF2ARB14 R W 00000000 00000000 00000000 00000000 2 R W 00C44Ch 00000000 00000000 IF2DTA14 RW 2 24 R W 00000000 00000000 00000000 00000000 IF2DTB14 RAW IF2DTB24 RAW H 00000000 00000000 00000000 00000000 00 458 reserved 00C45CH PE IF2DTA24 R W IF2DTA14 R W H 00000000 00000000 00000000 00000000 T IF2DTB24 R W IF2DTB14 R W 00000000 00000000 00000000 00000000 00 4684 reserved 00 47 4 24 TREQR14 R VOCABU 00000000 00000000 00000000 00000000 Status Flags 00 484 Page 88 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00 488 00 48 0084901 NEWDT24 NEWDT14 8 00000000 00000000 00000000 00000000 00 494 00 498 00 49 00 4 INTPND24 R INTPND14
24. PCNH13 RAN PCNL13 R W 0000000 000000 0 000340 PTMR14 R PCSR14 W 11111111 11111111 XXXXXXXX XXXXXXXX PPG 14 000344 PDUT14 W PCNH14 RAN PCNL14 RW 30000000 30000000 0000000 000000 0 000348 PTMR15 R PCSR15 W 11111111 11111111 XXXXXXXX XXXXXXXX 15 00034 PDUT15 W PCNH15 RAN PCNL15 R W XXXXXXXX XXXXXXXX 0000000 000000 0 000350 5 reserved 00035 000360 000364 000368 00036 000370 res res Page 53 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000374H 000378H 00037 res res 000380 reserved 00038 ROMS R ROM Select 0003904 11111111 00000000 res Register 0003944 s reserved do not use 0003BCy 0003 0 reserved L Gache 0003C4u reserved 000308 reserved 0003 0003 4 reserved L Gache 0003 8 3 reserved do not use 0003ECy Bit Search 0003F0H BSDO Module XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Page 54 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 0003F4 E 0003F8 pane XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0003FC 1 i XXXXXXXX XXXXXXXX
25. U D control CH A TTL CH2 Stop 2 5 mA General Purpose I O TP04 1 U D control CH A TTL CH2 Stop 2 5 mA General Purpose 1 with 1 analog output line 01 0 C2 no 1 Mode Pin MD 2 MD 1 MD 0 TC02 0 Up C2 no Input pin INITX NMIX 02 1 C2 no Input _3 TC10_0 no 5 mA Threestate Output 5mA for MONCLK 2003 4 MHz Oscillator Pin 32 KHz Oscillator Pin TA00_0 5 5 5 Analog power supply pin TA01_0 1 2 Analog I O pin TA02_0 1 5 Analog 1 pin TA03_0 Analog Ground pin Notes e The pull up pull down resistors are typical 50 The controlled pull up down s can be enabled by register setting e Input Types CH CMOS Schmitt trigger CH2 CMOS Schmitt trigger 2 A CMOS Automotive Schmitt trigger TTL TTL for input high low voltages please see section Operating Conditions e Stop control Switch to HiZ in STOP mode by register setting and disable input lines in STOP if the port is not configuerd to be external interrupt input e Default output driver strength is mA pins and 5 mA all other pins Page 121 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Pin Type Citcuit Comment combined use General Purpose Pin open drain if PFR 1 Pull up Resistor 50 with control Pull down Resistor 50 with control Output trigger Pch lou lo
26. Unit of Sub CUTR1 8 CUTR2 R ane 00000000 00000000 00000000 Page 57 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 CMPR CMCR RAN 000010 11111101 001 00 Clock Modulation CMT1 R W CMT2 R W 0004BC4 00000000 1 0000 000000 000000 RAN Clock 0004 0 0000 res res Control LVSEL RW LVDET RW HWWDE RW HWWD R W w LV Detection 0004C4u MW Hardware 00000101 00000 00 00 00011000 Watchdog Main Sub OSCRH RAN OSCRL RAN WPCRH RAN WPCRL RW Oscillation 000 001 000 000 001 00 Stabilisation Timer Main Oscillation Standby 0004 OSCCR RAN REGSEL R W REGCTR RAN 00 000100 0 00 Main Sub Regulator Control 34084 dem 0004D04 2100 168 00000000 00000000 Miedo do not use 0004D4 res EXTE RAN H 8 99999999 99999999 Supply Shut Dewn Mede do not use 000408 res res 00040 00063 58 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 note at the end of the section External Bus Unit 000640 ASRO RAN ACRO RAN j 00000000 00000000 11
27. m SGA Sound Generator amplitude out 66 P16 2 PPG10 5 04 0 65 P16 1 PPG9 64 16 0 PPG8 TF04 9 103 P18 6 SCK7 CK7 4 0 102 18 5 5017 TP04_0 _ TP04 0 SCK LIN USART clock 101 P18 4 SINZ SIN LIN USART serial input AT CK Free Run Timer input 99 P18 1 SOT6 4 04 0 98 P18 0 SING TP04_0 97 P19 6 SCK5 CK5 0 96 P19 5 5015 04 0 4 0 SCK LIN USART clock I O 95 P19 4 SIN5 5 SIN LIN USART serial input 94 P19 2 SCK4 CK4 4 0 SOT LIN USART serial out CK Free Run Timer input 93 P19_1 SOT4 TP04 0 92 P19 0 SIN4 TP04_0 63 P22 7 SCL1 _ 5 2 0 SCL serial clock I O SDA 2 serial data I O 62 P22_6 SDA1 INT15 02 0 INT External Interrupt input 2 0 81 P22_5 SCL0 TX CAN transmission I O 60 P22 4 SDA0 2 INT14 2 0 RX CAN reception input INT External Interrupt input 59 P22 3 TX5 4 0 58 P22 2 RX5 INT13 TP04_0 57 P22 1 TX4 4 0 Page 117 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Pin 1 EPFR 1 Special Type Comments 56 22 0 4 INTi2 04 0 53 P23 7 TX3 TP04 0 52 P23 6 RX3 INT 11 TP04 0 51 P23 5 TX2 TP04 0 50 P23 4 RX2 2 INT10 4 0 TX CAN transmission I O TP04 0 RX CAN reception input 49 23 3 TX1 I
28. will halt CPU functioning At this time the Flash memory s interface circuit enables direct control of the Flash memory unit from external pins by directly linking some of the signals to GP Ports Please see table below for signal mapping In this mode the Flash memory appears to the external pins as a stand alone unit This mode is generally set when writing erasing using the parallel Flash programmer In this mode all operations of the 8 5 Mbits Flash memory s Auto Algorithms are available Correspondence between MBM29LV400TC and Flash Memory Control Signals MB91F 467BA external pins MBM29LV400TC External pins FR CPU mode Comment Flash memory mode INITX Normal function Pin number FRSTX GP16 6 MD2 MD2 Set to 1 MD1 MD1 Set to 1 MDO MDO Set to 1 FMCS RDY bit RY BYX GP18 2 Internally fixed to H BYTEX GP16 4 WEX GP16 7 GP07 7 CEX GP07_6 Internal control signal control via interface Set to 0 circuit ATDIN GP18 6 EQIN GP18 5 Set to 0 TESTX GP16_5 Set to 1 RDYI GP18 4 Set to 0 FAO GP05 5 Set to 0 GP19 0 to GP19 2 GP19 4 0 to FA1 to FA4 92 to 95 GP19 5 to GP19 6 A4 to A7 A8 to A11 A12 to A15 A16 to A19 Internal address bus 5 to FA8 GP18 0 to GP18 1 96 to 99 9 to FA12 0 to 6
29. 0 27 P15 7 OCU7 TOT7 TP04_1 26 P15 6 OCU6 TOT6 TP04_1 25 P15 5 OCU5 TOT5 04 1 1 24 P15 4 4 1014 04_ OCU Output Compare Unit waveform out 137 P15 3 OCU3 TOT3 4 0 TOT Reload output 136 P15 2 OCU2 TOT2 z TP04_0 135 15 1 TOT1 4 0 134 P15 0 OCUO TOTO 4 0 7i P16 7 PPG15 ATGX 4 0 70 P16_6 PPG14 4 0 69 16 5 PPG13 SGO TP04_0 TP04 0 PPG Prog Pulse Generator waveform out 68 P16_4 PPG12 SGA ADC external trigger input TP04 0 SGO Sound Generator waveform out 7 P16_3 PPG11 E 9 SGA Sound Generator amplitude out 66 16 2 PPG10 4 0 65 P16 1 PPG9 4 0 64 P16_0 PPG8 4_0 35 17_7 PPG7 04 1 34 176 PPG6 2 04 1 33 P17_5 PPG5 04 1 32 17 4 PPG4 04 1 Prog Pulse Generator waveform out 31 P17_3 PPG3 TP04_1 30 P17_2 PPG2 TP04_1 29 17 1 PPG1 04 1 28 170 PPG0 04 1 2 SIN LIN USART serial 102 18 5 5077 04 0 SOT LIN USART serial out Free input 101 P184 SIN7 4 0 Page 112 01125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Pin I O PFR 1 EPFR 1 Special Type Comments 100 P18 2 SCK6 CK6 4 0 99 P18 1 SOT6 4 0 98 P18 0 SIN6 TP04_0 97 P19_6 SCK5 CK5
30. 0x000FFE70 87 Output Compare 0 100 64 0 26 0x000FFE6C 88 ICR42 0x46A Output Compare 1 101 65 0x268 0x000FFE68 89 Output Compare 2 102 66 0x264 0x000FFE64 90 ICR43 0x46B Output Compare 3 103 67 0x260 0x000FFE60 91 Output Compare 4 104 68 0x25G 0x000FFESC 92 ICR44 0 46 Output Compare 5 105 69 0x258 0x000FFE58 93 Output Compare 6 106 6A 0x254 0x000FFE54 94 ICR45 0x46D Output Compare 7 107 6B 0x250 0x000FFE50 95 Sound Generator 108 6 0 24 4 ICR46 0x46E reserved 109 6D 0x248 0x000FFE48 System reserved 110 6E 0x244 0x000FFE44 47 0x46F System reserved 111 6F 0x240 0x000FFE40 Prog Pulse Gen 0 112 70 0 23 0 000 15 96 48 0 470 Prog Pulse Gen 1 113 71 0x238 0x000FFE38 97 Prog Pulse Gen 2 114 72 0x234 0x000FFE34 98 ICR49 0x471 Prog Pulse Gen 3 115 73 0x230 0x000FFE30 99 Prog Pulse Gen 4 116 74 0x22G 0x000FFE2G 100 ICR50 0x472 Prog Pulse Gen 5 117 75 0x228 0x000FFE28 101 Page 106 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Prog Pulse Gen 6 118 76 0x224 0x000FFE24 102 ICR51 0x473 Prog Pulse Gen 7 119 77 0x220 0x000FFE20 103 Prog Pulse Gen 8 120 78 0x21C 0x000FFE1C 104 ICR52 0x474 Prog Pulse Gen 9 121 79 0x218 0x000FFE18 105 Prog Pulse Gen 10 122 7A 0x214 0x000FFE14 106 ICR53 0
31. 28 0 AN8 0 117 P29 7 7 5 0 116 P29 6 AN6 0 115 P29 5 5 0 114 P29 4 4 0 iis ANS _ 0 ADC Analog input 112 P29_2 AN2 2 0 111 29 1 AN1 2 0 110 29 0 AN0 2 0 84 TC02_0 Reset low active 85 NMIX 1 5 5 02 0 NMI pin low active 78 MD_3 TC02_0 Mode pin for external bus interface option 76 MD 2 1 0 75 MD 1 TC01 0 Mode pins 74 MD 0 01 0 VDD5 TS02 0 Power Supply for ring 5 V Page 114 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Pin I O 1 1 Special Type Comments Power Supply for external bus part of IO 36 VDD35 15020 ring VDD5R 8 1 TA00_0 supply for Voltage Regulator Core VSS5 500 0 Ground Supply 107 5 00 0 Analog Power supply 5 V 106 AVRH5 01 0 Analog High Reference 5 105 AVSS TA03 0 Analog Ground supply Low Reference 87 VCC18G 10 0 Voltage Regulator Capacitance pin Page 115 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 6 2 2 MB91F467BA 466BA 465 464 with MD 3 1 VDD35 7 5 A5 MB91F467BA 466 465BA 46
32. 3 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 3 3 The combination description of CMPR OSE9 Baseclk 52 2 and Fmax 96 9MHz was deleted from the table 7 2 Parameter item in table The maximum frequency was changed from 100MHz to 96MHz about the frequency description of Lock up time PLL1 027 Latstrevison Page 4 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Table of contents J ONS VISW oa S Q IDE 7 1 3 gt Block Diagram aus 7 2 Feature EU 8 247 Overview Table u u unun 8 2 2 Gore Furecti ralilyu uk de OR aei buc 10 224 Memory MP amp areas k 11 22 2 FR70 CPU ER 13 2 13 Sais dis S te 13 224 ee 14 225 Nermal BAM a 14 2 2 6 Internal Program Data RAM 14 2 2 7 External Bus Interface I ener m 14 ZB DMA Controller 55 15 2 35 Peripheral esse 16 2 4 Embedded Program Data Memory 21 2 4 1 Flashfe at r Su E 21 2922 CPU MOO Ls
33. 4 1 4 LIN USART FIFO x Resources in case of bus interface option In case of the bus interface option only the blue coloured numbers of resources will be available The bus interface option is enabled via the pin MD 3 Page 7 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 Feature List 2 1 Overview Table 91 467 466BA 465 464 Feature MB91V460 MD 3 0 3 1 Core frequency 80 MHz 96 MHz Resource frequency 40 MHz 48 MHz Watchdog yes yes Bit Search yes yes Reset Input yes yes Clock Modulator yes yes DMA 5 5 ch MPU EDSU 16 ch 8 ch 1024 KB 64 KB MB91F467BA Fi sh MT 768 KB 64 KB MB91F466BA 512 KB 32 KB MB91F465BA 384 KB 32 KB MB91F464BA Flash Protection n a yes D bus RAM 64 KB 24 KB GP RAM 64 KB 16 KB Direct mapped cache 16 KB 8 KB Boot ROM 4 kB 4 KB RTC 1 ch 1 ch Free Running Timer 8 ch 8 ch ICU 8 ch 8 ch 4 ch gt OCU 8 ch 8 ch 4 ch Reload Timer 8 ch 8ch PPG 16 ch 16 ch 8 ch PFM 1 ch Sound Generator 1 1 Page 8 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Feature MB91V460 91 467 466BA 465BA 464 MD 3 0 MD 3 1 UpDown Counter 4 ch 2 ch 278
34. Add a Cancellation line D A Converter Interrupt Control Unit and CAN 0 5 Status Flags 2006 08 07 4 Added Type in Table 6 Del a Cancellation line Interrupt Control Unit Add a Cancellation line Test function C Unit Test CSVCR bit7 CANCKD and l Unit Test 6 Del a postscript 4 It was already descripted User s Manual 0 21 2007 03 12 Added MB91F465BA information A Cover amp 1 amp 4 1 8 4 2 1 8 4 2 2 Add MB91F465BA 1 1 amp 2 1 Add 544KB FLASH and explanation of FLASH 2 2 1 Add memory map of MB91F465BA 2 2 9 Add 544 Fash memory map 6 Add Flash area of MB91F465BA Changed a discription about Clock supervisor 2 3 Clock supervisor function revival 2007 04 09 Added 4 3 Pin Types Page 2 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2007 04 12 Added MB91F466BA MB91F464BA information A Cover amp 1 amp 4 1 amp 4 2 1 amp 4 2 2 Add MB91F466BA and MB91F464BA 1 1 amp 2 1 Add 832KB 416KB FLASH and explanation of FLASH 2 2 1 Add memory map of MB91F466BA MB91F464BA 20 2 2 9 Add 832KB 416KB Fash memory map 6 Add Flash area of MB91F466BA MB91F464BA 07 04 19 Change of Chapter Constitution and Addition of Recommended Settings Chap1 Overview no change Chap2 Feature List small change in this Chap Chap3 Recommended Settings addition Chap4 IO Map in previous Ver Chap5
35. Comments 23 01 3 D19 1 22 01 2 018 5 04 1 21 P01_1 D17 5 1 20 P01_0 D16 TP04_1 138 7 0 0 0 139 7 1 1 TP03 0 140 P07_2 A2 0 141 7 3 0 143 Po7 4 _ 0 External Bus Address Lines 143 P07_5 A5 0 2 7 6 0 3 P07_7 7 2 0 4 0 A8 0 5 P06_1 A9 TP03_0 6 P06_2 A10 0 7 06 3 A11 _0 P06 4 TP03 0 External Bus Address Lines 9 P06_5 A13 0 10 06 6 A14 5 0 11 P06_7 A15 0 12 5 0 16 04 0 13 5 1 17 2 04 0 14 5 2 A18 4 0 15 3 4 0 External Bus Address Lines 16 P05_4 A20 4 0 17 05 5 A21 TP04_0 39 9 0 CSX0 4 0 40 09 1 CSX1 TP04_0 41 P08_0 WRX0 4 0 42 P08 4 RDX 4 0 External Bus Control Signals 43 08 7 RDY 5 4 0 44 WRX1 1 4 0 38 P10 0 SYSCLK z TP04_0 84 INITX 5 02 0 Reset pin low active 85 NMIX 1 1 TC02 0 NMI pin low active 78 MD_3 TC02 0 Mode pin for external bus interface option 76 MD 2 2 5 TC01_0 75 MD_1 TC01 0 Mode pins 74 MD 0 1 TC01_0 VDD5 TS02_0 Power Supply for ring 5 V Page 119 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ve
36. FFFFh 0002 0000h 0002 FFFFh 0003 0000h 0003 FFFFh 0004 0000h 0005 FFFFh 0006 0000h 0007 FFFFh 000B FFFFh 000C 0000h 000D FFFFh 000E 0000h 0010 0000h 0013 FFFFh 0014 0000h 0017 FFFFh 0018 0000h 001B FFFFh 001C 0000h 001F FFFFh 0020 0000h 0027 FFFFh 0028 0000h 002F FFFFh 0030 0000h 0037 0038 0000h 0040 0000h 0047 FFFFh 0048 0000h 0050 0000h FFFF FFFFh Legend MB91V460A I O Byte Data Halfword Data Word Data VO Flash Control Flash Cache Control Boot ROM 4 kB 2 Ra 8 8 External Bus Cache 4 kB or Instruction RAM 4 kB Data RAM 64 kB Instruction Data RAM 64 kB Emulation SRAM Area max 4 864 kB External Bus Area depending on ROMA ROMS setting External Bus Area Memory available in this area Memory not available in this area available but no 128 kB ROMSOL 128 kB ROMS02 128 kB ROMS03 128 kB ROMS04 128 kB ROMS05 128 kB ROMS06 256 kB ROMS07 256 kB ROMS08 256 kB ROMS09 256 kB ROMS10 512 kB ROMS11 512 kB ROMS12 512 kB ROMS13 512 kB ROMS14 512 kB ROMS15 512 kB 0000 0000h 0000 00FFh 0000 0100h 0000 01FFh 0000 0200h 0000 03FFh 0000 0400h 0000 0FFFh 0000 1000h 0000 10FFh 0000 2000h 0000 5FFFh 0000 7000h 0000 70F Fh 0000 8000h 0000 BFFFh 0000 000 0000 CFFFh 00
37. Function to search the first bit position of 1 0 Changed from MSB most significant bit within 1 word Up down counter 16 bits x 2 channels Not available in case of MD_3 1 Timer mode up down count mode phase difference mode x2 x4 Includes clock prescaler fres 2 fres 2 Reload timer 16 bits x 8 channels 16 bit reload counter e Includes clock prescaler fres 2 fres 2 fres 2 fres 2 fres 2 Free run timer 16 bits x 8 channels 16 bit free running counter signals an interrupt when overflow or match with compare register Includes prescaler lt 2 fRes 24 fres 2 fres 2 Timer data register has R W access PPG 16 bit 16 channels 16 bit x 8 channels in case of MD 3 1 16 bit down counter cycle and duty setting registers Interrupt at triggering cycle or duty match PWM operation and one shot operation Internal prescaler allows fres 2 fags 22 fngs 2 fres 2 as counter clock Can be triggered by software reload timer or external trigger event Reload timer 0 1 available as trigger for PPG 0 1 2 3 Reload timer 2 3 available as trigger for PPG 4 5 6 7 Reload timer 4 5 available as trigger for PPG 8 9 10 11 Reload timer 6 7 available as trigger for PPG 12 13 14 15 Input capture 16 bits x 8 channels 4 channels in case of MD 3 1 edge falling edge or rising amp falling edge sensitive Free run
38. INTPND13 R 00000000 00000000 00000000 00000000 00C3A44 Page 85 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00 8 00 00C3BO MSGVAL23 R MSGVAL13 R 00000000 00000000 00000000 00000000 00C3B44 00 3 8 00C3C0k reserved 00C400 CTRLR4 R W STATR4 RAN 1 00000000 00000001 00000000 00000000 00C404 ERRCNT4 R BTR4 R W 00000000 00000000 00100011 00000001 4 Control Register 00C408 INTR4 R TESTR4 RAN 00000000 00000000 00000000 0000000 00 40 BRPE4 R W CBSYNC4 2 00000000 00000000 Page 86 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 RW IFICMSK4 R W H 00000000 00000001 00000000 00000000 IF1MSK24 R W IF1MSK14 R W 00 414 11111111 11111111 41111111 11111111 AR IF1ARB24 RW 14 R W H 00000000 00000000 00000000 00000000 IF1MCTRA RAV 00041 00000000 00000000 IF1DTA14 R W IF1DTA24 R W H 00000000 00000000 00000000 00000000 4 IF 1 Register IF1DTB14 R W IF1DTB24 R W H 00000000 00000000 00000000 00000000 00 428 reserved 00 42 A IF1DTA24 R W IF1DTA14 R W H 00000000 00000000 00000000 00000000 T IF1DTB24 R W IF1DTB14 R W
39. Interrupt Vector Table Chap3 in previous Ver Chap6 Package and Pin Assignment Chap4 in a previous Ver Chap7 Electrical Characteristics Chap5 in a previous Ver 2007 05 01 Addition of information to be related Flash From 2 4 1 to 2 4 4 2007 05 30 Added information of specification change about port function 2 2 7 amp 6 2 2 Add Limitation 2 2 7 Add WRX1 6 2 2 Change function of Pin44 Changed a division point of power supply group 6 2 1 amp 6 2 2 Added package dimension in 6 1 Package 2007 06 18 Change of initial value in 4 IO map LVSEL 04 4 00000111 gt 00000101 REGSEL 04CEh 00000110 gt 00000100 2007 07 24 Changed of initial value in 4 IO map PFR00 00000000 11111111 PFRO1 2 PFRO3 PFRO04 5 PFRO6 PFRO7 PFRO8 9 PFR10 PFRO2 PFR03 and PFR04 changed only the description Because it is a part that IO doesn t have 00000000 gt 11111111 000000 gt 111111 00000000 gt 11111111 00000000 gt 11111111 lt lt 2007 09 05 2 1 Changed Core and Resource frequency Core frequency 80 MHz 100 MHz gt 96 MHz Resource frequency 40 MHz 50 MHz gt 48 MHz 2 2 2 Changed maximum operating frequency and PLL clock multiplier method Core clock 80 MHz 100 MHz gt 26 MHz 0 multiplied by 20 gt multiplied by 24 Page
40. PPCR23 R W 111 111 11 11111111 11111111 000 18 PPCR24 R W 25 4 26 R W 27 R W 11111111 H 11111111 11111111 Page 68 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 PPCR28 R W PPCR29 R W PPGR30 FRAM 000 1 11111111 11111111 PPGR32IRANT PPGR33IRAAT 000 20 44444444 44444444 000 24 reserved 000F3CH do not use Page 69 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 RAN 001000 DMADAO RAN 001004 DMASA1 RAN 001008 DMADA1 RAN 00100 DMASA2 RAN 001010H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMAC DMADA2 RAN 001014H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA3 RAN 001018H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADAS R W 00101 DMASA4 RAN 001020 DMADA4 RAN 001024
41. PPER43IRAM PPER14 RAW PPER15 RAW i 09090090 09090090 00000000 00000000 EE 16 R W 17 RW 18 R W 19 R W n 00000000 00000000 000 000 000 000 20 RAW 21 RAW 22 RAW 23 RAN 000 000 00 00000000 00000000 Page 67 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000ED8 PPER24 R W BPER2SIBAAn PPER26 R W 27 R W 4 00000000 90909090 00000000 00000000 000EDC PPER28 R W PPER29 R W PPER30JIRAA 4 00000000 00000000 90000000 90900000 BPER32JIBAAn 448 000 90000000 90000000 900900000 90909090 000 4 reserved 000 R bus Port PPCR00 R W PPCR01 R W PPGRO2FRAM PPGROSIRAN 3 000 00 11111111 11111111 11444444 14444444 Pull Up Down Control Register 000 4 PPCRO05 R W PPCRO06 R W PPCRO07 R W HHHH 111111 11111111 11111111 000 8 R W 9 R W 10 R W i ll 1 HHHH 000 PRPGRi2IRAA 4 PPCR14 R W PPCR15 R W n 44444114 HH 00000000 11111111 000 10 16 R W PPCR17 R W PPCR18 R W PPCR19 R W 00000000 00000000 111 111 111 111 000 14 PPCR20 R W R W 22 R W
42. R 00000000 00000000 00000000 00000000 00 4 4 00 4 8 00 4 00C4B0 MSGVAL24 R MSGVAL14 R 00000000 00000000 00000000 00000000 Page 89 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00 4 8 00C4BCH 00 4 0 reserved 00 4 066 CTRLR5 STATR5 RW 00000000 00000001 00000000 00000000 ER 5 R BTR5 R W H 00000000 00000000 00100011 00000001 CAN 5 Control Register INTR5 TESTR5 RW 00000000 00000000 00000000 0000000 5 R W N 00000000 00000000 rer CAN 5 5 RAN 5 5 RAW 00 510 00000000 00000001 00000000 00000000 IF 1 Register IF1MSK25 RAW IF1MSK15 R W 0005144 11111111 11111111 11111111 11111111 IF1ARB25 R W 15 R W 00000000 00000000 00000000 00000000 Page 90 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 5 RAW 00 51 00000000 00000000 eS 502558 15 R W IF1DTA25 R W i 00000000 00000000 00000000 00000000 IF1DTB15 RW IF1DTB25 R W 00000000 00000000 00000000 00000000 00 528 reserved 00C52CH ee IF1DTA25 R W IF1DTA15 R W 00000000 00000000 00000000 00000000 TR IF1DTB25 R W IF1DTB15
43. R W 00000000 00000000 00000000 00000000 00 538 reserved 00C53CH CAN 5 5 RAN IF2CMSK5 RAN 0005404 00000000 00000001 00000000 00000000 IF 2 Register 2 5 25 R W IF2MSK15 R W 000544 11111111 11111111 11111111 11111111 IF2ARB25 R W 2 15 R W H 00000000 00000000 00000000 00000000 00C54CH FAV res 00000000 00000000 Page 91 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 IF2DTA15 RW IF2DTA25 R W 00000000 00000000 00000000 00000000 EN IF2DTB15 RW IF2DTB25 R W H 00000000 00000000 00000000 00000000 00 558 reserved 00C55CH IF2DTA25 R W IF2DTA15 R W H 00000000 00000000 00000000 00000000 EE IF2DTB25 R W IF2DTB15 R W 00000000 00000000 00000000 00000000 00 568 reserved 00 57 CAN 5 25 R 5 00 580 00000000 00000000 00000000 00000000 Status Flags 00 584 00 588 00 58 25 NEWDT15 00000000 00000000 00000000 00000000 92 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 00 594 00 598 00 59 INTPND25 R INTPND 15 R
44. Reload Timer 4 TMCSRH4 TMCSRL4 PPG 8 9 000104 reserved RAN RAN 00000 0 000000 done TMRLR5 MW 5 H XXXXXXXX XXXXXXXX XXXXXXXX Reload Timer 5 TMCSRH5 TMCSRL5 PPG 10 11 0001DCu reserved RAW RAW 00000 0 000000 TMRLR6 W TMR6 XXXXXXXX Reload Timer 6 TMCSRH6 TMCSRL6 PPG 12 13 0001E4u reserved RAW RAW 00000 0 000000 TMRLR7 W TMR7 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Reload Timer 7 PPG 14 15 TMCSRH7 TMCSRL7 ADC 0001ECH reserved RAW RAW 00000 0 000000 Page 48 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 RAW TCCSO RAY Free Running 0001 XXXXXXXX XXXXXXXX res 00000000 Free Running 0001F44 res TCCS1 RW XXXXXXXX 00000000 G T RW Free Running 0001F84 RWI res RW Timer XXXXXXXX XXXXXXXX 00000000 OUR TCCS3 RW Free Running 0001 TCDT3 RAW res RW Timer3 XXXXXXXX XXXXXXXX 00000000 RW DMAG H 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACBO RW H 00000000 00000000 XXXXXXXX XXXXXXXX DMACA1 RM H 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB1 RM H 00000000 00000000 XXXXXXXX XXXXXXXX ME DMACA2 RA
45. field in slave mode LIN USART 2 and ICU 2 co operate for LIN sync field in slave mode LIN USART 3 and ICU 3 co operate for LIN sync field in slave mode LIN USART 4 and ICU 4 co operate LIN USART 5 and ICU 5 co operate LIN USART 6 and ICU 6 co operate for LIN sync field in slave mode LIN USART 7 and ICU 7 co operate for LIN sync field in slave mode for LIN sync field in slave mode for LIN sync field in slave mode Page 18 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 CAN 6 channels Supports CAN protocol version 2 0 part A and B Bitrates up to 1 Mbit s 32 message objects 1 channel with 64 message objects is under discussion Each message object has its own identifier mask Programmable FIFO mode concatenation of message objects Maskable interrupt Disabled Automatic Retransmission mode for Time Triggered CAN applications Programmable loop back mode for self test operation 400k fast mode 2 channels Master or slave transmission Arbitration function e Clock synchronization function Slave address and general call address detect function Transfer direction detect function Start condition repeat generation and detection function Bus error detect function Compatible to 2 standard and fast mode specification operation up to 400 kHz 10 bit addressing Includes clock d
46. parallel flash programming 3 Set offset by keeping FA 21 1 as described in section 2 4 3 Page 25 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 4 3 Parallel flash programming mode 2 4 3 1 Flash configuration in parallel flash programming mode Parallel Flash programming mode MD 2 0 111 FA 21 0 003F FFFFh 003F 0000h FFFFh 0000h 003D FFFFh 003D 0000h 003C FFFFh 003C 0000h 003B FFFFh 003B 0000h 003A FFFFh 003A 0000h 0039 FFFFh 0039 0000h 0038 FFFFh 0038 0000h 0037 FFFFh 0037 0000h 0036 FFFFh 0036 0000h 0035 FFFFh 0035 0000h 0034 FFFFh 0034 0000h 0033 FFFFh 0033 0000h 0032 FFFFh 0032 0000h 0031 FFFFh 0031 0000h 0030 FFFFh 0030 0000h 002F FFFFh 002F 002F DFFFh 002F 002F BFFFh 002F 002F 9FFFh 002F 8000h 002F 7FFFh 002F 6000h 002F 5FFFh 002F 4000h 002F 3FFFh 002F 2000h 002F 1FFFh 002F 0000h 8 8 8 SAQ 8KB FA 1 0 90 FA 1 0 10 16bit wite node DQ 15 0 DQ 15 0 Remark Always keep FA 0 0 and FA 21 1 in parallel programming mode Page 26 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 4 3 2 Pin connections in parallel programming mode Resetting after setting the MD 2 0 pins to 111
47. performed in word 32 bit length units 3 16 bit CPU mode CPU reads and writes in half word 16 bit length units Program execution from the Flash is not possible Actual Flash Memory access is performed in word 16 bit length units 4 Flash memory mode external access to Flash memory enabled Features through combination of Flash memory macro and FR CPU interface circuit Functions as CPU program data storage memory Enables access to 16 32 64 bit bus width Enables read write erase by CPU auto program algorithm Functions equivalent to MBM29LV400TC stand alone Flash memory product Enables read write erase by parallel Flash programmer auto program algorithm Auto program algorithm Embedded Algorithm TM 1 See MB91460 hardware manual for further details Page 21 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 4 2 CPU Mode 2 4 2 1 Flash configuration in CPU mode Flash memory map in CPU mode MD 2 0 00x MB91F467BA Fl ash CPU node 2 0 00 addr gu 0011 FFFFh 0010 0000h SA20 64KB SA21 64KB 0005 FFFFh 64KB SA9 64KB 0004 0000h 16011 read wite dat 31 16 dat 15 0 dat 31 16 dat 15 0 32bit read wite dat 31 0 dat 31 0 MB91F466BA Fl ash CPU node 2 0 00 addr
48. timer 0 and input capture 0 1 co operate Free run timer 1 and input capture 2 3 co operate Free run timer 4 and input capture 4 5 co operate Free run timer 5 and input capture 6 7 co operate Page 17 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Output compare 16 bits x 8 channels 4 channels in case of 3 1 Signals interrupt when a match with of 16 bit IO timer occurs An output signal can be generated Free run timer 2 and output compare 0 1 co operate Free run timer and output compare 2 3 co operate Free run timer 6 and output compare 4 5 co operate Free run timer 7 and output compare 6 7 co operate LIN USART LIN Local Interconnect Network 7 channels 4 channels in case of MD 3 1 Full duplex double buffer system 4 ch with 16 byte RX TX FIFO buffer each With parity without parity selectable 1 or 2 stop bits selectable 7 or 8 bits data length selectable NRZ type transfer format e Asynchronous synchronous communications selectable USART channel 0 only for asynchronous communication Master slave communication function multiprocessor mode Dedicated baud rate prescaler is embedded in each channel External clock is able to use as transfer clock Parity error frame error and overrun error detecting functions SPI compatible LIN master and slave LIN USART 0 and ICU 0 co operate for LIN sync
49. us output driving the ADC input and AVCC gt 4 5V Input leakage current In 1 1 uA 25 deg Sound generator Output voltage VoutHIGH VDD 0 5 VDD V VoutLow VSS VSS 0 5 V Output current Tout 5 mA PPG Output voltage VoutHIGH VDD 0 5 VDD V VoutLow VSS VSS 0 5 Output current Tout 5 mA IC Bus Interface Open Drain Output Output voltage VoutHIGH VDD VoutLow VSS VSS 0 5 loutLow 3mA Output current bot 3 mA Lock up time PLL1 0 1 0 2 ms valid for bidirectional tristate PAD cell 2 The protection diodes at the analog inputs are connected to the digital supply voltage 9 The longer alarm sense time can be selected for power safe modes in order to reduce the current consumption Page 128 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 7 3 Converter Characteristics A D Converter current Rating Parameter Symbol Unit Remark Minimum Typical Maximum Resolution 10 Bit Conversion error 3 0 LSB Overall error Non linearity 2 5 LSB Differential 1 9 LSB Non linearity Zero Reading Vor AVRL 1 5 AVRL 0 5 AVRL 2 5 LSB voltage Full scale reading Vest 3 5 AVRH 1 5 AVRH 0 5 LSB voltage Input current IA 2 4 4 7 mA AVCC Reference voltage IR 0 65 1 0 mA Page 129 of 125
50. 000 84 EPILR01 SA EPILR05 R W EPILR06 R W EPILR07 R W 90909090 000000 00000000 00000000 000 88 EPILR08 R W EPILR09 R W EPILR10 R W ERPs H 0 0 0 00 0 00000000 000 8 424 484 EPILR14 R W EPILR15 R W 90909090 90909090 00000000 00000000 000 90 EPILR16 R W EPILR17 R W EPILR18 R W EPILR19 R W 00000000 00000000 000 000 000 Page 66 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 EPILR20 R W EPILR21 R W EPILR22 R W EPILR23 R W 00 00 00 00000000 00000000 EPILR24 NW 54 26 R W 27 R W 00000000 09090090 00000000 00000000 Boreae EPILR28 R W EPILR29 R W EPIER291RAM EpPiLR3 IRAMI H 00000000 00000000 99099090 09090090 EPILR221RAW EPILR324BAW EPIER24I1RAN EPIER25IRAN 900 0 99009900 99999999 99009900 00000990 000EA4 5 reserved do not use 000 R bus RAW 1 RAW 2 RAM PPERO2 IRAN 000 00000000 00000000 09090090 09090090 Down Register PPER04IRAM PPER05 R W PPER06 RAW PPER07 RW H 09090090 000000 00000000 00000000 DONEC R W PPERO9 R W PPER10 R W PPERECIBAN 7 0 0 0 00 0 00000000 PPER42 RAM
51. 000000 000328 reserved 000320 IF1DTA23 R W IF1DTA13 R W 00000000 00000000 00000000 00000000 Page 83 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Dicas IF1DTB23 R W IF1DTB13 R W H 00000000 00000000 00000000 00000000 00 338 reserved 00C33CH CAN 3 IF2CREQ3 RAN IF2CMSK3 RAN 00C3404 00000000 00000001 00000000 00000000 IF 2 Register IF2MSK23 R W IF2MSK13 R W 006344 11111111 11111111 11111111 11111111 IF2ARB23 R W IF2ARB13 R W H 00000000 00000000 00000000 00000000 IF2MCTR3 RAN 00000000 00000000 IF2DTA13 R W IF2DTA23 R W H 00000000 00000000 00000000 00000000 IF2DTB13 RW IF2DTB23 R W B 00000000 00000000 00000000 00000000 00 358 reserved 00C35CH IF2DTA23 R W IF2DTA13 R W 00000000 00000000 00000000 00000000 IF2DTB23 R W IF2DTB13 R W 00000000 00000000 00000000 00000000 Page 84 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00 368 reserved 00 37 CAN 3 TREQR23 R TREQR13 RJ 00C3804 00000000 00000000 00000000 00000000 Status Flags 00 384 00 388 00C38CH EE NEWDT23 R NEWDT 13 00000000 00000000 00000000 00000000 00C3944 00C3984 00C39CH ER INTPND23 R
52. 0000000 Page 73 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00 084 00 088 00 08 20 NEWDT10 R 00000000 00000000 00000000 00000000 00 094 00 098 00 09 INTPND20 R INTPND10 R 00000000 00000000 00000000 00000000 4 00C0A8H 74 01125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 EE MSGVAL20 R MSGVAL10 8 H 00000000 00000000 00000000 00000000 MSGVAL40 IR MSGVAL30 IR 00 0 4 00 8 00 00 reserved 00 DE CTRLR1 R W STATR1 RW H 00000000 00000001 00000000 00000000 EN 1 R BTR1 R W H 00000000 00000000 00100011 00000001 CAN 1 Control Register INTR1 R TESTR1 RW H 00000000 00000000 00000000 0000000 BRPE1 00000000 00000000 1 RAW IF1CMSK1 RAN 001104 00000000 00000001 00000000 00000000 IF 1 Register IF1MSK21 RAW IF1MSK11 R W 11111111 11111111 11111111 11111111 Page 75 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary data
53. 0000000 00000000 BGR102 RW BGR002 R W BGR103 R W BGR003 R W 00000000 00000000 00000000 00000000 Generator USART LIN 0 7 PE BGR104 RW BGRO004 RW BGR105 RW BGRO05 R W H 00000000 00000000 00000000 00000000 uie BGR106 R W BGRO006 RW BGR107 RW BGROO7 R W H 00000000 00000000 00000000 00000000 000090 Reserved 0000 42 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 IBCR0 RAV IBSRO R ITBAHO R W ITBALO RW 00000000 00000000 00 00000000 ITMKHO R W ITMKLO RW ISMKO R W ISBAO R W 000004 00 11 11111111 01111111 0000000 200 IDARO R W ICCR0 R W ios 00000000 0011111 IBCR1 RW IBSR1 R ITBAH1 RAN ITBAL1 RW 00000000 00000000 00 00000000 ITMKH1 RAW ITMKL1 RAW ISMK1 RAW ISBA1 R W 0000 0 00 11 11111111 01111111 0000000 IDAR1 RW ICCR1 RW s 00000000 0011111 m 0000 8 Reserved 0000 GCN10 R W GCN20 R W PPG Control 0001004 00110010 00010000 9m 0000 0 3 GCN11 RW GCN21 RW PPG Control 000103 00110010 00010000 58 0000 4 7 GCN12 RW GCN22 RW PPG Control 0001084 00110010 00010000 res 0000 8 11 PTMROO R PCSR00 W ius H 11111111 11111111 XXXXXXXX XXXXXXXX Page 43 of 125 European MCU Desi
54. 0000000 00000000 Status Flags 000284 00 288 00028601 EN NEWDT22 R NEWDT12 H 00000000 00000000 00000000 00000000 000294 00 298 Page 81 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00 29 INTPND22 INTPND12 H 00000000 00000000 00000000 00000000 00 2 4 00C2A84 00 2 MSGVAL22 RJ MSGVAL12 8 H 00000000 00000000 00000000 00000000 00C2B4 00 288 00C2BC 00 2 0 reserved CTRLR3 R W STATR3 RW H 00000000 00000001 00000000 00000000 Page 82 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 ERRCNT3 RJ BTR3 RW H 00000000 00000000 00100011 00000001 INTR3 R TESTR3 RW H 00000000 00000000 00000000 X0000000 RW 00C30Ch 00000000 00000000 3 R W IF1CMSK3 RAN 0003101 00000000 00000001 00000000 00000000 IF 1 Register IF1MSK23 P W IF1MSK13 P W 006314 41111111 11111111 41111111 11111111 AER IF1ARB23 RW IF1ARB13 RW H 00000000 00000000 00000000 00000000 IF1MCTR3 R W 00C31Ch 00000000 00000000 res IF1DTA13 R W 23 R W H 00000000 00000000 00000000 00000000 IF1DTB13 R W IF1DTB23 R W H 00000000 00000000 00000000 00
55. 00000000 00000000 00000000 00000000 00 5 4 00 5 8 00 5 MSGVAL25 MSGVAL15 8 00000000 00000000 00000000 00000000 00 584 00C5B8u 00C5BCu Page 93 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 00 5 0 reserved BCTRL R W EDSU MPU 0000 7 77777777 11111100 00000000 BSTAT RAN 00F0044 r 000 00000000 10 000000 BIAC R 00 008 00000000 00000000 8 OOFOOCH 7 00000000 00000000 BIRQ R W OOF010u 7 00000000 00000000 00F0144 reserved 00 01 BCRO RAN O0OF020u C 00000000 00000000 00000000 BCR1 RW 00F0244 C CY C r 00000000 00000000 00000000 BCR2 RAN 00 028 00000000 00000000 00000000 BCR3 RAN OOFO2CH 00000000 00000000 00000000 00F030H BGBRA IRAAT Page 94 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00F034H BCR5 RAMI 00F038H BGRS FRAM 00F03CH RAM 00 040 reserved 00F07CH BADO RW EDSU MPU 00 080 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD1 RAN 00F084H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD2 RAN 00F
56. 01 0000h OOOL FFFFh 0002 0000h 0002 FFFFh 0003 0000h 0003 FFFFh 0004 0000h 0005 FFFFh 0006 0000h 0007 FFFFh 0008 0000h 0009 FFFFh 000A 0000h 000B FFFFh 000C 0000h 000D FFFFh 000 00001 OOOF FFFFh 0010 0000h 0013 FFFFh 0014 0000h 0017 FFFFh 0018 0000h 001B FFFFh 001C 0000h OOLF FFFFh 0020 0000h 0027 FFFFh 0028 0000h O02F FFFFh 0030 0000h 0037FFFFh 0038 0000h 003F FFFFh 0040 0000h 0047 FFFFh 0048 0000h O04F FFFFh 0050 0000h FFFF FFFFh MB91F467BA Byte Data Halfword Data Word Data Flash Cache 8 kB or Instruction RAM 8 kB Flash Control Flash l Cache Control Boot ROM 4 kB External Bus Cache 4 kB or Instruction RAM 4 kB Data RAM 24 kB Instruction Data RAM 16 kB Flash Memory Area 1024 KB 64 kB External Bus Area depending on ROMA setting External Bus Area External Bus Area 50 7 setting fixed to internal area OOOF FFFFh 0010 0000h O013FFFFh 0014 0000h 0017 FFFFh 0018 0000h 001B FFFFh 001C 0000h 001F FFFFh 0020 0000h 0027 FFFFh 0028 0000h 002F FFFFh 0030 0000h 0037 FFFFh 0038 0000h 003F FFFFh 0040 0000h 0047 FFFFh 0048 0000h 004F FFFFh 0050 0000h FFFF FFFFh MB91F466BA Byte Data Halfword Data 1 O Word Data Flash Memory Cache 8 kB or Instruction RAM 8 kB Flash
57. 014 8008 BSV2 0x0014 800C 1 Use a read access byte or halfword to this address to synchronize the CPU operation e g the interrupt acceptanceof the CPU to a preceding write access to the resources on R bus e g to an interrupt flag on followingaddresses 0x0000 0x01FF 0x0280 0x037F 0x0400 0x063F and 0x0C00 0x0FFF 2 Use a read access byte or halfword to this address to synchronize the CPU operation e g the interrupt acceptance of the CPU to a preceding write access to the CANs on D bus e g to an interrupt flag on following addresses 0xC000 0xFFFF Note makes valid after write to ELVR When you want to write to EIRR just after write to ELVR you must write to EIRR after dummy read ELVR Note reserved areas shall not be used at all Page 100 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 5 Interrupt Vector Table This section shows the allocation of interrupts and interrupt vector interrupt register Reset 0 00 0x3FC Mode vector 1 01 0x3F8 0x000FFFF8 System reserved 2 02 0x3F4 0x000FFFF4 System reserved 3 03 0x3F0 System reserved 4 04 0x3EC CPU supervisor mode INT 5 instruction 6 5 05 0x3E8 0x000FFFE8 Memory Protection exception 6 6 06 0x3E4 0x000FFFE4 Co processor fault trap B 7 07
58. 088H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD3 RAN 00F08CH XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD4 RAN 00F090H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD5 RW 00 094 BAD6 RAN 00F098H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD7 RAN 00F09CH XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD8 RAN OOFOA0 XXXXXXXX XXXXXXXX XXXXXXXX Page 95 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 BAD9 RW 4 BAD10 RW 8 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD11 RW XXXXXXXX BAD12 RW 00FOBOk XXXXXXXX XXXXXXXX BAD13 RW 00FOB4 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD14 R W 00F0B84 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BAD15 RW XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EDSU MPU 00 46 48 47 48 00 8 BAD48 IRAN BAD 9 FRAM 00 20 0 4 84524 96 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 OOFOD8y 2
59. 11 00 00000000 ASR1 RM 1 RW H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX TET ASR2 RAN ACR2 RAN B ASR3 RM ACR3 RAN 000550 ASR4 RAN ACR4 RAN i ASR5 RAN ACR5 RAN H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00658 ASR6 RM ACR6 RAN XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ASR7 RM ACR7 RW AWRO RW AWRi RW 01111111 11111 11 XXXXXXXX XXXXXXXX AWR2 RW AWR3 RW 4 AWR4 RW AWR5 RW 4 Page 59 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 EN AWR6 RA AWR7 RW H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX MCRA RAW MCRB RA 0006704 XXXXXXXX XXXXXXXX reserved 0006744 reserved e IOWRO R W IOWR1 R W IOWR2 R W IOWR3 R W H XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 00067 reserved CSER RW CHER RW TCR RW 0006804 00000001 11111111 0000 RCRH RAN RCRL R W 000684 00XXXXXX XXXX0XXX reserved 000688 reserved 0007 8
60. 11 11111111 20 RW IF1ARB10 RW H 00000000 00000000 00000000 00000000 RW 00 01 00000000 00000000 IF1DTA10 R W 20 R W H 00000000 00000000 00000000 00000000 0 IF 1 Register IF1DTB10 R W IF1DTB20 R W H 00000000 00000000 00000000 00000000 00 028 reserved 00 02 IF1DTA20 R W IF1DTA10 R W H 00000000 00000000 00000000 00000000 IF1DTB20 RAW IF1DTB10 R W H 00000000 00000000 00000000 00000000 00 038 reserved 00C03CH Page 72 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 EN IF2CREQO RW IF2CMSKO RAN H 00000000 00000001 00000000 00000000 IF2MSK20 R W IF2MSK10 RW 000044 41111111 11111111 11111111 11111111 20 RW 10 RW H 00000000 00000000 00000000 00000000 IF2MCTRO RAN 00 04 00000000 00000000 IF2DTA10 R W IF2DTA20 R W H 00000000 00000000 00000000 00000000 IF 2 Register IF2DTB10 R W IF2DTB20 R W H 00000000 00000000 00000000 00000000 00 058 reserved 00C05CH IF2DTA20 R W IF2DTA10 R W H 00000000 00000000 00000000 00000000 IF2DTB20 RAW IF2DTB10 R W H 00000000 00000000 00000000 00000000 00 068 reserved 00 07 00 080 IE AME Status Flags 00000000 00000000 00000000 0
61. 2 00FODCH BAD23 BAD24 IRAN 4 BAD25 00 0 8 BAD26 IRAN 27 18 OOFOF4y 20 00FOF8H BAD30 IRAAMJ BAD241 IRAN 00 100 reserved 010000 2 way eet 013FFC4 640000 0167FG 2 Page 97 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 014000 04 ice G 017 j 0180004 Gaehe RAMwayt 01BEFC 018000 0187 01 000 2 ee 101G000 01GZFG 020000 MB91F467BA 466BA 465BA 464BA D RAM size is 24kB DBUS RAM 02 000 24 02 data access is 0 waitcycles 030000H MB91F467BA 466BA 465BA 464BA I D RAM size is 16kB GP RAM 0300004 FLASHIF instruction access is 0 waitcycles data access is 1 waitcycle 16 MB91F467BA 500 area 128 Flash Memory OSFFFC MB 91F 465BA 464BA Not available in this area 1024kB 64kB MBO1F 466 Flash Memory 082030 ROMS01 area 128 768 64kB 07FFFC MB91F465BA 464BA Not available in this area H MBO1F 465BA Flash Memory 512KB 32KB ROMS02 area 128 aa MB91F464BA Not available in this area MB91F464BA H Flash Memory 384kB 3
62. 22 2 4 2 1 Flash configuration in CPU 22 2 4 2 2 Flash access timing settings in CPU mode 24 2 4 2 3 Address mapping from CPU to parallel programming 25 2 4 3 Parallel flash programming 26 2 4 3 1 Flash configuration in parallel flash programming mode 26 2 4 3 2 Pin connections in parallel programming 27 Bie Ary 2 18513601 u q 28 2441 q uu Susu PB 28 2442 Security Vector ec vie dece eed kasa 28 2 4 4 3 Security Vector 31 2 4 4 4 Register description for Flash 77 32 3 Recommended SENGS een 33 3 1 Phil ane 33 3 2 Flash interface settingsS 34 93 35 Clock uu u spres 35 JO Ma Q q astan eee 39 Interrupt Vector Table u EST 101 Page 5 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 6 Package and Pin Assignment
63. 2kB 0 0000 ROMS03 area 128 0 0000 ROMS04 area 128kB ODFFFCu Page 98 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 0 0000 505 area 128 OFFFF4 FMV R OFFFFE 06 00 00 004 Fixed Reset Mode FRV R Vector 00 00 BF 91 467 506 area 256kB 1024KB 64KB MB 91F 466BA 465B A 464BA Not available in this area 13FFFCH 91 466 Flash Memory 768 64kB MB91F465BA Flash Memory 140000 ROMS07 area 256 512 32KB MB91F467BA 466BA 507 size is 64kB 140000 14 17FFFCy MB91F465BA 464BA ROMS07 size is 32kB 148000 14 91 464 Flash Memory 384kB 32kB 5 ROMS08 area 256kB 1 1 0000 ROMS09 area 4255kB 200000 ROMS10 area 4512KB 2 280000 ROMS11 area 4512kB ROMS13 area 451218 3FFFFCu Page 99 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Ext bus Write operations to address OFFFF8x and are not possible When reading these addresses the values shown above will be read Flash Security Vectors are located as follows FSV1 0 0014 8000 5 1 0x0014 8004 FSV2 0 0
64. 4 Pad Layout 2006 03 08 4555 07 6 A6 07 7 37 P06 0 A8 P06 1 A9 P06 2 A10 P06 3 A11 P06 4 A12 06 5 A13 P06 6 A14 P06 7 A15 P05 0 A16 P05 1 A17 05 2 A18 P05 3 A19 P05 4 A20 P05 5 A21 VDD35 4555 1 0 D16 PO1 1 D17 1 2 D18 P01 3 D19 P01 4 D20 PO1 5 D21 1 6 022 P01 7 D23 0 0 024 0 1 025 P00_2 D26 00 3 027 00 4 D28 P00_5 D29 P00_6 D30 P00_7 D31 VDD35 7 4 7 7 2 2 7 1 1 aa 7_0 P15 3 OCU3 P15 2 OCU2 TOT2 o 4 P15 1 OCU1 TOT1 P15 0 OCUO TOTO P14 3 ICU3 TINS TTG11 3 P14 2 ICU2 2 TTG10 2 DDB 555 P28 7 15 555 P28 AN8 P29 7 7 29 6 AN6 P29 5 P29 4 29 3 P29 2 AN2 P29 1 P24 2 INT2 P28 6 P29 0 ANO P28 5 P28 4 AN12 P28 3 AN11 P28 2 AN10 P28 1 P24 3 INT3 P14 0 1CUO TINO TTG8 0 P14 1 1CUL TINL TTGY1 1 x 5 3 MB91F 467BA 466 465 464 with external bus interface MD 3 4 E 555 P10_0 SYSCLK PO9 0 CSXO PO9 1 CSXl 0 WRXO 4 RDX 7 RDY WRXL P24 1 INT1 P23 0 RXO INT8 P23 1 TXO P23 2 RX1 INT9 x 11 00000800 Aj al d VDDS AVCCS AVRHS AVSS ALARM 0 18 6
65. 8 External Interrupt 14 30 1E 0x384 0x000FFF84 ICR07 0x447 External Interrupt 15 31 1F 0x380 0x000FFF80 Reload Timer 0 32 20 0x37G 0x000FFF7C 4 32 ICR08 0x448 Reload Timer 1 33 21 0x378 0x000FFF78 5 33 Reload Timer 2 34 22 0x374 0x000FFF74 34 ICR09 0x449 Reload Timer 3 35 23 0x370 0x000FFF70 35 Reload Timer 4 36 24 0x36C 0x000FFF6C 36 ICR10 0x44A Reload Timer 5 37 25 0x368 0x000FFF68 37 Page 102 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Reload Timer 6 38 26 0x364 0x000FFF64 38 ICR11 0x44B Reload Timer 7 39 27 0x360 0x000FFF60 39 Free Run Timer 0 40 28 0 35 5 40 ICR12 0x44G Free Run Timer 1 41 29 0x358 0x000FFF58 41 Free Run Timer 2 42 2A 0x354 0x000FFF54 42 ICR13 0x44D Free Run Timer 3 43 2B 0x350 0x000FFF50 43 Free Run Timer 4 44 2C 0x34C 0 000 44 14 0 44 Free 5 45 2D 0x348 0x000FFF48 45 Free Run Timer 6 46 2E 0x344 0 000 44 46 15 0x44F Free Run Timer 7 47 2F 0x340 0x000FFF40 47 CAN 0 48 30 0x33C ICR16 0x450 CAN 1 49 31 0x338 0x000FFF38 2 50 32 0 334 0x000FFF34 ICR17 0x451 CAN 3 51 33 0x330 0x000FFF30 CAN 4 52 34 0 32 0x000FFF2C ICR18 0x452 CAN 5 53 35 0x328 0x000FFF28 USART LIN 0 RX 54 36 0x324 0x000FFF24 6 48 ICR19 0x453 USART LIN
66. 80 00000000 00000000 00000000 00000000 Status Flags 0001841 00 188 00C18CH Page 77 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00C1904 NEWDT21 R NEWDT11 00000000 00000000 00000000 00000000 00 194 00 198 00 19 INTPND21 R INTPND11 R 00000000 00000000 00000000 00000000 00 1 4 00 1 8 00C1ACH 00C1BOH MSGVAL21 R MSGVAL11 R 00000000 00000000 00000000 00000000 00C1B44 00C1B8H Page 78 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00C1BCH 00 1 0 reserved 00C1FCy CTRLR2 STATR2 RAN 00000000 00000001 00000000 00000000 R R W H 00000000 00000000 00100011 00000001 2 Control Register INTR2 8 TESTR2 RW 00000000 00000000 00000000 0000000 BRPE2 00000000 00000000 2 2 RAW IF1CMSK2 RAN 00 210 00000000 00000001 00000000 00000000 IF 1 Register IF1MSK22 R W IF1MSK12 R W 000214 11111111 11111111 11111111 11111111 IF1ARB22 R W IF1ARB12 R W 00000000 00000000 00000000 00000000 2 RAN
67. AMHz RT x C mode 40 uA f lt 100kHz stop mode Isstop 39 Alarm comparator Threshold voltages overvoltage 5 5 5 5 V external 4 1 divider undervoltage 25 5 sAVCC 2 5 5 Switching hysteresis V TAHYS 100 200 mV at VTAL Alarm sense time tas 0 1 100 us selectable by register Input resistance Rin 5 MQ Digital Inputs CMOS Schmitt Trigger High voltage range 0 7 VDD VDD V Low voltage range Vit VSS 0 3 VDD V CMOS Automotive Schmitt Trigger High voltage range 0 8 VDD VDD V Low voltage range Vit VSS 0 5 VDD V hysteresis voltage 0 2 0 5 V Input capacitance CiN tbd pF Input leakage current 1 1 Pull up resistor Rup 50 Pull down resistor 50 25 deg Digital outputs Output H voltage VDD 0 5 VDD V load 2 5 Output L voltage VSS VSS 0 4 V load 2 bmA Page 127 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 AMHz gt 16 96MHz Parameter Symbol min typ max Unit Condition ADC inputs 2 Reference voltage AVRH AVCC 0 75 AVCC input AVRL AVSS AVCC 0 25 V Input voltage range Vimax AVRH V Vimin AVRL V Input resistance 10 Input capacitance 17 pF Impedance of external 4 0 sampling time of 1 6
68. CU4 TIN4 TTG12 4 VDD5R P14 5 1CU5 TINS TTG13 S VDD5R P14 6 ICU6 TING TTG14 6 VCC18C P14 7 1CU7 1 7 TTG15 7 VSS5 P15 4 0 NMIX 15 5 0CU5 TOTS INITX P15 6 0CU6 TOT6 XIA P15 7 0CU7 TOT7 XOA P17 0 PPGO VSS5 17 1 1 17 2 2 P17 3 PPG3 MD 3 P17 4 PPG4 MONCLK 17 5 5 MD 2 P17 6 PPG6 MD 1 P17 7 PPG7 MD 0 0035 VSS5 20 2 ZNYCK2 8 ji 9 4 5 58 pgri SU 111 PETAT n 2 Sel T mi Mi i 31 oS 2 9 d e MN d Pi 18884886 2 8 88 NN Page 11101125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Pin I O PFR 1 EPFR 1 Special Type Comments 79 1 z 1 4 MHz quartz oscillator 80 TO00_0 83 X1A TO01_1 32 kHz quartz oscillator 82 X0A TO01 0 77 MONCLK TC10_0 Clock monitor output 23 P14 7 ICU7 TIN7 TIN7 TTG15 7 1 22 P14 6 ICU6 TIN6 TIN6 TTG14 6 1 21 P14 5 ICU5 TIN5 TIN5 TTG13 5 TPO4 1 20 14 4 ICU4 TIN4 TIN4 TTG12 4 TP04_1 ICU Input Capture Unit input TIN Reload Timer Event input 133 14 3 ICU3 TIN3 TIN3 TTG11 3 TP04 0 TTG Prog Pulse Generator Event input 132 14 2 ICU2 TIN2 TIN2 TTG10 2 4 0 131 14 1 ICU1 TIN1 TIN1 TTG9 1 04 0 130 P14 0 ICU0 TIN0 TIN0 TTG8 0 04
69. FUJITSU SEMICONDUCTOR 91 467 466 A 465B A 464BA preliminary datasheet MB91460 series European MCU Design Centre EMDC Fujitsu Microelectronics Europe GmbH Pittlerstr 47 63225 Langen Germany Fujitsu and Fujitsu Microelectronics Solutions Limited F MSL Version 0 27 File mb91f467ba shortspec r2 0 doc European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Revision History 0 13 2006 01 25 Corrections for external bus interface option Remove of package information MB91F467BA will be delivered in a QFP 144 package with pure Sn pin plating the related package number is to be defined Use UART3 instead of UART2 2006 02 14 Upgrade tables and feature lists to refer to external bus interface option 0 15 2006 02 16 Updated pinning added 1 USART in non external bus mode exchanged against WRX 0 2006 03 08 Changed pinning for 6ch CAN 32ch ADC and NMI 2006 03 09 Corrected operation supply voltage range 2006 06 08 Delete ESD Protection of Electrical Characteristics Added condition of current consumption 0 19 2006 07 20 Add a postscript to function limitation in 2 1 Overview Table Add the 6 IO Map 0 20 2006 07 25 1 1 Block Diagram change IO Voltage 2 2 1 Memory Map change not available area 2 2 7 2 2 8 correct memory capacity 2 3 correct feature of Clock supervisor 6 Add a postscript to function limitation
70. H 00000000 0000XXXX XXXXXXXX XXXXXXXX DMACB2 RM H 00000000 00000000 XXXXXXXX XXXXXXXX DMACA3 RW 00000000 0000XXXX Page 49 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00021C DMACB3 RAN 00000000 00000000 000220 DMACA4 RAN 00000000 0000XXXX XXXXXXXX XXXXXXXX 000224 DMACB4 RAN 00000000 00000000 XXXXXXXX XXXXXXXX 000228 reserved 00023Cy DMACR RW 0002404 00 0000 reserved 0002444 reserved 00024 000250 DMATESTO R W 00000000 00000000 0000 DMA do not use 000254 DMATEST1 R XXXXXXXX XXXXX000 00000000 00000000 0002584 reserved 0002 Input ICS045 R W ICS67 RAN 000200 res 00000000 res 00000000 000204 4 R 5 R Page 50 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 IPCP6 R IPCP7 OCS45 R W OCS67 R W 0002DCu 0 00 0000 00 0 00 0000 00 Output OCCP4 RM OCCP5 RAN 0002 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX oo een OCCP6 RM OCCP7 RAN H XXXXXXXX XXXXXXXX XXXXXXXX
71. NT External Interrupt input 48 2 RX1 INT9 4 0 47 P23 1 TXO 4 0 46 P23 0 RXO INT8 TP04_0 129 24 3 INT3 04 0 INT External Interrupt input 128 24 2 INT2 5 TP04_0 45 P24_1 INT1 5 4 0 104 ALARM 0 02 0 ALARM Comparator input 125 P28 7 AN15 0 124 P28 6 AN14 0 123 P28 5 AN13 0 122 P28 4 12 0 AN ADC Analog input 121 P28 3 11 0 120 28 2 10 5 0 119 28 1 9 5 0 118 28 0 8 2 0 117 P29 7 7 0 116 29 6 AN6 0 115 P29 5 ANS 0 114 29 4 0 V AN3 TP03_0 AN ADC Analog input 112 P29_2 AN2 5 _0 111 P29_1 AN1 5 0 110 29 0 AN0 5 0 35 7 D31 1 34 6 030 TP04_1 33 P00_5 D29 4 1 32 P00_4 D28 4 1 A P00 3 _ 4 1 External Bus Data Lines 30 P00_2 D26 TP04_1 29 P00_1 D25 2 TP04_1 28 P00_0 D24 1 27 7 023 4 1 External Bus Data Lines 26 P01_6 D22 TP04_1 25 P01_5 D21 TP04_1 24 P01_4 D20 TP04_1 Page 118 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Pin I O 1 EPFR 1 Special Type
72. R33IRAM 44 PODR35IRAN 000 20 90000000 90000000 90000000 90000000 000 24 reserved 000E3CH R bus Port 000 40 PILROO R W 1 R W PIERO2 BAN Input Level 00000000 00000000 90000000 90900909 Register 000 44 44 PILRO5 R W PILR06 R W PILR07 R W 90000000 000000 00000000 00000000 000 48 8 RAW PILRO9 R W PILR10 R W 0 0 0 00 0 00000000 000E4C 24 PILR14 R W PILR15 R W 99999999 90000000 00000000 00000000 Page 65 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000 50 PILR16 R W PILR17 R W PILR18 R W PILR19 R W 00000000 00000000 000 000 000 000 54 PILR20 R W PILR21 R W PILR22 RAW PILR23 R W 000 000 00000000 00000000 000 58 PILR24 R W 2545 PILR26 R W PILR27 R W H 00000000 90909090 00000000 00000000 000 5 PILR28 RAW PILR29 R W PILR304RAM RAM 00000000 00000000 90000000 50000000 000 60 HE HE 90909090 90909090 90909090 90909090 000 64 000 7 R bus EPILR00 R W EPILR01 R W EPILR02 EPHRO34RAM 000E804 00000000 00000000 90909090 90909090 Register
73. SCK7 CK7 P18 5 5017 18 4 SIN7 P18 2 5 6 6 P18 1 5076 18 0 51 6 19 6 5 5 5 19 5 5015 P19 4 SINS 19 2 5 4 4 P19 1 5074 19 0 51 4 555 VDDS VDD5R VDD5R VCC18C 4555 NMIX INITX XOA 4555 x0 MD 3 MONCLK MD 2 MD 1 MD 0 4555 Page 116 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Pin I O PFR 1 EPFR 1 Special Type Comments 79 z E 1 4 MHz quartz oscillator 80 X0 TO00_0 83 X1A 1 32 kHz quartz oscillator 82 XOA 1 0 77 MONCLK TC10 0 Clock monitor output 133 14 3 ICUS TIN3 TTG11 3 TP04_0 4 ICU Input Capture Unit input 132 14 2 ICU2 TIN2 TIN2 TTG10 2 TIN Reload Event input 131 14 1 ICU1 TIN1 TIN1 TTG9 1 TP04 0 TTG Prog Pulse Generator Event input 130 14 0 ICU0 TIN0 TIN0 TTG8 0 04 0 137 15 3 OCU3 TOT3 4 0 4 0 136 15 2 OCU2 TOT2 1 OCU Output Compare Unit waveform out 135 P15 1 OCU1 TOT1 1 4 0 TOT Reload output 134 P15 0 OCU0 0 71 16 7 PPG15 ATGX TP04_0 70 P16_6 PPG14 04 0 69 P16 5 PPG13 SGO 04 0 TP04 0 Prog Pulse Generator waveform out 68 P16_4 PPG12 SGA 2 ATGX ADC external trigger input 67 16 3 PPG11 5 4 0 SGO Sound Generator waveform out
74. SV2 4 set to 0 set to 1 FSV2 5 set to 0 set to 1 FSV2 6 set to 0 set to 1 FSV2 7 set to 0 set to 1 FSV2 8 set to 0 set to 1 FSV2 9 set to 0 set to 1 FSV2 10 set to 0 set to 1 FSV2 11 set to 0 set to 1 FSV2 1 2 set to 0 set to 1 FSV2 13 set to 0 set to 1 FSV2 14 set to 0 set to 1 FSV2 15 set to 0 set to 1 FSV2 16 set to 0 set to 1 not available FSV2 17 set to 0 set to 1 not available FSV2 18 set to 0 set to 1 not available FSV2 19 set to 0 set to 1 not available FSV2 20 set to 0 set to 1 not available FSV2 21 set to 0 set to 1 not available Page 31 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 FSV2 22 set to 0 set to 1 not available FSV2 23 set to 0 set to 1 not available FSV2 24 set to 0 set to 1 not available FSV2 25 set to 0 set to 1 not available FSV2 26 set to 0 set to 1 not available FSV2 27 set to 0 set to 1 not available FSV2 28 set to 0 set to 1 not available FSV2 29 set to 0 set to 1 not available FSV2 30 set to
75. XXXXXXX XXXXXXXX PPG 7 PDUTO7 W PCNHO7 RW PCNLO7 RW H XXXXXXXX 0000000 000000 0 PTMRO8 PCSR08 W H 11311111 11111111 XXXXXXXX XXXXXXXX PPG8 PDUTO8 W RW PCNLO8 RW H XXXXXXXX XXXXXXXX 0000000 000000 0 PTMRO9 PCSR09 W H 11111111 11111111 XXXXXXXX XXXXXXXX PPG 9 PDUT09 W 9 RW 09 RW H XXXXXXXX XXXXXXXX 0000000 000000 0 PTMR10 PCSR10 W H 11111111 11111111 XXXXXXXX XXXXXXXX PPG 10 PDUT10 W PCNH10 RW PCNL10 RW H XXXXXXXX XXXXXXXX 0000000 000000 0 PTMR11 R PCSR11 W PPG 11 H 11311111 11111111 XXXXXXXX XXXXXXXX Page 45 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00016 PDUT11 W XXXXXXXX XXXXXXXX PCNH11 RAN 0000000 PCNL11 000000 0 000170 000174 000178 00017CH reserved 000164 S k a IPCP2 IPCP3 R 0001868 Gr Compare EN 2 RAW RW XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Page 46 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27
76. XXXXXXXX 0002 8 reserved 0002 TCDT4 RW TCCS4 RW ES Ke B XXXXXXXX 00000000 ICU 45 EN TCDT5 RM TCCS5 RA 27 XXXXXXXX XXXXXXXX 00000000 ICU 6 7 RAW TCCS6 Rw Free Running 0002F8u 61 res 6 Timer 6 XXXXXXXX XXXXXXXX 00000000 OCU 4 5 TCDT7 RAW Tccs7 pw Free Running 0002FCH res Timer 7 XXXXXXXX XXXXXXXX 00000000 OCU 6 7 Up Down 00000 UDRC1 W UDRCO W UDCR1 R UDCRO R Coins 00000000 00000000 00000000 00000000 0 1 UDCCHO R W UDCCLO RW UDCSO R W 0003911 00000000 00001000 00000000 Page 51 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 UDCCH1 R W UDCCL1 RW UDCS1 RW 0003084 00000000 00001000 00000000 00030 reserved 0003104 0003144 0003184 res 00031 reserved GCN13 RW GCN23 R W PPG Control 000320 00110010 00010000 0000 12 15 0003244 reserved 00032 T PTMR12 R PCSR12 W H 11111111 11111111 XXXXXXXX XXXXXXXX PPG 12 PDUT12 W PCNH12 RW PCNL12 RW H XXXXXXXX XXXXXXXX 0000000 000000 0 PTMR13 R PCSR13 W H 11111111 11111111 XXXXXXXX XXXXXXXX Page 52 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00033 PDUT13 W
77. XXXXXXXX XXXXXXXX 000400 reserved 00043 Interrupt ICR00 RW ICRO1 RAW ICRO2 RW ICRO3 RAW 0004408 11111 11111 11111 11111 Control Unit T ICRO4 RW ICRO5 RW ICRO6 RW ICRO7 RAY 11111 11111 11111 11111 00138 ICR08 RW ICR09 RW ICR10 RW ICR11 RAW H 41111 11111 11111 11111 ICR12 RAW ICR13 RW ICR14 RAW ICR15 RW 211114 111 11111 11111 EE ICR16 RW ICR17 RW ICR18 RW ICR19 RAW h 11111 11111 11111 11111 P ICR20 RAN ICR21 RW ICR22 R W ICR23 RW 11111 11111 11111 11111 306458 ICR24 R W ICR25 R W ICR26 R W ICR27 R W 11111 11111 11111 11111 Page 55 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 00045 ICR28 RW ICR29 RAN ICR30 RAN ICR31 RAN 11111 11111 11111 11111 000460 ICR32 RAN ICR33 RW ICR34 RAN ICR35 RAN 11111 11111 11111 11111 ICR36 RAN ICR37 RAN ICR38 RAN ICR39 RAN 4 11111 11111 11111 11111 000468 ICR40 R W ICR41 R W ICR42 RAN ICR43 RAN 11111 11111 11111 00046 ICR44 RW ICR45 RAN ICR46 RAN ICR47 RAW 11111 411111 5511111 5441111 000470 ICR48 R W ICR49 R W ICR50 RAN ICR51 RAN 11111 11111 11111 41111 er ICR52 RW ICR53 RW ICR54 RAN ICR55 RW TI
78. alibration Calibration of the RTC timer in 32 kHz or RC oscillator operation based on the more accurate 4 MHz quartz is possible Main oscillation stabilization timer 23 bit counter for main oscillation stabilization wait when running in sub clock mode Generates an interrupt when stabilization time has elapsed Sub oscillation stabilization timer 15 bit counter for sub oscillation stabilization wait when running in main clock mode Generates an interrupt when stabilization time has elapsed Page 20 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 4 Embedded Program Data Memory 2 4 1 Flash features MB91F467BA 1024 Kbyte 64 Kbyte Flash MB91F466BA 768 Kbyte 64 Kbyte Flash MB91F465BA 512 Kbyte 32 Kbyte Flash MB91F464BA 384 Kbyte 32 Kbyte Flash Power Single 3 0 5 5V supply Programmable wait state for read write access Flash security with security vector at 0x0014 8000 0x0014 800F Basic specification Same as MBM29LV400TC except size and part of sector configuration Operation modes 1 64 bit CPU mode CPU reads and executes programs in word 32 01 length units Flash writing is not possible Actual Flash Memory access is performed in d word 64 bit length units 2 32 bit CPU mode CPU reads writes and executes programs in word 32 bit length units Actual Flash Memory access is
79. ating thickness Note 3 Pins width do not include tie bar cutting remainder 0 14520 055 Tom i 2003 FUJITSU LIMITED 214401955 The contents of this document are subject to change without notice Customers are advised to consult wit FUJITSU sales representatives before ordering FUJITSU unable to assume responsiblity for infringement of any patent or other nights of hird parties ansing from the use of the Information or package dimensions in this document Page 110 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 6 2 Pins and their functions 6 2 1 MB91F467BA 466 465BA 464 with MD_3 0 HiHi al HIMAASA GS SEES EAS 09999536 1393911 RRRRRRESERSRRERE 22220220 00 N 2 5 8 Ne MB91F467BA 466 465 464 mE Pad Layout 2006 03 08 4555 005 P27 6 22 AVCC5 P27 7 AN23 AVRH5 26 0 AN24 AVSS P26 1 AN25 ALARM 0 P26 2 AN26 P18 6 SCK7 P26 3 27 18 5 50T7 P26 4 AN28 18 4 SIN7 P26 5 29 P18 2 SCK6 6 P26 6 AN30 P18 1 5076 P26 7 AN31 P18 0 51 6 P24 4 INT4 19 6 SCK5 CK5 P24 5 INTS P19 5 5075 P24 6 INT6 P19 4 SIN5 P24 7 INT 19 2 5 4 4 P21 0 SINO P19 1 5074 MB91F 467BA 46684 46584 464BA VSS5 without external bus interface MD 3 0 005 P14 4 1
80. but no 128 kB ROMSOL 128 kB ROMS02 128 kB ROMS03 128 kB ROMS04 128 kB ROMS05 128 kB ROMS06 256 kB ROMS07 256 kB ROMS08 256 kB 09 256 kB ROMS10 512 kB ROMS11 512 kB ROMS12 512 kB ROMS13 512 kB ROMS14 512 kB ROMS15 512 kB zE 0000 0000h 0000 00FFh 0000 0100h 0000 01FFh 0000 0200h 0000 03FFh 0000 0400h 0000 0FFFh 0000 1000h 0000 10FFh 0000 2000h 0000 5FFFh 0000 7000h 0000 70F Fh 0000 8000h 0000 BFFFh 0000 000 0000 CFFFh 0001 0000h OOOL FFFFh 0002 0000h 0002 FFFFh 0003 0000h 0003 FFFFh 0004 0000h 0005 FFFFh 0006 0000h 0007 FFFFh 0008 0000h 0009 FFFFh 000A 0000h 000B FFFFh 000C 0000h 000D FFFFh 000 00001 OOOF FFFFh 0010 0000h 0013 FFFFh 0014 0000h 0017 FFFFh 0018 0000h 001B FFFFh 001C 0000h OOLF FFFFh 0020 0000h 0027 FFFFh 0028 0000h O02F FFFFh 0030 0000h 0037FFFFh 0038 0000h 003F FFFFh 0040 0000h 0047 FFFFh 0048 0000h O04F FFFFh 0050 0000h FFFF FFFFh MB91F465BA Byte Data Halfword Data Word Data Flash Cache 8 kB or Instruction RAM 8 kB Flash Control Flash l Cache Control Boot ROM 4 kB External Bus l Cache 4 kB or Instruction RAM 4 kB Data RAM 24 kB Instruction Data RAM 16 kB Flash Area 512 kB 32 kB or External Bus Area depending on ROMA setting External B
81. electable from among 8 16 and 32 bits Page 15 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 3 Peripheral Function General purpose port All functional pins can be used as general purpose ports if the corresponding function is not needed N channel open drain port out of above 4 for A D converter 32 channels 1 unit 16 channels case of MD 3 1 Series parallel type Resolution 10 bits Minimum conversion time 3us Single conversion mode Continuous conversion mode Stop conversion mode Activation by software or external trigger can be selected Reload timer 7 and A D Converter co operate Alarm comparator 1 channel Monitors an external voltage and generates an interrupt in case of a voltage lower or higher than the defined thresholds Status is readable interrupts can be masked separately External interrupt input 16 channels 12 channels in case of MD 3 1 Can be programmed to be edge sensitive or level sensitive Interrupt mask and request pending bits per channel 4channels combined with CAN RX for wakeup 2channels combined with SDA for wakeup Non maskable interrupt NMI 1 channel Highest priority of all user interrupts Page 16 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Bit search module using REALOS
82. errupt input 48 P23 2 RX1 INT9 4 0 47 23 1 0 46 P23 0 2 INT8 4 0 15 24 7 INT7 4 0 14 24 6 INT6 4 0 13 24 5 INT5 4 0 12 P24 4 4 5 4 0 Ke NE x ernal Interrupt Inpu 129 P24 3 INT3 z TP04_0 128 24 2 INT2 4 0 45 P24 1 INT 1 z 4 0 44 P24 0 INTO 4 0 Page 113 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Pin I O PFR 1 EPFR 1 Special Type Comments 11 P26_7 AN31 0 10 26 6 AN30 0 9 26 5 z AN29 0 5 I ANNES ADC Analog input 7 P26_3 27 0 6 26_2 26 0 5 P26 1 AN25 5 0 4 26 0 24 5 _0 3 27 7 23 5 _0 2 27 6 22 5 0 143 27 5 2 21 0 142 27 4 20 0 idi 3 _ 0 ADC Analog input 140 P27_2 18 _0 139 27 1 AN17 2 0 138 P27 0 5 16 TP03 0 104 ALARM 0 02 0 ALARM Comparator input 125 28 7 15 0 124 28 6 14 0 123 28 5 13 0 122 28 4 12 5 _0 g 3 _ 0 ADC Analog input 120 P28 2 10 E _0 119 28 1 9 5 _0 118
83. gn Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000144 PDUTOO W PCNHOO RW PCNLOO R W H XXXXXXXX XXXXXXXX 0000000 000000 0 PTMR01 PCSR01 W n 11111111 11111111 XXXXXXXX XXXXXXXX PPG 1 PDUTO1 PCNHO1 RW PCNLO1 RW H XXXXXXXX XXXXXXXX 0000000 000000 0 00180 2 R PCSR02 W 4 11111111 11111111 XXXXXXXX XXXXXXXX PPG 2 006151 PDUT02 W PCNH02 RW PCNLO2 RW XXXXXXXX 0000000 000000 0 DEE PTMRO3 R PCSRO3 W H 11111111 11111111 XXXXXXXX XXXXXXXX PPG3 PDUTOS W RW PCNLO3 R W 0000000 000000 0 PTMR04 R PCSR04 W H 11111111 11111111 XXXXXXXX XXXXXXXX PPG 4 PDUT04 W PCNH04 RW 04 R W H XXXXXXXX XXXXXXXX 0000000 000000 0 PTMR05 R PCSR05 W n 11111111 11111111 XXXXXXXX XXXXXXXX 5 E PDUTO5 W 5 RW PCNLO5 R W 0000000 000000 0 Page 44 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 P PTMROS PCSRO6 W H 11311111 11111111 20000000X PPG 6 PDUTO6 W PCNHO6 RW 06 RW H XXXXXXXX XXXXXXXX 0000000 000000 0 PTMR07 PCSR07 W H 11111111 11111111 X
84. gram Data RAM 16 kBytes integrated Zero wait state for read write access of instructions One wait state for read write access of data 2 2 7 External Bus Interface If the mode pin MD 3 is set to 1 an external bus interface will become available instead of several resources The external bus interface will include 16 data lines 22 address lines two chip select lines CLK RDX WRX0 WRX1 kkkkkkkkkk Limitation kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk In MB91F467BA 466BA 465BA 464BA you can not use Pin44 as general purpose port in a state of MD_3 1 It means that Pin44 is able to use only as WRX1 For a description of I O Ports please refer to Hardware Manual chapter 55 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Page 14 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 2 8 DMA Controller Four transfer modes supported single block burst continuous transfer and fly by 5 channels 3 types of transfer sources external pins internal peripherals and software Up to 128 selectable internal transfer sources Addressing mode Specifying up to 32 bit addresses Increment decrement fixed Transfer mode Demand transfer burst transfer step transfer block transfer Transferred data size s
85. input Analog input for AD converter Standby control TTL input Standby control Analog input Page 122 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Pin e mment Type Citcuit Commen General Purpose Pull up Resistor 50 with control Pull Up control Pull down Resistor 50 with control lou 2 5mA lo 2 5 Output trigger Pch CMOS Schmitt trigger input 0 8Vcc 0 2Vcc with standby control If standby assert CH input keeps previous Output tri Nch value CMOS Schmitt trigger input 0 7 0 3 with standby control Pull D I If standby assert input keeps previous value gt CMOS Automotive Schmitt trigger input 4 0 0 8 0 5 with standby control Standby control If standby assert AM input keeps previous CCH input value TTL input 2 0V 0 8V with standby control Standby control If standby assert TTL input becomes 4 AM input Standby control TTL input Standby control General Purpose with Analog output Pull up Resistor 50 kQ with control Full Pull down Resistor 50 with control lou 2 5mA lo 2 5 tput t Pch output tigger Pe CMOS Schmitt trigger input 0 8Vcc 0 2Vcc with standby control If standby asse
86. ivider functionality SCL SDA lines include optional noise filter The noise filter allows the suppression of spikes in the range of 1 to 1 5 cycles of the Peripheral Clock Sound Generator 1 channel 8 bit PWM signal is mixed with tone frequency from 16 bit reload counter e PWM clock by internal prescaler fres 2 fags 2 fres 2 fags 22 fres 2 Tone frequency PWM frequency 27 reload value 1 Time base watchdog timer 26 bits Adjustable watchdog timer interval between 2 and 2 system clock cycles Page 19 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Real time clock counts during stop mode RTC module can be clocked either from 32 kHz quartz 4 MHz quartz or from the RC Oscillator Facility to correct oscillation deviation subclock calibration Read write accessible second minute hour registers signal interrupts every half second second minute hour day Internal clock divider and prescaler provide exact 15 clock based on 4 MHz or a 32 kHz clock input Prescaler value for 4 MHz is 1E847Fh Prescaler value for 32 kHz is Clock supervisor Monitors external 32kHz and 4MHz for fails e g crystal breaks Switches in case of fail to an available recovery clock other oscillator or RC oscillator Clock modulator Reduction of Electro Magnetic Emission EME Subclock c
87. o 0 set to 0 set to 1 Write Protection all device modes without set all to 0 set to 0 set to 1 set to 0 exception Read Protection all device modes except set all to 0 INTVEC mode MD 2 0 000 and Write Protection all device modes Read Protection all device modes except INTVEC mode MD 2 0 000 Set all to 0 set to 1 set to 0 set to 1 Write Protection all device modes except INTVEC mode MD 2 0 000 Set all to 0 Read Protection all device modes except mode MD 2 0 000 and Write Protection all device modes except INTVEC mode MD 2 0 000 Set all to 0 set to 1 set to 1 set to 1 Page 29 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 m 5 1 bits 15 to 0 The setting of the Flash Security Vector FSV1 bits 15 0 is responsible for the individual write protection of the 8 KB sectors It is only evaluated if write protection bit FSV1 17 is set Explanation of the bits in the Flash Security Vector FSV1 15 0 Enable Write Disable Write FSV1 bit Comment Protection Protection FSV1 0 set to 1 FSV1 1 0 set to 1 FSV1 2 set to 1 FSV1 3 0 set to 1 FSV1 4 0 Write protection is mandatory FSV1 5 0 set to 1 FSV1 6 0 set to 1 FSV1 7
88. of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 000546 DDROO R W DDRO 1 R W DDRO2 IBAN DDRO2IBAN H 00000000 00000000 00000000 00000000 4 DDR05 R W DDR06 R W DDR07 R W 00000000 000000 00000000 00000000 DDRO8 R W DDR09 R W DDR10 RW DDR HHRAM 0 0 0 0 0 00000000 me 55242 IRAN DDRA2 IRAN DDR14 R W DDR15 R W H 00000000 00000000 00000000 00000000 DDR16 R W DDR17 RW DDR18 R W DDR19 R W 00000000 00000000 000 000 000 000 Fe DDR20 R W DDR21 R W DDR22 R W DDR23 R W H 2000 000 00000000 00000000 DDR24 R W DDR25 IRAN DDR26 R W DDR27 R W i 00000000 00000000 00000000 00000000 DDR28 R W DDR29 R W DDR39BAN DDBR214BAA H 00000000 00000000 00000000 00000000 000060 00000000 00000000 00000000 00000000 000064 reserved do not use 000D7Cu R bus PFROO R W PFRO1 R W PERO2IRANI 000080 11111111 11111111 44444444 HAHHA 27 Page 62 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 OE 4 5 RW PFR06 RW RW H 44444434 111111 11111111 11111111
89. ontrol X1A Clock input TO01 0 1 Standby control Page 125 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 7 Electrical Characteristics 7 1 Absolute Maximum Ratings Parameter Symbol min max Unit Condition Digital supply voltage VDD VSS 0 3 6 0 V Stepper motor control HVDD HVSS 0 3 6 0 V supply voltage Storage temperature Tsr 55 125 G Power consumption 1000 mW 25 C Digital input voltage VipiG 0 3 5 8 V VSS 0V VDD 5V Analogue input voltage VIA 0 3 5 8 V AVSS 0V AVCC 5V Analogue supply voltage AVCC AVSS 0 3 5 8 V AVSS 0V Analogue reference AVSS 0 3 5 8 V AVSS 0V voltage Static DC current into 2 2 mA X loots digital I O Making full use of the allowed static DC current into digital will lead to lower values here Page 126 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 7 2 Operating Conditions Parameter Symbol min typ max Unit Condition Operating temperature Top 40 105 Supply voltage Internal voltage reg Digital supply VDD5 VSS 30 5 5 VDDcore 1 8V 55 V External bus supply VDD35 VSS 3 0 Analog supply AVCC AVSS 3 0 33 NE Ta 25 Current consumption A run mode Isrun 140 mA VSS 0V VDD 5V Isatc 100 f
90. pt level for each interrupt request ICR is provided for each interrupt request The vector address for each EIT exception interrupt or trap is calculated by adding the listed offset to the table base register value TBR The TBR specifies the top of the EIT vector table The addresses listed in the table are for the default TBR value 0 000 00 The TBR is initialized to this value a reset After execution of the internal boot ROM TBR is set to Used by REALOS CR23 and ICR47 can be exchanged by setting the REALOS compatibility bit addr 0x0C03 IOS 0 5 System reserved 5 Memory Protection Unit MPU support Page 108 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 6 Package and Pin Assignment 6 1 Package 144 package wll be used for M891F467BA 466 465 464BA The package code is FPT 144P 8 Page 109 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 FUJITSU SEMICONDUCTOR LOW PROFILE QUAD FLAT PACKAGE 144 PIN PLASTIC FPT 144P M08 ckage width x senare 20 0 x 20 0 mm _ FPT 144P M08 Code 144 20 20 0 50 Reference gt 144 plastic LQFP Note 1 Values do not include resin protrusion FPT 144P M08 Resin protrusion is 0 25 010 Max each side Note 2 Pins width and pins thickness include pl
91. r 0 27 Pin I O 1 1 Special Type Comments Power Supply for external bus part of IO 36 VDD35 TS02 0 ring VDD5R 8 TA00_0 supply for Voltage Regulator Core VSS5 TS00 0 Ground Supply 107 5 00 0 Analog Power supply 5 V 106 AVRH5 01 0 Analog High Reference 5 V 105 55 TAO3 0 Analog Ground supply Low Reference 87 VCC18C TA10_0 Voltage Regulator Capacitance pin 1 There is the following limitation kkkkkkkkkk HANON NEEN OUO In MB91F467BA 466BA 465BA 464BA you can not use Pin44 as general purpose port in a state of MD_3 1 It means that Pin44 is able to use only as WRX1 For a description of I O Ports please refer to Hardware Manual chapter 55 kkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkkk Page 120 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 6 3 Pin Types DONT e ON Commen 2 0 U D control CH A TTL CH2 Stop 3 mA 2 Pin open drain if PFR 1 0 U D control CH A TTL CH2 Stop 2 5 mA General Purpose 1 with 1 analog input line 4 0
92. read and write access Flash read timing settings for MB91F 467BA 466BA 465B A 464BA Core clock CLKB to 24 MHz to 48 MHz to 96 MHz Core clock CLKB to 16 MHz to 32 MHz to 48 MHz to 64 MHz to 96 MHz 2 Keep REGSEL FLASHSEL 0 and REGSEL MAINSEL 0 at their initial value HWM Chapter 52 3 1 Page 24 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 4 2 3 Address mapping from CPU to parallel programming mode 8kB Sectors SAO SA7 SA0 SA2 SA4 SA6 Condition addr gt 14 0000h amp amp addr lt 14 FFFFh 88 addr 2 0 FA addr addr 00 4000h addr 00 4000h 2 addr 2 4 addr 4 05 0000h SA1 SA3 SA5 SA7 Condition gt 14 0000h amp amp lt 14 FFFFh 88 addr 2 1 FA addr addr 00 4000h addr 00 4000h 2 00 2000h addr 2 4 addr 4 05 0000h 64kB Sectors SA8 SA23 SA8 SA10 SA12 SA14 SA16 SA18 SA20 SA22 Condition addr gt 04 0000h amp amp addr lt 13 FFFFh 48 addr 2 0 FA addr addr 02 0000 addr 02 0000h 2 addr 2 4 addr 4 0C 0000h SA9 SA11 SA13 SA15 SA17 SA19 SA21 SA23 Condition addr gt 04 0000h amp amp addr lt 13 FFFFh amp amp addr 2 1 FA addr addr 02 0000h addr 02 0000h 2 01 0000h addr 2 4 addr 4 0C 0000h Remark FA result is without 20 0000h offset for
93. ropean MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Modulation Random No Degree Basecik k N MHz 3 3 066D 60 49 3 76 7 4 3 086 60 46 9 83 3 5 3 0 6 60 44 7 91 3 1 3 026 56 51 4 61 6 1 5 02 56 48 6 66 1 1 7 02ED 56 46 1 71 4 1 9 032 56 43 8 77 6 1 11 0368 56 41 8 84 9 1 13 56 39 9 93 8 2 3 046E 56 48 6 66 1 2 5 04 56 43 8 77 6 2 7 04 56 39 9 93 8 3 3 066D 56 46 1 71 4 3 5 06 56 39 9 93 8 4 3 086 56 43 8 77 6 5 3 0 6 56 41 8 84 9 6 3 56 39 9 93 8 1 3 026F 52 47 8 57 1 5 02 52 45 2 61 2 1 7 02ED 52 42 9 66 1 1 9 032 52 40 8 71 8 1 11 0368 52 38 8 78 6 1 13 52 37 1 86 8 2 3 046E 52 45 2 61 2 2 5 04 52 40 8 71 8 2 7 04 52 37 1 86 8 3 3 066D 52 42 9 66 1 3 5 06 52 37 1 86 8 4 3 086 52 40 8 71 8 5 3 0 6 52 38 8 78 6 6 3 52 37 1 86 8 1 3 026F 48 44 2 52 5 1 5 02 48 41 8 56 4 1 7 02ED 48 39 6 60 9 1 9 032 48 37 7 66 1 1 11 0368 48 35 9 72 3 1 13 48 34 3 79 9 1 15 03E9 48 32 8 89 1 2 3 046E 48 41 8 56 4 2 5 04 48 37 7 66 1 2 7 04 48 34 3 79 9 3 3 066D 48 39 6 60 9 3 5 06 48 34 3 79 9 4 3 086 48 37 7 66 1 5 3 0 6 48 35 9 72 3 6 3 48 34 3 79 9 Page 36 of 125 European MCU Design Centre
94. rt CH input keeps previous output trigger Nch value CMOS Schmitt trigger input 0 7Vcc 0 3Vcc Pull Down control with standby control If standby assert CCH input keeps previous value CH input CMOS Automotive Schmitt trigger input 4 1 0 8 0 5 with standby control Standby control If standby assert AM input keeps previous CCH input value TTL input 2 0V 0 8V with standby control Standby control If standby assert TTL input becomes L AM input Standby control TTL input Standby control Analog output Page 123 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Pin Citcuit Comment Type CMOS Input input 0 High resist pressure Input High impedance input 01 0 High resist pressure detection output CMOS Schmitt Trigger Input 0 Pull up Resistor 02 0 CH input CMOS Schmitt Trigger Input P TC02 1 N CH input Threestate Output 5mA lo 5mA P output trigger Pch TC10_0 N output trigger Nch Page 124 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 Pin Citcuit Comment 4 MHz Oscillator Pin with standby control Clock input TO00_0 ou TOOO 1 Standby control 32 KHz Oscillator Pin with standby c
95. sheet ver 0 27 ER IF1ARB21 R W 1 R W H 00000000 00000000 00000000 00000000 IF1MCTR1 RW 00C11Ch 00000000 00000000 res 11 R W IF1DTA21 R W 00000000 00000000 00000000 00000000 IF1DTB11 R W IF1DTB21 H 00000000 00000000 00000000 00000000 00C1284 reserved 00 12 IF1DTA21 R W IF1DTA11 R W 00000000 00000000 00000000 00000000 IF1DTB21 R W IF1DTB11 R W H 00000000 00000000 00000000 00000000 00 138 reserved 00C13CH CAN 1 IF2CREQ1 RAN IF2CMSK1 RAN 00 140 00000000 00000001 00000000 00000000 IF 2 Register IF2MSK21 R W IF2MSK11 R W 000144 11111111 11111111 11111111 11111111 IF2ARB21 R W IF2ARB11 R W 00000000 00000000 00000000 00000000 Page 76 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 IF2 MCTR1 RAW 00000000 00000000 nm 2 11 R W 2 21 RAW H 00000000 00000000 00000000 00000000 IF2DTB11 R W IF2DTB21 R W 00000000 00000000 00000000 00000000 00 158 reserved 00 15 IF2DTA21 R W IF2DTA11 R W 00000000 00000000 00000000 00000000 IF2DTB21 R W IF2DTB11 RAW 00000000 00000000 00000000 00000000 00 168 reserved 00 17 1 21 TREQR11 RJ 00 1
96. sheet ver 0 27 Modulation Degree k N MHz Random No Basecik E 1 1 2 2 2 2 3 3 3 4 4 5 6 7 8 9 1 1 1 1 1 1 1 2 2 2 2 2 3 3 3 4 4 5 5 6 7 8 9 02 nN A 38 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 4 O Map This section shows the association between memory space and each register of peripheral resources Table convention Address offset Register name Address 0 1 2 000000 PDRD R W PDR1 RW PDR2IR W PDR3 R W T unit Port data register MSB LSB Read Write attribute R Read W Write Register initial value 0 1 X undefined not implemented Register name First column register is 4n address Second column register is 4n 2 address Leftmost register address For Word access first register becomes MSB side of the data Note Bit value of register shows initial values as follows Initial value is 1 0 Initial value is O X Initial
97. tween memories Bit processing instruction Barrel shift instructions Instructions supporting C language Function s enter command exit command Multi load store command of register contents Assembler statement is also easily available Register s interlock function Multiplier s embedded application command level support Signed 32 bit multiplication 5 cycles Signed 16 bit multiplication 3 cycles Interrupt PC PS are saved 6 cycles 16 priority level Harvard architecture enables simultaneous execution of program access and data access Memory protection function Embedded debug support Commands compatible with FR family 2 2 3 Instruction Cache Direct mapped l cache 8KByte integrated Lock function enabling programs to be resident Page 13 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 2 4 Interrupt Controller total of 16 external interrupt lines 8 normal interrupt pins 8 interrupt pins shared with peripheral inputs for Wake Up from STOP mode i e CAN RX and SDA Interrupts from internal peripherals 128 interrupt vectors Priority levels programmable for normal interrupt lines excluding the non maskable one 16 levels Capable of using the normal interrupt pins for Wake Up from STOP mode 2 2 5 Internal Data RAM 24 KBytes integrated Zero wait state for read write access 2 2 6 Internal Pro
98. us Area External Bus Area I O 50 7 setting fixed to internal area 0010 0000h O013FFFFh 0014 0000h 0017 FFFFh 0018 0000h 001B FFFFh 001C 0000h 001F FFFFh 0020 0000h 0027 FFFFh 0028 0000h 002F FFFFh 0030 0000h 0037 FFFFh 0038 0000h 003F FFFFh 0040 0000h 0047 FFFFh 0048 0000h 004F FFFFh 0050 0000h FFFF FFFFh MB91F464BA O Byte Data Halfword Data 1 Word Data Flash Memory Cache 8 Instruction RAM 8 kB Flash Control Flash Memory Cache Control Boot ROM 4 kB External Bus Cache 4 kB or Instruction RAM 4 kB Data RAM 24 kB Instruction Data RAM 16 kB Flash Area 384 kB 32 kB or External Bus Ares depending on ROMA setting External Bus Area External Bus Area ROMSO 7 setting fixed to internal area Page 12 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 2 2 2 FR70 CPU Core 32 bit RISC load store architecture pipeline 5 stages Maximum operating frequency Core clock 96 MHz device dependent Source oscillation 4 MHz multiplied by 24 PLL clock multiplier method General purpose registers 16 x 32 bits 16 01 fixed length instruction Base instruction 32 bit linear address space 4 Gbytes Instructions suitable for embedded application Transfer command be
99. value is indeterminate N A No physical register exists in the position Do not use other data access attributes to access data Page 39 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 PDR00 R W PDR01 R W H XXXXXXXX XXXXXXXX PDR05 R W PDR06 R W PDR07 R W H XXXXXX XXXXXXXX XXXXXXXX PDR08 R W PDR09 R W PDR10 RW 000008 TEST 2 PDR14 R W PDR15 P W 00000Ch XXXXXXXX XXXXXXXX PDR16 RW PDR17 RW PDR18 RW PDR19 RW Rebus H XXXXXXXX XXXXXXXX XXX XXX XXX XXX Data Register EE PDR20 R W PDR21 RW PDR22 R W PDR23 R W H XXXXXXXX XXXXXXXX PDR24 R W PDR26 R W PDR27 R W H XXXXXXXX XXXXXXXX XXXXXXXX PDR28 RW PDR29 RW H XXXXXXXX XXXXXXXX 000020 000024 reserved do not use 000020 ENIR0 RW ELVRO RW 3 Ext INT 0 7 2221 00000000 00000000 00000000 Page 40 of 125 European MCU Design Centre MB91F467BA 466BA 465BA 464BA preliminary datasheet ver 0 27 EIRR1 3 ENIR1 R W ELVR1 RAN 3 000034 00000000 00000000 00000000 00000000 Sh INT eas 0000384 2 2 RBSYNC DLYI unit 00003 reserved do not use AE SCROO R W W SMROO R W W SSROO R W R NT H 00000000 00000000 00001000 MM ENS 0
100. x475 Prog Pulse Gen 11 123 7B 0x210 0x000FFE10 107 Prog Pulse Gen 12 124 7 0 20 108 ICR54 0x476 Prog Pulse Gen 13 125 7 0 208 0x000FFE08 109 Prog Pulse Gen 14 126 7E 0x204 0x000FFE04 110 ICR55 0x477 Prog Pulse Gen 15 127 7F 0x200 144 Up Down Counter 0 128 80 Ox1FC 0x000FFDFC ICR56 0x478 Up Down Counter 1 129 81 Ox1F8 0x000FFDF8 reserved 130 82 Ox1F4 0x000FFDF4 ICR57 0x479 reserved 131 83 0 1 0x000FFDF0 Real Time Clock 132 84 0x1EC 0x000FFDEC ICR58 0 47 Calibration Unit 133 85 0x1E8 0x000FFDE8 A D Converter 0 134 86 0x1E4 0x000FFDE4 14 112 ICR59 0x47B 135 87 0 1 0x000FFDEO Alarm Comparator 0 136 88 0x1DC 0x000FFDDG ICR60 0x47C reserved 137 89 0x1D8 0x000FFDD8 Page 107 of 125 European MCU Design Centre 91 467 466 465 464 preliminary datasheet ver 0 27 Low Voltage Detection 138 8A 0x1D4 0x000FFDD4 ICR61 0x47D reserved 139 8B 0x1D0 0x000FFDD0 Time base Overflow 140 8 0x1CC 0x000FFDCC ICR62 Ox47E PLL Clock Gear 141 8D 0x1C8 0x000FFDC8 DMA Controller 142 8 0 1 4 0x000FFDC4 ICR63 0 47 Main Sub OSC stability 143 8F 0x1C0 0x000FFDC0 Security vector 144 90 0x1BC 0x000FFDBC Used by the INT 145 91 0x1B8 0x000FFDB8 instruction to to to to 255 FF 0x000 0x000FFC00 Notes 7 The ICRs are located in the interrupt controller and set the interru

MB91F467BA/466BA/465BA/464BA preliminary datasheet

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