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External memory interface for TC1775

1. Pin name Pin name Description pC Memory A 21 2 A 19 0 Address bus AD 81 16 DQ 15 0 Data Input Output 16 bit Device 5 AD 15 0 DQ 15 0 Data Input Output 16 bit Device 6 cso CS Chip Select active low RD OE Output Enable read Strobe active low RD WR WE Write Enable write Strobe active low CLKOUT CLK Clock ADV LBA Load burst address active low BAA BAA Burst address advance active low WAIT IND Wait Highest burst counter address reached active low N C RY BY Ready busy active low HRST RESET Reset signal active low 3 3 V VCC Power Supply GND VSS Power Supply Application Note 35 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM 6 5 2 Configuration Definitions Connecting memories to the TC1775 EBU CPU clock fsvs 40MHZ tsvs tcvcte 25ns Flash write read timing tacc 65ns trc 65ns twc 65ns tiacc 65ns teacc 18ns Base address 0xA0000000 Flash devices connected to CSO Flash in asynchronous mode 32 Bit bus width 2 x 16 Bit 2 read Wait states 2 write Wait states O hold cycles 0 recovery cycles Address range 16MBit 16MBit 32MBit 4 MByte 1M x 32 A 26 20 will be compared to EBU_ADDSELO BASE A 21 0 will be used to address memory within 4 Mbyte address range EBU BUSCONO MASK 01018 5 address bits used for address comparison EBU BUSCONO CMULT 008 EBU BUSCONO WAITWRC 2 EBU BUSCONO CMULTR 008 EBU BUSCONO WAITR
2. 7 EBU Data 7 16 D EBU Address AD 31 0 A 25 0 Memory Memory 128K x 8 D 7 0 16 oH 6 0 Figure 2 Demultiplexed 8 Bit interface 4 2 Demultiplexed 16 Bit interface Memory devices in the organization x16 like a SRAM 256Kx16 transfer 16 Bit data for each read access SRAMs use very often control input pins to enable the output of the upper byte lower byte or both A SRAM device expects the configuration on HB and LB pins The management of these two pins can be done directly by using the Byte Control Pins of the EBU bus control signals BC 1 0 All memory accesses to an external memory device are 16 bit aligned because with each access 16 bit data are transferred on the EBU data bus AD 15 0 Z7 ge EBU Data 25 1g T EBU Address AD 31 0 A 25 0 2 o Memory Memory 256K x 16 D 15 0 T E A 17 0 HB LB Figure 3 Demultiplexed 16 Bit interface Because of the data width of 16 bit the address mapping for the EBU address line has to be shifted by one bit so the address lines A 17 0 of an external 256Kx16 SRAM has to be connected to EBU address pins A 18 1 The setting for the external bus width of 16 Bit for PORTW is 01a Application Note 13 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Bus topologies of external memory devices 4 3 Demultiplexed 32 Bit interface 32 Bit data transfers can be performed by using two devices
3. 6 6 3 Flash burst mode To execute code using the burst read mode on Intel Burst Flash devices e g 28F160F3B95 the Flash device must be initialized to perform burst read accesses The Flash memory device starts in asynchronous read mode after power on and expects a configuration data word in the Read Configuration Command register to enter the burst mode The Set Read Configuration command writes data to the read configuration register This operation is initiated by a standard two bus cycle command sequence The Read Configuration Setup command 60x is written to an address within the Flash device where Bits 15 0 include the configuration value A second write with command 03H confirms the operation where also the configuration value has to be part of the address RCD RCD 4 INTEL Configuration cmd value for 32 Bit Flash_Base 0xA0000000 Flash base address Cycle CMD Address Data Command 1 WR_ Flash_Base RCD 0x00600060 SET RCD CYCLE 1 2 WR Flash_Base RCD 0x00030003 SET RCD CYCLE 2 3 WR Flash_Base OxOOFFOOFF READ ARRAY RESET Table 21 Intel Set Read Configuration Command sequence 32 Bit access The 16 Bit read configuration register value has to be placed on the address bus A 15 0 Two configuration cycles are necessary to set the value of the read configuration register The frequency configuration code specifies the number of initial data access cycles tiacc For the Burst Flash
4. synchronize data return to function call Application Note 39 V 1 1 2002 09 AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 6 Intel Burst Flash memory devices Example 2 x Burst Flash 16 MBit 1M x 16 Intel 28F160F3B95 The Intel Fast Boot Block Flash memory offers highest performance using synchronous burst reads and supports asynchronous page mode operation for non clocked memory subsystems In synchronous burst mode the CLK input increments an internal burst address generator synchronizes the flash memory with the host CPU and outputs data on every rising or falling CLK edge up to 60 MHz Synchronous burst reads are enabled by configuring the read configuration register using the standard two bus cycle algorithm The 16 MBit device is organized in x16 organization and operates on 3 3 Volt power supply D 15 0 D 31 16 AD 31 16 DQ 15 0 VCC DQ 15 0 VCC AD 15 0 A 19 0 GND A 19 0 GND WE VCCQ WE vCCQ VPP gt OE VPP CE ADV BC 3 0 ICS 3 0 IWAIT IND HRST WAIT CLKOUT CLKIN Burst Flash Burst Flash EBU Interface 28F160F3 28F160F3 INTEL 1Mx16 INTEL 1Mx16 Device 7 Device 8 Figure 16 Interface to INTEL Burst Flash devices 32 Bit bus width Total memory space 2 16 MBit 4 MByte Application Note 40 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM Connecting memories to t
5. CS1 setting EBU BUSCON Bus configuration register psEBU EBU EBUA BASE pointer to EBU structure psEBU 5EBU CON 0x0000FF68 Time Out OxFF x 8 clock cycles EBU ext Master Ext Access to FPI Bus AGEN 0 demultiplexed mode Flash memory WAITWRC 2 CMULT 0 Multiplier 1 WAITRDC 2 CMULTR 0 Multiplier 1 psEBU gt EBU_BUSCON0 0x00020480 32Bit No hold recovery cycles psSEBU gt EBU_ADDSELO 0xA0000051 Enable region 0 Mask 5 Base psEBU gt 0xA0000000 SRAM WAITWRC 0 CMULT 0 Multiplier 1 WAITRDC 0 CMULTR 0 Multiplier 1 pSEBU gt EBU_BUSCON1 0x00020000 32Bit No Waitstates No hold recov cycles pSEBU gt EBU_ADDSEL1 0xA4000071 Enable region 1 Mask 7 Base 0xA4000000 A second way to set the value of EBU BUSCONO can be done by calculation of the register value uiWaitStates 2 set Waitstates to 2 uiConfig 0x00020000 32Bit No hold recovery cycles uiConfig uiWaitStates lt lt 6 WAITWRC 2 CMULT 0 Multiplier 1 uiConfig uiWaitStates lt lt 9 WAITRDC 2 CMULTR 0 Multiplier 1 psEBU 2BUSCONO uiConfig Set BUSCON register This may be helpful if the application will be assembled with different types of Flash devices like different read write access timing Application Note 33 V 1 1 2002 09 AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 5 AMD Burst Flash memory devices Example 2 x B
6. 1 0 falling edge 1 rising edge Burst Type BCR T 1 0 Interleaved burst order 1 Sequential burst order Valid data ready BCR 8 1 0 Pin R is low during burst clock 1 Pin R is low one data cycle before Y Latency BCR 9 1 0 one burst clock cycle 1 two burst clock cycles X Latency BCR 13 11 3 initial access time latency 010b 4 4 1 1 1 011b 5 5 1 1 1 or 5 2 2 2 100b 6 6 1 1 1 or 6 2 2 2 Read mode BCR 15 1 0 synchronous burst read 1 asynchronous read default Application Note 52 V 1 1 2002 09 AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU technologies ST Flash Timing for 40MHz clock frequency NDIV 2 tIACC 80ns output data on every rising or falling edge up to 65 MHz burst 4 1 1 1 four intial clock cycles one burst clock cycle Read timing 4 cycles cycle 1 two Wait states RDWLEN 2 cycle 3 one data cycle one address cycle burstlength 8 psEBU EBU EBUA BASE pointer to EBU structure psSCU SCU SCU BASE pointer to SCU structure psPMU PMU PMU BASE pointer to PMU structure if uiNDIV 5 set Waitstates dependent on NDIV uiWaitstates 4 Waitstates for asynchronous timing else uiWaitstates 3 clearing Waitstates in EBU_BUSCON Bus configuration register uiConfig amp OxFFFFFFFC clear CMULT uiConfig amp OxFFFFO03F clear WAITRDC and WAITRDC uiConfig amp OxFF3FFFFF clear CMULTR s
7. 2002 09 AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU technologies INTEL Flash Timing for 40MHz clock frequency NDIV 2 tIACC 95ns output data on every rising or falling edge up to 65 MHz burst 4 1 1 1 Read timing 4 cycles cycle 1 two Waitstate RDWLEN 2 cycle 3 one data cycle one address cycle burstlength 8 psEBU EBU EBUA BASE pointer to EBU structure psSCU SCU SCU BASE pointer to SCU structure psPMU PMU PMU BASE pointer to PMU structure if uiNDIV 5 set Waitstates dependent on NDIV uiWaitstates 4 Waitstates for asynchronous timing else uiWaitstates 3 clearing Waitstates in EBU BUSCON Bus configuration register uiConfig amp OxFFFFFFFC clear CMULT uiConfig amp OxFFFFO003F clear WAITRDC and WAITRDC uiConfig amp OxFF3FFFFF clear CMULTR setting EBU_BUSCON Bus configuration register uiConfig uiWaitStates lt lt 6 WAITWRC n CMULT 0 Multiplier 1 uiConfig uiWaitStates 9 WAITRDC n CMULTR 0 Multiplier 1 psEBUA BUSCONO uiConfig set BUSCON register setting EIFCON External instruction fetch register uiConfig uiWaitStates 1 1 one additional read wait cycle uiConfig PMUFBBMSEL buffer length defined by FBBLEN uiConfig PMUFBBLEN 8 Burst buffer length 8 uiConfig PMUIFUBLEN 8 Instruction burst length 8 PSPMU gt EIFCON uiConfig
8. Set EIFCON register setting SCU_CON System control unit Enable direct instruction fetch not via FPI bus uiConfig psSCU gt CON Load value of SCU uiConfig ENSWIF Enable switching of Instruct Fetch Path uiConfig EXTIF Instruction fetch direct uiConfig EBUEN Enable EBU psSCU gt CON uiConfig _isync synchronize instructions _dsync synchronize data return to function call Application Note 45 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 7 ST Microelectronics Burst Flash memory devices Example 1 x Burst Flash 16 MBit 512k x 32 ST M58BW016 The M58BW016B D is 3V Flash Memory in x32 organization An optional VPP of 12 Volt can be provided to speed up program and erase operations This Flash memory device has separate VDDQ and VDDQIN power supply pins for I O buffers This is useful to interface the Flash Memory device with lower or higher power supply devices VDDQ IN can go from 2 4V to VDD if VDD 3 3 Volt VDDQ can be between 2 4 Volt and 3 Volt A power supply voltage of 3 3 Volt 2 7 Volt minimum is mandatory to drive the core circuits of the Flash Memory D in UO EE ee 20 2 A 20 2 s A 25 0 A 18 0 vss RD IG vese BAA B ADV IL VDDQIN CS 3 0 ea BC 3 0 WAIT AIND WAIT IND JWAIT IND R HRST PHBST CLKOUT CLKIN EBU Interface Burst Flash M58BW016 ST 512k x 32 De
9. active low BC1 HB Byte Control higher byte Device 1 active low BC2 LB Byte Control lower byte Device 2 active low BC3 HB Byte Control higher byte Device 2 active low 3 3 V VCC Power Supply GND VSS Power Supply Table 15 Asynchronous SRAM configuration The SRAM devices need Byte Control Input Signals for the different operating modes and also for selecting upper and lower output pins during read write operations The TriCore EBU supports external devices with a data width of 8 16 and 32 bits and provides the Byte Control lines BC 3 0 The Byte Control lines are not generated if external memory is accessed directly via EBU and not via the FPI Bus If Directly Instruction fetch is selected in the SCU configuration register SCU_CON EXTIF or Directly Boot from external memory via EBU is selected by Boot options the Program Memory Unit fetches instructions directly without using the FPI Bus In this mode the EBU generates no Byte Control signals BC 3 0 high and activates the Code fetch status output CODE An external code fetch is not possible from SRAM during Direct Code Fetch Mode if the Byte Control signals BC 3 0 are connected directly to the external SRAM An AND operation of BCx and the CODE signals creates a Byte Control signal to have the opportunity to fetch code from external SRAM within Direct access mode without FPI Bus transfers see Figure 11 Application Note 26 V 1 1 2002 09 AP32035 Infi
10. at the end of the subroutine a data and instruction synchronization has to be performed using _isync and dsync commands isync Forces completion of all previous instructions flushes the CPU pipelines and invalidates any cached pipeline state before proceeding to the next instruction dsync Forces all data accesses to complete before any data accesses associated with an instruction semantically after the DSYNC are initiated Application Note 37 V 1 1 2002 09 technologies AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU Set system clock frequency and PLL settings Vv Switch to burst mode application code code fetches running in burst mode ee START vy Allocate memory buffer in SRAM for executing burst mode switch AA copy code from external Flash memory to buffer AA jump to buffer and execute code AA deallocate memory Enable burst mode on Flash memory device v Burst mode settings in PMU Instruction Fetch Control Register v Waitstate settings in EBU Bus Configuration Register v Instruction path selection in SCU Code running outside Flash memory burst mode enable sequence PMU EIFCON Burst mode timing Burst Length Buffer length EBU BUSCONx Set Read waitstates Set Write waitstates SCU
11. default after reset 1liB reserved Table 8 PORTW field of EBU Register EBU BUSCONx Via the Byte Control signals BC 3 0 byte access to corresponding byte locations can be controlled so that external memory devices with a data width of 8 16 or 32 bits can be connected The number of bus accesses for an instruction fetch from external memory depends from the bus width so a 32 Bit instruction fetch is divided into four 8 Bit access for a 8 Bit data bus configuration For Burst Flash memory accesses only the 32 Bit data bus width is supported In Burst Mode all instruction fetches will be transferred directly from the External Bus Unit EBU to the Program Management Unit PMU without using the FPI bus During these direct instruction fetches the FPI Bus can be used for transfers of peripheral units like Peripheral Control Processor Analog Digital Converter General Purpose l O s Communication interfaces etc Application Note 12 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Bus topologies of external memory devices 4 1 Demultiplexed 8 Bit interface External memories with a data bus width of 8 Bit can be connected directly to the EBU data interface The data transfer width is 8 Bit for each memory access and the address range of the external memory can be mapped directly to the EBU address interface The setting for the external bus width of 8 Bit for PORTW is 00s
12. 0 One address cycle RDWLEN 1 One additional wait cycles between initial address cycle and first data DATLEN 0 One data cycle FBBMSEL 1 Flash burst buffer length defined by FBBLEN FBBLEN 0108 Maximum 8 linear flash burst data cycles EIFBLEN 108 Instruction Fetch burst length 4 data accesses ADV j eom BAA V AD 31 0 i i i DATA X DATA X DATA X DATA EE liACC 3 cycles lt i i gt lt BACC 1 cycle i Cycle 0 i Cycle 1 i Cycle 2 i Cycle 3 i Cycle 4 i Cycle 4 i Cycle 5 i Cycle 6 i Address cycle Read wait cycle d Data cycles i ADVLEN 0 RDWLEN 1 E DATLEN O Figure 9 Synchronous burst read timing 3 1 1 1 Note The burst timing is related to the rising edge of the CLKIN signal Table 14 Synchronous burst read timing Application Note 23 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM EBU configuration Cycle Description Cycles Cycles Parameter min max Cycle 0 Address cycle 1 1 2 PMU EIFCON ADVLEN Cycle 1 Address cycle 2 0 1 PMU EIFCON SIDC Cycle 2 Read wait cycle 0 7 PMU EIFCON RDWLEN Cycle 3 Initial data cycle 1 1 fixed Cycle 4 Burst data cycle 1 2 PMU EIFCON DATLEN Cycle 5 Last burst data cycle 1 2 PMU EIFCON DATLEN Cycle 6 End of burst cycle 1 1 fixed Application Note 24 V 1 1 2002 09 AP32035 Infineon 1C1775 EX
13. an external code Flash memory In this case the reset value of 0000005Fu in the PMU External Instruction Fetch Control Register PMU EIFCON will be used for the burst mode settings The reset default values are defined as Burst length 1 access in field EIFBLEN two data cycles in field DATLEN two address cycles in field ADVLEN within the initial address cycle and seven read wait cycles between the initial address cycle and the first instruction cycle in Field RDWLEN 5 2 Burst mode configuration The Program Memory Unit PMU of the TC1775 is designed to perform burst mode cycles to operate together with external code Flash memory in Burst Mode For Burst Mode access to an external Flash memory device the PMU is directly connected to the External Bus Unit EBU which controls the connection to the external Flash device Some types of Burst flash memory devices support the continous burst mode The functionality of continous instructions fetching used by the continous burst mode is not implemented in the TC1775 although this mode is supported by different Burst flash memory devices For external burst flash mode only 32 bit data bus width is supported In the External Instruction Fetch Control register PMU EIFCON the parameter EIFBLEN and FFBLEN are specified to define the burst length for an external burst request to the Flash memory The burst length driven on the data bus depends on the specified burst buffer length so the minimum of speci
14. with a 16 Bit data interface in parallel Each device transfers half of the maximum data bus width of 32 Bit for each read access All memory accesses to an external memory device are 32 bit aligned because with each access 32 bit data are transferred on the EBU data bus AD 31 0 To handle the two external memory devices in parallel the address lines A 17 0 have to be connected to the EBU address lines A 19 2 to create an address offset and map the address lines in the correct way The management of the upper and lower data bus of each memory device can be done directly by using the Byte Control Pins of the EBU bus control signals BC 3 0 31 0 25 19 2 EBU Data EBU Address AD 31 16 AD 15 0 ADI31 0 777 4 A 25 0 15 0 15 0 Device B Device A oe Near ERO IG HB LB HB LB i o Figure 4 Demultiplexed 32 Bit interface The setting for the external bus width of 32 Bit for PORTW is 10s Note In demultiplexed mode an address is driven only on address lines A 25 0 Application Note 14 V 1 1 2002 09 AP32035 Infineon 1C1775 EXTMEM Bus topologies of external memory devices 4 4 Read Access timing for demultiplexed mode Parameters within the configuration registers of the External Bus Unit EBU allow to design applications with different read and write timings for the external memory The timing of the external memory can be defined by differen
15. 6 5 2 Configuration 2 aru e edd eae deed Ea eee ea SER E 36 6 5 3 Flash burst mode pem Rer eee ers ERECTA RE EUER ee 37 6 6 Intel Burst Flash memory devices 0 00 e eee eee eee 40 Application Note 3 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Table of Contents Page 6 6 1 Connections between EBU interface and external memory 41 6 6 2 Configuration osasse venir etes eee REA Re Ru A E RU eR p dors 42 6 6 3 Flash burst mode scc see b Rr RE AERE 43 6 7 ST Microelectronics Burst Flash memory devices 46 6 7 1 Connections between EBU interface and external memory 47 6 7 2 Configuration PE 49 6 7 3 Flash burst mode sacs ea e bh ERE he odes 50 6 8 TC1775 EBU and PMU settings 0 0 0 cece eee 54 7 References 0 c eee ete 55 Application Note 4 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Conventions Definitions and Abbreviations 1 Conventions Definitions and Abbreviations Name Description Byte 8 bit data format quantity Half word 16 bit data format quantity Word 32 bit data format quantity kByte 1024 bytes of memory MByte 1048576 bytes of memory BCU Bus Control Unit CPU Central Processing Unit DMU Data Memory Unit EBU External Bus Unit PCP Peripheral Control Processor PMU Program Memory Unit SCU System Control Unit Application Note 5 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM
16. A 21 0 will be used to address memory within 4 Mbyte address range EBU BUSCONO MASK 01015 5 address bits EBU BUSCONO CMULT 00s EBU BUSCONO WAITWRC 3 EBU BUSCONO CMULTR 008 EBU BUSCONO WAITRDC 3 EBU BUSCONO RECOVC 008 EBU BUSCONO HOLDC 008 Flash in asynchronous mode Flash address range 0xA0000000 Bus configuration register setting EBU BUSCON psEBU EBU EBUA BASE psEBU gt EBU_CON 0x0000FF68 Multiplier 1 Multiplier 1 No recovery cycle No Hold cycle OxA03FFFFF pointer to EBU structure Time Out OxFF x 8 clock cycles EBU ext Master Ext Access to FPI Bus AGEN 0 demultiplexed mode Set 3 Read wait states 3 Write wait states WAITWRC 3 CMULT 0 Multiplier 1 WAITRDC 3 CMULTR 0 Multiplier 1 pSEBU gt EBU_BUSCON0 0x000206C0 pSEBU gt EBU_ADDSELO 0xA0000051 32Bit No hold recovery cycles Enable region 0 Mask 5 Base 0xA0000000 A second way to set the value of EBU BUSCONO can be done by calculation of the register value uiWaitStates 3 uiConfig 0x00020000 uiConfig uiWaitStates lt lt 6 uiConfig uiWaitStates lt lt 9 psEBU BUSCONO uiConfig Application Note set Wait states to 3 32Bit No hold recovery cycles WAITWRC 3 CMULT 0 Multiplier 1 WAITRDC 3 CMULTR 0 Multiplier 1 Set BUSCON register 42 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU
17. Application Note V 1 1 September 2002 AP32035 TC1775 External memory interface 32 Bit Single Chip Microcontroller Microcontrollers Never stop thinking TC1775 Revision History 2002 09 V 4 1 Previous Version 2001 09 V 1 0 Page Subjects major changes since last revision all Changed to Infineon Template We Listen to Your Comments Any information within this document that you feel is wrong unclear or missing at all Your feedback will help us to continuously improve the quality of this document Please send your proposal including a reference to this document to mcdocu comments infineon com Edition 2002 09 Published by Infineon Technologies AG 81726 M nchen Germany Infineon Technologies AG 2006 All Rights Reserved LEGAL DISCLAIMER THE INFORMATION GIVEN IN THIS APPLICATION NOTE IS GIVEN AS A HINT FOR THE IMPLEMENTATION OF THE INFINEON TECHNOLOGIES COMPONENT ONLY AND SHALL NOT BE REGARDED AS ANY DESCRIPTION OR WARRANTY OF A CERTAIN FUNCTIONALITY CONDITION OR QUALITY OF THE INFINEON TECHNOLOGIES COMPONENT THE RECIPIENT OF THIS APPLICATION NOTE MUST VERIFY ANY FUNCTION DESCRIBED HEREIN IN THE REAL APPLICATION INFINEON TECHNOLOGIES HEREBY DISCLAIMS ANY AND ALL WARRANTIES AND LIABILITIES OF ANY KIND INCLUDING WITHOUT LIMITATION WARRANTIES OF NON INFRINGEMENT OF INTELLECTUAL PROPERTY RIGHTS OF ANY THIRD PARTY WITH RESPECT TO ANY AND ALL INFORMATION GIVEN IN T
18. CON Direct instruction fetch buffer Control Register not via FPI Bus END t END im END Figure 15 External burst mode instruction fetches If external boot is selected the TriCore starts execution of code from the external memory in asynchronous demultiplexed address mode see Booting from external memory on Page 18 To enable external burst mode instruction fetches changes to the External Instruction Fetch Register PMU EIFCON Bus configuration register EBU BUSCONXx and Control register of System Control Unit SCU CON must be made Note In some documents different interpretations of burst stream and Wait State stream can be found For the following examples the information 3 1 1 1 stands for burst stream and defines the number of clock cycles during the burst read access The start of the burst is defined on the valid edge of the clock signal when a burst start address is valid burst 3 1 1 1 3 clock cycles initial access time 1 clock cycle burst access time No burst read Wait States Application Note 38 V 1 1 2002 09 AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU technologies AMD Flash Timing for 40MHz clock frequency NDIV 2 tIACC 65ns tBACC 18ns burst 3 1 1 1 Read timing 3 cycles cycle 1 one Waitstate RDWLEN 1 cycle 3 one data cycle one address cycle burstlength 8 psEBU EBU EBUA BASE pointer to EBU structure ps
19. Configuration in register EBU BUSCONXx before the address range will be enabled in register EBU ADDSELx Application Note 28 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 3 Asynchronous Flash memory devices Example 2 x Flash memory 16 MBit 1M x 16 AMD Am29LV160BA 70 The Am29LV160BA is a 16 MBit 3 3 Volt only Flash memory device organized as 1Mx16 The device operates as a asynchronous Flash EPROM using the standard control pins WEZ OE and CE This device is designed to be programmed in system with the standard system 3 0 Volt Vcc supply A 12 0 Volt Ver or 5 0 Vcc are not required for write or erase operations The device requires only a single 3 3 Volt power supply for both read and write functions Internally generated and regulated voltages are provided for the program and erase operations The device offers access times of 70 80 90 and 120 ns AD 31 16 o 22 ponso vocc Hay ZEE DQ 15 0 A 1 2 AD 15 0 A 19 0 VSS A 19 0 A 25 0 vcc 3 3V VSS GND WE WE RD WR OE OE RD E CE CE BAA H ADV BYTE BYTE RY BY c RY BY BC 3 0 7 HRSTI RESETE CS 3 0 HRST RESET IWAITJIIND vaio Flash Flash MEST pss AM29LV160 AM29LV160 CLKOUT AMD 1Mx16 AMD 1Mx16 CLKIN Device 3 Device 4 EBU Interface Figure 12 Interface to asynchronous AMD Flash devices 32 Bit bus width Total memory sp
20. DC 2 EBU BUSCONO RECOVC 008 EBU BUSCONO HOLDC 008 Flash in asynchronous mode Flash address range 0xA0000000 Bus configuration register setting EBU BUSCON psEBU EBU EBUA BASE psEBU gt EBU_CON 0x0000FF68 Multiplier 1 Multiplier 1 No recovery cycle No Hold cycle OxAO3FFFFF pointer to EBU structure Time Out OxFF x 8 clock cycles EBU ext Master Ext Access to FPI Bus AGEN 0 gt demultiplexed mode Set 2 Read wait states 2 Write wait states WAITWRC 2 CMULT 0 Multiplier 1 WAITRDC 2 CMULTR 0 Multiplier 1 psEBU EBU BUSCON0 0x00020480 pSEBU gt EBU_ADDSELO 0xA0000051 32Bit No hold recovery cycles Enable region 0 Mask 5 Base 0xA0000000 A second way to set the value of EBU BUSCONO can be done by calculation of the register value uiWaitStates 2 uiConfig 0x00020000 uiConfig uiWaitStates lt lt 6 uiConfig uiWaitStates lt lt 9 psEBU BUSCONO uiConfig Application Note set Wait states to 2 32Bit No hold recovery cycles WAITWRC 2 CMULT 0 Multiplier 1 WAITRDC 2 CMULTR 0 Multiplier 1 Set BUSCON register 36 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 5 3 Flash burst mode To execute code using the burst read mode on AMD Burst Flash devices e g Am29BL162CB 65Cl both the Microcontroller and the Flash device must be initialized to perform b
21. ES A o A c Aa c BURST BUFFER amp o o INSTR LENGTH oooo20o 4lq o o o o O 0 0 N aa aa alo oooooocowv aaa no ofp ooooooo0 aaa a aly 4 200 00 4 ooooooo 0 0 0 0 0 0 oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo oooooo ooooo ooooo ooooo ooooo o o2o EIFBLEN FBBLEN FBBMSEL DATLEN RDWLEN ADVLEN Figure 19 101775 EBU PMU settings Application Note 54 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM 7 References References K6R4016V1C 4 MBit Static RAM data sheet Samsung Electronics 2000 M58BW016BT 16 MBit Burst Flash memory data sheet STMicroelectronics 2001 Am29LV160 16 MBit Flash memory data sheet AMD 1998 Am29BL162C 16 MBit Burst Flash memory data sheet AMD 2000 28F160F3 16 MBit Burst Flash memory data sheet INTEL 2000 TC1775 System Units 32 Bit Microcontroller Infineon Technologies 2001 V2 0 2001 02 TC1775 Data Sheet 32 Bit Microcontroller Infineon Technologies 2001 V1 1 2001 09 Application Note 55 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM References Application Note 56 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM References Application Note 57 V 1 1 2002 09 Infineon goes for Business Excellence Business excellence means intelligent approaches and clearly defined processes which are both const
22. EruP MIN 6ns tHoLb MIN 3ns Flash in asynchronous mode 32 Bit bus width 3 read Wait states 3 write Wait states 0 hold cycles 0 recovery cycles Flash devices connected to CSO Base address 0xA0000000 EBU is external master 16MBit 2 Mbyte 512K x 32 A 26 21 will be compared to EBU_ADDSEOL BASE A 20 0 will be used to address memory within 2 Mbyte address range EBU CONFO MASK 01108 6 address bits EBU CONFO CMULT 008 Multiplier 1 EBU CONFO WAITWRC 3 EBU CONFO CMULTR 008 Multiplier 1 EBU CONFO WAITRDC 3 EBU CONFO RECOVC 008 No recovery cycle EBU CONFO HOLDC 008 No Hold cycle Flash address range 0xA0000000 OxAO3FFFFF setting EBU_BUSCON Bus configuration register psEBU EBU EBUA BASE pointer to EBU structure uiWaitStates 3 set Waitstates to 3 psEBU EBU CON 0x0000FF68 Time Out OxFF x 8 clock cycles EBU ext Master Ext Access to FPI Bus AGEN 0 demultiplexed mode psEBU EBU ADDSELO 0xA0000061 Enable region 0 Mask 6 Base 0xA0000000 uiConfig 0x00020000 32Bit No hold recovery cycles uiConfig uiWaitStates lt lt 6 WAITWRC 3 CMULT 0 Multiplier 1 uiConfig uiWaitStates 9 WAITRDC 3 CMULTR 0 Multiplier 1 pPSEBU gt BUSCONO uiConfig Set BUSCON register Application Note 49 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 7 3 Flash burst mode
23. HIS APPLICATION NOTE Information For further information on technology delivery terms and conditions and prices please contact your nearest Infineon Technologies Office www infineon com Warnings Due to technical requirements components may contain dangerous substances For information on the types in question please contact your nearest Infineon Technologies Office Infineon Technologies Components may only be used in life support devices or systems with the express written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life support device or system or to affect the safety or effectiveness of that device or system Life support devices or systems are intended to be implanted in the human body or to support and or maintain and sustain and or protect human life If they fail it is reasonable to assume that the health of the user or other persons may be endangered _ AP32035 Infineon 1C1775 EXTMEM Table of Contents Page 1 Conventions Definitions and Abbreviations 5 2 Introduction ese sd eae oe Rede deba 6 3 External Bus Unit of the TriCore TC1775 7 3 1 VO voltage ranges sssssseeees III 7 3 2 EBU External Address Ranges 0 2 cece eee eee 9 3 2 1 Settings for Address Select and Bus Configuration Registers 11 3 2 1 1 Default settings 2 c eee ees 11 3 2 1 2 Examples
24. Input Output DC characteristics of external memory it could be necessary to increase the supply voltage of the EBU I O s and to decrease the supply voltage of memory l O s within the allowed range Both values must be within the specified values Examples An external SRAM device is specified for supply voltage Vcc 3 3 Volt Viumin 2 0 Volt and ViLmax 0 8 Volt Because of the specified DC characteristics of Microcontroller and SRAM both values are within the specification if the I O supply voltage of the TC1775 is VppPos 2 5 Volt An external Flash device is specified with Vcc 3 3 Volt Viumin 2 31 Volt and Vitmax 0 8 Volt Because of the specified DC characteristics of Microcontroller and Flash the value of Vou is outside the specification if the I O supply voltage of the TC1775 is VppPos 2 5 Volt In this case an increase of the TC1775 I O supply voltage Vppros to 2 6 Volt VoHmin 2 34 Volt and a decrease of the Flash power supply Vcc to 3 0 Volt Viumin 0 7 x Vcc 2 1 Volt meets the specification of both devices Application Note 8 V 1 1 2002 09 Infineon technologies 3 2 EBU External Address Ranges The EBU reacts to addresses in a range defined as external memory Each address is compared against the address defined in the Address Select Register EBU_ADDSELx AP32035 TC1775 EXTMEM External Bus Unit of the TriCore TC1775 Segment Address Range Description 10 A000 0000 External m
25. Introduction 2 Introduction The External Bus Unit EBU of the TC1775 is the interface to external memories and peripheral units which use the external address and data bus The EBU is primarily used for communication with external memories or peripheral units via the FPI Bus and also for instruction fetches directly from the PMU if external Burst Flash memories will be used The EBU controls all transactions required for these operations In Burst Mode the instruction fetches will be transferred directly from the External Bus Unit EBU to the Program Management Unit PMU without using the FPI bus During these direct instruction fetches the FPI Bus can be used for transfers of peripheral units like Peripheral Control Processor Analog Digital Converter General Purpose l O s Communication interfaces etc Burst Mode To external Memories Program Management Unit a PMU External SRAM i Bus i ae FPI Bus Unit Burst Flash i EBU Peripherals using multiplexed A D bus demultiplexed A D bus Data 8 16 32 Bit data bus Memory Unit DMU To Peripheral Units and PCP Figure 1 TC1775 External Bus Unit This document describes how to connect different types of memories to the External Bus Unit interface The most important settings of the configuration registers and examples how to initialize external memories can also be found within this document Additional information and a
26. ONO MASK 01018 5 address bits used for address comparison EBU BUSCONO CMULT 008 EBU BUSCONO WAITWRC 2 EBU BUSCONO CMULTR 008 EBU BUSCONO WAITRDC 2 EBU BUSCONO RECOVC 008 EBU BUSCONO HOLDC 008 Flash address range 0xA0000000 Bus configuration register setting EBU BUSCON psEBU EBU EBUA BASE psEBU gt EBU_CON 0x0000FF68 Multiplier 1 Multiplier 1 No recovery cycle No Hold cycle OxAO3FFFFF pointer to EBU structure Time Out OxFF x 8 clock cycles EBU ext Master Ext Access to FPI Bus AGEN 0 demultiplexed mode WAITWRC 2 CMULT 0 Multiplier 1 WAITRDC 2 CMULTR 0 Multiplier 1 pSEBU gt EBU_BUSCON0 0x00020480 pSEBU gt EBU_ADDSELO0 0xA0000051 32Bit No hold recovery cycles Enable region 0 Mask 5 Base 0xA0000000 A second way to set the value of EBU BUSCONO can be done by calculation of the register value uiWaitStates 2 uiConfig 0x00020000 uiConfig uiWaitStates lt lt 6 uiConfig uiWaitStates lt lt 9 pSEBU gt BUSCON0 uiConfig Application Note set Wait states to 2 32Bit No hold recovery cycles WAITWRC 2 CMULT 0 Multiplier 1 WAITRDC 2 CMULTR 0 Multiplier 1 Set BUSCON register 31 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 4 SRAM and Flash memory devices in asynchronous mode To connect both SRAM and Flash memory to the EBU interface C
27. SCU SCU SCU BASE pointer to SCU structure psPMU PMU PMU BASE pointer to PMU structure if uiNDIV 7 set Waitstates dependent on NDIV uiWaitstates 2 timing for burst mode uiWaitstate 1 else and asynchronous timing uiWaitstate uiWaitstates 3 clearing Waitstates in EBU BUSCON Bus configuration register uiConfig amp OxFFFFFFFC clear CMULT uiConfig amp OxFFFFO003F clear WAITRDC and WAITRDC uiConfig amp OxFF3FFFFF clear CMULTR setting EBU BUSCON Bus configuration register uiConfig uiWaitStates lt lt 6 WAITWRC n CMULT 0 Multiplier 1 uiConfig uiWaitStates 9 WAITRDC n CMULTR 0 Multiplier 1 pPSEBUA gt BUSCONO uiConfig set BUSCON register setting EIFCON External instruction fetch register uiConfig uiWaitStates 1 1 one additional read wait cycle uiConfig PMUFBBMSEL buffer length defined by FBBLEN uiConfig PMUFBBLEN 8 Burst buffer length 8 uiConfig PMUIFUBLEN 8 Instruction burst length 8 PSPMU gt EIFCON uiConfig Set EIFCON register setting SCU_CON System control unit Enable direct instruction fetch not via FPI bus uiConfig psSCU gt CON Load value of SCU uiConfig ENSWIF Enable switching of Instruct Fetch Path uiConfig EXTIF Instruction fetch direct uiConfig EBUEN Enable EBU psSCU gt CON uiConfig _isync synchronize instructions _dsync
28. SO and CS1 will be used to enable the devices Two separate address ranges within a Segment can be used for RAM and Flash memory In this example both ranges are located within Segment 10 which is the cached Segment This configuration is the combination of SRAM and Flash see Chapter 6 1 Asynchronous SRAM devices and Chapter 6 3 Asynchronous Flash memory devices with the difference that the SRAM range is mapped to address 0xA4000000 Type Base Adr Size Chip Select Read WS Write WS FLASH 0xA0000000 4 MByte CSO 2 2 SRAM 0xA4000000 1 MByte CS1 0 0 Table 17 SRAM and Flash memory devices BC 3 0 CS 3 0 AWAIT IND HRST CLKOUT CLKIN EBU Interface D 15 0 m BYTE HHRST RESET AM29LV160 AMD 1Mx16 DQ 15 0 vec Hey DQ 15 0 vec 2 A 19 0 vss LGND A 19 0 vss ono BC 3 0 IWAIT IND JHRST AM29LV160 AMD 1Mx16 D 15 0 VO 16 1 vec H 17 0 vss evo VO 16 1 vec H3 A 17 0 VSS evo a KS ICS rT UB SRAM SRAM 256k x 16 256k x 16 K6R4016C1B K6R4016C1B Samsung Samsung Figure 13 Interface to SRAM and Flash memory Application Note 32 V 1 1 2002 09 AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU technologies 6 4 1 Configuration Flash address range 0xA0000000 OxAO3FFFFF 4 MByte CSO SRAM address range 0xA4000000 OxA40FFFFF 1 MByte
29. TMEM Connecting memories to the TC1775 EBU 6 Connecting memories to the TC1775 EBU 6 1 Asynchronous SRAM devices Example 2 x SRAM 4 MBit 256k x 16 Alliance AS734098 15TI or SAMSUNG K6R4016V10C 15 The K6R4016V1C 15 is an asynchronous SRAM in x16 organization It operates at a power supply of 3 3 Volt and uses 16 common input and output lines which can be controlled by two data byte control pins for upper and lower byte DQ 15 8 and DQ 7 0 The SRAM devices use an asynchronous non multiplexed address data bus D 31 16 MO t643 VCC on63 VCC 17 0 vss 921 17 0 vss SRAM SRAM IWAIT IIND wamu 256k x 16 256k x 16 EA K6R4016C1B K6R4016C1B m Samsung Samsung CLKOUT CLKIN Device 1 Device 2 EBU Interface Figure 10 Interface to Samsung asynchronous SRAM 32 Bit bus width Total memory space 2 4 MBit 1 MByte Application Note 25 V 1 1 2002 09 AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 2 Connections between EBU interface and external memory Pin name Pin name Description uC Memory A 19 2 A 17 0 Address bus AD 31 16 DQ 15 0 Data Input Output 16 bit Device 1 AD 15 0 DQ 15 0 Data Input Output 16 bit Device 2 cso CS Chip Select active low RD OE Output Enable read Strobe active low RD WR ANE Write Enable write Strobe active low BCO LB Byte Control lower byte Device 1
30. To execute code using the burst read mode on ST Burst Flash devices e g M58BW016BT80 the Flash device must be initialized to perform burst read accesses The Flash memory device starts in asynchronous read mode after power on and expects a configuration data word in the Burst Configuration Register BCR to enter the burst mode The burst mode initialization code has to run outside the Flash memory The Set Burst Configuration Register command writes data to the Burst configuration register This operation is initiated by a standard two bus cycle command sequence The Set Burst Configuration Register command 0x60 is written to any address within the Flash memory device to enter the procedure In the second cycle the value 0x03 has to be written to a valid address within the Flash memory device where the Burst Configuration Word is transmitted on A 15 0 BCR 0x10CA Value for Burst Configuration register BCR BCR 4 ST Burst Configuration cmd value for 32 Bit Flash_Base 0xA0000000 Flash base address Cycle CMD Address Data Command 1 WR Flash_Base 0x00000060 SET RCD CYCLE 1 2 WR Flash_Base BCR 0x00030003 SET RCD CYCLE 2 Table 24 ST Set Burst Configuration Command sequence 32 Bit access Application Note 50 V 1 1 2002 09 AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU technologies Initialization code for ST Burst Flash uint32 puiAdr Address pointer uiWaits
31. ace 2 16 MBit 4 MByte Application Note 29 V 1 1 2002 09 T AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 3 1 Connections between EBU interface and external memory Pin name Pin name Description uc Memory A 21 2 A 19 0 Address bus AD 31 16 DQ 15 0 Data Input Output 16 bit Device 3 AD 15 0 DQ 15 0 Data Input Output 16 bit Device 4 cso CS Chip Select active low RD OE Output Enable read Strobe active low RD WR WE Write Enable write Strobe active low 3 3 V BYTE Select 8 Bit or 16 Bit mode high 16 Bit mode N C RY BY Ready busy active low HRST RESET Reset signal active low 3 3 V VCC Power Supply GND VSS Power Supply Table 16 Asynchronous Flash memory configuration Application Note 30 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM 6 3 2 Configuration Definitions Connecting memories to the TC1775 EBU CPU clock fsvs 40MHZ tsvs tcycLe 25ns Flash write read timing taccz70ns trc 70ns twc 70NS Base address 0xA0000000 Flash devices connected to CSO Flash in asynchronous mode 32 Bit bus width 2 x 16 Bit 2 read Wait states 2 write Wait states 0 hold cycles 0 recovery cycles Address range 16MBit 16MBit 32MBit 4 MByte 1M x 32 A 26 20 will be compared to EBU_ADDSELO BASE A 21 0 will be used to address memory within 4 Mbyte address range EBU BUSC
32. ait state no WRITE wait state e 32 Bit demultiplexed address data bus Memory range A4000000 AAFFFFFFuz 16 MByte EBU_ADDSEL1 0xA4000031 use User Address Range 0 connected to CS1 EBU_BUSCON1 0x00020180 A 26 24 will be used for the address range selection Enable region Region is not mirrored Write access enabled No Hold cycle no RECOVERY cycle 2 READ wait state 2 WRITE wait state 32 Bit demultiplexed address data bus Table 7 Settings for Address Select and Bus Configuration Registers Note During address range selection the address bits A 31 27 must always match Application Note 11 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Bus topologies of external memory devices 4 Bus topologies of external memory devices The EBU configuration is controlled by EBU Controls Status registers Address Region registers and Emulator registers External memory space can be managed via the four address region registers EBU_ADDSEL 3 0 The corresponding settings for each memory region can be controlled by the control status register EBU BUSCON 3 0 The external device data width for the different memory ranges can be adjusted in each EBU bus configuration register EBU_BUSCON The Settings can be done in the PORTW Field of EBU_BUSCONx 17 16 Field Bits Type Description PORTW 17 16 rw External Device Data Width Control O08 8 Bit data Ols 16 Bit data 10s 32 Bit data
33. antly under review and ultimately lead to good operating results Better operating results and business excellence mean less idleness and wastefulness for all of us more professional success more accurate information a better overview and thereby less frustration and more satisfaction Dr Ulrich Schumacher http www infineon com Published by Infineon Technologies AG
34. d Read Recovery i Setup Activation Waitstate iDeactivation Cycle i i CMULTR 1 i i SETUP 1 WAITRDC 1 IRECOVC 1 Figure 6 Read access timing in asynchronous demultiplexed mode trc 5 4 5 Multiplexed Address Data Bus In multiplexed mode both address and data are driven on the multiplexed address data bus AD 31 0 In the first part of an access the address is driven on AD 31 0 together with the Address Latch Enable signal ALE high In the second part in combination with ALE low the data is driven by the EBU interface for a write access during RD WR low and RD high For a read access data will be driven during RD low and RD WR high Wait cycles can be inserted between address and data cycle by initializing the WAITRDC CMULTR WAITWRC and CMULT fields in the selected EBU_BUSCONx register 31 16 7 0 i f EBU Address Data A AD 31 0 M 128K Ds 1st part eae exe address driven on AD 31 0 Address Latch Enable ALE high 7 D 7 0 9 2nd part data driven on AD 31 0 Address Latch Enable ALE low Figure 7 Multiplexed Address Data Bus Application Note 16 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM Bus topologies of external memory devices 4 6 Read Access timing for multiplexed mode Cycle Description Cycles min Cycles max Parameter Cycle 0a Address setup 1 1 fixed Cycle Oa A
35. ddress setup repeat 0 3 SETUP Cycle 1 Address hold 1 1 fixed Cycle 2a Read activation 1 1 fixed Cycle 2b Read activation wait state 0 127x8 WAITRDC 6 0 CMULTR 1 0 Cycle 3 Read deactivation 1 1 fixed Cycle 4 Recovery 0 3 RECOVC 1 0 Table 10 Read Access timing for multiplexed mode The minimum read time for an asynchronous read in multiplexed mode is four clock cycles Note In demultiplexed mode only addresses A 25 0 are driven to the external bus In multiplexed mode a complete 32 Bit address is driven to AD 31 0 Application Note V 1 1 2002 09 AP32035 Infineon TC1775 EXTMEM EBU configuration 5 EBU configuration 5 1 Booting from external memory The EBU supports booting from external memory using its default settings for setup and timing see Chapter 3 2 EBU External Address Ranges and Chapter 3 2 1 Settings for Address Select and Bus Configuration Registers With these settings a external boot memory configuration word can be read from address BOOTBASE 0x04 The settings of the EBU configuration register EBU BUSCONO will be overwritten with values read from external memory and set the EBU configuration to proper values for additional reads from external memory The BOOTCFG register is located in the external boot memory The options for a external boot sequence are asynchronous demultiplexed mode memory connected to CSO The EBU use registers EBU ADDSELO and EBU BUSCONO and operates as a ext
36. detailed description of all registers can be found in the System Units part of the TC1775 User s manual Application Note 6 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM External Bus Unit of the TriCore TC1775 3 External Bus Unit of the TriCore TC1775 3 1 O voltage ranges The EBU is connected to Port 4 0 and builds a communication interface to external memories and peripheral units The operation voltage for the bus output buffers is 2 5 Volt connected to pin Vopros Input receivers work also with an internal supply voltage of 2 5 Volt but are 3 3 Volt tolerant Class B After RESET the EBU is enabled by default and can be enabled or disabled by Bit DISS Bit 1 in the EBU Clock control register EBU_CLC Port Signals Purpose Operation Port O D 15 0 or Lower Data bus in demultiplexed mode 2 5V AD 15 0 Lower Address Data bus in multiplexed mode Port 1 D 31 16 or Higher Data bus in demultiplexed mode 2 5V AD 81 16 Higher Address Data bus in multiplexed mode Port 2 A 15 0 Lower Address bus in demultiplexed mode 2 5V Port 3 A 25 16 Higher Address bus in demultiplexed mode 2 5V CS 3 0 Chip Select signals active low CSEMU CSOVL Emulation and Overlay support active low Port 4 RD RD WR Read control Write control 2 5V ALE Address latch enable ADV Address valid output BAA Burst address advance output BC 3 0 Byte control line 3 0 WAIT IND Wait input End of bur
37. devices 28F160F3B Intel specifies CODE 3 for 95 ns access time VCC 3 3V 40MHz clock frequency lt 50MHz and CODE 4 for 120 ns access time VCC 3 3V clock frequency lt 46MHz Application Note 43 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU Name Field Bit s Description Burst length BL RCR 2 0 3 001b 4 Word Burst 010b 8 Word Burst 111b Continuous Burst Clock configuration CC RCR 6 1 0 falling edge 1 rising edge Burst sequence BS RCR 7 1 0 Intel burst order 1 linear order Data Output Config DOC RCR 9 1 0 one data hold cycle 1 two data hold cycles Frequency configuration RCR 13 11 3 binary value for CODE 011b 2 CODES 4 clock cycles 100b CODE 4 5 clock cycles Read mode RM RCR 15 1 0 enable burst mode Table 22 Specification of Intel Read Configuration register Initialization code for Intel Burst Flash uint32 puiAdr Address pointer uiWaitstates 3 NDiv 2 40 MHz value for CODE uiFlashBase 0xA0000000 Address range 0xA0000000 OxAO3FFFFF uiRCRvalue uiWaitstates 11 0x00C2 lin burst BL 8 rising edge puiAdr uint32 uiFlashBase uiRCRvalue 4 32 Bit calculation puiAdr 0x00600060 Set Read configuration cycle l1l puiAdr 0x00030003 Set Read configuration cycle 2 puiAdr OxOOFFOOFF Set Read Array Reset Application Note 44 V 1 1
38. emory space AFFF FFFFu cached area 256 MByte 11 B000 0000 External memory space BDFF FFFFu non cached area 224 MByte 11 BEO0 0000 External Emulator space BFFF FFFFu non cached area 16 MByte 14 E000 0000 External Peripheral and data memory space EFFF FFFFa non cached area 256 MByte Table 3 EBU External address ranges The EBU provides five programmable address regions Each region can be controlled by two separated registers the Address Select register ADDSELx and the Bus Control register BUSCONXx Each address region is linked to one chip select line CSx which will be activated if an address fits to an address region In the Address Select register the Base Address within the memory map is specified Configuration and timing parameters defined for the external memory region can be found in the Bus Control register The smallest possible address region is 4 kBytes MASK 15 the largest region can be set to 128 MByte MASK 0 Address Region Address Select Bus Control Chip Select Register Register User region 0 EBU ADDSELO EBU BUSCONO cso User region 1 EBU ADDSEL1 EBU BUSCON 1 CS1 User region 2 EBU ADDSEL2 EBU BUSCON2 CS2 User region 3 EBU_ADDSEL3 EBU BUSCONS CS3 Table 4 EBU User address regions Note The TC1775 provides an additional Chip select for the emulator region CSEMU and an additional Chip select for the overlay memory CSOVL CSEMU should not be used in any application and n
39. ernal bus master Option Field in Field in Description BOOTCFG EBU BUSCONO Boot memory data width CFG16 PORTW 8 16 32 Bit CFG32 Address generation AGEN AGEN multiplexed mode control demultiplexed mode Read Wait State control WAITRDC 6 5 WAITRDC Number of Wait States WAITRDC 4 3 in read access 0 127 Cycle Multiplier Control CMULT CMULT Wait cycle multiplier CMULTR CMULTR Read cycle multiplier Byte Control mode BCGEN BCGEN Functionality of BC 3 0 Variable Wait State WAIT WAIT asynchronous insertion control synchronous Extended Setup control SETUP SETUP Cycle 0 generation Active wait level control WAITINV WAITINV WAIT high or low Table 11 Boot configuration register Number of READ Wait states nWSr CMULTR WAITRDC with CMULTR 1 4 8 16 and WAITRDC 0 127 48 Number of WRITE Wait states nWSw CMULT WAITWRC with CMULT 1 4 8 16 and WAITWRC 0 127 7 defaults Application Note 18 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM EBU configuration To select External boot as master via FPI Bus the boot configuration input pins of the TC1775 microcontroller should be connected as follows OCDSE 1 BRKIN 1 CFG 3 0 11018 12VCC 0 GND The PC Start value is set to OxA0000000 Segment 10 If External boot directly via EBU is selected CFG 3 0 11008 the PMU is connected directly to the EBU and performs burst mode cycles for
40. etting EBU BUSCON Bus configuration register uiConfig uiWaitStates lt lt 6 WAITWRC n CMULT 0 Multiplier 1 uiConfig uiWaitStates 9 WAITRDC n CMULTR 0 Multiplier 1 psEBUA BUSCONO uiConfig set BUSCON register setting EIFCON External instruction fetch register uiConfig uiWaitStates 1 1 one additional read wait cycle uiConfig PMUFBBMSEL buffer length defined by FBBLEN uiConfig PMUFBBLEN 8 Burst buffer length 8 uiConfig PMUIFUBLEN 8 Instruction burst length 8 PSPMU gt EIFCON uiConfig Set EIFCON register setting SCU_CON System control unit Enable direct instruction fetch not via FPI bus uiConfig psSCU gt CON Load value of SCU uiConfig ENSWIF Enable switching of Instruct Fetch Path uiConfig EXTIF Instruction fetch direct uiConfig EBUEN Enable EBU psSCU gt CON uiConfig Set CON register isync synchronize instructions dsync synchronize data return to function call Application Note 53 V 1 1 2002 09 AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU technologies 6 8 TC1775 EBU and PMU settings As described in Chapter 4 4 Read Access timing for demultiplexed mode and Chapter 5 2 Burst mode configuration the register EBU_BUSCONx is used for the timing of external bus accesses in asynchronous mode and register PMU EIFCONXx is used for external instruction fetch con
41. fied burst length and burst buffer length will be used as the actual burst length A recommendation to define the burst length for different configurations is to set the value for the Flash Burst Buffer Length FBBLEN to 8 linear burst cycles and specify the actual burst length using the parameter External Instruction Flash Burst Length EIFBLEN with 1 2 4 or 8 data accesses Table 12 Actual Burst length definition The burst flash memories use a n Bit counter e g Am29BL162CB 65CI uses a 5 Bit counter 0 31 to increment the address for the next data cycle during a burst starting with the initial address If an overflow of this counter 28 29 30 31 0 1 2 3 occurs the flash memory creates a signal which can be used by the microcontroller Application Note 19 V 1 1 2002 09 _ AP32035 Infineon TC1775 EXTMEM EBU configuration Burst length EIFBLEN Burst Length FBBLEN Buffer Length 2 018 2 data accesses 0105 8 linear burst data cycles 4 108 4 data accesses 8 118 8 data accesses 2 01s 2 data accesses 001s 4 linear burst data cycles 4 108 4 data accesses In case of a instruction cache miss each burst access to the external Flash memory begins at the missed address The alignment of a cache line results to an 8 word address line border address bits A 4 0 0 Application Note 20 V 1 1 2002 09 T Infineon technologies Burst Flash Memory Me
42. he TC1775 EBU 6 6 1 Connections between EBU interface and external memory Pin name Pin name Description uc Memory A 21 2 A 19 0 Address bus AD 81 16 DQ 15 0 Data Input Output 16 bit Device 7 AD 15 0 DQ 15 0 Data Input Output 16 bit Device 8 cso CE Chip Enable active low RD OE Output Enable read Strobe active low RD WR WE Write Enable write Strobe active low CLKOUT CLK Clock ADV ADV Address valid active low WAIT WAIT _ Data valid feedback during burst mode active low HRST RST Reset signal active low 3 3 V WP Write protection active low 3 3 V VCC Power Supply 3 3 V VPP Block erase and program power supply 2 5V VCCQ Flash Output buffer voltage GND GND Power Supply Table 20 Intel Burst Flash memory configuration Application Note 41 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM 6 6 2 Configuration Definitions Connecting memories to the TC1775 EBU CPU clock 40MHz tsvs 25ns tacc 90ns Intel recommendation CPU clock lt 50MHz gt frequency configuration code 3 tiacc 4 clock cycles taacc 1 clock cycle burst 4 1 1 1 Flash in asynchronous mode 32 Bit bus width 2 x 16 Bit 3 read Wait states 3 write Wait states 0 hold cycles 0 recovery cycles Flash devices connected to CSO Address range 16MBit 16MBit 32MBit 4 Mbyte 1M x 32 A 26 20 will be compared to EBU_ADDSEOL BASE
43. mory Array f Address Latch Input Output buffer Decoder 1 n 30 31 Cache n 3 refill sequence n 3 n 4 External Bus Unit FPI Bus 1 Cache line 32 bytes 32 bytes TC1775 2 2 2 Instruction cache Figure 8 Cache refill sequence For the TC1775 each cache line is aligned to A 4 0 0 so the offset is defined to 0x00 0x20 0x40 0x60 Every Cache refill sequence starts with the missed address If a counter overflow occurs 30 31 0 1 the data stream transferred from the Flash memory is not a continous address range In the example above only word 6 and 7 will be updated by word 30 and 31 by the content of the flash memory buffer The words 0 and 1 will be received by the EBU but ignored to update any cache content Application Note TC1775 EXTMEM EBU configuration Infineon technologies AP32035 TC1775 EXTMEM Example EBU configuration Cache Miss for instruction at address 0xA0000078 The address lines A 21 2 of the EBU interface are connected to A 19 0 of the Flash memory A 4 0 are connected inside the Flash memory to the burst counter BL 4 Offset 0x78 011110xxeB Start counter 30 Burst order 30 31 0 1 BL 8 Offset 0x78 011110xxs Start counter 30 Burst order 30 31 0 1 2 3 4 5 5 2 1 Burst control
44. neon 1C1775 EXTMEM Connecting memories to the TC1775 EBU BCO_SRAM BC1_SRAM BC2_SRAM M CODE BC3 amp BC3_SRAM Figure 11 Generating a Byte Control signal to fetch code from external SRAM Application Note 27 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 2 1 Configuration Definitions CPU clock fsvs 40MHz tsvs tcycLe 25ns SRAM write read timing tac 15ns twc 15ns Base address 0xA0000000 SRAMs connected to CSO SRAM in asynchronous mode 32 Bit bus width 2 x 16 Bit 0 read Wait states 0 write Wait states 0 hold cycles 0 recovery cycles Address range 4MBit 4MBit 8MBit 1 MByte 256k x 32 A 26 20 will be compared to EBU ADDSELO BASE A 19 0 will be used to address memory within 1 Mbyte address range EBU BUSCONO MASK 01118 7 address bits used for address comparison SRAM address range 0xA0000000 OxAOOFFFFF setting EBU_BUSCON Bus configuration register psEBU EBU EBUA_BASE pointer to EBU structure psEBU EBU CON 0x0000FF68 Time Out OxFF x 8 clock cycles EBU ext Master Ext Access to FPI Bus AGEN 0 gt demultiplexed mode psEBU EBU BUSCON0 0x00020000 32Bit No Waitstates No hold recovery cycles psEBU 5EBU ADDSEL0 0xA0000071 Enable region 0 Mask 7 Base 0xA0000000 Note It is recommended to make the setup of the External Bus
45. o sri nstes4o Re LEX dela lib dna Balada Baa Rs 11 4 Bus topologies of external memory devices 12 4 1 Demultiplexed 8 Bit interface llle 13 4 2 Demultiplexed 16 Bit interface llli 13 4 3 Demultiplexed 32 Bit interface llli 14 4 4 Read Access timing for demultiplexed mode 20 05 15 4 5 Multiplexed Address Data Bus 2 00 00 eee elles 16 4 6 Read Access timing for multiplexed mode 0 ee ea ee 17 5 EBU configuration 0 0 0 c ee eee 18 5 1 Booting from external memory 2 2 ee eee 18 5 2 Burst mode configuration 00 cee eee 19 5 2 1 Burst control register llli 22 5 2 2 Synchronous burst read timing llle esses 23 6 Connecting memories to the TC1775 EBU 25 6 1 Asynchronous SRAM devices 000 0c ee eee eee e eas 25 6 2 Connections between EBU interface and externalmemory 26 6 2 1 Gonfig ration ses teen Euer Reo nne eats Ware Paden 28 6 3 Asynchronous Flash memory devices sli 29 6 3 1 Connections between EBU interface and external memory 30 6 3 2 Configuration ssssseseseee 31 6 4 SRAM and Flash memory devices in asynchronous mode 32 6 4 1 Configuration ss s smear REG n cR RR RR ERR E Deb dE 33 6 5 AMD Burst Flash memory devices 000 e eee eee eee 34 6 5 1 Connections between EBU interface and external memory 35
46. onous variable or disabled SETUP Cycle 0 generation 0s or 18 no CycleO RECOVC Number of recovery cycles 0 3 3 HOLDC _ Number of hold cycles in demultiplexed mode 0 3 3 WAITINV WAIT high or low active Osoris active low BCGEN Functionality of Byte Control BC 3 0 008 108 Control ALEC Address Latch Enable Duration control 0 3 3 WRDIS Memory Region Write Protection OB or 15 disabled Table 6 Parameter in the Bus Configuration Register BUSCONx Application Note 10 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM External Bus Unit of the TriCore TC1775 3 2 1 Settings for Address Select and Bus Configuration Registers 3 2 1 1 Default settings Number of WRITE Wait states nWSw CMULT WAITWRC 16 7 112 cycles Number of READ Wait states nWSr CMULTR WAITRDC 1 48 48 cycles Number of HOLD cycles nHold CMULT HOLDC 16 3 48 cycles Number of RECOVERY cycles nRECOV CMULT RECOVC 16 3 48 cycles Number of SETUP cycles nSETUP SETUP 0 cycles 3 2 1 2 Examples Note The largest possible address range is limited to 128 MByte Description of Configuration Settings Memory range A0000000 AOSFFFFFa 4 MByte EBU ADDSEL0 0xA0000051 e use User Address Range 0 connected to CS0 EBU BUSCON0 0x00020000 A 26 22 will be used for the address range selection Enable region Region is not mirrored Write access enabled No Hold cycle no RECOVERY cycle No READ w
47. ot for normal access Application Note V 1 1 2002 09 T Infineon technologies AP32035 TC1775 EXTMEM External Bus Unit of the TriCore TC1775 If the External Instruction Fetch Path Select Bit EXTIF in Register SCU CON is set to Instruction fetch via FPI Bus default the range of address bits which will be compared against the FPI Bus address can be defined in the MASK bits of register ADDSEL The base address of the memory range has to be defined in the BASE option EBU Description Value or Default ADDSELx Range value REGEN Memory region enable disable Osoris boot mode MIRRORE Memory region mirror enable disable Os or 18 0 BASE Base address of external memory range A 81 12 boot mode MASK Range and number of address bits compared 0 15 0 to BASE 26 12 Table 5 Definition of Address Select Register ADDSEL Note Memory Region Enable Bit and Base Adaress default value depend on boot mode EBU Description Value or Default BUSCONx Range value PORTW Memory data width 8 16 or 32 Bit 008 108 32 Bit AGEN multiplexed or demultiplexed mode 008 or 118 demuxed WAITRDC Number of Wait States in read access 0 127 48 WAITWRC Number of Wait States in write access 0 7 7 CMULT Wait cycle multiplier 1 4 8 16 16 CMULTR Read cycle multiplier 1 4 8 16 1 WAIT Wait State insertion asynchronous 00s 118 variable synchr
48. pply voltage Application Note 47 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU Asynchronous Read is the default read mode which the Flash device enters on power up or on return from Reset Power Down An asynchronous read cycle is performed when detecting a valid address on the address inputs A 18 0 Chip Enable E low Output Enable G low Write Enable W high and Output Disable GD high Synchronous Burst Read mode may be enabled after executing a initialization sequence Chapter 6 7 3 Flash burst mode A valid Synchronous Burst Read operation begins when the Burst Clock K is active and Chip Enable E and Latch Enable L are low The burst start address A 18 0 is latched and loaded into the internal Burst Address Counter on the valid Burst Clock K edge or on the rising edge of Latch Enable whichever occurs first After an initial burst access time taci the memory may output data on each clock cycle for the burst configuration X 1 1 1 depending on the clock frequency The Burst Address Advance input B controls the memory burst output Note In brackets the pin marking of the M58BWO16B D Flash memory device is described Application Note 48 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Connecting memories to the TC1775 EBU 6 7 2 Configuration CPU clock 40MHz tsvs 25ns Flash timing tacc 80ns ts
49. register Register Name Description SCU CON EXTIF 1 Instruction fetch directly PMU lt gt EBU ENSWIF 1 Enable changing of EXTIF bit EBUEN 1 Enable EBU PMU EIFCON ADVLEN Number of address cycles 1 2 RDWLEN Read wait cycles between initial address cycle and first data cycle 0 7 DATLEN Number of data cycles 1 2 FBBMSEL 0 ignore FBBLEN and EIFBLEN a new request is starting at MISSED address up to the end of the cache line 1 Burst buffer length defined by value in FBBLEN FBBLEN Maximum number of linear burst data cycles 001824 0108 8 0118 2 16 100s 32 PMU EIFCON EIFBLEN Instruction Fetch Burst length 008 1 data access 018 2 data accesses 10s 4 data accesses 11s 8 data accesses Table 13 Burst Flash configuration parameter If EIFBLEN is set to 118 a configuration of FBBLEN 0018 will enable four external instruction fetch accesses burst length 4 The burst length depends on the setting of field FBBLEN A new burst starts always at the MISSED address and goes until the specified parameters in EIFBLEN and FBBLEN if FBBMSEL Mode select is set to 1 Application Note 22 V 1 1 2002 09 AP32035 Infineon 1C1775 EXTMEM EBU configuration To guarantee correct functionality of the burst mode settings it is recommended to set Bit 12 of the register PMU EIFCON always to 0 5 2 2 Synchronous burst read timing Example ADVLEN
50. st input Table 1 EBU Port overview and description The TC1775 uses separate power supply pins for Core supply and Port supply The Port Power supply voltage has to be connected to pin Voppos 2 5 Volt for Port 5 0 and to pin Voopsi3 3 3 Volt 5 Volt for Ports 13 8 The pins for address and data bus and also for control signals are specified for VppPos 2 3 2 75 Volt and all input pins are 3 3 Volt tolerant All external memories which use a 3 3 Volt power supply for the Vopa output voltage or a single power supply Vpp for core and I O power supply can be connected directly to the EBU interface A Worst case check of the driver and receiver conditions Application Note 7 V 1 1 2002 09 AP32035 Infineon 1C1775 EXTMEM External Bus Unit of the TriCore TC1775 are necessary to guarantee a successful system behavior over the complete parameter range Parameter Symbol Limit value Conditions min max Specification VppPos 2 3 2 75 V Output low voltage VoL 0 45 V lo 600 pA Output high voltage VoH 0 9 x VppPos lo 600 pA Input low voltage ViL 0 5 0 2 x VppPos Input high voltage Vin 0 7 x VppPos 3 7V Default Voppos 2 5 V Output low voltage VoL 0 45 V lo 600 pA Output high voltage VoH 2 25 V lo 600 pA Input low voltage ViL 0 5 0 5V Input high voltage ViH 1 75 V 3 7V Table 2 Input Output DC Characteristics of EBU interface Depending on the
51. t fields like Wait Cycle Multiplier Read Cycle multiplier Read Wait States Write Wait States and the definition of an additional Recovery Cycle Hold Pause Cycle Write or Extended Address Cycle These parameters can be found in the EBU Bus Configuration Register EBU BUSCONx Cycle Description Cycles min Cycles max Parameter Cycle 0 Address setup optional 0 1 SETUP Cycle 1a Read activation 1 1 fixed Cycle 1b Read activation wait state 0 127x8 WAITRDC 6 0 CMULTR 1 0 Cycle 2 Read deactivation 1 1 fixed Cycle 3 Recovery 0 3 RECOVO 1 0 Table 9 Read Access timing for demultiplexed mode The minimum read time for a asynchronous read in demultiplexed mode is two clock cycles Fixed cycles are marked grey in the following timing diagrams Cycle 1a Cycle 2 Cycle 1a Cycle 2 ne CSx EE RD A 25 0 AD 31 0 Read Read i Read i Read Activation Deactivation Activation iDeactivation CMULTR 1 CMULTR 1 WAITRDC 0 WAITRDC 0 Figure 5 Read access timing in asynchronous demultiplexed mode trc 2 Application Note 15 V 1 1 2002 09 _ AP32035 Infineon 1C1775 EXTMEM Bus topologies of external memory devices Cycle 0 Cycle la Cycle 1b Cycle 2 Cycle 3 ment LE LE LE Lt Ut CSx RD mu A 25 0 lt i i gt RC 5 cycles ACC ie i AD 31 0 DATA d i Address i Read i Rea
52. tates 4 NDiv 2 40 MHz value for X Latency e g 4 uiFlashBase 0xA0000000 Address range 0xA0000000 OxAO3FFFFF uiBCRvalue uiWaitstates 2 11 0x00C2 BL 8 ris edge one clock puiAdr uint32 uiFlashBase Set Adr pointer to Flash base adr puiAdr 0x00000060 Set Read configuration cycle l puiAdr uint32 uiFlashBase uiBCRvalue 4 32 Bit adr calculation puiAdr 0x00000003 Set Read configuration cycle 2 CLKN f f f ADV mE CSx IBAA A 25 0 AD 31 0 tlACC 4 cycles T T i i gt 1BACC 1 cycle burst configuration 4 1 1 1 CycleO Oydei Cycle 2 Cycde3 Cycle4 Cyde4 Cycle5 Cycles Address cycle Read wait cycle Data cycles i ADVLEN 0 RDWLEN 2 i DATLEN 0 Figure 18 Burst configuration 4 1 1 1 example Table 25 Specification of ST Burst Configuration register If Y Latency is set to 0 a data word 32 Bit is driven on the data bus on each valid clock edge The initial access time depends on the parameter X Latency Application Note 51 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU Name Field Bit s Description Burst length BCR 2 0 3 001b 4 Word Burst 010b 8 Word Burst 111b Continuous Burst Wrapping BCR S3 1 0 boundary wrap 1 no boundary wrap Valid clock edge BCR 6
53. trol To initialize the modes and functionalities for the external bus interface the registers may be set directly with the configuration value or with a calculated value Additional information to the functionality of each bit can be found in the TC1775 User s manual The most important parameters for the timing on the external memory bus for asynchronous mode and synchronous burst mode can be found together with some examples in the table below EBU BUSCON 31 0 19 18 17 16 15 14 13 121 HEX 3 0x00020000 0 0x00020240 0 0x00020480 0 0 0 e e D e N S XN N e N a N N e N N N D e e 0000 0x000206C0 0x00020900 Aa w o O READ WS Aa w n O WRITE WS ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo ooooo o o ojo 2oooo o o 00 N o2o coo ooooo on ooooots ooooo oOoo0o00N ooooo 2 ooooo eo SS S S S32 Bit 1 1 1 1 1 ooooo ooooo ooooo oooo ooo 00 00 00 00 oooo oooo CMULTR WAITRDC WAITWRC HOLDC RECOVC CMULT IFCON 31 0 16 15 14 13 12111 1 0000 HEX 3 0x00000D44 0x000008C4 0x00000D54 0x000008D4 0x00000D56 0x000008D6 e N o S eo MN XN D o N a N N e M m N N e o o oooooo u Burst 4 1 1 1 4 1 1 1 4 2 2 2 4 2 2 2 5 2 2 2 5 2 2 2 a 3 ADRCYCLES 6 N N N N RD WAIT CYCLES NN S DATA CYCL
54. urst Flash 16 MBit 1M x 16 AMD Am29BL162CB 65CI The Am29BL162C is a 16 MBit 3 0 Volt only burst mode Flash memory device organized as 1Mx16 In burst mode the device allows a microcontroller to operate without wait states The device can operate as a asynchronous Flash EPROM using the standard control pins WEZ OE and CE After power on the device starts in asynchronous read mode that allows the system to boot directly from the Flash The User can set the operating mode to burst read mode using a burst mode enable command sequence software sequence In burst read mode the data are transferred on the rising edge of the clock signal in combination with the load address pin LBA and the burst address advance pin BAA ok D 15 0 33V D 31 16 33V AD 31 16 DQ 15 0 VCC DQ 15 0 VCC D AD 15 0 A 19 0 VSS GND A 19 0 VSS GND WE WE OE CE LBA BC 3 0 f ANE WADE A RY BY WAIT IND HRST IND CLKOUT CLKIN Burst Flash Burst Flash EBU Interface AM29BL162 AM29BL162 AMD 1Mx16 AMD 1Mx16 Device 5 Device 6 Figure 14 Interface to AMD Burst Flash devices 32 Bit bus width Total memory space 2 16 MBit 4 MByte 6 5 1 Connections between EBU interface and external memory Table 18 AMD Burst Flash memory configuration Application Note 34 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU
55. urst read accesses The Flash memory device starts in asynchronous read mode after power on and expects a burst mode enable sequence to enter the burst mode Address Offsets for configuration settings of AMD Flash memory SETUP 0x0555 4 AMD Setup Address offset for 32 Bit access UNLOCK 0x02AA 4 AMD Unlock Address offset for 32 Bit access Flash_Base 0xA0000000 Flash base address Cycle CMD Address Data Command 1 WR Flash Base SETUP 0x00AA00AA FLASH SETUP 2 WR Flash_Base UNLOCK 0x00550055 FLASH UNLOCK 3 WR Flash_Base SETUP 0x00C000CO FLASH BURST MODE 4 WR Flash_Base 0x00010001 FLASH BURST ENABLE 5 WR Flash Base OxOOFOOOFO FLASH RESET Table 19 AMD Burst mode enable sequence based on 32 Bit data bus width The external burst mode instruction fetches are controlled and defined by the PMU EIFCON register which is located in the PMU To switch the code fetch mode from asynchronous mode to synchronous burst mode the code has to be executed from the internal or external SRAM To enable the burst mode on both the external Flash memory and the PMU the code has to run from a defined memory range that isn t located in external Flash memory After the last FLASH RESET command the Flash memory all instruction fetches are performed in the synchronous burst mode To guarantee that all data and instructions accesses to the system and local data memory busses will be successfully executed
56. vice 9 Figure 17 Interface to ST Burst Flash devices 32 Bit bus width Total memory space 1 16 MBit 2 MByte 6 7 1 Connections between EBU interface and external memory Table 23 ST Burst Flash memory configuration Application Note 46 V 1 1 2002 09 Infineon technologies AP32035 TC1775 EXTMEM Connecting memories to the TC1775 EBU Pin name Pin name Description pC Memory A 20 2 A 18 0 Address bus AD 31 0 DQ 31 0 Data Input Output 32 bit Device 9 CSO E Chip Select Chip Enable active low RD IG Output Enable read Strobe active low low when the Flash Memory is in read mode high during a Flash write operation 3 3 V GD Output Disable active low deactivates the output buffers and set to high impedance must be connected to an external pull up resistor RD WR IW Write Enable write Strobe active low BAA B Burst address advance active low ADV L Latch Enable active low Load burst address active low CLKOUT K Burst Clock N C R Valid data ready Open Drain output identifies if the memory is ready to output data 3 3 V WP Write protect HRST RP Reset Power down active low 3 3 V VDD Supply voltage 2 5 V VDDQ Flash Output supply voltage used for DQ s 2 5 V VDDQIN Flash Input supply voltage used for all input signals 3 3 V VPP Program Erase Supply Voltage GND VSS Ground Power Supply GND VSSQ Ground Output su

External memory interface for TC1775

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