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UM10308 P89LPC9331/9341/9351/9361 user manual

1. 110 SPI single master multiple slaves configuration 111 SPI slave transfer format with 0 114 SPI slave transfer format with CPHA 1 115 SPI master transfer format with 20 116 All information provided in this document is subject to legal disclaimers Fig 49 Fig 50 Fig 51 Fig 52 Fig 53 Fig 54 Fig 55 Fig 56 SPI master transfer format with 1 117 P89LPC9331 9341 comparator input and output 119 P89LPC9351 9361 comparator input and output 119 Comparator configurations Suppose PGA1 is disabled or 1 121 Watchdog Prescaler 124 Watchdog Timer in Watchdog Mode WDTE 1 lene RED ny 128 Watchdog Timer in Timer Mode WDTE 0 129 Forcing ISP 140 NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 160 of 163 NXP Semiconductors UM10308 24 Contents P89LPC9331 9341 9351 9361 user manual 3 2 1 1 3 2 1 2 3 2 2 3 2 3 3 2 3 1 3 2 3 2 3 2 3 3 3 2 3 4 3 2 3 5 3 2 3 6 3 2 3 7 3 2 4 3 2 4 1 3 2 4 2 3 2 4 3 3 2 4 4 3 2 5 UM10308 Introduction 3 Pin 3 Pin description 5 Functional
2. 8 Block 9 Special function registers 10 Memory organization 28 GloCKS ch LE Ee RR 29 Enhanced 29 Clock 29 Oscillator Clock 29 Crystal oscillator 30 Low speed oscillator option 30 Medium speed oscillator option 30 High speed oscillator option 30 Clock 30 On chip RC oscillator option 30 Watchdog oscillator option 31 External clock input option 31 Clock source switching on the fly 32 Oscillator Clock OSCCLK wake up delay 33 CPU Clock CCLK modification DIVM register 33 Low power 34 A D 34 General description 34 A D features 34 Programmable Gain Amplifier PGA 891 9351 9361 36 calibration 37 Channel selection dependency 38 Temperature 38 ADC operating modes 39 Fixed channel single conversion mode 39 Fixed channel continuous conversion mode 39 Auto scan single conversion mode 40 Auto scan c
3. 9 6 1SE6 LVE6 LEE6Dd 168d SOEOLINN dXN jenuew 1 2102 15 05 12e qns siy uomeuuojur 6911091 80601 1 pamasa Su 72102 7 74 dXN Table 3 Special function registers P89LPC9331 9341 continued indicates SFRs that are bit addressable Name SBUF SCON SSTAT SP SPCTL SPSTAT SPDAT TAMOD TCON THO TH1 TLO TL1 TMOD TRIM WDCON Description SFR addr Serial Portdata 99 buffer register Bit address Serial port 98H control Serial port BAH extended status register Stack pointer 81H SPI control E2H register SPI status E1H register SPI data register Timer 0 and 1 8FH auxiliary mode Bit address Timer 0 and 1 88H control Timer 0 high 8CH Timer 1 high 8DH Timer 0 low 8AH Timer 1 low 8BH Timer 0 and 1 89H mode Internal 96H oscillator trim register Watchdog A7H control register Bit functions and addresses Reset value MSB LSB Hex Binary XX XXXX XXXX 9 9 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 07 0000 0111 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 0000 0100 SPIF WCOL 00 00 00 0000 0000 T1M2 TOM2 00 xxxO 8F 8E 8D 8C 8B 8A 89 88 TF1 1 TFO TRO I
4. UART break detect AUXR 6 brownout detect reset 002aae129 Fig 18 Block diagram of reset Table 51 Reset Sources register RSTSRC address DFh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOIF BOF POF R BK R WD R SF R EX Reset x 0 1 1 0 0 0 0 The value shown is for a power on reset Other reset sources will set their corresponding bits Table 52 Reset Sources register RSTSRC address DFh bit description Bit Symbol Description 0 external reset Flag When this bit is logic 1 it indicates external pin reset Cleared by software by writing a logic the bit or a Power on reset If RST is still asserted after the Power on reset is over R EX will be set R SF software reset Flag Cleared by software by writing a logic 0 to the bit or a Power on reset 2 RWD Watchdog Timer reset flag Cleared by software by writing a logic 0 to the bit or a Power on reset NOTE UCFG1 7 must be 1 3 break detect reset If a break detect occurs and EBRR AUXR1 6 is set to logic 1 a system reset will occur This bit is set to indicate that the system reset is caused by a break detect Cleared by software by writing a logic 0 to the bit or on a Power on reset 4 POF Power on Detect Flag When Power on Detect is activated the POF flag is set to indicate an initial power up condition The POF flag will remain set until cleared by softw
5. siy 6911092 80601 1 pamasa Su 72102 7 74 dXNO Table 5 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary TPCR2L Prescaler control TPCR2L7 TPCR2L 6 TPCR2L5 TPCR2L 4 TPCR2L 3 TPCR2L 2 TPCR2L 1 TPCR2L 0 00 0000 0000 register low TRIM Internal oscillator 96H TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O trim register WDCON Watchdog control A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK Mie register WDL Watchdog load C1H FF 1111 1111 WFEED1 Watchdog feed 1 C2H WFEED2 Watchdog feed 2 C3H 1 2 3 4 All ports in input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the P89LPC9351 9361 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after watchdog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset and watchdog reset the TRIM SFR is initialized with a f
6. f BUS UM10308 P89LPC9331 9341 9351 9361 user manual Rev 4 1 20 August 2012 User manual Document information Info Content Keywords P89LPC9331 9341 9351 9361 Absiract Technical information for the P89LPC9331 9341 9351 9361 device NXP Semiconductors UM10308 Revision history P89LPC9331 9341 9351 9361 user manual Rev Date Description 4 1 20120820 Table 5 and Table 127 updated reset value of DEECON register 4 20101014 Section 2 3 updated oscillator information Section 16 1 updated oscillator information Section 16 3 updated oscillator information e Section 16 5 updated oscillator information Section 18 corrected data EEPROM row fill information Table 11 updated oscillator information Table 124 updated oscillator information 3 20090617 Added information for the P89LPC9361 device 2 20090505 Added information for the P89LPC9331 and P89LPC9341 devices 1 20081118 Initial version Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 2 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 1 Introduction The
7. 45 88h bit description 64 Table 28 A D Input select ADINS address A3h bit Table 59 Real time Clock System Timer clock sources 68 description 45 Table 60 Real time Clock Control register RTCCON Table 29 Temperature Sensor control register TPSCON address D1h bit allocation 69 address FFCAh bit allocation Table 61 Real time Clock Control register RTCCON P89LPC9331 9341 46 address D1h bit description 70 Table 30 Temperature Sensor control register TPSCON Table 62 CCU prescaler control register high byte address FFCAh bit description TPCR2H address CBh bit allocation 72 91 9331 9341 46 Table 63 CCU prescaler control register high byte Table 31 PGAO Control register PGACONO address TPCR2H address CBh bit description 72 FFCAh bit allocation P89LPC9351 9361 46 Table 64 CCU prescaler control register low byte TPCR2L UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 157 of 163 NXP Semiconductors UM10308 Table 65 Table 66 Table 67 Table 68 Table 69 Table 70 Table 71 Table 72 Table 73 Table 74 Table 75 Table 76 Table 77 Table 78 Table 79 Table 80 Table 81 Table 82 Table 83 Table 84 Table 85 Table 86 Ta
8. 05 jea 12e qns si siy uomeuuojur 69110 C 80601 1 pamasa Su 72102 7 74 dXNO Table 5 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name OCRBL OCRCH OCRCL OCRDH OCRDL P1 P2 P3 POM1 POM2 P1M1 P1M2 P2M1 P2M2 Description SFR addr Output compare FAH B register low Output compare FDH C register high Output compare FCH C register low Output compare FFH D register high Output compare FEH D register low Bit address Port 0 80H Bit address Port 1 90H Bit address Port 2 Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Port 1 output 91H mode 1 Port 1 output 92H mode 2 Port 2 output A4H mode 1 Port 2 output A5H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 87 86 85 84 83 82 81 80 T1 KB7 CMP1 CMPREF CIN1A CIN1B CIN2A CIN2B H KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 OCC OCB RST INT1 INTO SDA TO SCL RXD TXD 6 5 4 2 1 0 SPICLK 55 5 MOSI OCD ICB B6 B5 B4 B3 B2 B1 0 XTAL1 XTAL2 POM1 7 1 6 POM1 5 POM1 4 POM1 3 0 1 2 1 1 1 0 11111111 POM2 7 2
9. 2 2 002 561 Fig 51 891 9351 9361 comparator input and output connections 14 2 Internal reference voltage An internal reference voltage Vretbg may supply a default reference when a single comparator input pin is used Please refer to the P89LPC9331 9341 9351 9361 data sheet for specifications 14 3 Comparator input pins Comparator input and reference pins maybe be used as either digital I O or as inputs to the comparator When used as digital I O these pins are 5 V tolerant However when selected as comparator input signals in CMPn lower voltage limits apply Please refer to the P89LPC9331 9341 9351 9361 data sheet for specifications UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 119 of 163 NXP Semiconductors U M1 0308 UM10308 14 4 14 5 P89LPC9331 9341 9351 9361 user manual Comparator interrupt Each comparator has an interrupt flag CMFn contained in its configuration register This flag is set whenever the comparator output changes state The flag may be polled by software or may be used to generate an interrupt The two comparators use one common interrupt vector The interrupt will be generated when the interrupt enable bit EC in the IEN1 register is set and the interrupt system is enabled via the EA bit in the IENO register If both comparators enable interrupts after
10. 57 RSet toe EE IR Eie 60 61 Timers 0 and 1 62 Mode 63 Mode 1 p EE Ri 63 Mode 2 zog bu RES ERR RR 64 Mode ore Red 64 6 6 lille ket eb ROI 64 Timer overflow toggle output 66 Real time clock system timer 66 Real time clock 67 Changing RTCS1 RTCSO 68 Real time clock interrupt wake up 68 Real time clock read 68 Reset sources affecting the Real time clock 68 Capture Compare Unit CCU 891 9351 9361 70 CCU Clock 70 CCU Clock prescaling 70 Basic timer 71 Output 73 Input capture 74 PWM operation 75 Alternating output mode 76 Synchronized PWM register update 77 I EMT TP Hae eae 77 continued gt gt NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 161 of 163 NXP Semiconductors UM10308 10 10 10 11 11 11 4 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 9 11 11 11 11 11 11 11 11 11 11 10 11 12 13 14 215 16 17 18 19 11 20 12 12 1 12 2 12 3 12 4 12 5
11. KBMASK KBPATN OCRAH OCRAL OCRBH Description SFR addr Input capture A ABH register high Input capture A AAH register low Input capture B AFH register high Input capture B AEH register low Bit address Interrupt enable 0 A8H Bit address Interrupt enable 1 Bit address Interrupt priority 0 BBH Interrupt priorityO 7 high Bit address Interrupt priority 1 F8H Interrupt priority 1 F7H high Keypad control 94H register Keypad interrupt 86H mask register Keypad pattern 93H register Output compare EFH A register high Output compare EEH A register low Output compare FBH B register high Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 AF AE AD AC AB AA A9 A8 EA EWDRT EBO ES ESR ET1 EX1 ETO 00 0000 0000 EF EE ED EC EB EA 9 E8 EADEE EST ECCU ESPI EC EKBI EI2C 0001 00 0 0000 BD BC BB BA 9 PWDRT PBO PS PSR PT1 PX1 PTO 0001 000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH 0001 x000 0000 PSRH FF FE FD FC FB FA F9 F8 PADEE PST PCCU PSPI PC PKBI 2 0001 00 0 0000 PSTH PCCUH PSPIH PCH PKBIH PI2CH 0001 00x0 0000 5 PATN KBIF 0001 xx00 _SEL 00 0000 0000 FF 11111111 00 0000 0000 00 0000 0000 00 0000 0000 9 6 1SE6 LVE6 LEE6Dd 168d SOEOLINN dXN jenuew asn 2102 15
12. 123 Watchdog 123 Feed sequence 124 Watchdog clock source 127 Watchdog Timer in Timer mode 128 Power down 129 Periodic wake up from power down without an external 129 Additional features 129 Software 130 Dual Data 130 Data EEPROM P89LPC9351 9361 131 Data EEPROM 132 Data EEPROM write 132 Hardware reset 133 Multiple writes to the DEEDAT register 133 Sequences of writes to DEECON and DEEDAT 133 Data EEPROM Row Fill 133 Data EEPROM Block Fill 134 Flash 134 General 134 134 Flash programming 135 Using Flash as data storage IAP Lite 135 In circuit programming ICP 139 ISP and IAP capabilities of the P89LPC9331 9341 9351 9361 139 139 Power on reset code execution 139 Hardware activation of Boot Loader 140 In system programming ISP 140 Using the In system programming 141 In appl
13. NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual TX clock DL JL write to SBUF shift gt transmit tart TXD Do X 02 X D3 X D4 X X 06 X stopbi TI A M INTLO 0 INTLO 1 Sum RXD ot X Di X X 5 X 06 Y stop bi shift receive 002aaa926 Fig 32 Serial Port Mode 1 only single transmit buffering case is shown 11 12 More about UART Modes 2 and 3 Reception is the same as in Mode 1 The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated a RI 0 and b Either SM2 0 or the received 9th data bit 1 If either of these conditions is not met the received frame is lost and RI is not set If both conditions are met the received 9th data bit goes into RB8 and the first 8 data bits go into SBUF TX clock JL n n n n n n Im write to SBUF shift transmit tart LO XI X 02 X 03 X 04 Y stopbi 0 INTLO 1 RX cx Jl JT T mn m m m mp IL RXD 16 reset bt DO X Di X D2 X D3 X D4 X D5 X 06 X D7 X RB8 shift IL n n pn n n n m RI 4 k SMODO 0 SMODO receive
14. UM10308 P89LPC9331 9341 9351 9361 user manual P2 0 ICB DACO AD03 P2 1 OCD AD02 P0 0 CMP2 KBIO ADO1 P1 7 OCC AD00 1 6 P1 5 RST Vss P3 1 XTAL1 P3 0 XTAL2 CLKOUT P1 4 INT1 P1 3 INTO SDA P1 2 TO SCL P2 2 MOSI P2 3 MISO Fig 2 P89LPC9351 9361 TSSOP28 pin configuration QO P89LPC9351FDH P89LPC9361FDH 002aad557 P2 7 ICA P2 6 0CA PO 1 CIN2B KBI1 AD10 P0 2 CIN2A KBI2 AD1 1 P0 3 CIN1B KBI3 AD12 PO 4 CIN1A KBI4 DAC1 AD13 5 5 VDD P0 6 CMP1 KBI6 P0 7 T1 KBI7 P1 0 TXD P1 1 RXD P2 5 SPICLK 2 4 55 P2 0 ICB DACO AD03 4 P1 7 OCC ADOO 3 PO 0 CMP2 KBIO ADO1 2 P2 1 OCD AD02 1 26 P0 1 CIN2B KBH AD10 28 P2 7 ICA 27 P2 6 0CA P1 6 OCB P1 5 RST Vss P3 1 XTAL1 P3 0 XTAL2 CLKOUT P1 4 INT1 P1 3 INTO SDA P89LPC9351FA Fig 3 28 pin configuration Lo eo r 8 olo 3 x x e 232 Oct ENMaA DL NN WN a P0 2 CIN2A KBI2 AD11 P0 3 CIN1B KBI3 AD12 P0 4 CIN1A KBI4 DAC1 AD13 P0 5 CMPREF KBI5 VDD P0 6 CMP1 KBI6 P0 7 T1 KBI7 002aad558 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 4 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 1 2 Pin description T
15. 2012 All rights reserved User manual Rev 4 1 20 August 2012 10 of 163 jenuew asn 2102 1snBny oz jeba jueuinoop siy E91 JO LL 80 0LWN pamasa Su 72102 7 74 dXN O Table 3 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 Name ADCONO ADCON 1 ADINS ADMODA ADMODB ADOBH ADOBL ADODATO ADODAT1 ADODAT2 ADODATS AD1BH AD1BL Description SFR addr Bit address Accumulator EOH A D control register 0 A D control 97H register 1 A D input A3H select A D mode COH register A A D mode A1H register B A D 0 BBH boundary high register A D 0 A6H boundary low register A D 0 data C5H register 0 A D 0 data C6H register 1 A D 0 data C7H register 2 A D 0 data register 3 A D_1 C4H boundary high register A D_1 BCH boundary low register Bit functions and addresses Reset value MSB E7 ENBIO ADI13 BNDI1 CLK2 E6 ENADCIO ENADCI1 ADI12 BURST1 CLK1 E5 TMMO 1 ADI11 SCC1 CLKO 4 EDGEO EDGE1 ADI10 SCAN1 INBNDO E3 ADCIO ADCI1 ADI03 BNDIO ENDAC1 E2 ENADCO ENADC1 ADIO2 BURSTO ENDACO E1 ADCS01 ADCS11 ADIO1 SCCO BSA1 LSB EO
16. DACO 1 1 input MUX AD10 Aninto AD11 AD12 ane L SAR AD13 lt T 8 DAC1 1 1 ae gt 4 Lr 10 comparators Fig 10 P89LPC9331 9341 ADC block diagram CONTROL LOGIC 002aae463 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 35 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual sen input MUX 00 PGAO SAR CECI CONTROL input MUX LOGIC AD10 Anin10 AD11 H AD12 Anin13 SAR AD13 1 DAC1 1 1 RRRAER CCLK gt 4 lt gt to comparators 002aad576 Fig 11 P89LPC9351 9361 ADC block diagram 3 2 1 UM10308 Programmable Gain Amplifier PGA P89LPC9351 9361 Additional PGA is integrated in each ADC module to improve the effective resolution of the ADC A single channel can be selected for amplification The block diagram of PGA is shown in Figure 12 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 36 of 163 NXP Semiconductors U M1 0308 UM10308 3 2 1 1 P89LPC93
17. PRE2 to PREO WDL in decimal Timeout Period Watchdog Clock Source in watchdog clock 400 KHz Watchdog 12 MHz CCLK 6 MHz cycles Oscillator Clock CCLK Watchdog Nominal Clock 000 0 33 82 5 us 5 50 us 255 8 193 20 5 ms 1 37 ms 001 0 65 162 5 us 10 8 us 255 16 385 41 0 ms 2 73 ms 010 0 129 322 5 us 21 5 us 255 32 769 81 9 ms 5 46 ms 011 0 257 642 5 us 42 8 us 255 65 537 163 8 ms 10 9 ms 100 0 513 1 28 ms 85 5 us 255 131 073 327 7 ms 21 8 ms 101 0 1 025 2 56 ms 170 8 us 255 262 145 655 4 ms 43 7 ms 110 0 2 049 5 12 ms 341 5 us 255 524 289 1 31 87 4 111 0 4097 10 2 ms 682 8 us 255 1 048 577 2 62 174 8 0 10308 All information provided this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 126 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341 9351 9361 user manual 16 3 Watchdog clock source The watchdog timer system has an on chip 400 KHz oscillator The watchdog timer can be clocked from the watchdog oscillator PCLK or low speed crystal oscillator refer to Figure 53 by configuring the WDCLK bit in the Watchdog Control Register WDCON and XTALWD bit in CLKCON register When the watchdog feature is enabled the timer must be fed regularly by software in order to prevent it from resetting the CPU Table 124 Watchdog input clock selection WDCLK WDCON 0 XTALWD CLKCON 4 Watchdog input clock selection 0 0 PCLK 1 0
18. When CRSEL 0 the 2 interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register The duty cycle does not need to be 50 The STA bit is START flag Setting this bit causes the 2 interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode The STO bit is STOP flag Setting this bit causes the 2 interface to transmit a STOP condition in master mode or recovering from an error condition in slave mode If the STA and STO are both set then STOP condition is transmitted to the I2C bus if it is in master mode and transmits a START condition afterwards If it is in slave mode an internal STOP condition will be generated but it is not transmitted to the bus Table 95 12 Control register 2 address D8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 2 5 5 CRSEL Reset x 0 0 0 0 0 x 0 Table 96 Control register 2 address D8h bit description Bit Symbol Description 0 CRSEL lt selection When set 1 Timer 1 overflow generates SCL when cleared 0 the internal SCL generator is used base on values of I2SCLH and I2SCLL 1 reserved 2 AA The Assert Acknowledge Flag When set to 1 an acknowledge low level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 The
19. master slave 5 MISO 8 BIT SHIFT 74 8 BIT SHIFT REGISTER Mes REGISTER SPICLK SPICLK SPI CLOCK ms GENERATOR port SS 8 5 REGISTER SPICLK gt port 55 gt 002aaa903 Fig 45 SPI single master multiple slaves configuration In Figure 45 SSIG SPCTL 7 bits for the slaves are logic 0 and the slaves are selected by the corresponding SS signals The SPI master can use any port pin including P2 4 SS to drive the SS pins 13 1 Configuring the SPI Table 111 shows configuration for the master slave modes as well as usages and directions for the modes Table 111 SPI master and slave selection SPEN SSIG 55 MSTR Master MISO MOSI SPICLK Remarks or Slave Mode 0 2 411 x SPI 2 301 2 2 1 2 5 SPI disabled P2 2 P2 3 P2 4 P2 5 are used Disabled as port pins 1 0 0 0 Slave output input Selected as slave 1 0 1 0 Slave Hi Z input X input Not selected MISO is high impedance to avoid bus contention 1 0 0 1 gt Slave output input P2 4 SS is configured as an input or 0 2 quasi bidirectional pin SSIG is 0 Selected externally as slave if SS is selected and is driven low The MSTR bit will be cleared to logic 0 when SS becomes low UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 111 of 163
20. 12 6 12 6 1 12 6 2 12 6 3 12 6 4 13 13 1 13 2 13 3 13 4 13 5 13 6 13 7 14 14 1 14 2 14 3 UM10308 PLL 78 CCU interrupt structure 79 UART ieu RR RR RR HER ce eee 82 Mode creer exi 82 Mode i acri enoto repudia deacons 82 Mode 82 Mode 3 sid dm eee deere abe 83 SFR 5 2 2522 5456 Hane 83 Baud Rate generator and selection 83 Updating the BRGR1 and BRGRO SFRs 83 Framing 84 Break 84 More about UART Mode 0 86 More about UART 1 87 More about UART Modes 2 and 3 88 Framing error and RI in Modes 2 and 3 with SM2 Edge deere aed LETT 88 Break 89 Double 89 Double buffering in different modes 89 Transmit interrupts with double buffering enabled Modes 1 2 3 89 The 9th bit bit 8 in double buffering Modes 1 2 and 90 Multiprocessor communications 91 Automatic address recognition 92 12 93 12 data 94 12 slave address register 94 2 control 95 12 Status reg
21. Fig 4 Fig 5 Fig 6 Fig 7 Fig 8 Fig 9 Fig 10 Fig 11 Fig 12 Fig 13 Fig 14 Fig 15 Fig 16 Fig 17 Fig 18 Fig 19 Fig 20 Fig 21 Fig 22 Fig 23 Fig 24 Fig 25 Fig 26 Fig 27 Fig 28 Fig 29 Fig 30 Fig 31 Fig 32 Fig 33 Fig 34 Fig 35 Fig 36 Fig 37 Fig 38 Fig 39 Fig 40 Fig 41 Fig 42 Fig 43 Fig 44 Fig 45 Fig 46 Fig 47 Fig 48 UM10308 P89LPC9331 9341 TSSOP28 pin configuration 3 P89LPC9351 9361 TSSOP28 pin configuration 4 28 pin configuration 4 Functional diagram P89LPC9331 9341 8 Functional diagram P89LPC9351 9361 8 Block diagram s iced idee tinii Phas ed eas 9 P89LPC9331 9341 9351 9361 memory map 28 Using the crystal 32 Block diagram of oscillator control 32 P89LPC9331 9341 ADC block diagram 35 P89LPC9351 9361 ADC block diagram 36 PGA block diagram 37 Interrupt sources interrupt enables and power down wake up 50 Quasi bidirectional 52 Open drain output 53 INPUUONY cs Paka 53 Push pull 54 Block diagram of 61 Timer counter 0 or 1 in Mode 0 13 bit counter 65 Timer counter 0 or 1 in mode 1 16 bit counter 65 Timer counter 0 or 1 in Mode 2
22. NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 111 SPI master and slave selection continued SPEN SSIG SSPin MSTR Master MISO MOSI SPICLK Remarks or Slave Mode 1 0 1 1 Master Hi Hi Z MOSI and SPICLK are at high impedance to idle avoid bus contention when the MAster is idle The application must pull up or pull down SPICLK depending on CPOL SPCTL 3 to avoid a floating SPICLK N Master output output MOSI and SPICLK are push pull when the active Master is active 1 1 P24l l 0 Slave output input 1 1 2 411 1 Master input output output 1 Selected as a port function 2 The MSTR bit changes to logic 0 automatically when SS becomes low in input mode and SSIG is logic 0 13 2 Additional considerations for a slave When CPHA equals zero SSIG must be logic 0 and the SS pin must be negated and reasserted between each successive serial byte If the SPDAT register is written while SS is active low a write collision error results The operation is undefined if CPHA is logic 0 and SSIG is logic 1 When equals one SSIG may be set to logic 1 If SSIG 0 the SS may remain active low between successive transfers can be tied low at all times This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line 13 3 Additional considerations for a master In SPI transfers are always initiated by the mas
23. OR 6 Mode 3 9 bit UART Variable see Table 81 Table 87 Serial Port Status register SSTAT address BAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DBMOD CIDIS DBISEL FE BR OE STINT Reset X X xX X X X 0 0 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 85 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 88 Serial Port Status register SSTAT address BAh bit description Bit Symbol Description 0 STINT Status Interrupt Enable When set 1 FE BR or OE can cause an interrupt The interrupt used vector address 0023h is shared with RI CIDIS 1 or the combined TI RI CIDIS 0 When cleared 0 FE BR OE cannot cause an interrupt Note FE BR or OE is often accompanied by a RI which will generate an interrupt regardless of the state of STINT Note that BR can cause a break detect reset if EBRR AUXR1 6 is set to logic 1 1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full before the software has read the previous character from the buffer i e when bit 8 of a new byte is received while RI in SCON is still set Cleared by software 2 BR Break Detect flag A break is detected when any 11 consecutive bits are sensed low Cleared by software 3 FE Framing error flag is set when the
24. SPI CLOCK GENERATOR PORT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SPICLK 1 1 1 1 1 1 1 1 1 002 901 1 1 1 Fig 43 SPI single master single slave configuration In Figure 43 SSIG SPCTL 7 for the slave is logic 0 and SS is used to select the slave The SPI master can use any port pin including P2 4 SS to drive the SS pin master slave 8 BIT SHIFT 8 BIT SHIFT REGISTER _ REGISTER SPICLOCK TE SPI CLOCK GENERATOR 99 GENERATOR 1 1 1 1 1 1 1 1 1 1 1 1 SPICLK 1 1 1 1 1 1 002aaa902 1 1 1 Fig 44 SPI dual device configuration where either be a master or a slave Figure 44 shows a case where two devices are connected to each other and either device can be a master or a slave When no SPI operation is occurring both can be configured as masters MSTR 1 with SSIG cleared to 0 and P2 4 SS configured in quasi bidirectional mode When a device initiates a transfer it can configure P2 4 as an output and drive it low forcing a mode change in the other device see Section 13 4 Mode change 55 to slave UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 110 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual
25. address E9h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A TICF2B TICF2A Reset 0 0 0 0 0 x 0 0 Table 77 CCU interrupt flag register TIFR2 address E9h bit description Bit Symbol Description 0 TICF2A Input Capture Channel A Interrupt Flag Bit Set by hardware when an input capture event is detected Cleared by software 1 TICF2B Input Capture Channel B Interrupt Flag Bit Set by hardware when an input capture event is detected Cleared by software E Reserved for future use Should not be set to logic 1 by user program TOCF2A Output Compare Channel A Interrupt Flag Bit Set by hardware when the contents of TH2 TL2 match that of OCRHA OCRLA Compare channel A must be enabled in order to generate this interrupt If EA bit in IENO ECCU bit in IEN1 and TOCIE2A bit are all set the program counter will vectored to the corresponding interrupt Cleared by software 4 TOCF2B Output Compare Channel B Interrupt Flag Bit Set by hardware when the contents of TH2 TL2 match that of OCRHB OCRLB Compare channel B must be enabled in order to generate this interrupt If EA bit in IENO ECCU bit in and TOCIE2B bit are set the program counter will vectored to the corresponding interrupt Cleared by software 5 TOCF2C Output Compare Channel C Interrupt Flag Bit Set by hardware when the contents of TH2 TL2 match that of OCRHC OCRLC Compare channel C must be enabled in order to generate this interrupt
26. as well as ECCU bit in IEN1 are all set the program counter will be vectored to the corresponding interrupt The user must manually clear the bit by writing a logic O to it Two bits in OCCRx the Output Compare x Mode bits OCMx1 and OCMXxO select what action is taken when a compare match occurs Enabled compare actions take place even if the interrupt is disabled All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 73 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual In order for a Compare Output Action to occur the compare values must be within the counting range of the CCU timer When the compare channel is enabled the I O pin which must be configured as an output will be connected to an internal latch controlled by the compare logic The value of this latch is zero from reset and can be changed by invoking a forced compare A forced compare is generated by writing a logic 1 to the Force Compare x Output bit FCOx bit in OCCRx Writing a one to this bit generates a transition on the corresponding I O pin as set up by OCMx1 OCMx0 without causing an interrupt In basic timer operating mode the bits always read zero Note This bit has a different function in PWM mode When an output compare pin is enabled and connected to the compare latch the state of the compare pin remains unchanged unt
27. 0 is shown no ending TX interrupt DBISEL SSTAT 4 0 double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6 0 is shown with ending TX interrupt DBISEL SSTAT 4 1 002aaa928 11 18 The 9th bit bit 8 in double buffering Modes 1 2 and 3 If double buffering is disabled DBMOD i e SSTAT 7 0 TB8 can be written before or after SBUF is written provided TB8 is updated before that TB8 is shifted out TB8 must not be changed again until after TB8 shifting has been completed as indicated by the Tx interrupt UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 90 of 163 NXP Semiconductors U M1 0308 UM10308 11 19 P89LPC9331 9341 9351 9361 user manual If double buffering is enabled TB8 MUST be updated before SBUF is written as TB8 will be double buffered together with SBUF data The operation described in the Section 11 17 Transmit interrupts with double buffering enabled Modes 1 2 and 3 becomes as follows 1 The double buffer is empty initially 2 The CPU writes to TB8 3 The CPU writes to SBUF 4 The SBUF TB8 data is loaded to the shift register and a Tx interrupt is generated immediately If there is more data go to 7 else continue on 6 6 If there is no more data then f DBISEL is logic 0 no more interru
28. 002aaa927 Fig 33 Serial Port Mode 2 or 3 only single transmit buffering case is shown 11 13 Framing error RI in Modes 2 and 3 with SM2 1 If SM2 1 in modes 2 and 3 RI and FE behaves as in the following table UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 88 of 163 NXP Semiconductors U M1 0308 UM10308 11 14 11 15 11 16 11 17 P89LPC9331 9341 9351 9361 user manual Table 89 FE and RI when SM 1 in Modes 2 3 Mode 6 RB8 RI FE SMODO 2 0 0 No RI when RB8 0 Occurs during STOP bit 1 Similar to Figure 33 with SMODO 0 RI Occurs during STOP occurs during RB8 one bit before FE bit 3 1 0 No RI when RB8 0 Will NOT occur 1 Similar to Figure 33 with SMODO 1 RI Occurs during STOP occurs during STOP bit bit Break detect A break is detected when 11 consecutive bits are sensed low and is reported in the status register SSTAT For Mode 1 this consists of the start bit 8 data bits and two stop bit times For Modes 2 3 this consists of the start bit 9 data bits and one stop bit The break detect bit is cleared in software or by a reset The break detect can be used to reset the device and force the device into ISP mode This occurs if the UART is enabled and the the EBRR bit AUXR1 6 is set and a break occurs Double buffering The UART ha
29. 0400h O3FFh 0000h 1 Fig 7 read protected joes Se eres a IAP calls only entry FFEFh Euge on SPECIAL FUNCTION DATA DATA FF1Fh 128 BYTES ON CHIP 51 ASM code usd REGISTERS DATA MEMORY STACK C code EEG DIRECTLY ADDRESSABLE AND INDIR ADDR DATA 128 BYTES ON CHIP SFFFh DATA MEMORY STACK DIRECT AND INDIR ADDR 4 REG BANKS R 7 0 ISP CODE 1 512 ISP serial loader entry points for UART auto baud I2C SPI etc 1 3E00h SECTOR 14 data memory DATA IDATA SECTOR 13 SECTOR 12 EXTENDED SFRs SECTOR 11 FFBOh SECTOR 10 RESERVED SECTOR 9 O1FFh DATA EEPROM 512 BYTES XDATA 512 BYTES P89LPC9351 9361 SECTOR 8 SFR ACCESS 0000h P89LPC9351 9361 0000h SECTOR 7 data EEPROM SECTOR 6 002aae090_NEW SECTOR 5 SECTOR 4 SECTOR 3 SECTOR 2 SECTOR 1 SECTOR 0 ISP code is located at the end of sector 3 on the P89LPC9331 at the end of sector 7 on the P89LPC9341 9351 and at the end of sector 15 on the P89LPC9361 P89LPC9331 9341 9351 9361 memory map UM10308 The various P89LPC9331 9341 9351 9361 memory spaces are as follows DATA 128 bytes of internal data memory space 00h 7Fh accessed via direct or indirect addressing using instruction other than MOVX and MOVC All or part of the Stack may be in this area IDATA Indirect Data 256 bytes of internal data memory space 0
30. 8 bit 65 Timer counter 0 Mode 3 two 8 bit counters 66 Timer counter 0 or 1 in mode 6 PWM 66 Real time clock system timer block diagram 67 Capture Compare Unit block diagram 71 Asymmetrical PWM downcounting 76 Symmetrical 76 Alternate output 77 Capture compare unit interrupts 80 Baud rate generation for UART Modes 1 3 84 Serial Port Mode 0 double buffering must be disabled ke VELO 87 Serial Port Mode 1 only single transmit buffering case is 88 Serial Port Mode 2 or 3 only single transmit buffering case is shown 88 Transmission with and without double buffering 90 I C bus 94 Format the Master Transmitter mode 98 Format of Master Receiver mode 99 A Master Receiver switches to Master Transmitter after sending Repeated Start 99 Format of Slave Receiver mode 100 Format of Slave Transmitter mode 100 serial interface block diagram 101 SPI block diagram 108 SPI single master single slave configuration 110 SPI dual device configuration where either can be a master
31. Auto scan single Auto scan single 0 1 0 Fixed channel 0 1 0 Fixed channel continuous continuous Dual channel Dual channel continuous continuous 1 0 0 Auto scan 1 0 0 Auto scan continuous continuous Conversion start modes Timer triggered start An A D conversion is started by the overflow of Timer 0 Once a conversion has started additional Timer 0 triggers are ignored until the conversion has completed The Timer triggered start mode is available in all A D operating modes This mode is selected by the TMMx bit and the ADCSx1 and ADCSx0 bits See Table 20 and Table 22 Start immediately Programming this mode immediately starts a conversion This start mode is available in all A D operating modes This mode is selected by setting the ADCSx1 and ADCSx0 bits in the ADCONXx register See Table 20 and Table 22 Edge triggered An A D conversion is started by rising or falling edge of P1 4 Once a conversion has started additional edge triggers are ignored until the conversion has completed The edge triggered start mode is available in all A D operating modes This mode is selected by setting the ADCSx1 and ADCSxO bits in the ADCONXx register See Table 20 and Table 22 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 41 of 163 NXP Semiconductors U M1 0308 UM10308 3 2 4 4 3 2 5 3 2 6 3
32. Boot ROM When the microcontroller contains a a 256 byte Boot ROM that is separate from the user s Flash program memory This Boot ROM contains routines which handle all of the low level details needed to erase and program the user Flash memory A user program simply calls a common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation Boot ROM operations include operations such as erase sector erase page program page CRC program security bit etc The Boot ROM occupies the program memory space at the top of the address space from FF00 to FFFFh thereby not conflicting with the user program memory space This function is in addition to the IAP Lite feature Power on reset code execution The P89LPC9331 9341 9351 9361 contains two special Flash elements the BOOT VECTOR and the Boot Status Bit Following reset the P89LPC9331 9341 9351 9361 examines the contents of the Boot Status Bit If the Boot Status Bit is set to zero power up execution starts at location 0000H which is the normal start address of the user s application code When the Boot Status Bit is set to one the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 139 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 93
33. If EA bit in IENO ECCU bit in IEN1 and TOCIE2C bit are all set the program counter will vectored to the corresponding interrupt Cleared by software 6 TOCF2D Output Compare Channel D Interrupt Flag Bit Set by hardware when the contents of TH2 TL2 match that of OCRHD OCRLD Compare channel D must be enabled in order to generate this interrupt If EA bit in IENO ECCU bit in IEN1 and TOCIE2D bit are all set the program counter will vectored to the corresponding interrupt Cleared by software 7 2 CCU Timer Overflow Interrupt Flag bit Set by hardware on CCU Timer overflow Cleared by software Table 78 CCU interrupt control register TICR2 address C9h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A TICIE2B TICIE2A Reset 0 0 0 0 0 x 0 0 Table 79 CCU interrupt control register TICR2 address C9h bit description Bit Symbol Description 0 TICIE2A Input Capture Channel A Interrupt Enable Bit If EA bit and this bit all be set when a capture event is detected the program counter will vectored to the corresponding interrupt 1 TICIE2B Input Capture Channel B Interrupt Enable Bit If EA bit and this bit all be set when a capture event is detected the program counter will vectored to the corresponding interrupt Reserved for future use Should not be set to logic 1 by user program TOCIE2A Output Compare Channel A Interrupt Enable Bit If EA bit and this bit are set to 1 whe
34. P in the PSW could be moved into TB8 When data is received the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved The baud rate is programmable to either 1 16 or 1 32 of the CCLK frequency as determined by the SMOD bit in PCON All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 82 of 163 NXP Semiconductors U M1 0308 UM10308 11 5 P89LPC9331 9341 9351 9361 user manual Mode 3 11 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 Mode 3 is the same as Mode 2 in all respects except baud rate The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 11 6 Baud Rate generator and selection In all four modes transmission is initiated by any instruction that uses SBUF as a destination register Reception is initiated in Mode 0 by the condition RI 0 and REN 1 Reception is initiated in the other modes by the incoming start bit if REN 1 SFR space The UART SFRs are at the following locations Table 80 UART SFR addresses Register Description SFR location PCON Power Control 87H SCON Serial Port UART Control 98H SBUF Serial Port UART Data Buffer 99H SADDR Serial Port UART Address A9
35. if SSIG bit 0 1 002 937 1 Not defined Fig 49 SPI master transfer format with CPHA 1 13 7 SPI clock prescaler select SPI clock prescaler selection uses the SPR1 SPRO0O bits in the SPCTL register see Table 107 14 Analog comparators Two analog comparators are provided on the P89LPC9331 9341 9351 9361 Input and output options allow use of the comparators in a number of different configurations Comparator operation is such that the output is a logic 1 which may be read in a register and or routed to a pin when the positive input one of two selectable pins is greater than the negative input selectable from a pin or an internal reference voltage Otherwise the output is a zero Each comparator may be configured to cause an interrupt when the output value changes In LPC9351 9361 the comparators inputs can be amplified by using PGA1 module The PGA1 can supply gain factors of 2x 4x 8x or 16x eliminating the need for external opamps in the end application Refer to Section 3 2 1 Programmable Gain Amplifier PGA P89LPC9351 9361 for PGA details 14 4 Comparator configuration Each comparator has a control register CMP1 for comparator 1 and CMP2 for comparator 2 The control registers are identical and are shown in Table 113 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual R
36. in the CCU Control Register 1 TCR21 The function of this bit depends on whether the timer is running in PWM mode or in basic timer mode In basic timer mode writing a one to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as zero In PWM mode writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow As long as the latch is pending TCOU2 will read as one and will return to zero when the latch takes place TCOU2 also controls the latching of all the Output Compare registers as well as the Timer Overflow Reload registers TOR2 10 5 Input capture Input capture is always enabled Each time a capture event occurs on one of the two input capture pins the contents of the timer is transferred to the corresponding 16 bit input capture register ICRAH ICRAL or ICRBH ICRBL The capture event is defined by the UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 74 of 163 NXP Semiconductors U M1 0308 UM10308 10 6 P89LPC9331 9341 9351 9361 user manual Input Capture Edge Select ICESx bit x being A or B in the CCCRx register The user will have to configure the associated I O as an input in order for an external event to trigger a capture A simple noise filter can be enabled on the input capture input When the Input Capt
37. logic 1 read n Bytes acknowledge A acknowledge SDA LOW E from Master to Slave A not acknowledge SDA HIGH from Slave to Master S START condition P STOP condition 002 929 Fig 36 Format the Master Transmitter mode Master Receiver mode In the Master Receiver Mode data is received from a slave transmitter The transfer started in the same manner as in the Master Transmitter Mode When the START condition has been transmitted the interrupt service routine must load the slave address and the data direction bit to 2 Data Register I2DAT The SI bit must be cleared before the data transfer can continue When the slave address and data direction bit have been transmitted and an acknowledge bit has been received the SI bit is set and the Status Register will show the status code For master mode the possible status codes are 40H 48H or 38H For slave mode the possible status codes are 68H 78H or BOH Refer to Table 104 for details All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 98 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave A not acknowledge SDA HIGH from Slave to Master S START con
38. 0 Symbol I2ADR 6 l2ADR 5 I2ADR 4 I2ADR 3 I2ADR 2 I2ADR 1 2 0 GC Reset 0 0 0 0 0 0 0 0 Table 94 slave address register IZADR address DBh bit description Bit Symbol Description 0 GC General call bit When set the general call address 00H is recognized otherwise it is ignored 1 7 I2ADR1 7 7 bit own slave address When in master mode the contents of this register has no effect All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 94 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 12 3 2 control register The CPU can read and write this register There are two bits are affected by hardware the SI bit and the STO bit The SI bit is set by hardware and the STO bit is cleared by hardware CRSEL determines the SCL source when the 2 is in master mode In slave mode this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master 2 device When CRSEL 1 the 2 interface uses the Timer 1 overflow rate divided by 2 for the 2 clock rate Timer 1 should be programmed by the user in 8 bit auto reload mode Mode 2 Data rate of I C bus Timer overflow rate 2 PCLK 2 256 reload value If fos 12 MHz reload value is 0 to 255 so 2 data rate range is 11 72 Kbit sec to 3000 Kbit sec
39. 0 0 Table 30 Temperature Sensor control register TPSCON address FFCAh bit description P89LPC9331 9341 Bit Symbol Description 1 0 Reserved 3 2 TSEL1 TSELO Temperature sensor mux selection Select among temperature sensor internal reference voltage and ADO3 00 ADO3 01 internal reference voltage 10 temperature sensor enabled and selected 11 ADO3 4 7 Reserved Table 31 PGAO Control register PGACONO address FFCAh bit allocation P89LPC9351 9361 Bit 7 6 5 4 3 2 1 0 Symbol ENPGAO PGASELO1 PGASELOO PGATRIMO TSEL1 TSELO PGAGO1 PGAGOO Reset 0 0 0 0 0 0 0 0 Table 32 PGAO Control register PGACONO address FFCAh bit description P89LPC9351 9361 Bit Symbol Description 1 0 PGAGO1 PGA Gain selection bits PGAGOO 00 Gain 2 01 Gain 4 10 Gain 8 11 Gain 16 3 2 TSEL1 TSELO Temperature sensor mux selection Select among temperature sensor internal reference voltage and ADOS 00 ADOS 01 internal reference voltage 10 temperature sensor enabled and selected 11 ADO3 4 PGATRIMO PGAO trim enable bit If set PGAO is grounded for calibration mode If cleared normal operation mode 6 5 PGASELO1 PGA input channel selection PGASELOO 00 ADOO using PGA 01 ADO1 using PGA 10 ADO2 using PGA 11 ADO3 Bandgap Temperature sensor using PGA 7 ENPGAO PGAO enable If set enable PGAO If cleared disable PGAO UM10308 All information provided in this document is subject to legal disclaimers N
40. 0000 ENBIO ENADCIO TMMO EDGEO ADCIO ADCSO1 ADCSOO 00 0000 0000 ENADCIH 1 EDGE1 ADCH ENADC1 ADCS11 ADCS10 00 0000 0000 ADI13 ADI12 ADI11 ADI10 ADIO3 ADIO2 ADIO1 ADIOO 00 0000 0000 BNDI1 BURST1 SCC1 5 1 BNDIO BURSTO SCCO SCANO 00 0000 0000 CLK2 CLK1 CLKO INBNDO ENDAC1 ENDACO BSA1 BSAO 00 000x 0000 FF 1111 1111 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 1111 1111 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 956 1656 1756 155694168 SOEOLINN dXN jenuew asn 2102 1snBny 0 ed 12e qns siy 69110 02 80601 1 pamasa Su 72102 A a dXNO Table 5 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name AD1DATS3 AUXR1 B BRGROE BRGR1EI BRGCON CCCRA CCCRB CCCRC CCCRD 1 2 DEECON DEEDAT DEEADR Description SFR addr A D_1 data F5H register 3 Auxiliary function A2H register Bit address B register FOH Baud rate BEH generator 0 rate low Baud rate BFH generator 0 rate high Baud rate BDH generator 0 control Capture compare EAH A control register Capture compare EBH B control register Capture compare ECH C control register Capture compare EDH D control register Comparato
41. 125 hardware to from I2DAT to I2CON hardware STA 5 51 AA 88H Previously Read data byte or 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or own SLA address general address Data od read data byte 0 0 0 1 Switched to not addressed SLA received NACK mode Own SLA will be recognized has been returned general call address will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free 90H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned General call Data fead data byte 0 0 1 Data byte will be received and has been will be returned received ACK has been returned 98H Previously Read data byte 0 0 0 0 Switched to not addressed SLA addressed with mode no recognition of own SLA or General call Data General call address has been read data byte 0 0 0 1 Switched to not addressed SLA received NACK mode Own slave address will be has been returned recognized General call address will be recognized if IZADR 0 1 read data byte 1 0 0 0 Switched to not addressed S
42. 3 Write any address to DEEADR Note that the entire address is ignored in a block fill operation Poll EWERRt flag If EWERR1 DEECON 2 bit is logic 1 BOD EEPROM occurred Vdd 2 4V and Data EEPROM program is blocked If both the EIEE IEN1 7 bit and the EA IENO 7 bit are logic 1s wait for the Data EEPROM interrupt then read poll the EEIF DEECON 7 bit until it is set to logic 1 If EIEE or EA is logic 0 the interrupt is disabled and only polling is enabled When EEIF is logic 1 the operation is complete Poll EWERRO flag If EWERRO DEECON 1 bit is logic 1 it means BOD EEPROM occurred Vdd 2 4V during program or erase and the previous operation may not be correct 19 Flash memory UM10308 19 1 General description The P89LPC9331 9341 9351 9361 Flash memory provides in circuit electrical erasure and programming The Flash can be read and written as bytes The Sector and Page Erase functions can erase any Flash sector 1 kB or page 64 bytes The Chip Erase operation will erase the entire program memory Five Flash programming methods are available On chip erase and write timing generation contribute to a user friendly programming interface The P89LPC9331 9341 9351 9361 Flash reliably stores memory contents even after 100 000 erase and program cycles The cell is designed to optimize the erase and programming mechanisms P89LPC9331 9341 9351 9361 uses Vpp as the supply voltage to perform the Program Erase
43. 4 MHz to 18 MHz 2 9 Oscillator Clock OSCCLK wake up delay The P89LPC9331 9341 9351 9361 has an internal wake up timer that delays the clock until it stabilizes depending on the clock source used If the clock source is any of the three crystal selections low medium and high frequencies the delay is 1024 OSCCLK cycles plus 60 us to 100 us If the clock source is the internal RC oscillator the delay is 200 us to 300 us If the clock source is watchdog oscillator or external clock the delay is 32 OSCCLK cycles 2 10 CPU Clock CCLK modification DIVM register The OSCCLK frequency can be divided down by an integer up to 510 times by configuring a dividing register DIVM to provide CCLK This produces the CCLK frequency using the following formula CCLK frequency fosc 2N Where fosc is the frequency of OSCCLK is the value of DIVM UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 33 of 163 NXP Semiconductors U M1 0308 2 11 P89LPC9331 9341 9351 9361 user manual Since ranges from 0 to 255 the CCLK frequency can be in the range of fose to 210 for 0 CCLK fosc This feature makes it possible to temporarily run the CPU at a lower rate reducing power consumption By dividing the clock the CPU can retain the ability to respond to events other than those that can cause interrupts i e events t
44. 500 ADCS10 ADIOO SCANO BSAO Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 000x 0000 FF 1111 1111 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 1111 1111 00 0000 0000 956 1656 1756 155694168 SOEOLINN dXN jenuew asn 2102 15 02 ed jeba 12e qns siy 91 JO ZL 80601 1 pamasa Su 72102 dXN Table 3 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 continued Name AD1DATO AD1DAT1 AD1DAT2 AD1DAT3 AUXR1 B BRGRO I BRGR1EI BRGCON 1 2 DIVM DPTR DPH SFR addr Description A D_1 data D5H register 0 A D_1 data D6H register 1 A D_1 data D7H register 2 A D_1 data F5H register 3 Auxiliary A2H function register Bit address B register FOH Baud rate BEH generator 0 rate low Baud rate BFH generator 0 rate high Baud rate BDH generator 0 control Comparator 1 ACH control register Comparator 2 ADH control register CPU clock 95H divide by M control Data pointer 2 bytes Data pointer 83H high Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 00 00
45. 9351 9361 user manual Table 81 UART baud rate generation continued SCON 7 SCON 6 PCON 7 BRGCON A Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 1 0 0 X 1 X CCLKy 6 1 1 0 0 CCL 556 TH1 64 1 0 COL 56 1 2 X 1 CCLK BRGR1BRGRO 16 Table 82 Baud Rate Generator Control register BRGCON address BDh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SBRGS BRGEN Reset x x 0 0 Table 83 Baud Rate Generator Control register BRGCON address BDh bit description Bit Symbol Description 0 BRGEN Baud Rate Generator Enable Enables the baud rate generator BRGR1 and BRGRO can only be written when BRGEN 0 1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and 3 see Table 81 for details 2 7 reserved timer 1 overflow PCLK based aii 5 2 baud rate modes 1 and 3 SMOD1 0 baud rate generator SBRGS 1 CCLK based 002aaa897 Fig 30 Baud rate generation for UART Modes 1 3 Framing error A Framing error occurs when the stop bit is sensed as a logic 0 A Framing error is reported in the status register SSTAT In addition if SMODO 6 is 1 framing errors can be made available in SCON 7 If SMODO is 0 SCON 7 is SMO It is recommended that SMO and SM1 SCON 7 6 are programmed when SMODO is logic 0 Break detect A break detect is reported in the status registe
46. A D has been enabled All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 42 of 163 NXP Semiconductors U M1 0308 3 2 9 P89LPC9331 9341 9351 9361 user manual When used as digital I O these pins are 5 V tolerant If selected as input signals in ADINS these pins will be tolerant if the corresponding A D is enabled and the device is not in power down Otherwise the pin will remain 5 V tolerant Please refer to the P89LPC9331 9341 9351 9361 data sheet for specifications Power down and Idle mode In Idle mode the A D converter if enabled will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A D interrupt is enabled If PGAs temperature sensor or A D is enabled it will consume power Power can be reduced by disabling the PGAs temperature sensor and A D If ADC is configured to be in power down mode via PCONA 4 the internal clock to the ADC is disabled During ADCO power down mode configuration of PGAO can not be changed by writing to the PGACONO register However PGA1 can still be configured if either the ADC1 or the analog comparator is enabled or running To fully power down the ADC the user should clear the ENADC bits in ADCONXx registers PGA can be disabled via clearing ENPGAx bit and temperature sensor be disabled via setting TSEL1 0 not to 10
47. All bytes to be programmed must be within the same page All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 136 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Write the data for the next byte to be programmed to FMDATA Repeat writing of FMADRL and or FMDATA until all desired bytes have been loaded into the page register e Write the page address in user code memory to FMADRH and FMADRL 7 6 if not previously included when writing the page register address to FMADRL 5 0 Write the erase program command 68H to FMCON starting the erase program cycle Read FMCON to check status If aborted repeat starting with the LOAD command Table 129 Flash Memory Control register FMCON address E4h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol R z 8 HVA HVE 5 Symbol W 7 FMCMD 6 5 4 FMCMD 3 2 FMCMD 1 FMCMD 0 Reset 0 0 0 0 0 0 0 0 Table 130 Flash Memory Control register FMCON address E4h bit description Bit Symbol Access Description 0 Ol R Operation interrupted Set when cycle aborted due to an interrupt or reset FMCMD 0 W Command byte bit 0 1 SV R Security violation Set when an attempt is made to program erase or CRC a secured sector or page FMCMD 1 Command byte bit 1 2 HVE FMCMD 2 3 HVA High voltage error
48. Bits EDISx SPEDISx MOVCDISx Effects on Programming 0 0 0 None 0 0 1 Security violation flag set for sector CRC calculation for the specific sector Security violation flag set for global CRC calculation if any MOVCDISx bit is set Cycle aborted Memory contents unchanged CRC invalid Program erase commands will not result in a security violation 0 1 x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Sector erase and global erase are allowed 1 X x Security violation flag set for program commands or an erase page command Cycle aborted Memory contents unchanged Global erase is allowed 19 19 Boot Vector register Table 143 Boot Vector BOOTVEC bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BOOTV4 BOOTV2 BOOTV1 BOOTVO Factory default 0 0 0 1 1 1 1 1 Table 144 Boot Vector BOOTVEC bit description Bit Symbol Description 0 4 BOOTV 0 4 Boot vector If the Boot Vector is selected as the reset address the P89LPC9331 9341 9351 9361 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset 5 7 reserved 19 20 Boot status register Table 145 Boot Status BOOTSTAT bit allocation Bit 7 6 5 4 3 2 1 0 Symbol DCCP CWP AWP E BSB Factory default 0 0 0 0 0 0 0 1 value UM10308 All information provided in this document is subject
49. Data EEPROM program erase protection BOD EEPROM FLASH is always on except in power down or total power down mode PCON 1 1 It can not be disabled in software BOD EEPROM FLASH has only 1 trip voltage level of 2 4 V When voltage supply is lower than 2 4 V the BOD EEPROM FLASH is tripped and flash Data EEPROM program erase is blocked If brownout detection is enabled the brownout condition occurs when Vpp falls below the brownout trip voltage and is negated when Vpp rises above the brownout trip voltage For correct activation of Brownout Detect certain Vpp rise and fall times must be observed Please see the data sheet for specifications Table 44 BOD Trip points configuration BOE1 BOEO BOICFG1 BOICFGO BOD Reset BOD UCFG1 5 UCFG1 3 BOICFG 1 BOICFG 0 Interrupt 0 0 0 0 Reserved 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 2 2V 2 4V 0 1 1 0 2 2V 2 6V 0 1 1 1 2 2V 3 2V 1 0 0 0 Reserved 1 0 0 1 1 0 1 0 2 4V 2 6V 1 0 1 1 2 4V 3 2V 1 1 0 0 Reserved 1 1 0 1 1 1 1 0 1 1 1 1 3 0V 3 2V All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 56 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 45 BOD Reset and BOD Interrupt configuration PMOD1 PMODO PCON 1 0 EBO EA BOD BOD PCON 4 5 7 Reset Interrupt 11 total power down X X X N N 1
50. In Power down mode or Total Power down mode the A D PGA and Temp sensor do not function Table 19 A D Control register 0 ADCONO address 8Eh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENBIO ENADCIO TMMO EDGEO ADCIO ENADCO ADCS01 ADCS00 Reset 0 0 0 0 0 0 0 0 Table 20 A D Control register 0 ADCONO address 97h bit description Bit Symbol Description 1 0 ADCSO1 ADCSOO A D start mode bits see below 00 Timer Trigger Mode when TMMO 1 Conversions starts on overflow of Timer 0 When TMMO 0 no start occurs stop mode 01 Immediate Start Mode Conversion starts immediately 10 Edge Trigger Mode Conversion starts when edge condition defined by bit EDGEO occurs 2 ENADCO Enable ADCO When set 1 enables ADCO when 0 the ADC is in power down 3 ADCIO A D Conversion complete Interrupt 0 Set when any conversion or set of multiple conversions has completed Cleared by software 4 EDGEO An edge conversion start is triggered by a falling edge on P1 4 when EDGEO 0 while in edge triggered mode An edge conversion start is triggered by a rising edge on P1 4 when EDGEO 1 while in edge triggered mode 5 TMMO Timer Trigger Mode 0 Selects either stop mode TMMO 0 or timer trigger mode 1 when the ADCSO1 and ADCSOO bits 00 6 ENADCIO Enable A D Conversion complete Interrupt 0 When set will cause an interrupt if the ADCIO flag is set and the A D interrupt is enabled 7 ENBIO Enable A D bo
51. MOSI Master Out Slave In pin and flows from slave to master on the MISO Master In Slave Out pin The SPICLK signal is output in the master mode and is input in the slave mode If the SPI system is disabled i e SPEN SPCTL 6 0 reset value these pins are configured for port functions e SS is the optional slave select pin In a typical configuration an SPI master asserts one of its port pins to select one SPI device as the current slave An SPI slave device uses its SS pin to determine whether it is selected The SS is ignored if any of the following conditions are true If the SPI system is disabled i e SPCTL 6 0 reset value Ifthe SPI is configured as a master i e SPCTL 4 1 and P2 4 is configured as an output via the P2M1 4 and P2M2 4 SFR bits Ifthe SS pin is ignored i e SSIG SPCTL 7 bit 1 this pin is configured for port functions Note that even if the SPI is configured as a master MSTR 1 it can still be converted to a slave by driving the SS pin low if P2 4 is configured as input and SSIG 0 Should this happen the SPIF bit SPSTAT 7 will be set see Section 13 4 Mode change on SS Typical connections are shown in Figure 43 to Figure 45 Table 106 SPI Control register SPCTL address E2h bit allocation Bit 7 6 5 4 3 2 Symbol SSIG SPEN DORD MSTR CPOL CPHA Reset 0 0 0 0 0 1 1 0 SPR1 SPRO 0 0 All information provided in this documen
52. P89LPC9331 9341 9351 9361 user manual Table 55 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol T1M2 TOM2 Reset x x x 0 x x x 0 Table 56 Timer Counter Auxiliary Mode register TAMOD address 8Fh bit description Bit Symbol Description 0 TOM2 Mode Select for Timer 0 These bits are used with the 2 bit in the TAMOD register to determine the Timer 0 mode see Table 56 1 3 reserved 4 T1M2 Mode Select for Timer 1 These bits are used with the T1M2 bit in the TAMOD register to determine the Timer 1 mode see Table 56 The following timer modes are selected by timer mode bits TnM 2 0 000 8048 Timer serves as 5 bit prescaler Mode 0 001 16 bit Timer Counter THn and are cascaded there is no prescaler Mode 1 010 8 bit auto reload Timer Counter THn holds a value which is loaded into TL n when it overflows Mode 2 011 Timer 0 is a dual 8 bit Timer Counter in this mode TLO is an 8 bit Timer Counter controlled by the standard Timer 0 control bits THO is an 8 bit timer only controlled by the Timer 1 control bits see text Timer 1 in this mode is stopped Mode 3 100 Reserved User must not configure to this mode 101 Reserved User must not configure to this mode 110 PWM mode see Section 8 5 111 Reserved User must not configure to this mode 5 7 reserved 8 1 Mod
53. RO write data to page register INC RO point to next byte DJNZ R3 LOAD PAGE do until count is zero OV FMCON else erase amp program the page OV R7 FMCON copy status for return OV A R7 read status ANL 0FH save only four lower bits BAD i CLR clear error flag if good RET and return BAD SETB C set error flag RET and return A C language routine to load the page register and perform an erase program operation is shown below include lt REG9351 H gt unsigned char idata dbytes 64 data buffer unsigned char Fm stat status result bit PGM USER unsigned char unsigned char bit prog fail void main prog_fail PGM_USER 0x1F 0xC0 bit PGM_USER unsigned char page_hi unsigned char page_lo define LOAD0x00 clear page register enable loading define 0 68 erase amp program page unsigned char i loop count FMCON LOAD load command clears page reg FMADRH page hi FMADRL page 10 write my page address to addr regs for 1 0 1 lt 64 1 1 1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 138 of 163 NXP Semiconductors U M1 0308 UM10308 19 5 19 6 19 7 19 8 P89LPC9331 9341 9351 9361 user manual FMDATA dbytes i FMCON EP erase amp prog page command Fm_stat FMCON read the result status if Fm stat amp 0
54. SPICLK 16 P2 5 Port 2 bit 5 SPICLK SPI clock When configured as master this is output when configured as slave this pin is input P2 6 OCA 27 P2 6 Port 2 bit 6 Output Compare A P89LPC9351 9361 P2 7 ICA 28 y o P2 7 Port 2 bit 7 ICA Input Capture A P89LPC9351 9361 P3 0 to P3 1 Port 3 Port 3 is 2 bit I O port with a user configurable output type During reset Port 3 latches are configured in the input only mode with the internal pull up disabled The operation of Port 3 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details All pins have Schmitt trigger inputs Port 3 also provides various special functions as described below P3 0 XTAL2 9 P3 0 Port 3 bit 0 CLKOUT XTAL2 Output from the oscillator amplifier when a crystal oscillator option is selected via the flash configuration CLKOUT CPU clock divided by 2 when enabled via SFR bit ENCLK TRIM 6 It can be used if the CPU clock is the internal RC oscillator watchdog oscillator or external clock input except when XTAL1 XTAL2 are used to generate clock source for the RTC system timer P3 1 XTAL1 8 1 Port 3 bit 1 XTAL1 Input to the oscillator circuit and internal clock generator circuits when selected via the flash configuration It ca
55. Set when an error occurs in the high voltage generator Command byte bit 2 High voltage abort Set if either an interrupt or BOD FLASH is detected during a program or erase cycle Command byte bit 3 reserved Command byte bit 4 Command byte bit 5 Command byte bit 6 Command byte bit 7 FMCMD 3 7 FMCMD 4 FMCMD 5 FMCMD 6 FMCMD 7 oan A gt gt gt gt gt An assembly language routine to load the page register and perform erase program operation is shown below P pgm user code fO CK Kk ek ek e k ek e kx kk e k e KK kk kx kx kx ke kx kk xk kk kkkkkkkkkx f Inputs R3 number of bytes to program byte x R4 page address MSB byte R5 page address LSB byte R7 pointer to data buffer in RAM byte Outputs R7 status byte UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 137 of 163 NXP Semiconductors UM10308 UM10308 P89LPC9331 9341 9351 9361 user manual clear on no error set on error bs ER EEA IER ER LOAD EQU 00H EP EQU 68H PGM USER OV FMCON LOAD load command clears page register OV FMADRH R4 get high address OV FMADRL R5 get low address MOV A R7 i OV get pointer into RO LOAD_PAGE OV FMDAT
56. Table 127 Data Register DEEDAT is used for writing data to or reading data from the Data EEPROM Table 127 Data EEPROM control register DEECON address F1h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol HVERR ECTL1 ECTLO EWERR EWERR EADR8 1 0 Reset 1 0 0 0 0 0 0 0 Table 128 Data EEPROM control register DEECON address F1h bit description Bit Symbol Description 0 EADR8 Most significant address bit 8 of the Data EEPROM EADR7 0 are DEEADR 1 EWERR Data EEPROM write error flag 0 Set when Vpp lt 2 4V during program or erase 0 operation to indicate the previous operation may not be correct Can be cleared by power on reset watchdog reset or software write 2 EWERR Data EEPROM write error flag 1 Set when a program or erase is requested and 1 Vpp lt 2 4V Can be cleared by power on reset watchdog reset or software write Reserved 5 4 ECTL1 0 Operation mode selection The following modes are selected by ECTL 1 0 00 Byte read write mode 01 Reserved 10 Row 16 bytes fill 11 Block fill 512 bytes 6 HVERR High voltage error Indicates a programming voltage error during program or erase 7 Data EEPROM interrupt flag Set when a read or write finishes reset by software Byte Mode In this mode data can be read and written to one byte at a time Data is in the DEEDAT register and the address is in the DEEADR register Each write requires approximately 4 ms to
57. UART except that Timer 2 overflow cannot be used as a baud rate source The P89LPC9331 9341 9351 9361 does include an independent Baud Rate Generator The baud rate can be selected from the oscillator divided by a constant Timer 1 overflow or the independent Baud Rate Generator In addition to the baud rate generation enhancements over the standard 80C51 UART include Framing Error detection break detect automatic address recognition selectable double buffering and several interrupt options The UART can be operated in 4 modes as described in the following sections Mode 0 Serial data enters and exits through RXD TXD outputs the shift clock 8 bits are transmitted or received LSB first The baud rate is fixed at 1 16 of the CPU clock frequency Mode 1 10 bits are transmitted through TXD or received through RXD a start bit logic 0 8 data bits LSB first and a stop bit logic 1 When data is received the stop bit is stored in RB8 in Special Function Register SCON The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator see Section 11 6 Baud Rate generator and selection Mode 2 11 bits are transmitted through TXD or received through RXD start bit logic 0 8 data bits LSB first a programmable 9th data bit and a stop bit logic 1 When data is transmitted the 9th data bit TB8 in SCON can be assigned the value of 0 or 1 Or for example the parity bit
58. UM10308 The AUXR 1 register contains several special purpose control bits that relate to several chip features AUXR1 is described in Table 126 Table 125 AUXR1 register address A2h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKLP EBRR ENT1 ENTO SRST 0 DPS Reset 0 0 0 0 0 0 x 0 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 129 of 163 NXP Semiconductors U M1 0308 UM10308 17 1 17 2 P89LPC9331 9341 9351 9361 user manual Table 126 AUXR1 register address A2h bit description Bit Symbol Description 0 DPS Data Pointer Select Chooses one of two Data Pointers 1 Not used Allowable to set to a logic 1 2 0 This bit contains a hard wired 0 Allows toggling of the DPS bit by incrementing AUXR 1 without interfering with other bits in the register 3 SRST Software Reset When set by software resets the P89LPC9331 9341 9351 9361 as if a hardware reset occurred 4 ENTO When set the P1 2 pin is toggled whenever Timer 0 overflows The output frequency is therefore one half of the Timer 0 overflow rate Refer to Section 8 Timers 0 and 1 for details 5 When set the 7 pin is toggled whenever Timer 1 overflows The output frequency is therefore one half of the Timer 1 overflow rate Refer to Section 8 Timers 0 and 1 for details 6 EBRR UART Break Detect Reset Enable If logic
59. XRL dir data Exclusive OR immediate to direct byte 3 2 63 CLRA Clear A 1 1 E4 CPLA Complement A 1 1 F4 SWAP A Swap Nibbles of A 1 1 C4 RLA Rotate A left 1 1 23 RLC A Rotate A left through carry 1 1 33 Rotate A right RRA 1 1 03 Rotate A right through carry 1 1 13 DATA TRANSFER MOV A Rn Move register to A 1 1 E8 to EF MOV A dir Move direct byte to A 2 1 E5 Move indirect memory to A MOV A Ri 1 1 E6 to E7 MOV A data Move immediate to A 2 1 74 MOV Rn A Move A to register 1 1 F8 to FF MOV Rn ir Move direct byte to register 2 2 A8 to AF MOV Rn data Move immediate to register 2 1 78 to 7F MOV dir A Move A to direct byte 2 1 F5 MOV dir Rn Move register to direct byte 2 2 88 to 8F MOV dir dir Move direct byte to direct byte 3 2 85 MOV dir Ri Move indirect memory to direct byte 2 2 86 to 87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 to F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 to A7 MOV Ri data Move immediate to indirect memory 2 1 76 to 77 MOV data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 94 MOVX A Ri Move external data A8 to A 1 2 E2 to MOVX A DPTR Move external data A16 to A 1 2 EO MOVX Ri A Move A to external data A8 1 2 F2 to F3 MOVX QDPTR A Move A to external data A16 1 2 FO PUSH dir Push direct byte onto stack 2 2
60. a clock source between 0 5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and 32 MHz in PWM mode asymmetrical or symmetrical The PLL contains a 4 bit divider PLLDV3 0 bits in the TCR21 register to help divide PCLK into a frequency between 0 5 MHz and 1 MHz CCU Clock prescaling This CCUCLK can further be divided down by a prescaler The prescaler is implemented as a 10 bit free running counter with programmable reload at overflow Writing a value to the prescaler will cause the prescaler to restart All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 70 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual REGISTER 4 16 SHADOW REGISTER TOR2H TO TOR2L M 16 TIMER RELOAD 16 BIT CAPTURE 16 BIT UP DOWN TIMER Ec WITH RELOAD REGISTER ICRxH L ICNFx ICESx ICB 10 BIT DIVIDER Ft 002aab009 gt 4BIT 32x PLL DIVIDER Fig 25 Capture Compare Unit block diagram 16 BIT COMPARE VALUE OCD y OCC Jesse E OCA COMPARE CHANNELS A TO D OVERFLOW UNDERFLOW NOISE EDGE ICA FILTER SELECT X INTERRUPT FLAG TICF2x SET CAPTURE CHANNELS A B 10 3 UM10308 Basic timer operation The Timer is a free running up down counter counting at the pace determined by the prescaler The timer
61. accessed using 512 the MOVX instructions P89LPC9351 9361 UM10308 2 1 2 2 2 2 1 Enhanced CPU The P89LPC9331 9341 9351 9361 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices A machine cycle consists of two CPU clock cycles and most instructions execute in one or two machine cycles Clock definitions The P89LPC9331 9341 9351 9361 device has several internal clocks as defined below OSCCLK Input to the DIVM clock divider OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency see Figure 9 and Section 2 10 CPU Clock CCLK modification DIVM register Note fosc is defined as the OSCCLK frequency CCLK CPU clock output of the DIVM clock divider There are two CCLK cycles per machine cycle and most instructions are executed in one to two machine cycles two or four CCLK cycles RCCLK The internal 7 373 MHz RC oscillator output The clock doubler option when enabled provides an output frequency of 14 746 MHz PCLK Clock for the various peripheral devices and is CCK Oscillator Clock OSCCLK The P89LPC9351 9361 provides several user selectable oscillator options in generating the CPU clock This allows optimization for a range of needs from high precision to lowest possible cost These options are configured when the flash is programmed and include an on chip watchdog oscillator an on chip RC oscillator
62. an oscillator using an external crystal or an external clock source All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 29 of 163 NXP Semiconductors U M1 0308 UM10308 2 3 2 3 1 2 3 2 2 3 3 2 4 2 5 P89LPC9331 9341 9351 9361 user manual Crystal oscillator option The crystal oscillator can be optimized for low medium or high frequency crystals covering a range from 20 kHz to 18 MHz It can be the clock source of OSCCLK and RTC Low speed oscillator option can be the clock source of WDT Low speed oscillator option This option supports an external crystal in the range of 20 kHz to 100 kHz Ceramic resonators are also supported in this configuration Medium speed oscillator option This option supports an external crystal in the range of 100 kHz to 4 MHz Ceramic resonators are also supported in this configuration High speed oscillator option This option supports an external crystal in the range of 4 MHz to 18 MHz Ceramic resonators are also supported in this configuration Clock output The P89LPC9331 9341 9351 9361 supports a user selectable clock output function on the XTAL2 CLKOUT pin when the crystal oscillator is not being used This condition occurs if a different clock source has been selected on chip RC oscillator watchdog oscillator external clock input on X1 and if the Real time
63. and addresses Reset value FMCMD 6 I2ADR 5 DE 2 STA 3 AE EWDRT EE FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 LSB Ol 0 GC 08 CRSEL A8 EXO E8 Hex Binary 00 0000 0000 00 0000 0000 00 0000 0000 70 0111 0000 00 0000 0000 00 0000 0000 00 x000 00x0 00 0000 0000 00 0000 0000 F8 1111 1000 00 0000 0000 S10 onpuooiuleS dXN 966 1966 176 1886997168 80601110 jenuew 1 2102 1snDny 0 sJeuire osip 12e qns jueuinoop siy 94 JO pL 80601 1 pamasa Su 72102 7 74 dXNO Table 3 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 continued Name IEN1 IPO IPOH IP1 IP1H KBCON KBMASK KBPATN P1 P2 P3 POM1 POM2 Description SFR addr Interrupt E8H enable 1 Bit address Interrupt B8H priority 0 Interrupt B7H priority 0 high Bit address Interrupt F8H priority 1 Interrupt F7H priority 1 high Keypad control 94H register Keypad 86H interrupt mask register Keypadpattern 93H register Bit address Port 0 80H Bit address Port 1 90H Bit address Port 2 Bit address Port 3 BOH Port 0 output 84H mode 1 Port 0 output 85H mode 2 Bit functions and addresses Reset value MSB LSB Hex Binary EAD EST ESPI EC EK
64. appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities 21 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP B V NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 156 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual 22 Tables Table 1 Product comparison 3 Table 32 PGAO Control register PGACONO address Table2 Pin description 5 FFCAh bit description P89LPC9351 936
65. bit is logic 1 Note that this bit will not power down the Real time Clock The RTCPD bit PCONA 7 if set will power down and disable this block regardless of RTCEN 1 ERTC Real time Clock interrupt enable The Real time Clock shares the same interrupt as the watchdog timer Note that if the user configuration bit WDTE UCFG1 7 is logic 0 the watchdog timer can be enabled to generate an interrupt Users can read the RTCF RTCCON 7 bit to determine whether the Real time Clock caused the interrupt reserved RTCSO Real time Clock source select see Table 59 6 RTCS1 7 RTCF Real time Clock Flag This bit is set to logic 1 when the 23 bit Real time Clock reaches a count of logic 0 It can be cleared in software 10 Capture Compare Unit CCU P89LPC9351 9361 UM10308 10 1 10 2 This unit features A 16 bit timer with 16 bit reload on overflow Selectable clock CCUCLK with a prescaler to divide the clock source by any integer between 1 and 1024 Four Compare PWM outputs with selectable polarity Symmetrical Asymmetrical PWM selection Seven interrupts with common interrupt vector one Overflow 2xCapture 4xCompare safe 16 bit read write via shadow registers Two Capture inputs with event counter and digital noise rejection filter CCU Clock CCUCLK The CCU runs on the CCUCLK which can be either PCLK in basic timer mode or the output of a PLL see Figure 25 The PLL is designed to use
66. carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 2 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE Compare A direct jne relative 3 2 5 CJNE A d rel Compare immediate jne relative 3 2 B4 CJNE Rn d rel Compare register immediate jne relative 3 2 B8 to BF CJNE Ri d rel Compare indirect immediate relative 2 B6 to B7 DJNZ Rn rel Decrement register jnz relative 2 2 D8 to DF DJNZ dir rel Decrement direct byte jnz relative 3 2 D5 MISCELLANEOUS NOP No operation 1 1 00 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 155 of 163 NXP Semiconductors UM10308 21 Legal information P89LPC9331 9341 9351 9361 user manual 21 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 21 2 Disclaimers Limited warranty and liability
67. clock 95H 00 0000 0000 divide by M control Data pointer 2 bytes Data pointer high 83H 00 0000 0000 Data pointer low 82H 00 0000 0000 Program flash E7H 00 0000 0000 address high Program flash E6H 00 0000 0000 address low Program flash E4H BUSY HVA HVE SV Ol 70 0111 0000 control Read Program flash E4H FMCMD 7 FMCMD 6 FMCMD 5 FMCMD 4 FMCMD 3 FMCMD 2 FMCMD 1 FMCMD 0 control Write Program flash E5H 00 0000 0000 data I2C bus slave DBH 2 6 I2ADR 5 12 08 4 I2ADR 3 I2ADR 2 I2ADR 1 I2ADR 0 GC 00 0000 0000 address register Bit address DF DE DD DC DB DA D9 D8 I2C bus control D8H 2 STA STO Sl AA CRSEL 00 x000 00x0 register 2 data DAH register Serial clock DDH 00 0000 0000 generator SCL duty cycle register high Serial clock DCH 00 0000 0000 generator SCL duty cycle register low I2C bus status D9H STA 4 STA 3 STA 2 STA 1 STA O 0 0 0 F8 1111 1000 register 9 6 1SE6 LVE6 LEE6Dd 168d SOEOLINN dXN jenuew asn 2102 15 0 s jueuinoop siy 91 JO 80601 1 pamasa sjuBu 72102774 dXNO Table 5 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name ICRAL ICRBH ICRBL IENO IEN1
68. frequency of the internal RC oscillator 19 18 User security bytes This device has three security bits associated with each of its 4 8 16 sectors as shown in Table 140 Table 140 Sector Security Bytes SECx bit allocation Bit 7 6 5 4 3 2 1 0 Symbol EDISx SPEDISx MOVCDISx Unprogrammed 0 0 0 0 0 0 0 0 value UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 150 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 141 Sector Security Bytes SECx bit description Bit Symbol Description 0 MOVCDISx Disable Disables the MOVC command for sector x Any MOVC that attempts to read a byte in a MOVC protected sector will return invalid data This bit can only be erased when sector x is erased 1 SPEDISx Sector Program Erase Disable x Disables program or erase of all or part of sector x This bit and sector x are erased by either a sector erase command ISP IAP commercial programmer or a global erase command commercial programmer 2 EDISx Erase Disable ISP Disables the ability to perform an erase of sector x in ISP or IAP mode When programmed this bit and sector x can only be erased by a global erase command using a commercial programmer This bit and sector x CANNOT be erased in ISP or IAP modes 3 7 reserved Table 142 Effects of Security
69. generates an output signal of 32 times the input frequency This signal is used to clock the timer The user will have to set a divider that scales PCLK by a factor of 1 to 16 This divider is found in the SFR register TCR21 The PLL frequency can be expressed as follows PLL frequency PCLK N 1 Where N is the value of PLLDV3 0 Since N ranges in 0 to 15 the CCLK frequency can be in the range of PCLK to PCLK 16 Table 72 CCU control register 1 TCR21 address bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TCOU2 PLLDV 3 PLLDV 2 PLLDV 1 PLLDV O Reset 0 x x x 0 0 0 0 Table 73 CCU control register 1 TCR21 address F9h bit description Bit Symbol Description 0 3 PLLDV 3 0 PLL frequency divider 4 6 Reserved 7 TCOU2 In basic timer mode writing a logic 1 to TCOU 2 will cause the values to be latched immediately and the value of TCOU2 will always read as logic 0 In PWM mode writing a logic 1 to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow As long as the latch is pending TCOU2 will read as logic 1 and will return to logic 0 when the latching takes place TCOU2 also controls the latching of the Output Compare registers OCRAx OCRBx and OCRCx Setting the PLLEN bit in TCR20 starts the PLL When PLLEN is set it will not read back a one until the PLL is in lock At this time the PWM unit is ready to operate and the timer can be enabled The following start
70. in the case of single buffering if the Tx interrupt occurs at the end of a STOP bit a gap may exist before the next start bit 7 DBMOD Double buffering mode When set 1 enables double buffering Must be logic 0 for UART mode 0 In order to be compatible with existing 80C51 devices this bit is reset to logic 0 to disable double buffering 11 10 More about UART Mode 0 In Mode 0 a write to SBUF will initiate a transmission At the end of the transmission SCON 1 is set which must be cleared in software Double buffering must be disabled in this mode Reception is initiated by clearing RI SCON 0 Synchronous serial transfer occurs and RI will be set again at the end of the transfer When RI is cleared the reception of the next character will begin Refer to Figure 31 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 86 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual sidsi stes 516 81 516 stes Ste s side 51651 sies sies 88 write to l SBUF shift l l l l l l l l y transmit RXD data out TxD shittclock J WRITE to SCON clear Ld Lo RI l RXD D1 D2 D3 4 05 D6 7 data TXD shift clock LJ LJ LJ L 0
71. into Power down mode or Idle mode the interrupt occurrence will cause the processor to wake up and resume operation Refer to Section 6 3 Power reduction modes for details Note the external interrupt must be programmed as level triggered to wake up from Power down mode 4 2 External Interrupt pin glitch suppression Most of the P89LPC9331 9341 9351 9361 pins have glitch suppression circuits to reject short glitches please refer to the P89LPC9331 9341 9351 9361 data sheet Dynamic characteristics for glitch filter specifications However pins SDA INTO P1 3 and SCL TO P1 2 do not have the glitch suppression circuits Therefore INT1 has glitch suppression while INTO does not Table 40 Summary of interrupts Description Interrupt flag Vector Interrupt enable Interrupt Arbitration Power bit s address bit s priority ranking down wake up External interrupt 0 IEO 0003h IENO 0 IPOH O IPO 0 1 highest Yes Timer 0 interrupt TFO 000Bh ETO IENO 1 IPOH 1 IPO 1 4 No External interrupt 1 IE1 0013h EX1 IENO 2 2 IP0 2 7 Yes Timer 1 interrupt TF1 001Bh IENO 3 IPOH 3 IPO 3 10 No Serial port Tx and Rx TI and RI 0023h ES ESR IENO 4 IPOH 4 IPO 4 13 No Serial port Rx RI Brownout detect BOIF 002Bh EBO IENO 5 5 IPO 5 2 Yes Watchdog timer Real time WDOVF RTCF 0053h EWDRT IENO 6 1POH 6 IPO 6 3 Yes clock interrupt SI 0033h EI2C IEN1 0 IP1H 0 IP1 0 5 No interrupt K
72. is running during power down UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 58 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 47 Power Control register PCON address 87h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO Reset 0 0 0 0 0 0 0 Table 48 Power Control register PCON address 87h bit description Bit Symbol Description 0 PMODO Power Reduction Mode see Section 6 3 PMOD 1 2 GFO General Purpose Flag 0 May be read or written by user software but has no effect on operation 3 GF1 General Purpose Flag 1 May be read or written by user software but has no effect on operation 4 BOI Brownout Detect Interrupt Enable When logic 1 Brownout Detection will generate a interrupt 5 Reserved 6 SMODO Framing Error Location When logic 0 bit 7 of SCON is accessed as SMO for the UART When logic 1 bit 7 of SCON is accessed as the framing error status FE for the UART 7 SMOD1 Double Baud Rate bit for the serial port UART when Timer 1 is used as the baud rate source When logic 1 the Timer 1 overflow rate is supplied to the UART When logic 0 the Timer 1 overflow rate is divided by two before being supplied to the UART See Section 10 Table 49 Power Control register A PCONA address B5h bit allo
73. key DBYTE OxFF force key to be at address OxFF short pgm void OxFF00 set pointer to entry point key 0x96 set the authorization key pgm mtp execute the IAP function call After the function call is processed by the IAP routine the authorization key will be cleared Thus it is necessary for the authorization key to be set prior to EACH call to PGM that requires a key If an IAP routine that requires an authorization key is called without a valid authorization key present the MCU will perform a reset Flash write enable This device has hardware write enable protection This protection applies to both ISP and IAP modes and applies to both the user code memory space and the user configuration bytes UCFG1 UCFG2 BOOTVEC BOOTSTAT This protection does not apply to ICP or parallel programmer modes If the Activate Write Enable AWE bit in BOOTSTAT 7 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 144 of 163 NXP Semiconductors U M1 0308 UM10308 19 15 19 16 P89LPC9331 9341 9351 9361 user manual is a logic 0 an internal Write Enable WE flag is forced set and writes to the flash memory and configuration bytes are enabled If the Active Write Enable AWE bit is a logic 1 then the state of the internal WE flag can be controlled by the user The WE
74. logic 1 RTCF be used as an interrupt source This interrupt vector is shared with the watchdog timer It can also be a source to wake up the device 9 3 1 Real time clock read back Users can read RTCDATH and RTCDATL registers and get the 16 bit counter portion of the RTC 9 4 Reset sources affecting the Real time clock Only power on reset and watchdog reset will reset the Real time Clock and its associated SFRs to their default state Table 59 Real time Clock System Timer clock sources FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 000 0 00 High frequency crystal High frequency crystal DIVM 01 10 11 High frequency crystal DIVM 1 00 High frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator 001 0 00 Medium frequency crystal Medium frequency crystal DIVM 01 10 11 Medium frequency crystal DIVM 1 00 Medium frequency crystal Internal RC oscillator 01 10 11 Internal RC oscillator UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 68 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 59 Real time Clock System Timer clock sources continued FOSC2 0 RCCLK RTCS1 0 RTC clock source CPU clock source 010 0 00 Low frequency crystal Low frequency crystal 01 DIVM 10 11 Low frequency crystal DIV 1 00 Low frequency crystal Internal RC
75. manual Rev 4 1 20 August 2012 89 of 163 NXP Semiconductors UM10308 If P89LPC9331 9341 9351 9361 user manual If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data If DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following there is more data the CPU writes to SBUF again Then If INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter Go to 3 write to SBUF TX interrupt TXD write to SBUF TX interrupt TXD write to SBUF TX interrupt AUU LEE T Fig 34 Transmission with and without double buffering single buffering DBMOD SSTAT 7 0 early interrupt INTLO SSTAT 6 0 is shown i i i 1 1 1 1 1 1 double buffering DBMOD SSTAT 7 1 early interrupt INTLO SSTAT 6
76. mode Timing specifications may be found in the data sheet for this device This has the same effect as having a non zero status bit This allows an application to be built that will normally execute the user code but can be manually forced into ISP operation If the factory default setting for the Boot Vector is changed it will no longer point to the factory pre programmed ISP boot loader code If this happens the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and Boot Status Bit After programming the Flash the status byte should be programmed to zero in order to allow execution of the user s application code beginning at address 0000H RST 002aaa912 Fig 56 Forcing ISP mode In system programming ISP In System Programming is performed without removing the microcontroller from the system The In System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the P89LPC9331 9341 9351 9361 through the serial port This firmware is provided by NXP All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 140 of 163 NXP Semiconductor
77. modes mode 2 and mode 3 the Receive Interrupt will be automatically set when the received byte contains either the Given address or the Broadcast address The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses All of the slaves may be contacted by using the Broadcast address Two special Function Registers are used to define the slave s address SADDR and the address mask SADEN SADEN is used to define which bits in the SADDR are to be used and which bits are don t care The SADEN mask can be logically ANDed with the SADDR to create the Given address which the master will use for addressing each of the slaves Use of the Given address allows multiple slaves to be recognized while excluding others The following examples will help to show the versatility of this scheme Table 90 Slave 0 1 examples Example 1 Example 2 Slave 0 SADDR 11000000 Slave 1 SADDR 1100 0000 SADEN 1111 1101 SADEN 11111110 Given 1100 00X0 Given 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves Slave 0 requires a 0 in bit 0 and it ignores bit 1 Slave 1 requires a 0 in bit 1 and bit 0 is ignored A unique address fo
78. or less A minimum of 0 5 MHz is required to maintain A D accuracy CLK2 0 Divisor 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 Table 27 A D Input select ADINS address A3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol AIN13 AIN12 11 10 AINO2 AINO1 AINOO Reset 0 0 0 0 0 0 0 0 Table 28 A D Input select ADINS address A3h bit description Bit Symbol Description 0 AINOO When set enables the 00 pin for sampling and conversion 1 AINO1 When set enables the 01 pin for sampling and conversion 2 AINO2 When set enables the 02 pin for sampling and conversion 3 When set enables the 03 for sampling and conversion 4 AIN10 When set enables the Anin10 pin for sampling and conversion 5 AIN11 When set enables the Anin11 pin for sampling and conversion 6 AIN12 When set enables the Anin12 pin for sampling and conversion 7 AIN13 When set enables the Anin13 pin for sampling and conversion UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 45 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Table 29 Temperature Sensor control register TPSCON address FFCAh bit allocation P89LPC9331 9341 Bit 7 6 5 4 3 2 1 0 Symbol TSEL1 TSELO Reset 0 0 0 0 0 0
79. oscillator 01 10 11 Internal RC oscillator 011 0 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 100 0 00 High frequency crystal Watchdog oscillator 01 Medium frequency crystal DINM 10 Low frequency crystal 11 Watchdog oscillator DIVM 1 00 High frequency crystal Internal RC oscillator 01 Medium frequency crystal 10 Low frequency crystal 11 Internal RC oscillator 101 undefined undefined 110 X undefined undefined 111 0 00 External clock input External clock input 01 DIVM 10 11 External clock input DIVM 1 00 External clock input Internal RC oscillator 01 10 11 Internal RC oscillator Table 60 Real time Clock Control register RTCCON address 1 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RTCF RTCS1 50 RTCEN Reset 0 1 1 0 0 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 69 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 61 Real time Clock Control register RTCCON address D1h bit description Bit Symbol Description 0 RTCEN Real time Clock enable The Real time Clock will be enabled if this
80. output modes but provides a continuous strong pull up when the port latch contains a logic 1 The push pull mode may be used when more source current is needed from a port output The push pull port configuration is shown in Figure 17 A push pull port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9331 9341 9351 9361 data sheet Dynamic characteristics for glitch filter specifications All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 53 of 163 NXP Semiconductors U M1 0308 UM10308 5 6 5 7 P89LPC9331 9341 9351 9361 user manual VDD strong pin port latch N data input data lt NM glitch rejection 002aaa917 Fig 17 Push pull output Port 0 and Analog Comparator functions The P89LPC9331 9341 9351 9361 incorporates two Analog Comparators In order to give the best analog performance and minimize power consumption pins that are being used for analog functions must have both the digital outputs and digital inputs disabled Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Figure 16 Digital inputs on Port 0 may be disabled through the use of the PTOAD register Bits 1 through 5 in this register correspond to pins 1 through P0 5 of P
81. processed or by software TRO Timer 0 Run control bit Set cleared by software to turn Timer Counter 0 on off 5 Timer 0 overflow Set by hardware Timer Counter overflow Cleared by hardware when the processor vectors to the interrupt routine or by software except in mode 6 where it is cleared in hardware TR1 Timer 1 Run control bit Set cleared by software to turn Timer Counter 1 on off TF1 Timer 1 overflow flag Set by hardware on Timer Counter overflow Cleared by hardware when the interrupt is processed or by software except in mode 6 see above when it is cleared in hardware PCIR C T 0 overflow Tn pi _ interrupt n pin C C T 1 control xs toggle n LX Tn pin Gate INTn pin ENTn 002aaa919 Fig 19 Timer counter 0 or 1 in Mode 0 13 bit counter rfl PCLK C T 0 overflow Th oi interrupt n pin C T 1 control toggle Tn pin Gate INTn pin ENTn 002aaa920 Fig 20 Timer counter 0 or 1 in mode 1 16 bit counter PCLK overflow Th oi o TFn interrupt nein C C T 1 control 8 bits reload toggle Tn pin Gate THn INTn pin 8 bits ENTn 002 921 Fig 21 Timer counter 0 or 1 Mode 2 8 bit auto reload UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserv
82. reserved User manual Rev 4 1 20 August 2012 158 of 163 NXP Semiconductors UM10308 Table 133 IAP error 146 Table 134 IAP function calls 147 Table 135 Flash User Configuration Byte 1 UCFG1 bit AllOCALON eorr 149 Table 136 Flash User Configuration Byte 1 UCFG1 bit descriptlOri eae eee dees 149 Table 137 Oscillator type selection 150 Table 138 Flash User Configuration Byte 2 UCFG2 bit allocation iis e ix RR RE SEES 150 Table 139 Flash User Configuration Byte 2 UCFG2 bit description 150 Table 140 Sector Security Bytes SECx bit allocation 150 Table 141 Sector Security Bytes SECx bit description 151 P89LPC9331 9341 9351 9361 user manual Table 142 Effects of Security Bits 151 Table 143 Boot Vector bit allocation 151 Table 144 Boot Vector BOOTVEC bit description 151 Table 145 Boot Status BOOTSTAT bit allocation 151 Table 146 Boot Status BOOTSTAT bit description 152 Table 147 Instruction set summary 153 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 159 of 163 NXP Semiconductors UM10308 23 Figures P89LPC9331 9341 9351 9361 user manual Fig 1 Fig 2 Fig 3
83. the corresponding interrupt enable bit in the TICR2 register The order of priority is fixed as follows from highest to lowest TOIF2 TICF2A e TICF2B TOCF2A TOCF2B e TOCF2C TOCF2D An interrupt service routine for the CCU can be as follows 1 Read the priority encoded value from the TISE2 register to determine the interrupt source to be handled 2 After the current highest priority event is serviced write a logic 0 to the corresponding interrupt flag bit in the TIFR2 register to clear the flag 3 Read the TISE2 register If the priority encoded interrupt source is 000 all CCU interrupts are serviced and a return from interrupt can occur Otherwise return to step List item 2 for the next interrupt UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 79 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual EA IENO 7 ECCU IEN1 4 TOIE2 TICR2 7 TOIF2 TIFR2 7 TICIE2A TICR2 0 TICF2A TIFR2 0 TICIE2B TICR2 1 TICF2B TIFR2 1 TOCIE2A TICR2 3 TOCF2A TIFR2 3 other TOCIE2B TICR2 4 2 interrupt interrupt to CPU TOCF2B TIFR2 4 sources TOCIE2C TICR2 5 TOCF2C TIFR2 5 TOCIE2D TICR2 6 TOCF2D TIFR2 6 gt 0 PRIORITY ENCO
84. to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 151 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 146 Boot Status BOOTSTAT bit description Bit Symbol 0 BSB 1 4 5 6 CWP 7 Description Boot Status Bit If programmed to logic 1 the P89LPC9331 9341 9351 9361 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset See Section 7 1 Reset vector reserved Activate Write Protection bit When this bit is cleared the internal Write Enable flag is forced to the set state thus writes to the flash memory are always enabled When this bit is set the Write Enable internal flag can be set or cleared using the Set Write Enable SWE or Clear Write Enable CWE commands Configuration Write Protect bit Protects inadvertent writes to the user programmable configuration bytes UCFG1 BOOTVEC and BOOTSTAT If programmed to a logic 1 the writes to these registers are disabled If programmed to a logic 0 writes to these registers are enabled This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command to FMCON followed by writing 96H to FMDATA Disable Clear Configuration Protection command If Programmed to 1 the Clear Configuration Protection CCP command is di
85. to the high byte of the timer If the 16 bit CCU Timer is to be used as an 8 bit timer the user can write FFh for upcounting or for downcounting to TH2 When TL2 is written FFh TH2 for upcounting and 00h for downcounting will be loaded to CCU Timer The user will not need to rewrite TH2 again for an 8 bit timer operation unless there is a change in count direction When reading the timer TL2 must be read first When TL2 is read the contents of the timer high byte are transferred to a shadow register in the same PCLK cycle as the read is performed When 2 is read the contents of the shadow register are read instead If a read from TL2 is followed by another read from TL2 without TH2 being read in between the high byte of the timer will be transferred directly to TH2 Table 62 CCU prescaler control register high byte TPCR2H address CBh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TPCR2H 1 TPCR2H 0 Reset 0 0 Table 63 CCU prescaler control high byte TPCR2H address CBh bit description Bit Symbol Description 0 TPCR2H 0 Prescaler bit 8 1 TPCR2H 1 Prescaler bit 9 Table 64 CCU prescaler control register low byte TPCR2L address CAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TPCR2L 7 TPCR2L 6 TPCR2L 5 TPCR2L 4 TPCR2L3 TPCR2L2 TPCR2L1 TPCR2L 0 Reset 0 0 0 0 0 0 0 0 Table 65 CCU prescaler control register low byte TPCR2L address CAh bi
86. to write to this register 2 Write the fill pattern to the DEEDAT register Note that if the correct values are already written to DEEDAT there is no need to write to this register 3 Write address bits 7 to 0 to DEEADR Note that address bits 3 to 0 are ignored 4 Poll EWERR1 flag If EWERR1 DEECON 2 bit is logic 1 BOD EEPROM occurred Vdd 2 4V and Data EEPROM program is blocked All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 133 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 5 If both the EIEE IEN1 7 bit and the EA IENO 7 bit are logic 1s wait for the Data EEPROM interrupt then read poll the EEIF DEECON 7 bit until it is set to logic 1 If EIEE or EA is logic 0 the interrupt is disabled and only polling is enabled When EEIF is logic 1 the operation is complete and row is filled with the DEEDAT pattern Poll EWERRO flag If EWERRO DEECON 1 bit is logic 1 it means BOD EEPROM occurred Vdd 2 4V during program or erase and the previous operation may not be correct 18 7 Data EEPROM Block Fill The Data EEPROM array can be filled with a predetermined data pattern via polling or interrupt 1 Write to DEECON with ECTL1 ECTLO DEECON 5 4 11 and EWERR1 EWERRO DEECON 2 1 00 Set bit EADR8 1 Write the fill pattern to the DEEDAT register
87. up sequence is recommended 1 Set up the PWM module without starting the timer 2 Calculate the right division factor so that the PLL receives an input clock signal of 500 kHz to 1 MHz Write this value to PLLDV 3 Set PLLEN Wait until the bit reads one 4 Start the timer by writing a value to bits TMOD21 TMOD20 When the timer runs from the PLL the timer operates asynchronously to the rest of the microcontroller Some restrictions apply UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 78 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual The user is discouraged from writing or reading the timer in asynchronous mode The results may be unpredictable Interrupts and flags are asynchronous There will be delay as the event may not actually be recognized until some CCLK cycles later for interrupts and reads 10 11 CCU interrupt structure There are seven independent sources of interrupts in the CCU timer overflow captured input events on Input Capture blocks A B and compare match events on Output Compare blocks A through D One common interrupt vector is used for the CCU service routine and interrupts can occur simultaneously in system usage To resolve this situation a priority encode function of the seven interrupt bits in TIFR2 SFR is implemented after each bit is AND ed with
88. watchdog oscillator X 1 Low speed crystal oscillator WDCLK bit is used to switch between watchdog oscillator and PCLK And XTALWD bit is used to switch between watchdog oscillator PCLK and low speed crystal oscillator After changing clock source switching of the clock source will not immediately take effect As shown in Figure 55 the selection is loaded after a watchdog feed sequence In addition due to clock synchronization logic it can take two old clock cycles before the old clock source is deselected and then an additional two new clock cycles before the new clock source is selected Since the prescaler starts counting immediately after a feed switching clocks can cause some inaccuracy in the prescaler count The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles Note When switching clocks it is important that the old clock source is left enabled for two clock cycles after the feed completes Otherwise the watchdog may become disabled when the old clock source is disabled For example suppose PCLK WCLK 0 is the current clock source After WCLK is set to logic 1 the program should wait at least two PCLK cycles 4 CCLKs after the feed completes before going into Power down mode Otherwise the watchdog could become disabled when CCLK turns off The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first All information provided in this document i
89. writing the result to 3 TRIM 3 this register 4 TRIM 4 5 TRIM 5 6 ENCLK when 1 is output on the XTAL2 pin provided the crystal oscillator is not being used 7 RCCLK when 1 selects the RC Oscillator output as the CPU clock This allows for fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle 2 6 Watchdog oscillator option The watchdog has a separate oscillator which has a frequency of 400 kHz calibrated to 5 at room temperature This oscillator can be used to save power when a high clock frequency is not needed 2 7 External clock input option In this configuration the processor clock is derived from an external source driving the XTAL1 P3 1 The rate may be from 0 Hz up to 18 MHz The XTAL2 P3 0 pin may be used as a standard port pin or a clock output When using an oscillator frequency above 12 Mhz BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 31 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual quartz crystal or ceramic resonator XTAL1 I MCA 1 l XTAL2 002aad364 Note The oscilla
90. 0 0 prog_fail 1 else prog_fail 0 return prog fail In circuit programming ICP In Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system The In Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC9331 9341 9351 9361 through a two wire serial interface NXP has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ICP function uses five pins Vpp Vss P0 5 0 4 and RST Only a small connector needs to be available to interface your application to an external programmer in order to use this feature ISP and IAP capabilities of the P89LPC9331 9341 9351 9361 An In Application Programming IAP interface is provided to allow the end user s application to erase and reprogram the user code memory In addition erasing and reprogramming of user programmable bytes including UCFG1 UCFG2 the Boot Status Bit and the Boot Vector is supported As shipped from the factory the upper 512 bytes of user code space contains a serial In System Programming ISP loader allowing for the device to be programmed in circuit through the serial port This ISP boot loader will in turn call low level routines through the same common entry point that can be used by the end user application
91. 00 0000 CLKLP EBRR SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 00 0000 0000 00 0000 0000 SBRGS BRGEN 0012 00 CE1 CP1 CN1 OE1 CO1 CMF1 0011 00 0000 2 2 2 2 2 CMF2 0001 00 0000 00 0000 0000 00 0000 0000 966 1966 176 1886997168 80601110 dXN 80601 1 jenuew 1 2102 15 oz siy uomeuuojur peAuesei 5 72102 7 74 dXNO 91 JO EL Table 3 Special function registers P89LPC9331 9341 continued indicates SFRs that are bit addressable Name DPL FMADRH FMADRL FMCON FMDATA I2ADR I2CON I2DAT 25 I2SCLL 125 IENO SFR addr Description Data pointer 82H low Program flash E7H address high Program flash E6H address low Program flash control Read Program flash E4H control Write Program flash 5 data 2 slave DBH address register Bit address 2 control D8H register 2 data DAH register Serial clock DDH generator SCL duty cycle register high Serial clock DCH generator SCL duty cycle register low 2 status register Bit address Interrupt A8H enable 0 Bit address Bit functions
92. 02 925 Fig 31 Serial Port Mode 0 double buffering must be disabled 11 11 More about UART Mode 1 Reception is initiated by detecting a 1 to 0 transition on RxD RxD is sampled at a rate 16 times the programmed baud rate When a transition is detected the divide by 16 counter is immediately reset Each bit time is thus divided into 16 counter states At the 7th 8th and 9th counter states the bit detector samples the value of RxD The value accepted is the value that was seen in at least 2 of the 3 samples This is done for noise rejection If the value accepted during the first bit time is not 0 the receive circuits are reset and the receiver goes back to looking for another 1 to 0 transition This provides rejection of false start bits If the start bit proves valid it is shifted into the input shift register and reception of the rest of the frame will proceed The signal to load SBUF and RB8 and to set RI will be generated if and only if the following conditions are met at the time the final shift pulse is generated RI 0 and either SM2 0 or the received stop bit 1 If either of these two conditions is not met the received frame is lost If both conditions are met the stop bit goes into RB8 the 8 data bits go into SBUF and RI is activated UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 87 of 163
93. 0h POM2 0CFh POM1 030h 1 024h pin CALL delayl0us before use ANL CMP1 0FEh SETB EC SETB EA RET Disable digital INPUTS on CIN1A CMPREF Disable digital OUTPUTS on pins that are used for analog functions CIN1A CMPREF Turn on comparator 1 and set up for Positive input CINIA Negative input from CMPREF Output to CMP1 pin enabled comparator needs at least 10 microseconds Clear comparator 1 interrupt flag Enable the comparator interrupt Enable the interrupt system if needed Return to caller The interrupt routine used for the comparator must clear the interrupt flag in this case before returning All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 121 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 15 Keypad interrupt The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern This function can be used for bus address recognition or keypad recognition The user can configure the port via SFRs for different tasks There are three SFRs used for this function The Keypad Interrupt Mask Register KBMASK is used to define which input pins connected to Port 0 are enabled to trigger the interrupt The Keypad
94. 0h FFh accessed via indirect addressing using instructions other than MOVX and MOVC All or part of the Stack may be in this area This area includes the DATA area and the 128 bytes immediately above it All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 28 of 163 NXP Semiconductors U M1 0308 2 Clocks P89LPC9331 9341 9351 9361 user manual SFR Special Function Registers Selected CPU registers and peripheral control and status registers accessible only via direct addressing XDATA External Data or Auxiliary RAM Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR RO or R1 All or part of this space could be implemented on chip The P89LPC9351 9361 has 512 bytes of on chip XDATA memory plus extended SFRs located in XDATA CODE 64 kB of Code memory space accessed as part of program execution and via the MOVC instruction The P89LPC9331 9341 9351 9361 has 4 8 kB 16 kB of on chip Code memory The P89LPC9351 9361 also has 512 bytes of on chip Data EEPROM that is accessed via SFRs see Section Section 18 Data EEPROM P89LPC9351 9361 Table 7 Data RAM arrangement Type Data RAM Size bytes DATA Directly and indirectly addressable memory 128 IDATA Indirectly addressable memory 256 XDATA Auxiliary External Data on chip memory that is
95. 1 46 Table 3 Special function registers P89LPC9331 9341 11 Table 33 PGA1 Control register PGACON 1 address Table 4 Extended special function registers FFE1h bit allocation P89LPC9351 9361 47 89 9 31 934101 18 Table 34 PGA1 Control register PGACON 1 address Table 5 Special function registers P89LPC9351 9361 19 FFEth bit description P89LPC9351 9361 47 Table 6 Extended special function registers Table 35 PGAO Control register B PGACONOB address 891 9351 936111 27 FFCEh bit allocation P89LPC9351 9361 47 Table 7 Data RAM arrangement 29 Table 36 PGAO Control register PGACONOB address Table 8 On chip RC oscillator trim register TRIM FFCEh bit description P89LPC9351 9361 47 address 96h bit allocation 31 Table 37 PGA1 Control register PGACON1B address Table 9 On chip RC oscillator trim register TRIM FFE4h bit allocation P89LPC9351 9361 47 address 96h bit description 31 Table 38 PGA1 Control register B PGACON1B address Table 10 Clock control register CLKCON address FFE4h bit description P89LPC9351 9361 47 FFDEh bit allocation 33 Table 39 Interrupt priority level 48 Table 11 Clock control register CLKCON address Table 40 Summary of interrupts 49 FFDEh bit description 33 Table 41 N
96. 1 UART Break Detect will cause a chip reset and force the device into ISP mode 7 CLKLP Clock Low Power Select When set reduces power consumption in the clock circuits Can be used when the clock frequency is 8 MHz or less After reset this bit is cleared to support up to 12 MHz operation Software reset The SRST bit in AUXR1 gives software the opportunity to reset the processor completely as if an external reset or watchdog reset had occurred If a value is written to AUXR1 that contains a 1 at bit position 3 all SFRs will be initialized and execution will resume at program address 0000 Care should be taken when writing to AUXR1 to avoid accidental software resets Dual Data Pointers The dual Data Pointers DPTR adds to the ways in which the processor can specify the address used with certain instructions The DPS bit in the AUXR1 register selects one of the two Data Pointers The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled Specific instructions affected by the Data Pointer selection are INC DPTR Increments the Data Pointer by 1 JMP A DPTR Jump indirect relative to DPTR value MOV DPTR data16 Load the Data Pointer with a 16 bit constant MOVC A A DPTR Move code byte relative to DPTR to the accumulator MOVX A QDPTR Move accumulator to data memory relative to DPTR MOVX DPTR A Move from data memory relative to DPTR to the accumulator Also an
97. 1 any mode other than total 0 X X Y N power down 1 0 X Y N X 0 Y N 1 1 Y Y 6 2 Power on detection The Power On Detect has a function similar to the Brownout Detect but is designed to work as power initially comes up before the power supply voltage reaches a level where the Brownout Detect can function The POF flag RSTSRC 4 is set to indicate an initial power on condition The POF flag will remain set until cleared by software by writing a logic 0 to the bit BOF RSTSRO 5 will be set when POF is set 6 3 Power reduction modes The P89LPC9331 9341 9351 9361 supports three different power reduction modes as determined by SFR bits PCON 1 0 see Table 46 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 57 of 163 NXP Semiconductors U M1 0308 Table 46 P89LPC9331 9341 9351 9361 user manual Power reduction modes PMOD1 PCON 1 0 0 PMODO PCON 0 0 1 Description Normal mode default no power reduction Idle mode The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated Any enabled interrupt source or reset may terminate Idle mode Power down mode The Power down mode stops the oscillator in order to minimize power consumption The P89LPC9331 9341 9351 9361 exits Power down mode via any reset or certain interrup
98. 1 5 1 1 0 7 1 1 1 15 PWM operation PWM Operation has two main modes asymmetrical and symmetrical These modes of timer operation are selected by writing 10H or 11H to TMOD21 TMOD20 as shown Section 10 3 Basic timer operation In asymmetrical PWM operation the CCU Timer operates in downcounting mode regardless of the setting of TDIR2 In this case TDIR2 will always read 1 In symmetrical mode the timer counts up down alternately and the value of TDIR2 has no effect The main difference from basic timer operation is the operation of the compare module which in PWM mode is used for PWM waveform generation Table 71 shows the behavior of the compare pins in PWM mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 75 of 163 NXP Semiconductors U M1 0308 UM10308 10 7 P89LPC9331 9341 9351 9361 user manual The user will have to configure the output compare pins as outputs in order to enable the PWM output As with basic timer operation when the PWM compare pins are connected to the compare logic their logic state remains unchanged However since the bit FCO is used to hold the halt value only a compare event can change the state of the pin TOR2 compare value timer value 0x0000 non inverted inverted 002 893 Fig 26 Asymmetrical PW
99. 1 user manual Clock cycle 1 SPICLK CPOL 0 LE LE LE LE LPL I SPICLK CPOL 1 LF LE LE LE LE LE LE L I MOSI input DORD 0 MSB V LSB MISO output E DORD 1 LSB MSB SS if SSIG bit 0 002aaa935 1 Not defined Fig 47 SPI slave transfer format with CPHA 1 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 115 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Clock cycle 1 0 MOSI input DORD 0 5 LSB DORD 1 LSB MSB MISO output SS if SSIG bit 0 002 936 1 Not defined Fig 48 SPI master transfer format with 0 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 116 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Clock cycle 1 SPICLK CPOL 0 SPICLK CPOL 1 MOSI input GORD S DORD 1 B SB MISO output SS
100. 2 1 0 Symbol PGAENOFF1 Reset 0 0 0 0 0 0 0 0 Table 38 PGA1 Control register address FFE4h bit description P89LPC9351 9361 Bit Symbol Description 0 PGAENOFF1 PGA offset voltage enable bit When set enable the offset voltage on the PGA 1 7 Reserved UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 47 of 163 NXP Semiconductors U M1 0308 4 Interrupts P89LPC9331 9341 9351 9361 user manual UM10308 4 1 The P89LPC9331 9341 9351 9361 uses a four priority level interrupt structure This allows great flexibility in controlling the handling of the P89LPC9331 9341 9351 9361 s 15 interrupt sources Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IENO or IEN1 The IENO register also contains a global enable bit EA which enables all interrupts Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IPO IPOH IP1 and IP1H An interrupt service routine in progress can be interrupted by a higher priority interrupt but not by another interrupt of the same or lower priority The highest priority interrupt service cannot be interrupted by any other interrupt source If two requests of different priority levels are receiv
101. 2 7 3 2 8 P89LPC9331 9341 9351 9361 user manual Dual start immediately Programming this mode starts a synchronized conversion of both A D converters This start mode is available in all A D operating modes Both A D converters must be in the same operating mode In the autoscan single conversion modes both A D converters must select an identical number of channels Writing a 11 to the ADCSx1 ADCSxO bits in either ADCONXx register will start a simultaneous conversion of both A Ds Both A Ds must be enabled Boundary limits interrupt Each of the A D converters has both a high and low boundary limit register The user may select whether an interrupt is generated when the conversion result is within or equal to the high and low boundary limits or when the conversion result is outside the boundary limits An interrupt will be generated if enabled if the result meets the selected interrupt criteria The boundary limit may be disabled by clearing the boundary limit interrupt enable An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits In this case after the four MSBs have been converted these four bits are compared with the four MSBs of the boundary high and low registers If the four MSBs of the conversion meet the interrupt criteria i e outside the boundary limits an interrupt will be generated if enabled If the four MSBs do not meet the interrupt criteria the boundar
102. 3 independent functions BOD reset BOD interrupt and BOD EEPROM FLASH All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 55 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341 9351 9361 user manual BOD reset will cause a processor reset and it is always on except in total power down mode It could not be disabled in software BOD interrupt will generate an interrupt and could be enabled or disabled in software BOD reset and BOD interrupt each has 4 trip voltage levels BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are used as trip point configuration bits of BOD reset BOICFG1 bit and BOICFGO bit in register BODCFG are used as trip point configuration bits of BOD interrupt BOD reset voltage should be lower than BOD interrupt trip point Table 44 gives BOD trip points configuration In total power down mode PMOD1 PMODO 119 the circuitry for the Brownout Detection is disabled for lowest power consumption When PMOD1 PMODO not equal to 11 BOD reset is always on and BOD interrupt is enabled by setting BOI PCON 4 bit Please refer Table 45 for BOD reset and BOD interrupt configuration BOF bit RSTSRC 5 BOD reset flag is default as 0 and is set when BOD reset is tripped BOIF bit RSTSRC 6 BOD interrupt flag is default as 0 and is set when BOD interrupt is tripped BOD EEPROM FLASH is used for flash
103. 31 9341 9351 9361 user manual MUX 00 01 02 Anin03 ADO3 Vref bg Vsen PGAGO01 PGAGOO MUX 10 11 12 Anin13 PGAG11 PGAG10 PGATRIM1 PGASEL11 PGASEL10 Fig 12 PGA block diagram 002aae098 Register PGACONx and are used for PGA configuration The of PGA can be programmable to 2 4 8 or 16 by configuring PGAGx1 and PGAGx0 bits PGA is enabled by setting ENPGAx bit If ENPGAx is cleared PGA is disabled and bypassed which means the PGA gain value is 1 Four external analog input signals ADx0 ADx3 are selected by configuring PGASELx1 and 0 Temperature sensor the internal reference voltage Vret bg 1 23 V a 10 96 and analog input channel ADOS multiplex the same input channel to PGAO Selecting temperature sensor the internal reference voltage or ADO3 input pin is achieved by configuring TSEL1 and TSELO bits in register PGACONO PGA outputs go into the 4 input multiplexer of A D converter allowing the amplified signal to be converted by the ADC For 1 its outputs also pass to analog comparators PGA calibration PGA calibration is needed when changing to different gain level PGA offset voltage is used to guarantee the linearity of PGA output PGHAENOFFx bit in register is used to enable PGA offset voltage To calibrate PGA PGA input ne
104. 32 In system Programming ISP hex record formats Record type 00 01 02 Command data function Program User Code Memory Page nnaaaa00dd ddcc Where nn number of bytes to program aaaa page address dd dd data bytes cc checksum Example 100000000102030405006070809DC3 Read Version Id 00xxxx01cc Where xxxx required field but value is a don t care cc checksum Example 00000001FF Miscellaneous Write Functions 02xxxx02ssddcc Where xxxx required field but value is a don t care ss subfunction code dd data checksum Subfunction codes 00 UCFG1 012 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 3 0 Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 102 Clear Configuration Protection 182 Security Byte 8 192 Security Byte 9 1A Security Byte 10 1 Security Byte 11 1 Security Byte 12 1D Security Byte 13 1E Security Byte 14 1F Security Byte 15 Example 020000020347B2 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 142 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 132 In system Programming ISP hex record formats continued Record type Command daia fun
105. 361 user manual allocation 96 Table 98 2 Status register I2STAT address D9h bit 96 Table 99 12 clock rates selection 97 Table 100 I C Control register I2CON address D8h 97 Table 101 I C Control register 2 address D8h 99 Table 102 Master Transmitter mode 102 Table 103 Master Receiver mode 103 Table 104 Slave Receiver mode 104 Table 105 Slave Transmitter mode 106 Table 106 SPI Control register SPCTL address E2h bit allocation 108 Table 107 SPI Control register SPCTL address E2h bit description gt eR 109 Table 108 SPI Status register SPSTAT address 1 bit allocation 109 Table 109 SPI Status register SPSTAT address E1h bit description zs me ee 109 Table 110 SPI Data register SPDAT address E3h bit allocation cr RR ERES 110 Table 111 SPI master and slave selection Table 112 Comparator Control register CMP1 address ACh 2 address ADh bit allocation 118 Table 113 Comparator Control register CMP1 address ACh 2 address ADh bit description 118 Table 114 Keypad Pattern register KBPATN address 93h bit allocation 122 Table 115 Keypad Pattern register KBPATN addr
106. 51 9361 user manual The factory default settings for this device is shown in Table 131 below The factory pre programmed boot loader can be erased by the user Users who wish to use this loader should take cautions to avoid erasing the last 1 sector on the device Instead the page erase function can be used to erase the eight 64 byte pages located in this sector A custom boot loader can be written with the Boot Vector set to the custom boot loader if desired Table 131 Boot loader address and default Boot vector Product P89LPC9331 P89LPC9341 P89LPC9351 P89LPC9361 Flash size End Signature bytes Sector Pre programmed Default Boot address Mfg id Id 1 1 2 size size serial loader vector 4kBx8 OFFFh 15h DDh 37h 1kBx8 64 8 OEOO0htoOFFFh OFh 8 kB x 8 1FFFh 15h DDh 38h 1kBx8 64 8 1EO00hto 1FFFh 1Fh 8kBx8 1FFFh 15h DDh 2Eh 1 8 64 8 1EO00hto 1FFFh 1Fh 16 8 SFFFh 15h 39h 1kBx8 64 8 3E00h to 3FFFh 3Fh UM10308 19 9 Hardware activation of Boot Loader 19 10 The boot loader can also be executed by forcing the device into ISP mode during a power on sequence see Figure 56 This is accomplished by powering up the device with the reset pin initially held low and holding the pin low for a fixed time after Vpp rises to its normal operating value This is followed by three and only three properly timed low going pulses Fewer or more than three pulses will result in the device not entering ISP
107. 5h bit description continued Bit Symbol Description 4 ADPD A D Converter Power down When 1 turns off the clock to the ADC To fully power down the ADC the user should also set the ENADC1 and ENADCO bits in registers ADCON1 and ADCONO 5 VCPD Analog Voltage Comparators power down When logic 1 the voltage comparators are powered down User must disable the voltage comparators prior to setting this bit 6 DEEPD Data EEPROM power down When logic 1 the Data EEPROM is powered down Note that in either Power down mode or Total Power down mode the Data EEPROM will be powered down regardless of this bit P89LPC9351 9361 7 RTCPD Real time Clock power down When logic 1 the internal clock to the Real time Clock is disabled T Reset The P1 5 RST pin can function as either an active low reset input or as a digital input P1 5 The RPE Reset Pin Enable bit in UCFG1 when set to 1 enables the external reset input function on P1 5 When cleared P1 5 may be used as an input pin Remark During a power on sequence The RPE selection is overridden and this pin will always functions as a reset input An external circuit connected to this pin should not hold this pin low during a Power on sequence as this will keep the device in reset After power on this input will function either as an external reset input or as a digital input as defined by the RPE bit Only a power on reset will temporarily override the selection defined
108. 6 0 2 5 POM2 4 POM2 3 POM2 2 POM2 1 2 0 0001 0000 0000 P1M1 7 1 1 6 P1M1 4 1 1 3 1 1 2 P1M1 1 1 1 0 0301 11x1 xx11 P1M2 7 1 2 6 P1M2 4 P1M2 3 P1M2 2 P1M2 1 1 2 0 0001 00x0 xx00 P2M1 7 P2M1 6 P2M1 5 P2M1 4 P2M1 3 P2M1 2 P2M1 1 2 1 0 FFE 11111111 P2M2 7 2 2 6 P2M2 5 P2M2 4 P2M2 3 P2M2 2 P2M2 1 P2M2 0 00 11 0000 0000 9 6 1SE6 LVE6 LEE6Dd 168d SOEOLINN dXN jenuew asn 2102 1snBny 02 12e qns siy 91 JO vC 80601 1 peAuesei Su 72102 7 74 dXNO Table 5 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name P3M1 P3M2 PCON PCONA PSW PTOAD RSTSRC RTCCON RTCH RTCL SADDR SADEN SBUF SCON SSTAT SP SPCTL Description SFR addr Port 3 output B1H mode 1 Port 3 output B2H mode 2 Power control 87H register Power control B5H register A Bit address Program status DOH word Port O digitalinput disable Reset source DFH register RTC control D1H RTC register high D2H RTC register low D3H Serial port 9 address register Serial port B9H address enable Serial Port data 99H buffer register Bit address Serial port control 98H Serial port BAH extended st
109. 6X PGAO trim FFCDH 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIMO 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIMO 4 register PGAOTRIM2X4X trim FFCCH 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIMO 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIMO 4 register RTCDATH Real time FFBFH 00 0000 0000 clock data register high RTCDATL Real time FFBEH 00 0000 0000 clock data register low 1 Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The MOVX A DPTR and MOVX instructions are used to access these extended SFRs 2 BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 when power on reset 3 CLKCON register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 4 On power on reset and watchdog reset the PGAxTRIM8X16X and PGAxTRIM2XAX registers are initialized with a factory preprogrammed value Other resets will not cause initialization 9 6 16 6 H 6 L 60d 168d 80 0LIAfi dXN NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 1 6 Memory organization FFOOh FFEFh 3FFFh 3E00h 3C00h 3BFFh 3800h 37FFh 3400h 33FFh 3000h 2FFFh 2C00h 2BFFh 2800h 27FFh 2400h 23FFh 2000h 1FFFh 1C00h 1BFFh 1800h 17FFh 1400h 18FFh 1000h OFFFh 0 00 OBFFh 0800h O7FFh
110. 7h R4 address MSB R5 address LSB Return parameter s R7 data 19 17 User configuration bytes A number of user configurable features of the P89LPC9331 9341 9351 9361 must be defined at power up and therefore cannot be set by the program after start of execution These features are configured through the use of an Flash byte UCFG1 and UCFG2 shown in Table 136 and Table 139 Table 135 Flash User Configuration Byte 1 UCFG1 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol WDTE RPE BOE1 WDSE BOEO FOSC2 FOSC1 FOSCO Unprogrammed 0 1 1 0 0 0 1 1 value Table 136 Flash User Configuration Byte 1 UCFG1 bit description Bit Symbol Description 0 FOSCO CPU oscillator type select See Section 2 Clocks for additional information Combinations other than those 1 FOSC1 shown in Table 137 are reserved for future use and should not be used 2 FOSC2 3 BOEO Brownout Detect Configuration see Section 6 1 Brownout detection UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 149 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 136 Flash User Configuration Byte 1 UCFG1 bit description continued Bit Symbol Description 4 WDSE Watchdog Safety Enable bit Refer to Table 120 Watchdog timer configuration for details 5 BOE1 Brownout Detect Configuration
111. ACK received will be returned 68H Arbitration lostin No I2DAT action x 0 0 0 Data byte will be received and NOT SLA R Was or ACK will be returned master Own I2DAT action x 0 0 1 Data byte will be received and ACK SLA W has been will be returned received ACK returned 70H General call l2DAT action x 0 0 0 Data byte will be received and NOT address 00H has or ACK will be returned been received no I2DAT action x 0 0 1 Data byte will be received and ACK ACK has been will be returned returned 78H Arbitration lostin 2 action x 0 0 0 Data byte will be received and NOT SLA R W as or ACK will be returned master General I2DAT action 0 0 1 Data byte will be received and ACK call address has will be returned been received ACK bit has been returned 80H Previously Read data byte or x 0 0 0 Data byte will be received and NOT addressed with ACK will be returned own SLA address read data byte x 0 0 1 Data byte will be received ACK bit Data has been will be returned received ACK has been returned UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 104 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Table 104 Slave Receiver mode continued Status code Status of the 2 Application software response Next action taken by 2
112. ADxDAT2 First channel second conversion result ADxDAT3 Second channel second conversion result All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 40 of 163 NXP Semiconductors U M1 0308 UM10308 3 2 3 6 3 2 3 7 3 2 4 3 2 4 1 3 2 4 2 3 2 4 3 P89LPC9331 9341 9351 9361 user manual Single step mode This special mode allows single stepping in an auto scan conversion mode Any combination of the four input channels can be selected for conversion After each channel is converted an interrupt is generated if enabled and the A D waits for the next start condition The result of each channel is placed in the result register which corresponds to the selected input channel See Table 15 May be used with any of the start modes This mode is selected by clearing the BURSTx SCCx and SCANXx bits in the ADMODA register which correspond to the ADC in use Conversion mode selection bits Each A D uses three bits in ADMODA to select the conversion mode for that A D These mode bits are summarized in Table 18 below Combinations of the three bits other than the combinations shown are undefined Table 18 Conversion mode bits Burst SCC1 5 ADC1conversion 0 SCCO 5 0 ADCO conversion mode mode 0 0 0 Single step 0 0 0 Single step 0 0 1 Fixed channel 0 0 1 Fixed channel single single
113. ALT Setting the HLTEN bit in TCR20 enables the PWM Halt Function When halt function is enabled a capture event as enabled for the Input Capture A pin will immediately stop all activity on the PWM pins and set them to a predetermined state defined by FCOx bit In PWM Mode the FCOx bits in the CCCRx register hold the value the pin is forced to during halt The value of the setting can be read back The capture function and the interrupt will All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 77 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual still operate as normal even if it has this added functionality enabled When the PWM unit is halted the timer will still run as normal The HLTRN bit in TCR20 will be set to indicate that a halt took place In order to re activate the PWM the user must clear the HLTRN bit The user can force the PWM unit into halt by writing a logic 1 to HLTRN bit 10 10 PLL operation The PWM module features a Phase Locked Loop that can be used to generate a CCUCLK frequency between 16 MHz and 32 2 At this frequency the PWM module provides ultrasonic PWM frequency with 10 bit resolution provided that the crystal frequency is 1 MHz or higher The PWM resolution is programmable up to 16 bits by writing to TOR2H TOR2L The PLL is fed an input signal of 0 5 MHz to 1 MHz and
114. AO on P89LPC9351 9361 Block diagram CONFIGURABLE OSCILLATOR 2 3 Fig 6 ON CHIP RC OSCILLATOR WITH CLOCK DOUBLER REAL TIME CLOCK SYSTEM TIMER 2 1 ANALOG COMPARATORS CCU CAPTURE COMPARE UNIT ADC1 DAC1 2 ADCO TEMP SENSOR DACO S POWER MONITOR POWER ON RESET BROWNOUT RESET 002aad555 TXD RXD SCL SDA SPICLK MOSI MISO SS UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 9 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 1 5 Special function registers Remark SFR accesses are restricted in the following ways User must not attempt to access any SFR locations not defined Accesses to any defined SFR locations must be strictly for the functions for the SFRs SFR bits labeled 0 or 1 can only be written and read as follows Unless otherwise specified must be written with 0 but can return any value when read even if it was written with 0 It is a reserved bit and may be used in future derivatives 40 must be written with 0 and will return a 0 when read 1 must be written with 1 and will return a 1 when read UM10308 All information provided in this document is subject to legal disclaimers NXP
115. All rights reserved User manual Rev 4 1 20 August 2012 51 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual The third pull up is referred to as the strong pull up This pull up is used to speed up low to high transitions on a quasi bidirectional port pin when the port latch changes from a logic 0 to a logic 1 When this occurs the strong pull up turns on for two CPU clocks quickly pulling the port pin high The quasi bidirectional port configuration is shown in Figure 14 Although the P89LPC9331 9341 9351 9361 is a 3 V device most of the pins are 5 V tolerant If 5 V is applied to a pin configured in quasi bidirectional mode there will be a current flowing from the pin to Vpp causing extra power consumption Therefore applying 5 V to pins configured in quasi bidirectional mode is discouraged A quasi bidirectional port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9331 9341 9351 9361 data sheet Dynamic characteristics for glitch filter specifications Fig 14 Quasi bidirectional output port latch data Vpp 4 2 CPU CLOCK DELAY trong very weak weak port gt input data glitch rejection 002 914 UM10308 5 3 Open drain output configuration The open drain output configuration turns off all pull ups and only drives the pull down trans
116. BI EI2C 001 00 0 0000 BF BE BD BC BB BA B9 B8 PWDRT PBO PS PSR PT1 PX1 PTO PXO 0011 000 0000 PWDRTH PBOH PSH PT1H PX1H PTOH 0011 000 0000 PSRH FF FE FD FC FB FA F9 F8 PAD PST PSPI PC PKBI 2 001 00 0 0000 PADH PSTH PSPIH PCH PKBIH PI2CH 001 00x0 0000 PATN KBIF 00111 00 _SEL 00 0000 0000 FF 11111111 87 86 85 84 83 82 81 80 1 7 1 2 2 H KB6 KB5 KB4 KB3 KB2 KB1 KBO 97 96 95 94 93 92 91 90 RST INT1 INTO SDA TO SCL RXD TXD A7 A6 A5 A4 A3 A2 A1 0 5 SPICLK 55 5 MOSI 7 B6 B5 B4 B3 B2 B1 BO XTAL1 XTAL2 11 POM1 7 POM1 6 0 1 5 1 4 1 3 1 2 1 1 1 0 FFE 1111 1111 2 7 0 2 6 2 5 POM2 4 0 2 3 2 2 POM2 1 0 2 0 0001 0000 0000 966 1966 176 1886997168 80601 1 dXN jenuew asn 2102 1snBny 0 s siy uomeuuojur 6910561 80601 1 pamasa 5 72102774 dXNO Table 3 indicates SFRs that are bit addressable Special function registers P89LPC9331 9341 continued Name 1 1 1 2 2 1 2 2 1 2 PSW PTOAD RSTSRC RTCCON R
117. BIF 003 1 1 8 Yes Comparators 1 and 2 CMF1 CMF2 0043h EC IEN1 2 IP1H 2 1P1 2 11 Yes interrupts SPI interrupt SPIF 004Bh ESPI IEN1 3 IP1 3 14 Capture Compare Unit 005Bh ECCU IEN1 4 IP1H 4 IP1 4 6 No P89LPC9351 9361 Serial port Tx Tl 006Bh EST IEN1 6 IP1H 6 IP1 6 12 No ADC Data EEPROM write ADCI1 BNDI1 0073h EAD 1 7 IP1H 7 IP1 7 15 lowest No complete P89LPC9351 9361 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 49 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Xo 1 uc EBO k wake up RTCF J KBIF if in power down ERTC EKBI RTCCON 1 7 b WDOVF EWDRT 2 1 EA IEO 7 l ES ESR J EST 2 o D 6 ESP any CCU interrupt ECCU interrupt to CPU EEIF 2 ENADCIO ADCIO ENADCI1 ADCIH BNDIO ENBI1 BNDI1 EADEE 2 3 002aad560 1 See Section 10 2 P89LPC9351 9361 3 P89LPC9331 9341 Fig 13 Interrupt sources interrupt enables and power down wake up sources 5 ports The P89LPC9331 9341 9351 9361 has four I O ports Port 0 Port 1 Port 2 and Port 3 Ports 0 1 and 2 are 8 bit
118. Byte 3 0 Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 18 Security Byte 8 19 Security Byte 9 1A Security Byte 10 1B Security Byte 11 1C Security Byte 12 1D Security Byte 13 1E Security Byte 14 1F Security Byte 15 Return parameter s R7 register data if no error else error status Carry set on error clear on no error Erase Sector Page Input parameters requires key ACC 04h R4 address MSB R5 address LSB R7 OOH erase page or 01H erase sector Return parameter s R7 data Carry set on error clear on no error All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 148 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 134 IAP function calls continued IAP function IAP call parameters Read Sector CRC Input parameters ACC 05h R7 sector address Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read Global CRC Input parameters ACC 06h Return parameter s R4 CRC bits 31 24 R5 CRC bits 23 16 R6 CRC bits 15 8 R7 CRC bits 7 0 if no error R7 error status if error Carry set on error clear on no error Read User Code Input parameters ACC 0
119. CO POP dir Pop direct byte from stack 2 2 DO A Rn Exchange A and register 1 1 C8 to CF XCH Exchange A and direct byte 2 1 C5 XCH A Ri Exchange A and indirect memory 1 1 C6 to C7 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 154 of 163 UM10308 P89LPC9331 9341 9351 9361 user manual NXP Semiconductors Table 147 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code XCHD A Ri Exchange and indirect memory nibble 1 1 D6 to D7 BOOLEAN Mnemonic Description Bytes Cycles Hex code CLRC Clear carry 1 1 C3 CLR bit Clear direct bit 2 1 C2 SETBC Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPLC Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 BO ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carry 2 2 AO MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 BRANCHING ACALL addr 11 Absolute jump to subroutine 2 2 116F 1 LCALL addr 16 Long jump to subroutine 3 2 12 RET Return from subroutine 1 2 22 RETI Return from interrupt 1 2 32 AJMP addr 11 Absolute jump unconditional 2 2 016E1 LJMP addr 16 Long jump unconditional 3 2 02 SJMP rel Short jump relative address 2 2 80 JC rel Jump on
120. Clock and Watchdog Timer are not using the crystal oscillator as their clock source This allows external devices to synchronize to the P89LPC9331 9341 9351 9361 This output is enabled by the ENCLK bit in the TRIM register The frequency of this clock output is that of the CCLK If the clock output is not needed in Idle mode it may be turned off prior to entering Idle saving additional power Note on reset the TRIM SFR is initialized with a factory preprogrammed value Therefore when setting or clearing the ENCLK bit the user should retain the contents of other bits of the TRIM register This can be done by reading the contents of the TRIM register into the ACC for example modifying bit 6 and writing this result back into the TRIM register Alternatively the ANL direct or ORL direct instructions can be used to clear or set bit 6 of the TRIM register On chip RC oscillator option The P89LPC9331 9341 9351 9361 has a 6 bit TRIM register that can be used to tune the frequency of the RC oscillator During reset the TRIM value is initialized to a factory pre programmed value to adjust the oscillator frequency to 7 373 MHz 1 96 at room temperature Note the initial value is better than 1 96 please refer to the P89LPC9331 9341 9351 9361 data sheet for behavior over temperature End user applications can write to the TRIM register to adjust the on chip RC oscillator to other frequencies Increasing the TRIM value will decrease the osci
121. D AD10 gt gt 2 gt gt lt gt AD11 gt KBI2 gt CIN2A gt lt lt gt 10 4 5 AD12 gt a lt INTO SDA DACI AD13 gt PORTO FORET INTI KBI5 gt CMPREF lt RST 6 CMP1 gt OCB id P89LPC9351 TROGO er re CLKOUT XTAL2 P89LPC9361 ICB DACO PORT 3 4 4 OCD 002 XTAL1 gt lt lt gt MOSI 4 lt gt MISO 2 55 4 gt SPICLK 4 4 ICA 002 556 Fig 5 Functional diagram P89LPC9351 9361 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 8 of 163 NXP Semiconductors UM10308 1 4 Block diagram P89LPC9331 9341 9351 9361 user manual P89LPC9331 9341 9351 9361 ACCELERATED 2 CLOCK 80 51 CPU W 4 kB 8 kB 16 kB CODE FLASH internal bus 256 BYTE 3 DATA RAM 512 BYTE AUXILIARY RAM 1 512 BYTE DATA EEPROM 217 0 KEYPAD INTERRUPT WATCHDOG AND OSCILLATOR PROGRAMMABLE CPU OSCILLATOR DIVIDER clock CRYSTAL XTAL1 oR RESONATOR aio P89LPC9351 9361 PGA1 on P89LPC9351 9361 PG
122. DER gt ENCINT 2 002aaa896 Fig 29 Capture compare unit interrupts Table 74 CCU interrupt status encode register TISE2 address DEh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENCINT 2 ENCINT 1 ENCINT O Reset X X X X X 0 0 0 Table 75 CCU interrupt status encode register TISE2 address DEh bit description Bit Symbol Description 2 0 ENCINT 2 0 Interrupt Encode output When multiple interrupts happen more than one interrupt flag is set in CCU Interrupt Flag Register TIFR2 The encoder output can be read to determine which interrupt is to be serviced The user must write a logic 0 to clear the corresponding interrupt flag bit in the TIFR2 register after the corresponding interrupt has been serviced Refer to Table 77 for TIFR2 description 000 No interrupt pending 001 Output Compare Event D interrupt lowest priority 010 Output Compare Event C interrupt 011 Output Compare Event B interrupt 100 Output Compare Event A interrupt 101 Input Capture Event B interrupt 110 Input Capture Event A interrupt 111 CCU Timer Overflow interrupt highest priority 37 Reserved UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 80 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 76 CCU interrupt flag register TIFR2
123. E1 IT1 IEO ITO 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 00 0000 0000 T1GATE 1 1 1 1 0 TOGATE TOC T TOM1 TOMO 00 0000 0000 RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O BIS PRE2 PRE1 PREO WDRUN WDTOF WDCLK 1416 956 1656 1756 1556 4 168 SOEOLINN dXN jenuew asn 2102 1snBny 02 12e qns si siy E91 JO ZL 80 0 pamasa Su 72102 A a dXN Table 3 Special function registers P89LPC9331 9341 continued indicates SFRs that are bit addressable Name Description SFR Bit functions and addresses Reset value addr LSB Hex Binary WDL Watchdog load FF 1111 1111 WFEED1 Watchdog C2H feed 1 WFEED2 Watchdog C3H feed 2 1 2 3 4 5 6 All ports input only high impedance state after power up BRGR1 and BRGRO must only be written if BRGEN in BRGCON SFR is logic 0 If any are written while BRGEN 1 the result is unpredictable The RSTSRC register reflects the cause of the P89LPC9331 9341 reset except BOIF bit Upon a power up reset all reset source flags are cleared except POF and BOF the power on reset value is x011 0000 After reset the value is 1110 01x1 i e PRE2 to PREO are all logic 1 WORUN 1 and WDCLK 1 WDTOF bit is logic 1 after watch
124. FR addresses 83 UART baud rate generation 83 Baud Rate Generator Control register BRGCON address BDh bit allocation 84 Baud Rate Generator Control register BRGCON address BDh bit description 84 Serial Port Control register SCON address 98h bit allocation 85 Serial Port Control register SCON address 98h bit description 85 Serial Port modes 85 Serial Port Status register SSTAT address BAh bit allocation ERAI 85 Serial Port Status register SSTAT address BAh bit description 86 FE and RI when SM2 1 in Modes 2 and 89 Slave 0 1 examples 92 Slave 0 1 2 examples 92 2 data register IBDAT address DAh bit allocation Rura 94 12C slave address register IBADR address DBh bit allocation 94 12C slave address register IBADR address DBh bit 94 2 Control register 2 address D8h bit allocation 95 12C Control register 2 address D8h bit description 95 12 Status register 125 address D9h bit All information provided in this document is subject to legal disclaimers P89LPC9331 9341 9351 9
125. H SADEN Serial Port UART Address Enable B9H SSTAT Serial Port UART Status BAH BRGR1 Baud Rate Generator Rate High Byte BRGRO Baud Rate Generator Rate Low Byte BRGCON Baud Rate Generator Control BDH Baud Rate generator and selection The P89LPC9331 9341 9351 9361 enhanced UART has an independent Baud Rate Generator The baud rate is determined by a value programmed into the BRGR1 and BRGRO SFRs The UART can use either Timer 1 or the baud rate generator output as determined by BRGCON 2 1 see Figure 30 Note that Timer T1 is further divided by 2 if the SMOD 1 bit PCON 7 is set The independent Baud Rate Generator uses CCLK Updating the BRGR1 and BRGRO SFRs The baud rate SFRs BRGR1 and BRGRO must only be loaded when the Baud Rate Generator is disabled the BRGEN bit in the BRGCON register is logic 0 This avoids the loading of an interim value to the baud rate generator CAUTION If either BRGRO or BRGR1 is written when BRGEN 1 the result is unpredictable Table 81 UART baud rate generation SCON 7 SCON 6 PCON 7 BRGCON A Receive transmit baud rate for UART SMO SM1 SMOD1 SBRGS 0 0 X X CCLKy 6 0 1 0 0 CCL 556 TH1 64 1 0 COL o6 TH1 32 X 1 CCLKY BRGR1 BRGRO 16 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 83 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341
126. Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Su
127. LA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free read data byte 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if IPADR O 1 A START condition will be transmitted when the bus becomes free UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 105 of 163 NXP Semiconductors UM10308 Table 104 Slave Receiver mode continued P89LPC9331 9341 9351 9361 user manual Status code Status of the 2 Application software response Next action taken by 2 125 hardware to from I2DAT to 2 hardware STA STO E A STOP condition I2DAT action 0 0 0 0 Switched to not addressed SLA or repeated mode no recognition of own SLA or START condition General call address has beenreceived I2DAT action 0 0 0 1 Switched to not addressed SLA while stil mode Own slave address will be addressed as recognized General call address SLA REC will be recognized if IZADR 0 1 SLA TRX I2DAT action 1 0 0 0 Switched to not addressed SLA mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free no I2DAT action 1 0 0 1 Switched to not ad
128. M downcounting TOR2 compare value timer value 0 non inverted inverted 002 894 Fig 27 Symmetrical PWM The CCU Timer Overflow interrupt flag is set when the counter changes direction at the top For example if TOR contains 01FFH CCU Timer will count 01FEH 01FFH 01FEH The flag is set in the counter cycle after the change from TOR to TOR 1 When the timer changes direction at the bottom in this example it counts 0001H 0000H 0001H The CCU Timer overflow interrupt flag is set in the counter CCUCLK cycle after the transition from 0001H to 0000H The status of the TDIR2 bit in TCR20 reflects the current counting direction Writing to this bit while operating in symmetrical mode has no effect Alternating output mode In asymmetrical mode the user can program PWM channels A B and C D as alternating pairs for bridge drive control By setting ALTAB or ALTCD bits in TCR20 the output of these PWM channels are alternately gated on every counter cycle This is shown in the following figure All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 76 of 163 NXP Semiconductors U M1 0308 UM10308 10 8 10 9 P89LPC9331 9341 9351 9361 user manual TOR2 COMPARE VALUE A or C COMPARE VALUE B or D 4 TIMER VALUE 0 PW
129. M OUTPUT A or P2 6 PWM OUTPUT or D P1 6 002 895 Fig 28 Alternate output mode Table 71 Output compare pin behavior OCMxi OCMx0 Output Compare pin behavior Basic timer mode Asymmetrical PWM Symmetrical PWM 0 0 Output compare disabled On power on this is the default state and pins are configured as inputs 0 1 Set when compare in Non Inverted PWM Set Non Inverted PWM operation Cleared on on compare match Cleared on compare compare 21 Cleared on CCU Timer match upcounting Set underflow on compare match downcounting 1 0 invalid configuration 1 1 Toggles on compare Inverted PWM Cleared Inverted PWM Set on matchl2 on compare match Set compare match on CCU Timer upcounting Cleared on underflow 2 compare match downcounting 2 1 x A B C D 2 ON means in the CCUCLK cycle after the event takes place Synchronized PWM register update When the OCRx registers are written a built in mechanism ensures that the value is not updated in the middle of a PWM pulse This could result in an odd length pulse When the registers are written the values are placed in two shadow registers as is the case in basic timer operation mode Writing to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow If OCRxH and or OCRxL are read before the value is updated the most currently written value is read H
130. OM2 0 PO 1 POM1 1 POM2 1 2 POM1 2 POM2 2 P0 3 POM1 3 POM2 3 P0 4 POM1 4 POM2 4 P0 5 POM1 5 POM2 5 P0 6 POM1 6 POM2 6 7 1 7 2 7 1 0 1 1 0 1 2 0 1 1 1 1 1 P1M2 1 P1 2 1 1 2 1 2 2 P1 3 P1M1 3 P1M2 3 P1 4 P1M1 4 P1M2 4 P1 5 P1M1 5 P1M2 5 P1 6 P1M1 6 P1M2 6 P1 7 P1M1 7 P1M2 7 P2 0 P2M1 0 P2M2 0 P2 1 P2M1 1 P2M2 1 P2 2 P2M1 2 P2M2 2 P2 3 P2M1 3 P2M2 3 P2 4 P2M1 4 P2M2 4 P2 5 P2M1 5 P2M2 5 P2 6 2 1 6 2 2 6 2 7 2 1 7 2 2 7 P3 0 P3M1 0 P3M2 0 P3 1 P3M1 1 2 1 Alternate usage Notes KBIO CMP2 ADO1 KBI1 CIN2B AD10 Refer to Section 5 6 Port 0 and Analog Comparator functions for KBI2 CIN2A AD11 usage as analog inputs KBI3 CIN1B AD12 KBI4 CIN1A AD13 DAC1 5 CMPREF 6 CMP1 KBI7 T1 TXD RXD TO SCL INTO SDA INT1 RST OCB OCC ADOO ICB ADO3 DACO OCD AD02 MOSI MISO SS SPICLK OCA ICA CLKOUT XTAL2 XTAL1 Input only or open drain input only or open drain 6 Power monitoring functions UM10308 6 1 The P89LPC9331 9341 9351 9361 incorporates power monitoring functions designed to prevent incorrect operation during initial power on and power loss or reduction during operation This is accomplished with two hardware functions Power on Detect and Brownout Detect Brownout detection The brownout detect function determines if the power supply voltage drops below a certain level Enhanced BOD has
131. P89LPC9331 9341 9351 9361 are single chip microcontrollers designed for applications demanding high integration low cost solutions over a wide range of performance requirements The P89LPC9331 9341 9351 9361 are based on a high performance processor architecture that executes instructions in two to four clocks six times the rate of standard 80C51 devices Many system level functions have been incorporated into the P89LPC9331 9341 9351 9361 in order to reduce component count board space and system cost Table 1 Product comparison overview Device Flash Sector ADC1 ADCO PGAO PGA1 Temp CCU DATA Memory size Sensor EEPROM P89LPC9331 4 1 kB X X X P89LPC9341 4 1 kB X X X P89LPC9351 8 1 kB X X X X X X X P89LPC9361 16 kB 1kB X X X X X X X 1 1 Pin configuration P2 0 AD03 DACO P2 7 P2 1 AD02 P2 6 P0 0 CMP2 KBIO ADO1 P0 1 CIN2B KBH AD10 P1 7 ADO0 P0 2 CIN2A KBI2 AD1 1 P1 6 P0 3 CIN1B KBI3 AD12 P1 5 RST P0 4 CIN1 A KBI4 DAC1 AD13 Vss P0 5 CMPREF KBI5 P89LPC9331FDH P89LPC9341FDH DD P3 0 XTAL2 CLKOUT P0 6 CMP1 KBI6 P1 4 INT1 P0 7 T1 KBI7 P1 3 INTO SDA P1 0 TXD P1 2 TO SCL P1 1 RXD P2 2 MOSI P2 5 SPICLK P2 3 MISO P2 4 SS 002aae462 Fig 1 P89LPC9331 9341 TSSOP28 pin configuration UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 3 of 163 NXP Semiconductors UM10308
132. Pattern Register KBPATN is used to define a pattern that is compared to the value of Port 0 The Keypad Interrupt Flag KBIF in the Keypad Interrupt Control Register KBCON is set when the condition is matched while the Keypad Interrupt function is active An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA 1 The PATN SEL bit in the Keypad Interrupt Control Register KBCON is used to define equal or not equal for the comparison In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series the user needs to set KBPATN OFFH and PATN SEL 0 not equal then any key connected to PortO which is enabled by KBMASK register is will cause the hardware to set KBIF 1 and generate an interrupt if it has been enabled The interrupt may be used to wake up the CPU from Idle or Power down modes This feature is particularly useful in handheld battery powered systems that need to carefully manage power consumption yet also need to be convenient to use In order to set the flag and cause an interrupt the pattern on Port 0 must be held longer than 6 CCLKs Table 114 Keypad Pattern register KBPATN address 93h bit allocation Bit 7 Symbol KBPATN 7 Reset 1 6 5 4 3 2 1 0 KBPATN 6 5 4 KBPATN 3 2 KBPATN 1 0 1 1 1 1 1 1 1 Table 115 Keypad Pattern register KBPATN address 93h bit description Bit Sy
133. TCH RTCL SADDR SADEN Description SFR addr Port 1 output 91H mode 1 Port 1 output 92H mode 2 Port 2 output A4H mode 1 Port 2 output A5H mode 2 Port 3 output B1H mode 1 Port 3 output B2H mode 2 Power control 87H register Power control B5H register A Bit address Program status DOH word Port 0 digital F6H input disable Reset source DFH register RTC control D1H RTC register D2H high RTC register D3H low Serial port 9 address register Serial port B9H address enable Bit functions and addresses Reset value MSB LSB Hex Binary P1M1 7 1 1 6 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 D3U 11x1 11 P1M2 7 1 2 6 1 2 4 1 2 3 1 22 P1M2 1 1 2 0 0011 00 0 00 P2M1 7 2 1 6 2 1 5 2 1 4 2 1 3 2 1 2 P2M1 1 2 1 0 11111111 P2M2 7 2 2 6 2 2 5 2 2 4 P2M2 3 P2M2 2 P2M2 1 2 2 0 00 0000 0000 2 P3M1 1 1 0 031 11 P3M2 1 2 0 000 xx00 SMOD1 SMODO GF1 GFO PMOD1 PMODO 00 0000 0000 RTCPD VCPD ADPD I2PD SPPD SPD 0011 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV F1 P 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 00 000 BOIF BOF POF R_BK R_WD R_SF R_EX RTCS1 RTCSO RTCEN 6011161 011x 00 0018 0000 0000 00161 0000 0000 00 0000 0000 00 0000 0000
134. Temperature with formula 2 3 2 3 ADC operating modes 3 2 3 1 3 2 3 2 Fixed channel single conversion mode A single input channel can be selected for conversion A single conversion will be performed and the result placed in the result register which corresponds to the selected input channel see Table 15 An interrupt if enabled will be generated after the conversion completes The input channel is selected in the ADINS register This mode is selected by setting the SCANXx bit in the ADMODA register Table 15 Input channels and result registers for fixed channel single auto scan single and auto scan continuous conversion mode Result register Input channel ADODATO 00 ADODAT1 01 ADODAT2 02 ADODATS Anin03 AD1DATO 10 AD1DAT1 Anin11 AD1DAT2 12 AD1DATS 13 Fixed channel continuous conversion mode A single input channel can be selected for continuous conversion The results of the conversions will be sequentially placed in the four result registers see Table 16 interrupt if enabled will be generated after every four conversions Additional conversion All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 39 of 163 NXP Semiconductors U M1 0308 UM10308 3 2 3 3 3 2 3 4 3 2 3 5 P89LPC9331 9341 9351 9361 user manual results will again cycl
135. XP 2012 rights reserved User manual Rev 4 1 20 August 2012 46 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 33 PGA1 Control register PGACON1 address 1 bit allocation P89LPC9351 9361 Bit 7 6 5 4 3 2 1 0 Symbol ENPGA1 PGASEL11 PGASEL10 PGATRIM1 PGAG11 PGAG10 Reset 0 0 0 0 0 0 0 0 Table 34 PGA1 Control register PGACON1 address FFE1h bit description P89LPC9351 9361 Bit Symbol Description 1 0 PGAG11 PGAG10 PGA Gain selection bits 00 Gain 2 01 Gain 4 10 Gain 8 11 Gain 16 3 2 reserved 4 PGATRIM1 1 trim enable bit If set PGA1 is grounded for calibration mode If cleared normal operation mode 6 5 PGASEL11 PGA input channel selection PGASEL10 00 AD10 using PGA 01 AD11 using PGA 10 AD12 using PGA 11 AD13 using PGA 7 1 1 enable If set enable PGA1 If cleared disable 1 Table 35 Control register PGACONOB address FFCEh bit allocation P89LPC9351 9361 Bit 7 6 5 4 3 2 1 0 Symbol PGAENOFFO Reset 0 0 0 0 0 0 0 0 Table 36 Control register PGACONOB address FFCEh bit description P89LPC9351 9361 Bit Symbol Description 0 PGAENOFFO PGA offset voltage enable bit When set enable the offset voltage on the PGA 1 7 Reserved Table 37 PGA1 Control register PGACON1B address FFE4h bit allocation P89LPC9351 9361 Bit 7 6 5 4 3
136. able2 Pin description Symbol Pin Type Description PLCC28 TSSOP28 0 to 7 y o Port 0 Port 0 is 8 bit I O port with a user configurable output type During reset Port 0 latches are configured in the input only mode with the internal pull up disabled The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details The Keypad Interrupt feature operates with Port 0 pins All pins have Schmitt trigger inputs Port 0 also provides various special functions as described below P0 0 CMP2 3 P0 0 Port 0 bit 0 KBIO ADO1 2 Comparator 2 output KBIO Keyboard input 0 AD01 ADCO channel 1 analog input P0 1 CIN2B 26 P0 1 Port 0 bit 1 KBIT AD10 CIN2B Comparator 2 positive input B KBI1 Keyboard input 1 AD10 ADC1 channel 0 analog input P0 2 CIN2A 25 P0 2 Port 0 bit 2 KBI2 AD11 CIN2A Comparator 2 positive input 2 Keyboard input 2 AD11 ADC1 channel 1 analog input P0 3 CIN1B 24 P0 3 Port 0 bit 3 High current source KBIS AD12 CIN1B Comparator 1 positive input KBI3 Keyboard input 3 AD12 ADC1 channel 2 analog input P0 4 CIN1A 23 P0 4 Port 0 bit 4 High current source KBI4 DAC1 AD13 CIN1A Comparator 1 positive input 4 Keyboard inp
137. actory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset sources that affect these SFRs are power on reset and watchdog reset 9 6 16 6 H 6 L 60d 168d SOEOLINN dXN jenuew asn 2102 1snBny 02 12e qns siy uomeuuojur 91 JO 2 80601 1 pamasa Su 72102 7 74 dXN Table 6 Extended special function registers 891 9351 936111 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGO 21 configuration register CLKCON CLOCK FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO 11 1000 xxxx Control register 1 1 control FFE1H ENPGA1 PGASEL1 PGASEL1 PGATRIM PGAG11 PGAG10 00 0000 0000 register 1 0 1 PGACON1B PGA1 control FFE4H PGAENO 00 0000 0000 register B PGA1TRIM8X16X 1 trim FFE3H 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIMO 8XTRIM3 8XTRIM2 8XTRIM1 8XTRIMO 14 register PGA1TRIM2X4X 1 trim FFE2H 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIMO 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIMO 4 register PGACONO PGAOcontrol FFCAH ENPGAO PGASELO PGASELO PGATRIM TSEL1 TSELO PGAGO1 PGAGOO 00 0000 0000 register 1 0 0 PGACONOB PGAO control FFCEH PGAENO 00 0000 0000 register B FFO PGAOTRIM8X1
138. al disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 92 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual reset SADDR and SADEN are loaded with Os This produces a given address of all don t cares as well as a Broadcast address of all don t cares This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature 12 I2C interface The I C bus uses two wires serial clock SCL and serial data SDA to transfer information between devices connected to the bus and has the following features Bidirectional data transfer between masters and slaves Multimaster bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer The I C bus may be used for test and diagnostic purposes A typical 1 C bus configuration is shown in Figure 35 Depending on the state of the direction bit R W two types of data transfers are possible on the I C bus Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data b
139. algorithms When voltage supply is lower than 2 4 V the BOD FLASH is tripped and flash erase program is blocked 19 2 Features Parallel programming with industry standard commercial programmers In Circuit serial Programming ICP with industry standard commercial programmers e AP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 134 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite Default serial loader providing In System Programming ISP via the serial port located in upper end of user program memory Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space providing flexibility to the user Programming and erase over the full operating voltage range Read Programming Erase using ISP IAP or IAP Lite Any flash program operation in 2 ms 4 ms for erase program Programmable security for the code in the Flash for each sector gt 100 000 typical erase program cycles for each byte 10 year minimum data retention 19 3 Flash programm
140. are by writing a logic 0 to the bit Note On Power on reset both BOF and this bit will be set while the other flag bits are cleared 5 BOF BOD Reset Flag When BOD Reset is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit Note On a Power on reset both POF and this bit will be set while the other flag bits are cleared 6 BOIF BOD Interrupt Flag When BOD Interrupt is activated this bit is set It will remain set until cleared by software by writing a logic 0 to the bit Y reserved 7 1 Reset vector Following reset the P89LPC9331 9341 9351 9361 will fetch instructions from either address 0000h or the Boot address The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address 00h The Boot address UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 61 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual will be used if a UART break reset occurs or the non volatile Boot Status bit BOOTSTAT 0 1 or the device has been forced into ISP mode Otherwise instructions will be fetched from address 0000 8 Timers 0 and 1 The P89LPC9331 9341 9351 9361 has two general purpose counter timers which are upward compatible with the 80C51 Timer 0 and Timer 1 Both can be config
141. atus register Stack pointer 81H SPI control E2H register Bit functions and addresses Reset value MSB LSB Hex Binary P3M1 1 1 0 0311 xx11 P3M2 1 2 0 0011 xx00 SMOD1 SMODO BOI GF1 GFO PMOD1 PMODO 00 0000 0000 RTCPD DEEPD VCPD ADPD I2PD SPPD SPD CCUPD O0 0000 0000 D7 D6 D5 D4 D3 D2 D1 DO CY AC FO RS1 RSO OV 1 00 0000 0000 PTOAD 5 PTOAD 4 PTOAD 3 PTOAD 2 PTOAD 1 00 00 000x BOIF BOF POF R BK R WD SF REX RTCF RTCS1 RTCSO ERTC RTCEN 60161 011 00 00 60 0000 0000 0041 0000 0000 00 0000 0000 00 0000 0000 XX XXXX XXXX 9F 9E 9D 9C 9B 9A 99 98 SMO FE SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000 DBMOD INTLO CIDIS DBISEL FE BR OE STINT 00 0000 0000 07 0000 0111 SSIG SPEN DORD MSTR CPOL CPHA SPR1 SPRO 04 0000 0100 9 6 16 6 H 6 L 60d 168d SOEOLINN dXN jenuew asn 2102 1snBny 0 12efqns si jueuinoop siy 91 JO SC 80601 1 pamasa Su 72102 A a dXNO Table 5 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name SPSTAT SPDAT TAMOD TCON TCR20 TCR21 THO TH1 TH2 TICR2 TIFR2 TISE2 TLO TL1 TL2 TMOD TOR2H TOR2L TPCR2H Description SFR Bit functions and addresses R
142. automatic reload as shown in Figure 21 Overflow from TLn not only sets TFn but also reloads TLn with the contents of THn which must be preset by software The reload leaves THn unchanged Mode 2 operation is the same for Timer 0 and Timer 1 8 4 Mode 3 When Timer 1 is in Mode it is stopped The effect is the same as setting TR1 0 Timer 0 in Mode 3 establishes TLO and THO as two separate 8 bit counters The logic for Mode 3 on Timer 0 is shown in Figure 22 TLO uses the Timer 0 control bits TOC T TOGATE TRO INTO and TFO THO is locked into a timer function counting machine cycles and takes over the use of TR1 and TF1 from Timer 1 Thus THO now controls the Timer 1 interrupt Mode 3 is provided for applications that require an extra 8 bit timer With Timer 0 in Mode 3 an P89LPC9331 9341 9351 9361 device can look like it has three Timer Counters Note When Timer 0 is in Mode 3 Timer 1 can be turned on and off by switching it into and out of its own Mode 3 It can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt 8 5 Mode 6 In this mode the corresponding timer can be changed to a PWM with a full period of 256 timer clocks see Figure 23 Its structure is similar to mode 2 except that e TFn n 0 and 1 for Timers 0 and 1 respectively is set and cleared in hardware The low period of the TFn is in THn and should be between 1 and 254 and e The high period o
143. ave Transmitter Mode After the address and the direction bit have been received the SI bit is set and a valid status code can be read from the Status Register I2STAT Refer to Table 105 for the status codes and actions UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 99 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341 9351 9361 user manual logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave A not acknowledge SDA HIGH from Slave to Master S START condition P STOP condition RS repeated START condition 002aaa932 Fig 39 Format of Slave Receiver mode 12 6 4 Slave Transmitter mode The first byte is received and handled as in the Slave Receiver Mode However in this mode the direction bit will indicate that the transfer direction is reversed Serial data is transmitted via P1 3 SDA while the serial clock is input through P1 2 SCL START and STOP conditions are recognized as the beginning and end of a serial transfer In a given application the 2 may operate as a master and as a slave In the slave mode the 2 hardware looks for its own slave address and the general call address If one of these addresses is detected an interrupt is requested When the microcontrollers wishes to become th
144. ble 87 Table 88 Table 89 Table 90 Table 91 Table 92 Table 93 Table 94 Table 95 Table 96 Table 97 UM10308 address bit allocation 72 CCU prescaler control register low byte TPCR2L address bit description 72 CCU control register 0 TCR20 address C8h bit allocatiori exten Bes 73 CCU control register 0 TCR20 address C8h bit description 73 Capture compare control register CCRx address Exh bit allocation 74 Capture compare control register CCRx address Exh bit description 74 Event delay counter for input capture 75 Output compare behavior 77 CCU control register 1 TCR21 address bit allocation i2 eee Beale re Rien 78 CCU control register 1 TCR21 address F9h bit description 78 CCU interrupt status encode register TISE2 address DEh bit allocation 80 CCU interrupt status encode register TISE2 address DEh bit description 80 CCU interrupt flag register TIFR2 address E9h bit allocation 81 CCU interrupt flag register TIFR2 address E9h bit description CCU interrupt control register TICR2 address C9h bit allocation CCU interrupt control register TICR2 address C9h bit description 81 UART S
145. by RPE bit Other sources of reset will not override the RPE bit Note During a power cycle Vpp must fall below Vpog see P89LPC9331 9341 9351 9361 data sheet Static characteristics before power is reapplied in order to ensure a power on reset Reset can be triggered from the following sources e External reset pin during power on or if user configured via UCFG1 Power on detect Brownout detect Watchdog timer e Software reset UART break character detect reset For every reset source there is a flag in the Reset Register RSTSRC The user can read this register to determine the most recent reset source These flag bits can be cleared in software by writing a 0 to the corresponding bit More than one flag bit may be set During a power on reset both POF and BOF are set but the other flag bits are cleared A watchdog reset is similar to a power on reset both POF and BOF are set but the other flag bits are cleared Forany other reset previously set flag bits that have not been cleared will remain set UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 60 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual RPE UCFG1 6 WDTE UCFG1 7 watchdog timer reset n software reset SRST AUXR1 3 gt chip reset power on detect
146. byte 2 1 05 INC Ri Increment indirect memory 1 1 06 to 07 DECA Decrement A 1 1 14 DEC Rn Decrement register 1 1 18 to 1F DEC dir Decrement direct byte 2 1 15 DEC Ri Decrement indirect memory 1 1 16 to 17 INC DPTR Increment data pointer 1 2 A3 MUL AB Multiply A by B 1 4 A4 DIV AB Divide A by B 1 4 84 DAA Decimal Adjust A 1 1 D4 LOGICAL ANL A Rn AND register to A 1 1 58 to 5F ANL A dir AND direct byte to A 2 1 55 ANL A Ri AND indirect memory to A 1 1 56 to 57 ANL A data AND immediate to A 2 1 54 ANL dir A AND A to direct byte 2 1 52 ANL dir data AND immediate to direct byte 3 2 53 ORL A Rn OR register to A 1 1 48 to 4F ORL A dir OR direct byte to A 2 1 45 ORL A Ri OR indirect memory to A 1 1 46 to 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 153 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Table 147 Instruction set summary continued Mnemonic Description Bytes Cycles Hex code A Rn Exclusive OR register to A 1 1 68 to 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to A 1 1 66 to 67 XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62
147. cation Bit 7 6 5 4 3 2 1 0 Symbol RTCPD DEEPD VCPD ADPD 2 SPPD SPD CCUPD Reset 0 0 0 0 0 0 0 0 Table 50 Power Control register A PCONA address B5h bit description Bit Symbol Description 0 CCUPD Compare Capture Unit CCU power down When logic 1 the internal clock to the CCU is disabled Note that in either Power down mode or Total Power down mode the CCU clock will be disabled regardless of this bit Note This bit is overridden by the CCUDIS bit in FCFG1 If CCUDIS 1 CCU is powered down P89LPC9351 9361 1 SPD Serial Port UART power down When logic 1 the internal clock to the UART is disabled Note that in either Power down mode or Total Power down mode the UART clock will be disabled regardless of this bit 2 SPPD SPI power down When logic 1 the internal clock to the SPI is disabled Note that in either Power down mode or Total Power down mode the SPI clock will be disabled regardless of this bit 3 I2PD power down When logic 1 the internal clock to the I2C bus is disabled Note that in either Power down mode or Total Power down mode the 2 clock will be disabled regardless of this bit UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 59 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 50 Power Control register A PCONA address B
148. complete Each read requires three machines after writing the address to the DEEADR register All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 131 of 163 NXP Semiconductors U M1 0308 UM10308 18 1 18 2 P89LPC9331 9341 9351 9361 user manual Row Fill In this mode the addressed row 16 bytes with address DEEADR 3 0 ignored is filled with the DEEDAT pattern To erase the entire row to or program the entire row to FFh write 00h FFh to DEEDAT prior to row fill Each row fill requires approximately 4 ms to complete Block Fill In this mode all 512 bytes are filled with the DEEDAT pattern To erase the block to 00h or program the block to FFh write 00h or FFh to DEEDAT prior to the block fill Prior to using this command EADR8 must be set 1 Each Block Fill requires approximately 4 ms to complete In any mode after the operation finishes the hardware will set EEIF bit An interrupt can be enabled via the IEN1 7 bit If IEN1 7 and the EA bits are set it will generate an interrupt request The EEIF bit will need to be cleared by software Data EEPROM program or erase will be blocked when Vpp 2 4V See Table 128 EWERR 1 bits are used to indicate the write error for BOD EEPROM will be Set when Vpp 2 4V during program or erase operation to indicate the previous operat
149. ction 03 Miscellaneous Read Functions 01xxxx03sscc Where xxxx required field but value is a don t care ss subfunction code cc checksum Subfunction codes 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 reserved 05 reserved 06 reserved 07 reserved 08 Security Byte 0 09 Security Byte 1 OA Security Byte 2 OB Security Byte 0 Security Byte 4 00 Security Byte 5 OE Security Byte 6 OF Security Byte 7 102 Manufacturer 112 Device Id 12 Derivative Id 182 Security Byte 8 19 Security Byte 9 1A Security Byte 10 1 Security Byte 11 1C Security Byte 12 1D Security Byte 13 1E Security Byte 14 1F Security Byte 15 Example 0100000312 04 Erase Sector Page 03 04 Where xxxx required field but value is a don t care aaaa sector page address ss 01 erase sector ss 00 erase page cc checksum Example 03000004010000F8 05 Read Sector CRC 01xxxx05aacc Where xxxx required field but value is a don t care aa sector address high byte cc checksum Example 0100000504F6 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 143 of 163 NXP Semiconductors U M1 0308 UM10308 19 12 19 13 19 14 P89LPC9331 9341 9351 9361 user manual Table 132 In system Programming ISP hex reco
150. ction taken by 2 125 hardware to from I2DAT 1012 hardware STA STO SI COH Data byte in I2DAT action 0 0 0 0 Switched to not addressed SLA I2DAT has been or mode no recognition of own SLA or transmitted General call address NACK has been j2DAT action 0 0 0 1 Switched to not addressed SLA received or mode Own slave address will be recognized General call address will be recognized if IZADR 0 1 nol2DAT action 1 0 0 0 Switched to not addressed SLA or mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free nol2DAT action 1 0 0 1 Switched to not addressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free C8H Last data byte No I2DAT action 0 0 0 0 Switched to not addressed SLA I2DAT has been or mode no recognition of own SLA or transmitted General call address AA 0 ACK I2DAT action 0 0 0 1 Switched to not addressed SLA has been received or mode Own slave address will be recognized General call address will be recognized if IPADR O 1 nol2DAT action 1 0 0 0 Switched to not addressed SLA or no I2DAT action 1 0 0 mode no recognition of own SLA or General call address A START condition will be transmitted when the bus becomes free Switched to not addressed SLA mode Own slave address will be
151. ddress 89h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 1 T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO Reset 0 0 0 0 0 0 0 0 Table 54 Timer Counter Mode register TMOD address 89h bit description Bit Symbol Description TOMO Mode Select for Timer 0 These bits are used with the TOM2 bit in the TAMOD register to determine the 1 TOM1 Timer 0 mode see Table 56 2 Timeror Counter selector for Timer 0 Cleared for Timer operation input from CCLK Set for Counter operation input from TO input pin Gating control for Timer 0 When set Timer Counter is enabled only while the INTO is high and the TRO control pin is set When cleared Timer 0 is enabled when the TRO control bit is set T1MO Mode Select for Timer 1 These bits are used with the 1 2 bit in the TAMOD register to determine the 1 1 Timer 1 mode see Table 56 6 _ Timer or Counter Selector for Timer 1 Cleared for Timer operation input from CCLK Set for Counter operation input from T1 input pin 7 Gating control for Timer 1 When set Timer Counter is enabled only while the INT1 pin is high and the TR1 control pin is set When cleared Timer 1 is enabled when the TR1 control bit is set UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 62 of 163 NXP Semiconductors U M1 0308
152. de if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle interrupt request flag IEn in TCON is set causing an interrupt request Since the external interrupt pins are sampled once each machine cycle an input high or low level should be held for at least one machine cycle to ensure proper sampling If the external interrupt is edge triggered the external source has to hold the request pin high All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 48 of 163 UM10308 P89LPC9331 9341 9351 9361 user manual NXP Semiconductors for at least one machine cycle and then hold it low for at least one machine cycle This is to ensure that the transition is detected and that interrupt request flag IEn is set IEn is automatically cleared by the CPU when the service routine is called If the external interrupt is level triggered the external source must hold the request active until the requested interrupt is generated If the external interrupt is still asserted when the interrupt service routine is completed another interrupt will be generated It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive it simply tracks the input pin level If an external interrupt has been programmed as level triggered and is enabled when the P89LPC9331 9341 9351 9361 is put
153. de of the range defined by the ADC1 boundary registers UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 44 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Table 25 A D Mode register B ADMODB address Ath bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLK2 CLK1 CLKO INBNDO ENDAC1 ENDACO BSA1 BSAO Reset 0 0 0 0 0 0 0 0 Table 26 A D Mode register B ADMODB address Ath bit description Bit Symbol Description 0 BSAO ADCO Boundary Select All When 1 BNDIO will be set if any ADCO input exceeds the boundary limits When 0 BNDIO will be set only if the ADOO input exceeded the boundary limits 1 BSA1 ADC1 Boundary Select All When 1 BNDI1 will be set if ADC1 input exceeds the boundary limits When 0 BNDI1 will be set only if the AD10 input exceeded the boundary limits ENDACO When 1 selects DAC mode for ADCO when 0 selects ADC mode 3 ENDAC1 When 1 selects DAC mode for ADC1 when 0 selects ADC mode 4 INBNDO When set 1 generates an interrupt if the conversion result is inside or equal to the boundary limits When cleared 0 generates an interrupt if the conversion result is outside the boundary limits 7 5 CLK2 CLK1 CLKO Clock divider to produce the ADC clock Divides CCLK by the value indicated below The resulting ADC clock should be 8 MHz
154. dition 002 930 Fig 37 Format of Master Receiver mode After a repeated START condition I C bus may switch to the Master Transmitter Mode logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave A not acknowledge SDA HIGH from Slave to Master S START condition P STOP condition SLA slave address RS repeat START condition 002aaa931 Fig 38 A Master Receiver switches to Master Transmitter after sending Repeated Start 12 6 3 Slave Receiver mode In the Slave Receiver Mode data bytes are received from a master transmitter To initialize the Slave Receiver Mode the user should write the slave address to the Slave Address Register IBADR and the 12 Control Register ICON should be configured as follows Table 101 Control register ICON address D8h Bit 7 6 5 4 3 2 1 0 2 5 5 CRSEL value 1 0 0 0 1 CRSEL is not used for slave mode 2 must be set 1 to enable 2 function AA bit must be set 1 to acknowledge its own slave address or the general call address STA STO and SI are cleared to 0 After IZADR and 2 are initialized the interface waits until it is addressed by its own address or general address followed by the data direction bit which is O W If the direction bit is 1 R it will enter Sl
155. dog reset and is logic 0 after power on reset Other resets will not affect WDTOF On power on reset and watchdog reset the TRIM SFR is initialized with a factory preprogrammed value Other resets will not cause initialization of the TRIM register The only reset sources that affect these SFRs are power on reset and watchdog reset 19 6 1SE6 LVE6 LEE6Dd 168d SOEOLINN dXN jenuew asn 2102 1snBny 05 sJeuire osip jeba 12e qns siy 9130 8L 80601 1 paniesal Su 72102774 dXN Table 4 Extended special function registers PS9LPC9331 9341 1 Name Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary BODCFG BOD FFC8H BOICFG1 BOICFGO 21 configuration register CLKCON CLOCK Control FFDEH CLKOK XTALWD CLKDBL FOSC2 FOSC FOSCO 8 register TPSCON Temperature FFCAH TSEL1 TSELO 00 00000000 sensor control register RTCDATH Real time clock FFBFH 00 0000 0000 data register high RTCDATL Real time clock FFBEH 00 0000 0000 data register low Extended SFRs are physically located on chip but logically located in external data memory address space XDATA The A DPTR and MOVX instructions are used to access these extended SFRs 2 BOICFG1 0 will be copied from UCFG1 5 and UCFG1 3 wh
156. dressed SLA mode Own slave address will be recognized General call address will be recognized if I2ADR 0 1 A START condition will be transmitted when the bus becomes free Table 105 Slave Transmitter mode Status code Status of the 12 Application software response Next action taken by 25 hardware to from I2DAT to I2CON hardware STA STO 81 AA A8h Own SLA R has Load data byte or x 0 0 0 Last data byte will be transmitted been received and ACK bit will be received ACK has been load data byte x 0 0 1 Data byte will be transmitted ACK returned will be received BOh Arbitration lostin Load data byte or x 0 0 0 Last data byte will be transmitted SLA R W as and ACK bit will be received master Own load data byte x 0 0 1 Data byte will be transmitted ACK SLA R has been bit will be received received ACK has been returned B8H Data byte in Load data byte or x 0 0 0 Last data byte will be transmitted I2DAT has been and ACK bit will be received transmitted ACK load data byte x 0 0 1 Data byte will be transmitted ACK has been received will be received UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 106 of 163 UM10308 NXP Semiconductors P89LPC9331 9341 9351 9361 user manual Table 105 Slave Transmitter mode continued Status code Status of the I2C Application software response Next a
157. e During reset Port 2 latches are configured in the input only mode with the internal pull up disabled The operation of Port 2 pins as inputs and outputs depends upon the port configuration selected Each port pin is configured independently Refer to Section 5 1 Port configurations for details All pins have Schmitt trigger inputs Port 2 also provides various special functions as described below P2 0 ICB DACO 1 P2 0 Port 2 bit 0 ADOS ICB Input Capture P89LPC9351 9361 DACO Digital to analog converter output ADO03 ADCO channel analog input UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 6 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 2 Pin description continued Symbol Pin Type Description PLCC28 TSSOP28 P2 1 OCD AD02 2 2 1 Port 2 bit 1 OCD Output Compare D P89LPC9351 9361 02 ADCO channel 2 analog input P2 2 MOSI 13 P2 2 Port 2 bit 2 yo MOSI SPI master out slave in When configured as master this pin is output when configured as slave this pin is input P2 3 MISO 14 y o P2 3 Port 2 bit 3 y o MISO When configured as master this pin is input when configured as slave this pin is output P2 4 SS 15 P2 4 Port 2 bit 4 SS SPI Slave select P2 5
158. e 0 Putting either Timer into Mode 0 makes it look like an 8048 Timer which is an 8 bit Counter with a divide by 32 prescaler Figure 19 shows Mode 0 operation In this mode the Timer register is configured as a 13 bit register As the count rolls over from all 1s to all Os it sets the Timer interrupt flag TFn The count input is enabled to the Timer when TRn 1 and either 0 or INTn 1 Setting TNGATE 1 allows the Timer to be controlled by external input INTn to facilitate pulse width measurements TRn is a control bit in the Special Function Register TCON Table 58 The TnGATE bit is in the TMOD register The 13 bit register consists of all 8 bits of THn and the lower 5 bits of TLn The upper 3 bits of TLn are indeterminate and should be ignored Setting the run flag TRn does not clear the registers Mode 0 operation is the same for Timer 0 and Timer 1 See Figure 19 There are two different GATE bits one for Timer 1 TMOD 7 and one for Timer 0 TMOD 3 8 2 Mode 1 Mode 1 is the same as Mode 0 except that all 16 bits of the timer register THn and are used See Figure 20 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 63 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 8 3 Mode 2 Mode 2 configures the Timer register as an 8 bit Counter TLn with
159. e bus master the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted If bus arbitration is lost in the master mode the 2 switches to the slave mode immediately and can detect its own slave address in the same serial transfer logic 0 write data transferred logic 1 read n Bytes acknowledge A acknowledge SDA LOW from Master to Slave A not acknowledge SDA HIGH from Slave to Master S START condition P STOP condition 002aaa933 Fig 40 Format of Slave Transmitter mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 100 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual ADDRESS REGISTER I2ADR COMPARATOR INPUT FILTER P1 3 SDA OUTPUT SHIFT REGISTER STAGE BIT COUNTER ARBITRATION amp CCLK INPUT SYNC LOGIC TIMING m FILTER AND CONTROL 2 P1 2 SCL LOGIC SERIAL CLOCK OUTPUT GENERATOR interrupt 2 STAGE timer 1 overflow 2 CONTROL REGISTERS amp 25 SCL DUTY CYCLE REGISTERS I2SCLL Biss STATUS Sidtus Dus DECODER I2STAT STATUS REGISTER 002aaa899 N Fig 41 12 serial interface block diagram UM10308 A
160. e description of INTLO bit in SSTAT register in the other modes Must be cleared by software 2 RB8 The 9th data bit that was received in Modes 2 and 3 In Mode 1 SM2 must be 0 RB8 is the stop bit that was received In Mode 0 RB8 is undefined 3 TB8 The 9th data bit that will be transmitted in Modes 2 and 3 Set or clear by software as desired 4 REN Enables serial reception Set by software to enable reception Clear by software to disable reception 5 SM2 Enables the multiprocessor communication feature Modes 2 and 3 In Mode 2 or 3 if SM2 is set to 1 then RI will not be activated if the received 9th data bit RB8 is 0 In Mode 0 SM2 should be 0 In Mode 1 SM2 must be 0 6 SM1 With SMO defines the serial port mode see Table 86 7 65 The use of this bit is determined by SMODO in the PCON register If SMODO 0 this bit is read and written as SMO which with SM1 defines the serial port mode If SMODO 1 this bit is read and written as FE Framing Error FE is set by the receiver when an invalid stop bit is detected Once set this bit cannot be cleared by valid frames but is cleared by software Note UART mode bits SMO and SM1 should be programmed when SMODO is logic 0 default mode on any reset Table 86 Serial Port modes SMO SM1 00 01 10 11 UART mode UART baud rate Mode 0 shift register CCLK 6 default mode on any reset Mode 1 8 bit UART Variable see Table 81 Mode 2 9 bit UART
161. e through the four result registers overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the SCCx bit in the ADMODA register Table 16 Result registers and conversion results for fixed channel continuous conversion mode Result register Contains ADxDATO Selected channel first conversion result ADxDAT 1 Selected channel second conversion result ADxDAT2 Selected channel third conversion result ADxDAT3 Selected channel fourth conversion result Auto scan single conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel See Table 15 An interrupt if enabled will be generated after all selected channels have been converted If only a single channel is selected this is equivalent to single channel single conversion mode This mode is selected by setting the SCANx bit in the ADMODA register Auto scan continuous conversion mode Any combination of the four input channels can be selected for conversion by setting a channel s respective bit in the ADINS register The channels are converted from LSB to MSB order in ADINS A conversion of each select
162. ed User manual Rev 4 1 20 August 2012 65 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual C T 0 PCLK overflow Fonn interrupt pn C C T 1 control 8 bits toggle 07 L TO pin Gate P1 2 open drain INTO pin ENTO AUXR1 4 overflow Osc 2 TE TF1 interrupt control 8 05 toggle Tei T1 pin 0 7 AUXR1 5 002aaa922 Fig 22 Timer counter 0 Mode 3 two 8 bit counters SITO overflow PCLK o on gt interrupt control 8 045 reload THn on falling transition and 256 THn on rising transition toggle Gate INTn pin ENTn 002aaa923 Fig 23 Timer counter 0 or 1 in mode 6 PWM auto reload 8 6 Timer overflow toggle output Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs The same device pins that are used for the TO and T1 count inputs and PWM outputs are also used for the timer toggle outputs This function is enabled by control bits ENTO and the AUXR1 register and apply to Timer 0 and Timer 1 respectively The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on In order for this mode to function the C T bit must be cleared selecting PCLK as the clock source for the timer 9 Real time cl
163. ed input will be performed and the result placed in the result register which corresponds to the selected input channel See Table 15 An interrupt if enabled will be generated after all selected channels have been converted The process will repeat starting with the first selected channel Additional conversion results will again cycle through the result registers of the selected channels overwriting the previous results Continuous conversions continue until terminated by the user This mode is selected by setting the BURSTx bit in the ADMODA register Dual channel continuous conversion mode The any combination of two of the four input channels can be selected for conversion The result of the conversion of the first channel is placed in the first result register The result of the conversion of the second channel is placed in the second result register The first channel is again converted and its result stored in the third result register The second channel is again converted and its result placed in the fourth result register See Table 17 An interrupt is generated if enabled after every set of four conversions two conversions per channel This mode is selected by setting the SCCx bit the ADMODA register Table 17 Result registers and conversion results for dual channel continuous conversion mode Result register Contains ADxDATO First channel first conversion result ADxDAT1 Second channel first conversion result
164. ed simultaneously the request of higher priority level is serviced If requests of the same priority level are pending at the start of an instruction cycle an internal polling sequence determines which request is serviced This is called the arbitration ranking Note that the arbitration ranking is only used for pending requests of the same priority level Table 40 summarizes the interrupt sources flag bits vector addresses enable bits priority bits arbitration ranking and whether each interrupt may wake up the CPU from a Power down mode Interrupt priority structure Table 39 Interrupt priority level Priority bits IPxH Interrupt priority level 0 0 Level 0 lowest priority 0 1 Level 1 1 0 Level 2 1 1 Level 3 There are four SFRs associated with the four interrupt levels IPO IPOH IP1 IP1H Every interrupt has two bits in and IPxH x 0 1 and can therefore be assigned to one of four levels as shown in Table 40 The P89LPC9331 9341 9351 9361 has two external interrupt inputs in addition to the Keypad Interrupt function The two interrupt inputs are identical to those present on the standard 80C51 microcontrollers These external interrupts can be programmed to be level triggered or edge triggered by clearing or setting bit IT1 or ITO in Register TCON If ITn 0 external interrupt n is triggered by a low level detected at the INTn pin If ITn 1 external interrupt n is edge triggered In this mo
165. ed to be grounded and only PGA offset voltage connects into amplifier PGATRIMx bit in register PGACONXx is used as trim enable bit If set PGA input is grounded for calibration mode 4 bit trim value is used to provide the PGA offset voltage in PGA trim registers PGAxTRIM2X4X and PGAxTRIM8X16X Then through A D conversion we can get PGA trim result The trim result from the ADC then needs to be subtracted from each result of the ADC Users need to store the trim result and do the offset subtraction by themselves PGA usage steps All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 37 of 163 NXP Semiconductors U M1 0308 UM10308 3 2 1 2 3 2 2 P89LPC9331 9341 9351 9361 user manual 1 Select PGA gain level and input channel by configuring PGACONXx register Enable PGA by Setting ENPGAx bit Setting PGAENOFFx bit to enable PGA offset voltage Setting PGATRIMx bit to ground PGA input Using ADC to get converting result as PGA offset result and store it Clear PGATRIMx bit to enable input signal Using ADC to get converting result Get amplified ADC result by subtracting PGA offset result from ADC result End users application can write to PGA trim registers to adjust PGA offset voltage Increasing 4 bit trim value will increase the corresponding PGA offset voltage During reset 4 bits
166. en power on reset 3 register reset value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 966 1666 1766 16660964168 SOEOLINN dXN jenuew asn 2102 15 05 jeba siy 9130 6L 80601 1 pamasa Su 72102774 dXNO Table 5 indicates SFRs that are bit addressable Special function registers P89LPC9351 9361 Name ADCONO ADCON1 ADINS ADMODA ADMODB ADOBH ADOBL ADODATO ADODAT1 ADODAT2 ADODATS AD1BH AD1BL AD1DATO AD1DAT1 AD1DAT2 Description SFR addr Bit address Accumulator EOH A D control register 0 A D control 97H register 1 A D input select A3H A D mode COH register A A D mode A1H register B A D_0 boundary BBH high register A D_0 boundary A6H low register A D_0 data C5H register 0 A D_0 data C6H register 1 A D_0 data C7H register 2 A D_0 data F4H register 3 A D_1 boundary C4H high register A D_1 boundary BCH low register A D_1 data D5H register 0 A D_1 data D6H register 1 A D_1 data D7H register 2 Bit functions and addresses Reset value MSB LSB Hex Binary E7 E6 E5 E4 2 E1 EO 00 0000
167. entering the interrupt service routine the user will need to read the flags to determine which comparator caused the interrupt When a comparator is disabled the comparator s output COx goes high If the comparator output was low and then is disabled the resulting transition of the comparator output from a low to high state will set the comparator flag CMFx This will cause an interrupt if the comparator interrupt is enabled The user should therefore disable the comparator interrupt prior to disabling the comparator Additionally the user should clear the comparator flag CMFx after disabling the comparator Comparators and power reduction modes Either or both comparators may remain enabled when Power down mode or Idle mode is activated but both comparators are disabled automatically in Total Power down mode If a comparator interrupt is enabled except in Total Power down mode a change of the comparator output state will generate an interrupt and wake up the processor If the comparator output to a pin is enabled the pin should be configured in the push pull mode in order to obtain fast switching times while in Power down mode The reason is that with the oscillator stopped the temporary strong pull up that normally occurs during switching on a quasi bidirectional port pin does not take place Comparators consume power in Power down mode and Idle mode as well as in the normal operating mode This should be taken into consideration
168. eset value addr MSB LSB Hex Binary SPI status E1H SPIF WCOL 00 00 register SPI data register E3H 00 0000 0000 Timer 0 and 1 8FH T1M2 TOM2 00 0 xxxO auxiliary mode Bit address 8F 8E 8D 8 8 89 88 0 1 88 TF1 TR1 TFO TRO IE1 IT1 IEO ITO 00 0000 0000 control CCU control C8H PLEEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 00 0000 0000 register 0 CCU control F9H TCOU2 PLLDV3 PLLDV 2 PLLDV1 PLLDVO 00 Oxxx 0000 register 1 Timer 0 high 8CH 00 0000 0000 Timer 1 high 8DH 00 0000 0000 CCU timer high CDH 00 0000 0000 CCU interrupt C9H TOIE2 TOCIE2D TOCIE2C TOCIE2B TOCIE2A TICIE2B 2 00 0000 0 00 control register CCUinterruptflag E9H TOIF2 TOCF2D TOCF2C TOCF2B TOCF2A TICF2B TICF2A 00 0000 0x00 register CCU interrupt DEH ENCINT 2 ENCINT 1 0 00 000 status encode register Timer 0 low 8AH 00 0000 0000 Timer 1 low 8BH 00 0000 0000 CCU timer low CCH 00 0000 0000 Timer 0 and 1 89H 1 T1C T T1M1 T1MO TOGATE TOC T TOM1 TOMO 00 0000 0000 mode CCU reload CFH 00 0000 0000 register high CCU reload CEH 00 0000 0000 register low Prescaler control CBH TPCR2H 1 TPCR2H 0 00 00 register high 9 6 1SE6 LVE6 LEE6Dd 168d SOEOLINN dXN jenuew asn 2102 1snBny 05
169. ess 93h bit description 122 Table 116 Keypad Control register KBCON address 94h bit allocation 122 Table 117 Keypad Control register KBCON address 94h bit description 122 Table 118 Keypad Interrupt Mask register KBMASK address 86h bit allocation 123 Table 119 Keypad Interrupt Mask register KBMASK address 86h bit description 123 Table 120 Watchdog timer configuration 124 Table 121 Watchdog Timer Control register WDCON address A7h bit allocation 126 Table 122 Watchdog Timer Control register WDCON address A7h bit description 126 Table 123 Watchdog timeout vales 126 Table 124 Watchdog input clock selection 127 Table 125 AUXR1 register address A2h bit allocation 129 Table 126 AUXR1 register address A2h bit description 130 Table 127 Data EEPROM control register DEECON address F1h bit allocation 131 Table 128 Data EEPROM control register DEECON address F1h bit description 131 Table 129 Flash Memory Control register FMCON address E4h bit allocation Table 130 Flash Memory Control register FMCON address E4h bit description 137 Table 131 Boot loader address and default Boot vector 140 Table 132 In system Programming ISP hex record formats NXP B V 2012 All rights
170. ev 4 1 20 August 2012 117 of 163 NXP Semiconductors UM10308 UM10308 P89LPC9331 9341 9351 9361 user manual The overall connections to both comparators are shown in Figure 50 and Figure 51 There are eight possible configurations for each comparator as determined by the control bits in the corresponding CMPn register CPn CNn and OEn These configurations are shown in Figure 52 When each comparator is first enabled the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds The corresponding comparator interrupt should not be enabled during that time and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service Table 112 Comparator Control register CMP1 address ACh CMP2 address ADh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CEn CPn CNn OEn COn CMFn Reset x X 0 0 0 0 0 0 Table 113 Comparator Control register CMP1 address ACh CMP2 address ADh bit description Bit Symbol Description 0 CMFn Comparator interrupt flag This bit is set by hardware whenever the comparator output COn changes state This bit will cause a hardware interrupt if enabled Cleared by software COn Comparator output synchronized to the CPU clock to allow reading by software 2 OEn Output enable When logic 1 the comparator output is connected to the CMPn pin if the comparator is enabled CEn 1 This outp
171. f the TFn is always 256 THn Loading THn with 00h will force the Tx pin high loading THn with FFh will force the Tx pin low Note that interrupt can still be enabled on the low to high transition of TFn and that TFn can still be cleared in software like in any other modes Table 57 Timer Counter Control register TCON address 88h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol TF1 TR1 TFO TRO IE1 IT1 IEO ITO Reset 0 0 0 0 0 0 0 0 Table 58 Timer Counter Control register TCON address 88h bit description Bit Symbol Description ITO Interrupt O Type control bit Set cleared by software to specify falling edge low level triggered external interrupts 1 IEO Interrupt 0 Edge flag Set by hardware when external interrupt 0 edge is detected Cleared by hardware when the interrupt is processed or by software 2 ITI Interrupt 1 Type control bit Set cleared by software to specify falling edge low level triggered external interrupts UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 64 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 58 Timer Counter Control register TCON address 88h bit description continued Bit Symbol Description 3 Interrupt 1 Edge flag Set by hardware when external interrupt 1 edge is detected Cleared by hardware when the interrupt is
172. flag is SET by writing the Set Write Enable 08H command to FMCON followed by a key value 96H to FMDATA FMCON 0x08 FMDATA 0x96 The WE flag is CLEARED by writing the Clear Write Enable OBH command to followed by a key value 96H to FMDATA or by a reset FMCON 0x08 FMDATA 0x96 The ISP function in this device sets the WE flag prior to calling the IAP routines The IAP function in this device executes a Clear Write Enable command following any write operation If the Write Enable function is active user code which calls IAP routines will need to set the Write Enable flag prior to each IAP write function call Configuration byte protection In addition to the hardware write enable protection described above the configuration bytes may be separately write protected These configuration bytes include UCFG1 UCFG2 and BOOTSTAT This protection applies to both ISP and IAP modes and does not apply to ICP or parallel programmer modes If the Configuration Write Protect bit CWP in BOOTSTAT 6 is a logic 1 writes to the configuration bytes are disabled If the Configuration Write Protect bit CWP is a logic 0 writes to the configuration bytes are enabled The CWP bit is set by programming the BOOTSTAT register This bit is cleared by using the Clear Configuration Protection CCP command in IAP or ISP The Clear Configuration Protection command can be disabled in ISP or IAP mode by programmi
173. ge address MSB R5 page address LSB R7 pointer to data buffer in RAM use IDATA Return parameter s R7 status Carry set on error clear on no error Input parameters 01h Return parameter s R7 IAP version id Misc Write requires Input parameters UM10308 ACC 02h R5 data to write R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 Security Byte 2 OB Security Byte 3 OC Security Byte 4 OD Security Byte 5 OE Security Byte 6 OF Security Byte 7 10 Clear Configuration Protection 18 Security Byte 8 19 Security Byte 9 1A Security Byte 10 1B Security Byte 11 1C Security Byte 12 1D Security Byte 13 1E Security Byte 14 1F Security Byte 15 Return parameter s R7 status Carry set on error clear on no error All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 147 of 163 NXP Semiconductors UM10308 UM10308 P89LPC9331 9341 9351 9361 user manual Table 134 IAP function calls continued IAP function Misc Read IAP call parameters Input parameters ACC 03h R7 register address 00 UCFG1 01 UCFG2 02 Boot Vector 03 Status Byte 04 to 07 reserved 08 Security Byte 0 09 Security Byte 1 Security Byte 2 OB Security
174. hat allow exiting the Idle mode by executing its normal program at a lower rate This can often result in lower power consumption than in Idle mode This can allow bypassing the oscillator start up time in cases where Power down mode would otherwise be used The value of DIVM may be changed by the program at any time without interrupting code execution Low power select The P89LPC9331 9341 9351 9361 is designed to run at 18 MHz CCLK maximum However if CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to a logic 1 to lower the power consumption further On any reset CLKLP is logic 0 allowing highest performance This bit can then be set in software if CCLK is running at 8 MHz or slower 3 A D converter UM10308 3 1 General description The P89LPC9331 9341 9351 9361 have two 8 bit 4 channel multiplexed successive approximation analog to digital converter modules sharing common control logic An on chip temperature sensor is integrated with one of the ADC modules and operates over wide temperature In P89LPC9351 9361 two high speed programmable gain amplifiers PGA are integrated The PGAs provide selectable gains of 2x 4x 8x or 16x A block diagram of the A D converter is shown in Figure 10 and Figure 11 Each A D converter consists of an 4 input multiplexer which feeds a sample and hold circuit providing an input signal to one of two comparator inputs The control logic in combination with the SAR drives a digita
175. he P89LPC9331 9341 9351 9361 will accept up to 64 40H data bytes The AAAA string represents the address of the first byte in the record If there are zero bytes in the record this field is often set to 0000 The RR string indicates the record type A record type of 00 is a data record A record type of 01 indicates the end of file mark In this application additional record types will be added to indicate either commands or data for the ISP facility The maximum number of data bytes in a record is limited to 64 decimal ISP commands are summarized in Table 132 As a record is received by the P89LPC9331 9341 9351 9361 the information in the record is stored internally and a checksum calculation is performed The operation indicated by the record type is not performed until the entire record has been received Should an error occur in the checksum the P89LPC9331 9341 9351 9361 will send an X out the serial port indicating a checksum error If the checksum calculation is found to match the checksum in the record then the command will be executed In most cases successful reception of the record will be indicated by transmitting a character out the serial port All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 141 of 163 NXP Semiconductors UM10308 UM10308 P89LPC9331 9341 9351 9361 user manual Table 1
176. he 16 bit counter portion of the RTC is readable by reading the RTCDATH and RTCDATL registers Reload on underflow TCU 3 bit down counter are RTCDATH RTCDATL Wake up from power down Power on reset XTAL2 XTAL1 LOW FREQ MED FREQ internal oscillators Interrupt if enabled shared with WDT d RTC underflow flag RTC enable select Fig 24 Real time clock system timer block diagram m ga ERTC 002aae091 UM10308 9 1 Real time clock source RTCS1 RTCSO RTCCON 6 5 are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock then the RTC will use CCLK as its clock source All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 67 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 9 2 Changing RTCS1 RTCSO RTCS1 RTCSO cannot be changed if the RTC is currently enabled RTCCON O 1 Setting RTCEN and updating RTCS1 RTCSO may be done in a single write to RTCCON However if RTCEN 1 this bit must first be cleared before updating RTCS1 RTCSO 9 3 Real time clock interrupt wake up If ERTC RTCCON 1 EWDRT IEN1 0 6 and EA IENO 7 are set to
177. he SS pin decides whether the device is master or slave The SS pin can be used as a port pin see Table 111 Table 108 SPI Status register SPSTAT address E1h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SPIF WCOL Reset 0 0 x x x x x x Table 109 SPI Status register SPSTAT address Eth bit description Bit Symbol Description 0 5 reserved 6 WCOL Write Collision Flag WCOL bit is set if the SPI data register SPDAT is written during a data transfer see Section 13 5 Write collision The WCOL flag is cleared in software by writing a logic 1 to this bit 7 5 SPI Transfer Completion Flag When a serial transfer finishes the SPIF bit is set and an interrupt is generated if both the ESPI IEN1 3 bit and the EA bit are set If SS is an input and is driven low when SPI is in master mode and SSIG 0 this bit will also be set see Section 18 4 Mode change on 55 The SPIF flag is cleared in software by writing a logic 1 to this bit All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 109 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 110 SPI Data register SPDAT address E3h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol MSB LSB Reset 0 0 0 0 0 0 0 0 master slave MISO 8 BIT SHIFT REGISTER
178. hen this bit is set the output of PWM channel C and D are alternately gated on every counter cycle PWM Halt Enable When logic 1 a capture event as enabled for Input Capture A pin will immediately stop all activity on the PWM pins and set them to a predetermined state PWM Halt When set indicates a halt took place In order to re activate the PWM the user must clear the HLTRN bit Phase Locked Loop Enable When set to logic 1 starts PLL operation After the PLL is in lock this bit it will read back a one 10 4 Output compare UM10308 The four output compare channels A B C and D are controlled through four 16 bit SFRs OCRAH OCRAL OCRBH OCRBL OCRCH OCRCL OCRDH OCRDL Each output compare channel needs to be enabled in order to operate The channel is enabled by selecting a Compare Output Action by setting the 1 0 bits in the Capture Compare x Control Register CCCRx x A B C D When a compare channel is enabled the user will have to set the associated I O pin to the desired output mode to connect the pin Note The SFR bits for port pins P2 6 P1 6 P1 7 P2 1 must be set to logic 1 in order for the compare channel outputs to be visible at the port pins When the contents of TH2 TL2 match that of OCRxH OCRxL the Timer Output Compare Interrupt Flag TOCFx is set in TIFR2 This happens in the CCUCLK cycle after the compare takes place If EA and the Timer Output Compare Interrupt Enable bit TOCIE2x in TICR2 register
179. ication programming IAP 144 IAP authorization 144 Flash write 144 Configuration byte protection 145 IAP error status 145 User configuration bytes 149 User security bytes 150 Boot Vector 151 Boot status register 151 continued gt gt NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 162 of 163 NXP Semiconductors UM10308 20 Instruction set 153 21 Legal 156 21 1 Definitions ws 156 21 2 156 21 3 156 22 Tables 2 2221222123 157 23 FIQUIOS sauces era ni 160 24 Contents 2 2 161 P89LPC9331 9341 9351 9361 user manual Please be aware that important notices concerning this document and the product s described herein have been included in section 1 information NXP B V 2012 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 20 August 2012 Document identifier UM10308
180. il a compare event or forced compare occurs Table 68 Capture compare control register CCRx address Exh bit allocation Bit Symbol Reset 6 5 4 3 2 1 0 ICECx2 ICEOx1 ICECxO ICESx 1 0 0 0 0 0 0 0 0 Table 69 Capture compare control register CCRx address Exh bit description Bit Symbol Description 0 0 Output Compare x Mode See Table 71 Output compare behavior 1 OCMx1 2 Force Compare X Output Bit When set invoke a force compare 3 ICNFx Input Capture x Noise Filter Enable Bit When logic 1 the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event The inputs are sampled every two CCLK periods regardless of the speed of the timer 4 ICESx Input Capture x Edge Select Bit When logic 0 Negative edge triggers a capture When logic 1 Positive edge triggers a capture 5 ICECx0 Capture Delay Setting Bit 0 See Table 70 for details 6 ICEOx1 Capture Delay Setting Bit 1 See Table 70 for details 7 1 2 Capture Delay Setting Bit 2 See Table 70 for details When the user writes to change the output compare value the values written to OCRH2x and OCRL2x are transferred to two 8 bit shadow registers In order to latch the contents of the shadow registers into the capture compare register the user must write a logic 1 to the CCU Timer Compare Overflow Update bit TCOU2
181. ill be reset STOP condition followed by a START condition will be transmitted STO flag will be reset 2 will be released not addressed slave will be entered A START condition will be transmitted when the bus becomes free Table 103 Master Receiver mode Status code Status of the IC Application software response Next action taken by IC hardware 125 hardware to from I2DAT 1012 STA STO 1 STA 08H A START Load SLA R x 0 0 x SLA R will be transmitted ACK bit condition has will be received been transmitted 10H A repeat START Load SLA R or X 0 0 X As above condition has Load SLA W SLA W will be transmitted I2C bus been transmitted will be switched to Master Transmitter Mode 38H Arbitration lostin I2DAT action 0 0 0 x 2 will be released it will enter NOT ACK bit or a slave mode I2DAT action 1 0 0 START condition will be transmitted when the bus becomes free 40h SLA R has been nol2DAT action 0 0 0 0 Data byte will be received NOT ACK transmitted or bit will be returned has been received 2 action 0 0 1 Databyte will be received ACK bit or will be returned 48h SLA R has been l2DAT action 1 0 0 X Repeated START will be transmitted transmitted NOT or ACK has been nol2DAT action 0 1 0 STOP condition will be transmitted received or STO flag will be reset l2DAT action 1 1 0 X STOP condition followed by a START
182. ing and erase The P89LPC9331 9341 9351 9361 program memory consists 1 kB sectors Each sector can be further divided into 64 byte pages In addition to sector erase and page erase a 64 byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time substantially reducing overall programming time Five methods of programming this device are available Parallel programming with industry standard commercial programmers In Circuit serial Programming ICP with industry standard commercial programmers e IAP Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application Internal fixed boot ROM containing low level In Application Programming IAP routines that can be called from the end application in addition to IAP Lite Afactory provided default serial loader located in upper end of user program memory providing In System Programming ISP via the serial port Note Flash erase program will be blocked if BOD FLASH is detected Vdd 2 4 V 19 4 Using Flash as data storage IAP Lite The Flash code memory array of this device supports IAP Lite in addition to standard IAP functions Any byte in a non secured sector of the code memory array may be read using the instruction and thus is suitable for use as non volatile data storage IAP Lite provides an erase program function that makes it easy for o
183. ion may not be correct EWERR 1 will be Set when a program or erase is requested and Vpp 2 4V Both can be cleared by power on reset watchdog reset or software write Data EEPROM read A byte can be read via polling or interrupt 1 Write to DEECON with ECTL1 ECTLO DEECON 5 4 00 and correct bit 8 address to EADRS Note that if the correct values are already written to DEECON there is no need to write to this register 2 Without writing to the DEEDAT register write address bits 7 to 0 to DEEADR 3 If both the EIEE IEN1 7 bit and the EA IENO 7 bit are logic 1s wait for the Data EEPROM interrupt then read poll the EEIF DEECON 7 bit until it is set to logic 1 If EIEE or EA is logic 0 the interrupt is disabled only polling is enabled 4 Read the Data EEPROM data from the DEEDAT SFR Note that if DEEDAT is written prior to a write to DEEADR if DEECON 5 4 007 a Data EEPROM write operation will commence The user must take caution that such cases do not occur during a read An example is if the Data EEPROM is read in an interrupt service routine with the interrupt occurring in the middle of a Data EEPROM cycle The user should disable interrupts during a Data EEPROM write operation see Section 18 2 Data EEPROM write A byte can be written via polling or interrupt 1 Write to DEECON with ECTL1 ECTLO DEECON 5 4 00 and EWERR1 EWERRO DEECON 2 1 00 and correct bit 8 address to EADRS Note tha
184. is started by setting the CCU Mode Select bits TMOD21 and TMOD20 in the CCU Control Register 0 TCR20 as shown in the table in the TCR20 register description Table 66 The CCU direction control bit TDIR2 determines the direction of the count TDIR2 0 Count up TDIR2 1 Count down If the timer counting direction is changed while the counter is running the count sequence will be reversed in the CCUCLK cycle following the write of TDIR2 The timer can be written or read at any time and newly written values will take effect when the prescaler overflows The timer is accessible through two SFRs TL2 low byte and TH2 high byte A third 16 bit SFR TOR2H TOR2L determines the overflow reload value TL2 TH2 and TOR2H TOR2L will be 0 after a reset Up counting When the timer contents are FFFFH the next CCUCLK cycle will set the counter value to the contents of TOR2H TOR2L Down counting When the timer contents are 0000 the next CCUCLK cycle will set the counter value to the contents of TOR2H TOR2L During the CCUCLK cycle when the reload is performed the CCU Timer Overflow Interrupt Flag TOIF2 in the CCU Interrupt Flag Register TIFR2 will be set and if the EA bit in the IENO register and ECCU bit in the IEN1 register IEN1 4 are set program execution will vector to the overflow interrupt The user has to clear the interrupt flag in software by writing a logic 0 to it When writing to the reload registers TOR2H and TOR2L the val
185. isclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 125 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual tclks 2 255 1 1 1048577 5 Table 123 shows sample P89LPC9331 9341 9351 9361 timeout values Table 121 Watchdog Timer Control register WDCON address A7h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PRE2 PRE1 PREO WDRUN WDTOF WDCLK Reset 1 1 1 x x 1 1 0 1 Table 122 Watchdog Timer Control register WDCON address A7h bit description Bit Symbol Description 0 WDCLK Watchdog input clock select When set the watchdog oscillator is selected When cleared PCLK is selected If the CPU is powered down the watchdog is disabled if WDCLK 0 see Section 16 5 Note If both WDTE and WDSE are set to 1 this bit is forced to 1 Refer to Section 16 3 for details 1 WDTOF Watchdog Timer Time Out Flag This bit is set when the 8 bit down counter underflows In watchdog mode a feed sequence will clear this bit It can also be cleared by writing a logic 0 to this bit in software 2 WDRUN Watchdog Run Control The watchdog timer is started when WDRUN 1 and stopped when WDRUN 0 This bit is forced to 1 watchdog running and cannot be cleared to zero if both WDTE and WDSE are set to 1 3 4 reserved PREO 6 PRE1 Clock Prescaler Tap Select Refer to Table 123 for details 7 PRE2 Table 123 Watchdog timeout vales
186. ister 96 12 SCL duty cycle registers 25 and I2SCLL 96 12 operation modes 97 Master Transmitter 97 Master Receiver 98 Slave Receiver mode 99 Slave Transmitter mode 100 Serial Peripheral Interface SPI 107 Configuring the SPI 111 Additional considerations for a slave 112 Additional considerations for a master 112 Mode change on 55 112 Write 113 Data mode 113 SPI clock prescaler select 117 Analog comparators 117 Comparator configuration 117 Internal reference voltage 119 Comparator input pins 119 All information provided in this document is subject to legal disclaimers 14 4 14 5 14 6 15 16 16 1 16 2 16 3 16 4 16 5 16 6 17 17 1 17 2 18 18 1 18 2 18 3 18 4 18 5 18 6 18 7 19 19 1 19 2 19 3 19 4 19 5 19 6 19 7 19 8 19 9 19 10 19 11 19 12 19 13 19 14 19 15 19 16 19 17 19 18 19 19 19 20 P89LPC9331 9341 9351 9361 user manual Comparator 120 Comparators and power reduction modes 120 Comparators configuration example 121 Keypad interrupt 122 Watchdog timer WDT
187. istor of the port pin when the port latch contains a logic 0 To be used as a logic output a port configured in this manner must have an external pull up typically a resistor tied to Vpp The pull down for this mode is the same as for the quasi bidirectional mode The open drain port configuration is shown in Figure 15 An open drain port pin has a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9331 9341 9351 9361 data sheet Dynamic characteristics for glitch filter specifications All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 52 of 163 NXP Semiconductors U M1 0308 5 4 5 5 UM10308 P89LPC9331 9341 9351 9361 user manual t pin port latch data J gt input data 4 glitch rejection 002aaa915 Fig 15 Open drain output Input only configuration The input port configuration is shown in Figure 16 It is a Schmitt triggered input that also has a glitch suppression circuit Please refer to the P89LPC9331 9341 9351 9361 data sheet Dynamic characteristics for glitch filter specifications input port data lt pin glitch rejection 002aaa916 Fig 16 Input only Push pull output configuration The push pull output configuration has the same pull down structure as both the open drain and the quasi bidirectional
188. itability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or UM10308 All information provided in this document is subject to legal disclaimers malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide
189. l be set FMADRL will auto increment to the next location Auto increment after writing to the last byte in the page register will wrap around to the first byte in the page register but will not affect FMADRL 7 6 Bytes loaded into the page register do not have to be continuous Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA However each location in the page register can only be written once following each LOAD command Attempts to write to a page register location more than once should be avoided FMADRH and FMADRL T7 6 are used to select page of code memory for the erase program function When the erase program command is written to FMCON the locations within the code memory page that correspond to updated locations in the page register will have their contents erased and programmed with the contents of their corresponding locations in the page register Only the bytes that were loaded into the page register will be erased and programmed in the user code array Other bytes within the user code memory will not be affected Writing the erase program command 68H to FMCON will start the erase program process and place the CPU in a program idle state The CPU will remain in this idle state until the erase program cycle is either completed or terminated by an interrupt When the program idle state is exited FMCON will contain status information for the cycle If an inte
190. l to analog converter which provides the other input to the comparator The output of the comparator is fed to the SAR 3 2 A D features Two 8 bit 4 channel multiplexed input successive approximation A D converters Programmable Gain Amplifier PGA with selectable gains of 2x 4x 8x or 16x P89LPC9351 9361 On chip wide range temperature sensor Four result registers for each A D Six operating modes Fixed channel single conversion mode Fixed channel continuous conversion mode Auto scan single conversion mode Auto scan continuous conversion mode Dual channel continuous conversion mode Single step mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 34 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Four conversion start modes Timer triggered start Start immediately Edge triggered Dual start immediately 8 bit conversion time of gt 1 61 us at an A D clock of 8 0 MHz Interrupt or polled operation High and low boundary limits interrupt DAC output to a port pin with high output impedance Clock divider Power down mode input MUX ADOO Anin00 01 02 AD02 SAR Anin03 I ADO03 Vret bg Vsen input MUX 8
191. l2DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset 28h Data byte in Load data byte or 0 0 0 X Data byte will be transmitted I2DAT 1 ACK bit will be received transmitted has been received I2DAT action 1 0 0 X Repeated START will be or transmitted l2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset I2DAT action 1 1 0 STOP condition followed by a START condition will be transmitted STO flag will be reset UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 102 of 163 NXP Semiconductors UM10308 Table 102 Master Transmitter mode continued P89LPC9331 9341 9351 9361 user manual Status of the I2C hardware Status code 125 30h Data byte in I2DAT has been transmitted NOT ACK has been received 38H Arbitration lost in SLA R W or data bytes Application software response Next action taken by IC to from I2DAT Load data byte or I2DAT action or I2DAT action or I2DAT action No I2DAT action or No I2DAT action hardware to I2CON STA STO E 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 Data byte will be transmitted ACK bit will be received Repeated START will be transmitted STOP condition will be transmitted STO flag w
192. ll information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 101 of 163 NXP Semiconductors UM10308 Table 102 Master Transmitter mode P89LPC9331 9341 9351 9361 user manual Status code Status of the Application software response Next action taken by 2 125 hardware to from I2DAT to I2CON hardware STA STO 51 08H A START Load SLA W x 0 0 x SLA W will be transmitted condition has ACK bit will be received been transmitted 10H A repeat START LoadSLA Wor x 0 0 X As above SLA W will be condition has Load SLA R transmitted 2 switches been transmitted to Master Receiver Mode 18h SLA W has been Load data byte or 0 0 0 X Data byte will be transmitted transmitted ACK ACK bit will be received has been received no 2DAT action 1 0 0 x Repeated START will be or transmitted l2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset l2DAT action 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset 20h SLA W has been Load data byte 0 0 0 X Data byte will be transmitted transmitted ACK bit will be received has ng 2 action 1 0 0 Repeated START will be been received or transmitted l2DAT action 0 1 0 x STOP condition will be or transmitted STO flag will be reset
193. llator frequency When the clock doubler option is enabled UCFG2 7 1 the output frequency is doubled If CCLK is 8 MHz or slower the CLKLP SFR bit AUXR1 7 can be set to logic 1 to reduce power consumption On reset CLKLP is logic 0 allowing highest performance access This bit can then be set in software if CCLK is running at 8 MHz or slower When clock doubler option is enabled BOE1 bit UCFG1 5 and BOEO bit UCFG1 3 are required to hold the device in reset at power up until Vpp has reached its specified level All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 30 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 8 On chip RC oscillator trim register TRIM address 96h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol RCCLK ENCLK TRIM 5 TRIM 4 TRIM 3 TRIM 2 TRIM 1 TRIM O Reset 0 0 Bits 5 0 loaded with factory stored value during reset Table 9 On chip RC oscillator trim register TRIM address 96h bit description Bit Symbol Description 0 TRIM O Trim value Determines the frequency of the internal RC oscillator During reset 1 TRIM 1 these bits are loaded with a stored factory calibration value When writing to either bit 6 or bit 7 of this register care should be taken to preserve the current TRIM value 2 TRIM 2 by reading this register modifying bits 6 or 7 as required and
194. llows CLR EA disable interrupt MOV DEEDAT RO write data pattern MOV DEEADR R1 write address for the data SETB EA wait for the interrupt orpoll the DEECON 7 EEIF bit Hardware reset During any hardware reset including watchdog and system timer reset the state machine that remembers a write to the DEEDAT register will be initialized If a write to the DEEDAT register occurs followed by a hardware reset a write to the DEEADR register without a prior write to the DEEDAT register will result in a read cycle Multiple writes to the DEEDAT register If there are multiple writes to the DEEDAT register before a write to the DEEADR register the last data written to the DEEDAT register will be written to the corresponding address Sequences of writes to DEECON and DEEDAT registers A write to the DEEDAT register is considered a valid write i e will trigger the state machine to remember a write operation is to commence if DEECON 5 4 00 If these mode bits are already 00 and address bit 8 is correct there is no need to write to the DEECON register prior to a write to the DEEDAT register Data EEPROM Row Fill A row 16 bytes can be filled with a predetermined data pattern via polling or interrupt 1 Write to DEECON with ECTL1 ECTLO DEECON 5 4 10 and EWERR1 EWERRO DEECON 2 1 00 and correct bit 8 address to EADRS Note that if the correct values are already written to DEECON there is no need
195. ltiprocessor systems is as follows When the master processor wants to transmit a block of data to one of several slaves it first sends out an address byte which identifies the target slave An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte With SM2 1 no slave will be interrupted by a data byte An address byte however will interrupt all slaves so that each slave can examine the received byte and see if it is being addressed The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow The slaves that weren t being addressed leave their SM2 bits set and go on about their business ignoring the subsequent data bytes Note that SM2 has no effect in Mode 0 and must be logic 0 in Mode 1 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 91 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 11 20 Automatic address recognition Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port This feature is enabled by setting the SM2 bit in SCON In the 9 bit UART
196. mbol 0 7 7 0 R W Access Description Pattern bit 0 bit 7 Table 116 Keypad Control register KBCON address 94h bit allocation Bit 7 Symbol Reset x 6 5 4 3 2 1 0 PATN SEL x x x x x 0 0 Table 117 Keypad Control register KBCON address 94h bit description Bit Symbol Access Description 0 KBIF R W Keypad Interrupt Flag Set when Port 0 matches user defined conditions specified in KBPATN KBMASK and PATN_SEL Needs to be cleared by software by writing logic 0 1 PATN SEL R W Pattern Matching Polarity selection When set Port 0 has to be equal to the user defined Pattern in KBPATN to generate the interrupt When clear Port 0 has to be not equal to the value of KBPATN register to generate the interrupt 2 7 reserved UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 122 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 118 Keypad Interrupt Mask register KBMASK address 86h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol KBMASK 7 KBMASK 6 KBMASK 5 KBMASK 4 KBMASK 3 2 KBMASK 1 KBMASK 0 Reset 0 0 0 0 0 0 0 0 Table 119 Keypad Interrupt Mask register KBMASK address 86h bit description Bit Symbol Description 0 KBMASK 0 When set enables 0 0 as a cause of a Keypad Interrupt 1 KBMASK 1 When
197. n be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source and if XTAL1 XTAL2 are not used to generate the clock for the RTC system timer Vss 7 Ground 0 reference Vpp 21 Power supply This is the power supply voltage for normal operation as well as Idle and Power down modes Input output for P1 0 to P1 4 P1 6 P1 7 Input for P1 5 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 7 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 1 3 Functional diagram Vpp Vss ADO1 gt CMP2 lt 4 gt lt gt TXD AD10 CIN2B lt gt AD11 2 gt TO 4 SCL 12 KBI3 gt lt gt INTO lt gt SDA DAC1 4 AD13 gt CINIA PORTO gt lt gt PORTA lt KBI5 gt CMPREF gt lt gt RST KBI6 CMP1 lt lt gt lt gt ADOO KBI Tft gt Pa9LPC9331 57 CLKOUT XTAL2 4 gt P89LPC9341 4 AD03 gt DACO PORT 3 4 AD02 XTAL1 gt lt gt lt gt MOSI 11111117 002 461 Fig 4 Functional diagram P89LPC9331 9341 Vpp Vss ADO1 CMP2 lt lt gt lt gt TX
198. n compare channel is enabled and the contents of TH2 TL2 match that of OCRHA OCRLA the program counter will vectored to the corresponding interrupt 4 TOCIE2B Output Compare Channel B Interrupt Enable Bit If EA bit and this bit are set to 1 when compare channel B is enabled and the contents of TH2 TL2 match that of OCRHB OCRLB the program counter will vectored to the corresponding interrupt UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 81 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 79 CCU interrupt control register TICR2 address C9h bit description continued Bit Symbol 5 2 6 TOCIE2D 7 2 Description Output Compare Channel C Interrupt Enable Bit If EA bit and this bit are set to 1 when compare channel C is enabled and the contents of TH2 TL2 match that of OCRHC OCRLC the program counter will vectored to the corresponding interrupt Output Compare Channel D Interrupt Enable Bit If EA bit and this bit are set to 1 when compare channel D is enabled and the contents of TH2 TL2 match that of OCRHD OCRLD the program counter will vectored to the corresponding interrupt CCU Timer Overflow Interrupt Enable bit 11 UART UM10308 The P89LPC9331 9341 9351 9361 has an enhanced UART that is compatible with the conventional 80C51
199. ne or more bytes within a page to be erased and programmed in a single operation without the need to erase or program any other bytes in the page IAP Lite is performed in the application under the control of the microcontroller s firmware using four SFRs and an internal 64 byte page register to facilitate erasing and programing within unsecured sectors These SFRs are FMCON Flash Control Register When read this is the status register When written this is a command register Note that the status bits are cleared to logic Os when the command is written FMADRL FMADRH Flash memory address low Flash memory address high Used to specify the byte address within the page register or specify the page within user code memory UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 135 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341 9351 9361 user manual FMDATA Flash Data Register Accepts data to be loaded into the page register The page register consists of 64 bytes and an update flag for each byte When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared When FMDATA is written the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL In addition the update flag for that location wil
200. ng the Disable Clear Configuration Protection bit DCCP in BOOTSTAT 7 toa logic 1 When DCCP is set the CCP command may still be used in ICP or parallel programming modes This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programming modes IAP error status It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory During an IAP erase program or CRC the CPU enters a program idle state The CPU will remain in this program idle state until the erase program or CRC cycle is completed These cycles are self timed When the cycle is completed code execution resumes If an interrupt occurs during an erase programming or CRC cycle the erase programming or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt An IAP error condition will be flagged by setting the carry flag and status information returned The status information returned is shown in Table 133 If the application permits interrupts during erasing programming or CRC cycles the user code should check the carry flag after each erase programming or CRC operation to see if an error occurred If the operation was aborted the user s code will need to repeat the operation All information provided this document is subject to legal disclaimers NXP B V 2012 All rights reserved U
201. nitiate a transfer and therefore collision can occur For receiving data received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character However the received character must be read from the Data Register before the next character has been completely shifted in Otherwise the previous data is lost WCOL can be cleared in software by writing a logic 1 to the bit Data mode Clock Phase Bit CPHA allows the user to set the edges for sampling and changing data The Clock Polarity bit CPOL allows the user to set the clock polarity Figure 46 to Figure 49 show the different settings of Clock Phase bit CPHA All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 113 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Clock cycle 1 SPICLK CPOL 0 PE y LE LE LE LE LE LI I SPICLK CPOL 1 LJ LE Ly TI MOSI input DORD 0 MSB v LSB SS if SSIG bit 0 002aaa934 1 Not defined Fig 46 SPI slave transfer format with CPHA 0 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 114 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 936
202. ns to disable and re enable interrupts may be removed In watchdog mode WDTE 1 writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8 bit down counter and the WDCON to the shadow register If writing to the WDCON register is not immediately followed by the feed sequence a watchdog reset will occur For example setting WDRUN 1 OV ACC WDCON get WDCON SETB ACC 2 set WD RUN 1 OV WDL 0FFh New count to be loaded to 8 bit down counter CLR EA disable interrupt OV WDCON ACC write back to WDCON after the watchdog is enabled a feed must occur immediately OV WFEEDI 0A5h do watchdog feed part 1 OV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt In timer mode WDTE 0 WDCON is loaded to the control register every CCLK cycle no feed sequence is required to load the control register but a feed sequence is required to load from the WDL SFR to the 8 bit down counter before a time out occurs The number of watchdog clocks before timing out is calculated by the following equations 205 PRE 1 1 3 where PRE is the value of prescaler PRE2 to PREO which can be the range 0 to 7 and WDL is the value of watchdog load register which can be the range of 0 to 255 The minimum number of tclks is tclks 20 904 1 1 33 4 The maximum number of tclks is All information provided in this document is subject to legal d
203. ock system timer The P89LPC9331 9341 9351 9361 has a simple Real time Clock System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down The Real time Clock can be an interrupt or a wake up source see Figure 24 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 66 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual The Real time Clock is a 23 bit down counter The clock source for this counter can be either the CPU clock or the XTAL1 2 oscillator There are five SFRs used for the RTC RTCCON Real time Clock control RTCH Real time Clock counter reload high bits 22 to 15 RTCL Real time Clock counter reload low bits 14 to 7 RTCDATH Real time clock data register high RTCDATL Real time Clock data register low The Real time clock system timer be enabled by setting the RTCEN 0 bit The Real time Clock is a 23 bit down counter initialized to all 05 when RTCEN 0 that is comprised of a 7 bit prescaler and a 16 bit loadable down counter When RTCEN is written with logic 1 the counter is first loaded with RTCH RTCL 1111111 and will count down When it reaches all 05 the counter will be reloaded again with RTCH RTCL 41111111 and a flag RTCF RTCCON 7 will be set T
204. on The P89LPC9331 9341 9351 9361 CPU interfaces with the 2 through six Special Function Registers SFRs I2CON Control Register I2DAT 12 Data Register 125 2 Status Register IZADR 12 Slave Address Register 25 SCL Duty Cycle Register High Byte and I2SCLL SCL Duty Cycle Register Low Byte I2C data register I2DAT register contains the data to be transmitted or the data received The CPU can read and write to this 8 bit register while it is not in the process of shifting a byte Thus this register should only be accessed when the SI bit is set Data in I2DAT remains stable as long as the SI bit is set Data in I2DAT is always shifted from right to left the first bit to be transmitted is the MSB bit 7 and after a byte has been received the first bit of received data is located at the MSB of I2DAT Table 92 12 data register 2 address DAh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol 120 7 2 6 120 5 120 4 120 120 2 120 2 0 Reset 0 0 0 0 0 0 0 0 I2C slave address register I2ADR register is readable and writable and is only used when the 2 interface is set to slave mode In master mode this register has no effect The LSB of I2ADR is general call bit When this bit is set the general call address 00h is recognized Table 93 12 slave address register IZADR address DBh bit allocation Bit 7 6 5 4 3 2 1
205. ontinuous conversion mode 40 Dual channel continuous conversion mode 40 Single step mode 41 Conversion mode selection bits 41 Conversion start 41 Timer triggered 41 Start immediately 41 Edge triggered 41 Dual start immediately 42 Boundary limits 42 All information provided in this document is subject to legal disclaimers 3 2 7 10 1 10 2 10 3 10 4 10 5 10 6 10 7 10 8 10 9 DAC output to a port pin with high output 42 Clock divider 42 I O pins used with ADC functions 42 Power down and Idle mode 43 48 Interrupt priority structure 48 External Interrupt pin glitch suppression 49 VO ports cicu I Rex 50 Port 51 Quasi bidirectional output configuration 51 Open drain output configuration 52 Input only configuration 53 Push pull output configuration 53 Port 0 and Analog Comparator functions 54 Additional port features 54 Power monitoring functions 55 Brownout detection 55 Power on detection 57 Power reduction
206. or condition will be transmitted STO flag will be reset UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 103 of 163 NXP Semiconductors UM10308 Table 103 Master Receiver mode continued P89LPC9331 9341 9351 9361 user manual Status code Status of the Application software response Next action taken by I2C hardware 125 hardware to from I2DAT I2CON STA STO E STA 50h Data byte has Read data byte 0 0 0 0 Data byte will be received NOT ACK been received bit will be returned ACK has been read data byte 0 0 0 1 Data byte will be received ACK bit returned will be returned 58h Data byte has Read data byte or 1 0 x Repeated START will be transmitted been received read data byte 0 1 x STOP condition will be transmitted NACK has been STO flag will be reset returned read data byte 1 1 0 x STOP condition followed by a START condition will be transmitted STO flag will be reset Table 104 Slave Receiver mode Status code Status of the 2 Application software response Next action taken by I2STAT hardware to from I2DAT to I2CON hardware STA STO 51 AA 60H Own SLA W has nol2DAT action x 0 0 0 Data byte will be received and NOT been received or ACK will be returned ACK has been no I2DAT action x 0 0 1 Data byte will be received and
207. ort 0 respectively Setting the corresponding bit in PTOAD disables that pin s digital input Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port On any reset PTOAD bits 1 through 5 default to logic Os to enable the digital functions Additional port features After power up all pins are in Input Only mode Please note that this is different from the LPC76x series of devices After power up all I O pins except P1 5 may be configured by software Pin P1 5 is input only Pins P1 2 and P1 3 are configurable for either input only or open drain Every output on the P89LPC9331 9341 9351 9361 has been designed to sink typical LED drive current However there is a maximum total output current for all ports which must not be exceeded Please refer to the P89LPC9331 9341 9351 9361 data sheet for detailed specifications All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals The slew rate is factory set to approximately 10 ns rise and fall times All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 54 of 163 NXP Semiconductors UM10308 Table 43 Port output configuration P89LPC9331 9341 9351 9361 user manual Port pin Configuration SFR bits PxM1 y PxM2 y PO 0 POM1 0 P
208. own slave address has been received 2 The general call address has been received while the general call bit GC in 2 is set 3 A data byte has been received while the 2 interface is in the Master Receiver Mode 4 A data byte has been received while the 2 interface is in the addressed Slave Receiver Mode When cleared to 0 an not acknowledge high level to SDA will be returned during the acknowledge clock pulse on the SCL line on the following situations 1 data byte has been received while the 2 interface is in the Master Receiver Mode 2 A data byte has been received while the I C interface is in the addressed Slave Receiver Mode UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 95 of 163 NXP Semiconductors U M1 0308 UM10308 12 4 12 5 P89LPC9331 9341 9351 9361 user manual Table 96 12 Control register 2 address D8h bit description continued Bit Symbol Description 3 SI 2 Interrupt Flag This bit is set when one of the 25 possible I C states is entered When EA bit and EI2C 1 0 bit are both set an interrupt is requested when SI is set Must be cleared by software by writing O to this bit 4 STO STOP Flag STO 1 In master mode a STOP condition is transmitted to the 2 When the bus detects the STOP condition it will clear STO bit au
209. ports and Port 3 is a 2 bit port The exact number of I O pins available depends upon the clock and reset options chosen see Table 41 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 50 of 163 NXP Semiconductors U M1 0308 UM10308 5 1 5 2 P89LPC9331 9341 9351 9361 user manual Table 41 Number of I O pins available Clock source Reset option Number of I O pins On chip oscillator or watchdog No external reset except during power up 26 oscillator External RST pin supported 25 External clock input No external reset except during power up 25 External RST pin supported 24 Low medium high speed oscillator external reset except during power 24 external crystal or resonator External RST pin supported 23 Port configurations All but three I O port pins on the P89LPC9331 9341 9351 9361 may be configured by software to one of four types on a pin by pin basis as shown in Table 42 These are quasi bidirectional standard 80C51 port outputs push pull open drain and input only Two configuration registers for each port select the output type for each port pin P1 5 RST can only be an input and cannot be configured P1 2 SCL TO and P1 3 SDA INTO may only be configured to be either input only or open drain Table 42 Port output configuration settings 1 2 Por
210. pt will occur If DBISEL is logic 1 and INTLO is logic 0 a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter which is also the last data f DBISEL is logic 1 and INTLO is logic 1 a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter which is also the last data 7 If there is more data the CPU writes to TB8 again 8 The CPU writes to SBUF again Then f INTLO is logic 0 the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter If INTLO is logic 1 the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter 9 Go to 4 10 Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following Multiprocessor communications UART modes 2 and 3 have a special provision for multiprocessor communications In these modes 9 data bits are received or transmitted When data is received the 9th bit is stored in RB8 The UART can be programmed such that when the stop bit is received the serial port interrupt will be activated only if RB8 1 This feature is enabled by setting bit 5 2 in SCON One way to use this feature mu
211. r SSTAT A break is detected when any 11 consecutive bits are sensed low Since a break condition also satisfies the requirements for a framing error a break condition will also result in reporting a framing error Once a break condition has been detected the UART will go into an idle state and remain in this idle state until a stop bit has been received The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit AUXR1 6 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 84 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Table 84 Serial Port Control register SCON address 98h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol SMO FE SM1 SM2 REN TB8 RB8 TI RI Reset X X X X x X 0 0 Table 85 Serial Port Control register SCON address 98h bit description Bit Symbol Description 0 Receive interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 approximately halfway through the stop bit time in Mode 1 For Mode 2 or Mode 3 if SMODO it is set near the middle of the 9th data bit bit 8 If SMODO 1 it is set near the middle of the stop bit see SM2 SCON 5 for exceptions Must be cleared by software 1 Transmit interrupt flag Set by hardware at the end of the 8th bit time in Mode 0 or at the stop bit se
212. r 1 ACH control register Comparator 2 ADH control register Data EEPROM F1H control register Data EEPROM F2H data register Data EEPROM address register Bit functions and addresses Reset value MSB LSB Hex Binary 00 0000 0000 CLKLP EBRR ENT1 ENTO SRST 0 DPS 00 0000 00x0 F7 F6 F5 F4 F3 F2 F1 FO 00 0000 0000 00 0000 0000 00 0000 0000 SBRGS BRGEN 00217 xx00 ICECA2 ICECA1 ICECAO ICESA ICNFA FCOA OCMA1 OCMAO 00 0000 0000 ICECB2 ICECB1 ICECBO ICESB ICNFB FCOB OCMB1 OCMBO 00 0000 0000 FCOC OCMC1 OCMCO 00 xxxx x000 FCOD OCMD1 OCMDO 00 000 CE1 CP1 CN1 1 CO1 CMF1 0001 00 0000 CE2 CP2 CN2 OE2 2 CMF2 0011 00 0000 EEIF HVERR ECTL1 ECTLO EWERR1 EWERRO EADR8 80 1000 0000 00 0000 0000 00 0000 0000 956 16 56 1756 1556 4 168 80601 1 dXN asn 2102 15 02 jeba 12e qns jueuinoop siy 6911012 80601 1 pamasa Su 72102 7 74 dXN Table 5 Special function registers P89LPC9351 9361 indicates SFRs that are bit addressable Name DIVM DPTR DPH DPL FMADRH FMADRL FMCON FMDATA I2ADR I2CON I2DAT I2SCLH I2SCLL 125 Description SFR Bit functions and addresses Reset value addr MSB LSB Hex Binary CPU
213. r Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1 A unique address for slave 1 would be 1100 0001 since a 1 in bit O will exclude slave 0 Both slaves can be selected at the same time by an address which has bit 0 0 for slave 0 and bit 1 0 for slave 1 Thus both could be addressed with 1100 0000 In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0 Table 91 Slave 0 1 2 examples Example 1 Slave 0 SADDR SADEN Given UM10308 1 2 3 1100 0000 Slave1 SADDR 11100000 Slave 2 SADDR 1100 0000 1111 1001 SADEN 1111 1010 SADEN 1111 1100 1100 0XX0 Given 1110 0X0X Given 1110 00XX ll ll In the above example the differentiation among the 3 slaves is in the lower 3 address bits Slave 0 requires that bit 0 0 and it can be uniquely addressed by 1110 0110 Slave 1 requires that bit 1 0 and it can be uniquely addressed by 1110 and 0101 Slave 2 requires that bit 2 0 and its unique address is 1110 0011 To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100 since it is necessary to make bit 2 1 to exclude slave 2 The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN Zeros in this result are treated as don t cares In most cases interpreting the don t cares as ones the broadcast address will be FF hexadecimal Upon All information provided in this document is subject to leg
214. r and the 8 bit down counter Before the feed sequence any new values written to these two SFRs will not take effect To avoid a watchdog reset the watchdog timer needs to be fed via a special sequence of software action called the feed sequence prior to reaching an underflow All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 124 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341 9351 9361 user manual To feed the watchdog two write instructions must be sequentially executed successfully Between the two write instructions SFR reads are allowed but writes are not allowed The instructions should move to the WFEED1 register and then to the WFEED2 register An incorrect feed sequence will cause an immediate watchdog reset The program sequence to feed the watchdog timer is as follows CLR EA disable interrupt WFEED1 0A5h do watchdog feed part 1 MOV WFEED2 05Ah do watchdog feed part 2 SETB EA enable interrupt This sequence assumes that the P89LPC9331 9341 9351 9361 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence If an interrupt was allowed to be serviced and the service routine contained any SFR writes it would trigger a watchdog reset If it is known that no interrupt could occur during the feed sequence the instructio
215. r details Table 97 Status register 125 address D9h bit allocation Bit 7 6 5 4 3 2 1 Symbol 5 4 STA 3 STA 2 STA 1 5 0 0 0 Reset 0 0 0 0 0 0 0 Table 98 Status register 125 address D9h bit description Bit Symbol Description 0 2 Reserved are always set to 0 3 7 STA 0 4 12C Status code 2 SCL duty cycle registers I2SCLH and I2SCLL When the internal SCL generator is selected for the 2 interface by setting CRSEL 0 in the I2CON register the user must set values for registers I2SCLL and I2SCLH to select the data rate I2SCLH defines the number of PCLK cycles for SCL high I2SCLL defines the number of PCLK cycles for SCL low The frequency is determined by the following formula Bit Frequency PCLK 2 I2SCLH I2SCLL Where fpc x is the frequency of PCLK All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 96 of 163 NXP Semiconductors U M1 0308 UM10308 12 6 12 6 1 P89LPC9331 9341 9351 9361 user manual The values for I2SCLL and I2SCLH do not have to be the same the user can give different duty cycles for SCL by setting these two registers However the value of the register must ensure that the data rate is in the 2 data rate range of 0 to 400 kHz Thus the values of I2SCLL and I2SCLH have some restrictions and values for both regi
216. r used during power down These include Brownout Detect e Watchdog Timer if WOCLK WDCON O is logic 1 e Comparators Note Comparators be powered down separately with PCONA 5 set to logic 1 and comparators disabled Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD i e 7 is logic 1 Total Power down mode This is the same as Power down mode except that the Brownout Detection circuitry and the voltage comparators are also disabled to conserve additional power Note that a brownout reset or interrupt will not occur Voltage comparator interrupts and Brownout interrupt cannot be used as a wake up source The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled The following are the wake up options supported e Watchdog Timer if WDCLK WDCON O is logic 1 Could generate Interrupt or Reset either one can wake up the device External interrupts INTO INT1 when programmed to level triggered mode Keyboard Interrupt Real time Clock System Timer and the crystal oscillator circuitry if this block is using it unless RTCPD 7 is logic 1 Note Using the internal RC oscillator to clock the RTC during power down may result in relatively high power consumption Lower power consumption can be achieved by using an external low frequency clock when the Real time Clock or watchdog timer
217. r value comes from UCFG1 and UCFG2 The reset value of CLKCON 2 to CLKCON 0 come from UCFG1 2 to UCFG1 0 and reset value of CLKDBL bit comes from UCFG2 7 Table 10 Clock control register CLKCON address FFDEh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKOK XTALWD CLKDBL FOSC2 FOSC1 FOSCO Reset 1 0 0 0 X X X X Table 11 Clock control register CLKCON address FFDEh bit description Bit Symbol Description 2 0 FOSC2 FOSC1 CPU oscillator type selection for clock switch See Section 2 for additional FOSCO information Combinations other than those shown in Table 12 are reserved for future use and should not be used 3 CLKDBL Clock doubler option for clock switch When set doubles the output frequency of the internal RC oscillator 4 XTALWD Low speed external crystal oscillator as the clock source of watchdog timer When 0 disable the external crystal oscillator as the clock source of watchdog timer 6 5 reserved 7 CLKOK Clock switch completed flag When 1 clock switch is completed When 0 clock switch is processing and writing to register CLKCON is not allowed Table 12 Oscillator type selection for clock switch FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 5 96 011 Internal RC oscillator 7 373 MHz x 1 96 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator
218. rd formats continued Record type Command daia function 06 Read Global CRC 00xxxx06cc Where xxxx required field but value is a don t care cc checksum Example 00000006FA 07 Direct Load of Baud Rate 02xxxx07HHLLcc Where xxxx required field but value is a don t care HH high byte of timer LL low byte of timer cc checksum Example 02000007FFFFF9 08 Reset MCU 00xxxx08cc Where xxxx required field but value is a don t care cc checksum Example 00000008F8 In application programming IAP Several In Application Programming IAP calls are available for use by an application program to permit selective erasing and programming of Flash sectors pages security bits configuration bytes and device id All calls are made through a common interface PGM_MTP The programming functions are selected by setting up the microcontroller s registers before making a call to PGM_MTP at The IAP calls are shown in Table 134 IAP authorization key IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call This authorization key is set by writing 96H to RAM location FFH The following example was written using the Keil C compiler The methods used to access a specific physical address in memory may vary with other compilers include lt ABSACC H gt enable absolute memory access define
219. receiver fails to see a valid STOP bit at the end of the frame Cleared by software 4 DBISEL Double buffering transmit interrupt select Used only if double buffering is enabled This bit controls the number of interrupts that can occur when double buffering is enabled When set one transmit interrupt is generated after each character written to SBUF and there is also one more transmit interrupt generated at the beginning INTLO 0 or the end 1 of the STOP bit of the last character sent i e no more data in buffer This last interrupt can be used to indicate that all transmit operations are over When cleared 0 only one transmit interrupt is generated per character written to SBUF Must be logic 0 when double buffering is disabled Note that except for the first character written when buffer is empty the location of the transmit interrupt is determined by INTLO When the first character is written the transmit interrupt is generated immediately after SBUF is written 5 CIDIS Combined Interrupt Disable When set 1 Rx and Tx interrupts are separate When cleared 0 the UART uses a combined Tx Rx interrupt like a conventional 80 51 UART This bit is reset to logic 0 to select combined interrupts 6 _ Transmit interrupt position When cleared 0 the Tx interrupt is issued at the beginning of the stop bit When set 1 the Tx interrupt is issued at end of the stop bit Must be logic 0 for mode 0 Note that
220. recognized General call address will be recognized if IZADR 0 1 A START condition will be transmitted when the bus becomes free 13 Serial Peripheral Interface SPI UM10308 The P89LPC9331 9341 9351 9361 provides another high speed serial communication interface the SPI interface SPI is a full duplex high speed synchronous communication bus with two operation modes Master mode and Slave mode Up to 3 Mbit s can be supported in either Master or Slave mode It has a Transfer Completion Flag and Write Collision Flag Protection All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 107 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual SPR1 SPIF woot CPU clock DIVIDER BY 4 16 64 128 SEL 8 BIT SHIFT REGISTER READ DATA BUFFER SPI clock master SPR SPI CONTROL 4 SPI STATUS REGISTER MISO P2 3 MOSI P2 2 SPICLK P2 5 58 2 4 SPI CONTROL REGISTER SPI internal interrupt data request bus Fig 42 SPI block diagram 002 900 UM10308 The SPI interface has four pins SPICLK MOSI MISO and SS SPICLK MOSI and MISO are typically tied together between two or more SPI devices Data flows from master to slave on the
221. ress 97h Table 51 Reset Sources register RSTSRC address DFh bit description 43 bit allocation 61 Table 21 A D Control register 1 ADCON1 address 97h bit Table 52 Reset Sources register RSTSRC address DFh allocation 44 bit description 61 Table 22 A D Control register 1 ADCON1 address 97h bit Table 53 Timer Counter Mode register TMOD address description 44 89h bit allocation 62 Table 23 A D Mode register A ADMODA address 0COh Table 54 Timer Counter Mode register TMOD address bit 44 89h bit description 62 Table 24 A D Mode register A ADMODA address OCOh Table 55 Timer Counter Auxiliary Mode register TAMOD bit description 44 address 8Fh bit allocation 63 Table 25 A D Mode register ADMODB address A1h bit Table 56 Timer Counter Auxiliary Mode register TAMOD AllOCALION a eas 45 address 8Fh bit description 63 Table 26 A D Mode register B ADMODB address A1h bit Table 57 Timer Counter Control register TCON address COSCHPUOM escep sanii x Rem bee p doe 45 88h bit allocation 64 Table 27 A D Input select ADINS address A3h bit Table 58 Timer Counter Control register TCON address alloCatlon
222. rising edge on P1 4 5 TMM1 Timer Trigger Mode 1 Selects either stop mode TMM1 0 or timer trigger mode TMM1 1 when the ADCS11 and ADCS10 bits 00 6 ENADCI1 Enable A D Conversion complete Interrupt 1 When set will cause an interrupt if the ADCI flag is set and the A D interrupt is enabled 7 Enable A D boundary interrupt 1 When set will cause and interrupt if the boundary interrupt 1flag BNDI1 is set and the A D interrupt is enabled Table 23 A D Mode register ADMODA address OCOh bit allocation Bit 7 6 5 4 3 2 1 0 Symbol BNDI1 BURST1 1 SCAN1 BNDIO BURSTO SCCO SCANO Reset 0 0 0 0 0 0 0 0 Table 24 A D Mode register ADMODA address 0COh bit description Bit Symbol Description 0 SCANO When 1 selects single conversion mode auto scan or fixed channel for ADCO 1 SCCO When 1 selects fixed channel continuous conversion mode for ADCO 2 BURSTO When 1 selects auto scan continuous conversion mode for ADCO 3 BNDIO ADCO boundary interrupt flag When set indicates that the converted result is outside of the range defined by the ADCO boundary registers 4 SCAN1 When 1 selects single conversion mode auto scan or fixed channel for ADC1 5 SCC1 When 1 selects fixed channel continuous conversion mode for ADC1 6 BURST1 When 1 selects auto scan continuous conversion mode for ADC1 7 BNDI1 ADC1 boundary interrupt flag When set indicates that the converted result is outsi
223. rrupt occurs during an erase programming cycle the erase programming cycle will be aborted and the OI flag Operation Interrupted in FMCON will be set If the application permits interrupts during erasing programming the user code should check the Ol flag FMCON 0 after each erase programming operation to see if the operation was aborted If the operation was aborted the user s code will need to repeat the process starting with loading the page register The erase program cycle takes 4 ms 2 ms for erase 2 ms for programming to complete regardless of the number of bytes that were loaded into the page register Erasing programming of a single byte or multiple bytes in code memory is accomplished using the following steps Write the LOAD command 00H to FMCON The LOAD command will clear all locations in the page register and their corresponding update flags Write the address within the page register to FMADRL Since the loading the page register uses FMADRL 5 0 and since the erase program command uses FMADRH and FMADRL T7 6 the user can write the byte location within the page register FMADRL 5 0 and the code memory page address FMADRH and FMADRL T7 6 at this time Write the data to be programmed to FMDATA This will increment FMADRL pointing to the next byte in the page register Write the address of the next byte to be programmed to FMADRL if desired Not needed for contiguous bytes since FMADRL is auto incremented
224. s U M1 0308 19 11 UM10308 P89LPC9331 9341 9351 9361 user manual and embedded within each P89LPC9331 9341 9351 9361 device The NXP In System Programming facility has made in circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area The ISP function uses five pins Vss TXDO RXDO and RST Only a small connector needs to be available to interface your application to an external circuit in order to use this feature Using the In system programming ISP The ISP feature allows for a wide range of baud rates to be used in your application independent of the oscillator frequency It is also adaptable to a wide range of oscillator frequencies This is accomplished by measuring the bit time of a single bit in a received character This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency The ISP feature requires that an initial character an uppercase U be sent to the P89LPC9331 9341 9351 9361 to establish the baud rate The ISP firmware provides auto echo of received characters Once baud rate initialization has been performed the ISP firmware will only accept Intel Hex type records Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below NNAAAARRDD DDCC crlf In the Intel Hex record the NN represents the number of data bytes in the record T
225. s a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted Double buffering allows transmission of a string of characters with only one stop bit between any two characters provided the next character is written between the start bit and the stop bit of the previous character Double buffering can be disabled If disabled DBMOD i e SSTAT 7 0 the UART is compatible with the conventional 80C51 UART If enabled the UART allows writing to SnBUF while the previous data is being shifted out Double buffering in different modes Double buffering is only allowed in Modes 1 2 and 3 When operated in Mode 0 double buffering must be disabled DBMOD 0 Transmit interrupts with double buffering enabled Modes 1 2 and 3 Unlike the conventional UART when double buffering is enabled the Tx interrupt is generated when the double buffer is ready to receive new data The following occurs during a transmission assuming eight data bits 1 The double buffer is empty initially 2 The CPU writes to SBUF 3 The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately 4 If there is more data go to 6 else continue 5 If there is no more data then f DBISEL is logic 0 no more interrupts will occur All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User
226. s subject to legal disclaimers NXP B V 2012 rights reserved User manual Rev 4 1 20 August 2012 127 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual MOV WFEED1 0A5H MOV WFEED2 05AH Watchdog PRESCALER ma 8 BIT DOWN oscillator COUNTER A i oscillator SHADOW REGISTER XTALWD reset WDCON A7H PRE2 PRE1 PREO WDRUN WDTOF WDCLK PRE emet preo wonuN woror woe Fig 54 Watchdog Timer in Watchdog Mode WDTE 1 002aae093 16 4 Watchdog Timer in Timer mode Figure 55 shows the Watchdog Timer in Timer Mode In this mode any changes to WDCON are written to the shadow register after one watchdog clock cycle A watchdog underflow will set the WDTOF bit If IENO 6 is set the watchdog underflow is enabled to cause an interrupt WDTOF is cleared by writing a logic O to this bit in software When an underflow occurs the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs Incorrect feeds are ignored in this mode UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 Aug
227. sabled during ISP or IAP modes This command can still be used in ICP or parallel programmer modes If programmed to 0 the CCP command can be used in all programming modes This bit is set by programming the BOOTSTAT register This bit is cleared by writing the Clear Configuration Protection CCP command in either ICP or parallel programmer modes UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 152 of 163 NXP Semiconductors UM10308 20 Instruction set P89LPC9331 9341 9351 9361 user manual Table 147 Instruction set summary Mnemonic Description Bytes Cycles Hex code ARITHMETIC ADD A Rn Add register to A 1 1 28 to 2F ADD A dir Add direct byte to A 2 1 25 ADD A Ri Add indirect memory to A 1 1 26 to 27 ADD A data Add immediate to A 2 1 24 ADDC A Rn Add register to A with carry 1 1 38 to 3F ADDC Add direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 to 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 to 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with 1 1 96 to 97 borrow SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increment A 1 1 04 INC Rn Increment register 1 1 08 to OF INC dir Increment direct
228. see Section 6 1 Brownout detection 6 RPE Reset pin enable When set 1 enables the reset function of pin P1 5 When cleared P1 5 may be used as an input pin NOTE During a power up sequence the RPE selection is overridden and this pin will always functions as a reset input After power up the pin will function as defined by the RPE bit Only a power up reset will temporarily override the selection defined by RPE bit Other sources of reset will not override the RPE bit 7 WDTE Watchdog timer reset enable When set 1 enables the watchdog timer reset When cleared 0 disables the watchdog timer reset The timer may still be used to generate an interrupt Refer to Table 120 Watchdog timer configuration for details Table 137 Oscillator type selection FOSC 2 0 Oscillator configuration 111 External clock input on XTAL1 100 Watchdog Oscillator 400 kHz 5 96 011 Internal RC oscillator 7 373 MHz x 1 95 010 Low frequency crystal 20 kHz to 100 kHz 001 Medium frequency crystal or resonator 100 kHz to 4 MHz 000 High frequency crystal or resonator 4 MHz to 18 MHz Table 138 Flash User Configuration Byte 2 UCFG2 bit allocation Bit 7 6 5 4 3 2 1 0 Symbol CLKDBL 2 0 X X X X X X X value Table 139 Flash User Configuration Byte 2 UCFG2 bit description Bit Symbol Description 0 6 Not used 7 CLKDBL Clock doubler When set doubles the output
229. ser manual Rev 4 1 20 August 2012 145 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 133 IAP error status Bit Flag Description 0 Ol Operation Interrupted Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle 1 SV Security Violation Set if program or erase operation fails due to security settings Cycle is aborted Memory contents are unchanged CRC output is invalid 2 HVE High Voltage Error Set if error detected in high voltage generation circuits Cycle is aborted Memory contents may be corrupted 3 VE Verify error Set during IAP programming of user code if the contents of the programmed address does not agree with the intended programmed value IAP uses the MOVC instruction to perform this verify Attempts to program user code that is MOVC protected can be programmed but will generate this error after the programming cycle has been completed 4to7 unused reads as a logic 0 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 146 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Table 134 IAP function calls IAP function IAP call parameters Program User Code Page Input parameters requires key Read Version Id 00h R32 number of bytes to program R4 pa
230. set enables PO 1 as a cause of a Keypad Interrupt 2 KBMASK 2 When set enables 0 2 as a cause of a Keypad Interrupt 3 KBMASK 3 When set enables P0 3 as a cause of a Keypad Interrupt 4 KBMASK A When set enables 0 4 as a cause of a Keypad Interrupt 5 KBMASK 5 When set enables 0 5 as a cause of a Keypad Interrupt 6 KBMASK 6 When set enables PO 6 as a cause of a Keypad Interrupt 7 KBMASK 7 When set enables 0 7 as a cause of a Keypad Interrupt 1 The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective 16 Watchdog timer WDT The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count The watchdog timer can only be reset by a power on reset 16 1 Watchdog function The user has the ability using the WDCON and UCFG1 registers to control the run stop condition of the WDT the clock source for the WDT the prescaler value and whether the WDT is enabled to reset the device on underflow In addition there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer The WDTE bit UCFG1 7 if set enables the WDT to reset the device on underflow Following reset the WDT will be running regardless of the state of
231. sters greater than three PCLKs are recommended Table 99 12C clock rates selection Bit data rate Kbit sec at fosc I2SCLL CRSEL 7 373 MHz 3 6865 MHz 1 8433 MHz 12 MHz 6 MHz I2SCLH 6 0 307 154 7 0 263 132 8 0 230 115 375 9 0 205 102 333 10 0 369 184 92 300 15 0 246 123 61 400 200 25 0 147 74 37 240 120 30 0 123 61 31 200 100 50 0 74 37 18 120 60 60 0 61 31 15 100 50 100 0 37 18 9 60 30 150 0 25 12 6 40 20 200 0 18 9 5 30 15 1 3 6 Kbps to 1 8 Kbpsto 0 9 Kbpsto 5 86Kbpsto 2 93 Kbps to 922 Kbps 461 Kbps 230 Kbps 1500 Kbps 750 Kbps Timer 1 in Timer 1 in Timer 1 in Timer 1 in Timer 1 in mode 2 mode 2 mode 2 mode 2 mode 2 12 operation modes Master Transmitter mode In this mode data is transmitted from master to slave Before the Master Transmitter mode can be entered I2CON must be initialized as follows Table 100 Control register 2 address D8h Bit 7 6 5 4 3 2 1 0 2 5 5 CRSEL value 1 0 0 0 x bit rate CRSEL defines the bit rate 2 must be set to 1 to enable the 2 function If the AA bit is 0 it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode STA STO and SI bits must be cleared to 0 All information provided in this document is subject to legal disclaimers NXP B V 2012 All righ
232. subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 112 of 163 NXP Semiconductors U M1 0308 UM10308 13 5 13 6 P89LPC9331 9341 9351 9361 user manual slave and start sending data to it To avoid bus contention the SPI becomes a slave As a result of the SPI becoming a slave the MOSI and SPICLK pins are forced to be an input and MISO becomes an output The SPIF flag in SPSTAT is set and if the SPI interrupt is enabled an SPI interrupt will occur User software should always check the MSTR bit If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master the user must set the MSTR bit again otherwise it will stay in slave mode Write collision The SPI is single buffered in the transmit direction and double buffered in the receive direction New data for transmission can not be written to the shift register until the previous transaction is complete The WCOL SPSTAT 6 bit is set to indicate data collision when the data register is written during transmission In this case the data currently being transmitted will continue to be transmitted but the new data i e the one causing the collision will be lost While write collision is detected for both a master or a slave it is uncommon for a master because the master has full control of the transfer in progress The slave however has no control over when the master will i
233. t description Bit Symbol Description 0 TPCR2L 0 Prescaler bit 0 1 TPCR2L 1 Prescaler bit 1 2 TPCR2L 2 Prescaler bit 2 3 TPCR2L 3 Prescaler bit 3 4 TPCR2L 4 Prescaler bit 4 UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 72 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 65 CCU prescaler control register low byte TPCR2L address CAh bit description Bit Symbol Description 5 TPCR2L 5 Prescaler bit 5 6 TPCR2L 6 Prescaler bit 6 7 TPCR2L 7 Prescaler bit 7 Table 66 CCU control register 0 TCR20 address C8h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol PLLEN HLTRN HLTEN ALTCD ALTAB TDIR2 TMOD21 TMOD20 Reset 0 0 0 0 0 0 0 0 Table 67 CCU control register 0 TCR20 address C8h bit description Bit Symbol 1 2 TMOD20 21 2 TDIR2 3 ALTAB 4 ALTCD 5 HLTEN 6 HLTRN 7 PLLEN Description CCU Timer mode TMOD21 TMOD20 00 Timer is stopped 01 Basic timer function 10 Asymmetrical PWM uses PLL as clock source 11 Symmetrical PWM uses PLL as clock source Count direction of the CCU Timer When logic 0 count up When logic 1 count down PWM channel A B alternately output enable When this bit is set the output of PWM channel A and B are alternately gated on every counter cycle PWM channel C D alternately output enable W
234. t if the correct values are already written to DEECON there is no need to write to this register 2 Write the data to the DEEDAT register 3 Write address bits 7 to 0 to DEEADR 4 Poll EWERR1 flag If EWERR1 DEECON 2 bit is logic 1 BOD EEPROM occurred Vdd 2 4V and Data EEPROM program is blocked All information provided this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 132 of 163 NXP Semiconductors U M1 0308 18 3 18 4 18 5 18 6 UM10308 P89LPC9331 9341 9351 9361 user manual 5 If both the EIEE IEN1 7 bit and the EA IENO 7 bit are logic 1s wait for the Data EEPROM interrupt then read poll the EEIF DEECON 7 bit until it is set to logic 1 If EIEE or EA is logic 0 the interrupt is disabled and only polling is enabled When EEIF is logic 1 the operation is complete and data is written 6 Poll EWERRO flag If EWERRO DEECON 1 bit is logic 1 it means BOD EEPROM occurred Vdd 2 4V during program or erase and the previous operation may not be correct As a write to the DEEDAT register followed by a write to the DEEADR register will automatically set off a write if DEECON 5 4 4007 the user must take great caution in a write to the DEEDAT register It is strongly recommended that the user disables interrupts prior to a write to the DEEDAT register and enable interrupts after all writes are over An example is as fo
235. t is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 108 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341 9351 9361 user manual Table 107 SPI Control register SPCTL address E2h bit description Bit Symbol Description 0 SPRO SPI Clock Rate Select 1 SPRI SPR1 SPRO 00 CCLKy 01 CCLKy 6 10 CCLKy 11 CCLKy 28 2 SPI Clock PHAse select see Figure 46 to Figure 49 1 Data is driven on the leading edge of SPICLK and is sampled on the trailing edge 0 Data is driven when SS is low SSIG 0 and changes on the trailing edge of SPICLK and is sampled on the leading edge Note If SSIG 1 the operation is not defined 3 CPOL SPI Clock POLarity see Figure 46 to Figure 49 1 SPICLK is high when idle The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge 0 SPICLK is low when idle The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge 4 MSTR Master Slave mode Select see Table 111 5 DORD SPI Data ORDer 1 The LSB of the data word is transmitted first 0 The MSB of the data word is transmitted first 6 5 SPI Enable 1 The SPI is enabled 0 The SPI is disabled and all SPI pins will be port pins 7 590 8510 1 MSTR bit 4 decides whether the device is a master or slave 0 T
236. t output mode 0 0 Quasi bidirectional 0 1 Push pull 1 0 Input only high impedance 1 1 Open drain Quasi bidirectional output configuration Quasi bidirectional outputs can be used both as an input and output without the need to reconfigure the port This is possible because when the port outputs a logic high it is weakly driven allowing an external device to pull the pin low When the pin is driven low it is driven strongly and able to sink a large current There are three pull up transistors in the quasi bidirectional output that serve different purposes One of these pull ups called the very weak pull up is turned on whenever the port latch for the pin contains a logic 1 This very weak pull up sources a very small current that will pull the pin high if it is left floating A second pull up called the weak pull up is turned on when the port latch for the pin contains logic 1 and the pin itself is also at a logic 1 level This pull up provides the primary source current for a quasi bidirectional pin that is outputting a 1 If this pin is pulled low by an external device the weak pull up turns off and only the very weak pull up remains on In order to pull the pin low under these conditions the external device has to sink enough current to overpower the weak pull up and pull the port pin below its input threshold voltage All information provided in this document is subject to legal disclaimers NXP B V 2012
237. t underflows and the watchdog reset is enabled When the watchdog reset is enabled writing to WDL or WDCON must be followed by a feed sequence for the new values to take effect If a watchdog reset occurs its behavior is similar to power on reset Both POF and BOF are cleared Table 120 Watchdog timer configuration WDTE WDSE FUNCTION 0 x The watchdog reset is disabled The timer can be used as an internal timer and can be used to generate an interrupt WDSE has no effect 1 0 The watchdog reset is enabled The user can set WDCLK to choose the clock source 1 1 The watchdog reset is enabled along with additional safety features 1 WDCLK is forced to 1 using watchdog oscillator 2 WDCON and WDL register can only be written once WDRUN is forced to 1 Watchdog oscillator crystal oscillator XTALWD PRE2 PRE1 PREO Fig 53 Watchdog Prescaler Watchdog clock after a Watchdog feed sequence r pix r TO WATCHDOG DOWN COUNTER after prescaler 1 count delay DECODE 002 092 UM10308 16 2 Feed sequence The watchdog timer control register and the 8 bit down counter See Figure 54 are not directly loaded by the user The user writes to the WDCON and the WDL SFRs At the end of a feed sequence the values in the WDCON and WDL SFRs are loaded to the control registe
238. ter If the SPI is enabled SPEN 1 and selected as master writing to the SPI data register by the master starts the SPI clock generator and data transfer The data will start to appear on MOSI about one half SPI bit time to one SPI bit time after data is written to SPDAT Note that the master can select a slave by driving the SS pin of the corresponding device low Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master After shifting one byte the SPI clock generator stops setting the transfer completion flag SPIF and an interrupt will be created if the SPI interrupt is enabled ESPI or IEN1 3 1 The two shift registers in the master CPU and slave CPU can be considered as one distributed 16 bit circular shift register When data is shifted from the master to the slave data is also shifted in the opposite direction simultaneously This means that during one shift cycle data in the master and the slave are interchanged 13 4 Mode change on SS If SPEN 1 SSIG 0 and MSTR 1 the SPI is enabled in master mode The SS pin can be configured as an input P2M2 4 P2M1 4 00 or quasi bidirectional P2M2 4 2 1 4 01 In this case another master can drive this pin low to select this device as an SPI UM10308 All information provided in this document is
239. the WDTE bit The WDRUN bit WDCON 2 can be set to start the WDT and cleared to stop the WDT Following reset this bit will be set and the WDT will be running All writes to WDCON need to be followed by a feed sequence see Section 16 2 Additional bits in WDCON allow the user to select the clock source for the WDT and the prescaler When the timer is not enabled to reset the device on underflow the WDT can be used in timer mode and be enabled to produce an interrupt IENO 6 if desired The Watchdog Safety Enable bit WDSE UCFG1 4 along with WDTE is designed to force certain operating conditions at power up Refer to Table 120 for details Figure 54 shows the watchdog timer in watchdog mode It consists of a programmable 13 bit prescaler and an 8 bit down counter The down counter is clocked decremented by a tap taken from the prescaler The clock source for the prescaler is either PCLK low UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 123 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual speed crystal oscillator or the watchdog oscillator selected by the WDCLK bit in the WDCON register and XTALWD bit in the CLKCON register Note that switching of the clock sources will not take effect immediately see Section 16 3 The watchdog asserts the watchdog reset when the watchdog coun
240. tomatically In slave mode setting this bit can recover from an error condition In this case no STOP condition is transmitted to the bus The hardware behaves as if a STOP condition has been received and it switches to not addressed Slave Receiver Mode The STO flag is cleared by hardware automatically 5 STA Start Flag STA 1 2 enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator When the I C interface is already in master mode and some data is transmitted or received it transmits a repeated START condition STA may be set at any time it may also be set when the 12C interface is in an addressed slave mode STA 0 no START condition or repeated START condition will be generated 6 I2EN 2 Interface Enable When set enables the 12C interface When clear the function is disabled 7 reserved 2 Status register This is a read only register It contains the status code of the 2 interface The least three bits are always 0 There are 26 possible status codes When the code is F8H there is no relevant information available and SI bit is not set All other 25 status codes correspond to defined 2 states When any of these states entered the SI bit will be set Refer to Table 102 to Table 105 fo
241. tor must be configured in one of the following modes Low frequency crystal medium frequency crystal or high frequency crystal 1 A series resistor may be required to limit crystal drive levels This is especially important for low frequency crystals see text Fig 8 Using the crystal oscillator XTAL1 XTAL2 OSCCLK CCLK RC OSCILLATOR RCCLK cew i WITH CLOCK DOUBLER 7 3728 MHz 14 7456 MHz 1 96 gt WATCHDOG gt OSCILLATOR PCLK 400 kHz 5 CCU 002aad559 Fig 9 Block diagram of oscillator control 2 8 Clock source switching on the fly P89LPC9331 9341 9351 9361 can implement clock switching on any sources of watchdog oscillator 7 14 MHz IRC oscillator crystal oscillator and external clock input during code is running CLKOK bit in register CLKCON is read only and used to indicate the clock switch status When CLKOK is 0 clock switch is processing not completed When CLKOK is 1 clock switch is completed When start new clock source switch CLKOK is cleared automatically Notice that when CLKOK is 0 Writing to UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 32 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual register is not allowed During reset CLKCON registe
242. trigger inputs Port 1 also provides various special functions as described below P1 0 TXD 18 y o P1 0 Port 1 bit 0 TXD Transmitter output for serial port P1 1 RXD 17 y o P1 1 Port 1 bit 1 RXD Receiver input for serial port P1 2 TO SCL 12 P1 2 Port 1 bit 2 open drain when used as output TO Timer counter 0 external count input or overflow output open drain when used as output y o SCL 2 serial clock input output P1 3 INTO SDA 11 y o P1 3 Port 1 bit 3 open drain when used as output INTO External interrupt 0 input y o SDA I C bus serial data input output 1 1 10 1 4 Port 1 bit 4 High current source External interrupt 1 input P1 5 RST 6 P1 5 Port 1 bit 5 input only RST External Reset input during power on or if selected UCFG1 When functioning as a reset input a LOW on this pin resets the microcontroller causing I O ports and peripherals to take on their default states and the processor begins execution at address 0 Also used during a power on sequence to force ISP mode P1 6 OCB 5 y o P1 6 Port 1 bit 6 High current source O OCB Output Compare B P89LPC9351 9361 P1 7 OCC ADOO 4 y o P1 7 Port 1 bit 7 High current source O OCC Output Compare C P89LPC9351 9361 AD00 ADCO channel 0 analog input P2 0 to P2 7 y o Port 2 Port 2 is an 8 bit I O port with a user configurable output typ
243. trim value is initialized to a factory pre programmed value To guarantee the linearity of PGA output it is recommended not to change the trim registers Table 13 trim register Register bits Contains PGAXxTRIM2XAX 3 0 trim value for 2x gain value PGAxTRIM2X4X 7 4 trim value for 4x gain value PGAxTRIM8X16X 3 0 trim value for 8x gain value PGAxTRIM8X16X 7 4 trim value for 16x gain value Channel selection dependency In auto scan mode and fixed channel single conversion mode the PGA channel selection is dependent on the ADC channel selection which means the PGA channel selection is tracking ADC channel selection In other modes the PGA channel selection is independent and can be different from the ADC channel selection If different the gain of the selected ADC channel is 1 Table 14 channel selection ADC conversion mode PGA channel selection dependency Fixed channel continuous conversion mode PGA channel selection is independent to Dual channel continuous conversion mode ADC channel selection Single step mode Fixed channel single conversion mode the PGA channel selection is dependent on Auto Scan single continuous conversion mode the ADC channel selection Temperature sensor An on chip wide range temperature sensor is integrated with ADCO module It provides temperature sensing capability of 40 C 85 C To get an accurate temperature value it is necessary to get supply voltage by meas
244. ts external pins INTO INT1 brownout Interrupt keyboard Real time Clock System Timer watchdog and comparator trips Waking up by reset is only enabled if the corresponding reset is enabled and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit IENO 7 is set External interrupts should be programmed to level triggered mode to be used to exit Power down mode In Power down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled In Power down mode the power supply voltage may be reduced to the RAM keep alive voltage VRAM This retains the RAM contents at the point where Power down mode was entered SFR contents are not guaranteed after Vpp has been lowered to VRAM therefore it is recommended to wake up the processor via Reset in this situation Vpp must be raised to within the operating range before the Power down mode is exited When the processor wakes up from Power down mode it will start the oscillator immediately and begin execution when the oscillator is stable Oscillator stability is determined by counting 1024 CPU clocks after start up when one of the crystal oscillator configurations is used or 200ms to 300ms after start up for the internal RC or 32 OSCCLK cycles after start up for external clock input Some chip functions continue to operate and draw power during Power down mode increasing the total powe
245. ts reserved User manual Rev 4 1 20 August 2012 97 of 163 NXP Semiconductors U M1 0308 12 6 2 UM10308 P89LPC9331 9341 9351 9361 user manual The first byte transmitted contains the slave address of the receiving device 7 bits and the data direction bit In this case the data direction bit R W will be logic 0 indicating a write Data is transmitted 8 bits at a time After each byte is transmitted an acknowledge bit is received START and STOP conditions are output to indicate the beginning and the end of a serial transfer The I C bus will enter Master Transmitter Mode by setting the STA bit The 12C logic will send the START condition as soon as the bus is free After the START condition is transmitted the SI bit is set and the status code in I2STAT should be 08h This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT Data Register and data direction bit SLA W The SI bit must be cleared before the data transfer can continue When the slave address and R W bit have been transmitted and an acknowledgment bit has been received the SI bit is set again and the possible status codes are 18h 20h or 38h for the master mode or 68h 78h or OBOh if the slave mode was enabled setting AA Logic 1 The appropriate action to be taken for each of these status codes is shown in Table 102 am S ws 2 logic 0 write L data transferred
246. ues written are stored in two 8 bit shadow registers In order to latch the contents of the shadow registers into TOR2H and TOR2L the user must write a logic 1 to the CCU Timer Compare Overflow Update bit TCOU2 in CCU Timer Control Register 1 TCR21 The function of this bit All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 71 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual depends on whether the timer is running in PWM mode or in basic timer mode In basic timer mode writing a one to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as zero In PWM mode writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow As long as the latch is pending TCOU2 will read as one and will return to zero when the latching takes place TCOU2 also controls the latching of the Output Compare registers OCR2A OCR2B and OCR2C When writing to timer high byte TH2 the value written is stored in a shadow register When TL2 is written the contents of TH2 s shadow register is transferred to TH2 at the same time that TL2 gets updated Thus TH2 should be written prior to writing to TL2 If a write to TL2 is followed by another write to TL2 without TH2 being written in between the value of TH2 will be transferred directly
247. umber of I O pins available 51 Table 12 Oscillator type selection for clock switch 33 Table 42 Port output configuration settings 51 Table 13 PGA trim register 38 Table 43 Port output configuration 55 Table 14 PGA channel 38 Table 44 BOD Trip points configuration 56 Table 15 Input channels and result registers for fixed Table 45 BOD Reset and BOD Interrupt configuration 57 channel single auto scan single and auto scan Table 46 Power reduction modes 58 continuous conversion mode 39 Table 47 Power Control register PCON address 87h bit Table 16 Result registers and conversion results for fixed 59 channel continuous conversion mode 40 Table 48 Power Control register PCON address 87h bit Table 17 Result registers and conversion results for dual description 59 channel continuous conversion mode 40 Table 49 Power Control register A PCONA address B5h Table 18 Conversion mode bits 41 bit allocation 59 Table 19 A D Control register O ADCONO address 8Eh Table 50 Power Control register A PCONA address B5h bit 43 bit description 59 Table 20 A D Control register 0 ADCONO add
248. undary interrupt 0 When set will cause an interrupt if the boundary interrupt 0 flag BNDIO is set and the A D interrupt is enabled UM10308 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 43 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Table 21 A D Control register 1 ADCON1 address 97h bit allocation Bit 7 6 5 4 3 2 1 0 Symbol ENBI1 ENADCI1 1 EDGE1 ADCI1 ENADC1 ADCS11 ADCS10 Reset 0 0 0 0 0 0 0 0 Table 22 A D Control register 1 ADCON1 address 97h bit description Bit Symbol Description 1 0 ADCS11 ADCS10 A D start mode bits see below 00 Timer Trigger Mode when TMM1 1 Conversions starts on overflow of Timer 0 When 1 0 no start occurs stop mode 01 Immediate Start Mode Conversion starts immediately 10 Edge Trigger Mode Conversion starts when edge condition defined by bit EDGE 1 occurs 11 Dual Immediate Start Mode Both ADC s start a conversion immediately 2 ENADC1 Enable A D channel 1 When set 1 enables ADC1 Must also be set for D A operation of this channel 3 ADCI1 A D Conversion complete Interrupt 1 Set when any conversion or set of multiple conversions has completed Cleared by software 4 EDGE1 When 0 an Edge conversion start is triggered by a falling edge on P1 4 When 1 an Edge conversion start is triggered by a
249. ure Noise Filter ICNFx bit is set the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event The inputs are sampled every two CCLK periods regardless of the speed of the timer An event counter can be set to delay a capture by a number of capture events The three bits ICECx2 ICECx1 and ICECx0 the CCCRx register determine the number of edges the capture logic has to see before an input capture occurs When a capture event is detected the Timer Input Capture x x is A or B Interrupt Flag TICF2x TIFR2 1 or TIFR2 0 is set If EA and the Timer Input Capture x Enable bit TICIE2x TICR2 1 or TICR2 0 is set as well as the ECCU IEN1 4 bit is set the program counter will be vectored to the corresponding interrupt The interrupt flag must be cleared manually by writing a logic O to it When reading the input capture register ICRxL must be read first When ICRxL is read the contents of the capture register high byte are transferred to a shadow register When ICRXH is read the contents of the shadow register are read instead If a read from ICRxL is followed by another read from ICRxL without ICRxH being read in between the new value of the capture register high byte from the last ICRxL read will be in the shadow register Table 70 Event delay counter for input capture ICECx2 ICECx1 ICECxO Delay numbers of edges 0 0 0 0 0 0 1 1 0 1 0 2 0 1 1 3 1 0 0 4 1 0
250. ured to operate either as timers or event counters see Table 54 An option to automatically toggle the Tx pin upon timer overflow has been added In the Timer function the timer is incremented every PCLK In the Counter function the register is incremented in response to a 1 to 0 transition on its corresponding external input pin TO or T1 The external input is sampled once during every machine cycle When the pin is high during one cycle and low in the next cycle the count is incremented The new count value appears in the register during the cycle following the one in which the transition was detected Since it takes two machine cycles four CPU clocks to recognize a 1 to 0 transition the maximum count rate is 1 4 of the CPU clock frequency There are no restrictions on the duty cycle of the external input signal but to ensure that a given level is sampled at least once before it changes it should be held for at least one full machine cycle The Timer or Counter function is selected by control bits TnC T x 0 and 1 for Timers 0 and 1 respectively in the Special Function Register TMOD Timer 0 and Timer 1 have five operating modes modes 0 1 2 3 and 6 which are selected by bit pairs 1 TnMO in TMOD and TnM2 in TAMOD Modes 0 1 2 and 6 are the same for both Timers Counters Mode 3 is different The operating modes are described later in this section Table 53 Timer Counter Mode register TMOD a
251. uring the internal reference voltage V ef bg first Temperature sensor voltage can be calculated by the following formula Vsen senX Vrorpgy Aref bg 1 In formula 1 Aref pgy is the A D converting result of Vret og and Asen is the A D converting result of Ven Temperature Sensor transfer function can be shown in the following formula All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 38 of 163 NXP Semiconductors U M1 0308 UM10308 P89LPC9331 9341 9351 9361 user manual mx temp b where m 11 3 mV C b 890 mV 2 P89LPC9331 9341 Temperature Sensor usage steps Config TSEL1 and TSELO as 01 to choose internal reference voltage Using ADC to get converting result as Aret Config TSEL1 and TSELO as 10 to choose temperature sensor Using ADC to get converting result as Agen A WD gt Calculate Vsen with formula 1 Calculate Temperature with formula 2 P89LPC9351 9361 Temperature Sensor usage steps Setting PGASELO1 and PGASELOO bits to choose ADOS channel Config TSEL1 and TSELO as 01 to choose internal reference voltage Using ADC to get converting result as Aret Config TSEL1 and TSELO as 10 to choose temperature sensor Using ADC to get converting result as Agen Calculate Vsen with formula 1 NO of WD Calculate
252. ust 2012 128 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Watchdog oscillator MOV WFEED1 0A5H 2 N MOV WFEED2 05AH oscillator PRESCALER ma 11 interrupt A A A XTALWD wocon ari Tener J PRED were Fig 55 Watchdog Timer in Timer Mode WDTE 0 002aae094 16 5 Power down operation 16 6 The WDT oscillator and low speed crystal oscillator will continue to run in power down consuming approximately 50 pA as long as the WDT oscillator is selected as the clock source for the WDT Selecting PCLK as the WDT source will result in the WDT oscillator going into power down with the rest of the device see Section 16 3 Power down mode will also prevent PCLK from running and therefore the watchdog is effectively disabled Periodic wake up from power down without an external oscillator Without using an external oscillator source the power consumption required in order to have a periodic wake up is determined by the power consumption of the internal oscillator source used to produce the wake up The Real time clock running from the internal RC oscillator can be used The power consumption of this oscillator is approximately 300 uA Instead if the WDT is used to generate interrupts the current is reduced to approximately 50 uA Whenever the WDT underflows the device will wake up 17 Additional features
253. ut 4 DAC1 Digital to analog converter output 1 AD13 ADC1 channel 3 analog input P0 5 CMPREF 22 0 5 Port 0 bit 5 High current source KBIS CMPREF Comparator reference negative input KBI5 Keyboard input 5 P0 6 CMP1 KBI6 20 P0 6 Port 0 bit 6 High current source 1 Comparator 1 output KBI6 Keyboard input 6 P0 7 T1 KBI7 19 y o P0 7 Port 0 bit 7 High current source 1 Timer counter 1 external count input or overflow output KBI7 Keyboard input 7 UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 5 of 163 NXP Semiconductors UM10308 P89LPC9331 9341 9351 9361 user manual Table 2 Pin description continued Symbol Pin Type Description PLCC28 TSSOP28 P1 0 to P1 7 VO Port 1 Port 1 is an 8 bit I O port with a user configurable output type except for three pins as noted below During reset Port 1 latches are configured in the input only mode with the internal pull up disabled The operation of the configurable Port 1 pins as inputs and outputs depends upon the port configuration selected Each of the configurable port pins are programmed independently Refer to Section 5 1 Port configurations for details P1 2 to P1 3 are open drain when used as outputs P1 5 is input only All pins have Schmitt
254. ut is asynchronous to the CPU clock 3 CNn Comparator negative input select When logic 0 the comparator reference pin CMPREF is selected as the negative comparator input When logic 1 the internal comparator reference Vngr is selected as the negative comparator input 4 CPn Comparator positive input select When logic 0 CINnA is selected as the positive comparator input When logic 1 CINnB is selected as the positive comparator input 5 CEn Comparator enable When set the corresponding comparator function is enabled Comparator output is stable 10 microseconds after CEn is set 6 7 reserved All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 118 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual 0 4 CIN1A P0 3 CIN1B 1 P0 6 0 5 CMPREF Vref bg interrupt EC 0 2 CIN2A 0 1 CIN2B P0 0 002aae483 Fig 50 P89LPC9331 9341 comparator input and output connections CP1 0 4 CIN1A comparator 1 0 3 CO1 D 7 1 P0 6 P0 5 CMPREF 4 Vref bg change detect 0 2 2 P0 1 CIN2B CN1 2 interrupt change detect EC i E23 gt CMF2 comparator 2 EZ P0 0 2
255. when system power consumption is an issue To minimize power consumption the user can power down the comparators by disabling the comparators and setting PCONA 5 to logic 1 or simply putting the device in Total Power down mode All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 120 of 163 NXP Semiconductors UM10308 UM10308 14 6 P89LPC9331 9341 9351 9361 user manual CINnA CMPREF gt 002 618 000 CINnA Vngr 1 23 V 002aaa621 CPn OEn 2010 CINnB COn CMPREF 002aaa623 e CPn 100 CINnB 1 23 V 002aaa625 9 CPn 110 Fig 52 Comparator configurations CINnA COn CMPREF gt CME 002aaa620 b CPn CNn OEn 001 CINNA Vrek 123 V 002 622 d CNn OEn 0 1 1 CINnB COn CMPREF eM 002aaa624 f CPn OEn 10 1 CINnB gt 002 626 h CPn CNn OEn 1 1 1 Suppose 1 is disabled or gain 1 Comparators configuration example The code shown below is an example of initializing one comparator Comparator 1 is configured to use the CIN1A and CMPREF inputs outputs the comparator result to the 1 pin and generates an interrupt when the comparator output changes CMPINIT MOV ANL ORL MOV PTOAD 03
256. y instruction that reads or manipulates the DPH and DPL registers the upper and lower bytes of the current DPTR will be affected by the setting of DPS The MOVX instructions have limited application for the P89LPC9331 9341 9351 9361 since the part does not have an external data bus However they may be used to access Flash configuration information see Flash Configuration section or auxiliary data XDATA memory All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 4 1 20 August 2012 130 of 163 NXP Semiconductors U M1 0308 P89LPC9331 9341 9351 9361 user manual Bit 2 of AUXR1 is permanently wired as a logic 0 This is so that the DPS bit may be toggled thereby switching Data Pointers simply by incrementing the AUXR1 register without the possibility of inadvertently altering other bits in the register 18 Data EEPROM P89LPC9351 9361 UM10308 The P89LPC9331 9341 9351 9361 has 512 bytes of on chip Data EEPROM that can be used to save configuration parameters The Data EEPROM is SFR based byte readable byte writable and erasable via row fill and sector fill The user can read write and fill the memory via three SFRs and one interrupt Address Register DEEADR is used for address bits 7 to 0 bit 8 is in the DEECON register Control Register DEECON is used for address bit 8 setup operation mode and status flag bit see
257. y limits will again be compared after all 8 bits have been converted The boundary status register BNDSTAO flags the channels which caused a boundary interrupt DAC output to a port pin with high output impedance Each A D converter s DAC block can be output to a port pin In this mode the ADxDAT3 register is used to hold the value fed to the DAC After a value has been written to the DAC written to ADxDAT3 the DAC output will appear on the channel pin The DAC output is enabled by the ENDAC1 and ENDACO bits in the ADMODB register See Table 26 Clock divider The A D converter requires that its internal clock source be in the range of 320kHz to 8MHz to maintain accuracy A programmable clock divider that divides the clock from 1 to 8 is provided for this purpose See Table 26 pins used with ADC functions The analog input pins maybe be used as either digital I O or as inputs to A D through PGA and thus have a digital input and output function In order to give the best analog performance pins that are being used with the ADC should have their digital outputs and inputs disabled and have the 5V tolerance disconnected Digital outputs are disabled by putting the port pins into the input only mode as described in the Port Configurations section see Table 42 Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and its corresponding
258. ytes The slave returns an acknowledge bit after each received byte Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a repeated START condition Since a repeated START condition is also the beginning of the next serial transfer the 2 will not be released The P89LPC9331 9341 9351 9361 device provides a byte oriented 12C interface It has four operation modes Master Transmitter Mode Master Receiver Mode Slave Transmitter Mode and Slave Receiver Mode UM10308 All information provided in this document is subject to legal disclaimers NXP 2012 All rights reserved User manual Rev 4 1 20 August 2012 93 of 163 NXP Semiconductors U M1 0308 UM10308 12 1 12 2 P89LPC9331 9341 9351 9361 user manual Rp Rp 12C bus 1 3 80 P12 SCL OTHER DEVICE OTHER DEVICE P89LPC9331 9341 WITH I2C BUS WITH I2C BUS 9351 9361 INTERFACE INTERFACE 002aad731 Fig 35 I C bus configurati

UM10308 P89LPC9331/9341/9351/9361 user manual

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