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Cypress Semiconductor CYBL10162-56LQXI Datasheet

1. Acronym Description abus analog local bus ADC analog to digital converter AG analog global AHB AMBA advanced microcontroller bus archi tecture high performance bus an ARM data transfer bus ALU arithmetic logic unit AMUXBUS analog multiplexer bus API application programming interface APSR application program status register ARMS advanced RISC machine a CPU architecture ATM automatic thump mode BW bandwidth CAN Controller Area Network a communications protocol CMRR common mode rejection ratio CPU central processing unit CRC cyclic redundancy check an error checking protocol DAC digital to analog converter see also IDAC VDAC DFB digital filter block DIO digital input output GPIO with only digital capabilities no analog See GPIO DMIPS Dhrystone million instructions per second DMA direct memory access see also TD DNL differential nonlinearity see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read only memory EMI electromagnetic interference EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge Acronym Description ETM embedded trace macrocell FET field
2. CYPRESS PRELIMINARY Family Datasheet PERFORM Table 8 DC Specifications continued vu Details Spec ID Parameter Description Min Typ Max Units Conditions SID19 Ippo Execute from flash CPU at 24 MHz 7 1 mA T 25 C Vpp 3 3V SID20 Ipp40 Execute from flash CPU at 24 MHz mA T 40 C to 85 C SID21 Ipp41 Execute from flash CPU at 48 MHz 13 4 mA T 25 C Vpp 3 3V SID22 Ipp12 Execute from flash CPU at 48 MHz mA T 40 C to 85 C Sleep Mode Vpp 1 8 to 5 5 V SID23 Ipp13 IMO on mA T 25 C Vpp 3 3 V SYSCLK 3 MHz Sleep Mode Vpp and Vppg 1 9 to 5 5 V SID24 Ipp14 ECO on mA T 25 C Vpp 3 3 V SYSCLK 3 MHz Deep Sleep Mode Vpp 1 8 to 3 6 V SID25 Ipp45 WDT with WCO on 1 3 pA T 25 C Vpp 3 3V SID26 Ipp46 WDT with WCO on pA T 40 C to 85 C Deep Sleep Mode Vpp 3 6 to 5 5 V SID27 Ipp17 WDT with WCO on pA T 25 C Vpp 5V SID28 Ipp48 WDT with WCO on pA T 40 C to 85 C Deep Sleep Mode Vpp 1 71 to 1 89 V Regulator Bypassed SID29 Ipp49 WDT with WCO on pA T 225 C SID30 Ipp2o WDT with WCO on pA T 40 C to 85 C Hibernate Mode Vpp 1 8 to 3 6 V SID37 Ipp27 GPIO and reset active 150 nA T 25 C Vpp 3 3V SID38 Ipp28 GPIO and reset active nA T 40 C to 85 C Hibernate Mode Vpp 3 6 to 5 5 V SID39 Ipp29 GPIO and reset active
3. Hove z Details Spec ID Parameter Description Min Typ Max Units Conditions SID1 VDDD ABS Analog digital or radio supply 0 5 6 V Absolute max B relative to Vss Vssp E VssA SID2 Vccp ABS Direct digital core voltage input 0 5 1 95 V Absolute max i relative to Vssp SID3 VGPIO_ABS GPIO voltage 0 5 Vpp 0 5 V Absolute max SID4 IcPio ABS Maximum current per GPIO 25 25 mA Absolute max SID5 IGPIO_ injection GPIO injection current Max for Vy 0 5 0 5 mA Absolute max i gt Vppp and Min for Vij lt Vas current injected per pin BID57 ESD HBM Electrostatic discharge human body 2200 1 V model BID58 ESD CDM Electrostatic discharge charged 500 V device model BID61 LU Pin current for latch up 200 200 mA BLE Subsystem Table 7 BLE Subsystem ae 2 a Details Spec ID Parameter Description Min Typ Max Units Conditions RF Receiver Specifications SID340 RXS IDLE RX sensitivity with idle transmitter 89 dBm SID340A RXS IDLE RX sensitivity with idle transmitter 91 dBm Guaranteed by design excluding balun loss simulation SID341 RXS DIRTY RX sensitivity with dirty transmitter 87 70 dBm RF PHY Specification RCV LE CA 01 C SID342 RXS HIGHGAIN RX sensitivity in high gain mode 91 dBm with idle transmitter SID343 PRXMAX Maximum input power 10 1 dBm RF PHY Specification RCV LE CA 06 C SID344 CI1 Co channel interference 9 21 dB RF PHY Specification Wanted
4. The selection of peripheral functions for different GPIO pins is given in Table 4 Table 4 Port Pin Connections Digital HSIOM_PORT_SELx SELy x denotes port number and y denotes pin number Name Analog 0 8 9 10 14 15 GPIO Active 0 Active 1 Active 2 Deep Sleep 0 Deep Sleep 1 P0 0 GPIO TCPWMO P 3 SCB1 UART RX 1 SCB1 I2C SDA 1 SCB1 SPI MOSI 1 P0 1 GPIO TCPWMO N 3 SCB1 UART TX 1 SCB1 I2C SCL 1 SCB1 SPI MISO 1 P0 3 GPIO TCPWM1 N 3 SCB1 UART CTS 1 SCB1 SPI SCLK 1 P0 4 GPIO TCPWM1 P 0 SCBO UART RX 1 EXT CLK Oy SCBO I2C SDA 1 SCBO SPI MOSI 1 ECO OUT 0 P0 5 GPIO TCPWM1 N 0 SCBO UART TX 1 SCBO I2C SCL 1 SCBO SPI MISO 1 Document Number 001 90478 Rev G Page 11 of 41 PRoC BLE CYBL10X6X WE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 4 Port Pin Connections continued Digital HSIOM PORT SELx SELy x denotes port number and y denotes pin number Name Analog 0 8 9 10 14 15 GPIO Active 0 Active 1 Active 2 Deep Sleep 0 Deep Sleep 1 P0 6 GPIO TCPWM2 P 0 SCBO UART RTS 1 SWDIO 0 SCBO SPI SSO 1 P0 7 GPIO TCPWM2 N 0 SCBO UART CTS 1 SWDCLK O0 SCBO SPI SCLK 1 P1 0 GPIO TCPWMO P 1 WCO OUT 2 P1 1 GPIO TCPWMO N 1 SCB1 SPI SS1 P1 2 GPIO TCPWM1_P 1 SCB1_SPI_SS2 P1 3 GPIO TCPWM1 N 1 SCB1 SPI SS3
5. m nA T 25 C Vpp 5V SID40 Ipp3o GPIO and reset active E nA T 40 C to 85 C Hibernate Mode Vpp 1 71 to 1 89 V Regulator Bypassed SID41 Ippa1 GPIO and reset active nA T 25 C SID42 Ipp32 GPIO and reset active a nA T 40 C to 85 C Stop Mode Vp 1 8 to 3 6 V SID43 Ipp33 Stop mode current Vpp 20 nA T 25 C Vpp 3 3V SID44 Ipp34 Stop mode current Vppg 40 nA T 25 C VbpR 3 3V SID45 Ipp35 Stop mode current Vpp nA T 40 C to 85 C SID46 Ippae Stop mode current Vppg nA T 40 C to 85 C VDDR 1 9Vto3 6V Document Number 001 90478 Rev G Page 20 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Table 8 DC Specifications continued Spec ID Parameter Description Min Typ Max Units aoe Stop Mode Vpp 3 6 to 5 5 V SID47 Ippa7 Stop mode current Vpp nA T 25 C Vpp 5 V SID48 Ipp38 Stop mode current Vppg nA T 25 C VppR 5V SID49 Ippao Stop mode current Vpp nA T 40 C to 85 C SID50 Ipp40 Stop mode current Vppg x nA T 40 C to 85 C Stop Mode Vpp 1 71 to 1 89 V Regulator Bypassed SID51 Ipp41 Stop mode current Vpp nA T 25 C SID52 Ipp42 Stop mode current Vpp 7 nA T 40 C to 85 C Table 9 AC Spec
6. mA SID376A ITX RF OdBm TX current at 0 dBm setting PA7 15 6 mA Measured at Vopr SID376B ITX RF OdBm TX current at 0 dBm excluding 14 2 mA Guaranteed by design Balun loss simulation SID377 ITX 3 dBm TX current at 3 dBm setting PA4 15 5 mA SID378 ITX 6 dBm TX current at 6 dBm setting PA3 14 5 mA SID379 ITX 12 dBm TX current at 12 dBm setting 13 2 mA PA2 SID380 ITX 18 dBm TX current at 18 dBm setting 12 5 mA PA1 SID380A lavg_1sec OdBm Average current at 1 second BLE 18 9 pA TXP 0 dBm 20 ppm connection interval master and slave clock accuracy For empty PDU exchange Document Number 001 90478 Rev G Page 18 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Table 7 BLE Subsystem continued Spec ID Parameter Description Min Typ Max Units C DE SID380B lavg 4sec OdBm Average current at 4 second BLE 6 25 pA TXP 0 dBm 20 ppm connection interval master and slave clock accuracy For empty PDU exchange General RF Specification SID381 FREQ RF operating frequency 2400 2482 MHz SID382 CHBW Channel spacing 2 MHz SID383 DR On air data rate 1000 kbps SID384 IDLE2TX BLE Radio Idle to BLE Radio TX 120 140 HS transition time SID385 IDLE2RX BLE Radio Idle to BLE Radio RX 75 120 us transition time RSSI Specification SID386 RSSI
7. 48 MHz SID215 TPWMPWINT Pulse width internal 2 Tok ns SID216 TPWMEXT Pulse width external 2 x Tok ns SID217 TPWMKILLINT Kill pulse width internal 2 x Tok ns SID218 TpwMKILLEXT Kill pulse width external 2x Tok ns SID219 TPWMEINT Enable pulse width internal 2 Tok ns SID220 TPWMENEXT Enable pulse width external 2 Tok ns SID221 TpwMREswiNT Reset pulse width internal 2 Tek ns SID222 Tpwmreswext Reset pulse width external 2 x Tok ns Fc Table 26 IC DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID223 li2c1 Block current consumption at 100 kHz 50 pA SID224 lice Block current consumption at 400 kHz 155 pA SID225 li2c3 Block current consumption at 1 Mbps 390 pA SID226 li2c4 C enabled in Deep Sleep mode 1 4 pA Table 27 Fixed I C AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID227 Fioc4 Bit rate 1 Mbps LCD Direct Drive Table 28 LCD Direct Drive DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID228 li cpLow Operating current in low power mode 17 5 HA 16 x 4 small segment display at 50 Hz SID229 Ci cDCAP LCD capacitance per segment common 500 5000 pF driver SID230 LCDorrsET Long term segment offset B 20 mV SID231 li cboP1 LCD system operating c
8. pA range Document Number 001 90478 Rev G Page 25 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Digital Peripherals 4x TCPWM Table 20 Timer DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID189 lTiM1 Block current consumption at 3 MHz 42 pA 16 bit timer SID190 IriM2 Block current consumption at 12 MHz 130 pA 16 bit timer SID191 Iri M3 Block current consumption at 48 MHz 535 pA 16 bit timer Table 21 Timer AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID192 TTIMFREQ Operating frequency Feik 48 MHz SID193 TCAPWINT Capture pulse width internal 2x Toi Kk ns SID194 TCAPWEXT Capture pulse width external 2 Tek ns SID195 TTIMRES Timer resolution TeLk ns SID196 TTENWIDINT Enable pulse width internal 2 Tok ns SID197 TTENWIDEXT Enable pulse width external 2x Toi Kk ns SID198 Trimreswint Reset pulse width internal 2 Tok ns SID199 TTIMRESEXT Reset pulse width external 2x Toi Kk ns Counter Table 22 Counter DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID200 leTrR4 Block current consumption at 3 MHz B 42 pA 16 bit Counter
9. which reduces the data interchange by reading and writing an array of memory Refer to Table 4 on page 11 for the possible SPI connections to the GPIOs Inter IC Sound Bus S Inter IC Sound Bus I S is a serial bus interface standard used for connecting digital audio devices The specification is from Philips Semiconductor 12 S bus specification February 1986 revised June 5 1996 s operates only in the Master mode supporting the transmitter TX and the receiver RX which have independent data byte streams These byte streams are packed with the most signif icant byte first The number of bytes used for each sample a sample for the left or right channel is the minimum number of bytes to hold a sample LCD The LCD controller can drive up to four commons and up to 32 segments It uses full digital methods to drive the LCD segments providing ultra low power consumption The two methods used are referred to as digital correlation and PWM The digital correlation method modulates the frequency and signal levels of the commons and segments to generate the highest RMS voltage across a segment to light it up or to maintain the RMS signal as zero This method is good for STN displays but may result in reduced contrast in TN cheaper displays The PWM method drives the panel with PWM signals to effec tively use the capacitance of the panel to provide the integration of the modulated pulse width to generate the desired LCD vol
10. setting PA1 SID362 F2AVG Average frequency deviation for 185 kHz RF PHY Specification 10101010 pattern TRM LE CA 05 C SID363 F1AVG Average frequency deviation for 225 250 275 kHz RF PHY Specification 11110000 pattern TRM LE CA 05 C SID364 EO Eye opening AF2AVG AF1AVG 0 8 RF PHY Specification TRM LE CA 05 C SID365 FTX ACC Frequency accuracy 150 150 kHz RF PHY Specification TRM LE CA 06 C SID366 FTX MAXDR Maximum frequency drift 50 50 kHz RF PHY Specification TRM LE CA 06 C SID367 FTX INITDR Initial frequency drift 20 20 kHz RF PHY Specification TRM LE CA 06 C SID368 FTX DR Maximum drift rate 20 20 kHz RF PHY Specification 50 us TRM LE CA 06 C SID369 IBSE1 In band spurious emission at 20 dBm RF PHY Specification 2 MHz offset TRM LE CA 03 C SID370 IBSE2 In band spurious emission at 30 dBm RF PHY Specification 23 MHz offset TRM LE CA 03 C SID371 TXSE1 Transmitter spurious emissions 55 5 dBm FCC 15 247 average 1 0 GHz SID372 TXSE2 Transmitter spurious emissions 41 5 dBm FCC 15 247 average gt 1 0 GHz RF Current Specification SID373 IRX Receive current in normal mode 18 7 mA SID373A IRX RF Receive current in normal mode 16 4 mA Measured at Vopr SID374 IRX HIGHGAIN Receive current in high gain mode 21 5 mA SID375 ITX 3 dBm TX current at 3 dBm setting PA10 20 mA SID376 ITX 0 dBm TX current at 0 dBm setting PA7 16 5
11. Conditions SID240 Fspi SPI operating frequency master 6x 8 MHz oversampling Table 34 Fixed SPI Master Mode AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID241 Tpmo MOSI valid after SCLK driving edge 18 ns SID242 Tpsi MISO valid before SCLK capturing 20 ns Full clock late MISO edge Full clock late MISO sampling sampling used SID243 Tumo Previous MOSI data hold time 0 ns Referred to Slave capturing edge Table 35 Fixed SPI Slave Mode AC Specifications Spec ID Parameter Description Min Typ Max Units SID244 TDMI MOSI valid before SCLK capturing 40 m ns edge SID245 Tpso MISO valid after SCLK driving edge 42 3 x Tscp ns SID246 Tpso ex MISO Valid after SCLK driving edge in 50 ns external clock mode Vpp lt 3 0 V SID247 Tuso Previous MISO data hold time 0 ns SID248 TssELsCK SSEL valid to first SCK valid edge 100 ns Document Number 001 90478 Rev G Page 28 of 41 PRoC BLE CYBL10X6X DJ CYPRESS PRELIMINARY Family Datasheet PERFORM Memory Table 36 Flash DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID249 VpE Erase and program voltage 1 71 5 5 V SID309 Twsas Number of Wait states at 2 CPU execution from 32 48 MHz flash SID310 Tws3
12. Datasheet PERFORM Table 10 GPIO DC Specifications continued Spec ID Parameter Description Min Typ Max Units C Dee SID68 VoL Output voltage LOW level 0 4 V loi 3 mA at 3 3 V VDD SID69 RpPuLLUP Pull up resistor 3 5 5 6 8 5 kQ SID70 RPULLDOWN Pull down resistor 3 5 5 6 8 5 kQ SID71 lu Input leakage current absolute value 2 nA 25 C Vpp 3 3V SID72 liL CTBM Input leakage on CTBm input pins 4 nA SID73 CiN Input capacitance 7 pF SID74 VHYSTTL Input hysteresis LVTTL 25 40 mV Vpp gt 2 7 V SID75 Vuyscmos Input hysteresis CMOS 0 05 x E mV Vpp SID76 IDIODE Current through protection diode to 100 pA Vpp Vss SID77 lor GPIO Maximum total source or sink chip z 200 mA B current Table 11 GPIO AC Specifications Spec ID Parameter Description Min Typ Max Units C Pelee SID78 TRISEF Rise time in Fast Strong mode 2 12 ns 3 3 V Vppp Cioap 25 pF SID79 TFALLF Fall time in Fast Strong mode 2 12 ns 3 3 V Vppp CioAp 25 pF SID80 TRISES Rise time in Slow Strong mode 10 60 ns 3 3 V Vppp CioAp 25 pF SID81 TEALLS Fall time in Slow Strong mode 10 60 ns 3 3 V Vppp CioAp 25 pF SID82 Fepiout1 GPIO Fout 3 3 V lt Vpp x 5 5 V 33 MHz 90 1096 25 pF load Fast Strong mode 60 40 duty cycle SID83 Fepiout2 GPIO Fout 1 7 Vx Vpp x 3 3 V 16 7 MHz 90 10 25 pF load Fast Strong mode 60 40 duty cycle SID84 F GPIOUT3 GPIO Fout 3 3 V lt Vpp lt 5 5 V 7 MHz 90 1096 25 pF load Slow Strong mode 60 40 d
13. L i PRoC BLE 56 OF N VDDR Document Number 001 90478 Rev G amp T Page 14 of 41 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Development Support The CYBL10X6X family has a rich set of documentation devel opment tools and online resources to assist you during your development process Visit www cypress com procble to find out more Documentation A suite of documentation supports the CYBL10X6X family to ensure that you find answers to your questions quickly This section contains a list of some of the key documents Component Datasheets PSoC Creator Components provide hardware abstraction using APIs to configure and control peripheral activity The Component datasheet covers Component features its usage and operation details API description and electrical specifications This is the primary documentation used during development These Components can represent peripherals on the device such as a timer I C or UART or high level system functions such as the BLE Component Application Notes Application notes help you to understand how to use various device features They also provide guidance on how to solve a variety of system design challenges Document Number 001 90478 Rev G Technical Reference Manual TRM The TRM describes all peripheral functionality in detail with register level descriptions This document is divided into two parts the Architecture TRM
14. P1 4 GPIO TCPWM2 P 1 SCBO_UART_RX 0 SCBO I2C SDA 0 SCBO SPI MOSI 1 P1 5 GPIO TCPWM2 N 1 SCBO UART TX 0 SCBO I2C SCL 0 SCBO SPI MISO 1 P1 6 GPIO TCPWMS3 P 1 SCBO UART RTS 0 SCBO SPI SSO 1 P1 7 GPIO TCPWMS3 N 1 SCBO_UART_CTS 0 SCBO SPI SCLK 1 P2 0 GPIO SCBO SPI SS1 P2 1 GPIO SCBO SPI SS2 P2 2 GPIO WAKEUP SCBO SPI SS3 P2 3 GPIO WCO_OUT 1 P2 4 GPIO P2 5 GPIO P2 6 GPIO P2 7 GPIO EXT CLK 1 ECO OUT 1 P3 0 SARMUX 0 GPIO TCPWMO P 2 SCBO UART RX 2 SCBO I2C SDA 2 P3 1 SARMUX 1 GPIO TCPWMO N 2 SCBO UART TX 2 SCBO I2C SCL 2 P3 2 SARMUX 2 GPIO TCPWM1 P 2 SCBO UART RTS 2 P3 3 SARMUX 3 GPIO TCPWM1 N 2 SCBO UART CTSI 2 P3 4 SARMUX 4 GPIO TCPWM2 P 2 SCB1 UART RX 2 SCB1 I2C SDA 2 P3 5 SARMUX 5 GPIO TCPWM2 N 2 SCB1 UART TX 2 SCB1 I2C SCL 2 P3 6 SARMUX 6 GPIO TCPWM3 P 2 SCB1 UART RTS 2 P3 7 SARMUX 7 GPIO TCPWMS3 N 2 SCB1 UART CTS 2 WCO OUT 0 P4 0 CMOD GPIO TCPWMO PI 0 SCB1 UART RTS 0 SCB1 SPI MOSI 0 P4 1 CTANK GPIO TCPWMO N 0 SCB1 UART CTS 0 SCB1 SPI MISO 0 P5 0 GPIO TCPWM3_P 0 SCB1 UART RX 0 EXTPA EN SCB1 I2C SDA 0 SCB1 SPI SSO 0 P5 1 GPIO TCPWMS3 N 0 SCB1 UART TX 0 EXT CLK 2 SCB1 I2C SCL 0 SCB1 SPI SCLK O0 ECO OUT 2 P6 0 XTAL320 GPIO P6 1 XTAL32I GPIO Document Number 001 90478 Rev G Page 12 of 41 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Power PRoC BLE can be supplied from batteries
15. SID201 IcrR2 Block current consumption at 12 MHz 7 x 130 pA 16 bit Counter SID202 loTR3 Block current consumption at 48 MHz 535 pA 16 bit Counter Table 23 Counter AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID203 TerRFREQ Operating frequency Feik 48 MHz SID204 TerRPwiNT Capture pulse width internal 2x Tok ns SID205 TerRPwExr Capture pulse width external 2 Tok ns SID206 TcTRES Counter resolution Tek ns SID207 Tcenwipint Enable pulse width internal 2x Tek ns SID208 Tcenwipext Enable pulse width external 2x Tok ns SID209 TerRRESWINT Reset pulse width internal 2 Tok ns SID210 TergnEswExrT Reset pulse width external 2x Tek ns Pulse Width Modulation PWM Table 24 PWM DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID211 IpwMt1 Block current consumption at 3 MHz 42 pA 16 bit PWM SID212 lpwme2 Block current consumption at 12 MHz 130 HA 16 bit PWM SID213 IpPwM3 Block current consumption at 48 MHz 535 pA 16 bit PWM Document Number 001 90478 Rev G Page 26 of 41 mE E PRoC BLE CYBL10X6X WE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 25 PWM AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID214 TPWMFREQ Operating frequency Fork
16. When SCB1 is used SDA and SCL can be connected to P0 0 and P0 1 or P3 4 and P3 5 or P5 0 and P5 1 Document Number 001 90478 Rev G PRELIMINARY PRoC BLE CYBL10X6X Family Datasheet Configurations for lC are as follows m SCB1 is fully compliant with the Standard mode 100 KHz Fast mode 400 kHz and Fast Mode Plus 1 MHz 2c signaling specifications when routed to GPIQ pins P5 0 and P5 1 except for hot swap capability during I C active commu nication m SCB1 is compliant only with Standard mode 100 kHz when not used with P5 0 and P5 1 m SCBO is compliant with Standard mode 100 kHz only UART mode This is a full feature UART operating up to 1 Mbps It supports automotive single wire interface LIN infrared interface IrDA and SmartCard 1807816 protocols In addition it supports the 9 bit multiprocessor mode which allows addressing of peripherals connected over common RX and TX lines The UART hardware flow control is supported to allow slow and fast devices to communicate with each other over UART without the risk of losing data Refer to Table 4 on page 11 for possible UART connections to the GPIOs SPI Mode The SPI mode supports full Motorola amp SPI Texas Instruments amp Secure Simple Pairing SSP essentially adds a start pulse used to synchronize SPI Codecs and National Microwire half duplex form of SPI The SPI function is imple mented using the Cypress provided software Component EzSPI
17. and RCV LE CA 04 C Interferer at F 2 003 2 399 MHz SID352 OBB3 Out of band blocking 35 27 dBm RF PHY Specification Wanted signal at 67 dBm and RCV LE CA 04 C Interferer at F 2 484 2 997 MHz SID353 OBB4 Out of band blocking 30 27 dBm RF PHY Specification Wanted signal a 67 dBm and Inter RCV LE CA 04 C ferer at F 3 000 12 750 MHz SID354 IMD Intermodulation performance 50 dBm RF PHY Specification Wanted signal at 64 dBm and RCV LE CA 05 C 1 Mbps BLE third fourth and fifth offset channel SID355 RXSE1 Receiver spurious emission 57 dBm 100 kHz 30 MHz to 1 0 GHz measurement bandwidth ETSI EN300 328 V1 8 1 SID356 RXSE2 Receiver spurious emission 47 dBm 1 MHz measurement 1 0 GHz to 12 75 GHz bandwidth ETSI EN300 328 V1 8 1 RF Transmitter Specifications SID357 TXP ACC RF power accuracy 4 dB SID358 TXP RANGE RF power control range 20 dB SID359 TXP 0 dBm Output power 0 dB gain setting 4 0 3 dBm PA7 Document Number 001 90478 Rev G Page 17 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Table 7 BLE Subsystem continued I Details Spec ID Parameter Description Min Typ Max Units Conditions SID360 TXP MAX Output power maximum power 1 3 6 dBm setting PA10 SID361 TXP MIN Output power minimum power 18 dBm
18. and the Register TRM Online In addition to the print documentation Cypress forums connect you with fellow users and experts from around the world 24 hours a day 7 days a week Tools With industry standard cores programming and debugging interfaces the CYBL10X6X family is part of a development tool ecosystem Visit us at www cypress com go psoccreator for the latest infor mation on the revolutionary easy to use PSoC Creator IDE supported third party compilers programmers and debuggers Kits Cypress provides a portfolio of kits to accelerate time to market Visit us at www cypress com procble Page 15 of 41 PERFORM Electrical Specifications This section provides detailed electrical characteristics Absolute maximum rating for the CYBL10X6X devices is listed in the following table Usage above the absolute maximum conditions may cause permanent damage to the device Absolute Maximum Ratings PRELIMINARY PRoC BLE CYBL10X6X Family Datasheet Exposure to absolute maximum conditions for extended periods of time may affect device reliability The maximum storage temperature is 150 C in compliance with JEDEC Standard JESD22 A103 High Temperature Storage Life When used below absolute maximum conditions but above normal operating conditions the device may not operate to the specification Table 6 Absolute Maximum Ratings
19. device when the supply voltage is too low for proper device operation The LVD circuit generates an interrupt if the supply voltage drops below a user selectable level Page 4 of 41 PERFORM An external active LOW reset pin XRES can be used to reset the device The XRES pin has an internal pull up resistor and in most applications does not require any additional pull up resistors The power system is described in detail in the Power section on page 13 Clock Control The PRoC BLE clock control is responsible for providing clocks to all subsystems and also for switching between different clock sources without glitching The clock control for PRoC BLE consists of the IMO and the internal low speed oscillator ILO It uses the 24 MHz external crystal oscillator ECO and the 32 kHz WCO In addition an external clock may be supplied from a pin The device has 12 dividers with 16 divider outputs Two dividers have additional fractional division capability The HFCLK signal is divided down as shown in Figure 2 to generate the system clock SYSCLK and peripheral clock PERx CLK for different peripherals The system clock SYSCLK driving buses registers and the processor must be higher than all the other clocks in the system that are divided off HFCLK The ECO and WCO are present in the BLE subsystem and the clock outputs are routed to the system resources Internal Main Oscillator IMO The IMO is the primary system clock sour
20. effect transistor FIR finite impulse response see also IIR FPB flash patch and breakpoint FS full speed GPIO general purpose input output applies to a PSoC pin HCI host controller interface HVI high voltage interrupt see also LVI LVD IC integrated circuit IDAC current DAC see also DAC VDAC IDE integrated development environment C or IIC Inter Integrated Circuit a communications protocol S Inter IC Sound IIR infinite impulse response see also FIR ILO internal low speed oscillator see also IMO IMO internal main oscillator see also ILO INL integral nonlinearity see also DNL I O input output see also GPIO DIO SIO USBIO IPOR initial power on reset IPSR interrupt program status register IRQ interrupt request ITM instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network a communications protocol LR link register LUT lookup table LVD low voltage detect see also LVI LVI low voltage interrupt see also HVI LVTTL low voltage transistor transistor logic MAC multiply accumulate MCU microcontroller unit MISO master in slave out NC no connect NMI nonmaskable interrupt NRZ non return to zero NVIC nested vectored interrupt controller Document Number 001 90478 Rev G Page 37 of 41 PERFORM Table 56 Acronyms Used in This Document continued PRELIMINARY PRoC BLE CYBL10X6X Family Datasheet Table 56 Acronyms Used in This Document c
21. signal at 67 dBm and RCV LE CA 03 C Interferer at Frx Note 2 This does not apply to the RF pins ANT XTALI and XTALO RF pins ANT XTALI and XTALO are tested for 500 V HBM Document Number 001 90478 Rev G Page 16 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Table 7 BLE Subsystem continued Spec ID Parameter Description Min Typ Max Units C D SID345 CI2 Adjacent channel interference 3 15 dB RF PHY Specification Wanted signal at 67 dBm and RCV LE CA 03 C Interferer at FRX x1 MHz SID346 CI3 Adjacent channel interference 29 dB RF PHY Specification Wanted signal at 67 dBm and RCV LE CA 03 C Interferer at FRx 2 MHz SID347 Cl4 Adjacent channel interference 39 dB RF PHY Specification Wanted signal at 67 dBm and RCV LE CA 03 C Interferer at ZFgx 3 MHz SID348 CI5 Adjacent channel interference 20 dB RF PHY Specification Wanted Signal at 67 dBm and RCV LE CA 03 C Interferer at Image frequency Fimace SID349 CI3 Adjacent channel interference 30 dB RF PHY Specification Wanted signal at 67 dBm and RCV LE CA 03 C Interferer at Image frequency Fimace 1 MHz SID350 OBB1 Out of band blocking 30 27 dBm RF PHY Specification Wanted signal at 67 dBm and RCV LE CA 04 C Interferer at F 30 2000 MHz SID351 OBB2 Out of band blocking 35 27 dBm RF PHY Specification Wanted signal at 67 dBm
22. 1 GPIO Port 5 Pin 1 analog digital Icd csd 9 VSSD GROUND Digital ground 10 VDDR POWER 1 9 V to 5 5 V radio supply 11 GANT1 GROUND Antenna shielding ground 12 ANT ANTENNA Antenna pin 13 GANT2 GROUND Antenna shielding ground 14 VDDR POWER 1 9 V to 5 5 V radio supply 15 VDDR POWER 1 9 V to 5 5 V radio supply 16 XTAL24I CLOCK 24 MHz crystal or external clock input 17 XTAL240 CLOCK 24 MHz crystal 18 VDDR POWER 1 9 V to 5 5 V radio supply 19 P0 0 GPIO Port 0 Pin 0 analog digital Icd csd 20 PO 1 GPIO Port 0 Pin 1 analog digital Icd csd 21 P0 2 GPIO Port 0 Pin 2 analog digital Icd csd 22 P0 3 GPIO Port 0 Pin 3 analog digital Icd csd 23 VDDD POWER 1 7 1 V to 5 5 V digital supply 24 P0 4 GPIO Port 0 Pin 4 analog digital Icd csd 25 P0 5 GPIO Port 0 Pin 5 analog digital Icd csd 26 P0 6 GPIO Port 0 Pin 6 analog digital Icd csd 27 P0 7 GPIO Port 0 Pin 7 analog digital Icd csd 28 P1 0 GPIO Port 1 Pin 0 analog digital Icd csd 29 P1 1 GPIO Port 1 Pin 1 analog digital Icd csd 30 P1 2 GPIO Port 1 Pin 2 analog digital Icd csd 31 P1 3 GPIO Port 1 Pin 3 analog digital Icd csd 32 P1 4 GPIO Port 1 Pin 4 analog digital Icd csd 33 P1 5 GPIO Port 1 Pin 5 analog digital Icd csd 34 P1 6 GPIO Port 1 Pin 6 analog digital Icd csd 35 P1 7 GPIO Port 1 Pin 7 analog digital Icd csd 36 VDDA POWER 1 71 V to 5 5 V analog supply 37 P2 0 GPIO Port 2 Pin 0 analog digital Icd csd 38 P2 1 GPIO Port 2 Pin 1 analog digital Icd csd 39 P2 2 GPIO Port 2 Pin 2 analog digita
23. 2 Number of Wait states at 1 CPU execution from 16 32 MHz flash SID311 Tws16 Number of Wait states for 0 CPU execution from 0 16 MHz flash Table 37 Flash AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID250 TRowwritel Row block write time erase and n B 20 ms Row block 128 bytes program SID251 TROWERASE Row erase time 13 ms SID252 TRONPROGRAM I Row program time after erase 7 ms SID253 TBULKERASEHI Bulk erase time 128 KB zx 35 ms SID254 Tpevprog Total device program time 25 seconds SID255 FEND Flash endurance 100 K cycles SID256 FRET Flash retention Ta lt 55 C 100K 20 years P E cycles SID257 FnET2 Flash retention Ta x 85 C 10K 10 years P E cycles System Resources Power on Reset POR Table 38 POR DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID258 VRisEIPOR Rising trip voltage 0 80 1 45 V SID259 VEALLIPOR Falling trip voltage 0 75 1 40 V SID260 ViPORHYST Hysteresis 15 200 mV Table 39 POR AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID264 TPPOR TR Precision power on reset PPOR 1 Hs response time in Active and Sleep modes Note 4 Itcan take as much as 20 ms to write to flash During this time the device should not be reset or flash operations will be interrupted and cannot be relied on to have completed Reset sources include the XRES pin softwar
24. 3 V 16 MHz 90 1096 25 pF Fast Strong mode load 60 40 duty cycle XRES Table 14 XRES DC Specifications i 5 Details Spec ID Parameter Description Min Typ Max Units Conditions SID87 Vin Input voltage HIGH threshold 0 7 x V CMOS input VDDD SID88 Vi Input voltage LOW threshold 0 3 x Vppp V CMOS input SID89 ReuLLuP Pull up resistor 3 5 5 6 8 5 kQ SID90 Cin Input capacitance 3 pF SID91 VuvsxRES Input voltage hysteresis 100 mV SID92 IDIODE Current through protection diode to x 100 pA Vpp Vss Table 15 XRES AC Specifications SUE 3 Details Spec ID Parameter Description Min Typ Max Units Conditions SID93 TRESETWIDTH Reset pulse width 1 uS Document Number 001 90478 Rev G Page 23 of 41 PERFORM Analog Peripherals Temperature Sensor PRELIMINARY Table 16 Temperature Sensor Specifications PRoC BLE CYBL10X6X Family Datasheet Spec ID Parameter Description Min Typ Max Units Details Conditions SID155 TsENSACC Temperature sensor accuracy 5 1 5 C 40 to 85 C SAR ADC Table 17 SAR ADC DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID156 A RES Resolution 12 bits SID157 A CHNIS S Number of channels single ended 8 8 full speed SID158 A CHNKS D Number of channels differentia
25. 6 pin QFN 7 mm x 7 mm and 68 ball WLCSP 3 52 mm x 3 91 mm packages PSoC Creator Design Environment m Easy to use IDE to configure develop program and test a BLE application m Option to export the design to Keil IAR or Eclipse Bluetooth Low Energy Protocol Stack m Bluetooth Low Energy protocol stack supporting generic access profile GAP Central Peripheral Observer or Broad caster roles a Switches between Central and Peripheral roles on the go Standard Bluetooth Low Energy profiles and services for interoperability a Custom profile and service for specific use cases San Jose CA 95134 1709 408 943 2600 Revised December 19 2014 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet Contents Blocks and Functionality sees 3 CPU S bSysSteim i225 nct rir tette ree 4 BLE SUBSYSTEM i iure ritardi ER 4 System Resources Subsystem crcr 4 Peripheral Blocks 0c ccssccceseosectsnsseececneessbennencetee 5 Dd Lir c 8 hio 13 Low Power Modes esseee 13 Development Support eene 15 Documentation ssssse en 15 eun mE 15 Iso cm Q 15 dp 15 Electrical Specifications eee 16 Absolute Maximum Ratings ineen 16 BLE SUbSyStetri iauna entiteiten 16 Device Level Specifications ssss
26. 67 V SID275 Vivid LVI A D SEL 83 0 1010b 2 63 2 70 2 77 V SID276 VLvI12 LVI A D SEL 3 0 1011b 2 73 2 80 2 87 V SID277 Viya43 LVI A D SEL 3 0 1100b 2 83 2 90 2 97 V SID278 VLy114 LVI A D SEL 3 0 1101b 2 93 3 00 3 08 V SID279 Vivits LVI_A D_SEL 3 0 1110b 3 12 3 20 3 28 V SID280 Vivit6 LVI A D SEL 3 0 1111b 4 39 4 50 4 61 V SID281 LVI IDD Block current 100 pA Table 43 Voltage Monitor AC Specifications Spec ID Parameter Description Min Typ Max Units C rode E SID282 TMONTRIP Voltage monitor trip time 1 Hs Document Number 001 90478 Rev G Page 30 of 41 mE E PRoC BLE CYBL10X6X WE CYPRESS PRELIMINARY Family Datasheet PERFORM SWD Interface Table 44 SWD Interface Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID283 F SWDCLK1 3 3V lt Vpp lt 5 5 V 14 MHz SWDCLK s 1 3 CPU clock frequency SID284 F SWDCLK2 1 71 V lt Vpp lt 3 3 V 7 MHz SWDCLK s 1 3 CPU clock frequency SID285 T SWDI SETUP T 1 f SWDCLK 0 25 x T ns SID286 T SWDI HOLD T 1 f SWDCLK 0 25 x T ns SID287 T SWDO VALID T 1 f SWDCLK 0 5 T ns SID288 T SWDO HOLD T 1 f SWDCLK 1 ns Internal Main Oscillator Table 45 IMO DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID289 limot IMO operating current at 48 MHz 1000 pA S
27. ACC RSSI accuracy 5 dB SID387 RSSI RES RSSI resolution 1 dB SID388 RSSI PER RSSI sample period 6 us Device Level Specifications All specifications are valid for C40 C lt TA lt 85 C and TJ x 100 C except where noted Specifications are valid for 1 71 V to 5 5 V except where noted Table 8 DC Specifications Spec ID Parameter Description Min Typ Max Units C Des S SID6 Vbo eee input voltage VppA 18 z 55 y With regulator enabled ppp Vpp SID7 Vpb E ae Vinee al 1 71 1 8 1 89 V Md unregulated SID8 VDDR Radio supply voltage Radio on 1 9 5 5 V SID8A VDDR Radio supply voltage Radio off 1 71 5 5 V SID9 Weed e M output voltage for _ 18 V SID10 Buca Sie output bypass 1 1 3 16 uF X5R ceramic or better Active Mode Vpp 1 71 V to 5 5 V SID13 em Execute from flash CPU at 3 MHz 1 7 mA Uis 25 2 DD 9 SID14 Ipp4 Execute from flash CPU at 3 MHz mA T 40 C to 85 C SID15 Ipps Execute from flash CPU at 6 MHz 2 5 mA T 25 C Vpp 3 3 V SID16 Ippe Execute from flash CPU at 6 MHz mA T 40 C to 85 C SID17 Ipp7 Execute from flash CPU at 12 MHz 4 mA T 25 C Vpp 3 3 V SID18 Ippa Execute from flash CPU at 12 MHz mA T 40 C to 85 C Document Number 001 90478 Rev G Page 19 of 41 PRoC BLE CYBL10X6X
28. CYBL10X6X Family Datasheet Z CYPRESS PRELIMINARY PERFORM Programmable Radio on Chip With Bluetooth Low Energy PRoC BLE General Description PRoC BLE is a 32 bit 48 MHz ARM Cortex9 MO BLE solution with CapSense 12 bit ADC four timer counter pulse width modulators TCPWM thirty six GPIOs two serial communication blocks SCBs LCD and 12S PRoC BLE includes a royalty free BLE stack compatible with Bluetooth 4 1 and provides a complete programmable and flexible solution for HID remote controls toys beacons and wireless chargers In addition to these applications PRoC BLE provides a simple low cost way to add BLE connectivity to any system Features Bluetooth Smart Connectivity m Bluetooth 4 1 single mode device m 2 4 GHz BLE radio and baseband with integrated balun m TX output power 18 dBm to 3 dBm m Received signal strength indicator RSSI with 1 dB resolution m RX sensitivity 89 dBm m TX current 15 6 mA at 0 dBm m RX current 16 4 mA ARM Cortex M0 CPU Core m 32 bit processor 0 9 DMIPS MHz with single cycle 32 bit multiply operating at up to 48 MHz m 128 KB flash memory m 16 KB SRAM memory m Emulated EEPROM using flash memory m Watchdog timer with dedicated internal low speed oscillator ILO Ultra Low Power m 1 3 uA Deep Sleep mode with watch crystal oscillator WCO on m 150 nA Hibernate mode current with SRAM retention m 60 nA Stop mode current with GPIO wakeup CapSen
29. CYPRESS PRELIMINARY Family Datasheet PERFORM Table 2 CYBL10X6X Pin List WLCSP Package continued Pin Name Type Description H5 VSSR GROUND Radio ground H6 VSSR GROUND Radio ground H7 ANT ANTENNA Antenna pin J1 P0 4 GPIO Port 0 Pin 4 analog digital Icd csd J2 P0 0 GPIO Port 0 Pin 0 analog digital Icd csd J3 VDDR POWER 1 9 V to 5 5 V radio supply J6 VDDR POWER 1 9 V to 5 5 V radio supply J7 NO CONNECT The I O subsystem consists of a high speed I O matrix HSIOM which is a group of high speed switches that routes GPIOs to the resources inside the device These resources include CapSense TCPWMs I2C SPI UART and LCD HSIOM_PORT_SELx are 32 bit wide registers that control the routing of GPIOs Each register controls one port four dedicated bits are assigned to each GPIO in the port This provides up to 16 different options for GPIO routing as shown in Table 3 Table 3 HSIOM Port Settings Value Description 0 Firmware controlled GPIO 1 Reserved 2 Reserved 3 Reserved 4 Pin is a CSD sense pin 5 Pin is a CSD shield pin 6 Pin is connected to AMUXA 7 Pin is connected to AMUXB 8 Pin specific Active function 0 9 Pin specific Active function 1 10 Pin specific Active function 2 11 Reserved 12 Pin is an LCD common pin 13 Pin is an LCD segment pin 14 Pin specific Deep Sleep function 0 15 Pin specific Deep Sleep function 1
30. F picofarad ppm parts per million ps picosecond S second Sps samples per second sqrtHz square root of hertz V volt Ww watt Page 39 of 41 CYPRESS PERFORM Revision History PRELIMINARY PRoC BLE CYBL10X6X Family Datasheet Description Title CYBL10X6X Family Datasheet Programmable Radio on Chip With Bluetooth Low Energy PRoC BLE Document Number 001 90478 Revision ECN Canes emn Description of Change F 4567076 CSAI 11 11 2014 Initial release G 4600081 SKAR 12 19 2014 Revision to 16 bit Timer Counter PWM block current consumption at 3 12 and 48 MHz to align with CHAR data Revision of I C UART block current consumption to align with CHAR data Revision of LCD Direct Drive operating current in low power mode to align with CHAR data Revision of BLE RF Average Current Spec for 4 sec BLE connection interval to 6 25 pA to align with CHAR data Revision of RXS with idle transmitter with balun loss and in high gain mode to align with CHAR data Clarified the lego operating current to reflect crystal current LDO and Bandgap current as well Corrected Typo for SID 245 CPU gt SCB Corrected Typo for SID 275 Removed errata Document Number 001 90478 Rev G Page 40 of 41 PRoC BLE CYBL10X6X PRELIMINARY Family Datasheet PERFORM Sales Solutions and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of o
31. ID290 limo2 IMO operating current at 24 MHz E 325 pA SID291 limo3 IMO operating current at 12 MHz 225 pA SID292 limoa IMO operating current at 6 MHz 180 pA SID293 limos IMO operating current at 3 MHz 150 pA Table 46 IMO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID296 FIMOTOL3 Frequency variation from 3 to 2 With API called 48 MHz calibration SID297 FIMOTOL3 IMO startup time 12 Hs Internal Low Speed Oscillator Table 47 ILO DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID298 lit o2 ILO operating current at 32 kHz 0 3 1 05 pA Table 48 ILO AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID299 TSTARTILO1 ILO startup time 2 ms SID300 FiLoTRIM4 32 kHz trimmed frequency 15 32 50 kHz Table 49 External Clock Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID301 ExtClkFreq External clock input frequency 0 48 MHz CMOS input level only TTL input is not supported SID302 ExtClkDuty Duty cycle measured at Vpp 2 45 55 CMOS input level only TTL input is not supported Document Number 001 90478 Rev G Page 31 of 41 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Data
32. X A Product Type 1 Embedded Only 4 CapSense 5 Touch B Flash Capacity 6 128 KB C Feature set DE Package Pins 56 70 FG Package code LQ QFN FN WLCSP LT Tape and Reel H Pb X Pb free X Absent with Pb l Temperature Range C Commercial 0 C to 70 C l Industrial 40 C to 85 C Document Number 001 90478 Rev G Page 34 of 41 EE E PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Packaging Table 52 Package Characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature 40 25 85 C Tj Operating junction temperature 40 100 C TJA Package 0 4 56 pin QFN 16 9 C watt Tuc Package 0 c 56 pin QFN 9 7 C watt TJA Package 0 4 68 ball WLCSP 16 6 C watt Tuc Package 8 jc 68 ball WLCSP 0 19 C watt Table 53 Solder Reflow Peak Temperature Package E ume 56 pin QFN 260 C 30 seconds 68 ball WLCSP 260 C 30 seconds Table 54 Package Moisture Sensitivity Level MSL IPC JEDEC J STD 2 Package MSL 56 pin QFN MSL 3 68 ball WLCSP MSL 1 Table 55 Package Details Spec ID Package Description 001 58740 Rev A 56 pin QFN 7 mm x 7 mm x 0 6 mm 001 92343 Rev 68 ball WLCSP 3 52 mm x 3 91 mm x 0 55 mm Document Number 001 90478 Rev G Page 35 of 41 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datashe
33. ce which can be adjusted in the range of 3 MHz to 48 MHz in steps of 1 MHz The IMO accuracy is 2 Internal Low Speed Oscillator ILO The ILO is a very low power 32 kHz oscillator which is primarily used to generate clocks for peripheral operations in Deep Sleep mode The ILO driven counters can be calibrated to the IMO to improve accuracy Cypress provides a software component which does the calibration Figure 2 Clock Control BLE Subsystem gt HFCLK I Prescaler SYSCLK 16 Mmo 3 Divider9 EXTCLK X 4 143 PERO CLK Fractional L Divider0 116 5 z Fractional PER15_CLK Divider1 16 5 gt LFCLK ILO Document Number 001 90478 Rev G PRoC BLE CYBL10X6X Family Datasheet External Crystal Oscillator ECO The ECO is used as the active clock for the BLE subsystem to meet the 50 ppm clock accuracy requirement of the Bluetooth 4 1 specification The ECO includes a tunable load capacitor to tune the crystal clock frequency by measuring the actual clock frequency The high accuracy ECO clock can also be used as a System clock Watch Crystal Oscillator WCO The WCO is used as the sleep clock for the BLE subsystem to meet the 500 ppm clock accuracy requirement of the Bluetooth 4 1 specification The sleep clock provides accurate sleep timing and enables wakeup at spec
34. d Size CapSense SCB TCPWM SAR S PWM LCD Package MHz KB ADC CYBL10161 56LQXI 48 128 No 1 2 1 Msps No No No 56 QFN CYBL10162 56LQXI 48 128 No 2 4 1 Msps No 4 No 56 QFN CYBL10163 56LQXI 48 128 No 2 4 1Msps Yes No No 56 QFN CYBL10461 56LQXI 48 128 Yes 2 4 1 Msps No No No 56 QFN CYBL10462 56LQXI 48 128 Yes 2 4 1Msps Yes No No 56 QFN CYBL10463 56LQXI 48 128 Yes 2 4 1 Msps No No Yes 56 QFN CYBL10561 56LQXI 48 128 Yes 2 4 1 Msps No No No 56 QFN Gestures CYBL10562 56LQXI 48 128 Yes 2 4 1Msps Yes 1 No 56 QFN Gestures CYBL10563 56LQXI 48 128 Yes 2 4 1Msps Yes 1 Yes 56 QFN CYBL10563 68FNXI 48 128 Yes 2 4 1Msps Yes 1 Yes 68 WLCSP Part Numbering Conventions The part numbers are of the form CYBL10ABC DEFGHI where the fields are defined as follows Example CYBL10 A B C DE FG H I CYBL PRoC BLE Family Cypress 10 CYBL10XXX Sub family 1 Embedded only 4 CapSense Product Type 5 Touch 6 128 KB Flash Capacity 3 Part Identifier Feature Set 56 68 Number of Pins Package Pins LQ QFN FN WLCSP Package Code X With Pb Pb Pb free I Industrial Temperature Range Document Number 001 90478 Rev G Page 33 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM The Field Values are listed in the following table Field Description Values Meaning CYBL Cypress PRoC BLE Family CYBL 10 Subfamily 10 CYBL10X6
35. e resets CPU lockup states and privilege violations improper power supply levels and watchdogs Make certain that these are not inadvertently activated Document Number 001 90478 Rev G Page 29 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Table 40 Brown Out Detect Spec ID Parameter Description Min Typ Max Units C D SID261 VEALLPPOR BOD trip voltage in Active and Sleep 1 64 V modes SID262 VEALLDPSLP BOD trip voltage in Deep Sleep 1 4 V Table 41 Hibernate Reset Spec ID Parameter Description Min Typ Max Units Cones SID263 VHBRTRIP BOD trip voltage in Hibernate 1 1 V Voltage Monitors LVD Table 42 Voltage Monitor DC Specifications Spec ID Parameter Description Min Typ Max Units C Dos SID265 Vivi LVI_A D_SEL 3 0 0000b 1 71 1 75 1 79 V SID266 Vivi2 LVI_A D_SEL 3 0 0001b 1 76 1 80 1 85 V SID267 Vivis LVI A D SEL 83 0 0010b 1 85 1 90 1 95 V SID268 Vivi4 LVI A D SEL 3 0 0011b 1 95 2 00 2 05 V SID269 Vivis LVI A D SEL 3 0 0100b 2 05 2 10 2 15 V SID270 Vivie LVI_A D_SEL 3 0 0101b 2 15 2 20 2 26 V SID271 Viyiz LVI A D SEL 3 0 0110b 2 24 2 30 2 36 V SID272 Vivis LVI A D SEL 3 0 0111b 2 34 2 40 2 46 V SID273 Vivig LVI_A D_SEL 3 0 1000b 2 44 2 50 2 56 V SID274 Vivito LVI_A D_SEL 3 0 1001b 2 54 2 60 2
36. ems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress product in a life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Use may be limited by and subject to the applicable Cypress software license agreement Document Number 001 90478 Rev G Revised December 19 2014 Page 41 of 41 All products and company names mentioned in this document may be the trademarks of their respective holders
37. eripheral Figure 3 SAR ADC System Diagram Control AHB DSI lt x SARSEQ SARMUX SARADC vMinus SARREF Sequencer P3 0 P3 7 X NZ Analog Mux Vrefs Bus A B Ref bypass Page 5 of 41 PERFORM A diode based on chip temperature sensor is used to measure the die temperature The temperature sensor is connected to the ADC which digitizes the reading and produces a temperature value using the Cypress supplied software that includes calibration and linearization 4x Timer Counter PWM TCPWM The 16 bit TCPWM module can be used to generate the PWM output or to capture the timing of edges of input signals or to provide a timer functionality TCPWM can also be used as a 16 bit counter that supports up down and up down counting modes Rising edge falling edge combined rising falling edge detection or pass through on all hardware input signals can be used to derive counter events Three routed output signals are available to indicate underflow overflow and counter compare match events A maximum of four TCPWMs are available 4x PWM These PWMs are in addition to the TCPWMs The PWM peripheral can be configured as 8 bit or 16 bit resolution The PWM provides compare outputs to generate single or continuous timing and control signals in hardware It also provides an easy method of generating complex real time events accurately with minimal CPU in
38. et PERFORM Figure 5 56 Pin QFN 7 mm x 7 mm x 0 6 mm TOP VIEW SIDE VIEW BOTTOM VIEW 7 00 0 10 TT 56 43 43 56 UUUUUUUUUUUUUU E 3 IN Bl Er gt C P BESI eee gt cj 2 gt 7 00 0 10 E gt F 0 20 0 05 6 CE I gt Cj gt om I gt C I gt Cj 14 29 2925 C4 a nnanaannnanaann 15 28 0 05 MAX 28 19 n E i a g NOTES 1 R HATCH AREA IS SOLDERABLE EXPOSED PAD 2 BASED ON REF JEDEC MO 248 3 ALL DIMENSIONS ARE IN MILLIMETERS 001 58740 Rev A The center pad on the QFN package must be connected to ground VSS for the proper operation of the device Figure 6 68 Ball WLCSP Package Outline TOP VIEW SIDE VIEW BOTTOM VIEW H 1234567 8 87 6 55432 1 us L oe T pe xN crommoonuso mv crammooonp NOTES 1 REFERENCE JEDEC PUBLICATION 95 DESIGN GUIDE 4 18 2 ALL DIMENSIONS ARE IN MILLIMETERS 001 92343 Rev Document Number 001 90478 Rev G Page 36 of 41 PERFORM Acronyms Table 56 Acronyms Used in This Document PRELIMINARY PRoC BLE CYBL10X6X Family Datasheet Table 56 Acronyms Used in This Document continued
39. ffices solution centers manufacturer s representatives and distributors To find the office closest to you visit us at Cypress Locations Products PSoC Solutions Automotive cypress com go automotive psoc cypress com solutions Clocks amp Buffers cypress com go clocks PSoC 1 PSoC 3 PSoC 4 PSoC 5LP Interface cypress com go interface Cypress Developer Community Lighting amp Power Control cypress com go powerpsoc Community Forums Blogs Video Training Memory cypress com go memory Technical Support PSoC cypress com go psoc cypress com go support Touch Sensing cypress com go touch USB Controllers cypress com go USB Wireless RF cypress com go wireless Cypress Semiconductor Corporation 2013 2014 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product Nor does it convey or imply any license under patent or other rights Cypress products are not warranted nor intended to be used for medical life support life saving critical control or safety applications unless pursuant to an express written agreement with Cypress Furthermore Cypress does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress products in life support systems appl
40. gital Icd csd A5 VSSD GROUND Digital ground A6 VSSA GROUND Analog ground AT VCCD POWER Regulated 1 8 V supply connect to 1 uF capacitor A8 VDDD POWER 1 7 1 V to 5 5 V digital supply B1 P2 3 GPIO Port 2 Pin 3 analog digital Icd csd B2 VSSA GROUND Analog ground B3 P2 7 GPIO Port 2 Pin 7 analog digital Icd csd B4 P3 4 GPIO Port 3 Pin 4 analog digital Icd csd B5 P3 5 GPIO Port 3 Pin 5 analog digital Icd csd B6 P3 6 GPIO Port 3 Pin 6 analog digital Icd csd B7 XTAL32I P6 1 CLOCK 32 768 kHz crystal or external clock input B8 XTAL320 P6 0 CLOCK 32 768 kHz crystal C1 VSSA GROUND Analog ground C2 P2 2 GPIO Port 2 Pin 2 analog digital Icd csd C3 P2 6 GPIO Port 2 Pin 6 analog digital Icd csd C4 P3 0 GPIO Port 3 Pin 0 analog digital Icd csd Document Number 001 90478 Rev G Page 9 of 41 PERFORM PRoC BLE CYBL10X6X PRELIMINARY Table 2 CYBL10X6X Pin List WLCSP Package continued Family Datasheet Pin Name Type Description C5 P3 1 GPIO Port 3 Pin 1 analog digital Icd csd C6 P3 2 GPIO Port 3 Pin 2 analog digital Icd csd C7 XRES RESET Reset active LOW C8 P4 0 GPIO Port 4 Pin 0 analog digital Icd csd D1 P1 7 GPIO Port 1 Pin 7 analog digital Icd csd D2 VDDA POWER 1 71 V to 5 5 V analog supply D3 P2 0 GPIO Port 2 Pin 0 analog digital Icd csd D4 P2 1 GPIO Port 2 Pin 1 analog digital Icd csd D5 P2 5 GPIO P
41. ication implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges Any Source Code software and or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign United States copyright laws and international treaty provisions Cypress hereby grants to licensee a personal non exclusive non transferable license to copy use modify create derivative works of and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement Any reproduction modification translation compilation or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Cypress reserves the right to make changes without further notice to the materials described herein Cypress does not assume any liability arising out of the application or use of any product or circuit described herein Cypress does not authorize its products for use as critical components in life support syst
42. ifications Spec ID Parameter Description Min Typ Max Units C D 5 SID53 Fopy CPU frequency DC 48 MHz 1 71V X Vppx 5 5 V SID54 TsLEEP Wakeup from Sleep mode 0 Hs Guaranteed by characterization SID55 TpEEPsLEEP Wakeup from Deep Sleep mode 25 Hs 24 MHz IMO Guaranteed by characterization SID56 THIBERNATE Wakeup from Hibernate mode 2 ms Guaranteed by characterization SID57 Tstop Wakeup from Stop mode 2 ms Guaranteed by characterization GPIO Table 10 GPIO DC Specifications Spec ID Parameter Description Min Typ Max Units C De SID58 Vin Input voltage HIGH threshold 0 7xVpp V CMOS input SID59 ViL Input voltage LOW threshold 0 3 Vpp V CMOS input SID60 Vin LVTTL input Vpp 2 7 V 0 7xVpp V SID61 Vi LVTTL input Vpp 2 7 V 0 3 Vpp V SID62 Vin LVTTL input Vpp gt 2 7 V 2 0 V SID63 ViL LVTTL input Vpp gt 2 7 V 0 8 V SID64 Vou Output voltage HIGH level Vpp 0 6 V lop 4 mA at 3 3 V VoD SID65 VoH Output voltage HIGH level Vpp 0 5 V lon 1 mA at 1 8 V Vpp SID66 VoL Output voltage LOW level B 0 6 V loi 8 mA at 3 3 V Vpp SID67 VoL Output voltage LOW level 0 6 V lo 4 mA at 1 8 V Vpp Note 3 Vj must not exceed Vpp 0 2 V Document Number 001 90478 Rev G Page 21 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family
43. ified advertisement and connection intervals With the WCO and firmware an accurate real time clock within the bounds of the 32 768 kHz crystal accuracy can be realized Voltage Reference The internal bandgap reference circuit with 196 accuracy provides the voltage reference for the 12 bit SAR ADC To enable better SNRs and absolute accuracy it will be possible to bypass the internal bandgap reference using a REF pin and to use an external reference for the SAR Watchdog Timer WDT A watchdog timer is implemented in the system resources subsystem running from the ILO this allows watchdog opera tions during Deep Sleep mode and generates a watchdog reset if not serviced before the timeout occurs The watchdog reset is recorded in the Reset Cause register Peripheral Blocks 12 Bit SAR ADC The ADC is a 12 bit 1 Msps SAR ADC with a built in sample and hold S H circuit The ADC can operate with either an internal voltage reference or an external voltage reference Preceding the SAR ADC is the SARMUX which can route external pins and internal signals analog mux bus and temper ature sensor output to the eight internal channels of the SAR ADC The sequencer controller SARSEQ is used to control the SARMUX and SAR ADC to do an automatic scan on all enabled channels without CPU intervention and for preprocessing tasks such as averaging the output data A Cypress supplied software driver Component is used to control the ADC p
44. l 4 Differential inputs use neighboring I O SID159 A MONO Monotonicity Yes SID160 A GAINERR Gain error 0 1 With external reference SID161 A OFFSET Input offset voltage 2 mV Measured with 1 V VREF SID162 A ISAR Current consumption 1 mA SID163 A_VINS Input voltage range single ended Vss VDDA V SID164 A VIND Input voltage range differential Vss VDDA V SID165 A INRES Input resistance 2 2 kQ SID166 A_INCAP Input capacitance 10 pF SID312 VREFSAR Trimmed internal reference to SAR 1 1 Percentage of Vbg 1 024 V Table 18 SAR ADC AC Specifications Spec ID Parameter Description Min Typ Max Units C De 5 SID167 A PSRR Power supply rejection ratio 70 dB Measured at 1 V SID168 A CMRR Common mode rejection ratio 66 dB SID169 A SAMP Sample rate 1 Msps SID313 Fsarintref SAR operating speed without external 100 Ksps 12 bit resolution reference bypass SID170 A SNR Signal to noise ratio SNR 65 dB Fyy 10 kHz SID171 A BW Input bandwidth without aliasing imc cdd kHz SID172 A INL Integral nonlinearity INL Vpp 1 71to 1 7 2 LSB Vprer 1 V to Vpp 5 5 V 1 Msps SID173 A INL Integral nonlinearity Vppp 1 71 to 1 5 1 7 LSB Vngr 7 1 71 Vto Vpp 3 6 V 1 Msps SID174 A INL Integral nonlinearity Vpp 1 71t05 5 V 1 5 1 7 LSB Vner 1 V to Vpp 500 Ksps SID175 A DNL Differential nonlinearity DNL Vpp 1 2 2 LSB Vprer 1V
45. l Icd csd 40 P2 3 GPIO Port 2 Pin 3 analog digital Icd csd Page 8 of 41 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Table 1 CYBL10X6X Pin List QFN Package continued Pin Name Type Description 41 P24 GPIO Port 2 Pin 4 analog digital Icd csd 42 P2 5 GPIO Port 2 Pin 5 analog digital Icd csd 43 P2 6 GPIO Port 2 Pin 6 analog digital Icd csd 44 P2 7 GPIO Port 2 Pin 7 analog digital Icd csd 45 VREF REF 1 024 V reference 46 VDDA POWER 1 71 V to 5 5 V analog supply 47 P3 0 GPIO Port 3 Pin 0 analog digital Icd csd 48 P3 1 GPIO Port 3 Pin 1 analog digital Icd csd 49 P3 2 GPIO Port 3 Pin 2 analog digital Icd csd 50 P3 3 GPIO Port 3 Pin 3 analog digital Icd csd 51 P3 4 GPIO Port 3 Pin 4 analog digital Icd csd 52 P3 5 GPIO Port 3 Pin 5 analog digital Icd csd 53 P3 6 GPIO Port 3 Pin 6 analog digital Icd csd 54 P3 7 GPIO Port 3 Pin 7 analog digital Icd csd 55 VSSA GROUND Analog ground 56 VCCD POWER Regulated 1 8 V supply connect to 1 uF capacitor 57 EPAD GROUND Ground paddle for the QFN package Table 2 shows the pin list for the CYBL10X6X device WLCSP package Table 2 CYBL10X6X Pin List WLCSP Package Pin Name Type Description Al VREF REF 1 024 V reference A2 VSSA GROUND Analog ground A3 P3 3 GPIO Port 3 Pin 3 analog digital Icd csd A4 P3 7 GPIO Port 3 Pin 7 analog di
46. m The BLE subsystem consists of the link layer engine and physical layer The link layer engine supports both master and slave roles The link layer engine implements time critical functions such as encryption in the hardware to reduce the power consumption and provides minimal processor inter vention and a high performance The key protocol elements such as host control interface HCI and link control are imple mented in firmware The direct test mode DTM is included to test the radio performance using a standard Bluetooth tester Document Number 001 90478 Rev G PRoC BLE CYBL10X6X Family Datasheet The physical layer consists of a modem and an RF transceiver that transmits and receives BLE packets at the rate of 1 Mbps over the 2 4 GHz ISM band In the transmit direction this block performs GFSK modulation and then converts the digital baseband signal of these BLE packets into radio frequency before transmitting them to air through an antenna In the receive direction this block converts an RF signal from the antenna to a digital bit stream after performing GFSK demodulation The RF transceiver contains an integrated balun which provides a single ended RF port pin to drive a 50 O antenna terminal through a pi matching network The output power is program mable from 18 dBm to 3 dBm to optimize the current consumption for different applications The Bluetooth Low Energy protocol stack uses the BLE subsystem and p
47. mode input and output buffers disabled a Input only a Weak pull up with strong pull down a Weak pull up with weak pull down a Strong pull up with weak pull down a Strong pull up with strong pull down a Open drain with strong pull down a Open drain with strong pull up m Port pins 36 m Input threshold select CMOS or LVTTL m Individual control of input and output buffers enabling disabling in addition to drive strength modes m Hold mode for latching the previous state used for retaining the I O state in Deep Sleep and Hibernate modes m Selectable slew rates for dV dt to improve EMI m The GPIO pins P5 0 and P5 1 are overvoltage tolerant m The GPIO cells including P5 0 and P5 1 cannot be hot swapped or powered up independent of the rest of the system Page 7 of 41 Table 1 shows the pin list for the CYBL10X6X device Table 1 CYBL10X6X Pin List QFN Package PRoC BLE CYBL10X6X Family Datasheet Document Number 001 90478 Rev G Pin Name Type Description 1 VDDD POWER 1 71 V to 5 5 V digital supply 2 XTAL320 P6 0 CLOCK 32 768 kHz crystal 3 XTAL32I P6 1 CLOCK 32 768 kHz crystal or external clock input 4 XRES RESET Reset active LOW 5 P4 0 GPIO Port 4 Pin 0 analog digital Icd csd 6 P4 1 GPIO Port 4 Pin 1 analog digital Icd csd 7 P5 0 GPIO Port 5 Pin 0 analog digital Icd csd 8 P5
48. mory XRES external reset I O pin RISC reduced instruction set computing XTAL crystal RMS root mean square RTC real time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC CT Switched capacitor continuous time SCL 12C serial clock SDA 12C serial data S H sample and hold SINAD signal to noise and distortion ratio SIO special input output GPIO with advanced features See GPIO SOC start of conversion SOF start of frame SPI Serial Peripheral Interface a communications protocol SR slew rate Page 38 of 41 PERFORM Document Conventions Units of Measure Table 57 Units of Measure PRELIMINARY PRoC BLE CYBL10X6X Table 57 Units of Measure continued Family Datasheet Symbol Unit of Measure C degrees Celsius dB decibel dBm decibel milliwatts fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz kQ kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MO mega ohm Msps megasamples per second pA microampere uF microfarad Document Number 001 90478 Rev G Symbol Unit of Measure uH microhenry Hs microsecond uV microvolt uW microwatt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt Q ohm p
49. n device It does not require special interfaces debugging pods simulators or emulators Only the standard programming connections are required to fully support debug Document Number 001 90478 Rev G BLE Subsystem XTAL321 P6 1 s XTAL320 P6 0 GPIOs GPIOs GPIOs GPIOs I O Subsystem The PSoC Creator IDE provides fully integrated programming and debug support for PRoC BLE devices The SWD interface is fuly compatible with industry standard third party tools PRoC BLE also supports disabling the SWD interface and has a robust flash protection feature Page 3 of 41 PERFORM CPU Subsystem PU The CYBL10X6X device is based on an energy efficient ARM Cortex MO 32 bit processor offering low power consumption high performance and reduced code size using 16 bit thumb instructions The Cortex MO s ability to perform single cycle 32 bit arithmetic and logic operations including single cycle 32 bit multiplication helps in better performance The inclusion of the tightly integrated Nested Vectored Interrupt Controller NVIC with 32 interrupt lines enables the Cortex MO to achieve a low latency and a deterministic interrupt response The CPU also includes a 2 pin interface the serial wire debug SWD which is a 2 wire form of JTAG The debug circuits are enabled by default and can only be disabled in firmware If disabled the only way to re enable them is to erase the entire device clear flash protection and
50. ontinued Document Number 001 90478 Rev G Acronym Description Acronym Description NVL nonvolatile latch see also WOL SRAM static random access memory opamp operational amplifier SRES software reset PAL programmable array logic see also PLD STN super twisted nematic PC program counter SWD serial wire debug a test protocol PCB printed circuit board SWV single wire viewer PGA programmable gain amplifier TD transaction descriptor see also DMA PHUB peripheral hub THD total harmonic distortion PHY physical layer TIA transimpedance amplifier PICU port interrupt control unit TN twisted nematic PLA programmable logic array TRM technical reference manual PLD programmable logic device see also PAL TTL transistor transistor logic PLL phase locked loop TX transmit PMDD package material declaration data sheet UART Universal Asynchronous Transmitter Receiver a POR power on reset communications protocol PRES precise power on reset USB A Serial Bus PRS pseudo random sequence USBIO eee PSoC pins used to connect to PS portread dataregister VDAC voltage DAC see also DAC IDAC PSoc Programmable System on Chip WDT watchdog timer FaR power supply rejection ratio WOL write once latch see also NVL PWN pulsewidth modulator WRES watchdog timer reset BAM random access me
51. ort 2 Pin 5 analog digital Icd csd D6 VSSD GROUND Digital ground D7 P4 1 GPIO Port 4 Pin 1 analog digital Icd csd D8 P5 0 GPIO Port 5 Pin 0 analog digital Icd csd E1 P1 2 GPIO Port 1 Pin 2 analog digital Icd csd E2 P1 3 GPIO Port 1 Pin 3 analog digital Icd csd E3 P1 4 GPIO Port 1 Pin 4 analog digital Icd csd E4 P1 5 GPIO Port 1 Pin 5 analog digital Icd csd E5 P1 6 GPIO Port 1 Pin 6 analog digital Icd csd E6 P2 4 GPIO Port 2 Pin 4 analog digital Icd csd E7 P5 1 GPIO Port 5 Pin 1 analog digital Icd csd E8 VSSD GROUND Digital ground F1 VSSD GROUND Digital ground F2 P0 7 GPIO Port 0 Pin 7 analog digital Icd csd F3 P0 3 GPIO Port 0 Pin 3 analog digital Icd csd F4 P1 0 GPIO Port 1 Pin 0 analog digital Icd csd F5 P1 1 GPIO Port 1 Pin 1 analog digital Icd csd F6 VSSR GROUND Radio ground F7 VSSR GROUND Radio ground F8 VDDR POWER 1 9 V to 5 5 V radio supply G1 P0 6 GPIO Port 0 Pin 6 analog digital Icd csd G2 VDDD POWER 1 71 V to 5 5 V digital supply G3 P0 2 GPIO Port 0 Pin 2 analog digital Icd csd G4 VSSD GROUND Digital ground G5 VSSR GROUND Radio ground G6 VSSR GROUND Radio ground G7 GANT GROUND Antenna shielding ground G8 VSSR GROUND Radio ground H1 P0 5 GPIO Port 0 Pin 5 analog digital Icd csd H2 PO 1 GPIO Port 0 Pin 1 analog digital Icd csd H3 XTAL240 CLOCK 24 MHz crystal H4 XTAL24I CLOCK 24 MHz crystal or external clock input Document Number 001 90478 Rev G Page 10 of 41 mE E PRoC BLE CYBL10X6X WE
52. ow Power Modes PRoC BLE supports five power modes Refer to Table 5 for more details on the system status The PRoC BLE device consumes the lowest current in Stop mode the device wakeup from stop mode is with a system reset through the XRES or WAKEUP pin It can retain the SRAM data in Hibernate mode and is capable of retaining the complete system status in Deep Sleep mode Table 5 shows the different power modes and the peripherals that are active Digital Analog Clock Current Code Wake Up Wake Up Power Mode 5 Peripherals Peripherals Sources Consumption Execution Available Available Avallable Sources Time Active 850 pA 260 uA Yes All All All per MHzl Sleep 1 1 mA at 3 MHz No All All All Any interrupt 0 source Deep Sleep 1 3 pA No WDT LCD POR BOD WCO GPIO WDT 25 us l C SPI ILO I C SPI Link Link Layer Layer Hibernate 150 nA No No POR BOD No GPIO 2ms Stop 60 nA No No No No Wake Up pin 2 ms XRES Note 1 For CPU subsystem Document Number 001 90478 Rev G Page 13 of 41 E PRoC BLE CYBL10X6X PRELIMINARY Family Datasheet PERFORM A typical system application connection diagram for the 56 QFN package is shown in Figure 4 Figure 4 PRoC BLE Applications Diagram C1 1 0 uF VSSA Dogg m j Oooo L LI m po c po o o T Eo c3 C4 36 pF T t8 pF ul 2 1 I 1 voon 32 T68KHz hes XTAL320 P6 D XTAL32U PB 1 ANTENNA n XRES _
53. reprogram the device with the new firmware that enables debugging In addition it is possible to use the debug pins as GPIO too The device has four break points and two watchpoints for effective debugging 9 Flash The device has a 128 KB flash memory with a flash accelerator tightly coupled to the CPU to improve average access times from flash The flash is designed to deliver 1 wait state WS access time at 48 MHz and with 0 WS access time at 24 MHz The flash accelerator delivers 8596 of single cycle SRAM access perfor mance on average Part of the flash can be used to emulate EEPROM operation if required During flash erase and programming operations the maximum erase and program time is 20 ms per row the IMO will be set to 48 MHz for the duration of the operation This also applies to the emulated EEPROM System design must take this into account because peripherals operating from different IMO frequencies will be affected If it is critical that peripherals continue to operate with no change during flash programming always set the IMO to 48 MHz and derive the peripheral clocks by dividing down from this frequency SRAM The low power 16 KB SRAM memory retains its contents even in Hibernate mode ROM The 8 KB supervisory ROM contains a library of executable functions for flash programming These functions are accessed through supervisory calls SVC and enable in system programming of the flash memory BLE Subsyste
54. rovides the following features m Link Layer LL da Master and Slave roles a 128 bit AES engine a Encryption a Low duty cycle advertising Bluetooth 4 1 feature a LE Ping Bluetooth 4 1 feature m Bluetooth Low Energy 4 1 single mode protocol stack with logical link control and adaptation protocol L2CAP attribute ATT and security manager SM protocols m Master and slave roles m API access to generic attribute profile GATT generic access profile GAP and L2CAP m L2CAP connection oriented channel Bluetooth 4 1 feature m GAP features a Broadcaster Observer Peripheral and Central roles a Security mode 1 Level 1 2 and 3 a Security mode 2 Level 1 and 2 da User defined advertising data Multiple bond support W GATT features og GATT Client and Server a Supports GATT subprocedures a 32 bit universally unique identifiers UUID Bluetooth 4 1 feature m Security Manager SM q Panne methods Just Works Passkey Entry and Out of an a Authenticated man in the middle MITM protection and data signing m Supports all SIG adopted BLE profiles System Resources Subsystem Power The power block includes internal LDOs that supply required voltage levels for different blocks The power system also includes POR BOD and LVD circuits The POR circuit holds the device in the reset state until the power supplies have stabilized at appropriate levels and the clock is ready The BOD circuit resets the
55. se Touch Sensing with Two Finger Gestures m Up to 36 capacitive sensors for buttons sliders and touchpads m Two finger gestures scroll inertial scroll pinch stretch and edge swipe m Cypress Capacitive Sigma Delta CSD provides best in class SNR gt 5 1 and liquid tolerance m Automatic hardware tuning algorithm SmartSense Peripherals m 12 bit 1 Msps SAR ADC with internal reference sample and hold S H and channel sequencer m Ultra low power LCD segment drive for 128 segments with operation in Deep Sleep mode m Two serial communication blocks SCBs supporting Ic Master Slave SPI Master Slave or UART Cypress Semiconductor Corporation Document Number 001 90478 Rev G 198 Champion Court m Four dedicated 16 bit TCPWMs a Additional four 8 bit or two 16 bit PWMs m Programmable LVD from 1 8 V to 4 5 V m 2S Master interface Clock Reset and Supply m Wide supply voltage range 1 9 V to 5 5 V m 3 MHz to 48 MHz internal main oscillator IMO with 2 accuracy m 24 MHz external clock oscillator ECO without load capaci tance m 32 kHz WCO Programmable GPIOs m 36 GPIOs configurable as open drain high low pull up pull down HI Z or strong output m Any GPIO pin can be CapSense LCD or analog with flexible pin routing Programming and Debug m 2 pin SWD m In system flash programming support Temperature and Packaging m Operating temperature range 40 C to 85 C m Available in 5
56. sheet PERFORM Table 50 ECO Specifications Spec ID Parameter Description Min Typ Max Units C td E SID389 FEco Crystal frequency 24 MHz SID390 FroL Frequency tolerance 50 50 ppm SID391 ESR Equivalent series resistance 60 Q SID392 PD Drive level 100 uW SID393 TSTART1 Startup time Fast Charge on 850 HS SID394 TsraRT2 Startup time Fast Charge off 3 ms SID395 CL Load capacitance 8 pF SID396 C o Shunt capacitance 1 1 pF SID397 leco Operating current 7 1400 HA Includes LDO BG current Table 51 WCO Specifications Spec ID Parameter Description Min Typ Max Units C De SID398 Fwco Crystal frequency 32 768 kHz SID399 FroL Frequency tolerance 50 ppm S1D400 ESR Equivalent series resistance 50 kQ S1D401 PD Drive level 1 uW SID402 TSTART Startup time 500 ms SID403 CL Crystal load capacitance 6 12 5 pF SID404 Co Crystal shunt capacitance 1 35 pF SID405 lwco1 Operating current high power 8 pA mode SID406 lwco2 Operating current low power 1 pA mode Document Number 001 90478 Rev G Page 32 of 41 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Ordering Information The CYBL10X6X part numbers and features are listed in the following table CPU Flash 12 Bit Part Number Spee
57. sss 19 Analog Peripherals esee 24 Document Number 001 90478 Rev G Digital Peripherals 26 iuba e toed 29 System RESOUICES airian iiceoe 29 Ordering Information eere 33 Part Numbering Conventions eses 33 Packaging inaasa enne nnne nnne 35 ACTONYIMS M 37 Document Conventions eene 39 Units of Measure see 39 Revision History eene 40 Sales Solutions and Legal Information 41 Worldwide Sales and Design Support 41 PEOGUCIS occas oett rH ERE POHREER SENE 41 PSoCGO SOlUtlOriS 2 aie totiens eee 41 Cypress Developer Community ssse 41 Technical SUpport 2222 race titer tenens 41 Page 2 of 41 PERFORM Blocks and Functionality PRELIMINARY PRoC BLE CYBL10X6X Family Datasheet The CYBL10X6X block diagram is shown in Figure 1 There are five major subsystems CPU subsystem BLE subsystem system resources peripheral blocks and I O subsystem Figure 1 Block Diagram CPU Subsystem System Resources Peripherals GPIOs GPIOs GPIOs The PRoC BLE family includes extensive support for programming testing debugging and tracing both hardware and firmware The complete debug on chip functionality enables full device debugging in the final system using the standard productio
58. tage This method results in higher power consumption but provides better results in driving TN displays LCD operation is supported during Deep Sleep mode by refreshing a small display buffer four bits one 32 bit register per port Page 6 of 41 LL PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM CapSense CapSense is supported on all GPIOs through a Capacitive Sigma Delta CSD block which can be connected to any GPIO through an analog mux bus Any GPIO pin can be connected to the analog mux bus via an analog switch The CapSense function can thus be provided on any pin or group of pins in a system under software control A software Component in PSoC Creator is provided for the CapSense block to make it easy for the user The shield voltage can be driven on another mux bus to provide liquid tolerance capability Driving the shield electrode in phase with the sense electrode keeps the shield capacitance from attenuating the sensed input The CapSense trackpad touchpad with gestures has the following features m Supports 1 finger and 2 finger touch applications m Supports up to 35 X Y sensor inputs m includes a gesture detection library a 1 finger touch tracing pan click double click a 2 finger touch pan click zoom Document Number 001 90478 Rev G VO Subsystem The I O subsystem which comprises the GPIO block imple ments the following m Fight drive strength modes a Analog input
59. tervention A maximum of four 8 bit PWMs or two 16 bit PWMs are available Serial Communication Block SCBO SCB1 The SCB can be configured as an I C UART or SPI interface It supports an 8 byte FIFO for receive and transmit buffers to reduce CPU intervention A maximum of two SCBs SCBO SCB1 are available IC mode The l C peripheral is compatible with the Ic Standard mode Fast mode and Fast Mode Plus devices as defined in the NXP I C bus specification and user manual UM10204 The IC bus I O is implemented with GPIOs in open drain modes The hardware I C block implements a full multimaster and slave interface it is capable of multimaster arbitration This block is capable of operating at speeds of up to 1 Mbps Fast Mode Plus and has flexible buffering options to reduce the interrupt overhead and latency for the CPU The I C function is imple mented using the Cypress provided software Component EzI2C that creates a mailbox address range in the memory of PRoC BLE and effectively reduces the 12C communication to reading from and writing to an array in memory In addition the block supports an 8 byte FIFO for receive and transmit which by increasing the time given for the CPU to read data greatly reduces the need for clock stretching caused by the CPU not having read the data on time When SCBO is used Serial Data SDA and Serial Clock SCL of I C can be connected to P0 4 and PO 5 or P1 4 and P1 5 or P3 0 and P3 1
60. to Vpp 1 71 to 5 5 V 1 Msps Document Number 001 90478 Rev G Page 24 of 41 PERFORM PRELIMINARY PRoC BLE CYBL10X6X Family Datasheet Table 18 SAR ADC AC Specifications continued Spec ID Parameter Description Min Typ Max Units C Ds SID176 A DNL Differential nonlinearity Vpp 1 71 to 1 2 LSB Vngr 7 1 71 Vto Vpp 3 6 V 1 Msps SID177 A DNL Differential nonlinearity Vpp 1 71 to 1 2 2 LSB Vrer 1 V to Vpp 5 5 V 500 Ksps SID178 A THD Total harmonic distortion 65 dB Fiy 10 kHz CSD Table 19 CSD Block Specifications ee Details Spec ID Parameter Description Min Typ Max Units Conditions SID179 VCSD Voltage range of operation 1 71 5 5 V SID180 IDAC1 DNL for 8 bit resolution 1 1 LSB SID181 IDAC1 INL for 8 bit resolution 3 3 LSB SID182 IDAC2 DNL for 7 bit resolution 1 1 LSB SID183 IDAC2 INL for 7 bit resolution 3 3 LSB SID184 SNR Ratio of counts of finger to noise 5 2 Z Ratio Capacitance range of 9 pF to 35 pF 0 1 pF sensitivity Radio is not operating during the scan SID185 IDAC1 CRT4 Output current of IDAC 1 8 bits in HIGH m 612 uA E range SID186 IDAC1 CRT2 Output current of IDAC1 8 bits in LOW 306 uA m range SID187 IDAC2 CRT4 Output current of IDAC2 7 bits in HIGH zs 305 uA E range SID188 IDAC2 CRT2 Output current of IDAC2 7 bits in LOW 153
61. urrent E 2 mA 32 x 4 segments Vbias 5 V 50 Hz 25 C SID232 li cpopP2 LCD system operating current 2 mA 32 x 4 segments Vbias 3 3 V 50 Hz 25 C Table 29 LCD Direct Drive AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID233 Ficp LCD frame rate 10 50 150 Hz Table 30 Fixed UART DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID234 lUART4 Block current consumption at 100 kbps 55 pA SID235 lUART2 Block current consumption at 312 pA 1000 kbps Document Number 001 90478 Rev G Page 27 of 41 PRoC BLE CYBL10X6X CYPRESS PRELIMINARY Family Datasheet PERFORM Table 31 Fixed UART AC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID236 FUART Bit rate 1 Mbps SPI Specifications Table 32 Fixed SPI DC Specifications Spec ID Parameter Description Min Typ Max Units Details Conditions SID237 Ispi4 Block current consumption at 1 Mbps m 360 pA SID238 Ispi2 Block current consumption at 4 Mbps 560 pA SID239 Ispi3 Block current consumption at 8 Mbps m E 600 pA Table 33 Fixed SPI AC Specifications Spec ID Parameter Description Min Typ Max Units Details
62. uty cycle SID85 FGPIOUT4 GPIO Fout 1 7 V lt Vpp x 3 3 V 3 5 MHz 90 1096 25 pF load Slow Strong mode 60 40 duty cycle SID86 FGPIOIN GPIO input operating frequency 48 MHz 90 1096 Vio 1 71 V lt Vppx 5 5 V Table 12 OVT GPIO DC Specifications P5 0 and P5 1 Only Spec ID Parameter Description Min Typ Max Units C DE SID71A lu Input leakage absolute value 10 pA 125 C Vpp OV Vin Vin gt Vpp 3 0V SID66A VoL Output voltage LOW level 0 4 V lo 20 mA Vpp gt 2 9 V Document Number 001 90478 Rev G Page 22 of 41 mE E PRoC BLE CYBL10X6X WE CYPRESS PRELIMINARY Family Datasheet PERFORM Table 13 OVT GPIO AC Specifications P5 0 and P5 1 Only XM 3 Details Spec ID Parameter Description Min Typ Max Units Conditions SID78A TRISE OVFS Output rise time in Fast Strong mode 1 5 12 ns 25 pF load i 10 90 Vpp 3 3 V SID79A TEALL OVFS Output fall time in Fast Strong mode 1 5 12 ns 25 pF load i 10 90 Vpp 3 3 V SID80A TnisEss Output rise time in Slow Strong mode 10 60 ns 25 pF load 10 90 Vpp 3 3 V SID81A TFALLSS Output fall time in Slow Strong mode 10 60 ns 25 pF load 10 90 Vpp 3 3V SID82A FGPIOUT1 GPIO Foyt 3 3 V lt Vpp lt 5 5 V 24 MHz 90 1096 25 pF Fast Strong mode load 60 40 duty cycle SID83A Fopiout2 GPIO Four 1 71 V lt Vpp lt 3
63. with a voltage range Power Supply Bypass Capacitors of 1 9 V to 5 5 V by directly connecting to the digital supply Mp 0 1 yF ceramic at each pin plus bulk Vppp analog supply VppA and radio supply Vppg pins The capacitor 1 uF to 10 uF internal LDOs in the device regulate the supply voltage to required levels for different blocks The device has one regulator VDDA 0 1 uF ceramic at each pin plus bulk for the digital circuitry and separate regulators for radio circuitry capacitor 1 UF to 10 pF for noise isolation The analog circuits run directly from the VDDR 0 1 uF ceramic at each pin plus bulk analog supply VppA input The device uses separate regulators capacitor 1 uF to 10 uF for Deep Sleep and Hibernate modes to minimize the power 7 consumption The radio stops working below 1 9 V but the rest Vccp TF ceramic capacitor at the VCCDpin of the system continues to function down to 1 71 V without RF y Bypass capacitors must be used from VDDx x A D or R to REF optional E ips UF ft gor S ground The typical practice for systems in this frequency range is to use a capacitor in the 1 uF range in parallel with a smaller capacitor for example 0 1 UF Note that these are simply rules of thumb and that for critical applications the PCB layout lead inductance and the bypass capacitor parasitic should be simulated to design to obtain optimal bypassing Table 5 Power Modes System Status L

Cypress Semiconductor CYBL10162-56LQXI Datasheet

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