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MIP7365 64-bit Superscaler Microprocessor (6/07)

1. Device Compact Model Junction Operating power is dissipated in any package watts offered at worst case power supply Notes 1 Short term is understood as the definition stated in Telcordia Generic Requirements GR 63 Core 2 the junction to case thermal resistance the junction to board thermal resistance are obtained from Package vendor 3 OSA is the thermal resistance of the heat sink to ambient OCS is the thermal resistance of the heat sink attached material 4 The actual OSA required may vary according to the air speed at the location of the device in the system with all the components in place SCD7365 Rev C 8 25 11 11 Aeroflex Plainview MIP7365 216 PIN LOFP PACKAGE OUTLINE 26 20 1 031 25 80 1 015 27 0 20 008 C A B D 1810516 a A AA 12 90 508 210279 2534 E e PORE AAA ERE SEE DETAIL C E A 26 20 1 031 ya 25 80 1 015 N DETAIL A AA EJ E 24 20 953 1 23 80 937 13 10
2. Lm ses 184 circuit board Aeroflex Plainview MIP7365 D 9171 09000 A i T 99229990229999229995 c oocooooocGooooo2o0D000O0 Fe D 0000 0660 G 0000 2066 K L 2025 M dc E 1 lt 4 T 00090900605000060500000 U 06000096090000000000 ic Y Wn ea 7 rt p gt q4 p ri TOP VIEW T DETAIL x gt BOTTOM VIEW O Q DA 5 0 95 DETAIL X O O b rx SIDE VIEW A 000000 a OO00008 012 2b F Ne B 4 DETAR X SEATING PLAN DETAIL Y MAX 067 sem mem LL m r mas seres es oem e SCD7365 Rev C 8 25 11 16 Aeroflex Plainview MIP7365 256 TBGA PACKAGE OUTLINE NOTES Notes 1 Package dimensions conform to JEDEC Registration 149 2 2 e represents the basic solder ball grid patch 3 M represents the maximum solder ball matrix size 4 Dimension b is measured at the maximum solder ball diameter parallel to the primary datum c 5 6 7 8 The Primary datum c and the seating plane are defin
3. 516 AA B B 12 90 508 12100476 7 11 90 485 bbb bb b Mold d depressionin AA lt 6 6 260 gt plastic solder L 24 20 953 5 _ 0 20 008 H A B p 4X 23 80 93 t937 4X EXPOSED PAD OPTION The solderable exposed pad must be BOTTOM VIEW connected to ground on the PCB DETAIL B E 1 45 057 i 42 N 0 20 008 MIN 27005 jm WI MIN O R0 08 003 MIN TYP 0 40 0167 I 9 201 008 1 60 063 MAX A 0 20 008 X 0 05 9 H 0 08 003 AFTER PLATING DATUM PLANE 2 BASE PLANE A es AA 0 08 003 C GAGE PLANE 0 25 010 AA 0 07 003 Q ODG 0 15 006 A v SEATING PLANE Ssi 902 A 0 75 029 0 13 0 23 WITH LEAD FINISH 0 45 018 1 00 039 REF 0 09 0 20 _ 0 09 0 16 DETAIL B 2 1 lt 0 13 0 18 METAL sun sns n n n SIDE VIEW BSC AB D 0 35 DETAIL DETAIL EXPOSED PAD CORNER DETAIL SCD7365 Rev C 8 25 11 12 Aeroflex Plainview MIP7365 216 PIN EPad LOFP PACKAGE OUTLINE NOTES Notes 1 All dimensions and tolerancing conform to ANSI Y14 5 1982 Inches are shown in parentheses A Datum plane H located at mold parting line and coincident with lead where lead exits plastic body at bottom of parting line A Datums A B and D to be determined at centerline between
4. vw vs Maen SCD7365 Rev C 8 25 11 19 Aeroflex Plainview PART NUMBER BREAKDOWN MIP7365 216 EPad LOFP 7365 450 PR MIPS Series T T screening Base Processor Type 1 Industrial Temp 40 C to 85 R Extended Temp 55 C to 110 C Maximum Pipeline Frequency 450 450MHz Package Type amp Size P 26mm Sq 216 EPad LQFP PART NUMBER BREAKDOWN MIP7365 256 TBGA MIP 7365 450 BI RU MIPS Series T I Package Substrate Base Processor Type Blank D004 Maximum Pipeline Frequency U D004U 450 450MHz Screening 1 Industrial Temp 40 to 85 Extended Temp 55 C to 110 C Package Type amp Size B1 26mm Sq 256 TGBA SCD7365 Rev 8 25 11 20 Aeroflex Plainview SAMPLE ORDERING INFORMATION PIPELINE FREO MHZ Note 2 450 256 TBGA PART NUMBER MIP7365 450PI 1 MIP7365 450PR 1 SCREENING PACKAGE Industrial Temperature Range 40 C to 85 C Testing Extended Temperature Range 55 C to 110 C Testing Industrial Temperature Range 40 C to 85 C Testing MIP7365 450B 11 MIP7365 450B1R Extended Range 55 C to 110 C MIP7365 450B1IU 2 MIP7365 450B 1RU Notes 1 Substrate 0004 2 Substrate D004U Industrial Temperature Range 40 C to 85 C Testing Extended Temperature Range 55 C to 110 C Testing PLAINVIEW NEW YORK Toll Free 800 THE 1553 Fax 516 694 6715 SE
5. 0 3V 5 HN 0 5uA VIN VccIO VeclO 2 3V 2 7V PARAMETER MINIMUM MAXIMUM CONDITIONS aw pL eS poe veo 15uA 0 15pA VIN VcclO POWER CONSUMPTION IIoUTI 2mA CPU SPEED 450MHz 450MHz PARAMETER CONDITIONS IND MIL Power mWatts Active Maximum with no FPU operation 2 3100 3250 Notes 1 Worst case supply voltage maximum Vcclnt with worst case temperature maximum TCASE 2 Dhrystone 2 1 instruction mix 3 supply power is application dependant but typically lt 20 of Vcclnt SCD7365 Rev C 8 25 11 8 Aeroflex Plainview AC CHARACTERISTICS CAPACITIVE LOAD DERATION SYMBOL PARAMETER MINIMUM MAXIMUM UNITS CLOCK PARAMETERS BUS SPEED PARAMETER SYMBOL TEST CONDITIONS VM UNITS ru eme __ eee ome 9S pe p LE T x p es T oj E ra mesanman Notes 1 Operation of the MIP7365 is only guaranteed with the Phase Loop enabled SYSTEM INTERFACE PARAMETERS YO TYPE PARAMETER TEST CONDITIONS gt LVTTL IVTILYO UNITS LVTTL VccIO 3 3 mode 14 13 01 slowest a r Notes In LVTTL mode timings are measured from 0 425 x VccIO of clock to 0 425 x VccIO of signal for 3 3V and from 0 48 x 1 of clock to 0 48 x VccIO of signal for 2 5V
6. Cvt Div Sqrt Branch PC Adder FA Bus ITLB Virtual DTLB Virtual Multiplier Array Program Counter PLL Clocks Int Mult Div Madd Logicals Integer Control Integer Control BLOCK DIAGRAM SCD7365 Rev D 2 17 12 2 Aeroflex Plainview DESCRIPTION The MIP7365 Microprocessor is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle It has two high performance 64 bit integer units as well as a high throughput fully pipelined 64 bit floating point unit The MIP7365 integrates 16 Kbytes 4 way set associative instruction and data caches along with an integrated 256 Kbytes 4 way set associative secondary cache The primary data and secondary caches are write back and non blocking The memory management unit contains a 64 48 entry fully associative TLB and a 64 bit system interface supporting multiple outstanding reads with out of order return and hardware prioritized and vectored interrupts The MIP7365 is available in a 216 EPad LQFP package and 256 pin TBGA package The 216 EPad package is pin compatible with previous RM7965 and the RM5261A ExposedPad products The MIP7365 ideally suits high end embedded control applications such as internetworking high performance image manipulation high speed printing and 3 D visualization The MIP7365 is also applicable to the low end workstation market where its balanced integer and floating point performance provides outstanding price
7. performance For additional Detail Information regarding the operation of the PMC Sierra see the latest PMC Sierra datasheet for the RM7065C Family Microprocessors Data Sheet Issue No 5 August 2006 Document No PMC 2021816 Issue 5 SCD7365 Rev D 2 17 12 3 Aeroflex Plainview PIN DESCRIPTIONS The following is a list of control data clock interrupt and miscellaneous pins of MIP7365 System Interface PIN NAME TYPE DESCRIPTION ExtRqst Input External request Signals that the external agent is submitting an external request Release Output Release interface Signals that the processor is releasing the system interface to slave state RdRdy Input Read Ready Signals that an external agent can now accept a processor read WrRdy Input Write Ready Signals that an external agent can now accept a processor write request ValidIn Input Valid Input Signals that an external agent is now driving a valid address or data on the bus and a valid command or data identifier on the SysCmd bus ValidOut Output Valid output Signals that the processor is now driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus Output Processor Request When asserted this signal requests that control of the system interface be returned to the processor This is enabled by Mode Bit 26 Input Processor Acknowledge When asserted in response to PRqst this signal indicates to the processor that it has been grante
8. A SCD7365 Rev C 8 25 11 Do Not Connect Do Not Connect Do Not Connect SysCmdP SysCmd8 109 110 Wem es NN IINE NEC NN pee pep em Dona Comen T _ 5 Sen vw fe veo veo see p 9 sapo _ ValidIn 140 SysAD41 fe vem 5 Dona ema MS 7 san __ Luo e ams ____ SysCmd7 JTCK 151 SysAD5 SysCmd6 JTDI 152 SysAD36 Aeroflex Plainview MIP7365 216 LQFP NUMERICAL PINOUT vs FUNCTION 2 CON T FUNCTION FUNCTION SCD7365 Rev C 8 25 11 1 The exposed pad on the bottom of the EPad LQFP package acts as the sole device ground and as the primary heat conduction path As such it must be soldered to the printed 2 See PMC 2030256 216 EPad LQFP Design Guidelines Application Note for details 156 Do Not Connect Eme 158 Do Not Connect Exe ee 159 Do Not Connect 197 SysADC2 160 Do Not Connect 198 SysAD63 161 Do Not Connect BEEN INN 163 Do Not Connect Em sas paw vem Lr ses Sew Lm vem KA f Donaco Lus vem ____ 28 24 m vam 2 veo
9. AND MID ATLANTIC Tel 321 951 4164 Fax 321 951 4254 INTERNATIONAL Tel 805 778 9229 Fax 805 778 1980 WEST COAST Tel 949 362 2260 Fax 949 362 2266 NORTHEAST Tel 603 888 3975 Fax 603 888 4585 CENTRAL Tel 719 594 8017 Fax 719 594 8468 EROFLEX A passion for performance www aeroflex com info ams aeroflex com Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications design function or form of its products described herein All parameters must be validated for each customer s application by engineering No liability is assumed as a result of use of this product No patent licenses are implied Our passion for performance is defined by three attributes represented by these three icons solution minded performance driven and customer focused SCD7365 Rev 2 17 12 21
10. I O Input Rise Fall time 1V Ins Capacitive load for all LVTTL maximum output timings is 50 pF Minimum output timings are for theoretical no load conditions untested Data Output timing applies to all signal pins whether tristate or output only Setup and Hold parameters apply to all signal pins whether tristate I O or input only Only mode 14 13 01 is tested and guaranteed Data shown is for 3 3 V For 2 5 V I O derate min by 0 25 nS and max by 0 5 nS Mode setting is mode 14 13 fastest or 01 slowest Data 67 LVTTL VecIO 3 3V mode 14 13 10 fastest N as SCD7365 Rev C 8 25 11 9 Plainview TIMING DIAGRAMS CLOCK TIMING t High t Low trise tran Et SYSTEM INTERFACE TIMING SysAD SysCmd ValidIn ValidOut etc INPUT TIMING SysClock Data OUTPUT TIMING SysClock Data SCD7365 Rev 8 25 11 10 Aeroflex Plainview THERMAL INFORMATION This product is designed to operate over a wide temperature range when used with a heat sink Mazimum long term operating junction temperature to ensure adeguate long term life TBD at 450 MHz Maximum junction temperature for short term excursions with guaranteed continued TBD at 450 MHz functional performance Minimum ambient temperature Device Compact Model Compact Model cs Go Ambient Osa Heat Sink
11. Standard Products MIP7365 64 Bit Superscaler Microprocessor February 17 2012 EROFLEX FEATURES A passion for performance a a Upscreened PMC Sierra RM7065C Military and Industrial Grades Available Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price performance 450MHz operating frequency High performance system interface o Multiplexed address data bus SysAD supports 2 5 V 3 3V I O logic o Processor clock multipliers 2 2 5 3 3 5 4 4 5 5 6 7 8 9 Support for 64 bit or 32 bit external agents Integrated primary and secondary caches o All are 4 way set associative with 32 byte line size o 16 Kbytes instruction 16 Kbytes data 256 Kbytes on chip secondary Per line cache locking in primaries and secondary o Fast Packet Cache increases system efficiency in networking applications High performance floating point unit 1600MFLOPS maximum o Single cycle repeat rate for common single precision operations and some double precision operations o Single cycle repeat rate for single precision combined multiply add operations o Two cycle repeat rate for double precision multiply and double precision combined multiply add operations MIPS IV superset instruction set architecture o Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution o Single cycle floating point multiply add Integrated memory
12. ata Identifier Bus Parity For the MIP7365 unused on input and zero on output SCD7365 Rev 8 25 11 4 Aeroflex Plainview Clock Control Interface PIN NAME TYPE DESCRIPTION SysClock Input System clock Master clock input used as the system interface reference clock All output timings are relative to this input clock Pipeline operation freguency is derived by multiplying this clock up by the factor selected during boot initialization SysClock Input System clock Differential clock input used only in HSTL mode Set SysClock to VccIO or Do Not Connect for non HSTL operation Power Supply PIN NAME TYPE DESCRIPTION VccP Input Vcc for PLL Quiet VccInt for the internal phase locked loop Must be connected to VccInt through a filter circuit VREF In Reference voltage for HSTL I O Do not connect for non HSTL VssP Input Vss for PLL Quiet Vss for the internal phase locked loop Must be connected to Vss through a filter circuit Interrupt Interface PIN NAME TYPE DESCRIPTION INT 9 0 Input Interrupt Ten general processor interrupts bit wise ORed with bits 9 0 of the interrupt register NMI Input Non maskable interrupt Non maskable interrupt ORed with bit 15 of the interrupt register bit 6 in R5000 compatibility mode SCD7365 Rev C 8 25 11 5 Aeroflex Plainview JTAG Interface JTRST JTAG reset Notes 1 The JTRST input was added to the RM70xxC and RM79xx CPUS to directly control the reset to
13. d control of the system interface RspSwap Input Response Swap RspSwap is used by the external agent to signal the processor when it is about to return a memory reference out of order i e of two outstanding memory references the data for the second reference is being returned ahead of the data for the first reference In order that the processor will have time to switch the address to the tertiary cache this signal must be asserted a minimum of two cycles prior to the data itself being presented Note that this signal works as a toggle i e for each cycle that it is held asserted the order of return is reversed By default anytime the processor issues a second read it is assumed that the reads will be returned in Order i e no action is required if the reads are indeed returned in order This is enabled by Mode Bit 26 Output Read Type During the address cycle of a read request RdType indicates whether the read request is an instruction read or a data read SysAD 63 0 Input Output System address data bus A 64 bit address and data bus for communication between the processor and an external agent SysADC 7 0 Input Output System address data check bus An 8 bit bus containing parity check bits for the SysAD bus during data cycles SysCmd 8 0 Input Output System command data identifier bus A 9 bit bus for command and data identifier transmission between the processor and an external agent SysCmdP Input Output System Command D
14. e Data In Serial boot mode data input HSTL Sel Input HSTL VTL Control Asserting this signal low places the system I O pins in HSTL mode Pulling this signal high or allowing to float places all system I O pins in LVTLL mode Notes 1 In HSTL mode maximum voltage level of ModeClock is determined by VccJ level 2 SysClock VREF In and HSTL SEL signal pin are no connect on LVTTL mode 3 Functionality of the HSTL mode is not tested by Aeroflex and guaranteed to work at Industrial temperatures only SCD7365 Rev C 8 25 11 6 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS SYMBOL RATING RANGE UNITS Terminal Voltage with respect to Vss 0 52 to 3 9 Operating Temperature I Industrial 40 to 485 R Extended 55 to 110 55 0 125 55 to 125 Notes 1 Stresses above those listed under Absolute Maximums Rating may cause permanent damage to the device This is stress rating only Military Military Screened VIN minimum When VIN lt or VIN No more than one output should shorted at one time Duration of the short should not exceed more than 30 second and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability 2 0V for pulse width less than 15nS VIN maximum shou
15. ed by the spherical crowns of the solder balls All dimensions in inches Dimensioning and tolerancing per ASME Y 14 5M 1994 After surface mount assembly solder ball will have 0 006 TYP collapse in A dimension 9 Substrate base material is copper 10 Package top surface shall be black 11 Cavity depth maximum is 020 SCD7365 Rev 8 25 11 17 Aeroflex Plainview MIP7365 256 TBGA NUMERICAL PINOUT vs FUNCTION 1 2 Function Function Function Function ee ee a m vs veo e ve vs B5 B6 _ smaxs _ sw sysapco Br smans swabso sysAD29 616 Do Not Connect veo DoNorcomea or vem vem D veo vem wem veo o smaxs D vem ses som ss Seen vs we swa Sas veo Sea N vem sa SCD7365 Rev C 8 25 11 18 Aeroflex Plainview MIP7365 256 TBGA NUMERICAL PINOUT vs FUNCTION 1 2 Pim Function Pi Function Pin Function Pin Function Pr sms P2 pa vem coReset Rese m vs r DonotConnect m vem Rie ms nm vs m eer mo veo nw Wer D
16. ld not exceed 3 95 Volts RECOMMENDED OPERATING CONDITIONS TEMP CASE CPU GRADE Industrial 450 MHz Extended 450 MHz Military 450 MHz Notes 1 3 V 50 mV 1 3 V 50 mV 1 3 V 50 mV 40 C to 85 C VccIO 33 V 150 mV or 2 5 V 200 mV Note 6 3 3 150 mV 2 5 V 200 mV Note 6 33 V 150 mV 2 5 V 200 mV 6 1 3 V 50 mV 1 3 V 50 mV 1 3 V 50 mV 1 should not exceed VccInt by greater than 2 5 V during the power up sequence 2 Applying a logic high state to any I O pin before VccInt becomes stable is not recommended 3 As specified in IEEE 1149 1 JTAG the JTMS pin must be held high during reset to avoid entering JTAG test mode Refer to the RM7000 User Manual 3 3 V 150 mV 2 5 V 200 mV 6 33 150 mV 2 5 V 200 mV 6 33 V 150 mV 2 5 200 mV 6 4 VccP must connected to Vcclnt through passive filter circuit See 7000 User Manual fo recommended circuit 5 Contact factory for extended military temperature range products CQFP hermetic MCM packages will be screened at 55 to 125 6 These voltages are recommended for HSTL mode operations only HSTL mode operation is guaranteed at Industrial temperatures only SCD7365 Rev C 8 25 11 Aeroflex Plainview DC ELECTRICAL CHARACTERISTICS VeclO 3 15 3 45V PARAMETER MINIMUM MAXIMUM CONDITIONS
17. leads where leads exit plastic body at datum plane H To be determined at seating plane C A Dimensions do not include mold protrusion Allowable mold protrusion is 0 254 mm on dimensions 6 216 is the total number of terminals These dimensions to be determined at datum plane H Package top dimensions are smaller than bottom dimensions and top of package will not overhang bottom of package Dimension does not include Dambar protrusion Allowable Dambar protrusion shall be 0 08 mm total in excess of the dimension at maximum material condition Dambar cannot be located on the lower radius or the foot 10 Controlling dimension millimeter 11 Maximum allowable die thickness to be assembled in this package family is 0 38 mm 12 This outline conforms to JEDEC publication 95 registration MS 026 variation BGB Defined as the distance from the seating plane to the lowest point of the package body 14 Exposed pad shall be coplanar with bottom of package within 0 05 Corner chamfer of exposed die pad shall be within 0 30 mm SCD7365 Rev D 2 17 12 13 Aeroflex Plainview MIP7365 216 EPad LQFP NUMERICAL PINOUT vs FUNCTION 12 FUNCTION E FUNCTION PIN FUNCTION ColdReset SysCmdl RspSwap PIN UNCTION Do Not Connect Do Not Connect o Not Connect Do Not Connect 1 NN za 7 L 35g 1 357 m m KA KA EN EA 98 ES ES X PETNI EA E INI E
18. management unit o Fully associative joint TLB shared by I and D translations 64 48 dual entries map 128 96 pages o Variable page size Embedded application enhancements o Specialized DSP integer Multiply Accumulate instructions MAD MADU and three operand multiply instruction MUL o I amp D Test Break point Watch registers for emulation amp debug Performance counter for system and software tuning amp debug Fourteen fully prioritized vectored interrupts 10 external 2 internal 2 software Fully static CMOS design with dynamic power down logic 216 EPad LQFP 24x24mm are pin compatible with the RM7965 and RM5261A EPad products NOTE 216 Enhanced Pad package EPad MIPS64 and Fast Packet Cache are Trademarks of PMC Sierra SCD7365 Rev D On chip 256 Byte Secondary Cache 4 way Set Associative Secondary Tags Secondary Tags Secondary Tags Secondary Tags SetA SetB Set Set D Primary Data Cache Primary Instruction Cache 4 way Set Associative 4 way Set Associative DTLB ITLB A D Bus Pad Buffer Address Buffer Pad Bus Prefetch Buffer Instruction Dispatch Unit F Pipe Register M Pipe Register M Pipe Bus D Bus _ emm Floating Point Load Align Joint TLB VA Load Aligner ile M Pipe F Pipe Adder Adder T Write Buffer Read Buffer Packer Unpacker System Memory Control IVA Comparator StAIn Sh PC Incrementer Floating Point MultAdd Add Sub
19. the state machine boundary scan test equipment must be able to drive JTRST high to allow boundary scan operation 2 The JTRST input must be connected to GND Vss through a 220 to 1 pull down resistor to force the state machine into the reset state to allow normal operation JTAG boundary scan mode disabled 3 The interface electrical characteristics are dependent on the VccJ level chosen 2 5 V or 3 3 V Initialization Interface PIN NAME TYPE DESCRIPTION BigEndian Input Big Endian Little Endian Control Allows the system to change the processor addressing VccOK Input is OK When asserted this signal indicates to the MIP7365 that the VccInt power supply has been above the recommended value for more than 100 milliseconds and will remain stable The assertion of VccOK initiates the reading of the boot time mode control serial stream ColdReset Input Cold Reset This signal must be asserted for a power on reset or a cold reset ColdReset must be de asserted synchronously with SysClock Reset Input Reset This signal must be asserted for any reset sequence It may be asserted synchronously or asynchronously for a cold reset or synchronously to initiate a warm reset Reset must be de asserted synchronously with SysClock ModeClock Output Boot Mode Clock Serial boot mode data clock output at the system clock frequency divided by two hundred and fifty six Modein Input Boot Mod

MIP7365 64-bit Superscaler Microprocessor (6/07)

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