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VSBC-32 - Kontron

1. ID 21168 Rev 04 PEP Modular Computers GmbH Page A 3 VSBC 32 r A 2 DM600 Memory Piggybacks The DM600 is a memory piggyback fitted with 4 Flash 1 2 4 A 2 1Board Layout and Jumper Location Figure A 1 DM600 Memory Piggyback Legend 1 Flash Memory 2 DRAM A 2 2 Jumper Description and Flash Addresses III LITT 49 50 LITT T LLLLLLLLLELLLLLLELLLELELLLELEI LITITITILITITIITITITITITTILI 50 Table A 2 Jumper J1 Settings and Flash Memory Address Ranges All flash EP ROM s write protected Open 1 2 No Protection 1 3 Flash Bank 1 Write protected Upper 512 KB Upper 2 MB Flash Bank 1 Address Range 0x04080000 0x04020000 0x04100000 0x04400000 1 4 Flash Bank 0 Write protected Lower 512 KB Lower 2 MB Flash Bank 0 Address Range 0x04000000 0x04000000 0 04000000 0 04080000 0 04200000 0 04200000 Default settings are in italics 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 A 3 DM601 Memory Piggybacks The DM601 is a memory piggyback fitted with 16 Flash Memory 1 2 or 4 A 3 1Board Layout and Jumper Location Figure A 2 DM601 Memory Piggyback Legend 1 Flash Memory 2 DRAM A 3 2 Jumper Description and F
2. s os 72 72 77 72 72 RS I RS232 non optoisolated or RS485 optoisolated 10Base 10Base2 or 10Base5 or 10BaseT Ethernet Serial or Ethernet Ethernet with VSBC 32E only Page 1 8 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction 1 3 2 Frontpanels Figure 1 2 VSBC 32 E Frontpanel LED s Green U General purpose Yellow W Watchdog Red Halt Pushbuttons RST left Reset AB right Abort SI Piggyback Frontend Connector s The additional frontend ID 21168 Rev 04 PEP Modular Computers GmbH Page 1 9 VSBC 32 Introduction m 1 3 3 Board Layouts Figure 1 3 VSBC 32 E Board Diagram front J12 J11 poul mm FLASH EPROM Upper Data D8 D15 even Byte addresses Lower Data 00 07 odd Byte addresses BDM Background Debug Mode Page 1 10 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction Figure 1 4 VSBC 32 E Board Diagram reverse Warning Solder jumpers factory set avoid possible damage to your equiment please do not alter them ID 21168 Rev 04 PEP Modular Computers GmbH Page 1 11 VSBC 32 r Introduction 1
3. Note When using an 8TE board on the CXC5 and CXC8 backplane one slot is lost between each board and the next 8 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 OS 9 Cabling Appendix D OS 9 Cabling ID 21168 Rev 04 PEP Modular Computers GmbH D 1 This page was intentionally left blank D 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 OS 9 Cabling 5 9 Cabling This appendix outlines the connection definitions of OS 9 systems to various outside media D 1 OS 9 System Terminal D 1 1 Software XON XOFF or No Handshake Figure D 1 15 Pin Connector on OS 9 Side 15 pin male 25 pin male 7 GND 7 SIGNAL ground 2 TxD 2 RxD 3 RxD 3 TxD 4 CTS 4 CTS 5 RTS 5 5 6 8 DSR 20 DTR Figure 0 2 8 RJ45 Connector OS 9 Side SMART I O 8 pin RJ45 25 pin male 3 GND 7 GND SIGNAL ground 4 TxD 3 RxD 5 RxD 2 TxD 7 CTS 1 4 RTS 2 RTS 5 CTS 6 DSR 20 DTR ID 21168 Rev 04 PEP Modular Computers GmbH Page D 3 VSBC 32 OS 9 Cabling r Figure D 3 6 RJ12 Connector on OS 9 Side 6 pin RJ12 25 pin male 2 GND 7 GND SIGNAL ground 3 TxD 3 RxD 4 RxD 2 TxD 6 CTS 4 RTS 1 RTS 5 CTS 6 DSR 8 DCD 20 0 1 2 Hardware Handshake Set Terminal to CTS DTR Handshake Figure D 4 15 Pin Connector on OS 9 Side
4. 1 8 1 9 1 3 3 Board 1 10 1 4 Technical Specifications 1 1 12 ID 21168 Rev 04 PEP Modular Computers GmbH Page iii VSBC 32 Contents m 1 5 Applied Sland ardS EN kaa a ke abi ieee an 1 14 19 1 GE ssec ena 1 14 1 5 2 Mechanical Compliance 1 14 Log Environmental Tests 1 14 16 Related Publications estad donat is 1 15 16 1 VMEbus CXC Systems Boards 1 15 1 6 2 Manufacturers Component Documentation 1 15 Chapter 2 2e FPUNCHO Mal DeSCHOION and 2 3 21 General Information dec 2 3 22 u bat lup 2 4 2 2 1 System Control Functionality sisse m kabin ata aje A Di ap 2 4 222 Memory Configurations oec pter ae kk ka ka ik eL bob volal k kman sede 2 5 22 3 DMA Ghannels 2 6 2 24 Serial Communications Control 2 7 2 3 Functional Block Diagram t 2 10 24 Board Interface aw asa ao sten a aa ii TT 2 11 2 4 1 Serial O Interfaces M C 2 11 2 4 2 Piggyback Interface Connectors for Serial Interface Piggybacks 2 12 2 4 3 Memory Piggyback Interface Connectors
5. 3 4 3 2 Software Installation 3 4 Chapter 4 4 oor e tc 4 3 4 1 Hardware Configuration 4 3 41 1 4 3 41 2 Solder JUMPS Rm 4 4 4 2 Software Configuration ius ko ougan ai aa a k km m ap n Ta a on BEER PNE n n pa AS 4 5 Address Mab ak l an n n kan en 4 5 4 22 Board Control Slatus Register diese abire din ce 4 6 4 2 3 VMEbus Control Status Register sess 4 7 4 2 4 VMEbus Interrupt Mask Register 4 8 ID 21168 Rev 04 PEP Modular Computers GmbH Page v VSBC 32 Contents r A Memory Piggybacks aka aa a pa 3 AAA General carrer ana na a tan na ok ak ol a aa E ik a sa l ala 3 A 4 A 2 1 Board Layout and Jumper Location A 4 A 2 2 Jumper Description and Flash Addresses A 4 5 A 3 1 Board Layout and Jumper Location 5 A 3 2 Jumper Description and Flash Addresses A 5 A4 DM602 qct T shu npadata A 6 A 4 1 Board Layout and Jumper Location
6. 2 12 244 EPROM DIP Sockets Rd 2 12 2 4 5 Background Debug Mode Interface 2 138 2 46 VMEbus Backplane Interface 2 13 24 7 Mezzanine Interface 2 14 2 5 VSBC to VSBC 32 System Upgrading 2 15 2 6 Special Board Functions 2 18 26 1 Real Tim CIock ond kdk an ab iinet ano ek ka DO sd pa AAA DADE 2 18 5282 era na Di 2 18 PLL Operation Mod u PT 2 18 26 4 TICK G eneral0P rr 2 18 2 6 5 2 19 Page iv PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Contents 2 6 6 Watchdog 2 20 26 7 FOSE 8001008 a0 ant t it ti aide di t a aa kaka ko kak 2 20 26 8 Slot 1 Detection no ia e io pk 2 20 2 7 Frontpanel Functions Dovilas 2 21 2 8 HTC and SRAM Data Retention 2 21 29 Address Decode ki dos e ae k k dee 2 23 2 9 1 Basic P 2 23 2 9 2 Boot Decoding 2 23 Chapter 3 3 Installation 3 1 Hardware Installation 3 3 3 1 1 External Serial Interface Module
7. Default settings are in italics Table B 6 Jumper 43 Shielding Open Unshielded 100 ohm termination Set Shielded 150ohm termination Default settings are in italics ID 21168 Rev 04 PEP Modular Computers GmbH Page B 7 VSBC 32 Serial Interface Piggybacks r B 5 SI PB232 The SI PB232 provides two RS 232 serial interfaces to the 68EN360 Controller chip It connects one of the range of PEP CPU boards via two RJ45 telephone jacks B 5 1 Front Panel View and Pinout Figure B 4 SI PB232 Serial Interface Piggyback CA Pine a E HJ45 v Connector Pint SCC1 Connector Pint 9 SCC4 Table B 7 SI PB232 Connectors SER1 and SER2 Pinouts u aj A N H gt lt o 8 Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Serial Interface Piggybacks B 6 SI PB485 ISO The SI PB485 ISO is an RS 485 optoisolated interface piggyback for 2 wire half duplex PROFIBUS connection It has one LED fitted indicating data transmission B 6 1 Specifications On board termination 150ohm jumper selectable Isolation voltage Optocoupler specified up to 2 5kV Max baudrate 1 5MBaud B 6 2 Front Panel View Jumper Layout and Pinout Figure B 5 SI PB485 ISO Serial Interface Piggyback 9 D Sub Pin1 9 Pin 6 female Pin 9 SCC1 Pin 5 amp a Transmit Yellow
8. A 6 A 4 2 Jumper Description and Flash Addresses 2 A 6 occ no A 7 A 5 1 Board Layout and Jumper Location sss A 7 A 5 2 Jumper Description and Flash Addresses A 7 MER OU dal A 8 A 6 1 Board Layout and Jumper Location A 8 A 6 2 Jumper Description and Flash Addresses A 8 7 DM605 A 9 A 7 1 Board Layout and Jumper Location eese A 9 A 7 2 Jumper Description and Flash Addresses A 9 Page vi PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Contents Appx B Serial Interface PIYGYDACKS p a pp vain pd ka man dan B 3 General najem k non tn na ana ia kan a is aw un otvo B 3 B2 SI UI at oken iya ske ee ees B 4 Specifications ROUTE B 4 B22 Front Panel 2 luto bou ia B 4 CIR 5 kons ton etan o B 5 B 5 B 3 2 Front Panel View Pinout B 5 B4 o ao B 6 BAT Sp IfiCall lS 6 B 4 2 Front Panel View Jumper Layout and Pinouts B 6 4 2 1 SI 10BT Jumper Settings eo
9. Explanation of Symbols CE Conformity This symbol indicates that the product described in this manual is in compliance with all applied CE standards Please refer also to the section Applied Standards in this manual Caution Electric Shock A This symbol and title warn of hazards due to electrical shocks gt 60V when touching products or parts of them Failure to observe the precautions indicated and or prescribed by the law may endanger your life nealth and or result in damage to your material Please refer also to the section High Voltage Safety Instruc tions on the following page This symbol and title inform that electronic boards and their components are sensitive to static electricity Therefore care must be taken during all handling operations and inspections of this product in order to ensure product integrity at all times jo Warning ESD Sensitive Device 4 Please read also the section Special Handling and Unpacking Instructions on the following page Warning This symbol and title emphasize points which if not fully under stood and taken into consideration by the reader may endanger your health and or result in damage to your material Note This symbol and title emphasize aspects the reader should read through carefully for his or her own advantage PEP Advantage modular computers This symbol and title emphasize advantages or positive aspects of a product
10. Table A 6 Jumpers J1 and 42 Settings and Flash Memory Address Ranges No Protection Set Ji Open Flash Bank 0 Write protected Lower 512 Lower2 Flash Bank 0 Address Range 0 04000000 0x04000000 0 04080000 0 04200000 Set No Protection Open Flash Bank 1 Write protected Upper 512 2 42 1 only Flash Bank 1 Address Range 0 04080000 0x04020000 0 04100000 0 04400000 8 PEP Modular Computers GmbH ID 21168 Rev 04 Figure 6 DM605 ory Piggyback Legend 1 Flash Memory 2 DRAM VSBC 32 A 7 DM605 The DM605 is a memory piggyback fitted with DRAM 64 MB FLASH MEMORY 1or 4 MB A 7 1 Board Layout and Jumper Location Memory Piggybacks A 7 2 Jumper Description and Flash Addresses 49 TUT HEEEBEHEEEEEEEEHEHEEEEEEENHEEN 50 Table A 7 Jumpers J1 and J2 Settings and Flash Memory Address Ranges Set No Protection Ji Open Flash Bank 0 Write protected Lower 512 Lower2 Flash Bank 0 Address Range 0x04000000 0x04000000 0 04080000 0 04200000 Set No Protection Open Flash Bank 1 Write protected Upper 512 2 J2 IMB only Flash Bank 1 Address Range 0 04080000 0x04020000 0 04100000 0 04400000 Default settings are in italics ID 21168 Rev 04 PEP Modular Computers GmbH a Pa
11. 2 TxD 6 RTS 5 RTS iors Page D 10 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 OS 9 Cabling D 4 2 Hardware Handshake Figure D 21 15 pin Connector 15 pin male 15 pin male 7 GND 7 GND SIGNAL ground 2 xD 3 RxD 3 RD 2 TD 4 10 DTR 10 4 CTS Figure 0 22 8 RJ45 Connector SMART 1 0 8 pin RJ45 15 pin male 3 GND 7 GND SIGNAL ground 4 TxD n 3RD 5 RD 2 7 CTS 10 DTR 8 e 4 CTS ID 21168 Rev 04 PEP Modular Computers GmbH Page D 11 This page was intentionally left blank D 12 PEP Modular Computers GmbH ID 21168 Rev 04
12. Modular Computers VSBC 32 Combined VMEbus System Controller and Serial Communications Controller Board Manual ID 21168 Rev Index 04 Jul 00 The product described in this manual is in compliance with all applied CE stan dards General VSBC 32 po Revision History Manual Product Title VSBC 32 Manual ID Number 21168 Rey Brief Description of Changes Board Index Bate of Index Issue 0100 Initial Issue 00 1 Aug 95 0200 General corrections 00 2 Dec 95 0201 J9 default setting changed 00 2 Nov 96 0300 General corrections and new manual structure 01 Dec 96 0301 New Preface 01 Aug 98 0311 Improvement to Fig 2 1 3 In Appendices 01 Sept 98 tions to flash addresses on pages 2 to MEM 4 page 5 replaced 04 Information of Errata Sheets 0100 1 2 integrated 01 July 00 adequate manual structure new memory piggy backs mentioned description of combined system and communications controller fucntionality function related board diagrams coherent termi nology e g processor and board variant names etc Appendices modified updated reduced Imprint Copyright 2000 PEP Modular Computers GmbH All rights reserved This manual may not be copied photocopied repro duced translated or converted to any electronic or machine readable form in whole or in part without prior written approval of Modular Computers e PEP Modular Computers GmbH
13. with the controller or placed to the right of the VSBC 32 E In the first case communication between the controller and the module is acchieved via the VSBC 32 E s on board CXC connector the second case via the VMEbus As the CXM SIOS can be used again as a carrier for various serial interface SI and serial communications SC piggybacks the VSBC 32 CXM SIO3 tandem represents a really powerful and versatile sytem control and serial communications control set Together with the two service debug interfaces a maximum of three four with the serial interface piggyback fitted completely configured serial interfaces are available for the base board Three two with serial interface piggyback fitted serial interfaces may be configured via the VMEbus where three of the four full modem Interfaces are routed The VSBC 32 E allows also a significant variety of memory configurations mainly DRAM and flash memory located on special memory piggybacks add on flash EPROM on DIP sockets battery backed up SRAM and EEPROM ID 21168 Rev 04 PEP Modular Computers GmbH Page2 3 VSBC 32 Functional Description r 2 2 Specifics 2 2 1 System Control Functionality Under the aspect of system control the on chip 32 bit CPU core of the Motorola MC68 EN 360 provides system integration at different processor freguencies The pro cessor core acts essentially as a Motorola CPU32 microprocessor operating at 25MHz or 33MHz without cache mem
14. 15 pin male 25 pin male 7 GND 7 GND SIGNAL ground 2 TxD 3 RD 3 RD 2 TxD 4CIS 20 DTR 10 5 CTS B 6 DSR C Figure D 5 8 pin RJ45 Connector on OS 9 Side SMART 1 0 8 pin RJ45 25 pin male 3 GND 7 GND SIGNAL ground 4 TD 3 RxD 5 RD Rs 2 7 CTS 20 DTR 8 DTR 5 CTS B 6 DSR 8 DCD PageD 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 OS 9 Cabling D 2 OS 9 System PC 0 2 1 Software XON XOFF or Handshake Figure D 6 15 pin Connector on OS 9 Side 25 pin Connector on PC Side 15 pin male 25 pin female 7 GND 7 GND SIGNAL ground 2 TxD 3 RD 3 RAD 2 4 CTS 5 CTS 5 RTS 6 DSR 8 DCD 20 DTR Figure D 7 15 pin Connector on OS 9 Side 9 pin Connector on PC Side 15 pin male 9 pin female 7 GND 7 GND SIGNAL ground 2 TxD 2 RxD 3 RxD 3 TxD 4 CTS 8 CTS 5 RTS 6 DSR 1 DCD 4 DTR ID 21168 Rev 04 PEP Modular Computers GmbH Page D 5 VSBC 32 5 9 Cabling r Figure D 8 8 RJ45 Connector on OS 9 Side SMART I O 25 Pin Connector on PC Side 8 pin RJ45 25 pin female 3 GND 7 GND SIGNAL ground 4 TxD 3 RxD 5 2 7 CTS 1 5 CTS 2 RTS 6 DSR 8 DCD 20 DTR Figure D 9 6 pin RJ12 Connector on OS 9 Side 25 Pin Connector on PC Side 6 pin RJ12 25 pin female
15. 54 0xB4000000 0x14000000 0x14000000 BU7 55 0xB5000000 0 15000000 0 15000000 56 0xB6000000 0x16000000 0x16000000 BUO 557 0xB7000000 0x17000000 0x17000000 is the system slot On 55 85 and 8ES for CXM STATI only Page C 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 C 2 CXC Generic Pinouts Table 1 3 CXC Connector Pinouts SERI RCLK User defined CXC 1 2 IRQ 2 SER1 TCLK _ _ 3 IRQ 3 GND _DMA_REQ 4 IRQ 4 SERI TXD User defined 5 User defined SERI RTS SER3 TCLK 6 User defined GND SER3 RCLK 7 VCC SER3_RTS VCC 8 User defined SER3 CD SER3 TXD 9 User defined GND SER3 RXD 10 User defined SERI RXD User defined 11 SER2 DTR User defined SER2 CD 12 SER3 DTR GND SER2 5 13 SERI SERI CTS SER2 CTS 14 SERI CD VCC 15 _CS CXC GND SER2_TCLK 16 _AS SER3 CTS SER2 RCLK 17 R W _SYSR SER2 TXD 18 VpS GND SER2 RXD 19 21052 _EDTACK VCC 20 VCC CXC CLK C521 21 Al GND _CS3 22 2 50 _ 54 23 51 24 4 GND _ 561 25 5 _ 57 26 VCC A7 27 DO GND 010 28 01 06 011 29 02 07 012 30 03 GND 013 31 04 08 014 32 05 09 015 1 Normally active low by R W only _ W ID 21168 Rev 04 PEP Modular Computers GmbH 5 VSBC 32 CXC r C 3 CPU Pinout Cross Reference The table b
16. 6 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Memory Piggybacks A 5 DM603 The DM603 is a memory piggyback fitted with DRAM 32 MB FLASH MEMORY 0 0 5 512 KB 1 2 or 4 A 5 1 Board Layout and Jumper Location Figure A 4 DM603 Mem ory Piggyback Legend 1 Flash Memory 2 DRAM ai 5 2 Jumper Description and Flash Addresses Table 5 Jumpers J1 and J2 Settings and Flash Memory Address Ranges Set No Protection Flash Bank 0 Write protected Lower 512 KB Lower 2 Flash Bank 0 Address Range 0x04000000 0x04000000 0x04000000 0x04080000 0x04200000 0x04200000 Set No Protection Open Flash Bank 1 Write protected Upper 512 KB Upper 2 MB J2 1MB only Flash Bank 1 Address Range 0x04080000 0x04020000 0x04100000 0x04400000 Default settings are in italics A ID 21168 Rev 04 PEP Modular Computers GmbH Page A 7 VSBC 32 r A 6 DM604 The DM604 is a memory piggyback fitted with 8 FLASH 1 4 A 6 1 Board Layout and Jumper Location Figure A 5 DM604 Mem ory Piggyback Legend 1 Flash Memory 2 DRAM Memory Piggybacks 1 2 A 6 2 Jumper Description and Flash Addresses 2 LLLLLLLLEL ELE LLEL LL LLLLLLI 49 LLLLLLLLLELLLLLLLLLELLLLLELELEI 50 49 50
17. data bus seven address lines and eight decoded chip select lines Each select line has 256 Bytes In total there are eight select signals C 1 CXC Address Ranges The following tables provide address range information for both the CXC standard back planes as well as the enhanced CXC backplanes ECXC for the CPU boards indicated Table C 1 CXC Address Range BU2 cso OxF 70000 0 1 70000 70000 0xCBF70000 0xB0000000 BU3 51 0 70400 0 1 70400 70400 OxCBF70400 0xB1000000 BU4 CS2 0xF 70800 0 1 70800 70800 OxCBF70800 0xB2000000 BU5 CS3 0xF 70C 00 0 1 70 00 0x0BF70C00 70 0xB3000000 BU6 54 0 71000 0 1 71000 0x0BF71000 OxCBF71000 0xB4000000 BU7 55 OxF 71400 0 1 71400 71400 71400 0xB5000000 56 0 71800 OxC1F71800 0x0BF71800 OxCBF71800 0xB6000000 BU0 CS7 0 71 00 OxC1F71C00 71 71 0xB7000000 4 is the system slot 55 85 and 8 5 for CXM STAT1 only ID 21168 Rev 04 PEP Modular Computers GmbH 3 VSBC 32 CXC r Table 1 2 Enhanced CXC Address Range BU2 50 0xB0000000 0x10000000 0x10000000 BU3 51 0xB1000000 0x11000000 0x11000000 BU4 52 0 2000000 0 12000000 0 12000000 BU5 53 0 83000000 0 13000000 0 13000000 806
18. 2 GND 7 GND SIGNAL ground 3 TxD 3 RxD 4 RD 2 6 CTS TI 5 CTS 1 RTS 6 DSR 8 DCD 20 DTR Figure 0 10 8 Pin RJ45 Connector on OS 9 Side SMART 9 Pin Connector on PC Side 3 GND 5 GND SIGNAL ground 4 TxD 2 5 RxD 7 CTS 2 RTS L Page D 6 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 OS 9 Cabling Figure D 11 6 pin RJ12 Connector on OS 9 Side 9 pin Connedctor on PC Side 6 pin RJ12 9 pin female 2 GND 5 GND SIGNAL ground 3 TxD 2 RD 4 3 TxD 6 CTS TI 8 CTS 1 RTS 6 DSR 1 DCD 4 DTR D 2 2 Hardware Handshake Select RTS CTS Handshake on the PC Side Figure D 12 15 pin Connector on OS 9 Side 25 pin Connector on PC Side 15 pin male 25 pin female 7 GND 7 GND SIGNAL ground 2 TxD 3 RxD 3 RxD 2 TxD 4 4 RTS 10 DTR 5 CTS 6 DSR 8 DCD 20 Figure 0 13 15 Connector OS 9 Side 9 Connector Side 15 pin male 9 female 7 GND or 5 GND SIGNAL ground 2 TxD 2 RxD 3 RxD 3 TxD 4 CTS 7 RTS 10 DTR 8 CTS 6 DSR 1 DCD 4 DTR ID 21168 Rev 04 PEP Modular Computers GmbH D 7 VSBC 32 5 9 Cabling r Figure D 14 8 RJ45 Connector on OS 9 Side SMART I O 25 Pin Connector PC Side 8 pin RJ45 25 pin female 3 GND 7 GND SIGNAL ground 4 TxD 3 RxD 5 RxD 2 TxD 7 CTS 4 RTS 8 5 CTS 6 DSR B 8 DCD 20
19. 360 which are called user defined in the generic CXC Specification are not part of the VSBC 32 E VMEbus or CXC specification Although the SMCs are configured on the mainboard these ports are also integrated on the VMEbus CXC because of possible ISDN applications where SMCs can be inte grated and other protocols supported by the MC68 EN 360 Note If the RCLK2 signal VMEbus CXM pin C16 is required jumper J4 24MHz clock must be opened and the serial drivers deliv ered by PEP Modular Computers must be modified ID 21168 Rev 04 PEP Modular Computers GmbH 2 15 VSBC 32 Functional Description r Table 2 5 IUC IUC 32 Porting Information Sheet 1 of 2 E IRQ 1 A1 Yes PCO IRQ 2 A2 Yes 1 IRQ 3 A3 Yes PC2 IRQ 4 A4 Yes PC3 DMA ACK 2 Yes PB5 DMA REQ Yes PB4 SERI RCLK Bl Yes PA8 SERI TCLK B2 Yes 10 SERI TXD B4 Yes PA3 SERI RXD B10 Yes 2 SERI RTS B5 Yes PB13 SERI DTR A13 Yes PB17 SERI CTS B13 Yes PC6 SERI CD B14 Yes PC7 SER2 RCLK C16 Yes PA13 Cannot be used if J 4 is set 3 SER2 TCLK C15 Yes PA12 SER2 TXD C17 Yes PA5 SER2 RXD C18 Yes PA4 SER2 RTS C12 Yes PB14 SER2 DTR Yes 16 SER2 CTS Yes SER2 CD Yes 9 SER3 C6 Yes 15 Not usable if SI piggyb
20. 4 Technical Specifications Table 1 2 VSBC 32 E Technical Specification Sheet 1 of 3 VSBC 32 Communications Controller Board Variants MC 68360 processor e VSBC 32E MC68EN360 processor Combined CPU Serial MC68360 25 MHz no Ethernet capability e MC68EN360 25MHz or 33 MHz Ethernet capability CPU performance Equivalent to Motorola CPU32 Serial 1 0 perform RISC 14 dedicated DMA channels On Board Memory SRAM 256kB or 1MB dual ported backed up by means of Gold Caps Note 1MB with VSBC 32E only 2 kbit serial 1 kbit available for applications Flash EPROM 256kB or 1MB DIP EPROM flash 16 bit access Minimum access time 120ns EEPROM Memory on Piggybacks DRAM 1 4 16 or 32 MB 32 bit access Flash 0 0 5 1 2 or 4 MB 32 bit access VMEbus Master Slave Master A24 D16 D8 arbitration AM codes Functionality Slave A24 D16 dual port RAM mailbox IRQ Interrupt Control 7 level CXC VME IRQ handler maskable via CXC VME inter rupt mask register system vectors ACFAIL via VME Level 7 autovectored Abort Level 7 autovectored Tick Level 6 autovectored Mailbox IRQ Level 5 autovectored maskable SYSFAIL Level 3 autovectored 16 on board interrupters levels vectors programmable Programmable Timers Tick Periodic interrupt timer Watchdog 512ms time out for reset On board bus error 8u s General purpose 4 16 bit or 2 32 bit Special Funct
21. DONE2 User defined CD2 PC9 CD3 LIRSYNCB SER2 CD 12 52 14 RTS3 LIRQB LIST3 SER2 RTS C13 CTS2 PC8 53 LITSYNCB SDACK2 SER2 CTS 15 TCLK2 PAI2 CLK5 BRGO3 TIN3 SER2 TCLK C16 RCLK2 PA13 CLK6 TOUT3 LIRCLKB BRGCLK2 SER2 RCLK C17 TXD2 PAS TXD3 LIRXDB SER2 TXD C18 RXD2 PA4 RXD3 LITXDB SER2 RXD C 6 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 CXC C 4 Timing Figure 1 Signal Timing 1 7 AS _LDS _UDS RA W _EDTACK DO D15 _CXC CSx Read Write Legend Min Max 1 Address valid to AS DS 10ns 2 _AS asserted 80ns 3 _AS negated to R _W invalid 10ns 4 Data in valid to EDTACK Ons 5 CXC CSx asserted to AS valid 25ns 6 _EDTACK negated to AS negated Ons 90ns 7 Data in hold time Ons 50ns 8 _AS negated 50ns 9 AS R W asserted to DS asserted 20ns 10 Data out valid to DS asserted 15ns 11 AS DS negated to data out invalid Ons A1 A7 address lines _AS address strobe _LDS _UDS lower upper data strobe R _W read not write _EDTACK external data transfer acknowledge _CXC CSx CXC CS0 to_CXC CS7 Recommended Assert EDTACK with CSx and UDS LDS and data valid during read cycles Latch data with CSx and_UDS LDS during write cycles Negate EDTACK with UDS LDS invalid A ID 21168 Rev 04 PEP Modular Computers GmbH Page C 7 VSBC 32 CXC r C 5 CXC Backplanes CXC2 CXC5 2 3 CXC8 CS cs CS CS cs 0 1 2
22. Default Address 0x OD 00 00 05 Figure 4 3 CS7 0x5 Bitmap 7 P_IRQ5 6 5 4 3 EN DPR EN BERR2 FSD BADR3 Table 4 7 Register Description Configuration 2 1 0 BADR2 BADR1 BADRO P_IRQS 1 0 0 0 0 Mailbox interrupt pending bit 7 Dual port SRAM incl mailbox EN_DPR 1 0 0 Value stored in interrupts enabled for VME bus bit 6 EEPROM requester Base address estab lished through bits BADRO 3 Enables the VME bus error timer pg 1 0 0 1 0 all VMEbus cycles Timeout 128 s FSD 1 1 0 1 0 VMEbus slot 1 detection flag of bit 4 system controller VMEbus address location of dual ported SRAM Equivalent to BADR3 Valie storediin VMEbus address lines A23 A20 0 0 programmable from 00 0 OF QM 1MB windows Enabled by EN DPR See also following table ID 21168 Rev 04 PEP Modular Computers GmbH Page 4 7 VSBC 32 Configuration r Table 4 8 Board Base Addresses 0000 0x 00 00 00 1000 0x 80 00 00 0001 0x 10 00 00 1001 0x 90 00 00 0010 0x 20 00 00 1010 0x AO 00 00 0011 0x 30 00 00 1011 0x BO 00 00 0100 0x 40 00 00 1100 00 00 0101 0x 50 00 00 1101 0x DO 00 00 0110 0x 60 00 00 1110 0x EO 00 00 0111 0 70 00 00 1111 Ox FO 00 00 4 2 4 VMEbus Interrupt Mask Register Address CS7 0x1 Format Byte Access Read write Value after HW Reset 0 Value after Inititalization of Valu
23. and or procedure Page x PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Preface Your new PEP product was developed and tested carefully to provide all features necessary to ensure the renown electrical safety requiremenis It was also designed for a long fault free life However the life expectancy of your product can be drastically reduced by improper treat ment during unpacking and installation Therefore in the interests of your own safety and of the correct operation of your new PEP product you are requested to conform with the follow ing guidelines For Your Safety High Voltage Safety Instructions Warning All operations on this device must be carried out by sufficiently lt skilled personnel only Caution Electric Shock However serious electrical shock hazards exist during all installation repair and maintenance operations with this prod uct Therefore always unplug the power cable to avoid expo sure to hazardous voltage Before installing your new PEP product into a system always ensure that your mains power is switched off This applies also to the installation of piggybacks Special Handling and Unpacking Instructions ESD Sensitive Device 6 Electronic boards and their components sensitive to static electricity Therefore care must be taken during all handling operations and inspections of this product in order to ensure product integrity at all times Do not handle this p
24. connector which can be extended by means of a variety of serial interface piggybacks and or external serial interface mod ules Other piggybacks provide DRAM flash memory Some of the outstanding features of the product described in this manual are VMEbus system and communications controller board Both VMEbus and eCXC connectivity Master slave system controller functionality 32 bit Motorola MC68 EN 360 integrated CPU and communications controller 25Hz or 33Hz CPU frequency CPU on chip background debugging 1 4 16 32 or 64 MB DRAM 0 0 5 1 2 or 4 MB flash memory 256kB or 1 MB SRAM 2kbit serial EEPROM 256 1MB DIP flash EPROM Real time clock backed up Six different communication standards possible Serial RS232 RS485 RS422 on request Ethernet 10Base2 10Base5 or 10BaseT Ethernet Up to six frontpanel serial interface connectors Compatibility with external serial interface module CXM SIO3 Reset and Abort control frontpanel buttons Halt watchdog and general purpose status indicators frontpanel LED s OS 9 and VxWorks drivers 1 2 2 Board Variants Two basic variants of the VSBC 32 E with different processors are available Depend ing on the controller chip used and the SRAM size there are four variants of the VSBC 32 E system and serial communications controller board The distinctive features of the variants are listed in the following Ethernet capability CP
25. level 4 for the MC68 EN 360 CPU internal requests and IRQ level 6 for the MC68 EN 360 serial controller internal requests In addition external interrupt sources can generate autovectored interrupts and an external VMEbus master may require an interrupt by setting a mailbox IRQ in the VMEbus control status register For any detailled information as well as a complete list of the Motorola MC68 EN 360 controller signals please refer to the relating Data Sheet 2 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description Table 2 2 External Autovector and Mailbox Interrupts ABORT ACFAIL MC68 EN 360 pin IRQ7 Autovector 7 Reserved MC68 EN 360 pin IRQ6 Autovector 6 Mailbox IRQ MC68 EN 360 pin IRQ5 Autovector 5 Reserved MC68 EN 360 pin IRQ4 Autovector 4 SYSFAIL MC68 EN 360 pin IRQ3 Autovector 3 Reserved MC68 EN 360 pin IRQ2 Autovector 2 Reserved MC68 EN 360 pin IRQ1 Autovector 1 Mailbox Pending BitP IRQ5 Control status register 2 2 2 Memory Configurations The VSBC 32 E allows a significant variety of memory configurations The special DRAM flash piggybacks DM60x for instance allows the user to take advantage of the on board programming facility to produce low cost upgrades by simply overwriting exist ing stored data This memory can be configured with different memory options allowing remarkable flexibility when customizing memory requirements
26. overall length 0 1000 000 16MB actually available Furthermore the e CXC contains a 4 IRQ capability 4 edge sensitive interrupt requests capability 1 channel DREQ DACK serial ports 3 channels Full MODEM and a set of parallel port signals These special CXC functions are based on the MC68 EN 360 controller resources Page 2 14 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description For general CXC information including generic pinouts and a comparison of the MC68 EN 360 and the MC68302 CPU pinouts on the CXC please refer to the CXC appendix attached to this manual the PEP Modular Computers CXC Reference Manual or to the CXC Specification 2 5 VSBC to VSBC 32 System Upgrading In the following the porting information required by customers wanting to upgrade their VSBC based systems to an VSBC 32 based one is supplied The VMEbus CXC ports SER1 SER2 and SER3 of the MC68302 are equivalent to ports SCC2 SCC3 and SCC4 respectively on the MC68 EN 360 controller chip With regard to special VMEbus CXC capabilities the VMEbus CXC pinout on the VSBC 32 E has been developed to provide maximum compatibility between the stan dard VMEbus CXC functions In addition all signals are available in order to configure two time division multiplexed channels via the VMEbus CXC ISDN PCM GCI and so on Multifunction pins with incompatible functions with regard to the MC68302 and MC68 EN
27. 10Base2 piggyback connected to the SI Interface on the VSBC 32 E Note The CXC bus does not support a 12V power supply Therefore the 10Base5 Ethernet piggyback SI 10B5 cannot be used on the IUC 32 E controller board Serial Channelling The VSBC 32 E mainboard is provided with TxD and RxD signals by the controller s SMC1 and SMC2 channels and supply RS232 interface software handshake XON XOFF capability They are configured as service debug connectors by default All full modem interfaces located on the piggybacks and or CXM SIO3 external serial interface module supply RxD TxD RTS CTS CD DTR and RCLK TCLK Two of the full modem interfaces can be configured on the piggyback interface with a variety of ID 21168 Rev 04 PEP Modular Computers GmbH Page2 7 VSBC 32 Functional Description r serial interface SI piggybacks RS232 RS485 Ethernet The SCC1 channel of the MC68 EN 360 provides the interface to the serial interface SI piggyback installed on the VSBC 32 E All other channels of the controller SCC2 SCC3 and 5 4 are ported to the CXC interface except for the SI PB232 piggyback which has on board additional control provided by the SCC4 channel through the piggyback interface for serial interface piggybacks Thanks to the fact that three out of four SCC channels are routed to the CXC interface connector also an CXM SIO3 external serial interface module can be installed in the sy
28. 15 pin DSUB female connector SI 10BT 10BaseT Ethernet interface one RJ 45 connector Note SI 10B with VSBC 32E only External serial interface modules CXM SIO3 Up to one module Front End Functions Pushbuttons Reset button Abort button LED s Red Halt Yellow Watchdog Green General purpose Data Retention Short term backup RTC and SRAM Via on board gold cap 21 A 3V gt 150 hours Long term backup Via VME 5V stand by line automatic switching between 5V stand by and internal gold cap Typ 300 A 3V Power Supply Typically 5V With SI PB5B 12V ID 21168 Rev 04 PEP Modular Computers GmbH A Page 1 13 VSBC 32 Introduction r Table 1 2 VSBC 32 E Technical Specification Sheet 3 of 3 Power Consumption VSBC 37 typ 3 0W VSBC 32E typ 3 5W Temperature Ranges Operation 0 to 70 standard 40 C to 85 C extended Storage 55 C to 125 C Humidity 0 95 non condensing Dimensions 4HP 3U Eurocard 100mm x 160mm Weight Mainboard 130g Serial interface piggyback 20 30g Memory piggyback 30g 1 5 Applied Standards 1 5 4 CE Compliance The PEP Modular Computers VMEbus and e CXC systems comply with the require ments of the following CE relevant standards e Emission 50081 1 e Immission EN50082 2 Electrical Safety EN60950 1 5 2 Mechanical Compliance Mechanical Di
29. 256 512 2x 27C010 or 2x 27C020 Open 1 2 EPROM 1 2x 27C040 1 2 1 2 2 2 27C080 1 3 Flash 12V read only 256kB 512kB 2 287010 or 2x 28F 020 1 3 1 3 Flash 5V read write 256kB 1MB 2 29F 010 or 2x 29F 040 Default settings are in italics A ID 21168 Rev 04 PEP Modular Computers GmbH Page 4 3 VSBC 32 Configuration r 4 1 2 Solder Jumpers The following parameters are selected via solder jumpers CPU bus clock freguency J1 J2 J3 Communications clock frequency J4 Serial EEPROM write protection J5 Connection of protective and signal Ground J6 CXC interface connector pin A5 function assignment J11 SRAM size J7 J8 amp Table 4 3 CPU Bus Clock Frequency Selection Warning All solder jumpers are factory set Alteration of their settings can result in damage to the board Therefore customers must not alter the settings of these jumpers Closed Closed Open 25MHz VSBC 32 and VSBC 32E Open Closed Open 33 3MHz 5 32 only Table 4 4 Clock Freguencies EEPROM Write Protection and GND Connection Open 24M Hz communications clock not connected to MC68 EN 360 Ja 24MHz communications clock connected to MC68 EN 360 Closed Note This jumper must be set to open if the RCLK2 signal pin 16 is required Open EEPROM urite protection disabled Closed EEPROM write protection enabled Open Sign
30. D 21168 Rev 04 VSBC 32 Preface Preface ID 21168 Rev 04 PEP Modular Computers GmbH Page vii This page was intentionally left blank Page viii PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Preface Preface Proprietary Note This document contains information proprietary to PEP Modular Computers It may not be copied or transmitted by any means disclosed to others or stored in any retrieval system or media without the prior written consent of PEP Modular Computers GmbHor one ofits autho rized agents The information contained in this document is to the best of our knowledge entirely correct However PEP Modular Computers cannot accept liability for any inaccuracies or the conse quences thereof nor for any liability arising from the use or application of any circuit product or example shown in this document PEP Modular Computers reserve the right to change modify or improve this document or the product described herein as seen fit by PEP Modular Computers without further notice Trademarks PEP Modular Computers the PEP logo and if occurring in this manual CXM are trade marks owned by PEP Modular Computers GmbH Kaufbeuren Germany In addition this document may include names company logos and trademarks which are registered trade marks and therefore proprietary to their respective owners ID 21168 Rev 04 PEP Modular Computers GmbH Page ix VSBC 32 Preface
31. DTR Figure 0 15 8 Pin Connector on OS 9 Side SMART I O 9 Pin Connector on PC Side 8 pin RJ45 9 pin female 3 GND 5 GND SIGNAL ground 4 TxD 2 RxD 5 RxD 3 TxD 7 5 7 RTS 8 8 CTS 6 DSR 1 DCD 4 D 8 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 D 3 OS 9 System Modem Figure D 16 15 pin Connector 15 pin male 7 0 0 A OQ N TxD RxD CTS RTS DCD DTR 25 pin male Figure D 17 8 pin RJ45 Connector SMART I O 8 pin RJ45 3 N NO ID 21168 Rev 04 GND TxD RxD CTS RTS DCD DTR 25 pin male PEP Modular Computers GmbH W N N or N 5 9 Cabling GND SIGNAL ground TxD RxD CTS RTS DCD DTR GND SIGNAL ground TxD RxD CTS RTS DCD DTR Page D 9 VSBC 32 OS 9 Cabling r 0 4 OS 9 System OS 9 System D 4 1 Software XON XOFF or No Handshake Figure D 18 15 pin Connector 15 pin male 15 pin male 7 GND 1 7 GND SIGNAL ground 2 TxD gt c 3 RxD 3RD 2 4 CTS 4 CTS 5 RTS A L 5 RTS Figure D 19 8 pin RJ45 Connector SMART 1 0 8 pin RJ45 15 pin male 3 GND 7 GND SIGNAL ground 4 TxD 3 RxD 5 RD 2 2 5 RTS 7 CTS A L 4 CTS Figure D 20 6 pin RJ12 Connector 6 RJ12 15 pin male 2 7 GND SIGNAL ground 3 TxD 3 RxD 4RxAD
32. Disclaimer PEP Modular Computers GmbH rejects any liability for the cor rectnesss and completeness of this manual as well as its suitabil ity for any particular purpose This manual was realized by TPD Engineering PEP Modular Computers GmbH Page ii 2000 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Contents Contents ix Proprietary Note Trader arK Y ix Explanation of Symbols x For Yol Safely ua n ot a Xi High Voltage Safety Instructions gt Josue tapa tutte epp di a pi no pp aa Xi Special Handling and Unpacking Instructions 222 20002020200 Xi General Instructions on Usage nrnna Two Year Warranty xiii Chapter 1 1 Introduction 1 1 System EWO NOW ti kant a a in e a an e a a api pk a na ini 1 3 1 2 Board Overview 1 4 1 2 1 Board Specific Information 1 4 122 Board uu sms i 1 4 1 2 8 Board Connectivity and Interface Expandibility 1 5 1 2 4 Memory Piggybacks aki kk n nin di a m 1 6 1 25 System Relevant Information 1 6 1 3 1 8 1 3 1 System Level Functional Block Diagram
33. For the location of the Watchdog LED please refer to the VSBC 32 E Frontpanel figure in the Introduction chapter of this manual 2 6 7 Reset Sources The VSBC 32 E interacts with the following reset sources Table 2 7 VSBC 32 E Reset Sources Push Button SYSRES VME No Watchdog WDG bit on board Board Control Status Register Power Monitor 4 65V Inside the MC68 EN 360 2 6 8 Slot 1 Detection During power up the VSBC 32 E detects whether it is being used as a system control ler slot 1 This information can be read from the VMEbus control status register and is valid until the next power down of the system For a complete map of the VMEbus control status register please refer to the relating section in the Configuration chapter of this manual Page 2 20 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description The frontpanel status indicators consist of three LED s with the following functions Yellow Watchdog LED Green General Purpose Red CPU Halt or Reset The green LED is user defined by the customer It is set by the software during startup when the MC68 EN 360 is initialized 2 7 Frontpanel Functions Figure 2 6 VSBC 32 E Frontpanel LED and Button Locations Watchdog LED General Purpose CPU Halt or Reset Reset Button Abort Button A Reset button is fitted to the front panel to avoid false operation The Reset button tr
34. Gold Caps U Volts 0 25 50 100 150 170 Time Hours Page 2 22 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description 2 9 Address Decoder 2 9 1 Basic Structure The address decoder of the VSBC 32 E consists of external logic and the MC68 EN 360 internal memory controller The MC68 EN 360 s internal chip select logic decodes all the basic address areas following its initialization The eight chip select out puts of the processor are connected to the different devices as shown in the following tablle Table 2 8 Chip Select Output Connection VETROM 51 on memory piggyback 32 Internal CS2 VMEbus 16 External C53 a E M 16 32 Internal 54 SRAM 16 External 55 CXC 16 External CS6 RTC 16 External CS7 Control status register 16 External Chip selects for flash on memory piggybacks and EPROM sockets are exchanged depending on the selected boot device Jumper J18 The external address decoder switches the boot chip select CSO memory piggyback or EPROM on flash EPROM sockets depending on the selected boot device The interrupt acknowledge cycles are also decoded by the external address decoder Moreover the external address decoder includes a fast bus error BERR generator which monitors the delay between external cycle start and generated CSx line 2 9 2 Boot Decoding The type of boot device can be selected fro
35. N C N C RXD TxD Receive Transmit Data plus N C DGND Data Ground GND 5V Voltage Plus 5V N C RxD TxD Receive Transmit minus N C o o On Ww N rmm N C Not connected ID 21168 Rev 04 PEP Modular Computers GmbH Page B 9 VSBC 32 Serial Interface Piggybacks r B 6 3 SI PB485 ISO Jumper Settings Table B 9 Jumpers J1 and J2 End of Line Termination Open No internal line termination Set internal line termination Default settings are in italics Table B 10 Jumpers J3 and J4 Idle Setting Open No internal idle status Set Internal idle status Default settings are in italics Table B 11 Jumper J5 Isolation Voltage Supply 1 3 Isolating VCC supplied internally 1 2 Shielded 150 0hm termination Default settings are in italics Table B 12 Jumper J6 Received Control 1 3 Receive permanently enabled 1 2 Receive enabled Default settings are in italics Page B 10 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 CXC Appendix CXC A ID 21168 Rev 04 PEP Modular Computers GmbH Page C 1 This page was intentionally left blank 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 CXC C CXC The Controller eXtension Connector CXC is the local interface It contains a 16 bit
36. OM 32 MC68EN360 Comm Controller 25MHz 33MHz Flash or EPROM 256 or 1 MB CXC Interface CPU Options Memory Piggybacks 1MB DRAM 0 or 1 MB Flash EPROM 4MB 1 2 or 4 MB Flash EPROM 8MB DRAM 1 2 or 4 Flash EPROM 16MB DRAM 1 2 or 4 MB Flash EPROM 32MB DRAM 0 5 1 or 2 MB Flash EPROM 64 DRAM 1 2 or 4 Flash EPROM 2 2 3 DMA Channels Two independent channels are provided by the MC68 EN 360 controller chip and can be used by applications requiring data transfer between VMEbus modules as well as CXC modules if present DRAM flash memory and dual ported SRAM Memory to memory transfers with the DMA s of the MC68 EN 360 are possible with any combination of on board and VMEbus addresses Page 2 6 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description Under the aspect of serial communications control a major advantage of the MC68 EN 360 serial communications controller core SIM60 is its compatibility with all important communication standards A detailled description of all control functions is provided on the following pages alongside with a comprehensive list of the possible serial interface piggybacks and their connectors 2 2 4 Serial Communications Control For the mainboard interface connector pinouts refer also to the Board Interfaces sec tion of this chapter For a description and pinouts of the conn
37. Report issued by PEP with the repaired or replaced item PEP Modular Computers will not accept liability for any further claims resulting directly or indi rectly from any warranty claim other than the above specified repair replacement or refund ing In particular all claims for damage to any system or process in which the product was employed or any loss incurred as a result of the product not functioning at any given time are excluded The extent of PEP Modular Computers liability to the customer shall not exceed the original purchase price of the item for which the claim exists PEP Modular Computers issues no warranty or representation either explicit or implicit with respect to its products reliability fitness quality marketability or ability to fulfil any particular application or purpose As a result the products are sold as is and the responsibility to ensure their suitability for any given task remains that of the purchaser In no event will PEP be liable for direct indirect or consequential damages resulting from the use of our hardware or software products or documentation even if PEP were advised of the possibility of such claims prior to the purchase of the product or during any period since the date of its purchase Please remember that no PEP Modular Computers employee dealer or agent is authorized to make any modification or addition to the above specified terms either verbally or in any other form written
38. SBC 32 E mainboard is not provided with any on board DRAM flash These are provided by special memory piggybacks DM60x By means of these piggybacks the following memory configurations are possible s 64MB of DRAM lt 4MB of flash EPROM For a detailled description of the memory piggybacks please refer to the Memory Pig gybacks appendix of this manual 1 2 5 System Relevant Information System Configuration Up to twenty one VSBC 32 E boards can be installed in a VMEbus 3U rack Please refer to the description of the VMEbus backplane connector in the Functional Descrip tion chapter of this manual If used as a system controller the board should be always installed in the system slot If a CXM SIOS or a CXM SCSI module is used in combination with the VSBC 32 E the module can be sandwiched with the controller Communication between the controller and the I O module being acchieved via the VSBC 32 E s on board CXC connector Master Slave Functionality The VSBC 32 E is a combined system and communications controller board provided with both a VMEbus backplane interface which can operate both as a VMEbus master and slave simultaneously Thanks to this feature all twenty one VSBC 32 E boards possible in a VMEbus system can operate as VMEbus masters while at the same time sixteen of them can act as VMEbus slaves The VSBC 32 E VMEbus master slave or neither operation is a function of the application software Boots
39. The VMEbus interrupt acknowl edgement is controlled via a daisy chain driver that is supplied with the board IACK is connected via the VMEbus backplane for IACKIN of the system slot The signals SYSCLK and SYSRES can be routed from on board to the VMEbus through the use of jumpers leaving to the VMEbus user instead of the system controller the initiative of generating these signals SYSFAIL generates a maskable on board autovectored level 3 interrupt please refer also to the section System Control Function ality Interrupt Control of this chapter whereas ACFAIL generates a non maskable on board level 7 interrupt ID 21168 Rev 04 PEP Modular Computers GmbH 2 13 VSBC 32 Functional Description r The VSBC 32 E also provides a bus monitor for the VMEbus 128us bus error timer monitors the cycle lengths of the VMEbus data transfer and generates a VMEbus BERR signal on timeout This timer is enabled and disabled via the VMEbus control status reg ister which contains alsao a timeout status bit in order to identify the bus errors generated by the bus monitor Exchange and retention of system relevant data from the VMEbus to the CPU DMA and viceversa is provided by means of 256kB or 1MB of a 16 bit wide dual ported SRAM which is backed up using Gold Caps Both the VMEbus users and the on board CPU have access to the SRAM memory upper 8kB i e even Byte addresses Note The dual ported SRAM cannot be a
40. U frequency SRAM size The following basic board variants are available VSBC 32 MC68360 processor no Ethernet control capability VSBC 32E MC68EN360 processor Ethernet control capability 1 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction The MC68EN360 processor is also available with two different clock rates 25MHZ 33MHz this variant is again supplied with either 256KB 1MB SRAM The below described frontend connectivity and interface expandibility are common to all board variants 1 2 3 Board Connectivity and Interface Expandibility The VSBC 32 E mainboard is provided with the following standard connectors Non optoisolated RS232 serial interface two RJ45 connectors on frontpanel One set of piggyback interface connectors for serial interface SI piggybacks three 7 pin row male connectors One set of memory piggyback interface connectors two 50 pin row female connectors Two sets of flash EPROM DIP sockets two 32 pin row female sockets Background debug mode BDM interface one 12 pin row male connector VMEbus backplane interface one 96 pin DIN 41612 style C male connector Enhanced CXC mezzanine interface one 96 pin DIN 41612 style C male connector In addition the mainboard external interfacing is usually integrated by one of the follow ing piggyback mounted frontpanel interface options serial interface piggybacks The kinds of
41. ace piggyback Full MODEM 1 Full MODEM 2 SCC2 External serial interface module Full MODEM 3 SCC3 External serial interface module External serial interface module Full MODEM 4 SCC4 Mainboard or Serial interface piggyback or External serial interface module Legend Board versions with Ethernet port E Board versions without Ethernet port 1 Independent of Ethernet configuration 9 4 is not used by any of the Ethernet piggybacks With these piggybacks SCC4 can be used on the CXC bus ID 21168 Rev 04 PEP Modular Computers GmbH Page2 9 VSBC 32 Functional Description 2 3 Functional Block Diagram Figure 2 4 VSBC 32 Board Level Functional Block Diagram System Controller Subordinbate CPU Control Functions Subordinbate CPU Memory Functions System Controller Core Status Control Flash EPROM IRQ Handler Reset Logic DIP Flash EPROM Serial EEPROM Serial Communications Controller SMC2 E E s Controller Logic SI Industrial I O Boards Piggyback Piggyback Inteeligent Serial I O Boards RS232 non optoisolated or RS485 optoisolated 10Base2 or 10 5 or 10BaseT Ethernet a RA S 5 2 oa a dp 72 75 Mw 72 72 a da 2 10 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description The following section provides a description of the mai
42. ack uses 5 4 SER3 TCLK C5 Yes 14 SER3 TXD C8 Yes PAT Not usable if SI piggyback uses SCC4 4 Legend 1 Reserved Pin On a standard VSBC 32 board this signals is used for UART ports at BU7 and BUG 2 Reserved Pin On a standard VSBC 32 board this signal is used for SPI to which the EEPROM is already con nected PBO is chip select of the EEPROM 3 Reserved Pin On PA13 a 24 MHz clock signal is routed via jumper J4 This signal is always needed for PEP standard software serial drivers 4 Dual Functioning Pin This signal is routed both to the mainboard s interface for serial interface piggybacks ST5C and the CXC backplane connector and can be used by either one or the other but not both at the same time Due to this a conflict exists if the SCC4 port is to be used with the SI232 piggyback and CXC boards such as CXM SIO3 as both boards access this port The SCC4 port can therefore not be used at the same time by serial interface piggybacks and CXC boards 2 16 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description Table 2 5 IUC IUC 32 Porting Information Sheet 2 of 2 SER3 RXD c9 Yes PA6 Not usable if SI piggyback uses scc4 4 SER3 RTS B7 Yes PB15 Not usable if SI piggyback uses SCC4 4 SER3 DTR A12 Yes PB9 Not usable if SI piggyback uses SCC4 4 SER3 CTS B16 Yes 10 Not usable if SI piggyback uses SCC4 4 SER3 CD B8 Yes 11 Not usable
43. al GND not connected to Protective GND J6 Signal GND connected to Protective GND Closed Note If this jumper is set care must be taken to avoid any grounding currents Table 4 5 SRAM Size Selection 1 2 1 2 1MB VSBC 32E only 1 3 1 3 256kB VSBC 32 and VSBC 32E Default settings are in italics 4 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 4 2 Software Configuration 4 2 1 Address Map Configuration Software applications may require to configure data in the VSBC 32 E registers For this pur pose the configurable memory is described in the following The address map in the table below is based on the recommended default initialization of the MC68 EN 360 chip select logic Figure 4 1 VSBC 32 E Memory Map Address See C RR 0x 00 xx xx XX Ox 04 xx 07 00 Ox xx Ox 09 xx F7 xx xx 0 OC xx xx xx Ox OD xx xx x1 Ox OD xx xx x5 Ox OD xx xx x7 Ox 82 xx xx xx Ox 83 85 00 0x 87 xx xx xx Memory Device DRAM on DRAM Flash piggyback FLASH on DRAM Flash piggyback MC68 EN 360 internal RAM register Flash EPROM sockets SRAM CXC Real time clock VMEbus IRQ mask register VMEbus control status register Board control status register VMEbus user defined AM code VMEbus user defined AM code VMEbus short 1 0 AM code VMEbus st
44. andard AM code MC68 EN 360 51 50 CS3 C54 CS6 57 1 57 5 57 7 52 52 52 52 1 I the ROM sockets are selected as the default boot device then the address 0x 09 xx xx i e CS3 of the MC68 EN 360 is automatically selected as the base address for the flash on the memory piggyback 2 See the appendix of this manual for further addressing information Note The above shown memory map is PEP default All other addresses do not cause 50 57 signals Therefore access to them leads to bus errors BERR Furthermore in order to determine the base of the internal memory map of the MC68 EN 360 controller the module base address register MBAR must be set The location of this register is fixed in the address area Supervisor CPU Space at 3FFOOH For more informa tion on the recommended MC68 EN 360 initialization sequence please refer to the Software Installation section in this manual ID 21168 Rev 04 PEP Modular Computers GmbH Page 4 5 VSBC 32 r Configuration 4 2 2 Board Control Status Register Address CS7 0 7 Format Byte Access Read write Value after HW Reset 0 PEP Default Address 0 OD 00 00 07 Figure 4 2 7 0 7 Bitmap 7 WDG 6 5 4 3 2 1 0 BERR2 BERR1 TR WDG EN ACFAIL LED G Table 4 6 Register Description WDG Set by watchdog timer when timout has been reached Used to differentiate be
45. bus ownership i e the time gap between a VMEbus request and the starting of the VMEbus cycle is monitored by the on board bus error timer The VMEbus cycles themselves are monitored by the separate VMEbus error timer Note The internal MC68 EN 360 bus error timer hardware watchdog timer is not used on the VSBC 32 E Therefore it should remain disabled default setting VMEbus Error Timer In addition to the on board bus error timer the VSBC 32 E provides a bus monitor for the VMEbus A 128us timer monitors VMEbus data transfer cycle lengths and generates a VMEbus bus error signal BERR for error termination This error is enabled and dis abled via the VMEbus control status register which also supplies a timeout status bit in order to identify bus errors genrated by the bus monitor For a complete map of the VMEbus control status register please refer to the relating section in the Configuration chapter of this manual ID 21168 Rev 04 PEP Modular Computers GmbH Page 2 19 VSBC 32 Functional Description r 2 6 6 Watchdog Timer A 512ms watchdog timer triggers the on board reset generator at timeout Once enabled via the board control status register the watchdog timer cannot be reset by software It must be re triggered via the corresponding bit in the board control status register periodically within the timeout period Watchdog timer running is a status that is displayed by the yellow front panel LED
46. ccessed through its own VMEbus interface A bus monitor timeout would result due to the fact that any access by the VMEbus to the DPRAM would be blocked as long as the VSBC 32 E is bus master An external VMEbus master may interrupt the VSBC 32 E by setting P IRQ5 mailbox interrupt pending in the VMEbus control status register Seen from the VMEbus the address of this dual ported register is identical to the base address of the dual ported SRAM lower 8kB i e odd Byte addresses Note bits of the VMEbus control status register can be read from the VMEbus but only the bit P is read write For a complete map of the VMEbus control status register please refer to the relating section in the Configuration chapter of this manual For any general VMEbus information including generic pinouts please refer to Appendix B of the ANSI VITA VME64 Specification 2 4 7 Mezzanine Interface The VSBC 32 E is equipped with a CXC mezzanine interface connector CXC and eCXC both contain a 16 bit data bus seven address lines and eight decoded chip select lines In total there are eight control signals 50 57 The base address of the CXC can be programmed the CS5 line of the MC68 EN 360 The main difference between the two VITA standards is the amount of address space available for peripheral devices CXC 8 256Bytes overall length 0 400 1024Bytes actually available eCXC 8 16
47. de day ann a an bay kaa aka k dw aa aa B 7 B 8 5 1 Front Panel View Pinout 8 GNE Lu 5 20 B 9 EDI Specifications 9 B 6 2 Front Panel View Jumper Layout and Pinout B 9 6 3 SI PB485 ISO Jumper Settings B 10 C 1 CXC Address Ranges PEE C 3 C 2 CXC Generic Pinouts a a bas ason es ai pid kas C 5 CPU Pinout Cross Reference 6 7 C 5 CXC Backplanes 8 ID 21168 Rev 04 PEP Modular Computers GmbH Page vii VSBC 32 Contents m Appx D Ol AIO RTT ETT D 3 D 1 OS 9 System Terminal D 3 0 1 1 Software No Handshake D 3 D 1 2 Hardware Handshake Set Terminal to CTS DTR Handshake D 4 D 2 OS 9 System PO D 5 D 2 1 Software or No Handshake D 5 D 2 2 Hardware Handshake Select RTS CTS Handshake on the PC Side D 7 OS 9 System D 9 D 4 OS 9 System OS 9 System ei oka ion kone aie pisan D 10 D 4 1 Software or Handshake D 10 D 4 2 Hardware ad sw sok aaa be sent otn pu ka ki kaa D 11 Page viii PEP Modular Computers GmbH I
48. e 3 3 VSBC 32 Installation r To remove the board please proceed as follows Ensure that the safety requirements indicated above are observed Disconnect any interfacing cables that may be connected to the board Disengage the board retaining mechanism by pressing down on the board release handle disengaging the board from the backplane connector and pull the board out of the slot 3 1 1 External Serial Interface Module Being a combined system and serial communications controller board the VSBC 32 E is designed for a possible combined use together with the CXM SIO3 external serial interface module If such an interface module is used all communication signals between the mainboard and the module are transmitted via the CXC bus For this pur pose the external interface module must be sandwiched with the VSBC 32 E main board 3 2 Software Installation There are no special requirements for software installation However many components of the VSBC 32 E are controlled by the MC68 EN 360 processor Due to this fact the controller requires a special initialization sequence before any other software can be started For any details on the initialization sequence and the address list of involved registers please refer to the relevant description in the User s Manual included with your operat ing system Page 3 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Configuration Chapter Co
49. e stored in EEPROM PEP Software PEP Default Address 0 OD 00 00 01 Figure 4 4 7 0 1 Bitmap 7 6 5 4 3 2 1 0 EN 1807 IRQ6 EN IRQ5 EN IRQ4 EN EN 2 EN_IRQ1 SYSFAIL Table 4 9 Register Description IROx 1 Enable VME bus interrupt requests where 1 7 SYSFAIL 1 Enable VMEbus level 3 autovector interrupt SYSFATL 4 8 PEP Computers GmbH ID 21168 Rev 04 VSBC 32 Memory Piggybacks Appendix Memory Piggybacks ID 21168 Rev 04 PEP Modular Computers GmbH Page A 1 This page was intentionally left blank Page A 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Memory Piggybacks A Memory Piggybacks A 1 General The Memory Piggybacks described herein provide main memory capability for the stor age of progam code and data either in DRAM or flash memory Various configurations of DRAM and flash memory as indicated in the table below are available for a wide variety of PEP CPU boards All configurations have 32 bit access and a maximum address range of 64 MB In addition jumpers are available for providing write protection Table A 1 Memory Piggyback Types and Configurations 1MB DM600 4MB 2 4 1MB DM601 16 MB 2 MB 4 0 MB DM602 1 MB 1 2 MB 0 KB 512 KB DM603 32 MB 1 2 MB 4 1 DM604 8 MB 2 MB 4 1 DM605 64 MB 2 MB 4
50. ectors of the serial inter face communication piggybacks as well as of the CXM SIO3 frontpanel interface connectors please refer instead to the SI Piggybacks appendix of this manual as well as to the CXM SIO3 user s manual and its Serial Communications Piggybacks appen dix respectively Communication Standards and Protocols Six communication standards are available on the VSBC 32 E Serial I O RS232 RS485 RS422 Ethernet 10Base2 10Base5 10BaseT Serial communications using the RS232 standard are available on the VSBC 32 E mainboard frontpanel as well as on a dedicated piggyback to be connected to its SI Interface In addition RS232 communication is possible via a CXM SIO3 serial interface module Communications using the PROFIBUS protocol are supported by an optoisolated half duplex RS485 serial interface implemented on a dedicated piggy back to be connected to the SI Interface of either the VSBC 32 E or the external serial interface module RS422 is not commonly available on the VSBC 32 E but can be sup plied by PEP Modular Computers on special request The MC68 EN 360 processor is specified to support also a full set of EEE 802 3 Ether net CSMA CD media access control and channel interface functions Since the control ler requires an external interface adapter and transceiver function the Ethernet interface can be adapted to all standard Ethernet functions such as 10BaseT 10Base5 and
51. elow shows a cross reference of the special CXC released by the MC68302 and the MC68EN360 Table 1 4 Cross Reference of MC68302 MC68 EN 360 to CXC Signals NE ooo kok 1 11 PC0 RTSI LISTI IRQ 1 A2 10 1 RTS2 LIST2 IRQ 2 A3 PB9 PC2 RTS3 LIRQB LIST3 IRQ 3 A4 PB8 PC3 RTS4 LIROAJLIST4 IRQ 4 A5 PB7 WDOG PBO SPISEL RRJCTI User defined A6 PB6 TOUT2 PBI SPICLK RSTRT2 User defined A8 PB5 TIN2 PB2 SPIMOSI SPITXD RRJCT2 User defined A9 PB4 TOUTI PB3 SPIMISO SPIRXD BRGO4 User defined 10 PB3 TIN1 PB8 SMSYN1 DREQ2 User defined 11 PB2 IACK1 PB16 BRGO3 STRBO SER2 DTR A12 1 IACK6 PB9 SMSYN2 DACK2 SER3 DTR A13 IACK7 PB17 RSTRTI STRBI SERI Bl RCLK1 PA8 CLK1 BRGOTI LIR CLKA TIN1 SER1 RCLK B2 TCLK1 PA10 CLK3 BRGO2 LITCLKA TIN2 SERI TCLK B4 TXD1 PA3 TXD2 SERI TXD B5 RTS1 PB13 RTS2 LIST2 SER1 RTS B7 RTS3 PB15 RTS4 LIRQA LIST4 SER3 RTS B8 CD3 11 CD4 LIRSYNCA SER3 CD B10 RXD1 PA2 RXD2 SERI RXD B11 1 PBIO SMTXD2 LICLKOB User defined B13 51 PC6 CTS2 SERI CIS B14 CD1 7 CD2 TGATE2 SER1 CD B16 53 PC10 CTS4 LITSYNCA SDACK1 SER3_CTS Cl DONE PB6 SMTXD1 DONE User defined C2 DACK PB5 BRGO2 _DACK1 DMA C3 DREQ PBAJBRGO1 DREQ1 DMA REQ C4 BRG3 PBII SMRXD2 LICLKOA User defined 5 TCLK3 PAI4 CLK7 BRGO4 TIN4 SER3 TCLK C6 RCLK3 PA15 CLK8 _TOUT4 LITCLKB SER3_RCLK C8 TXD3 PAT TXD4 LIRXDA SER3_TXD C9 RXD3 PA6 RXDA LITXDA SER3 RXD C10 BRG2 PB7 SMRXD1
52. for real time applications The DM60x piggybacks provide between 1MB and 64MB of DRAM with 32 bit access and up to 4MB of 5V flash memory In addition set of DIP sockets located on the VSBC 32 E mainboard allows the installation of an additional 1MB of flash EPROM Both memory devices can be used for bootstrapping The selection of the boot memory is achieved by hardware jumpering Note Physically the DM60x piggybacks provide up to 64MB of DRAM However the IUC 32 E mainboard envisages addressing for up to two memory banks of 64MB each Exchange and retention of system relevant data from the VMEbus to the CPU DMA and viceversa is provided by means of 256kB or 1MB of a 16 bit wide dual ported SRAM which is backed up using Gold Caps Both the VMEbus users and the on board CPU have access to the SRAM memory Note The upper 8kB of dual ported SRAM are accessed by the VMEbus the lower 8kB are reserved for mailbox interrupts Configuration data are stored in a 2kbit EEPROM 1kbit is used for factory specific con figuration purposes and 1kbit is available for application specific configuration data A ID 21168 Rev 04 PEP Modular Computers GmbH Page 2 5 VSBC 32 Functional Description m A schematic overview of all possible memory configurations is given in the figure on the next page Figure 2 1 VSBC 32 Memory Configuration Variants Mainboard VSBC 32 MC68360 25MHZ 2kbit EEPR
53. ge A 9 VSBC 32 Memory Piggybacks m Page A 10 PEP Modular Computers GmbH ID 21168 Rev 04 This page was intentionally left blank Page A 11 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Memory Piggybacks m 12 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Serial Interface Piggybacks Appendix B Serial Interface Piggybacks A ID 21168 Rev 04 PEP Modular Computers GmbH Page B 1 This page was intentionally left blank B 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Serial Interface Piggybacks B Serial Interface Piggybacks B 1 General The serial interface SI piggybacks described herein adapt the multi protocol serial channels of the 68 EN360 controller chip to one of the following physical interfaces 10Base2 thin or cheapernet Ethernet 10Base5 Ethernet 10BaseT twisted pair Ethernet RS 232 modem compatible RS485 optoisolated PROFIBUS and are available for wide variety of PEP CPU boards Table B 1 SI Piggyback Types and Configurations 10Base2 RG58 Ethernet thin Coaxial 10Base5 D Sub 51 1085 15 10BaseT RJ45 SIHOBT Twisted pair 8 pin RS 232 2 x RJ 45 SI PB232 Modem interface 8 pin 85485 m SI PB485 ISO Optoisolated 2 wire half duplex 9 pin PROFIBUS P ID 21168 Rev 04 PEP Modular Compu
54. gybacks and CXC boards ID 21168 Rev 04 PEP Modular Computers GmbH A 2 17 VSBC 32 Functional Description r 2 6 Special Board Functions 2 6 1 Real Time Clock The three wire serial interface real time clock V3021 is 1 bit device which is accessi ble over the CS6 of the MC68 EN 360 Its time keeping features include as follows seconds minutes hours day of month month year week day and week number BCD format leap year and week number correction stand by supply smaller than 11A For further information please refer also to the Software Configuration chapter in this manual and the EM Microelectronic V3021 data sheet 2 6 2 EEPROM The serial EEPROM is a 1 bit device which is accessible over the three wire Interchip SPI Interface of the MC68 EN 360 The first half of the EEPROM 1 kbit is reserved for factory data including Board ID codes Internet Ethernet addresses boot information etc The second half of the EEPROM is available for the user See also the Software Configuration chapter in this manual For further information on the EEPROM please refer also to the XICOR X25C02 data sheet 2 6 3 PLL Operation Mode The MC68 EN 360 inputs EXTAL and CPU clock use the same input frequency The XTAL input is left open The clock mode is selected via the hard wired inputs MODCLKO and MODCLK1 With the default settings of MODCLKO 1 and MODCLK1 0 the fol lowing conf
55. he specific board version which must not be exceeded If batteries are present their temperature restrictions must be taken into account n performing all necessary installation and application operations please follow only the instructions supplied by the present manual Keep all the original packaging material for future storage or warranty shipments If it is necessary to store or ship the board please re pack it as nearly as possible in the manner in which it was delivered Special care is necessary when handling or unpacking the product Please consult the special handling and unpacking instruction on the following page of this manual Page xii PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Preface PEP Computers grants the original purchaser of PEP products a TWO YEAR LIMITED HARDWARE WARRANTY as described in the following However no other warranties that may be granted or implied by anyone on behalf of PEP are valid unless the consumer has the express written consent of PEP Modular Computers Two Year Warranty PEP Modular Computers warrants their own products excluding software to be free from manufacturing and material defects for a period of 24 consecutive months from the date of purchase This warranty is not transferable nor extendible to cover any other users or long term storage of the product It does not cover products which have been modified altered or repaired by any other pa
56. if SI piggyback uses SCC4 4 Used on board SPI SEL for EEPROM i i Cannot be used on CXC 2 SPI can be used if an SPI SEL Mo im other than is used SP TxD can be used if an SPI SEL AB Na sen other than PBO is used SPI can be used if an SPI SEL 19 po EBS other than is used 10 PB8 See MC68360 User Manual B11 No PBIO Used on board SMC2 Transmit 1 Cl No Used on board SMC1 Transmit 1 4 11 Used board SMC2 Receive 1 C10 No PB7 Used on board SMC1 Receive 1 Legend 1 Reserved Pin On a standard VSBC 32 board this signals is used for UART ports at BU7 and BUG Reserved Pin On a standard VSBC 32 board this signal is used for SPI to which the EEPROM is already con nected is chip select of the EEPROM 3 Reserved Pin On PA13 a 24 MHz clock signal is routed via jumper J4 This signal is always needed for PEP standard software serial drivers 4 Dual Functioning Pin This signal is routed both to the mainboard s interface for serial interface piggybacks ST5C and the CXC backplane connector and can be used by either one or the other but not both at the same time Due to this a conflict exists if the SCC4 port is to be used with the 51232 piggyback and CXC boards such as CXM SIO3 as both boards access this port The SCC4 port can therefore not be used at the same time by serial interface pig
57. ig gers the on board system reset generator In addition an Abort button is also fitted to the front panel The Abort button generates a non maskable level 7 interrupt which is used for debugging purposes 2 8 RTC and SRAM Data Retention Short term data retention for RTC and SRAM is gained with two Gold Caps each with a value of 0 22 Farad In contrast to Lithium cells Gold Caps do not require servicing This short term backup is intended for short power failures or for reconfiguring systems An empty Gold Cap needs approximately three hours to charge up with backup times dependant on the temperature memory size and memory manufacturer tolerances A well charged Gold Cap provides a minimum of 10 hours backup time Laboratory tests at PEP indicate a typical backup time of 1 week for both 256kB and 1MByte SRAM plus RTC the typical on board backup current is below 21A The charge and discharge behaviour of Gold Caps is documented in the graphics overleaf For long term data retention 5V standby power supply could be provided via CXC ST3A pin 5 user defined line This would require special wiring on the CXC backplane or a special battery CXC module ID 21168 Rev 04 PEP Modular Computers GmbH Page 2 21 VSBC 32 Functional Description r Figure 2 7 Gold Cap Charge and Dischage Characteristics Charge Characteristics of the Gold Caps U Volts 0 0 0 1 1 5 10 60 120 Time Minutes Discharge Characteristics of the
58. iguration is selected no prescaler multiplication factor 1 CLKIN to the prescaler CPU clock internal frequency VCO 2 CPU clock 2 6 4 Tick Generator The MC68 EN 360 internal Periodic Interrupt Timer is used by the PEP real time operat ing system as Tick generator For further information please refer also to the Motorola MC68 EN 360 User s Manual 2 18 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description The VSBC 32 E provides an on board bus error timer and a VMEbus error timer There are three cases of bus error 2 6 5 Bus Error Timers Table 2 6 Bus Error Types Reserved address BERRO 100ns Permanently enabled Enable disable possible on board BERRI ils set in board control register Enable disable possible Tails set in VME bus control register On Board Bus Error Timer An 8us timeout on board timer monitors the cycle lengths of data transfers to and from locations beyond the CPU data bus buffer including on board I O VMEbus SRAM and CXC After a timeout occurs it generates an on board bus error signal for error termina tion This timer is enabled disabled via the board control status register which also sup plies a timeout status bit in order to identify bus errors generated by the on board bus error timer During VMEbus cycles the on board bus error timer is reset as soon as the VSBC 32 E gains VME
59. ilable via the VMEbus International Trade Association VITA htip www vita com Many system relevant features that are specific for VMEbus systems can be found in the ANSI VITA VME64 Standard and in the VITA PEP CXC MPI Specification which despite its name applies also to VMEbus MPI carriers The VME64 Standard includes the following information VMEbus Specification Signal Lines Bus Modules Typical Operation Electrical Specifications Mechanical Specifications The CXC MPI Specification includes the following information Mechanical dimensions Electrical specifications Interface description ID Byte assignment With reference to the e CXC aspects of mixed VMEbus CXC systems please refer also to the PEP CXC Reference Manual ID 21168 Rev 04 PEP Modular Computers GmbH Page 1 3 VSBC 32 Introduction r 1 2 Board Overview 1 2 1 Board Specific Information The VSBC 32 E is a 3U Enhanced CXC combined system and communications con troller board that can operate in either a VMEbus or a mixed VMEbus CXC environ ment The board is based on the Motorola Quad Integrated Communications Controller QUICC MC68 EN 360 Therefore it is particularly suitable for system control functions within applications with communications requirements Depending on the controller chip used there are two board variants with different CPU frequencies The board s external interfacing consists of a twin RS232 interface
60. ions Real time clock backed up Date year month week day Time hour minute second 2kbit serial EEPROM 1kbit for board specific data serial number IP address etc lkbitfor application purposes DMA 2 additional independent channels transfers between DRAM FLASH VME and CXC Page 1 12 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction Table 1 2 VSBC 32 E Technical Specification Sheet 2 of 3 Communication Standards Serial 1 0 5232 RS422 RS 485 Ethernet VSBC 32E only Mainboard Connectivity Non optoisolated RS 232 serial interface two 12 connectors on frontpanel One set of piggyback interface connectors for serial inter face SI piggybacks two 13 pin row fe male connectors One set of memory piggyback interface connectors two 50 pin row fe male connectors Background debug mode BDM interface one 12 pin row male connector VMEbus backplane interface one 96 pin DIN 41612 style C male connector Enhanced CXC mezzanine interface one 96 pin DIN 41612 style C male connector Interface Expandibility Serial interface piggybacks SI PB232 non optoisolated RS 232 serial interface two RJ 45 connectors SI PB485 1SO optoisolated RS485 serial interface two 45 connectors SI 10B2 10Base2 Ethernet interface one RG58 coaxial connector SI 10B5 10Base5 Ethernet interface one
61. lash Addresses Table A 3 Jumper J1 Settings and Flash Memory Address Ranges All flash EP ROM s write protected 49 LLLLLLLLLELLLLLLELLT T LI HILL TITITT HEEEEEE 50 ZEEEEEEEEENEEEEEEEN Open 1 2 No Protection 1 3 Flash Bank 1 Write protected Upper 512 KB Upper 2 MB Flash Bank 1 Address Range 0x04080000 0x04020000 0x04100000 0x04400000 1 4 Flash Bank 0 Write protected Lower 512 KB Lower 2 MB Flash Bank 0 Address Range 0x04000000 0x04000000 0x04000000 0x04080000 0x04200000 0x04200000 Default settings are in italics ID 21168 Rev 04 PEP Modular Computers GmbH A Page A 5 VSBC 32 Memory Piggybacks A 4 DM602 The DM602 is a memory piggyback fitted with DRAM 1 MB Flash Memory 0 1 2 A 4 1Board Layout and Jumper Location Figure A 3 DM602 Memory Piggyback Legend 1 Flash Memory 2 BEBE 50 A 4 2 Jumper Description and Flash Addresses Table 4 Jumpers J1 and 42 Settings and Flash Memory Address Ranges Set No Protection Ji Open Flash Bank 1 Write protected Upper 512 KB Flash Bank 1 Address Range 0x04080000 0 04100000 Set No Protection default J2 Open Flash Bank 0 Write protected Lower 512 KB Flash Bank 0 Address Range 0 04000000 0x04000000 0x04080000 0x04200000 Page A
62. ll piggybacks fit on bott basic board variants IUC 32 and IUC 32E the MN68360 processor of the IUC 32 variant does not support Ethernet communication Therefore Ethernet piggybacks should be used only on the IUC 32E board variants For a detailled description of the pinouts of these piggyback interface connectors please refer to the VITA PEP Modular Computers CXC MPI Specification 2 4 3 Memory Piggyback Interface Connectors The VSBC 32 E is equipped with a set of memory piggyback interface connectors two 50 pin row female connectors The pinout of these piggyback interface connectors includes all signals for the connection of up to 128MB of DRAM and up to 4 MB of flash EPROM For a detailled description of the pinouts of these piggyback interface connectors please refer to the VITA PEP Modular Computers CXC MPI Specification 244 EPROM DIP Sockets The VSBC 32 E is equipped with two sets of flash EPROM DIP sockets two 32 pin row female sockets The pinout of these DIP sockets includes all signals for the connec tion of up to 1MB of SRAM 2 12 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description The VSBC 32 E is equipped with a background debug mode BDM interface connector one 12 pin row male connector This connector allows an external debugger to be interfaced to the MC68 EN 360 for controlling purposes The interface connector is specified by Motorola 2 4 5 Backg
63. m the DRAM flash memory piggyback or the EPROM devices on the two flash EPROM sockets The flash EPROM sockets can be configured by the user with the EPROM or different flash devices Please note that regardless of the boot device selected both possible areas can be addressed due to the fact that each area is connected to a seperate CS line of the controller This means that the CSO line which is the global boot select of the controller is exchanged for the CS3 line by the boot decoder logic ID 21168 Rev 04 PEP Modular Computers GmbH Page 2 23 This page was intentionally left blank Page 2 24 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Installation Chapter Installation A ID 21168 Rev 04 PEP Modular Computers GmbH Page 3 1 This page was intentionally left blank Page 3 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Installation 3 Installation 3 1 Hardware Installation The board described in this manual can be installed in the system slot of any VMEbus compatible computer The frontpanel of the board should be safely secured by screws to the chassis to avoid lossening of the board through vibration and to ensure correct earth connection Caution Electric Shocks Switch off the VMEbus system before installing the board in a free VMEbus slot Failure to do so could endanger your life health and may damage your board or system ESD Equipment Yo
64. mensions IEEE 1101 10 1 5 3 Environmental Tests Vibration IEC68 2 6 Permanent Shock IEC68 2 29 Single Shock IEC68 2 27 Page 1 14 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction 1 6 Related Publications 1 61 VMEbus CXC Systems Boards e ANSI VITA VME64 Draft Specification 1 1994 Rev 1 9 VITA CXC Specification Rev 2 0 PEP Modular Computers CXC MPI Draft Specification Rev 3 1 ID 12190 PEP Modular Computers CXC Reference Manual ID 05263 PEP Modular Computers CXM SIO3 Manual ID 14411 PEP Modular Computers CXM SCCI Manual ID 03545 1 6 2 Manufacturers Component Documentation Motorola MC68EN360 Quad Integrated Communications Controller User s Manual EM Microelectronic V3021 1 Bit Real Time Clock Datasheet e XICOR X25C02 SPI Serial EEPROM Datasheet ID 21168 Rev 04 PEP Modular Computers GmbH 1 15 This page was intentionally left blank Page 1 16 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description Chapter Functional Description A ID 21168 Rev 04 PEP Modular Computers GmbH Page 2 1 This page was intentionally left blank 2 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description 2 Functional Description 2 1 General Information The VSBC 32 E is a 3U VMEbus combined system and communications controller board based on the M
65. nboard interface connector pinouts For a detailled list and description of the connectors of the serial interface com munication piggybacks and of the frontpanel interface connectors please refer to the 5 Piggybacks appendix of this manual as well as to the CXM SIO3 user s manual and its Serial Communications Piggybacks appendix respectively 2 4 Board Interfaces 2 4 1 Serial I O Interfaces The mainboard RJ12 RS232 frontpanel connec Figure 2 5 Orientation of tors BU7 and BU8 of the VSBC 32 E are pro the VSBC 32 E Mainboard vided with TxD and RxD signals by the controller s Serial Interfaces SMC1 and SMC2 channels and supply RS232 interface software handshake XON XOFF capa bility They are configured as service debug con nectors by default The pinouts of the RJ12 connectors are shown in the following table 1 2 GND 3 TxD 4 RxD 5 N C 6 N C N C Not connected ID 21168 Rev 04 PEP Modular Computers GmbH Page 2 11 VSBC 32 Functional Description 2 4 2 Piggyback Interface Connectors for Serial Interface Piggybacks The VSBC 32 E is equipped with a set of piggyback interface connectors for serial interface SI piggybacks three 7 pin row male connectors The pinout of these piggy back interface connectors includes all signals for serial RS232 PROFIBUS RS485 and Ethernet 10BaseT 10Base5 10Base2 communication Note Although physically a
66. nfiguration ID 21168 Rev 04 PEP Modular Computers GmbH 4 1 This page was intentionally left blank 4 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Configuration 4 Configuration 4 1 Hardware Configuration The VSBC 32 E has fifteen jumpers fitted to the board The list of default jumper set tings is shown below A board layout with all jumper locations and pinouts is supplied in the Board Layouts section of the Introduction chapter of this manual 4 1 1 Wire Jumpers The following parameters are selected via wire jumpers Boot device selection J9 CXC Enhanced CXC selection J10 Connection of SYSCLK to VMEbus J11 Connection of on board reset to VMEbus J12 DIP socket memory type and size J13 J14 Note Jumpers J9 to J14 are normal wire jumpers that can be config ured by the user The other jumpers are solder jumpers and are factory set Table 4 1 ACFAIL e CXC and Boot Device Selection General Purpose Jumper Boot from flash on DRAM Flash piggyback enabled Closed Boot from flash EPROM DIP sockets enabled No Open CXC enabled Closed Enhanced CXC enabled TY Open SYSCLK disconnected from VMEbus Closed SYSCLK connected to VMEbus dio Open On board RESET generator not to VMEbus Closed On board RESET generator to VMEbus Table 4 2 DIP Socket Memory Selection Open Open EPROM
67. on 14 GND 7 N C 15 N C 8 N C relevant base board manual Not connected ID 21168 Rev 04 PEP Modular Computers GmbH The SI 10B5 requires an external 12V from the base board For further details please refer to the a Page B 5 VSBC 32 Serial Interface Piggybacks r B 4 SI 10BT The SI 10BT is a physical twisted pair 10BaseT interface to the 68EN360 Controller chip It connects one of the range of PEP CPU boards to an unshielded 100ohm twisted pair cable via an RJ45 telephone jack The SI 10BT has two LEDs fitted a red LED indicates collision detection and a yellow LED for data B 4 1 Specifications On board termination 100ohm Max Baudrate 10Mbit s according to Ethernet specification B 4 2 Front Panel View Jumper Layout and Pinouts Figure B 3 SI 10BT Serial Interface Piggy back Collision Transmit 10BaseT Ping Z ne M E RJ45 Pin 1 connector Table B 3 SI 10BT Connector Pinout TD 2 TD 3 RD 4 NIC 5 NIC 6 RD 7 NIC 8 Not connected Page 6 PEP Computers GmbH ID 21168 Rev 04 VSBC 32 Serial Interface Piggybacks 4 2 1 SI 10BT Jumper Settings Table B 4 Jumper J1 Sguelch Threshold Open Normal Set 4 5dB reduced threshold Default settings are in italics Table B 5 Jumper J2 Link Test Open Link Test enabled Set Link Test disabled
68. or electronically transmitted without the company s consent ID 21168 Rev 04 PEP Modular Computers GmbH Page xiii This page was intentionally left blank Page xiv PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction Chapter Introduction ID 21168 Rev 04 PEP Modular Computers GmbH Page 1 1 This page was intentionally left blank Page 1 2 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction 1 Introduction 1 1 System Overview The PEP Modular Computers product described in this chapter operates with the VMEbus architecture In addition some products also support the CXC Enhanced CXC eCXC local mezzanine interface standards which represent a stream lined variant of the VMEbus standard itself Thus a wide range of I O functions for indus trial applications are supplied Some of the major advantages of the VMEbus standard are internationally accepted VITA standards VMEbus CXC eCXC broad range of available VMEbus solutions scalable processor performance In addition in combination with e CXC technology the VMEbus equipment offers the following advantages lower costs and optimized reliability thanks to reduced design complexity compact I O sub systems thanks to easier I O wiring For detailled information concerning the VMEbus and e CXC standards please consult the VMEbus and CXC Specifications which are ava
69. ory In addition the MC68 EN 360 offers background debug ging the on chip Background Debug Mode which allows direct communication with the CPU To act as a system controller the VSBC 32 E is provided with arbiter system clock driver power monitor with system reset driver IACK daisy chain driver and 7 level VMEbus interrupt controller Arbitration is single level FAIR compare VME64 Specification Rule 3 14 Observation 3 17 If the VSBC 32 E is used as a system controller and consequently placed in the VMEbus backplane s system slot a special detection function provided by the board makes any slot 1 jumper setting superfluous The VSBC 32 E also provides a bus monitor for the VMEbus Interrupt Control The interrupt control logic of the MC68 EN 360 processes internal interrupt requests alongside with external autovectored interrupt requests and a mailbox interrupt request from the VMEbus control status register The interrupt control logic is built up using the processor s internal interrupt control and an external IRQ7 interrupt handler Internal requests are related to all interrupt requests caused by the controller sources including the processor s system integration functions watchdog timer periodic inter rupt timer and the communications processor module RISC controller timers DMAS SCC s etc In order to avoid conflicts regarding the different interrupt levels it is recommended to use IRQ
70. otorola Quad Integrated Communications Controller QUICC MC68 EN 360 Depending on the controller chip used and the SRAM size there are four board variants with different characteristics The following table provides an over view of the various VSBC 32 E board variants Table 1 1 VSBC 32 E Board Variants VSBC 32 MC68360 25MHz 256KB 25MHz 256kB VSBC 32E MC68EN360 33MHz 256kB 33MHz 1MB Being the MC68 EN 360 a CPU and serial communications controller it is particularly suitable for system control functions within applications with communications require ments such as LAN WAN or fieldbusses CAN LON PROFIBUS In fact both the VSBC 32 and the VSBC 32E allow for a wide range of serial interfaces based on the MC68 EN 360 controller which is able to handle up to six serial communi cations channels The channels can be configured in the following way Two service debug interface connectors SMC interface RxD TxD RS232 only Four full modem interface connectors multiprotocol channels SCC interfaces Thus the VSBC 32 E mainboard comes complete with two non optoisolated RS232 external interfaces which are located on the lower half of the front panel However the external serial interfacing can be extended by means of a variety of serial interface SI piggybacks and or a CXM SIOS type external serial interface module This external mod ule can be either sandwiched
71. piggyback that can be used depend on the mainboard variant Table 1 1 Serial Interface Piggybacks SI PB232 Non optoisolated R5232 serial interface two 45 connectors oe 51 485 150 Optoisolated RS485 serial interface one 9 pin female DSUB connector e 51 1082 10Base2 Ethernet interface one RG58 coaxial connector VSBC 32E 51 1082 10Base2 Ethernet interface one RG58 coaxial connector VSBC 32E SI 10BT 10BaseT Ethernet interface one 45 connector VSBC 32E Applications requiring further communication interfaces may be upgraded by means of an external CXM SIO3 serial interface module which provides the following interface extension possibilities RS232 serial interface connectors non optoisolated Serial interface piggyback ports Serial communications piggyback port ID 21168 Rev 04 PEP Modular Computers GmbH Page 1 5 VSBC 32 Introduction r Maximum one CXM SIO3 module can be controlled by a VSBC 32 E board The CXM SIO3 module provides access to internal communication signals of the base board that are transferred to the module via the CXC bus For a detailled list and description of the frontpanel interface and serial interface com munication piggybacks please refer to the Serial Interface Piggybacks appendix of this manual as well as to the CXM SIOS user s manual and its Serial Communications Pig gybacks appendix respectively 1 2 4 Memory Piggybacks The V
72. roduct out of its protective enclosure while it is not used for operational purposes unless it is otherwise protected Whenever possible unpack or pack this product only at EOS ESD safe work stations Where safe work stations are not guaranteed it is important for the user to be electri cally discharged before touching the product with his her hands or tools This is most easily done by touching a metal part of your system housing tis particularly important to observe standard anti static precautions when changing piggy backs ROM devices jumper settings etc If the product contains batteries for RTC or memory back up ensure that the board is not placed on conductive surfaces including anti static plastics or sponges They can cause short circuits and damage the batteries or tracks on the board ID 21168 Rev 04 PEP Modular Computers GmbH Page xi VSBC 32 Preface r General Instructions on Usage n order to maintain PEP s product warranty this product must not be altered or modified in any way Changes or modifications to the device which are not explicitly approved by PEP Modular Computers and described in this manual or received from PEP Technical Support as a special handling instruction will void your warranty This device should only be installed in or connected to systems that fulfill all necessary technical and specific environmental requirements This applies also to the operational temperature range of t
73. round Debug Mode Interface Connector The pinouts of the BDM interface connector are shown in the following table For any further details please refer to the Motorola MC68 EN 360 User s Manual Table 2 4 BDM Interface Connector Pinouts 1 GND 2 CLKO1 3 DS 4 BERR 5 GND 6 BKPT DSCLK 7 GND 8 FREEZE 9 RESETH 10 IFETCH DSI 11 VCC 12 IPIPEO DSO 246 VMEbus Backplane Interface The VSBC 32 E is equipped with a VMEbus backplane interface connector The board is provided with a complete master interface for the VMEbus backplane con nector The VMEbus master interface consists of a VMEbus arbiter requester system controller and buffers for data address control signals Simultaneously the VSBC 32 E can act as a VMEbus slave as it is provided with a slave interface which consists of a programmable board address decoder a dual ported SRAM access and a mailbox interrupt controller To act as a system controller the VSBC 32 E is provided with arbiter system clock driver power monitor with system reset driver IACK daisy chain driver and 7 level VMEbus interrupt controller Arbitration is single level FAIR compare VME64 Specification Rule 3 14 Observation 3 17 on the VSBC 32 E is used as a system controller a special detection function provided by the board which is also readable within the VMEbus control status register makes any slot 1 jumper setting superfluous
74. rty than PEP Modular Computers or their authorized agents Further more any product which has been or is suspected of being damaged as a result of negli gence improper use incorrect handling servicing or maintenance or which has been damaged as a result of excessive current voltage or temperature or which has had its serial number s any other markings or parts thereof altered defaced or removed will also be excluded from this warranty If the customer s eligibility for warranty has not been voided in the event of any claim he may return the product at the earliest possible convenience to the original place of purchase together with a copy of the original document of purchase a full description of the application the product is used on and a description of the defect Pack the product in such a way as to ensure safe transportation see our safety instructions PEP provides for repair or replacement of any part assembly or sub assembly at their own discretion or to refund the original cost of purchase if appropriate In the event of repair refunding or replacement of any part the ownership of the removed or replaced parts reverts to PEP Modular Computers and the remaining part of the original guarantee or any new guarantee to cover the repaired or replaced items will be transferred to cover the new or repaired items Any extensions to the original guarantee are considered gestures of goodwill and will be defined in the Repair
75. stem which therefore becomes a sort of privileged serial extension of the VSBC 32 E board itself In addition to two non optoisolated RS232 serial interface connectors the external serial interface module supports again a serial interface piggyback and up to three serial communications piggybacks with the relating interfacing options Maxi mum one CXM SIO3 module can be controlled by an VSBC 32 E board Figure 2 2 MC68 EN 360 Serial Communication Channeling CXC Interface RS232 RS432 RS485 Ethernet 10Base2 10Base5 10BaseT yo VW RS232 RS232 Rx and Tx only Note The serial channel SCC4 is routed to both the piggyback inter face for serial interface piggybacks and the CXC and can be used by either one or the other not both at the same time Page 2 8 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Functional Description Depending on whether the piggyback interface for serial interface SI piggybacks is configured as Ethernet port board versions with Ethernet piggyback or not the serial interfaces channels of the VSBC 32 E can assume the functions described in the following figure Figure 2 3 VSBC 32 E Serial Interface Channel Configurations Serial Communication Port Interface Location Channel Service Debug 1 SMC1 Mainboard upper RJ12 Service Debug 2 SMC2 Mainboard lower RJ12 Ethernet SCC1 Mainboard serial interf
76. ters GmbH Page B 3 VSBC 32 Serial Interface Piggybacks r B 2 SI 10B2 The SI 10B2 is a physical cheapernet 10Base2 interface to the 68EN360 Controller chip It connects one of the range of PEP CPU boards to a 50 ohm coax cable via an RG58 BNC T connector The SI6 10B2 has two LEDs fitted a red LED indicates collision detection and a yellow LED for data transmission B 2 1 Specifications On board termination None Cheapernet cable is terminated at both ends Max Baudrate 10Mbit s according to Ethernet specification B 2 2 Front Panel View Figure B 1 SI 10B2 Serial Interface Piggyback Collision Col Tx Transmit 4 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 B 3 SI 10B5 Serial Interface Piggybacks The SI 10B5 is a physical AUI interface to the 68EN360 Controller chip 3 1 Specifications On board termination None Max Baudrate 10Mbit s according toEthernet specification B 3 2 Front Panel View and Pinout Figure B 2 SI 10B5 Serial Interface Piggyback Pin 1 Pin 8 ETHERNET 10Base5 Pin 9 Pin 15 15 pin D Sub female connector Control IN circuit shield Control IN circuit shield 1 9 2 Control IN circuit A 10 Data OUT circuit B 3 Data OUT circuit A 11 Data OUT circuit shield 4 Control IN circuit shield 12 Data IN circuit B 5 Data IN circuit A 13 12 6 Voltage comm
77. trap Loader Via the VSBC 32 E frontend serial interface connectors the flash memory of the board s memory piggyback can be re programmed by means of the Bootstrap Loader which is delivered already installed in the DM60x memory piggybacks This standalone software has the capability of loading flash memory from Motorola S records or from any absolute address If the downloaded image does not work properly the Bootstrap Page 1 6 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 Introduction Loader can be re entered the memory contents analyzed and a further programming cycle initiated si Operating Systems Warning To avoid damaging of your Bootstrap Loader and consequently leaving your board unusable please read the separate Bootstrap Loader manual before re setting the flash contents of your VSBC 32 board The VSBC 32 E can operate under the following operating systems 5 9 VxWorks Drivers are available for both operating systems Porting to other operating systems on request ID 21168 Rev 04 PEP Modular Computers GmbH 1 7 VSBC 32 Introduction m 1 3 Board Diagrams 1 3 1 System Level Functional Block Diagram Figure 1 1 VSBC 32 E System Level Functional Block Diagram VSBC 32 Mainboard Master EM Piggyback Piggybacks VMEB us Master Slave Boards Piggyback SI 5 1 Serial and Industrial Boards Serial and Industrial I O Boards
78. tween resets caused by the watchdog and bit 7 Read Write resets caused by the reset button power up resets can be identified within the MC 68 EN 360 Set by VMEbus error timer on timeout to identify bus errors BERR2 Wo bit 6 Read Write caused by this timer See also VMEbus status control register 1 Set by on board bus error timer on timeout to identify bus Read Write ig bit 5 errors caused by this timer EN_WDG Enables the watchdog timer It can only be set once and bit 4 A Read Write remains enabled until the next reset aa 1 Read Write Triggers the watchdog timer Watchdog timeout 512ms Enables the on board bus error timer It also monitors all bit 2 1 Read Write on board 1 0 cycles including the time from the VMEbus request to the VMEbus grant Timeout 5 ACFAIL 1 Read Write VME ACFAIL signal latched when active in order to distinguish bit 1 level 7 NMI from an ABORT or ACFAIL 1 Read Write Enables the green general purpose front panel LED amp Page 4 6 Warning The correct functionality of your equipment may be jeopardized due to a loss of information if bit 7 is written to Therefore the customer should not write any data to bit 7 PEP Modular Computers GmbH ID 21168 Rev 04 VSBC 32 4 2 3 VMEbus Control Status Register Address CS7 0x5 Format Byte Access Read write Value after HW Reset See table PEP
79. ur VMEbus board contains electrostatically sensitive devices Please observe the necessary precautions to avoid damage to your board Discharge your clothing before touching the assembly Tools must be discharged before use Do not touch components connector pins or traces If working at an anti static workbench with professional dis charging equipment please do not omit to use it To install the board please proceed as follows Ensure that the safety requirements indicated above are observed Ensure that the serial interface piggyback is properly installed and the relating front panel secured to the mainboard see appropriate documentation for configuration Ensure that the flash DRAM memory piggyback and the DIP flash EPROM is prop erly installed and that the boot memory selection jumper is set correctly Ensure that all other wire jumpers are set correctly DIP socket memory type and size boot device system clock and on board resets Warning Failure to set the wire jumpers correctly may cause damage or malfunctionning to your board Please refer to the Hardware Configuration section in this manual for any details on jumper settings Install the board in an appropriate slot and engage the retaining mechanism Connect external interfacing cables to the board as required Ensure that the board and interfacing cables are properly secured A ID 21168 Rev 04 PEP Modular Computers GmbH Pag

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