E6173-90021
Contents
1. Descripulonin 2662 Soe OR aI page 9 e Warnings and Cautions 0 0 eee eee eee page 10 e Setting the Address Switch 2 0 0 0 0 0 eee eee page 11 e Setting the Interrupt Line 0000000 page 11 Installing ina VXI Mainframe 2 04 page 12 The Agilent E6173A is a register based two channel isolated arbitrary waveform generator Each independent channel provides a waveform output a marker output and an input trigger BNC connector Additionally a BNC connector is provided to allow the use of an external timebase the external timebase is common to both channels The Agilent E6173A Arbitrary Waveform Generator is shown in Figure 1 1 The module is controlled via register access in A24 VXIbus addressing Multiple waveforms can be downloaded into memory Waveforms can be sequenced in any order linked to other waveforms and repeated The sample rate can be set by the internal 10 MHz timebase or by using an external timebase A programmable marker output on each channel can be used to synchronize other instruments Each channel also accepts an external trigger input to allow both channels or multiple modules to start simultaneously Getting Started 9 CHANNEL 1 Out Marker Ext Trig CHANNEL 2 gt IRQ Default 1 Logical Address Factory Default 80 Out Marker Ext Trig Ext Timebase oD Figure 1 1 Agilent E6173A Arbitrary Waveform Generat2. Calibration will use three waveforms in memory Each waveform is a single segment long and the Next sequence Pointer is set to continuously repeat this segment This creates a DC voltage output at the segment value The three segments will output de voltages of 0 V 16 38 V and 16 38 Volts 1 Following a 30 minute warmup period download the segment and sequence memory as follows Sequence Memory A24 Address Comments Segment Pointer A24_ base A24_ offset 800001 Sequence 0 segment pointer A24_base A24_ offset 80002 Sequence 1 segment pointer A24_base A24_ offset 80004 Sequence 2 segment pointer Repeat Count A24_base A24_ offset 900001 Sequence 0 repeat count 0 A24_base A24_ offset 90002 Sequence 1 repeat count 0 A24_base A24_ offset 90004 Sequence 2 repeat count 0 Dwell Count A24_base A24_ offset AO000 Sequence 0 dwell count 0 A24_base A24_ offset A0002h Sequence 1 dwell count 0 A24 base A24 offset A0004 Sequence 2 dwell count 0 Next Sequence Pointer A24_base A24_ offset BOOOO oO CO CO CO GO GO CO MY Sequence 0 continuous A24 base A24 offset B0002h e Sequence 1 continuous Sequence Number A24 base A24 offset BO004 Segment Memo A24 Address N Sequence 2 continuous Comments 0 A24_base A24_ offset 00000 A24_base A24_ offse
3. abort Status Control register bit 10 channel 1 amp bit 11 channel 2 The aborted channel s will set the stop bit s once abort is complete Status Control register bit 12 channel 1 and bit 13 channel 2 One the segment and sequence memories have been loaded into A24 space use the following general procedure to start the Agilent E6173 1 Configure the output attenuator filter on off state and impedance Channel Status Register base OCh bits 0 through 3 and 8 2 Configure the clock selection Select internal or external clock Channel Status Register base 12h bit O set 1 for external clock reset 0 for internal clock 3 Configure the Clock Adjust Register base 10 4 Select the trigger Channel Status Register base OC bits 4 through 6 Ifa VXIbus backplane trigger 1s to be used set the VXIbus trig0 trig7 line Channel Trigger Register base OE bits 0 through 2 5 Select the sequence to start by writing the sequence number to the On the Fly register base 12 Defaults to sequence 0 if not written 6 Start the Agilent E6173 by setting the start bits Card Status Control Register base 04 bits 8 and 9 and applying the trigger condition Chapter 3 Programming the Agilent E6173 29 set in step 4 Examples Examples are given in a general manner for a single sequence and multiple sequence downloads A detailed program example that generates an n segment sinewave is
4. 2 s compliment value For example to set the output voltage to 5 00 Volts Since Outputvoltage Segmentvalue x StepSize then Segmentvalue 9 160039 x In 20 bit binary and hexadecimal form the value 160039 looks like Bit 19 is the sign bit for the 2 s compliment number When bit 19 is set the number is a negative number For example to set the output voltage to 5 00 Volts 5 00 2 888537 0 3124x10 SegmentValue In 20 bit binary and hexadecimal form the value 888537 looks like Binary Hex 18 Understanding the Agilent E6173A Chapter 2 Because the segment value is a 20 bit value it must be broken into two 16 bit words in VXIbus memory To do this the four least significant bits are sent as the least significant bits of the first memory word For example the 20 bit 5 00 V value Binary Hex Address base n 2 base n Chapter 2 Sequences Markers Bits 6 and 7 are the MKR and EOS bit respectively As demonstrated above each segment value occupies two adjacent 16 bit memory locations Each segment is loaded into memory such that the entire waveform is contiguous with the
5. Bits A24_base A24_offset 004 Segment 1 LSByte 4 Least Significant bits EOS FALSE A24_base A24_ offset 006 Segment 1 MSWord 16 Most Significant Bits 7 T T A24_base A24_offset 024 Segment 9 LSByte 4 Least Significant bits EOS TRUE A24_base A24_offset 026 Segment 9 MSWord 16 Most Significant Bits Sequence 1 Chapter 3 A24_base A24_offset 028 Segment 10 LSByte 4 Least Significant bits EOS FALSE A24_base A24_offset 02Ap Segment 10 MSWord 16 Most Significant Bits A T A24_base A24_offset 18Ch Segment 99 LSByte 4 Least Significant bits EOS TRUE A24_base A24_offset 18Ep Segment 99 MSWord 16 Most Significant Bits Programming the Agilent E6173 31 Comments 4 Least Significant bits EOS FALSE A24 address A24_base A24 offset 190 Segment 100 LSByte 16 Most Significant Bits A24_base A24_offset 192 Segment 100 MSWord Sequence 2 T T T A24 base A24_offset F9C Segment 999 LSByte 4 Least Significant bits EOS TRUE A24_base A24_ offset F9E Segment 999MSWord 16 Most Significant Bits 4 Sequence Memory downloaded Sequence Memory A24 address Comments Register A24 base A24_offset 80000 A24_base A24 offset 80002y A24_base A24_offset 80004 A24_base A24_offset 90000 A24_base A24_ offset 90
6. and segment memory will remain unchanged However the A16 registers clock adjust triggers relays amp clock selection must be reset to the desired condition prior to restarting the waveform sequencer In particular the relays need to be set reset and then set to the desired state This is required due to the latching nature of the relays CH Channel select bit Writing a 0 to this bit select operations on channel 1 writing a 1 to this bit selects operations on channel 2 D Interrupt disable bit Writing a 1 to this bit disables interrupts Reading a 0 indicates interrupts are enabled a 1 indicates interrupts are disabled This bit is set to 0 following a reset Appendix B B Busy bit A read only bit indicating the current busy status of the module A 0 indicates the module is busy a 1 indicates the module is not busy STO Start channel 1 bit Writing a 1 to this bit starts channel 1 output contingent on the trigger being present ST1 Start channel 2 bit Writing a 1 to this bit starts channel 2 output contingent on the trigger being present AO Operation abort bit for channel 1 Writing a 1 to this bit will abort the output on channel 1 A1 Operation abort bit for channel 2 Writing a 1 to this bit will abort the output on channel 2 Note The specific sequence for aborting the waveform must be followed to insure proper operation of the E6173 In order to properly abort the w
7. the external markings described in Safety Symbols and Regulatory Markings on page 4 4 Ground the System To minimize shock hazard the system chassis must have a hard wired connection to an electrical protective earth ground The system must also be connected to the ac power mains through a power cable that includes a protective earth conductor The power cable ground wire must be connected to an electrical ground safety ground at the power outlet Any interruption of the protective grounding will cause a potential shock hazard that could result in personal injury Fuses Use only fuses with the required rated current voltage and specified type normal blow time delay Do not use repaired fuses or short circuited fuse holders To do so could cause a shock or fire hazard Operator Safety Information MODULE CONNECTORS AND TEST SIGNAL CABLES CONNECTED TO THEM CANNOT BE OPERATOR ACCESSIBLE Cables and connectors are considered inaccessible if a tool e g screwdriver wrench socket etc or a key equipment in a locked cabinet is required to gain access to them Additionally the operator cannot have access to a conductive surface connected to any cable conductor High Low or Guard Safety and Support Information ASSURE THE EQUIPMENT UNDER TEST HAS ADEQUATE INSULATION BETWEEN THE CABLE CONNECTIONS AND ANY OPERATOR ACCESSIBLE PARTS DOORS COVERS PANELS SHIELDS CASES CABINETS ETC Ve
8. 0 G General Programming Information 26 General programming information A24 access 27 abort operation 29 channel selection 26 memory load run 27 sequence operation 26 starting the Agilent Z2471A 29 trigger operation 28 Installing in a VXI mainframe 12 Instrument Description 9 Interrupt line setting 11 Mainframe installation 12 Manufacturer identification register 38 Memory A16 and A24 23 Index 49 segment 24 sequence 25 waveform 24 Memory Load Run 27 N Next Sequence Pointer 26 O Offset register 40 On the fly register 43 R Register base address 35 offset 37 Register addressing 35 Register Offset 37 Registers sequence memory 25 S Sample rate 15 Segment Memory 24 Segment memory example 20 Segment Memory Pointer 25 Segment value 18 Segments 15 Segments and sequences defining 18 Sequence Memory 25 Sequence Memory Registers 25 Sequence memory registers dwell count 26 next sequence pointer 26 segment memory pointer 25 Sequence Operation 26 Sequences 16 defining segments and 18 Setting the address switch 11 Setting the interrupt line 11 Specifications 33 Starting the Agilent E6173 29 T Trigger Operation 28 50 Index W Warnings and cautions 10 Waveform Memory 24 Waveforms arbitrary 14 defining arbitrary 14
9. 002 A24_base A24 offset 90004 A24_base A24_ offset A0000 A24_base A24_offset A0002 A24_base A24_offset A0004 Sequence 0 segment pointer Segment Pointer Sequence 1 segment pointer Sequence 2 segment pointer Sequence 0 repeat count 0 Repeat Count Sequence 1 repeat count 0 Sequence 2 repeat count 0 Sequence 0 dwell count 0 Dwell Count Sequence 1 dwell count 0 Sequence 2 dwell count 0 Next Sequence Pointer A24_base A24_offset B0000 Sequence 0 next sequence is 1 A24_base A24 offset B0002 Sequence 1 next sequence is 2 A24_base A24 offset BO004 32 Programming the Agilent E6173 Sequence 2 next sequence is 0 Chapter 3 Appendix A Specifications The following Agilent E6173A formerly Agilent Z2471A specifications apply under the following conditions Temperature 0 C to 55 C Warm up time 30 minutes Amplitude Resolution 20 bits monotonic to 16 bits typical Timebase Sources VXI CLK10 or external BNC input Sample Rate Generation Method timebase with digital dividers Maximum Waveform Frequency 250 kHz for square wave 100 kHz for 10 point sine wave Waveform Segment Memory 128 k samples Sequence Memory 32 k sequences Maximum Number of Waveforms in Memory 64k DC Accuracy 0 5 of setting 20 mV with OdB attenuator no load Maximum Output 16 38V into Hi Z 1 25V i
10. 1 Next Sequence Pointer is set to 2 and sequence 2 Next Sequence pointer is set to 0 When the Agilent E6173 is started a continuous loop of the three waveforms is output sequence 0 sequence 1 sequence 2 sequence gt 1 Determine the starting address to write the segment data Sequence 0 segment numbers 0 to 9 starting segment number 0 Address of segment 0 A24_base A24 offset 4 segment_number A24 base A24 offset 0 30 Programming the Agilent E6173 Chapter 3 Sequence 0 A24_base A2 offset Op Sequence 1 segment numbers 10 to 99 starting segment number 10 Address of segment 10 A24_base A24_ offset 4 segment_number A24 base A24 offset 40 A24_base A24 offset 28 Sequence 2 segment numbers 100 to 999 starting segment number 100 Address of segment 100 A24_base A24 offset 4 segment_number A24 base A24 offset 400 A24_base A24 offset 190 2 Determine the integer to write to the Segment Pointer Sequence 0 first segment 0 Segment_pointer segment_number 2 0 Sequence 1 first segment 10 Segment_pointer segment_number 2 5 Sequence 2 first segment 100 Segment_pointer segment_number 2 50 3 Segment memory downloaded A24 address A24_base A24_ offset 000 Segment 0 LSByte Comments 4 Least Significant bits EOS FALSE A24_base A24_ offset 002 Segment 0 MSWord 16 Most Significant
11. 3 therefore requires two main steps 1 Loading the waveform information into A24 and 2 Controlling the waveform output by setting bits in the A16 control registers gt NEXT SEQUENCE 200000h A24_offset BO000h COUNT 200000h A24_offset A0000h gt SEQUENCE MEMORY 200000h A24_ offset 90000h 200000h A24_ offset 80000h e Figure 3 1 Sequence and Segment memory single channel Chapter 3 Programming the Agilent E6173 23 Note The two channels of the E6173 share a common A24 segment and sequence address space The channel which will be programmed is determined by a bit in the A16 Status Control register offset 04 Waveform Memo ry Waveform memory is divided into two categories segment memory and sequence memory Both segment memory and sequence memory are loaded into A24 address space Figure 3 1 shows the location of segment and sequence memory in A24 Segment Memory Segment memory uses 24 bits for each output value Each segment requires two 16 bit words Segment memory is represented as Address base n 2 Value bits4 19 12 base n Not Used EOS MKR Not Used a Value bitsO 3 The memory address of each 16 bit word begins with the A24 base memory address A maximum of 131072 segments can be stored one half of the usable 256k addresses In Figure 3 1 two waveforms sequences have been stored in segment memory The first waveform sequence 0 is sto
12. 535 For example with a Clock Adjust Register value of 0 the minimum segment duration is 2 00 uSec Setting the Dwell value to 1000 creates a segment duration of 2 002 mSec A waveform can contain any number of segments Each segment defines an output de voltage The voltage output at a particular segment is determined as Outputvoltage Segmentvalue x StepSize In the Agilent E6173A the minimum step value is 31 242370 uVolts with Understanding the Agilent E6173A 15 OdB attenuation This minimum step value is derived by taking the full scale range 16 38 volts and dividing by the total number of steps 22 1048576 Thus the minimum step size is 16 38 16 38 1048576 31 242370 uV Conversely for a desired voltage the segment value DAC code required is Vdesired 31 242370 uV This segment value is represented by a 20 bit 2 s complement binary word The 9 segment sinewave shown in Figure 2 2 could have the following values for each segment iyi Segment Value X Step Size Output Voltage 0 0 31 242 uVolts OV 1 102870 31 242 uVolts 3 2 V 2 157606 31 242 uVolts 4 9V 3 138597 31 242 uVolts 4 3V 4 54737 31 242 uVolts 1 7V 5 54736 31 242 Volts 1 7V 6 138597 31 242 Volts 4 3 V 7 157606 31 242 uVolts 4 9 V 8 102880 31 242 uVolts 3 2 V Seq uences The series of segments that define a waveform are called a sequence Sequences can be added together t
13. Agilent TS 5400 Functional Test System Series IIB Agilent E6173A Arbitrary Waveform Generator User s Manual Manual Part Number E6173 90021 i Agilent Technologies Notices Agilent Technologies Inc 1996 2003 No part of this manual may be reproduced in any form or by any means including electronic storage and retrieval or transla tion into a foreign language without prior agreement and written consent from Agi lent Technologies Inc as governed by United States and international copyright laws Documentation History All Editions and Updates of this manual and their creation date are listed below The first Edition of the manual is Edition 1 The Edition number increments by 1 whenever the manual is revised Updates which are issued between Editions contain replace ment pages to correct or add additional information to the current Edition of the manual Whenever a new Edition is cre ated it will contain all of the Update infor mation for the previous Edition Each new Edition or Update also includes a revised copy of this documentation history page Edition 1 E6173 90000 Februaryl 1996 Edition 2 E6173 90001 May 1996 Edition 3 E6173 90011 September 2000 Edition 4 E6173 90021 August 2003 Manual Part Number E6173 90021 Printed in USA Agilent Technologies Inc 1601 California Street Palo Alto CA 94304 USA Warranty The material contained in this docu ment is provided as is and is su
14. Agilent Technologies standard commercial license terms and non DOD Departments and Agencies of the U S Gov ernment will receive no greater than Restricted Rights as defined in FAR 52 227 19 c 1 2 June 1987 U S Govern ment users will receive no greater than Limited Rights as defined in FAR 52 227 14 June 1987 or DFAR 252 227 7015 b 2 November 1995 as applicable in any technical data Safety Notices Caution A Caution notice denotes a hazard It calls attention to an operating procedure practice or the like that if not correctly performed or adhered to could result in damage to the product or loss of important data Do not proceed beyond a Caution notice until the indicated conditions are fully understood and met WARNING A WARNING notice denotes a hazard It calls attention to an operating procedure practice or the like that if not correctly per formed or adhered to could result in personal injury or death Do not proceed beyond a WARNING notice until the indicated condi tions are fully understood and met Safety Summary The following general safety precautions must be observed during all phases of operation of this system Failure to comply with these precautions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of the system Agilent Technologies Inc assumes no liability for the customer s failure to comply with th
15. D5 D4 D3 D2 D1 DO Appendix B For writes to this register bit 15 is undefined For reads bit 15 is the data valid bit When bit 15 is set 1 the data in bits O through 14 may be considered valid If bit 15 is not set the data in bits O through 14 may not contain a valid value Register Definitions 43 A24 Registers Waveform Memo ry Waveform memory is controlled by the channel select bit in the Status Control Register When this bit is set to 0 the channel 1 waveform memory bank is enabled When this bit is set to 1 the channel 2 waveform memory bank is enabled The use of sequences and segments is described in Chapters 2 and 3 Seg ment Memory Segment memory is a 128k X 24 bit memory space mapped into the first 500 kbytes of the defined A24 space Waveform data is 20 bits wide bits 0 to 19 Bits 20 and 21 are not used Bit 6 is the marker bit Bit 7 is the End of Sequence EOS bit Seg ment Pointer Segment pointer memory is 32k X 16 bit memory mapped directly above the Segment Memory This memory is a pointer to the segment memory Not all segment addresses are decoded and a segment sequence cannot start on an odd memory boundary Repeat Counter The Repeat Counter memory is a 32k X 16 bit memory mapped directly Mem ory above the Segment Pointer memory This memory provides a 16 bit counter to repeat a particular segment sequence Dwell Counter The Dwell Count
16. DDER is the module s logical address and 64 is the number of address bytes per VXI device For example the Agilent E6173A s factory set logical address LADDR is 80 50 therefore it will have a base address of Al6base C000 50 40 C000 1400 D400 or decimal Al6pace 49 152 80 64 49 152 5 120 54272 When the A16 address space is inside the Command Module see Figure B 2 the module s base address is computed as 1FC000 LADDR 40 or decimal 2 080 768 LADDR 64 where 1FCO00 2 080 768 is the starting location of the VXI A16 addresses LADDR is the module s logical address and 64 is the number of address bytes per register based device Again the Agilent E6173A factory set address is 80 If this address is not changed the module will have a base address of 1FCO00 50 40 1FC000 1400 1FD400 or decimal 2 080768 80 64 2 080 768 5120 2 085 888 The register offset is the register s location in the block of 64 address bytes that belong to the module For example the module s Status Control Register has an offset of 04 When you write a command to this register the offset is added to the base address to form the register address 1FD400 04 1FD404 or decimal 2 085 888 4 2 085 292 Register Definitions 37 Control Register Descriptions Manufacturer Identification Register Device Type Register Card Status Control The Arb
17. Repeat Count number maximum repeat count 65 536 Dwell Count number maximum dwell count 65 536 Next Sequence Pointer also contain the stop bit Seg ment Memory This register contains a pointer to the first segment in the sequence This Pointer register is a 16 bit register and so can contain values up to 65536 Since the number of segments can range to 131072 only even number segments can be used to start a waveform The Agilent E6173 multiplies the value of the segment memory pointer by 2 to arrive at the starting address of the first segment in the waveform For example to set the pointer to point to segment number 100 in memory the segment memory pointer value is set to 50 Re peat Count The value in this register specifies the number of times the current sequence is to be repeated a sequence may have up to 131072 segments For example a burst of sinewaves may be generated by programming a value into the repeat counter A repeat value of 0 outputs the sequence once for example a single sinewave a value of 1 outputs two sinewaves or sequences the first and a repeat of 1 A repeat count value of 99 would generate a 100 sinewave burst Chapter 3 Programming the Agilent E6173 25 Dwell Count Each segment value is held at the output for the sample duration A value in the Dwell Count register causes the output to be held for multiples of the sample duration A value of 0 holds the output for the sample duration a value of 1
18. S bit of the current sequence is found 28 Programming the Agilent E6173 Chapter 3 Abort Operation Note Starting the Agilent E6173 When this register base 12 is read the register contains the current sequence number Bit 15 of this register is a valid bit When bit 15 of this register is set bits 0 through 14 define the present sequence number The Card Status Control register contains an abort bit for each channel This register is at address base 04h Bit 10 is the channel 1 abort bit Bit 11 is the channel 2 abort bit When this bit is set 1 the Agilent E6173 stops at the next EOS bit and hold the voltage of the last segment at the output You can control the abort output voltage by the placement of the EOS bit in segment memory Following an abort all internal sequence pointer registers are reset and you must restart the Agilent E6173 using the start bit in the Card Status Control register The Agilent E6173 always begins at sequence 0 unless the On the Fly register contains a different starting sequence value following an abort The specific sequence for aborting the waveform must be followed to insure proper operation of the E6173 In order to properly abort the waveform follow the sequence listed below 1 Post the abort bits Status Control register bit 10 channel 1 amp bit 11 channel 2 2 Remove the start and abort bits start Status Control register bit 8 channel 1 and bit 9 channel 2
19. TLO TTL Input Select 0 0 0 TTL Trigger 0 0 0 1 TTL Trigger 1 0 1 0 TTL Trigger 2 0 1 1 TTL Trigger 3 1 0 0 TTL Trigger 4 1 0 1 TTL Trigger 5 1 1 0 TTL Trigger 6 1 1 1 TTL Trigger 7 Register Definitions 41 EN Trigger output enable bit The E6173 has the capability of driving the VXI backplane triggers By setting the EN bit to 0 the backplane trigger driver is disabled By setting this bit to 1 the backplane trigger driver is enabled and the trigger as selected by TO T2 bits 5 6 and 7 can be driven by the E6173 See related control bit SEL SEL trigger output select bit The E6173 can drive the VXI backplane triggers by one of two sources Either the channel marker output can drive the VXI backplane trigger or the front panel trigger input can be routed such that it drives the VXI backplane trigger When SEL is set to 0 the marker is selected as the source for the VXI backplane trigger output When SEL is set to 1 the front panel trigger input is routed to the VXI backplane trigger output TO T2 TTL output select bits These bits select which VXIbus TTL trigger line to use as defined in the following table T2 T1 TO TTL Output Select 0 0 0 TTL Trigger 0 0 0 1 TTL Trigger 1 0 1 0 TTL Trigger 2 0 1 1 TTL Trigger 3 1 0 0 TTL Trigger 4 1 0 1 TTL Trigger 5 1 1 0 TTL Trigger 6 1 1 1 TTL Trigger 7 Clock Adjust This read write register adjus
20. a a n cnn c ran aran 38 Manufacturer Identification Register ooonncnncnnninnconoccnonononcconaconannnnonnncnnnonn conan 38 Device Type Register ct e din et eed 38 Card Status Control Register 0 0 0 ceeeseeseceseceeeeeeeeeseeeaeeeseceseceseeeeeeseeeaeeeaaeenaees 38 Offset Regist noi coe Dineen Cate Ss Se tii 40 Channel Status Register tots vcd cee ceili eis dither hte ethene ini 40 Channel Trigger Register AAA caleivs secebxecece E eeu Sas 41 ANS TAC O AN 42 On the Ply Resister cnn 43 A24 RESISIETS a tt NA A A ds ln tea 44 Waveform Memory ou ceeccessessseessceseceseeeseeeseessaecsaeeseceseceseecaaecsecsseeseeeaeeeaaenaees 44 Sepment Memory iii ee el ei ee aan ents 44 Sement POMC liarla nt adas aii 44 Repeat Counter Memory usina ett 44 Dwell Counter Memory uri eae line ia 44 Next Sequence Pointer cocina ein ie awe ene eee pn 44 Appendix C Calibration ssccsscsssssscsscsscsssesssssesscssessnssessessscsscsscsssssnccsecsesesesssenceseesesssnsesssesssnseases 45 Calibration Period ucraniana 45 Equipment Requited siseses inen eaen lero ii aicairlesso teaulevbanecttbancese 45 Calibration Proc dure iii dica 45 POCO UTE minita A Ed A a eaten ee oN ie 46 INdeX APRA E A S A N 49 Chapter 1 Getting Started Using this Chapter Description Chapter 1 This chapter describes the Agilent E6173A formerly Agilent Z2471A Arbitrary Waveform Generator module This chapter contains the following sections
21. aveform follow the sequence listed below 1 Post the abort bits Status Control register bit 10 channel 1 amp bit 11 channel 2 2 Remove the start and abort bits start Status Control register bit 8 channel 1 and bit 9 channel 2 abort Status Control register bit 10 channel 1 amp bit 11 channel 2 The aborted channel s will set the stop bit s once abort is complete Status Control register bit 12 channel 1 and bit 13 channel 2 SP0 Stop channel 1 A 1 indicates channel 1 is stopped SP1 Stop channel 2 A 1 indicates channel 2 is stopped M MODID bit Read only bit Set to 0 when the module has been selected A24 Address enable bit Writing a 0 to this bit enables A16 addressing Writing a 1 to this bit enables A24 addressing Appendix B Register Definitions 39 Offset Register This register sets the offset address to map VXIbus A24 address space to the module A read write register base 06 base 07 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O15 O14 013 012 Undefined 012 O15 Defines the offset address that maps 1 Mbyte of VXIbus A24 space to the module Channel Status This read write register sets each channel output characteristics The H channel select bit CH in the Status Control Register sets which channel Register this register affects Note The E6173 uses latching relays in the analog output s
22. b ject to being changed without notice in future editions Further to the max imum extent permitted by applicable law Agilent disclaims all warran ties either express or implied with regard to this manual and any infor mation contained herein including but not limited to the implied warran ties of merchantability and fitness for a particular purpose Agilent shall not be liable for errors or for incidental or consequential damages in connection with the furnishing use or perfor mance of this document or of any information contained herein Should Agilent and the user have a separate written agreement with warranty terms covering the material in this document that conflict with these terms the warranty terms in the sep arate agreement shall control Technology Licenses The hardware and or software described in this document are furnished under a license and may be used or copied only in accordance with the terms of such license Restricted Rights Legend If software is for use in the performance of a U S Government prime contract or sub contract Software is delivered and licensed as Commercial computer soft ware as defined in DFAR 252 227 7014 June 1995 or as a commercial item as defined in FAR 2 101 a or as Restricted computer software as defined in FAR 52 227 19 June 1987 or any equivalent agency regulation or contract clause Use duplication or disclosure of Software is subject to
23. ce is inside or outside the Agilent E1405B or Agilent E1406A Command Module Register Definitions 35 Agilent E6173A FFFFig A16 Register Map Register 16 BIT Register 7 Offset Words Address On the Fly Clock Adjust Channel Trigger FFFF46 C00016 A16 Address Space C0001 Base Address C0001 Logical Address 40 OR 49 152 Logical Address 64 16 Z2471A FIG APPB1 Register Address Base Address Register Offset Figure B 1 Register Address Location within A16 E1406 Address Map FFFFFF 16 E00000 16 SEQUENCE MEMORY WAVEFORM MEMORY SEGMENT MEMORY Agilent E6173A A16 Register Map Offset Words 1F0000 1g Register plat aac 1F0000 1g 1F0000 146 PRS Z2471A FIG APPB2 2 080 768 200000 1g 200000 1g 000000 1g Base Address 1FC00046 Logical Address 40 OR 2 080 768 Logical Address 64 Register Address Base Address Register Offset Figure B 2 A16 Address Space in the Agilent E1406 36 Register Definitions Appendix B A16 Address Space Outside the Command Module A16 Address Space Inside the Command Module Register Offset Appendix B When an Agilent Command Module is not a part of your VXIbus system see Figure B 2 the Agilent E6173A base address is computed as Al 6base C000 LADDR ie 401 or decimal Al6base 49 152 LADDR 64 where C000 49 152 is the starting location of the register addresses LA
24. er memory is a 32k X 16 bit memory mapped directly above the Repeat Counter memory This memory provides a 16 bit counter Memory to dwell on a particular segment Next Seq uence The Next Sequence Memory is a 32k X 16 bit memory mapped directly Pointer above the Dwell Counter memory This memory provides the next sequence address which will execute when the EOS bit if found Bit 15 of this register is the Stop Bit 44 Register Definitions Appendix B Appendix C Calibration Calibration Period The Agilent E6173A formerly Agilent Z2471A is adjusted at the factory before shipment and should not require recalibration before use A calibration interval of 1 year is generally sufficient Equipment Required To calibrate the Agilent E6173A in addition to the VXIbus mainframe and commander you will need a DVM with the following characteristics 0 1 accuracy from 20 00 V to 20 00 V The Agilent 34401A is recommended Calibration Procedure Figure C 1 shows the location of the adjustments You will need side panel access while the Agilent E6173A is installed and running Channel 1 OFFSET GAIN Channel 1 eZ OFFSET GAIN 6 o 005 335k Z2471A APPC1 e Figure C 1 Adjustment Locations Appendix C Calibration 45 Procedure Register Use the following procedure to calibrate the Agilent E6173A Procedures for downloading and starting the Agilent E6173A are given in Chapter 3 of this manual
25. ese requirements General This product is provided with a protective earth terminal The protective features of this product may be impaired if it is used in a manner not specified in the operation instructions WARNING DO NOT OPERATE IN AN EXPLOSIVE ATMOSPHERE Do not operate the system in the presence of flammable gases or flames If the equipment in this system is used in a manner not specified by Agilent Technologies the protection provided by the equipment may be impaired Cleaning Instructions Clean the system cabinet using a soft cloth dampened in water Safety and Support Information WARNING DO NOT REMOVE ANY SYSTEM COVER Operating personnel must not remove system covers Component replacement and internal adjustments must be made only by qualified service personnel Equipment that appears damaged or defective should be made inoperative and secured against unintended operation until they can be repaired by qualified service personnel Environmental Conditions Unless otherwise noted in the specifications this system is intended for indoor use in an installation category II pollution degree 2 environment It is designed to operate at a maximum relative humidity of 80 and at altitudes of up to 2000 meters Refer to the specifications tables for the ac mains voltage requirements and ambient operating temperature range Before applying power Verify that all safety precautions are taken Note
26. ext segment number that segment is downloaded and output and so on until the EOS bit is found TRUE When the EOS bit is found the Next Sequence Pointer is used to jump to the next sequence to output Channel Selection The Agilent E6173 has two independent output channels When addressing A24 memory the channel desired must be specified The Card Status Control register contains a bit that defines which channel an operation applies to The register is in A16 memory at location base 04 and bit 4 defines the channel When the bit is reset 0 channel 1 operations are specified when the bit is set 1 channel 2 operations are specified The following table shows how the registers are affected by the channel selection bit 26 Programming the Agilent E6173 Chapter 3 Address Register Name Operations on A16 space base 00 Manufacturer ID Both Channels base 02 Device Type Both Channels base 04 Card Status Control Both Channels base 06 Offset Both Channels base OC Channel Status Channel selected in Register 04 bit 4 base OE Channel Trigger Channel selected in Register 04 bit 4 base 10 Clock Adjust Channel selected in Register 04 bit 4 base 12 On the Fly Channel selected in Register 04 bit 4 A24 space All Segment and Channel selected in Register 044 bit 4 Sequence A24 Access Memory Load Run EOS and Stop Control Bits EOS Chapter 3 The Card Sta
27. first segment in the lowest memory locations For example the nine segment sine wave will occupy eighteen adjacent 16 bit memory locations Memory locations are read and output at the sample rate starting with the first segment and incrementing the VXI memory location by 4 until an End of Sequence bit is found The End of Sequence bit is bit 7 of the base n 16 bit word of segment memory When this bit is set 1 the Agilent E6173A outputs the segment value voltage set in the upper 16 bit word and the last four bits of the base n 16 bit word and then does one or more of the following If interrupts are enabled and stop bit is set sets a VXIbus interrupt to the controller holds the last segment value on the output and stops Jumps to the first segment of the next sequence if a stop bit is not present Repeats this sequence by jumping to the first segment of the current sequence if the sequence repeat is set or if the next sequence pointer points to itself Bit 6 of the base n 16 bit word is the Marker bit When this bit is set 1 the Agilent E6173A will output a marker You can use this marker bit to synchronize the output with other instruments The marker output is a TTL compatible pulse approximately 5 clocks wide Understanding the Agilent E6173A 19 Note The E6173A marker signal is sourced directly from the state machine sequencer with very little delay while the waveform output is delayed slightly due to t
28. ge 44 Addressing the Registers The Base Address Appendix B To access a specific register for either read or write operations you must use the register address Register addresses for the VXI plug in modules are found in an address space known as A16 The exact location of the A16 address space within a VXIbus master s memory map depends on the design of the VXIbus master you are using for the Agilent E1405B and E1406A Command modules the A16 space starts at 1FO000 The A16 space is further divided so that the modules are addressed only at locations above 1FC000 within A16 Further every module is allocated 64 register addresses 40 The address of a module is determined by its logical address set by the address switches on the module times 64 40 For the Agilent E6173A module the factory preset address is 80 50 so the addresses start at 1FD400 1FC000 50 40 1FD400 Register addresses for register based devices are located in the upper 25 of VXI A16 address space Every VXI device up to 256 is allocated a 64 byte block of addresses Figure B 1 shows the register address locations within A16 address space in the Agilent E1406A Command Module When you are reading or writing to a module register you must specify a hexadecimal or decimal register address This address consists of a base address plus a register offset The base address used in register base programming depends on whether the A16 address spa
29. ger hold_off never trigger ojojoj jo 0 0 1 1 0 oO oOo o Software trigger immediate always L R Load Run memory bit When set to 0 selects the load memory function When set to 1 selects run from memory LoZ Output impedance select bit When set to 0 selects a 50 Q output impedance When set to 1 selects low impedance TRL Trigger event select bit When set to 0 selects edge sensitivity triggering When set to 1 select level triggering TP Trigger polarity select bit When bit 10 TP is set 1 the trigger is set to a high level or rising edge dependent upon the state of the TRL bit When bit 10 TP is reset 0 trigger is set to a low level or a falling edge dependent upon the state of the TRL bit This read write register selects the trigger source for each channel The A channel select bit CH in the Status Control Register sets which channel Register this register affects base 0E base 0F 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undefined T2 T1 TO SEL EN TTL2 TTL1 TTLO TTLO TTL2 TTL trigger input select bits These bits select which VXIbus TTL trigger line to use as defined in the following table Note These selection bits are only valid if the TTL backplane is selected as the Appendix B trigger source see channel status register bits 4 6 TTL2 TTL1 T
30. he output filter delays As a result the marker output will proceed the waveform output Expected lead time will be approximately 2 us when operating with the 600 kHz filter and 12 us when operating with the 40 kHz filter Segment Memory Example Since each segment requires two memory locations the segments are shown in the following way Address base n 2 Seren Value bits 4 19 base n Not Used EOS MKR Not Used KER Value bits 0 3 In this convention the first segment is located in VXIbus memory at the A24 base plus an offset to the desired memory location n Bits that are marked as not used can be 0 or 1 with no consequence In this manual these bits are assumed to be 0 If the first segment in a sequence is located at the A24 address base n 0 the memory contents for the 9 segment sinewave shown in Figure 2 2 could look like this Memory Address Binary Value Output Voltage 0x200022 1110011011100010 0x200020 0000000011000000 0x20001E 1101100110000101 0x20001C 0000000000001001 0x20001A 1101111000101001 0x200018 0000000000001011 0x200016 1111001010100011 0x200014 0000000000000000 0x200012 0000110101011101 0x200010 0000000000000001 0x20000E 0010000111010110 0x20000C 0000000000000101 0x20000A 0010011001111010 0x200008 0000000000000110 0x200006 0001100100011101 0x200004 0000000000000110 0x200002 0000000000000000 0x200000 0000000000000000 Segment 8 Segment 7 Segment 6 Seg
31. he power cord or have a qualified electrician install an external switch SIO lO Fle gt Regulatory Markings CE The CE mark is a registered trademark of the European Community The CSA mark is a registered trademark of the Canadian Standards G e Association The C tick mark is a registered trademark of the Spectrum Management Agency of Australia This signifies compliance with the Australian EMC Framework regulations under the terms of the Radio Communications Act of 1992 YNi0149 ISM 1 A This text indicates that the product is an Industrial Scientific and Medical Group 1 Class A product CISPR 11 Clause 4 Safety and Support Information 5 Service and Support 6 Any adjustment maintenance or repair of this product must be performed by qualified personnel Contact your customer engineer through your local Agilent Technologies Service Center Agilent on the Web You can find information about technical and professional services product support and equipment repair and service on the Web http www agilent com Click the link to Test amp Measurement Select your country from the drop down menus The Web page that appears next has contact information specific for your country Agilent by Phone If you do not have access to the Internet call one of the numbers in Table 2 Table 2 Agilent Call Centers and Regional Headquarters United States and Canada Test and Measurement Cal
32. holds the output for two sample durations and so on For example using the 2 uSec internal time base and no clock adjust a Dwell count register value of 0 holds the segment value for 2 uSec A Dwell Count register value of 2 holds the segment value for 6 uSec Next Seq uence This register holds the next sequence number This is the sequence that will Pointer execute when the current sequence is complete Sequence numbers can range from 0 to 32767 Setting the Next Sequence Pointer value to the current sequence number results in a continuous output of the waveform Note The value of the Next Sequence Pointer is the Sequence Number not the address offset of the sequence Bit 15 of the Next Sequence pointer is the Stop Bit The Agilent E6173 stops the sequence when this bit is set The output is held at the value of the last segment loaded with the EOS bit General Programming Information The segment and sequence data is loaded into A24 memory The status and control for the Agilent E6173 is in A16 Appendix B contains detailed information about data for these registers Seq uence The default sequence executed by the Agilent E6173 at start up is sequence i 0 Alternatively a different sequence may be started by writing the sequence Operation number to the On the Fly sequence jump register before start up Once the Agilent E6173 is started each segment value is downloaded and output The segment memory is stepped to the n
33. ilent E6173 continues until the Stop bit is found When the Stop bit is found the last segment voltage is held at the output A second edge trigger event can restart the Agilent E6173 at the point of the Stop Bit Level Sensitive When level sensitive trigger operations are specified a bit in the Channel Status register defines the level to be either high or low The register is in A16 space at base OC and bit 10 controls the level detection When this bit is set 1 the Agilent E6173 will trigger on high levels When reset 0 low active triggering 1s selected When the appropriate trigger level occurs the Agilent E6173 loads the next sequence parameters and begins operation Operation continues as long as the appropriate trigger level exists or until the Stop Bit is found When the Stop bit is found the last segment containing the EOS bit voltage is held on the output To restart after a Stop Bit termination the Start Bit must be cleared and posted again and the appropriate trigger level applied immediate J UMP The On the Fly Next Sequence register base 12 can be written to and Operation will override the value contained in the next sequence register at any time If several sequences are put in memory and each sequence is set to repeat On the Fly continuously the waveform output can be changed to any sequence by poking the next sequence into this register The Agilent E6173 will jump to the sequence indicated when the EO
34. inter value stored in sequence memory The first segment pointer value is 0 unless it has been modified by a write to the On the Fly register before starting the waveform The first segment can be the first segment of an entire waveform or can be a zero output one segment sequence The last segment in a sequence is indicated by the use of a special bit EOS in the segment memory The use of the segment and sequence memory is described in more detail later in this Chapter and in Chapter 3 The sample rate and segment duration are directly related as n segmentduratio samplerate The sample rate or how often the output changes to the next segment value can be set either internally or by the use of an external clock input Sample rates can be set as Using Internal Clock 2 00 uSec Clock Adjust Count X 100E Sec Using External Clock 20 External Clock Frequency Clock Adjust Count External Clock Frequency The Clock Adjust Count is set in the Clock Adjust Register Refer to Appendix B for more information about this register haclock adjust count of 0 the minimum segment duration or fastest sample rate is 2 00 uSec or 500 kHz You can set the segment duration using the Clock Adjust Register or you can set a dwell on each segment A dwell instructs the Agilent E6173A to hold or dwell on each segment for a specified number of segment durations You can set a dwell from 0 to 65
35. itrary Function Generator has the following A16 control registers Manufacturer ID Register base 00p Device Type Register base 02 Status Control Register base 04 Offset Register base 06 Channel Status Register base 0C Channel Trigger Register base 0E Clock Adjust Register base 10p On the Fly Register base 12 The Manufacturer ID Register is a 16 bit read only register at address 00y with the most significant byte MSB at 00 and the Least Significant Byte at 01 Reading this register returns the Agilent Technologies identification CFFF The Device Type Register is a 16 bit read only register at address 02 with the Most Significant Byte MSB at address 02 and the Least Significant Byte LSB at address 03 Reading this register returns 3222 The Card Status Control Register is a read write register at address 04 that Regi ster controls the module and indicates its status The following shows the register bit assignments base 04 base 05 15 14 13 12 11 10 9 8 7 6 D 4 3 2 1 0 Write A24 Undefined A1 AO ST1 STO Undefined D Undefined CH Undefined Read A24 M SP1 SPO A1 AO ST1 STO B D Undefined CH Undefined 38 Register Definitions R reset The module reset is accomplished by setting bit 0 of the status control register to 1 and then back to 0 After the reset procedure the sequence
36. l Center 800 452 4844 toll free in US Europe 41 22 780 8111 Japan Measurement Assistance Center 81 0426 56 7832 Latin America 305 269 7548 Asia Pacific 85 22 599 7777 Safety and Support Information Contents Chapter 1 Getting Started sac O O 9 Usingithis Chapters coria ninia 9 ONO 9 Warnings and Cautions coiciociocan citada a eviedelaaestedtisbageteevys eal cevees 10 Setting th eAddress Switcher sorae ti cd 11 Setting the Interrupt Mesina cleyevaddesebenagizesvia igevteceuuseeasadeaveeacs 11 Installing in a VXI Mainframe cee eeeeseeseceseceseceseceseesaeeeaeceaeecsaeeseceseeeseeeaaeenaees 12 Chapter 2 Understanding the Agilent E6173A csssccssssseccssscsssssssssccsscssscsssecescessscsssseecscoss 13 Using this Chapter ata A ad 13 Block Diasramy 3 dia tien Aue thee hates tanya anand acta nites eat eae Hae 13 About Arbitrary Waveforms ccccccccessecesseeeseeceeeeecsaecesaeceeaeeseaeeceaeeeaecneaeceeaeeseeees 14 Defining Waveforms dad ta 14 Sample Rate eis loans 15 SOQMEMUS ui ariete toi 15 SEQUENCES sa Aa AAA he Rae RE AA tas 16 Defining Segments and Sequences ces eeceeseceseceeeeeseceseeeseeeseceaecesueeseeeseeeaeeeaaeeaeees 18 Segment Valle ticas sheet eas ieee ante 18 SEQUENCES iiss Len RAG el ay A Wan he AAA IS 19 YA TA ASA EEEE addict 19 Segment Memory Example ccoo nena a A a a 20 Chapter 3 Programming the Agilent E6173 sccssssccssssscsssssssssscsscsssscssss
37. lock Diagram Segment Sequence Pointer Repeat Ram Ram DIGITAL 16 x 32k 16 x 32k Sse tee STATE MACHINE INTERFACE Channel 1 ENABLE State Machine CHANNEL 1 Xilinx MARKER CHANNEL 4 TRIGGER CHANNEL 1 lt VXI Interface RELAY CONTROL CHANNEL 1 U301 RELAY CONTROL CHANNEL 2 VXI Xilinx SYSCLK Control DATA STATE MACHINE INTERFACE CLOCK CLK10 peel CHANNEL 2 Channel 2 ENABLE gt MARKER CHANNEL 2 TRIGGER CHANNEL 2 lt EXT CLOCK IN Repeat Sequence Ram Ram ANALOG Each Channel 16x32k 16x 32x Rx FILTERS l DATA Sy OUTPUT 600 kHz ATTENUATORS IMPEDANCE l OPTO ISOLATOR OUTPUT SS ON OFF r des A reel Lars Pa erosi Dr I 3 E s 16 38V Max ENABLE gt y l OPTO ISOLATOR b Figure 2 1 Simplified Block Diagram Chapter 2 Understanding the Agilent E6173A 13 About Arbitrary Waveforms Defining Waveforms A waveform is created out of a series of dc voltages Each de voltage is referred to as a segment A waveform can have any number of segments The more segments used to create a waveform the more accurately the output will represent a continuous waveform More segments however require more memory to store and limit the upper frequency of the waveform A series of segments that define a waveform are referred to as a sequence Each sequence defines a different waveform Multiple sequences can be loaded into memory at the same time Sequences can be out
38. ment 5 Segment 4 Segment 3 Segment 2 Segment 1 Segment 0 20 Understanding the Agilent E6173A Chapter 2 Note the use of the EOS bit and the marker bit at memory address 0x200020 These bits indicates the end of the sequence and direct a marker to be output at the end of the sequence If the sequence is set to repeat and no clock adjustment is made the 2uSec sample rate will output all nine segments in 18 uSecs creating an output frequency of 55 5 kHz Chapter 2 Understanding the Agilent E6173A 21 Notes 22 Understanding the Agilent E6173A Chapter 2 Chapter 3 Programming the Agilent E6173 Using this Chapter This chapter describes procedures and examples for programming the Arbitrary Waveform Generator module This chapter only describes the control registers in general terms or in specific instances Complete descriptions of all the status and control registers is given in Appendix B The chapter has the following sections e A16 and A24 Memory 2 0 cece eee page 23 Sequence Memory Registers 0 00 00 mom page 25 General Programming Information page 26 Example musa Levee tegen hate tee laa page 30 A16 and A24 Memory You will use both A16 and A24 VXIbus memory to program the Agilent E6173 Hardware control occurs in the A16 locations and waveform information is loaded into A24 space Programming the Agilent E617
39. n 50Q Coarse Attenuator 0 or 20 dB Minimum Short Circuit Output Current 25mA Isolation Each output individually isolated to 42 Vpeak 0 gt 1 0 MQ Squarewave Rise Fall Time 2 Susec 10 to 90 Appendix A Sine wave THD 180 point sine wave maximum amplitude 9 harmonics into 1 kQ 60 dB to 1 kHz Sine wave Spurious Non harmonic Distortion 180 point sine wave maximum amplitude intol kQ The greater of 60 dBc or 45 dBm to 1 kHz Absolute ac Accuracy 180 point sine wave maximum amplitude into 1 kQ 0 1 dB attenuator error Attenuator Error DC to 1 kHz 0 1 dB 20 dB Output Impedance Low Z or 50Q calibrated for open circuit Output Filter programmable 40 kHz low pass or 600 kHz Waveform Sequence Looping 1 to 64k or continuous Frequency Sweep via sequence memory or external swept timebase External Timebase Range dc to 10 MHz Trigger Sources auto hold software VXI TTL TRG or faceplate Faceplate Connectors external clock per channel output trigger in and marker out Output Protection can withstand 1 msec 50 V spike can withstand 16 V continuous short Specifications 33 Notes 34 Specifications Appendix A Appendix B Register Definitions Using this Appendix This appendix contains Addressing the Registers 0 0 0 0 ce eee eee page 35 Control Register Descriptions 00000 page 38 e A24 Registers 0 eee pa
40. nt to sequence 2 12 Measure the output with the DVM Determine that the calibration is successful by verifying the E6173 output voltage to be 16 38V 92 mV 13 Repeat steps 2 through 12 for Channel 2 Calibration 47 Notes 48 Calibration Appendix C Index A A16 and A24 Memory 23 A24 Access 27 A24 Registers 44 A24 registers dwell counter memory 44 next sequence pointer 44 repeat counter memory 44 segment memory 44 segment pointer 44 waveform memory 44 Abort Operation 29 About arbitrary waveforms 14 Address switch setting 11 Addressing the registers 35 Arbitrary waveforms 14 sample rate 15 segments 15 sequences 16 B Base address 35 Block diagram 13 C Calibration equipment required 45 period 45 procedure 45 Card status control register 38 Cautions and warnings 10 Channel Selection 26 Channel status register 40 Channel trigger register 41 Clock adjust register 42 Control register descriptions 38 card status control register 38 channel status register 40 channel trigger register 41 clock adjust register 42 device type register 38 manufacturer identification register 38 offset register 40 on the fly register 43 D Defining segments and sequences 18 markers 19 segment value 18 Defining waveforms arbitrary 14 Description instrument 9 Device type register 38 Dwell Count 26 E Example of segment memory 20 Examples 30 single sequence 3
41. o create complex waveforms To use sequences you need to consider three parameters An end of sequence bit to indicate the last segment in a sequence A sequence repeat value to indicate how many times this sequence should be repeated A next sequence pointer to show either which sequence to output next or where to stop An End of Sequence bit indicates that the sequence is done that is all the segments have been output When this bit is found the Agilent E6173A can stop and hold the last voltage output value of the last segment can jump to another sequence in memory or can repeat the last sequence any number of times 16 Understanding the Agilent E6173A Chapter 2 Note Ifa sequence does not have a repeat value or a next sequence pointer but does contain a stop bit the output of the Agilent E6173A is left at the de value of the last segment in the sequence Every segment sequence MUST have an end of sequence bit Every sequence has a next sequence pointer If a segment does not have EOS set segment memory will roll over and the waveform sequence is repeated If the segment does have the EOS set but a valid next sequence address has not been stored the Agilent E6173A may jump to a random address producing unpredictable results Even if a repeat value is stored the next sequence pointer must be stored or the next sequence pointer must contain the stop bit Figure 2 3 shows an example ramp wavef
42. or Warnings and Cautions WARNING SHOCK HAZARD Only service trained personnel who are aware of the hazards involved should install remove or configure the switch module Before you remove any installed module disconnect AC power from the mainframe and from other modules that may be connected to the modules Caution STATIC ELECTRICITY Static electricity is a major cause of component failure To prevent damage to the electrical components in the switch module observe anti static techniques whenever removing a module from the mainframe or whenever working on a module 10 Getting Started Chapter 1 Setting the Address Switch Note The logical address switch LADDR factory setting is 80 You may have to change the setting during module installation Valid address values are from 1 to 255 If the Arbitrary Waveform Generator is used with an Agilent E1405B or E1406A Command Module in a C Size Mainframe refer to the Agilent Command Module User s Guide for addressing information Figure 1 1 shows the switch location and factory setting The value set on the address switch should be an integer multiple of 8 if the module is an instrument used in an Agilent E1405B or E1406A VXIbus mainframe Setting the Interrupt Line Chapter 1 The Arbitrary Waveform Generator can generate VXIbus interrupts The interrupt is sent to and acknowledged by the Command Module or other controller via the VXIbus back plane inter
43. orm output The example is made up of three sequences Sequence A is a ramp of 6 segments The segment dwell is set to O and the sequence repeat is set to 0 The next sequence pointer is set to point to the first segment in sequence B Sequence B is identical to sequence A except that segment dwell is set to 1 each segment is held for two samples The next sequence pointer is set to point to the first segment in sequence C Sequence C is a mirror image of sequence A The segment dwell is set to O but the sequence repeat is set to 2 and so executes the sequence three times The next sequence pointer is set to the first segment in sequence A All the sequences are then repeated indefinitely Figure 2 3 Example Waveform Output Chapter 2 Understanding the Agilent E6173A 17 Defining Segments and Sequences Segments are defined with a 24 bit memory register referred to a segment memory The 24 bits must be put in VXIbus memory as two 16 bit word writes The method used by the Agilent E6173A puts the 16 most significant bits in the n 2 memory location and the four least significant bits in the n 0 memory location To show this as two 16 bit registers where n is the segment number Address 15 14 13 12 11 10 MSB Segment Value base n 2 7 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ase n Not Used EOS MKR Not Used Segment Value LSB Seg ment Value The segment value is a 20 bit
44. output Stop Control The Stop Control bit is bit 15 of the Next Sequence Pointer If the bit is set 1 the Agilent E6173 will complete the current sequence and stop The voltage of the last segment which contained the EOS bit will be held on the output After the stop bit has been set 1 the Agilent E6173 can be restarted and continue running from where the stop bit occurred by 1 Resetting the Start Bit to O Register base 04 bits 8 or 9 2 Setting the Start bit to 1 Register base 04 bits 8 or 9 3 Applying an external trigger pulse if configured for trigger Trigger Operation The Agilent E6173 can be externally triggered in two ways edge sensitive or level sensitive The Channel Status register contains a bit that sets the trigger mode The register is in A16 space at base OC and bit 9 controls the trigger mode When bit 9 is set 1 level sensitive trigger operations are used Resetting bit 9 0 selects edge sensitive trigger operations Edge Sensitive When edge sensitive trigger operations are specified a bit in the Channel Status register defines the edge to be either rising or falling The register is in A16 space at base OC and bit 10 controls the edge detection When this bit is set 1 rising edges are selected Bit 10 set to O selects falling edge triggers When the appropriate trigger condition rising or falling edge occurs the Agilent E6173 loads next sequence parameters and begins operation The Ag
45. put in any order or linked together A sequence can be repeated A continuous waveform for example is created by repeating a single sequence infinitely a single waveform is output when a sequence is output only once and a de output is created by repeating a single segment sequence infinitely Sequences are described beginning on page 2 lt Reference gt Figure 2 2 shows a simple sinewave created using 9 segments The figure demonstrates how a series of dc voltages can be used to represent a waveform To create a waveform you must know two parameters The step size de voltage level at each point and How often the steps occur sample rate or how long each step is held segment duration These parameters are described in more detail later in this Chapter Figure 2 2 Segment Sinewave The segments that create a sequence waveform are loaded into VXIbus 14 Understanding the Agilent E6173A Chapter 2 Chapter 2 Sample Rate Note Segments A24 memory Multiple waveforms can be loaded at the same time and all segments are loaded into adjacent memory locations The Agilent E6173A when instructed to output steps through these memory locations in ascending order To send the correct waveform the Agilent E6173A must know the starting segment memory location and the ending segment memory location Upon start up the Agilent E6173A determines the address of the first segment in a sequence by loading the segment po
46. red at location A24_base A24_offset n As shown the A24_base is 200000 and for the first segment n 0 The A24_offset if not 0 is set by the system memory map Since VXIbus memory requires even byte addressing and since each segment requires two 16 bit words the next segment is located at memory location A24_base A24_offset 4 n The segments are therefore loaded into memory by incrementing the address by 4 for each segment number n The last segment of the first waveform is indicated by the EOS bit 24 Programming the Agilent E6173 Chapter 3 Sequence Memory A maximum of 32k sequences may be stored The sequence memory is located at a fixed location with respect to the A24_base and A24_ offset Figure 3 1 shows the sequence memory in the A24 memory space Each sequence consists of four registers Segment Memory Pointer Repeat Count number Dwell Count number Next Sequence Pointer also contains the stop bit Each register is located at an absolute address with respect to the A24_base address Sequence Number Segment Pointer Repeat Count Dwell Count Next Sequence Pointer A24_base A24_ offset 0x87FFF Ox97FFF OxA7FFF OxB7FFF T T T T T T T T 0x80004 0x90004 0xA0004 0xB0004 0x80002 0x90002 0xA0002 0xB0002 0x80000 0x90000 OxA0000 0xB0000 Sequence Memory Registers As described sequence memory contains four sequence control registers Segment Memory Pointer
47. rify there are multiple and sufficient protective means rated for the voltages you are applying to assure the operator will NOT come into contact with any energized conductor even if one of the protective means fails to work as intended For example the inner side of a case cabinet door cover or panel can be covered with an insulating material as well as routing the test cables to the module s front panel connectors through non conductive flexible conduit such as that used in electrical power distribution Safety Symbols and Regulatory Markings Symbols and markings on the system in manuals and on instruments alert you to potential risks provide information about conditions and comply with international regulations Table 1 defines the symbols and markings you may encounter Table 1 Safety Symbols and Markings Safety symbols Warning risk of electric shock Caution refer to accompanying documents Alternating current Both direct and alternating current Earth ground terminal Protective earth ground terminal Frame or chassis terminal Terminal is at earth potential Used for measurement and control circuits designed to be operated with one terminal at earth potential Switch setting indicator O Off On Standby supply units with this symbol are not completely disconnected from ac mains when this switch is off To completely disconnect the unit from ac mains either disconnect t
48. rupt lines Different controllers treat the interrupt lines differently and you should refer to your controller s documentation to determine how to set the interrupt line on your module Refer to Figure 1 1 to change the interrupt line used by the module If an interrupt is to be used you should generally select a line other than 1 Level 0 disables the interrupt The module s factory setting is 1 To change the setting turn the rotary selector with a small flat blade screwdriver Getting Started 11 Installing in a VXI Mainframe The Arbitrary Waveform Generator can be installed in any available mainframe slot except slot 0 Installation in an Agilent E1400B mainframe is shown below VXIbus C size Mainframe o o o o 4 rey a L E lo o 2 18 4 4 rert err per et LU 990 Figure 1 2 Installing the Agilent E6173A 12 Getting Started Chapter 1 Chapter 2 Understanding the Agilent E6173A Using this Chapter This chapter contains information about the operation of the Arbitrary Function Generator Specifically this chapter contains e Block Diagram isis spreen ia cece eee page 13 About Arbitrary Waveforms 0 200000 o page 14 Defining Segments and Sequences page 18 Segment Memory Example 0 000000 page 20 B
49. shown Single Seq uence For example to create a single continuous output sinewave containing 100 segments 1 Load sequence 0 information into sequence memory set the Next Sequence Pointer to 0 2 Load segments 0 through 99 of segment memory Upon start up the Agilent E6173 will download and execute sequence 0 beginning at segment 0 When the EOS bit is found the Next Sequence Pointer jumps back to the first segment of the sequence and so creates a continuous sinewave output The segment memory will have the following contents A24 address Comments A24_base A24 offset 000 Segment 0 LSByte 4 Least Significant bits EOS FALSE A24_base A24 offset 002 Segment 0 MSWord 16 Most Significant Bits A24_base A24 offset 004 Segment 1 LSByte 4 Least Significant bits EOS FALSE A24_base A24 offset 006 Segment 1 MSWord 16 Most Significant Bits A24 base A24 offset 18Cy Segment 99 LSByte 4 Least Significant bits EOS TRUE A24_base A24_ offset 18Ey Segment 99 MSWord 16 Most Significant Bits Multiple Seq uences This example loads three waveforms into memory The first waveform will be a sinewave indicated as sequence 0 and starting at segment 0 The second waveform will be sinewave indicated by sequence 1 and starting at segment 10 The Third waveform will be a sinewave indicated by sequence 2 and starting at segment number 100 Sequence 0 Next Sequence Pointer is set to 1 sequence
50. ssessscssescssssescssees 23 Using this Chapter iaa isa 23 Al6 and AZ MEVA tez 23 Waveform Memory eses lr a a a lios tati 24 Sequence Memory Registers isnan a ati reiii 25 Segment Memory Pointer sssi eE E Sa iS EKA E aaa S 25 Repeat COM la ier ie aie ton ate ten ae 25 Dwell Colima pao ita 26 Next Sequence Pointer cm sai tend tia 26 General Programming InforMatiON conncnnnccnnnnnonononanonononncnn nono nonncnnnoconncnnnonncnnnrnncnnnncos 26 Sequence Operativo dnd die eee 26 Channel Selection sais A Medea dehy de eet An eae 26 AAA CESS ii A alleges lea ves ee 27 Memory Load RUD usted titi tips 27 EOS and Stop Control Bits ii a o o fe tees dl 27 Trigger Operation scenerna e RR a eet da 28 Contents 7 8 Contents Immediate Jump Operation Om the FIY case can ese AEA e ida E 28 Abort Operation sessed hee acaba ibi 29 Starting the AgllentiEGLTS ia he eds Seared eateries dan 29 EXAMPIES 20 A sae eed Wate See AN 30 Single Sequence 30 Multiple Sequences iaa Ae ees tial ab 30 Appendix A NO CA 33 Appendix B Register Definitions scvciscsccccessccscessscecessccoecesssecsesscecedcetececeseceecedecceesecedcesessdcsessetesssevecsoes 35 Using his APPO ii A eres cael oe A fed ihe RL A ee Bleed eels 35 Addressing the Registers irinaren rinne a A E a A R E 35 The Base Address cios aeaaea sinh E ENE ia cethese leceebeceeve 35 Register Offset ui mart ae ee aap E e EnS anea Taari as 37 Control Register D scrtiptionSs issnin a
51. t 00002 Output 0V EQS TRUE A24_base A24_ offset 00004 A24_base A24_ offset 00006 Output 16 38V EQS TRUE A24_base A24_ offset 00008 46 Calibration A24 base A24 offset OOOOAh Output 16 38V EQS TRUE Appendix C Appendix C 9 Connect the DVM Hi input lead to the Channel 1 Output BNC center conductor and the DVM LO input lead to the Channel 1 Output BNC Shell Set the Clock source and Clock Adjust registers if desired The Clock Adjust can be left at the default of 0 and the internal timebase may be used for calibration Set Channel 1 active in the Card Status Control register base 04h bit 4 Establish channel 1 trigger conditions in the Channel Trigger Register base OE bits 0 through 7 Establish Lo Z output O dB attenuator low pass filter 600 kHz trigger mode and output on in the Channel Status Register base OCh Start the Agilent E6173A The first segment of the first sequence is loaded and output Measure the output with the DVM The DVM should indicate 0 000 Volts out Adjust the Channel 1 Offset adjustment shown in Figure C 1 if the reading is not within 0 001 V Set the On the Fly register to point to sequence 1 10 Measure the output with the DVM The DVM should indicate 16 380 Volts Adjust the Channel 1 Gain adjustment shown in Figure C 1 if the reading is not within 0 005 V 11 Set the On the Fly register to poi
52. tages As such the state of the relay at module power up will be the same as the state when the module was powered down The following procedure to clear the relays is recommended at module power up or reset to guarantee the state of the relays is deterministic 1 Set bits 1 2 3 and 8 of the Channel Status register to 1 2 Clear bits 1 2 3 and 8 of the Channel Status register to 0 3 Program bits 1 2 3 and 8 of the Channel Status register to the desired state base 0C base 0D 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Undefined TP TRL LoZ L R TR2 TR1 TRO ON FIL AT TB 40 Register Definitions TB Time base select bit When set to 0 selects the internal clock 10 MHz When set to 1 selects the external BNC timebase input AT Attenuator select bit When set to 0 selects the O dB attenuator when setto 1 selects the 20 dB attenuator FIL Low pass filter select bit when set to 0 selects the 600 kHz filter When set to 1 selects the 40 kHz filter ON Output on bit When set to 0 the output is turned OFF When set to 1 the output is turned ON TRO TR2 Trigger mode select bits These bits define the source of the channel trigger as described in the following table Appendix B Channel Trigger TR2 TR1 TRO Trigger Source Front Panel input TTL Trigger line VXI backplane Software trigger step to next EOS Software trig
53. ts the wait state between the DAC output Register cycles in single sample clock increments The channel select bit CH in the Status Control Register sets which channel this register affects base 10 base 11 15 14 13 12 11 10 9 8 4 6 5 4 3 2 1 0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 co 42 Register Definitions CO C15 Clock adjust bits This register controls a counter used to modify the duration of the waveform sequencer output segment duration The segment duration is determined by the following formula 20 clock frequency clock_adjust_count clock frequency For example with the internal CLK10 frequency source selected 10 MHz the segment duration vs clock adjust value can be determined Clock Adjust Value Waveform Segment Duration 0 20 10 MHz 0 10 MHz 2 0 us 1 20 10 MHz 1 10 MHz 2 1 us 10 20 10 MHz 10 10 MHz 3 0 us Appendix B On the Fly Register A write to this register will set the next sequence for an on the fly jump When the current sequence reaches the EOS bit and a value is in this register the Agilent E6173A will Jump to the sequence indicated Reading this register returns the current sequence number being output base 12 base 13 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Write X D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DO Read Valid D14 D13 D12 D11 D10 D9 D8 D7 D6
54. tus Control register contains a bit that allows the use of the A24 memory space The register is in A16 memory at location base 04 and bit 15 allows reads or writes to the sequence and segment memory When the bit is set 1 A24 access is allowed A24 space is released by resetting 0 this bit Sequence and segment memory in A24 can be controlled by two sources the VXIbus commander during data downloads and the Agilent E6173 during run time The Channel Status Register contains a bit that defines control of the A24 memory The register is in A16 memory at location base OC and bit 7 transfers memory control When the bit is reset 0 the VXIbus commander is given control When the bit is set 1 the Agilent E6173 is given control The Agilent E6173 sequence flow is controlled by the EOS and Stop Control bits The EOS bit is contained in the segment memory word see page 2 The EOS bit is checked for each segment time as the segment is downloaded from memory The EOS bit is set 1 to indicate the last segment in the current sequence If the EOS bit is set 1 the Agilent E6173 1 Points to a new sequence as defined by the Next Sequence Pointer 2 Loads the new sequence values into memory and a If the Stop Bit is NOT set 0 continues running with new sequence values b If the Stop bit is set 1 pauses The voltage of the last segment Programming the Agilent E6173 27 which contained the EOS bit will be held on the
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