Correct SH7734 User`s Manual:Hardware(HSPI)
Contents
1. 15 0 9 8 i 6 5 4 3 2 il 0 fre Perfor rer ber oorroafronfrocfroapor pea 0 0 0 0 0 0 0 0 0 0 0 H Initial value 0 R W R W R RW RW R W RW RW RW RW RW RW RW RW Initial Bit Bit Name Value Description 31to16 Reserved These bits are always read as an undefined value The write value should always be 0 High speed transfer enable Enables or disables generation of a serial clock signal with the division ratio set in SPCR2 0 The clock setting in SPCR2 is disabled 1 The clock setting in SPCR2 is enabled 14to11 Reserved These bits are always read as an undefined value The write value should always be 0 RENES Page 3 of 4 a AS RENESAS TECHNICAL UPDATE TN SH7 A857A E Date January 17 2013 Initial Bit BitName Value R W Description 10to6 CKHP 4 0 0 R W Serial clock high period The width at high level of the serial bit clock is set to this setting cycles of the SuperHyway clock clks If the width at high level is not set to half of the period setting in CKCYC the duty cycle will greatly diverge from 50 50 5 to 0 CKCYS 5 0 0 Serial clock period The period of the serial bit clock is set to this setting 1 cycles of the SuperHyway clock clks The maximum frequency of the serial bit clock is 20 MHz In accord with the formula for calculation given below the CKCYC value should be no less than 9 The serial bit clock frequency can be computed using the fol2. Date Jan 17 2013 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU MCU Document Category No TN SHT ABS7ALE Rev 1 00 Title Correct SH7734 User s Manual Hardware HSPI eae Technical Notification Lot No SH7734 User s Manual Hardware Rev 1 00 RO1UH0233EJ0100 Applicable Reference Product erie All lots Document There is correction and addition to explanation of 18 Serial Peripheral Interface HSPI in SH7734 User s Manual The correction is shown by shading 1 Correct to 18 1 1 Features in page 1567 lt Wrong gt Independent DMA transfer of data for transmission and received data is possible through two DMA channels lt Correct gt Independent DMA transfer of dat a for trans mission and received data is possible through two DMA channels Transmission and reception in master mode are supported as high speed modes for use with DMA transfer c 2013 Renesas Electronics Corporation All rights reserved Page 1 of 4 stENESAS RENESAS TECHNICAL UPDATE TN SH7 A857A E 2 Correct to Figure 18 1 Block Diagram of HSPI in page 1568 lt Wrong gt Register System control KX HSPiccs HSPI_RX Shift register Internal bus clock oh ee SHwy clock clks Clock division Clock division 2 Pi i olarity selection m SCK generator m D lt HSPI_CLK lt Correct
3. gt j Register System control HSPI_RX DQ Shift register DX HSPI_TX Internal bus clock RESA SHwy clock clks Clock division Clock division 2 i Polarity selection Ji SCK generator Bi I lt HSPI_CLK RENESAS Date January 17 2013 Page 2 of 4 RENESAS TECHNICAL UPDATE TN SH7 A857A E Date January 17 2013 3 Correct to Table 18 2 1 Register Configuration in page 1569 lt Wrong gt Receive buffer register SPRBR H 10 lt Correct gt Receive buffer register R H 10 Control register 2 R W H 14 4 Correct to Table 18 2 2 Register State in Each Operating Mode in page 1570 lt Wrong gt SPRBR Initialized Initialized Retained Retained Retained Initialized lt Correct gt SPRBR Initialized Initialized Retained Retained Retained Initialized SPCR2 Initialized Initialized Retained Retained Retained Initialized 5 Add 18 2 6 Control register 2 to page 1582 as explanation SPCR2 lt Wrong gt This explanation is nothing lt Correct gt 18 2 6 Control Register 2 SPCR2 SPCR2 is a 32 bit readable and writable register that is used to set the clock frequency for data transfer when transfer is to be at a higher rate than that set in the SPCR Transmission and reception in master mode are supported as high speed modes for use with DMA transfer Biti 30 29 28 2 26 29 24 23 22 21 20 19 18 7 16 Initial value R W R R R R R R R R R R R R R R R R Bit 14 13 12 11 1
4. lowing formula SuperHyway Internal bus clock frequency CKCYC 1 Serial bit clock frequency If any bit FBS CLKP IDIV or CLKC of SPCR is changed or any bit of SPCR2 is changed the HSPI is soft reset Register settings and serial bit clock frequencies are indicated below CKCYC 5 0 CKHP 4 0 Serial bit clock frequency Duty D 9 D 5 SuperHyway clock frequency 10 50 D 11 D 6 SuperHyway clock frequency 12 50 D 13 D 7 SuperHyway clock frequency 14 50 D 15 D s SuperHyway clock frequency 16 50 D 17 D 9 SuperHyway clock frequency 18 50 D 63 D 32 SuperHyway clock frequency 64 50 6 Correct 18 3 5 HSPI Software Reset to page 1587 lt Wrong gt The HSPI software reset is generated when the control bits except SPCR the interrupt DMA enable bits and the chip select value bit CSV of SPSCR are modified lt Correct gt The HSPI software reset is generated when the control bits except SPCR SPCR2 the interrupt DMA enable bits and the chip select value bit CSV of SPSCR are modified End of report RENESAS Page 4 of 4 E
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