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LPC11U3x - NXP Semiconductors

1. Symbol Parameter Conditions Min Typ Max Unit Vpp supply voltage core 2 1 8 3 3 3 6 V and external rail Ipp supply current Active mode Vpp 3 3 V Tamb 25 C code while 1 executed from flash system clock 12 MHz BIAIS 2 mA 6 7 8 system clock 50 MHz 4151 6 7 mA 71 81 9 Sleep mode BAB 1 mA Vpp 3 3 V Tamb 25 C 61 71 8 system clock 12 MHz Deep sleep mode Vpp 3 3 V M 300 uA Tamb 25 C Power down mode Vpp 3 3 V 2 uA Tamb 25 C Deep power down mode 0 220 nA Vpp 3 8 V Tamp 25 C Standard port pins RESET li LOW level input current V 0 V on chip pull up resistor 0 5 10 nA disabled liu HIGH level input Vi Vpp on chip pull down resistor 0 5 10 nA current disabled loz OFF state output Vo 0 V Vo Vpp on chip 0 5 10 nA current pull up down resistors disabled Vi input voltage pin configured to provide a digital mjo 5 0 V function Vpp 2 1 8 V 12 Vpp 0V 0 3 6 V Vo output voltage output active 0 Vpp V Vin HIGH level input 0 7Vpp V voltage ViL LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 4 V VoH HIGH level output 2 0 V lt Vpp 3 6 V lou 4 mA Vpp 0 4 V voltage 1 8 V lt Vpp lt 2 0 V lop 3 mA Vpp 04 E V VoL LOW level output 2 0 V lt Vpp x 3 6 V lop 4 mA 0 4 V voltage 1 8 V lt Vpp lt 2 0 V lg
2. Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC JEITA PROJECTION SOT314 2 136E10 MS 026 E 03 02 25 Fig 38 Package outline LQFP64 SOT314 2 ISSUE DATE LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 66 of 77 NXP Semiconductors LPC11U3x 13 Soldering 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of HVQFN33 package see detail X P rm lt 3 quier vi BAERS onda Ree dieelep Uia fe i je O0 it CO a a ERS C ETE DEA E x D SLx Bx Ax solder land Solder paste occupied area Dimensions in mm _ z 0 60 0 30 detail X P Ax Ay Bx By C nSPx nSPy 0 5 5 95 595 425 4 25 0 85 0 27 3 3 Issue date 11 11 20 Fig 39 Reflow soldering for the HVQFN33 5x5 package 002aag766 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 67 of 77 LPC11U3x 32 bit ARM Cortex M0 microcontroller NXP Sem
3. Symbol a Ia EM Reset Type Description e E Se state Cink Lu ul ik S S EEEE PIO1 16 RI A2 48 63 BI PU O PIO1 16 General purpose digital input output pin CT16B0 CAPO RI Ring Indicator input for USART CT16BO CAPO Capture input 0 for 16 bit timer 0 PIO1_17 CT16B0_CAP1 23 Il EPU O PIO1_17 General purpose digital input output pin RXD l CT16B0_CAP1 Capture input 1 for 16 bit timer 0 l RXD Receiver input for USART PIO1 18 CT16B1 CAP1 28 Bl PU I O PIO1 18 General purpose digital input output pin TXD l CT16B1_CAP1 Capture input 1 for 16 bit timer 1 O TXD Transmitter output for USART PIO1_19 DTR SSEL1 1 B1 2 3 B PU O PIO1 19 General purpose digital input output pin O DTR Data Terminal Ready output for USART I O SSEL1 Slave select for SSP1 PIO1_20 DSR SCK1 Hi 13 18 BI PU JO PIO1 20 General purpose digital input output pin l DSR Data Set Ready input for USART I O SCK1 Serial clock for SSP1 PIO1_21 DCD MISO1 G8 26 35 BI PU oO PIO1 21 General purpose digital input output pin l DCD Data Carrier Detect input for USART y o MISO1 Master In Slave Out for SSP1 PIO1 22 RI MOSI A7 38 51 BI l PU I O PIO1 22 General purpose digital input output pin s l RI Ring Indicator input for USART I O MOSI1 Master Out Slave In for SSP1 PIO1 23 CT16B1 MAT1 H4 18 24 BI PU VO PIO1 23
4. Modifications Use of USB CONNECT signal explained in Section 11 1 Suggested USB interface solutions Open drain 1 C bus and RESET pin descriptions clarified See Table 3 LPC11U3X v 2 1 20131230 Product data sheet LPC11U3X v 2 Modifications Add reserved function to pins PIOO 8 MISOO CT16BO MATO R IOH 6 and PIOO 9 MOSIO CT16BO MAT1 R IOH 7 LPC11US3X v 2 20131125 Product data sheet LPC11U3X v 1 1 Modifications Part LPC11U37HFBD64 401 with I O handler added e Additional I O Handler pin functions added in Table 3 Typical range of watchdog oscillator frequency changed to 9 4 kHz to 2 3 MHz See Table 13 e Section 11 8 I O Handler software library applications added Updated Section 11 1 Suggested USB interface solutions for clarity Condition Vpp 0 V added to Parameter V in Table 5 for clarity LPC11U3X v 1 1 20130924 Product data sheet LPC11U3X v 1 Modifications Removed the footnote The peak current is limited to 25 times the corresponding maximum current in Table 4 Table 3 Added 5 V tolerant pad to RESET PIOO 0 table note Table 7 Removed BOD interrupt level 0 Programmable glitch filter is enabled by default See Section 7 7 1 Added Section 11 6 ADC effective input impedance Table 5 Static characteristics added Pin capacitance section Updated Section 11 1 Suggested USB interface solutions
5. Table9 Flash characteristics Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 11 140000 100000 cycles tret retention time powered 10 years unpowered 20 years ter erase time sector or multiple 95 100 105 ms consecutive sectors torog programming time 2 0 95 1 1 05 ms 1 Number of program erase cycles 2 Programming times are given for writing 256 bytes from RAM to the flash Data must be written to the flash in blocks of 256 bytes Table 10 EEPROM characteristics Tamp 40 C to 85 C Vpp 2 7 V to 8 6 V Based on JEDEC NVM qualification Failure rate 10 ppm for parts as specified below Symbol Parameter Conditions Min Typ Max Unit Nendu endurance 100000 1000000 cycles tret retention time powered 100 200 years unpowered 150 300 years tprog programming 64 bytes 2 9 ms time 10 2 External clock Table 11 Dynamic characteristic external clock Tamp 40 C to 85 C Vpp over specified ranges Symbol Parameter Conditions Min Typ l Max Unit fosc oscillator frequency 1 25 MHz Teyi clock cycle time 40 g 1000 ns tcHcx clock HIGH time Teya x 0 4 ns teLcx clock LOW time Teya x 0 4 ns tCLCH clock rise time 5 ns tcHcL clock fall time 5 ns 1 Parameters are valid over
6. FE LPC11U3x Bus 32 bit ARM Cortex M0 microcontroller up to 128 kB flash up to 12 kB SRAM and 4 kB EEPROM USB device USART Rev 2 2 11 March 2014 Product data sheet 1 General description The LPC11U3x are an ARM Cortex MO based low cost 32 bit MCU family designed for 8 16 bit microcontroller applications offering performance low power simple instruction set and memory addressing together with reduced code size compared to existing 8 16 bit architectures The LPC11U3x operate at CPU frequencies of up to 50 MHz Equipped with a highly flexible and configurable full speed USB 2 0 device controller the LPC11U3x brings unparalleled design flexibility and seamless integration to today s demanding connectivity solutions The peripheral complement of the LPC11U3x includes up to 128 kB of flash memory up to 12 kB of SRAM data memory and 4 kB EEPROM one Fast mode Plus I2C bus interface one RS 485 EIA 485 USART with support for synchronous mode and smart card interface two SSP interfaces four general purpose counter timers a 10 bit ADC and up to 54 general purpose I O pins The I O Handler is a software library supported hardware engine that can be used to add performance connectivity and flexibility to system designs It is available on the LPC11U37HFBD64 401 The I O Handler can emulate serial interfaces such as UART 12C and I S with no or very low additional CPU load and can off load the C
7. LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm SOT313 2 detail X DIMENSIONS mm are the original dimensions UNIT Ai A2 Ag bp C 0 25 Note 1 Plastic or metal protrusions of 0 25 mm maximum per side are not included REFERENCES EUROPEAN PROJECTION ISSUE DATE OUTLINE VERSION IEC JEDEC JEITA SOT313 2 136E05 MS 026 E 03 02 25 Fig 37 Package outline LQFP48 SOT313 2 NXP Semiconductors N V 2014 All rights reserved 65 of 77 LPC11U3X All information provided in this document is subject to legal disclaimers Product data sheet Rev 2 2 11 March 2014 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4mm SOT314 2 detail X DIMENSIONS mm are the original dimensions UNIT A1 A2 A3 bp c
8. 2 The term short data sheet is explained in section Definitions 3 The product status of device s described in this document may have changed since this document was published and may differ in case of multiple devices The latest product status information is available on the Internet at URL http www nxp com 17 2 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information Short data sheet A short data sheet is an extract from a full data sheet with the same product type number s and title A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information For detailed and full information see the relevant full data sheet which is available on request via the local NXP Semiconductors sales office In case of any inconsistency or conflict with the short data sheet the full data sheet shall prevail Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer unless NXP Semiconductors and customer have explicitl
9. General purpose digital input output pin SSEL1 O CT16B1_MAT1 Match output 1 for 16 bit timer 1 y o SSEL1 Slave select for SSP1 PIO1 24 CT32BO MATO Ge 21 27 BI PU VO PIO1 24 General purpose digital input output pin O CT32BO MATO Match output 0 for 32 bit timer 0 P1O1_25 CT32B0_MAT1 A11 2 B l PU I O PIO1 25 General purpose digital input output pin O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIO1_26 CT32B0_MAT2 G2 11 14 BII PU I O PIO1 26 General purpose digital input output pin RXD IOH_19 O CT32BO MAT2 Match output 2 for 32 bit timer 0 l RXD Receiver input for USART I O IOH 19 I O Handler input output 19 LPC11U37HFBD64 401 only PIO1_27 CT32B0_MAT3 G1 12 15 BI PU VO PIO1 27 General purpose digital input output pin TXD IOH 20 O CT32B0_MAT3 Match output 3 for 32 bit timer 0 O TXD Transmitter output for USART y o IOH 20 I O Handler input output 20 LPC11U37HFBD64 401 only LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 15 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 3 Pin description Symbol a Ies Mee Reset Type Description E ae state O u L 1 gt u O G am Es qm pan
10. fmain The clock cycle time derived from the SPI bit rate Ty ck is a function of the main clock frequency fmain the SPI peripheral clock divider SSPCLKDIV the SPI SCR parameter specified in the SSPOCRO register and the SPI CPSDVSR parameter specified in the SPI clock prescale register 2 Tamb 40 C to 85 C B Toyo 12 x Tey PcLk 4 Tamb 25 C for normal voltage supply range Vpp 3 3 V LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 50 of 77 NXP Semiconductors LPC11U3x LPC11U3X 32 bit ARM Cortex M0 microcontroller SCK CPOL 0 SCK CPOL 1 MOSI MISO MOSI MISO Toy clk DATA VALID DATA VALID DATA VALID DATA VALID Fig 24 SSP master timing in SPI mode DATA VALID DATA VALID tpH CPHA 1 CPHA 0 002aae829 All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 51 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller Toy clk SCK CPOL 0 SCK CPOL 1 MOSI DATA VALID tva tha CPHA 1 MISO DATA VALID DATA VALID tps ipH MOSI
11. 0 22 0 82 WWDT 0 02 0 06 Main clock selected as clock source for the WDT USB 1 2 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 42 of 77 NXP Semiconductors LPC11U3x LPC11U3X 9 4 Electrical pin characteristics 32 bit ARM Cortex M0 microcontroller 3 6 VoH V 3 2 2 8 2 4 Conditions Vpp 3 3 V on pin PIOO_7 Fig 15 High drive output Typical HIGH level output voltage Voy versus HIGH level 002aae990 T 85 C 25 C 40 C 10 40 50 60 lon mA output current lop 2aaf01 60 002aaf019 loL T 85 C mA 25 C 40 C 40 20 0 0 0 2 0 4 0 6 Conditions Vpp 3 3 V on pins PIOO 4 and PIOO 5 Fig 16 I C bus pins high current sink Typical LOW level output current loj versus LOW level output voltage VoL VoL V All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 NXP Semiconductors LPC11U3x LPC11U3X 32 bit ARM Cortex M0 microcontroller 15 002aae991 lot T 85 C mA 25 C 40 C 10 5
12. 3 mA 0 4 V lou HIGH level output Vou Vpp 0 4 V 4 mA current 2 0 V lt Vpp lt 3 6 V 1 8 V lt Vpp 20 V 3 mA LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 32 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 5 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lo LOW level output VoL 0 4 V 4 mA current 2 0 V lt Vpop lt 3 6 V 1 8 V lt Vpop lt 2 0 V 3 mA lous HIGH level short circuit Voy 0 V 31 45 mA output current lots LOW level short circuit Voi Vpp 13 50 mA output current log pull down current Vi 5V 10 50 150 uA lou pull up current Vi 0V 15 50 85 uA 2 0 V lt Vppx 3 6 V 1 8 V lt Vpp 2 0 V 10 50 85 LA Vpp V lt 5V 0 0 0 pA High drive output pin PIOO 7 lit LOW level input current V 0 V on chip pull up resistor 0 5 10 nA disabled liu HIGH level input Vi Vpp on chip pull down resistor 0 5 10 nA current disabled loz OFF state output Vo 0 V Vo Vpp on chip 0 5 10 nA current pull up down resistors disabled Vi input voltage pin configured to provide a digital 10 5 0 V function Vpp 2 1 8 V
13. 40 C to 85 C Symbol Parameter Conditions Min Max Unit fscL SCL clock Standard mode 0 100 kHz frequency Fast mode 0 400 kHz Fast mode Plus 0 1 MHz tr fall time 415116117 of both SDA and SCL 300 ns signals Standard mode Fast mode 20 0 1 x Cp 300 ns Fast mode Plus 120 ns tLow LOW period of the Standard mode 4 7 us SCL clock Fast mode 1 3 us Fast mode Plus 0 5 us tHIGH HIGH period of the Standard mode 4 0 us SCL clock Fast mode 0 6 us Fast mode Plus 0 26 us tup DAT data hold time S A 8 Standard mode 0 us Fast mode 0 us Fast mode Plus 0 us tsu DAT data set up time 9 10 Standard mode 250 ns Fast mode 100 ns Fast mode Plus 50 ns 1 See the I C bus specification UM10204 for details 2 Parameters are valid over operating temperature range unless otherwise specified 3 tHD DAT is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 4 A device must internally provide a hold time of at least 300 ns for the SDA signal with respect to the Viu min of the SCL signal to bridge the undefined region of the falling edge of SCL 5 Cp total capacitance of one bus line in pF 6 The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pi
14. Dedicated USB PLL available Fully compliant with USB 2 0 specification full speed Supports 10 physical 5 logical endpoints including one control endpoint Single and double buffering supported Each non control endpoint supports bulk interrupt or isochronous endpoint types Supports wake up from Deep sleep mode and Power down mode on USB activity and remote wake up Supports SoftConnect I O Handler LPC11U37HFBD64 401 only The I O Handler is a software library supported hardware engine for emulating serial interfaces and off loading the CPU for processing intensive functions The I O Handler can emulate among others DMA and serial interfaces such as UART 12C or 12S with no or very low additional CPU load The software libraries are available with supporting All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 20 of 77 NXP Semiconductors LPC11U3x 7 11 7 11 1 7 12 7 12 1 LPC11U3X 32 bit ARM Cortex M0 microcontroller application notes from NXP see http www LPCware com LPCXpresso Keil and IAR IDEs are supported I O Handler library code must be executed from the memory area 0x2000 0000 to 0x2000 07FF This memory is not available for other use For application examples see Section 11 8 I O Handler software library applications Each I O Handler li
15. Do nothing on match The timer and prescaler can be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge System tick timer The ARM Cortex MO includes a system tick timer SYSTICK that is intended to generate a dedicated SYSTICK exception at a fixed time interval typically 10 ms Windowed WatchDog Timer WWDT The purpose of the WWDT is to prevent an unresponsive system state If software fails to update the watchdog within a programmable time window the watchdog resets the microcontroller Features nternally resets chip if not periodically reloaded during the programmable time out period Optional windowed operation requires reload to occur between a minimum and maximum time period both programmable Optional warning interrupt can be generated at a programmable time before watchdog time out All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 23 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller Software enables the WWDT but a hardware reset or a watchdog reset interrupt is required to disable the WWDT Incorrect feed sequence causes reset or interrupt if enabled Flag to indicate watchdog r
16. Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cxy1 Cx 1 MHz to 5 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF lt 300 Q 39 pF 39 pF 30 pF lt 300 Q 57 pF 57 pF 5 MHz to 10 MHz 10 pF lt 300 Q 18 pF 18 pF 20 pF 2000 39 pF 39 pF 30 pF 1000 57 pF 57 pF 10 MHz to 15 MHz 10 pF 1600 18 pF 18 pF 20 pF 600 39 pF 39 pF 15 MHz to 20 MHz 10 pF 800 18 pF 18 pF Table 19 Recommended values for Cx1 Cx2 in oscillation mode crystal and external components parameters high frequency mode Fundamental oscillation Crystal load Maximum crystal External load frequency Fosc capacitance C series resistance Rs capacitors Cxy1 Cx2 15 MHz to 20 MHz 10 pF 1800 18 pF 18 pF 20 pF 1000 39 pF 39 pF 20 MHz to 25 MHz 10 pF 1600 18 pF 18 pF 20 pF 800 39 pF 39 pF 11 3 XTAL Printed Circuit Board PCB layout guidelines Follow these guidelines for PCB layout LPC11U3X Connect the crystal on the PCB as close as possible to the oscillator input and output pins of the chip Take care that the load capacitors C4 Cx2 and Cy3 in case of third overtone crystal use have a common ground plane Connect the external components to the ground plain To keep parasitics and the noise coupled in via the PCB as small as possible keep loops as small as possible Choose smaller values of Cy and Cy if parasitic
17. 12 Vpp20V 0 3 6 V Vo output voltage output active 0 Vpp V Vin HIGH level input 0 7Vpp V voltage ViL LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 4 V Vou HIGH level output 2 5 V Vpp 3 6 V lou 20 mA Vpp 0 4 l V voltage 1 8 V lt Vpp lt 2 5 V lop 12 mA Vogt V VoL LOW level output 2 0 V lt Vpp lt 8 6 V loj 4 mA 0 4 V voltage 1 8 V lt Vpp lt 2 0 V lg 3 mA 0 4 V lou HIGH level output Vou Vpp 0 4 V 20 mA current 25V lt Vpop lt 3 6 V 1 8 V lt Vpp lt 2 5 V 12 mA lot LOW level output VoL 0 4 V 4 mA current 2 0 V lt Vpop lt 3 6 V 1 8 V lt Vpp 20 V 3 mA lois LOW level short circuit Voi Vpp 13 50 mA output current lod pull down current Vi 5V 10 50 150 uA LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 33 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 5 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit lou pull up current V 0V 15 50 85 uA 2 0 V lt Vppx 3 6 V 1 8 V lt Vpop lt 2 0 V 10 50 85 LA Vpp lt Vi
18. Table 4 Limiting values Updated Vpp min and max Updated V conditions Table 10 EEPROM characteristics Removed fy and ter the user does not have control over these parameters Changed the tprog from 1 1 ms to 2 9 ms the EEPROM IAP always does an erase and program thus the total program time is ter tprog Changed title of Figure 29 from USB interface on a self powered device to USB interface with soft connect Section 10 7 USB interface added Parameter tgopn and teopre renamed to tgopgp LPC11U3xX v 1 20120420 Product data sheet LPC11U3X All information provided in this document is subject to legal disclaimers Product data sheet NXP Semiconductors N V 2014 All rights reserved Rev 2 2 11 March 2014 73 of 77 NXP Semiconductors LPC11U3x 17 Legal information 32 bit ARM Cortex MO microcontroller 17 1 Data sheet status Document status 1I2 Product status Definition Objective short data sheet Development This document contains data from the objective specification for product development Preliminary short data sheet Qualification This document contains data from the preliminary specification Product short data sheet Production This document contains the product specification 1 Please consult the most recently issued document before initiating or completing a design
19. noted otherwise the system oscillator and PLL are running in both measurements The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 41 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 8 Power consumption for individual analog and digital blocks Peripheral Typical supply currentin Notes mA n a 12 MHz 48 MHz IRC 0 27 System oscillator running PLL off independent of main clock frequency System oscillator 0 22 IRC running PLL off independent of main clock at 12 MHz frequency Watchdog 0 004 System oscillator running PLL off independent oscillator at of main clock frequency 500 kHz 2 BOD 0 051 Independent of main clock frequency Main PLL 0 21 ADC 0 08 0 29 CLKOUT 0 12 0 47 Main clock divided by 4 in the CLKOUTDIV register CT16BO 0 02 0 06 CT16B1 0 02 0 06 CT32BO 0 02 0 07 CT32B1 0 02 0 06 GPIO 0 23 0 88 GPIO pins configured as outputs and set to LOW Direction and pin state are maintained if the GPIO is disabled in the SYSAHBCLKCFG register IOCONFIG 0 03 0 10 12C 0 04 0 13 ROM 0 04 0 15 SPIO 0 12 0 45 SPI1 0 12 0 45 UART
20. 0 0 0 2 0 4 0 6 VoL V Conditions Vpp 3 3 V standard port pins and PIOO 7 Fig 17 Typical LOW level output current loj versus LOW level output voltage VoL 002aae992 3 6 24 loH mA Conditions Vpp 3 3 V standard port pins Fig 18 Typical HIGH level output voltage Voy versus HIGH level output source current lon All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 44 of 77 NXP Semiconductors 002aae988 Vi V Conditions Vpp 3 3 V standard port pins Fig 19 Typical pull up current ly versus input voltage Vj 80 002aae989 id T 85 C p 25 C uA ee 60 40 20 0 0 1 2 3 4 5 Vi V Conditions Vpp 3 3 V standard port pins Fig 20 Typical pull down current lpa versus input voltage Vi LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 LPC11U3x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors LPC11U3x 10 Dynamic characteristics 32 bit ARM Cortex M0 microcontroller 10 1 Flash memory
21. 2 11 March 2014 7 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller PIO1 25 CT32B0 MAT1 PIO1 19 DTR SSEL1 RESET PIOO 0 PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE Vss XTALIN XTALOUT Vpp PIOO 20 CT16B1 CAPO PIOO 2 SSELO CT16BO CAPO PIO1 26 CT32B0 MAT2 RXD PIO1 27 CT32B0 MAT3 TXD 48 PIO1 16 RI CT16BO CAPO 47 PIOO 19 TXD CT32BO MAT1 46 PIOO 18 RXD CT32BO0 MATO 45 PIOO 17 RTS CT32B0 CAPO SCLK 43 PIO1 15 DCD CT16BO MAT2 SCK1 40 PIOO 16 AD5 CT32B1 MAT3 WAKEUP 42 PIOO 23 AD7 44 Vpp 41 Vss LPC11U34FBD48 311 LPC11U34FBD48 421 LPC11U35FBD48 401 LPC11U36FBD48 401 LPC11U37FBD48 401 39 SWDIO PIOO 15 AD4 CT32B1 MAT2 38 PIO1 22 RI MOSI1 37 PIO1 14 DSR CT16BO MAT1 RXD PIO1 13 DTR CT16B0 MATO TXD TRST PIOO 14 AD3 CT32B1 MAT1 TDO PIOO 13 AD2 CT32B1 MATO TMS PIOO 12 AD1 CT32B1 CAPO TDI PIOO 11 ADO CT32B0 MAT3 PIO1 29 SCKO CT32BO CAP1 PIOO 22 AD6 CT16B1 MAT1 MISO1 SWCLK PIOO 10 SCKO0 CT16BO MAT2 PIOO 9 MOSIO CT16BO MAT1 PIOO 8 MISOO CT16B0 MATO PIO1 21 DCD MISO1 PIO1 31 002aag811 PIO1 24 CT32BO MATO 21 USB DP 20 PIOO 6 USB CONNECT SCKO 22 PIOO 4 SCL 15 PIOO 5 SDA 16 PIOO 21 CT16B1 MATO MOSIM 17 USB DM 19 PIO1 28 CT32BO CAPO SCLK 24 PIOO 7 CTS 23 PIO1 23 CT16B1 MAT1 SSEL1 18 PIOO 3 USB VBUS 14 PIO1 20 DSR SCK4 13 Fig 4 Pin configuration LQFP48 LPC11U3X All information provided in t
22. 4 bit to 16 bit of data flowing from the master to the slave and from the slave to the master In practice often only one of these data flows carries meaningful data Features Maximum SSP speed of 25 Mbit s master or 4 17 Mbit s slave in SSP mode Compatible with Motorola SPI Serial Peripheral Interface 4 wire Texas Instruments SSI Serial Synchronous Interface and National Semiconductor Microwire buses Synchronous serial communication Master or slave operation All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 21 of 77 NXP Semiconductors LPC11U3x 7 13 7 13 1 7 14 7 14 1 LPC11U3X 32 bit ARM Cortex M0 microcontroller e 8 frame FIFOs for both transmit and receive 4 bit to 16 bit frame I2C bus serial I O controller The LPC11U3x contain one I C bus controller The I C bus is bidirectional for inter IC control using only two wires a Serial CLock line SCL and a Serial DAta line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addressed The I C bus is a mult
23. 40 15 10 35 60 85 temperature C Conditions BOD disabled all oscillators and analog blocks turned off in the PDSLEEPCFG register USB DP and USB DM pulled LOW externally Fig 12 Typical supply current versus temperature in Deep sleep mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 40 of 77 NXP Semiconductors LPC11U3x LPC11U3X 32 bit ARM Cortex M0 microcontroller 002aag746 20 i IDD Vpp 3 6 V 3 3 V pA Vpp 2 0 V Vpp 1 8 V 15 40 15 10 35 60 85 temperature C Conditions BOD disabled all oscillators and analog blocks turned off in the PDSLEEPCFG register USB_DP and USB_DM pulled LOW externally Fig 13 Typical supply current versus temperature in Power down mode 002aag747 0 8 g 40 15 10 35 60 85 temperature C Fig 14 Typical supply current versus temperature in Deep power down mode 9 3 Peripheral power consumption The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and PDRUNCFG for analog blocks registers All other blocks are disabled in both registers and no code is executed Measured on a typical sample at Tamp 25 C Unless
24. AAA AAA A OO ZZ ZZ ZA ZZ ZZ ZA ZZ ZZ ZA ZA EZ Hy Gy Sooo ZEE By Ay ZA ZZ ZZ ZA Zh Z ZZ ZZ mA a i EO aaa OOo D2 8x d L D1 E Bx gt a Ax SOT313 2 sot313 2 fr LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 70 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of LQFP64 package SOT314 2 a Hx Gx P2 je gt P1 Ad mW ia AAA A g A i i i i E IZ E Z MZ A L A A AA i J i E L EZZ ZZA E EE ZZA ZA 1 I ZA ZZA 1 ZZ ZA Sooo Hy Gy ZZ ZA By Ay Lu Za ZA ES I escas LZ LZ d Er uices cm ZZ KZA Mas TL Es 7777 EZZA ZZ EET 1 i i UE CAAA A A A A A A C UA I A VA 1 UA 1 iA Fog I Wage eo eee L D2 8x L D1 E Bx gt lt Ax gt Generic footprint pattern Refer to the package outline drawing for actual layout A solder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 13 300 13 300 10 300 10 300 1 500 0 280 0 400 10 500 10 500 13 550 13 550 E Fig 43 Reflow soldering for the LQFP64 package LPC11U3X All information provided in this document is subject to le
25. CT16B0_CAP 1 0 2 CT16B1 MAT 1 0 SSPO ae 16 bit COUNTER TIMER 1 lt CT16B1_CAP 1 0 2 CUM sean counrenmmeno C 32 bit COUNTER TIMER 0 CT32B0_CAP 1 0 2 l GT32B1_MATIS 0 32 bit COUNTER TIMER 1 econ DI CT32B1 CAP 1 0 2 C SYSTEM CONTROL WINDOWED WATCHDOG TIMER PMU GPIO pins GPIO INTERRUPTS GPIO pins GPIO GROUPO INTERRUPTS lt GPIO pins GPIO GROUP1 INTERRUPTS NS 002aag345 1 Not available on HVQFN33 packages LQFP64 packages only CT32B1_CAP1 available in TFBGA48 LQFP64 packages only 3 LPC11U37HFBD64 401 only Fig 1 Block diagram CLKOUT USB_DP USB_DM USB_VBUS USB_FTOGGLE USB_CONNECT AD 7 0 SCL SDA SCKO SSELO MISOO MOSIO SCK1 SSEL1 MISO1 MOSI1 2 CT16BO CAP1 CT16B1 CAP 1 available on LQFP64 packages only CT32BO CAP1 available on TFBGA48 LQFP48 and LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 5 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 6 Pinning information 6 1 Pinning E N m x v k O o xz EH g 6 S FEE t ES tig lt x aa 229 2 25 ooo o m tc m ea ow Nn QA NO PPP E BS ogo S Ow O OJO oi E EIE 8588 E cic Q L L N O yA EN FENT 2 ee28 aAa 2 L A terminal 1 0o00a0o0o0z n 00 5480860 inde
26. Figure 28 is used configure the PIOO_3 USB_VBUS pin for GPIO PIOO 3 in the IOCON block to ensure that the USB CONNECT signal can still be controlled by software For details on the soft connect feature see the LPC11USx user manual Ref 1 Remark When a self powered circuit is used without connecting VBUS configure the PIOO S USB VBUS pin for GPIO PIOO 3 and provide software that can detect the host presence through some other mechanism before enabling USB CONNECT and the soft connect feature Enabling the soft connect without host presence will lead to USB compliance failure All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 55 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 11 2 XTAL input LPC11U3X The input voltage to the on chip oscillators is limited to 1 8 V If the oscillator is driven by a clock in slave mode it is recommended that the input be coupled through a capacitor with Ci 100 pF To limit the input voltage to the specified range choose an additional capacitor to ground Cg which attenuates the input voltage by a factor C C Cg In slave mode a minimum of 200 mV RMS is needed LPC1xxx Cg 9 pF T 002aae788 Fig 29 Slave mode operation of the on chip oscillator In slave mode couple the input clock signal with a capacito
27. Sls is s a n0 ja ja PIO1_28 CT32BO_CAPO H7 24 31 BII PU VO PIO1 28 General purpose digital input output pin SCLK l CT32B0 CAPO Capture input 0 for 32 bit timer 0 I O SCLK Serial clock input output for USART in synchronous mode PIO1_29 SCK0 D7 31 41 B EPU VO PIO1 29 General purpose digital input output pin CT32B0_CAP1 VO SCK0 Serial clock for SSPO l CT32B0_CAP1 Capture input 1 for 32 bit timer O PIO1_31 25 l B l PU I O PIO1_31 General purpose digital input output pin USB_DM 13 G5 19 25 Vlr USB DM USB bidirectional D line USB DP 14 H5 20 26 VIF USB DP USB bidirectional D line XTALIN 4 D1 6 8g B Input to the oscillator circuit and internal clock generator circuits Input voltage must not exceed 1 8 V XTALOUT 5 E1 7 9 B Output from the oscillator amplifier Vpp 6 B4 8 10 Supply voltage to the internal regulator the external 29 E2 44 33 rail and the ADC Also used as the ADC reference 48 voltage 58 Vss 33 B5 5 7 Ground D2 41 154 1 Pin state at reset for default function Input O Output PU internal pull up enabled IA inactive no pull up down enabled F floating If the pins are not used tie floating pins to ground or power to minimize power consumption 2 5Vtolerant pad RESET functionality is not available in Deep power down mode Use the WAKEUP pin to reset the chip and wake up from Deep power down mode An exter
28. cycle The PLL is turned off and bypassed following a chip reset Software can enable the PLL later The program must configure and activate the PLL wait for the PLL to lock and then connect to the PLL as a clock source The PLL settling time is 100 ps Clock output The LPC11U3x feature a clock output function that routes the IRC oscillator the system oscillator the watchdog oscillator or the main clock to an output pin Wake up process The LPC11U3x begin operation by using the 12 MHz IRC oscillator as the clock source at power up and when awakened from Deep power down mode This mechanism allows chip operation to resume quickly If the application uses the main oscillator or the PLL software must enable these components and wait for them to stabilize Only then can the system use the PLL and main oscillator as a clock source Power control The LPC11U3x support various power control features There are four special modes of processor power reduction Sleep mode Deep sleep mode Power down mode and Deep power down mode The CPU clock rate can also be controlled as needed by changing clock sources reconfiguring PLL values and or altering the CPU clock divider value This power control mechanism allows a trade off of power versus processing speed based on application requirements In addition a register is provided for shutting down the clocks to individual on chip peripherals This register allows fine tuning of power All informat
29. efficient processing of late arriving interrupts 7 6 1 Features Controls system exceptions and peripheral interrupts n the LPC11U3x the NVIC supports 24 vectored interrupts LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 18 of 77 NXP Semiconductors LPC11U3x 7 6 2 T LPC11U3X 7 7 7 1 7 8 32 bit ARM Cortex M0 microcontroller Four programmable interrupt priority levels with hardware priority level masking Software interrupt generation Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but can have several interrupt flags Individual interrupt flags can also represent more than one interrupt Source IOCON block The IOCON block allows selected pins of the microcontroller to have more than one function Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals Connect peripherals to the appropriate pins before activating the peripheral and before enabling any related interrupt Activity of any enabled peripheral function that is not mapped to a related pin is treated as undefined Features Programmable pull up pull down or repeater mode All GPIO pins except PIOO 4 and PIOO 5 are pulled up to 3 3 V Vpp 3 3 V if their pull up resistor is enabled P
30. for EEPROM USB API Power profiles for configuring power consumption and PLL settings 32 bit integer division routines Memory map The LPC11U3x incorporates several distinct memory regions shown in the following figures Figure 6 shows the overall map of the entire address space from the user program viewpoint following reset The interrupt vector area supports address remapping The AHB Advanced High performance Bus peripheral area is 2 MB in size and is divided to allow for up to 128 peripherals The APB Advanced Peripheral Bus peripheral area is 512 kB in size and is divided to allow for up to 32 peripherals Each peripheral of either type is allocated 16 kB of space This addressing scheme allows simplifying the address decoding for each peripheral All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 17 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller LPC11U3x 4GB OxFFFF FFFF p ge B MAMMA reserved OxE010 0000 rivate peripheral bus reserved z 0x5000 4000 0x5000 0000 APB peripherals gt reserved z z 0x4008 0000 0x4008 4000 25 31 d USB S 0x4006 4000 0x4008 0000 GPIO GROUP1 INT APB peripherals Macc M DEI de i 0x4006 0000 1GB 0x4000 0000 GPIO GROUPO INT 4 4005 C000 reserved ES SSP 0x4005 8000 0x2000 4800 i
31. information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 16 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 7 Functional description LPC11U3X 7 1 7 2 7 3 7 4 7 5 On chip flash programming memory The LPC11U3x contain up to 128 kB on chip flash program memory The flash can be programmed using In System Programming ISP or In Application Programming IAP via the on chip boot loader software The flash memory is divided into 4 kB sectors with each sector consisting of 16 pages Individual pages can be erased using the IAP erase page command EEPROM The LPC11U3x contain 4 kB of on chip byte erasable and byte programmable EEPROM data memory The EEPROM can be programmed using In Application Programming IAP via the on chip boot loader software SRAM The LPC11U3x contain a total of 8 kB 10 kB or 12 kB on chip static RAM memory On the LPC11U37HFBD64 401 the 2 kB SRAM1 region at location 0x2000 0000 to 0x2000 07FFF is used for the I O Handler software library Do not use this memory location for data or other user code On chip ROM The on chip ROM contains the boot loader and the following Application Programming Interfaces APIs e In System Programming ISP and In Application Programming IAP support for flash including IAP erase page command AP support
32. lt 5V 0 0 0 uA I C bus pins PIOO 4 and PIOO 5 Vin HIGH level input 0 7Vpp V voltage Vit LOW level input voltage 0 3Vpp V Vhys hysteresis voltage 0 05Vpp V lo LOW level output VoL 0 4 V I2C bus pins configured 3 5 mA current as standard mode pins 2 0 V lt Vpp lt 3 6 V 1 8 V lt Vpp 2 0 V 3 zi zi lo LOW level output VoL 0 4 V I2C bus pins configured 20 mA current as Fast mode Plus pins 2 0 V lt Vpp lt 3 6 V 1 8 V lt Vpp lt 2 0 V 16 a g lu input leakage current Vi Vpp 14 2 4 uA Vi 5V E 10 22 uA Oscillator pins Vi xtal crystal input voltage 0 5 1 8 1 95 V Vowtal crystal output voltage 0 5 1 8 1 95 V USB pins loz OFF state output 0OV Vi 3 3V f 10 uA current VBus bus supply voltage 2 5 25 V Vpi differential input D D 2 0 2 V sensitivity voltage Vom differential common includes Vp range 2 0 8 2 5 V mode voltage range Vi rsse single ended receiver 2 0 8 2 0 V switching threshold voltage VoL LOW level output for low full speed 2 0 18 V voltage R of 1 5 KQ to 3 6 V Vou HIGH level output driven for low full speed 2 2 8 3 5 V voltage R of 15 kQ to GND Cirans transceiver capacitance pin to GND f 20 pF Zpnv driver output with 33 Q series resistor steady state 5II2 36 E 44 1 Q impedance for driver drive which is not high speed capable LPC11U3X All information provided in this document is sub
33. of instructions is suspended until either a reset or interrupt occurs Peripheral functions continue operation during Sleep mode and can generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself by memory systems and related controllers and by internal buses Deep sleep mode In Deep sleep mode the LPC11U3x is in Sleep mode and all peripheral clocks and all clock sources are off except for the IRC The IRC output is disabled unless the IRC is selected as input to the watchdog timer In addition all analog blocks are shut down and the flash is in stand by mode In Deep sleep mode the application can keep the watchdog oscillator and the BOD circuit running for self timed wake up and BOD protection The LPC11U3x can wake up from Deep sleep mode via reset selected GPIO pins a watchdog timer interrupt or an interrupt generating USB port activity Deep sleep mode saves power and allows for short wake up times Power down mode In Power down mode the LPC11U3x is in Sleep mode and all peripheral clocks and all clock sources are off except for watchdog oscillator if selected In addition all analog blocks and the flash are shut down In Power down mode the application can keep the BOD circuit running for BOD protection The LPC11U3x can wake up from Power down mode via reset selected GPIO pins a watchdog timer interrupt or an interrupt generating USB port activity Al
34. reliability of the device Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale as published at http www nxp com profile terms unless otherwise agreed in a valid written individual agreement In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant conveyance or implication of any license under any copyrights patents or other industrial or intellectual property rights NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 74 of 77 NXP Semiconductors LPC11U3x Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Non automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified the product is not suitable for automotive use It is neither qualified nor tested in accordance with automot
35. source EOP width tFEOPT differential data to ART SEO EOP skew ias n T t STPERIOD fFDEOP T receiver EOP width tgopg aaa 009330 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 53 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 11 Application information 11 1 Suggested USB interface solutions The USB device can be connected to the USB as self powered device see Figure 27 or bus powered device see Figure 28 On the LPC11U3x the PIOO 3 USB VBUS pin is 5 V tolerant only when Vpp is applied and at operating voltage level Therefore if the USB VBUS function is connected to the USB connector and the device is self powered the USB VBUS pin must be protected for situations when Vpp 0 V If Vpp is always greater than 0 V while VBUS 5 V the USB VBUS pin can be connected directly to the VBUS pin on the USB connector For systems where Vpp can be 0 V and VBUS is directly applied to the VBUS pin precautions must be taken to reduce the voltage to below 3 6 V which is the maximum allowable voltage on the USB VBUS pin in this case One method is to use a voltage divider to connect the USB VBUS pin to the VBUS on the USB connector The voltage divider ratio should be such that the USB VBUS pin will be greater than 0 7Vpp to indica
36. the Standard mode I C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time 0 SDA dis tHD DAT SCL S 1 f eee Sec es 1 SCL 002aaf425 Fig 23 I C bus pins clock timing LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 49 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 10 6 SSP interface Table 16 Dynamic characteristics of SPI pins in SPI mode Symbol Parameter Conditions Min Typ Max Unit SPI master in SPI mode Toy clk clock cycle time full duplex mode Hl 50 ns when only transmitting H 40 ns tps data set up time in SPI mode 2 15 ns 2 4 V lt Vpp x 3 6 V 20VxVpp 24V B 20 ns 18V lt Vpp lt 20V Bl 24 a ns tDH data hold time in SPI mode 2 0 ns tv data output valid time in SPI mode B 10 ns tha data output hold time in SPI mode 2 jo E ns SPI slave in SPI mode ToyPcu POLK cycle time 20 ns tps data set up time in SPI mode BIA j0 ns tDH data hold time in SPI mode BIA 3x Teyporky 4 l ns twa data output valid time in SPI mode BIA 3 x Tey PeLK 11 ns tha data output hold time in SPI mode BIA 2 x Tey PeLk 5 ns 1 Toy ei SSPCLKDIV x 1 SCR x CPSDVSR
37. 20 21 reserved 2 kB USB RAM LPC11U34 421 ATI 0x4004 C000 LPC11U35 401 501 19 interrupts LPC11U36 401 501 eT 0x4004 C000 LPC11U37 401 501 18 y 0x4004 8000 LPC11U37H 401 0x2000 4000 17 IOCON idoia do0 reserved i 16 SSPO 0x2000 0300 15 flash EEPROM controll K 2 kB SRAM1 LPC11U35 501 flas controller 04003 C000 LPC11U37 501 14 ERU I O Handler code area wae 0x4003 8000 0 5 GB peep Ie R EGE 0x2000 0000 10 13 reserved gt reserved ES Ox1FFF 4000 2 0x4002 8000 16 kB boot ROM r TESSIE 0x4002 4000 X reserved 0x4002 0000 gt reserved E ADC 0x4001 C000 0x1000 2000 8kB SRAMO LPC11U3x 0x1000 0000 32 bit counter timer 1 0x4001 8000 32 bit counter timer 0 0x4001 4000 reserved 16 bit counter timer 1 0x4001 0000 16 bit counter timer O 0x4000 C000 USART SMART CARD 0x4000 8000 0x0002 0000 128 kB on chip flash LPC11U37 7H 0x0001 8000 chi WWDT 96 kB on chip flash LPC11U36 C054 0000 d 0x4000 4000 64 kB on chip flash LPC11U35 sag cago L COS 0x4000 0000 xt 9 8 7 6 5 4 3 2 eo 0x0000 00CO 48 kB on chip flash LPC11U34 421 0x0000 A000 active interrupt vectors 0x0000 0000 0 GB 40 kB on chip flash LPC11U34 311 bo 9999 0000 Fig 6 LPC11U3x memory map 002aag813 7 6 Nested Vectored Interrupt Controller NVIC The Nested Vectored Interrupt Controller NVIC is part of the Cortex MO The tight coupling to the CPU allows for low interrupt latency and
38. 3 6 V Temperature range 40 C to 85 C Available as LQFP64 LQFP48 TFBGA48 and HVQFN33 packages Consumer peripherals W Handheld scanners Medical W USB audio devices Industrial control 4 Ordering information Table 1 Ordering information Type number Package Name Description Version LPC11U34FHN33 311 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm LPC11U34FBD48 311 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U34FHN33 421 HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm LPC11U34FBD48 421 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U35FHN33 401 HVQFNS3S3 plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 7 x 7 x 0 85 mm LPC11U35FBD48 401 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U35FBD64 401 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC11U35FHI33 501 HVQFN33 _ plastic thermal enhanced very thin quad flat package no leads 33 n a terminals body 5 x 5 x 0 85 mm LPC11U35FET48 501 TFBGA48 plastic thin fine pitch ball grid array package 48 balls body 4 5 x 4 5 SOT1155 2 x 0 7 mm LPC11U36FBD48 401 LQFP48 pl
39. 7 12 1 Features 2 ilssc eed Ebr Ene ERR 21 7 13 I2C bus serial I O controller 22 7 13 1 Features 2s iau ERROR EIER GE 22 7 14 10 biEADG i obe iet RR IRR 22 7 14 1 FeatUtes 2 2 ses siue p Ex E EE REA 22 7 15 General purpose external event counter timers lille 23 7 15 1 Features coos ee she VERDI LELIO SEL 23 7 16 System tick timer 0000 00s 23 7 17 Windowed WatchDog Timer WWDT 2 I 23 7 17 1 Eeatures 522 bebe bres Ebe Es E Gabbe 23 7 18 Clocking and power control 24 7 18 1 Integrated oscillators Lus 24 7 18 1 1 Internal RC oscillator 25 7 18 1 2 System oscillator lulu 26 LPC11U3X All information provided in this document is subject to legal disclaimers 7 18 1 3 7 18 2 7 18 3 7 18 4 7 18 5 7 18 5 1 7 18 5 2 7 18 5 3 7 18 5 4 7 18 5 5 7 18 6 7 18 6 1 7 18 6 2 7 18 6 3 7 18 6 4 7 18 6 5 7 18 6 6 7 19 8 9 9 1 9 2 9 3 9 4 10 10 1 10 2 10 3 10 4 10 5 10 6 10 7 11 11 1 11 2 11 3 11 4 11 5 11 6 11 7 11 8 11 8 1 11 8 2 11 8 3 11 8 4 Watchdog oscillator 26 System PLL and USB PLL 26 Clock output 02000 2 eee 26 Wake up process 2000055 26 Power control a an ennaa anaana 26 Power profiles 00 000e0 eee 27 Sleep mode lslsessesesss 27 Deep sleep mode islsuussss 27 Power
40. 8 26 LPC11U35FBD48 401 64 4 8 2 10 no 1 1 2 1 8 40 LPC11U35FBD64 401 64 4 8 2 10 no 1 1 2 1 8 54 LPC11U35FHI33 501 64 4 8 2 201 12 no 1 1 2 1 8 26 LPC11U35FET48 501 64 4 8 2 201 12 no 1 1 2 1 8 40 LPC11U36FBD48 401 96 4 8 2 10 no 1 1 2 1 8 40 LPC11U36FBD64 401 96 4 8 2 10 no 1 1 2 1 8 54 LPC11U37FBD48 401 128 4 8 2 10 no 1 1 2 1 8 40 LPC11U37HFBD64 401 128 4 8 2 212 10 yes 1 1 2 1 8 54 LPC11U37FBD64 501 128 4 8 2 201 12 no 1 1 2 1 8 54 1 For general purpose use 2 For I O Handler use only LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 4 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller 5 Block diagram SU XTALIN XTALOUT RESET UJ LPC11U3x SYSTEM OSCILLATOR TEST DEBUG CLOCK INTERFACE IRC WDO GENERATION POWER CONTROL SYSTEM FUNCTIONS CORTEX MO Por PLLO usBPLL EEPROM ET 4 kB EA FLASH SRAM ROM y 40 48 64 96 128 kB 8 10 12 kB 16 kB HIGHRSBEED slave mu slave O slave Q master GPIO ports 0 1 cpio K use vevice slave CONTROLLER AHB LITE BUS Vo master IOH_ 20 0 HANDLER Ga slave XZ APB BRIDGE RXD RIAL USART TT DCD DSR RI K 10 bit ADC CTS RTS DTR SMARTCARD INTERFACE SCLK 2C CT16BO MAT 2 0 C FC BUS 16 bit COUNTER TIMERO
41. C JEITA projection gt co SES 09 03 23 NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 63 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller TFBGA48 plastic thin fine pitch ball grid array package 48 balls body 4 5 x 4 5 x 0 7 mm SOT1155 2 D gt gt B A E ball A1 index area A2 E A I A1 detail X Y MO9v C A B 9 wc H i i e G F E t 6 eo D 12e C B A Y ball A1 1 2 3 4 5 6 7 8 solder mask open area index area not for solder ball 0 5mm L fi J L L Dimensions scale Unit A A4 A2 b D E e ey e2 v w y y1 max 1 10 0 30 0 80 0 35 46 4 6 mm nom 0 95 0 25 0 70 0 30 45 45 05 35 3 5 0 15 0 05 0 08 0 1 min 0 85 0 20 0 65 0 25 44 44 sot1155 2_po i References Outline ba Furopean Issue date version IEC JEDEC JEITA projection 43 06 47 SOT1155 2 e E Pp qid Fig 36 Package outline TFBGA48 SOT1155 2 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 64 of 77 LPC11U3x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors
42. Cortex MO microcontroller Table 3 Pin description Symbol a IS Reset Type Description Z T state Cin u LL t gt in O G I e l c c c a2 amp a amp PIO1_3 CT32B1_MAT3 l 50 B i PU I O PIO1_3 General purpose digital input output pin IOH_13 O CT32B1_MAT3 Match output 3 for 32 bit timer 1 I O IOH 13 I O Handler input output 13 LPC11U37HFBD64 401 only PIO1 4 CT32B1 CAPO 16 Bl PU YO PIO1 4 General purpose digital input output pin IOH 14 l CT32B1 CAPO Capture input 0 for 32 bit timer 1 VO IOH 14 I O Handler input output 14 LPC11U37HFBD64 401 only PIO1 5 CT32B1 CAP1 H8 32 DI EPU VO PIO1 5 General purpose digital input output pin IOH 15 CT32B1 CAP1 Capture input 1 for 32 bit timer 1 VO IOH 15 I O Handler input output 15 LPC11U37HFBD64 401 only PIO1 6 IOH 16 l 64 DI EPU I O PIO1_6 General purpose digital input output pin VO IOH 16 I O Handler input output 16 LPC11U37HFBD64 401 only PIO1 7 IOH 17 e B PU VO PIO1 7 General purpose digital input output pin VO IOH 17 I O Handler input output 17 LPC11U37HFBD64 401 only PIO1 8 IOH 18 39 BII PU VO PIO1 8 General purpose digital input output pin VO IOH 18 I O Handler input output 18 LPC11U37HFBD64 401 only PIO1_9 55 BI i PU JO PIO1_9 General purpos
43. DATA VALID twa tna CPHA 0 MISO DATA VALID DATA VALID 002aae830 Fig 25 SSP slave timing in SPI mode LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 52 of 77 LPC11U3x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors 10 7 USB interface Table 17 Dynamic characteristics USB pins full speed C 50 pF Rou 1 5 kQ on D to Vpp 3 0 V lt Vpp lt 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 to 90 8 5 13 8 ns tr fall time 10 to 90 96 7 7 13 7 ns tFRFM differential rise and fall time ty t 109 matching Vcns output signal crossover voltage 1 3 2 0 V tFEOPT source SEO interval of EOP see Figure 26 160 175 ns tFpEoP source jitter for differential transition see Figure 26 2 5 ns to SEO transition tJR1 receiver jitter to next transition 18 5 18 5 ns tJR2 receiver jitter for paired transitions 10 to 90 96 9 9 ns tEopR EOP width at receiver must accept as 82 ns EOP see Figure 26 1 Characterized but not implemented as production test Guaranteed by design differential data lines TPERIOD crossover point ae crossover point extended Fig 26 Differential data to EOP transition skew and EOP width
44. PU by performing processing intensive functions like DMA transfers in hardware Software libraries for multiple I O Handler applications are available on http www LPCware com For additional documentation related to the LPC11U3x parts see Section 15 References 2 Features and benefits E System ARM Cortex MO processor running at frequencies of up to 50 MHz ARM Cortex MO built in Nested Vectored Interrupt Controller NVIC Non Maskable Interrupt NMI input selectable from several input sources System tick timer B Memory Up to 128 kB on chip flash program memory with sector 4 kB and page erase 256 byte access 4 kB on chip EEPROM data memory byte erasable and byte programmable on chip API support Up to 12 kB SRAM data memory NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 16 kB boot ROM In System Programming ISP and In Application Programming IAP via on chip bootloader software ROM based USB drivers Flash updates via USB supported ROM based 32 bit integer division routines B Debug options Standard JTAG Joint Test Action Group test interface for BSDL Boundary Scan Description Language Serial Wire Debug BW Digital peripherals Up to 54 General Purpose I O GPIO pins with configurable pull up pull down resistors repeater mode and open drain mode Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sour
45. RT PERIPHERAL CLOCK DIVIDER UART MAINCLKSEL main clock select SYSTEM PLL CPU system control PMU SYSTEM CLOCK System clock n DIVIDER Da memories SSP1 PERIPHERAL CLOCK DIVIDER SSP1 IRC oscillator system oscillator SYSPLLCLKSEL system PLL clock select system oscillator USB PLL USB 48 MHz CLOCK USB USBPLLCLKSEL USB clock select USBUEN USB clock update enable IRC oscillator System oscillator CLKOUT PIN CLOCK CLKOUT pin watchdog oscillator DIVIDER P CLKOUTUEN CLKOUT update enable IRC oscillator WDT watchdog oscillator WDCLKSEL WDT clock select 002aaf892 Fig 7 LPC11U3x clocking generation block diagram 7 18 1 1 Internal RC oscillator The IRC can be used as the clock source for the WDT and or as the clock that drives the system PLL and then the CPU The nominal IRC frequency is 12 MHz Upon power up any chip reset or wake up from Deep power down mode the LPC11U3x use the IRC as the clock source Software can later switch to one of the other available clock sources LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 25 of 77 NXP Semiconductors LPC11U3x 7 18 1 2 7 18 1 3 7 18 2 7 18 3 7 18 4 7 18 5 LPC11U3X 32 bit ARM Cortex M0 microcontroller System oscillator The system oscillator can
46. astic low profile quad flat package 48 leads body 7 x 7 x 1 4 mm SOT313 2 LPC11U36FBD64 401 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 3 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 1 Ordering information continued Type number Package Name Description Version LPC11U37FBD48 401 LQFP48 plastic low profile quad flat package 48 leads body 7 x 7 x 1 4mm _ SOT313 2 LPC11U37HFBD64 401 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 LPC11U37FBD64 501 LQFP64 plastic low profile quad flat package 64 leads body 10 x 10 x 1 4 mm SOT314 2 4 1 Ordering options Table2 Ordering options Type number m m d r m Z E A E m z E gs X 2 3 z Zos 2 o e q rs fe Lr o X o D a lt q m 4 Sa I lt 2 a m o 9 amp u tc o tc oer o o oO o Oo a A L u o 2 2 Eo E x o gt o LPC11U34FHN33 311 40 4 8 8 no 1 1 2 1 8 26 LPC11U34FBD48 311 40 4 8 8 no 1 1 2 1 8 40 LPC11U34FHN33 421 48 4 8 2 10 no 1 1 2 1 8 26 LPC11U34FBD48 421 48 4 8 2 10 no 1 1 2 1 8 40 LPC11U35FHN33 401 64 4 8 2 10 no 1 1 2 1
47. atchDog Oscillator WDO with programmable frequency output PLL allows CPU operation up to the maximum CPU rate with the system oscillator or the IRC as clock sources A second dedicated PLL is provided for USB Clock output function with divider that can reflect the crystal oscillator the main clock the IRC or the watchdog oscillator W Power control LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 2 of 77 NXP Semiconductors LPC11U3x 3 Applications 32 bit ARM Cortex M0 microcontroller Integrated PMU Power Management Unit to minimize power consumption during Sleep Deep sleep Power down and Deep power down modes Power profiles residing in boot ROM provide optimized performance and minimized power consumption for any given application through one simple function call Four reduced power modes Sleep Deep sleep Power down and Deep power down Processor wake up from Deep sleep and Power down modes via reset selectable GPIO pins watchdog interrupt or USB port activity Processor wake up from Deep power down mode using one special function pin Power On Reset POR Brownout detect with up to four separate thresholds for interrupt and forced reset Unique device serial number for identification Single 3 3 V power supply 1 8 V to
48. be used as the clock source for the CPU with or without using the PLL On the LPC11U3x use the system oscillator to provide the clock source to USB The system oscillator operates at frequencies of 1 MHz to 25 MHz This frequency can be boosted to a higher frequency up to the maximum CPU operating frequency by the system PLL Watchdog oscillator The watchdog oscillator can be used as a clock source that directly drives the CPU the watchdog timer or the CLKOUT pin The watchdog oscillator nominal frequency is programmable between 9 4 kHz and 2 3 MHz The frequency spread over processing and temperature is 40 see also Table 13 System PLL and USB PLL The LPC11U3x contain a system PLL and a dedicated PLL for generating the 48 MHz USB clock The system and USB PLLs are identical The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz The input frequency is multiplied up to a high frequency with a Current Controlled Oscillator CCO The multiplier can be an integer value from 1 to 32 The CCO operates in the range of 156 MHz to 320 MHz To support this frequency range an additional divider keeps the CCO within its frequency range while the PLL is providing the desired output frequency The output divider can be set to divide by 2 4 8 or 16 to produce the output clock The PLL output frequency must be lower than 100 MHz Since the minimum output divider value is 2 it is insured that the PLL output has a 50 96 duty
49. brary uses a specific subset of I O Handler pins and in some cases other pins and peripherals such as the counter timers USART The LPC11U3x contains one USART The USART includes full modem control support for synchronous mode and a smart card interface The RS 485 9 bit mode allows both software address detection and automatic address detection using 9 bit mode The USART uses a fractional baud rate generator Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz Features Maximum USART data bit rate of 3 125 Mbit s 16 byte receive and transmit FIFOs Register locations conform to 16C550 industry standard Receiver FIFO trigger points at 1 B 4 B 8 B and 14 B Built in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values Fractional divider for baud rate control auto baud capabilities and FIFO control mechanism that enables software flow control implementation Support for RS 485 9 bit mode e Support for modem control Support for synchronous mode Includes smart card interface SSP serial I O controller The SSP controllers operate on a SSP 4 wire SSI or Microwire bus The controller can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer The SSP supports full duplex transfers with frames of
50. ces Two GPIO grouped interrupt modules enable an interrupt based on a programmable pattern of input states of a group of GPIO pins High current source output driver 20 mA on one pin High current sink driver 20 mA on true open drain pins Four general purpose counter timers with a total of up to 8 capture inputs and 13 match outputs Programmable Windowed WatchDog Timer WWDT with a dedicated internal low power WatchDog Oscillator WDO Analog peripherals 10 bit ADC with input multiplexing among eight pins W Serial interfaces USB 2 0 full speed device controller USART with fractional baud rate generation internal FIFO a full modem control handshake interface and support for RS 485 9 bit mode and synchronous mode USART supports an asynchronous smart card interface ISO 7816 3 Two SSP controllers with FIFO and multi protocol capabilities I C bus interface supporting the full I C bus specification and Fast mode Plus with a data rate of up to 1 Mbit s with multiple address recognition and monitor mode I O Handler for hardware emulation of serial interfaces and DMA supported through software libraries LPC11U37HFBD64 401 only B Clock generation Crystal Oscillator with an operating range of 1 MHz to 25 MHz system oscillator 12 MHz high frequency Internal RC oscillator IRC that can optionally be used as a system clock Internal low power low frequency W
51. ct data sheet Rev 2 2 11 March 2014 28 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 1 CRP1 disables access to the chip via the SWD and allows partial flash update excluding flash sector 0 using a limited set of the ISP commands This mode is useful when CRP is required and flash field updates are needed but all sectors cannot be erased 2 CRP2 disables access to the chip via the SWD and only allows full flash erase and update using a reduced set of the ISP commands 3 Running an application with level CRP3 selected fully disables any access to the chip via the SWD pins and the ISP This mode effectively disables ISP override using PIOO 1 pin as well If necessary the application must provide a flash update mechanism using IAP calls or using a call to the reinvoke ISP command to enable flash update via the USART CAUTION If level three Code Read Protection CRP3 is selected no future factory testing can be performed on the device In addition to the three CRP levels sampling of pin PIOO 1 for valid user code can be disabled For details see the LPC11Uxx user manual 7 18 6 4 APB interface The APB peripherals are located on one APB bus 7 18 6 5 AHBLite The AHBLite connects the CPU bus of the ARM Cortex MO to the flash memory the main static RAM and the ROM 7 18 6 6 External interrupt inputs All GPIO pins can be level or edge sensitive interrupt inputs LPC11U3X All i
52. deal transfer curve after appropriate adjustment of gain and offset errors See Figure 8 4 The offset error Eo is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve See Figure 8 5 The gain error Eg is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error and the straight line which fits the ideal transfer curve See Figure 8 6 The absolute error Er is the maximum difference between the center of the steps of the actual transfer curve of the non calibrated ADC and the ideal transfer curve See Figure 8 7 Tamb 25 C maximum sampling frequency fs 400 kSamples s and analog input capacitance Cia 1 pF 8 Input resistance Ri depends on the sampling frequency fs Rj 1 fs x Cia LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 36 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller offset gain error error Eo EG 1023 1022 1021 L 1020 1019 1018 Y LL code out 6 e 5 L 4L 3 L 2L 1 1 LSB ideal 7 okl iv 1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024 ViA LSBi offset error IA LSBideal Eo Vpp V 1LsB DD SS 1024 002aaf426 1 Exampl
53. down mode 20 27 Deep power down mode 28 System control 02000e ee 28 Heset us eh PRD ted edd ole ed ats 28 Brownout detection 28 Code security Code Read Protection CRP 28 APB interface 202 0055 29 A BLite itane x a duis eon aaa E MEER 29 External interrupt inputs 29 Emulation and debugging 30 Limiting values eese 31 Static characteristics 32 BOD static characteristics 38 Power consumption ssss 38 Peripheral power consumption 41 Electrical pin characteristics 43 Dynamic characteristics 46 Flash memory oer rela satan 46 External clock 00 000000 46 Internal oscillators lilius 47 I O piliS 5 xa oderat eto Een teens 48 I C DUS eve ree Reb et pet Shs 48 SSP interface 2 0000005 50 USB interface 0000000 00 53 Application information 54 Suggested USB interface solutions 54 XTAL input 56 XTAL Printed Circuit Board PCB layout guidelines 57 Standard I O pad configuration 58 Reset pad configuration 59 ADC effective input impedance 59 ADC usage notes 20 00 60 I O Handler software library applications 60 VO Handler I S 0 0 002 e e
54. e digital input output pin PIO1 10 12 amp l PU VO PIO1 10 General purpose digital input output pin PIO1 11 43 Bl EPU VO PIO1 11 General purpose digital input output pin PIO1 12 59 BI PU JO PIO1 12 General purpose digital input output pin PIO1 13 DTR B8 36 47 BII PU JO PIO1 13 General purpose digital input output pin CT16B0_MATO TXD O DTR Data Terminal Ready output for USART O CT16BO MATO Match output 0 for 16 bit timer 0 O TXD Transmitter output for USART PIO1_14 DSR A8 37 49 BII PU VO PIO1_14 General purpose digital input output pin CT16B0_MAT1 RXD l DSR Data Set Ready input for USART O CT16B0_MAT1 Match output 1 for 16 bit timer 0 l RXD Receiver input for USART PIO1_15 DCD 28 A4 43 57 BII PU VO PIO1 15 General purpose digital input output pin CT16B0 MAT2 SCK1 l DCD Data Carrier Detect input for USART O CT16B0_MAT2 Match output 2 for 16 bit timer 0 I O SCK1 Serial clock for SSP1 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 14 of 77 NXP Semiconductors LPC11U3x Table 3 Pin description 32 bit ARM Cortex M0 microcontroller
55. e of an actual transfer curve 2 The ideal transfer curve 3 Differential linearity error Ep 4 Integral non linearity E agj 5 Center of a step of the actual transfer curve Fig 8 ADC characteristics LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 37 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 9 1 BOD static characteristics Table 7 BOD static characteristics Tamb 25 C Symbol Parameter Conditions Min Typ Max Unit Vin threshold voltage interrupt level 1 assertion 2 22 V de assertion 2 35 V interrupt level 2 assertion 2 52 V de assertion 2 66 V interrupt level 3 assertion 2 80 V de assertion 2 90 V reset level 0 assertion 1 46 V de assertion 1 63 V reset level 1 assertion 2 06 V de assertion 2 15 V reset level 2 assertion 7 2 35 V de assertion 2 43 V reset level 3 assertion 7 2 63 V de assertion 2 71 V 1 Interrupt levels are selected by writing the level value to the BOD control register BODCTRL see the LPC11Uxx user manual 9 2 Power consumption Power measurements in Active Sleep and Deep sleep modes were performed under the following conditions see the LPC11Uxx user manual Co
56. ecuting code while 1 from flash internal pull up resistors disabled BOD disabled all peripherals disabled in the SYSAHBCLKCTRL register all peripheral clocks disabled low current mode USB DP and USB DM pulled LOW externally 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 10 Typical supply current versus temperature in Active mode All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 39 of 77 NXP Semiconductors LPC11U3x LPC11U3X 32 bit ARM Cortex M0 microcontroller 4 002aag751 IDD mA 3 48 MHz 2 Lo a 36 MHz 2 2 e oo 24 MHz 2 ee A ee es Se 1 12 MHz 1 0 40 15 10 35 60 85 temperature C Conditions Vpp 3 3 V Sleep mode entered from flash internal pull up resistors disabled BOD disabled all peripherals disabled in the SYSAHBCLKCTRL register all peripheral clocks disabled low current mode USB DP and USB DM pulled LOW externally 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 11 Typical supply current versus temperature in Sleep mode 002aag745 385 Seg IDD pA 375 365 355
57. ee 60 I O Handler UART 20 006 60 VO Handler C 0 0 0 0 0 0 c eee 61 I O Handler DMA 20 0005 61 continued gt gt NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 76 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller 12 Package outline sesess 62 13 Soldering RE 67 14 Abbreviations lrl eee 72 15 References lol IR ERE Ie ue 72 16 Revision history leseeseee 73 17 Legal information lssee 74 17 1 Data sheet status 00 74 17 2 Definitions sada tarbed mikia 74 17 3 Disclaimers nnana annaa 74 17 4 Trademarks 0 0 0 0 cece eee 75 18 Contact information 75 19 Contenis ec lc nonnii inai pE Nina 76 Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP Semiconductors N V 2014 All rights reserved For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 11 March 2014 Document identifier LPC11U3X
58. er 1 I O MOSI1 Master Out Slave In for SSP1 PIOO 22 AD6 20 E8 30 40 l PU VO PIOO 22 General purpose digital input output pin CT16B1 MAT1 MISO1 l AD6 A D converter input 6 O CT16B1_MAT1 Match output 1 for 16 bit timer 1 I O MISO1 Master In Slave Out for SSP1 PIOO 23 AD7 IOH 9 27 A5 42 56 6 1 PU JO PIOO 23 General purpose digital input output pin l AD7 A D converter input 7 VO IOH 9 I O Handler input output 9 LPC11U37HFBD64 401 only PIO1 O CT32B1 MATO l 1 BI i PU VO PIO1_0 General purpose digital input output pin IOH_10 7 O CT32B1_MATO0 Match output 0 for 32 bit timer 1 I O IOH 10 I O Handler input output 10 LPC11U37HFBD64 401 only PIO1 1 CT32B1 MAT1 l 17 Bl PU WO PIO1 1 General purpose digital input output pin IoH 11 CT32B1 MAT1 Match output 1 for 32 bit timer 1 VO IOH 11 I O Handler input output 11 LPC11U37HFBD64 401 only PIO1 2 CT32B1 MAT2 34 BII PU VO PIO1 2 General purpose digital input output pin loH 12 O CT32B1 MAT2 Match output 2 for 32 bit timer 1 VO IOH 12 I O Handler input output 12 LPC11U37HFBD64 401 only LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 13 of 77 NXP Semiconductors LPC11U3x 32 bit ARM
59. er s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Limiting values Stress above one or more limiting values as defined in the Absolute Maximum Ratings System of IEC 60134 will cause permanent damage to the device Limiting values are stress ratings only and proper operation of the device at these or any other conditions above those given in the Recommended operating conditions section if present or the Characteristics sections of this document is not warranted Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and
60. eset Programmable 24 bit timer with internal prescaler Selectable time period from Tey wDCLk x 256 x 4 to Tcy wDCLK x 224 x 4 in multiples of Tcy WDCLK x 4 The Watchdog Clock WDCLK source can be selected from the IRC or the dedicated watchdog oscillator WDO The clock source selection provides a wide range of potential timing choices of watchdog operation under different power conditions 7 18 Clocking and power control 7 18 1 Integrated oscillators The LPC11U3x include three independent oscillators the system oscillator the Internal RC oscillator IRC and the watchdog oscillator Each oscillator can be used for more than one purpose as required in a particular application Following reset the LPC11U3x operates from the internal RC oscillator until software switches to a different clock source The IRC allows the system to operate without any external crystal and the bootloader code to operate at a known frequency See Figure 7 for an overview of the LPC11U3x clock generation LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 24 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller peripheral clocks SYSAHBCLKCTRLn AHB clock enable IRC oscillator main clock SSPO PERIPHERAL CLOCK DIVIDER SSPO watchdog oscillator USA
61. gal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 71 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller 14 Abbreviations Table 20 Abbreviations Acronym Description A D Analog to Digital ADC Analog to Digital Converter AHB Advanced High performance Bus APB Advanced Peripheral Bus BOD BrownOut Detection GPIO General Purpose Input Output JTAG Joint Test Action Group PLL Phase Locked Loop RC Resistor Capacitor SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TAP Test Access Port USART Universal Synchronous Asynchronous Receiver Transmitter 15 References 1 LPC11U3x User manual UM10462 http www nxp com documents user manual UM1 0462 pdf 2 LPC11U3x Errata sheet http www nxp com documents errata sheet ES LPC11U3X pdf LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 72 of 77 NXP Semiconductors LPC11U3x 16 Revision history 32 bit ARM Cortex M0 microcontroller Table 21 Revision history Document ID Release date Data sheet status Change notice Supersedes LPC11U3X v 2 2 20140311 Product data sheet LPC11U3X v 2 1
62. gital or analog functions in order of the GPIO port number The default function after reset is listed first All port pins have internal pull up resistors enabled after reset except for the true open drain pins PIOO 4 and PIOO 5 32 bit ARM Cortex M0 microcontroller Every port pin has a corresponding IOCON register for programming the digital or analog function the pull up pull down configuration the repeater and the open drain modes The USART counter timer and SSP functions are available on more than one port pin Table 3 Pin description Symbol Reset state 1 Type Description RESET PIOO 0 N Pin HVQFN33 Q Pin TFBGA48 Pin LQFP48 Pin LQFP64 RESET External reset input with 20 ns glitch filter A LOW going pulse as short as 50 ns on this pin resets the device causing I O ports and peripherals to take on their default states and processor execution to begin at address 0 This pin also serves as the debug select input LOW level selects the JTAG boundary scan HIGH level selects the ARM SWD debug mode In deep power down mode this pin must be pulled HIGH externally The RESET pin can be left unconnected or be used as a GPIO pin if an external RESET function is not needed and Deep power down mode is not used 1 0 PIO0_0 General purpose digital input output pin PIOO_1 CLKOUT CT32B0_MAT2 USB_FTOGGLE 5 B PU 1 0 PIOO 1 General purpose digital
63. h these parameters is Rin 308 kQ ADC usage notes The following guidelines show how to increase the performance of the ADC in a noisy environment beyond the ADC specifications listed in Table 6 The ADC input trace must be short and as close as possible to the LPC11U3x chip e Shield The ADC input traces from fast switching digital signals and noisy power supply lines The ADC and the digital core share the same power supply Therefore filter the power supply line adequately To improve the ADC performance in a noisy environment put the device in Sleep mode during the ADC conversion I O Handler software library applications The following sections provide application examples for the I O Handler software library All library examples make use of the I O Handler hardware to extend the functionality of the part through software library calls The libraries are available on http www LPCware com 1 0 Handler 12S The I O Handler software library provides functions to emulate an 12S master transmit interface using the I O Handler hardware block The emulated 2S interface loops over a 1 kB buffer transmitting the datawords according to the 12S protocol Interrupts are generated every time when the first 512 bytes have been transmitted and when the last 512 bytes have been transmitted This allows the ARM core to load the free portion of the buffer with new data thereby enabling streaming audio Two channels with 16 bit pe
64. his document is subject to legal disclaimers Rev 2 2 11 March 2014 NXP Semiconductors N V 2014 All rights reserved 8 of 77 Product data sheet NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller PIO1 0 PIO1 25 PIO1 19 RESET PIOO 0 PIOO 1 PIO1 7 Vss XTALIN XTALOUT VDD PIOO 20 PIO1 10 PIO0 2 PIO1 26 PIO1 27 PIO1 4 Fig 5 64 PIO1 6 63 PIO1 16 62 PIOO_19 61 Plo0 18 60 PIOO_17 59 PIO1_12 58 Vpp 57 PlO1 15 56 Plo0 23 55 PlO1 9 54 Vss 53 PIOO_16 LPC11U35FBD64 401 LPC11U36FBD64 401 LPC11U37HFBD64 401 LPC11U37FBD64 501 52 SWDIO PIOO 15 51 PIO1 22 50 PIO1 3 49 PIO1 14 002aag812 PIO1 20 18 PIOT 1 17 See Table 3 for the full pin name Pin configuration LQFP64 PIOO 4 20 PIOO 5 21 PIOO 21 22 PIO1 18 28 PIOO 6 29 PIO1 24 27 PIOO 3 19 PIO1 17 23 PIO1 23 24 USB DM 25 USB DP 26 PIOO 7 30 PIO1 28 31 PIO1 5 32 Vpp PIO1 13 TRST PIOO 14 TDO PIOO 13 TMS PIOO 12 PIO1 11 TDI PIOO 11 PIO1 29 PIOO_22 PIO1_8 SWCLK PIOO 10 PIO0 9 PIOO0 8 PIO1 21 PIO1 2 Vpp LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 9 of 77 NXP Semiconductors LPC11U3x 6 2 Pin description Table 3 shows all pins and their assigned di
65. i master bus and more than one bus master connected to the interface can be controlled the bus Features The l C interface is an I C bus compliant interface with open drain pins The I2C bus interface supports Fast mode Plus with bit rates up to 1 Mbit s Easy to configure as master slave or master slave Programmable clocks allow versatile rate control Bidirectional data transfer between masters and slaves Multi master bus no central master Arbitration between simultaneously transmitting masters without corruption of serial data on the bus Serial clock synchronization allows devices with different bit rates to communicate via one serial bus Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer e The I C bus can be used for test and diagnostic purposes e The l C bus controller supports multiple address recognition and a bus monitor mode 10 bit ADC The LPC11U3x contains one ADC It is a single 10 bit successive approximation ADC with eight channels Features 10 bit successive approximation ADC Input multiplexing among 8 pins Power down mode Measurement range 0 V to Vpp e 10 bit conversion time gt 2 44 us up to 400 kSamples s Burst conversion mode for single or multiple inputs Optional conversion on transition of input pin or timer match signal Individual result registers for each ADC channel to reduce interrupt overhead Al
66. iconductors Footprint information for reflow soldering of HVQFN33 package M 9086 1 3 1 VO Vd SZ 2 Ald _ a 08 S 391 ese I zp eno GO e o 8 20 OA OID Solder resist covered via 0 30 PH ft a 0 60 SR cover 0 60 CU lt Oo x n 1o N N PID 0 30 CU OwDtot 5 10 OA 0 45 DM 4 25 m evia W 0 70 SP MANN SAAS AAA CAS 50929290000900 Wererersrarava VLL ROO i JJ GapD erem poor ES 126262626252929 1 2240 gt 2 70 SP evia SDhtot MS eem E T N LAN 4 85 CU DHS 5 80 CU LbD SPD 1 00 SP 4 7 95 CU LaD dS 02 101u3S as SS e Nd 98t SHA V0 01 S 0 3MO VO 028 AlO A side fully covered number of vias 20 solder land plus solder paste 7 solder land Solder resist s y WN solder paste deposit 1 N 001aa0134 Stencil thickness 0 125 mm Dimensions in mm occupied area Fig 40 Reflow soldering for the HVQFN33 7x7 package NXP Semiconductors N V 2014 All rights reserved All information provided in this docume
67. ing values Table 4 Limiting values In accordance with the Absolute Maximum Rating System IEC 60134 1 Symbol Parameter Conditions Min Max Unit Vpp supply voltage core and 21 0 5 14 6 V external rail Vi input voltage 5 V tolerant digital I O pins SII2 9 5 45 5 V Vpp 2 1 8 V Vpp 20V 0 5 413 6 V 5 V tolerant open drain pins 24 0 5 45 5 PIOO 4 and PIOO 5 ViA analog input voltage pin configured as analog input 2 0 5 4 6 V 3 Ipp supply current per supply pin 100 mA Iss ground current per ground pin 100 mA latch I O latch up current 0 5Vpp lt Vi lt 1 5Vpp 100 mA Tj 125 C Tstg storage temperature non operating 6 65 150 C Timax maximum junction 150 C temperature Ptot pack total power dissipation per based on package heat 1 5 W package transfer not device power consumption Vesp electrostatic discharge human body model all pins F 6500 V voltage 1 The following applies to the limiting values a This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge Nonetheless it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum b Parameters are valid over operating temperature range unless otherwise specified All voltages are with respect to Vss unless otherwise noted c The li
68. input output pin A LOW level on this pin during reset starts the ISP command handler or the USB device enumeration CLKOUT Clockout pin CT32B0_MAT2 Match output 2 for 32 bit timer 0 USB FTOGGLE USB 1 ms Start of Frame signal PIOO 2 SSELO CT16BO CAPO IOH 0 1 0 PIOO 2 General purpose digital input output pin 1 0 SSELO Slave select for SSPO CT16BO CAPO Capture input 0 for 16 bit timer 0 1 0 IOH 0 I O Handler input output 0 LPC11U37HFBD64 401 only PIO0_3 USB_VBUS IOH_1 1 0 PIO0_3 General purpose digital input output pin A LOW level on this pin during reset starts the ISP command handler A HIGH level during reset starts the USB device enumeration USB_VBUS Monitors the presence of USB bus power 1 0 IOH 1 I O Handler input output 1 LPC11U37HFBD64 401 only LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 10 of 77 NXP Semiconductors LPC11U3x Table 3 Pin description 32 bit ARM Cortex M0 microcontroller Symbol a e Reset Type Description Z E state O m L E ul zuo I e l c c c a a2 a amp PIOO 4 SCL IOH 2 10 G3 15 20 I lA
69. ion provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 26 of 77 NXP Semiconductors LPC11U3x 7 18 5 1 7 18 5 2 7 18 5 3 7 18 5 4 LPC11U3X 32 bit ARM Cortex M0 microcontroller consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider which provides even better power control Power profiles The power consumption in Active and Sleep modes can be optimized for the application through simple calls to the power profile The power configuration routine configures the LPC11U3x for one of the following power modes Default mode corresponding to power configuration after reset CPU performance mode corresponding to optimized processing capability Efficiency mode corresponding to optimized balance of current consumption and CPU performance Low current mode corresponding to lowest power consumption In addition the power profile includes routines to select the optimal PLL settings for a given system clock and PLL input clock Remark When using the USB configure the LPC11U3x in Default mode Sleep mode When Sleep mode is entered the clock to the core is stopped Resumption from the Sleep mode does not need any special sequence but re enabling the clock to the ARM core In Sleep mode execution
70. ive testing or application requirements NXP Semiconductors accepts no liability for inclusion and or use of non automotive qualified products in automotive equipment or applications In the event that customer uses the product for design in and use in automotive applications to automotive specifications and standards customer a shall use the product without NXP Semiconductors warranty of the product for such automotive applications use and specifications and b 18 Contact information 32 bit ARM Cortex MO microcontroller whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk and c customer fully indemnifies NXP Semiconductors for any liability damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications 17 4 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners I C bus logo is a trademark of NXP Semiconductors N V For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Prod
71. ject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 34 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller Table 5 Static characteristics continued Tamb 40 C to 85 C unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Pin capacitance Cio input output pins configured for analog function 7 1 pF capacitance I C bus pins PIOO 4 and PIO0_5 E E 2 5 pF pins configured as GPIO 2 8 pF 1 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 2 For USB operation 3 0 V lt Vpp lt 3 6 V Guaranteed by design 3 IRC enabled system oscillator disabled system PLL disabled 4 Ibp measurements were performed with all pins configured as GPIO outputs driven LOW and pull up resistors disabled 5 BOD disabled 6 All peripherals disabled in the AHBCLKCTRL register Peripheral clocks to USART SSP0 1 disabled in the SYSCON block 7 USB_DP and USB_DM pulled LOW externally 8 Low current mode PWR LOW CURRENT selected when running the set power routine in the power profiles 9 IRC disabled system oscillator enabled system PLL enabled 10 WAKEUP pin pulled HIGH externally An external pull up resistor is required on the RESET pin for the Deep power down mode 11 Including voltage on o
72. l GPIO pins default to inputs with interrupt disabled at reset Pin registers allow pins to be sensed and set individually Up to eight GPIO pins can be selected from all GPIO pins to create an edge or level sensitive GPIO interrupt request Any pin or pins in each port can trigger a port interrupt USB interface The Universal Serial Bus USB is a 4 wire bus that supports communication between a host and one or more up to 127 peripherals The host controller allocates the USB bandwidth to attached devices through a token based protocol The bus supports hot plugging and dynamic configuration of the devices The host controller initiates all transactions The LPC11U3x USB interface consists of a full speed device controller with on chip PHY PHYsical layer for device functions Remark Configure the LPC11U3x in default power mode with the power profiles before using the USB see Section 7 18 5 1 Do not use the USB with the part in performance efficiency or low power mode Full speed USB device controller The device controller enables 12 Mbit s data exchange with a USB Host controller It consists of a register interface serial interface engine and endpoint buffer memory The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer The status of a completed USB transfer or error condition is indicated via status registers If enabled an interrupt is generated Features
73. l information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 22 of 77 NXP Semiconductors LPC11U3x 7 15 7 15 1 7 16 rm 7 17 1 LPC11U3X 32 bit ARM Cortex M0 microcontroller General purpose external event counter timers The LPC11U3x includes two 32 bit counter timers and two 16 bit counter timers The counter timer is designed to count cycles of the system derived clock It can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt Features e A 32 bit 16 bit timer counter with a programmable 32 bit 16 bit prescaler Counter or timer operation Up to two capture channels per timer that can take a snapshot of the timer value when an input signal transitions A capture event can also generate an interrupt Four match registers per timer that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Resettimer on match with optional interrupt generation Up to four external outputs corresponding to match registers with the following capabilities SetLOW on match Set HIGH on match Toggle on match
74. l information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 27 of 77 NXP Semiconductors LPC11U3x 7 18 5 5 7 18 6 7 18 6 1 7 18 6 2 7 18 6 3 LPC11U3X 32 bit ARM Cortex M0 microcontroller Power down mode reduces power consumption compared to Deep sleep mode at the expense of longer wake up times Deep power down mode In Deep power down mode power is shut off to the entire chip except for the WAKEUP pin The LPC11U3x can wake up from Deep power down mode via the WAKEUP pin The LPC11U3x can be prevented from entering Deep power down mode by setting a lock bit in the PMU block Locking out Deep power down mode enables the application to keep the watchdog timer or the BOD running at all times When entering Deep power down mode an external pull up resistor is required on the WAKEUP pin to hold it HIGH Pull the RESET pin HIGH to prevent it from floating while in Deep power down mode System control Reset Reset has four sources on the LPC11U3x the RESET pin the Watchdog reset power on reset POR and the BrownOut Detection BOD circuit The RESET pin is a Schmitt trigger input pin Assertion of chip reset by any source once the operating voltage attains a usable level starts the IRC and initializes the flash controller A LOW going pulse as short as 50 ns resets the part When the i
75. may cause the IRC to fall outside the 12 MHz 1 96 accuracy specification for voltages below 2 7 V Fig 22 Internal RC oscillator frequency versus temperature Table 13 Dynamic characteristics Watchdog oscillator Symbol Parameter Conditions Min Typ Max Unit fosc nt internal oscillator DIVSEL Ox1F FREQSEL Ox1 IS 94 l kHz frequency in the WDTOSCCTRL register DIVSEL 0x00 FREQSEL OxF IS 2300 kHz in the WDTOSCCTRL register 1 Typical ratings are not guaranteed The values listed are at nominal supply voltages All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 47 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 2 The typical frequency spread over processing and temperature Tamb 40 C to 85 C is 40 3 See the LPC11Uxx user manual 10 4 I O pins Table 14 Dynamic characteristics I O pins Tamb 40 C to 85 C 3 0 V lt Vpp x 3 6 V Symbol Parameter Conditions Min Typ Max Unit tr rise time pin configured as output 3 0 5 0 ns tr fall time pin configured as output 2 5 5 0 ns 1 Applies to standard port pins and RESET pin 10 5 I C bus Table 15 Dynamic characteristic I C bus pins Tamb
76. miting values are stress ratings only Operating the part at these values is not recommended and proper operation is not guaranteed The conditions for functional operation are specified in Table 5 2 Maximum minimum voltage above the maximum operating voltage see Table 5 and below ground that can be applied for a short time lt 10 ms to a device without leading to irrecoverable failure Failure includes the loss of reliability and shorter lifetime of the device 3 See Table 6 for maximum operating voltage 4 Vpop present or not present Compliant with the I2C bus standard 5 5 V can be applied to this pin when Vpp is powered down 5 Including voltage on outputs in 3 state mode 6 The maximum non operating storage temperature is different than the temperature for required shelf life which should be determined based on required shelf lifetime Please refer to the JEDEC spec J STD 033B 1 for further details 7 Human body model equivalent to discharging a 100 pF capacitor through a 1 5 KQ series resistor LPC11U3X All information provided in this document is subject to legal disclaimers Rev 2 2 11 March 2014 NXP Semiconductors N V 2014 All rights reserved 31 of 77 Product data sheet NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller 9 Static characteristics Table 5 Static characteristics Tamb 40 C to 85 C unless otherwise specified
77. n 0 00 0 18 49 345 49 345 0 3 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included hvgfn33f po i References Outline bak Furopean Issue date version IEC JEDEC JEITA projection Htt MO 220 c9 11 10 17 NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 62 of 77 NXP Semiconductors LPC11U3x HVQFN33 plastic thermal enhanced very thin quad flat package no leads 33 terminals body 7 x 7 x 0 85 mm 32 bit ARM Cortex M0 microcontroller Fig 35 Package outline HVQFN33 7 x 7 x 0 85 mm LPC11U3X All information provided in this document is subject to legal disclaimers D T8 terminal 1 index area E A A4 Y i c detail X Y a e L C v M C A B wo C Y L i Iw F e t Eh e2 d Y terminal 1 index area 0 2 5 2mm j Lol i 1 Dimensions scale Unit ADU A b c DO Dp EO E e e e L v w y y max 1 00 0 05 0 35 7 1 485 7 1 4 85 0 75 mm nom 0 85 0 02 0 28 0 2 7 0 4 70 7 0 4 70 0 65 4 55 4 55 0 60 0 1 0 05 0 08 0 1 min 0 80 0 00 0 23 6 9 4 55 6 9 4 55 0 45 Note 1 Plastic or metal protrusions of 0 075 mm maximum per side are not included hvqfn33_po References Outline European Issue date version IEC JEDE
78. nal pull up resistor is required on this pin for the Deep power down mode See Figure 32 for the reset pad configuration 3 5 V tolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 31 4 l C bus pin compliant with the I C bus specification for 1 C standard mode I C Fast mode and 2C Fast mode Plus The pin requires an external pull up to provide output functionality When power is switched off this pin is floating and does not disturb the I2C lines Open drain configuration applies to all functions on this pin 5 5Vtolerant pad providing digital I O functions with configurable pull up pull down resistors and configurable hysteresis see Figure 31 includes high current output driver 6 5V tolerant pad providing digital I O functions with configurable pull up pull down resistors configurable hysteresis and analog input When configured as a ADC input digital section of the pad is disabled and the pin is not 5 V tolerant see Figure 31 includes digital input glitch filter 7 Pad provides USB functions It is designed in accordance with the USB specification revision 2 0 Full speed and Low speed mode only This pad is not 5 V tolerant 8 When the system oscillator is not used connect XTALIN and XTALOUT as follows XTALIN can be left floating or can be grounded grounding is preferred to reduce susceptibility to noise Leave XTALOUT floating LPC11U3X All
79. nfigure all pins as GPIO with pull up resistor disabled in the IOCON block Configure GPIO pins as outputs using the GPIOnDIR registers Write 0 to all GPIOnDATA registers to drive the outputs LOW LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 38 of 77 NXP Semiconductors LPC11U3x LPC11U3X 32 bit ARM Cortex M0 microcontroller 002aag749 lop 48 MHz mA es 36 MHz 2 LR ILLL M 24 MHz 2 E 12 MHz 1 ee Sd ES la REIS Vpp V Conditions Tamb 25 C Active mode entered executing code while 1 from flash internal pull up resistors disabled BOD disabled all peripherals disabled in the SYSAHBCLKCTRL register all peripheral clocks disabled low current mode USB DP and USB DM pulled LOW externally 1 System oscillator and system PLL disabled IRC enabled 2 System oscillator and system PLL enabled IRC disabled Fig 9 Typical supply current versus regulator supply voltage Vpp in active mode 002aag750 lop 48 MHz ma ss sso Me 36 MHz 2 DECRE EMEN ee cimi c 24 MHz 2 RC EM ee RE 3 12 MHz 1 0 40 15 10 35 60 85 temperature C Conditions Vpp 3 3 V Active mode entered ex
80. nformation provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 29 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller 7 19 Emulation and debugging Debug functions are integrated into the ARM Cortex MO Serial wire debug functions are supported in addition to a standard JTAG boundary scan The ARM Cortex MO is configured to support up to four breakpoints and two watch points The RESET pin selects between the JTAG boundary scan RESET LOW and the ARM SWD debug RESET HIGH The ARM SWD debug port is disabled while the LPC11U3x is in reset To perform boundary scan testing follow these steps Erase any user code residing in flash Power up the part with the RESET pin pulled HIGH externally Wait for at least 250 us Pull the RESET pin LOW externally Perform boundary scan operations oar WD Once the boundary scan operations are completed assert the TRST pin to enable the SWD debug mode and release the RESET pin pull HIGH Remark The JTAG interface cannot be used for debug purposes LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 30 of 77 LPC11U3x 32 bit ARM Cortex M0 microcontroller NXP Semiconductors 8 Limit
81. nly PIOO 9 MOSIO 18 F7 28 37 Bl EPU VO PIOO 9 General purpose digital input output pin CT16BO MATT R IOH 7 y o MOSIO Master Out Slave In for SSPO O CT16B0_MAT1 Match output 1 for 16 bit timer 0 Reserved y o IOH 7 I O Handler input output 7 LPC11U37HFBD64 401 only LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 11 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 3 Pin description Symbol a IS Reset Type Description Z E state Cn k E ul 2 u O og I e l c c amp amp amp a amp SWCLK PIOO 10 SCK0 19 E7 29 38 J LPU SWCLK Serial wire clock and test clock TCK for CT16BO MAT2 JTAG interface VO PIOO 10 General purpose digital input output pin O SCKO Serial clock for SSPO O CT16B0_MAT2 Match output 2 for 16 bit timer 0 TDI PIOO_11 ADO 21 D8 32 42 1 EPU TDI Test Data In for JTAG interface CT32B0 MATS VO PIOO 11 General purpose digital input output pin l ADO A D converter input 0 O CT32B0_MAT3 Match output 3 for 32 bit timer 0 TMS PIOO 12 AD1 22 C7 33 44 Bli PU TMS Test Mode Select for JTAG interface CT32B1_CAPO TT VO PIO 12 Gene
82. ns and the SDA SCL bus lines without exceeding the maximum specified t LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 48 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller 7 In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing 8 The maximum typ pat could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ par or tvp Ack by a transition time see UM10204 This maximum must only be met if the device does not stretch the LOW period ti ow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock 9 tSU DAT is the data set up time that is measured with respect to the rising edge of SCL applies to data in transmission and the acknowledge 10 A Fast mode I C bus device can be used in a Standard mode I C bus system but the requirement tsy par 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line tr max tsu pAr 1000 250 1250 ns according to
83. nt is subject to legal disclaimers LPC11U3X Rev 2 2 11 March 2014 68 of 77 Product data sheet NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller Footprint information for reflow soldering of TFBGA48 package SOT1155 2 OJOJOO OO OO OO OO solder land solder paste deposit 9j solder land plus solder paste occupied area solder resist DIMENSIONS in mm 60000 Oe OD 010101919 see detail X detail X P SL SP SR Hx Hy 0 50 0 225 0 275 0 325 4 75 4 75 sot 155 2 fr Fig 41 Reflow soldering for the TFBGA48 package LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 69 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Footprint information for reflow soldering of LQFP48 package Generic footprint pattern Refer to the package outline drawing for actual layout A solder land occupied area DIMENSIONS in mm P1 P2 Ax Ay Bx By C D1 D2 Gx Gy Hx Hy 0 500 0 560 10 350 10 350 7 350 7 350 1 500 0 280 0 500 7 500 7 500 10 650 10 650 Fig 42 Reflow soldering for the LQFP48 package Hx m Gx ry PA pa toa oat oa ce ipa ipa ipa tpa pa et PAAA
84. nternal Reset is removed the processor begins executing at address 0 which is initially the Reset vector mapped from the boot block At that point all of the processor and peripheral registers have been initialized to predetermined values In Deep power down mode an external pull up resistor is required on the RESET pin Brownout detection The LPC11U3x includes up to four levels for monitoring the voltage on the Vpp pin If this voltage falls below one of the selected levels the BOD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to cause a CPU interrupt Alternatively software can monitor the signal by reading a dedicated status register Four threshold levels can be selected to cause a forced reset of the chip Code security Code Read Protection CRP CRP provides different levels of security in the system so that access to the on chip flash and use of the Serial Wire Debugger SWD and In System Programming ISP can be restricted Programming a specific pattern into a dedicated flash location invokes CRP IAP commands are not affected by the CRP In addition ISP entry via the PIOO 1 pin can be disabled without enabling CRP For details see the LPC11Uxx user manual There are three levels of Code Read Protection All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Produ
85. operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 46 of 77 NXP Semiconductors LPC11U3x LPC11U3X 10 3 32 bit ARM Cortex M0 microcontroller tCHCX tcLCH tCHCL tcLcx Toy clk 002aaa907 Fig 21 External clock timing with an amplitude of at least Viigus 200 mV Internal oscillators Table 12 Dynamic characteristics IRC Tamb 40 C to 85 C 2 7 V lt Vpp lt 3 6 Vil Symbol Parameter Conditions Min Typ Max Unit fosc RC internal RC oscillator 11 88 12 12 12 MHz frequency 1 Parameters are valid over operating temperature range unless otherwise specified 2 Typical ratings are not guaranteed The values listed are at room temperature 25 C nominal supply voltages 12 15 002aaf403 f MHz VDD 3 6V 3 3V 3 0 V 12 05 27V 2 4 V 2 0 V 11 95 11 85 40 15 10 35 60 85 temperature C Conditions Frequency values are typical values 12 MHz 1 accuracy is guaranteed for 2 7 V lt Vpp 3 6 V and Tamb 40 C to 85 C Variations between parts
86. r channel are supported The code size of the software library is 1 kB and code must be executed from the SRAM1 memory area reserved for the I O Handler code 1 0 Handler UART The I O Handler UART library emulates one additional full duplex UART The emulated UART can be configured for 7 or 8 data bits no parity and 1 or 2 stop bits The baud rate is configurable up to 115200 baud The RXD signal is available on three I O Handler pins IOH 6 IOH 16 IOH 20 while TXD and CTS are available on all 21 I O Handler pins The code size of the software library is about 1 2 kB and code must be executed from the SRAM1 memory area reserved for the I O Handler code All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 60 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 11 8 3 I O Handler I C The I O Handler IC library allows to have an additional I2C bus master I C read I C write and combined I C read write are supported Data is automatically read from and written to user defined buffers The I O Handler 12C library combined with the on chip IC module allows to have two distinct I C buses allowing to separate low speed from high speed devices or bridging two I C buses 11 8 4 I O Handler DMA The I O Handler DMA library offers DMA like functionality Four types of transfer are suppo
87. r of 100 pF Figure 29 with an amplitude between 200 mV RMS and 1000 mV RMS This signal corresponds to a square wave signal with a signal swing of between 280 mV and 1 4 V The XTALOUT pin in this configuration can be left unconnected External components and models used in oscillation mode are shown in Figure 30 and in Table 18 and Table 19 Since the feedback resistance is integrated on chip only a crystal and the capacitances Cy and Cx need to be connected externally in case of fundamental mode oscillation L Cj and Rs represent the fundamental frequency Capacitance Cp in Figure 30 represents the parallel package capacitance and must not be larger than 7 pF Parameters Fosc C_ Rs and Cp are supplied by the crystal manufacturer LPC1xxx T XTALIN XTALOUT 4 CL OP XTAL _ k Rs Cxi Cx2 T e o 002aaf424 Fig 30 Oscillator modes and models oscillation mode of operation and external crystal model used for Cx1 Cx2 evaluation All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 56 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 18 Recommended values for Cx1 Cx2 in oscillation mode crystal and external components parameters low frequency mode
88. ral purpose digital input output pin l AD1 A D converter input 1 l CT32B1 CAPO Capture input 0 for 32 bit timer 1 TDO PIOO 13 AD2 23 C8 34 45 6 i PU O TDO Test Data Out for JTAG interface CT32B1 MATO ES VO PIOO 13 General purpose digital input output pin l AD2 A D converter input 2 O CT32B1 MATO Match output 0 for 32 bit timer 1 TRST PIOO 14 AD3 24 B7 35 46 6 EPU TRST Test Reset for JTAG interface CT32B1_MAT1 T VO PIOO 14 General purpose digital input output pin l AD3 A D converter input 3 O CT32B1_MAT1 Match output 1 for 32 bit timer 1 SWDIO PIO0_15 AD4 25 B6 39 52 l PU VO SWDIO Serial wire debug input output CT32B1_MAT2 Y F VO PIOO 15 General purpose digital input output pin l AD4 A D converter input 4 O CT32B1_MAT2 Match output 2 for 32 bit timer 1 PIOO 16 AD5 26 A6 40 53 EPU JO PIOO 16 General purpose digital input output pin CTS32B1 MATS IOH 8 l AD5 A D converter input 5 WAKEUP O CT32B1_MAT3 Match output 3 for 32 bit timer 1 VO IOH 8 I O Handler input output 8 LPC11U37HFBD64 401 only l WAKEUP Deep power down mode wake up pin with 20 ns glitch filter Pull this pin HIGH externally before entering Deep power down mode then pull LOW to exit Deep power down mode A LOW going pulse as short as 50 ns wakes up the part LPC11U3X All information provided in this doc
89. right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof LPC11U3X All information provided in this document is subject to legal disclaimers Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or environmental damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is custom
90. rogrammable pseudo open drain mode e Programmable 10 ns glitch filter on pins PIOO 22 PIOO 23 and PIOO 11 to PIOO 16 The glitch filter is turned on by default Programmable hysteresis Programmable input inverter General Purpose Input Output GPIO The GPIO registers control device pin functions that are not connected to a specific peripheral function Pins can be dynamically configured as inputs or outputs Multiple outputs can be set or cleared in one write operation LPC11U3x use accelerated GPIO functions e GPIO registers are a dedicated AHB peripheral so that the fastest possible I O timing can be achieved Entire port value can be written in one instruction Any GPIO pin providing a digital function can be programmed to generate an interrupt on a level a rising or falling edge or both The GPIO block consists of three parts 1 The GPIO ports 2 The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts 3 Two GPIO group interrupt blocks to control two combined interrupts from all GPIO pins All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 19 of 77 NXP Semiconductors LPC11U3x 7 8 1 7 9 7 9 1 7 9 1 1 7 10 LPC11U3X 32 bit ARM Cortex M0 microcontroller Features GPIO pins can be configured as input or output by software Al
91. rted memory to memory memory to peripheral peripheral to memory and peripheral to peripheral Supported peripherals are USART SSP0 1 ADC and GPIO DMA transfers can be triggered by the source target peripheral software counter timer module CT16B1 or I O Handler pin PIO1 6 IOH 16 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 61 of 77 NXP Semiconductors LPC11U3x 12 Package outline 32 bit ARM Cortex M0 microcontroller HVQFN33 plastic thermal enhanced very thin quad flat package no leads 32 terminals body 5 x 5 x 0 85 mm terminal 1 index area Fig 34 Package outline HVQFN33 5 x 5 x 0 85 mm LPC11U3X All information provided in this document is subject to legal disclaimers A4 i c detail X C ei amp v ClA B Y4 C gt Uy wc 17 v EE cr e A cj A Cc ay 1 E e2 i 1 2 e ci Y 24 terminal 1 index area 32 25 Dn 0 d 5 mm i L 1 Dimensions mm are the original dimensions scale Uni A AY b c DD p EU E e e e L w y y max 0 05 0 30 51 375 51 375 0 5 mm nom 0 85 0 2 05 35 35 0 05 0 05 0 1 mi
92. s of the PCB layout increase All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 57 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller 11 4 Standard I O pad configuration Figure 31 shows the possible pin modes for standard I O pins with analog input function Digital output driver Digital input Pull up enabled disabled Digital input Pull down enabled disabled Digital input Repeater mode enabled disabled Analog input VDD VDD open drain enable T pin configured output enable oE 2n ESD as digital output P p driver data output E strong pull down ESD Vss VDD iere pull up H X weak pin configured enable m pull down repeater mode as digital input pull down enable enable data input 10 ns RC GLITCH FILTER select data inverter select glitch filter select analog input pin configured p4 as analog input analog input 002aaf695 Fig 31 Standard I O pad configuration LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 58 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller 11 5 Reset pad configura
93. te a logic HIGH while below the 3 6 V allowable maximum voltage For the following operating conditions VBUS max 5 25 V Vpp 3 6 V the voltage divider should provide a reduction of 3 6 V 5 25 V or 0 686 V Fig 27 USB interface on a self powered device where USB VBUS 5 V USB CONNECT Soft connect switch R1 1 5 KQ LPC1xxx R2 R3 USB VBUS USB B connector UsB pP RS 339 d USB pM 887330 i Vss aaa 010178 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 54 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller For a bus powered device the VBUS signal does not need to be connected to the USB_VBUS pin see Figure 28 The USB_CONNECT function can additionally be connected as shown in Figure 27 to prevent the USB from timing out when there is a significant delay between power up and handling USB traffic Fig 28 USB interface on a bus powered device V PL REGULATOR LPC1xxx R1 1 5 kQ VBUS T USB DP Rs 330 j USB B pote connector USB DM Rs 339 Vss aaa 010179 LPC11U3X Remark When a bus powered circuit as shown in
94. tion Rpu dr 318 20 ns RC reset aurcH FILTER lt Fig 32 Reset pad configuration Vss 002aaf274 11 6 ADC effective input impedance A simplified diagram of the ADC input channels can be used to determine the effective input impedance seen from an external voltage source See Figure 33 ADC Block ADC Source COMPARATOR Fig 33 ADC input channel 002aah615 The effective input impedance Rin seen by the external voltage source Vgxr is the parallel impedance of 1 fa x Cia Rmux Rew and 1 fs x Cio and can be calculated using Equation 1 with fs sampling frequency Cia ADC analog input capacitance Rmux analog mux resistance Rew switch resistance Cio pin capacitance 1 1 B it B ure in f x C mux SW f x C LPC11U3X All information provided in this document is subject to legal disclaimers 1 NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 59 of 77 NXP Semiconductors LPC11U3x 11 8 11 8 1 11 8 2 LPC11U3X 32 bit ARM Cortex M0 microcontroller Under nominal operating condition Vpp 3 3 V and with the maximum sampling frequency fs 400 kHz the parameters assume the following values Cia 1 pF max Rmux 2 KQ max Rew 1 3 KQ max Cio 7 1 pF max The effective input impedance wit
95. uct data sheet Rev 2 2 11 March 2014 75 of 77 NXP Semiconductors LPC11U3x 19 Contents 32 bit ARM Cortex M0 microcontroller 1 General description esses 1 2 Features and benefits 1 3 Applications leeren 3 4 Ordering information 0 0 2005 3 4 1 Ordering options 0000 eae 4 5 Block diagram L 5 6 Pinning information Lees 6 6 1 PINNING oe desee eru ET de biked en d 6 6 2 Pin description 2 0005 10 7 Functional description 17 7 1 On chip flash programming memory 17 7 2 EEPROM esu sure xar ox are Rog 17 7 8 SRAM ose REL ERES EI IPS 17 7 4 On chip ROM sulellselslelss 17 7 5 Memory map 00 eee eee 17 7 6 Nested Vectored Interrupt Controller NVIG inni meer aide ace 18 7 6 1 Features 02 000 18 7 6 2 Interrupt sources l l eese 19 7 7 IOCON block 02000 eee eee 19 7 7 1 FeatUles lods epe tein teiba gen 19 7 8 General Purpose Input Output GPIO 19 7 8 1 Fatt c4 I Cr 20 7 9 USB interface 0 00 eae 20 7 9 1 Full speed USB device controller 20 7 9 1 1 Features 2 0 2 0 0 cee eee 20 7 10 1 O Handler LPC11U37HFBD64 401 only 20 7 11 USART sii rannas tetti Rope ails Ate 21 7 11 1 FeatU res 5e coo t e ped he 21 7 12 SSP serial I O controller 21
96. ument is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 12 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller Table 3 Pin description Symbol a es Reset Type Description Z E 3 state GO u L i zuo I e l c c c a aaa PIOO 17 RTS 30 A3 45 60 3 EPU VO PIOO 17 General purpose digital input output pin CT32B0_CAPO SCLK O RTS Request To Send output for USART I CT32BO CAPO Capture input 0 for 32 bit timer 0 y o SCLK Serial clock input output for USART in synchronous mode PIOO 18 RXD 31 B3 46 61 EPU lO PIOO 18 General purpose digital input output pin CTS2B0 MATO RXD Receiver input for USART Used in UART ISP mode O CT32BO MATO Match output 0 for 32 bit timer 0 PIOO 19 TXD 32 B2 47 62 Bl PU WO PIOO 19 General purpose digital input output pin C132B0_MAT1 O TXD Transmitter output for USART Used in UART ISP mode O CT32B0_MAT1 Match output 1 for 32 bit timer 0 PIOO_20 CT16B1_CAPO 7 F2 9 11 B 1 PU I O PIOO 20 General purpose digital input output pin l CT16B1 CAPO Capture input 0 for 16 bit timer 1 PIOO 21 CT16B1 MATO 12 G4 17 22 Bl PU I O PIOO 21 General purpose digital input output pin MOSI O CT16B1_MATO Match output 0 for 16 bit tim
97. utputs in 3 state mode 12 3 state outputs go into 3 state mode in Deep power down mode 13 Allowed as long as the current limit does not exceed the maximum current allowed by the device 14 To Vss 15 Includes external resistors of 33 O 1 96 on USB DP and USB DM LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 35 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex M0 microcontroller Table 6 ADC static characteristics Tamb 40 C to 85 C unless otherwise specified ADC frequency 4 5 MHz Vpp 2 5 V to 3 6 V Symbol Parameter Conditions Min Typ Max Unit ViA analog input voltage 0 Vpp V Cia analog input capacitance 1 pF Ep differential linearity error pll t1 LSB Ei adi integral non linearity GI 1 5 LSB Eo offset error ia t3 5 LSB Eg gain error 5I 0 6 Er absolute error 6 4 LSB Rysi voltage source interface 40 KQ resistance Ri input resistance 718 25 MQ 1 The ADC is monotonic there are no missing codes 2 The differential linearity error Ep is the difference between the actual step width and the ideal step width See Figure 8 3 The integral non linearity E agj is the peak difference between the center of the steps of the actual and the i
98. x area E Gi Go Gs Gs Gri Gs Gs TRST PIOO 14 AD3 CT32B1 MAT1 TDO PIOO 13 AD2 CT32B1 MATO TMS PIOO 12 AD1 CT32B1 CAPO TDI PIOO 11 ADO CT32BO MAT3 PIOO 22 ADG CT16B1 MAT1 MISO1 SWCLK PIOO 10 SCKO CT16BO MAT2 PIOO 9 MOSIO CT16BO MAT1 PIOO 8 MISOO CT16BO MATO PIO1 19 DTR SSEL1 RESET PIOO 0 PIOO 4 CLKOUT CT32B0 MAT2 USB FTOGGLE XTALIN XTALOUT VDD PIOO 20 CT16B1 CAPO PIOO 2 SSELO CT16BO CAPO w e lt 9 15 mD 12 m 002aag809 PIOO 4 SCL PIOO 5 SDA PIOO 21 CT16B1 MATO MOSI1 PIOO 7 CTS PIOO 3 USB VBUS PIOO 6 USB CONNECT SCKO Transparent top view For parts LPC11U34FHN33 311 LPC11U34FHN33 421 LPC11U35FHN33 401 LPC11U35FHI33 501 Fig2 Pin configuration HVQFN33 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2 2 11 March 2014 6 of 77 NXP Semiconductors LPC11U3x 32 bit ARM Cortex MO microcontroller Fig 3 ball A1 index area m O O U Er LPC11U35FET48 501 Me OOOOOO Mee OO0O000 OO OO CHO OO OO OO OO OO oOo0o000000 QUOC DO DOOGOGO 002aag810 Transparent top view Pin configuration TFBGA48 LPC11U3X All information provided in this document is subject to legal disclaimers NXP Semiconductors N V 2014 All rights reserved Product data sheet Rev 2
99. y agreed otherwise in writing In no event however shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet 17 3 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the
100. y o PIOO 4 General purpose digital input output pin open drain VO SCL I C bus clock input output open drain High current sink only if IC Fast mode Plus is selected in the I O configuration register lo IOH 2 I O Handler input output 2 LPC11U37HFBD64 401 only PIOO 5 SDA IOH 3 11 H3 16 21 M HIA O PIOO 5 General purpose digital input output pin open drain VO SDA I C bus data input output open drain High current sink only if 12C Fast mode Plus is selected in the I O configuration register VO IOH 3 I O Handler input output 3 LPC11U37HFBD64 401 only PIOO_6 USB_CONNECT 15 H6 22 29 Bl PU I O PIOO 6 General purpose digital input output pin SCKO IOH_4 O USB CONNECT Signal used to switch an external 1 5 kO resistor under software control Used with the SoftConnect USB feature VO SCKO Serial clock for SSPO VO IOH 4 I O Handler input output 4 LPC11U37HFBD64 401 only PIOO 7 CTS IOH 5 16 G7 23 30 Bl PU JO PIOO 7 General purpose digital input output pin high current output driver l CTS Clear To Send input for USART VO IOH 5 I O Handler input output 5 LPC11U37HFBD64 401 only PIOO 8 MISOO0 17 F8 27 36 Bl EPU lO PIOO 8 General purpose digital input output pin CT16B0 MATO R IOH 6 y o MISOO Master In Slave Out for SSPO O CT16BO MATO Match output 0 for 16 bit timer 0 Reserved VO IOH 6 I O Handler input output 6 LPC11U37HFBD64 401 o

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