User manual
Contents
1. POlE RXGP POERXGSN Jj X4 120A E11 13 122A 4 RX4P PCIERXAN An j BA2 126A 6 POIE RXe P J A7 PCIEERXGON B17 POlEETX7N POE 84 Table 13 XMC P15 Connections _ PCIE RX5 1200 mio gt 4 9 2 gt 2 Olmljo wo gt 4 1 61911911 61611911 9115 65 99109151 5109 mre ns ADM XRC 5TZ User Manual Version 2 0 Page 20 ADM XRC 5TZ User Manual 4 10 XRM 10146 Interface The following tables provide the user with information on the pin out of the XRM IO146 when fitted to an ADM XRC 5TZ version card The signal names 1 N 1 etc are internal to the ADM XRC 5TZ The important mapping is between the Mictor pin and the FPGA pin Table 15 10146 Mictor Connector Pins 39 76 ADM XRC 5TZ User Manual Version 2 0 Page 21 ADM XRC 5TZ User Manual Samtec FPGAPin Signal 100 ACA P 34 9 72 AD42 N34 ME 122 AF41 P 36 c 124 AF42 N36 BEN 1206 AJ2 P 38 NEM 128 1 38 MM 130 AB37 P 40 132 AB38 N40 MEAE 136 40 P 42 MK 134 39 42 140 AM41 P 44 MEE 138 ANM N44 142. 13 2 6 3 Memory IMCH ACCS E 13 4 7 XRM B s anda Front Panel ta 14 4 7 1 XRM Signalling Voltage b statut xe a 14 4 7 2 Interface Standard Signals and 15 4 7 3 XRM Interface MGT 18 4 8 a 19 4 81 Pn4Signalliig Voltage 19 4 9 XIV GAMIEM AGE M 20 4 Prima P losin d l 20 4 10 AMMO TAG IMEC 52658848 21 9 2 quia ont b nsu 23 Gi Um a re ad 24 ADM XRC 5TZ User Manual Version 2 0 ADM XRC 5TZ User Manual Table of Tables Table 1 Local Bus Interface Signal List eene rotten tees 5 Table 2 Voltage and Temperature 8 Table IMGT Clock Connections aus ooo nieto tue eta ono 11 Table 5 XRM Bus Regional 12 Table User PPOATO Bahk Voltage S nr aa Ete Dl Renta ona dii 13 Table 7 I O Voltage 1
3. XRM_RX2N Ni 220 11 116A 222 42 XRMRX3N 1 224 JP43 Table 18 XRM HSSDC2A 5T2 Pinout ADM XRC 5TZ User Manual Version 2 0 Page 23 ADM XRC 5TZ User Manual 6 Revision History Revision Nature of Change 18 07 2008 Initial release 04082008 08 2008 11 Modified Modified SysMon voltage description for PCI VIO 3V0 voltage description for PCI VIO 3V0 a 08 2008 2 references to XRC 5T2 updated description for MCLK usage 31 08 2009 1 1 Added Front I O voltages 2 2 Added note on power estimation and current requirements 2 3 New section on PCI mode selection 2 6 New section on cooling requirements 4 2 1 Added diagram of flash organisation 4 2 1 1 New section on power up sequence 4 2 1 2 New section on One Time Configuration feature 4 3 1 New section on Automatic Temperature Monitoring 4 5 1 Added note on default LCLK rate 4 5 3 Note on PCle Clock availability 4 5 4 Note on MGT clock defaults ADM XRC 5TZ User Manual Version 2 0 Page 24
4. Note Either of these clocks can provide a programmable source for applications that do not use This requires the instantiation of a DUAL component within the FPGA To simplify the task a wrapper module is provided in the SDK The default rate for both USERMGT CLKA and USERMGT CLKB is 250MHz and is set on power up An alternative default rate can be stored in flash memory FlashAdr 0x404 2 ClockWord 15 0 FlashAdr 0x406 ClockWord 31 16 see the 1 5843034 01 datasheet for details of the programming clock word 4 5 5 MGT Clock An XRM module can provide an MGT GTP reference clock input for user specific applications Clock Name PCIE_REFCLK 4 AD3 Primary XMC 15 MGTs USERMGT_CLKA AK4 AK3 Primary XMC Pn15 MGTs C4 Front CN2 user MGTs USERMGT CLKB 4 Front CN2 user MGTs Table 4 MGT Clock Connections ADM XRC 5TZ User Manual Version 2 0 Page 11 ADM XRC 5TZ User Manual 4 5 6 XRM Global Clock Input The XRM interface provides a differential input to the User FPGA global clocking resources The default on board terminations are suitable for an LVDS clock 4 5 7 Regional Clocks The XRM interface provides 8 clock lines that can be either be used single ended or as 4 LVDS differential pairs These clocks are routed to Clock Capable inputs on the User FPGA providing access to its regional clock capabilities Each clock pair can be coupl
5. ADM XRC 5TZ User Manual Version 2 0 Page 15 ADM XRC 5TZ User Manual Signal 7 FPGAPin Samtec Pin FPGAPin Signal N21 Ma je 6 1 22 2 P21 MP 00 9 170 40 26 P27 44147027 N27 0 9 2 8922 pg 142 P41 R40 Co co ININ OO 02 86 32 90 2 1 298 100 CLK2 Poa AL42 0 j N34 CLK4 100 AC41 CLK4 101 402 0 X X 01 6 12100 0100 011012 0114 1100 G5 O 34 734 E 3 8 9 59 0699 1907 068 71 J XRMCLKNN MGTREFP 19 0590 8 11 72 8 5052 PXRM_PECLN 192 14 JXRMSCL XRM Js 6 JRESERVED XRM 7 P 117 8 XRMRXYP 11 XRM TX7 N XRM RX7 N Table 9 XRM Interface part 2 ADM XRC 5TZ User Manual Version 2 0 Page 16 ADM XRC 5TZ User Manual Signal FPGAPin SamtecPin FPGAPin Signal 59 APO Table 10 XRM Interface part 3 Z 92 92 922 922 92 9922 92 Ul 2 2 9 UI Z 219 o ojo xoi o1 O1 O1 O1 O1 O1 O1 O1 O1 I2 I2 S iS i2 I2 09 O02 Oo Co CO CO 1 1 1 Co cO CO H 1 O1 01 0 O ADM XRC 5TZ User Manual Ver
6. pairs and each pair is matched in length The worst case difference in trace length between any two pairs is 10mm Signal FPGA Pin AK12 AK13 AM28 AL29 Pn4Pin FPGAPin CC 2 CC AJ30 CC CC l6 8 ug ed 1 N O n2 2 8 2 2 4 0 12 14 16 18 24 26 28 30 60 64 Table 12 Pn4 to FPGA Assignments O Oo ox o1 oO1 O1 O1 O1 AAAI AIAI 02149240246246 25 5 NJOJOJ OO NTO WO O NJ O1 H O1 CO In Table 12 pins marked CC are clock capable and may be used to access the regional clocking resources in the FPGA 4 8 1 Pn4 Signalling Voltage The signalling voltage on the Pn4 is fixed at 3 3V ADM XRC 5TZ User Manual Version 2 0 Page 19 ADM XRC 5TZ User Manual 4 9 XMC Interface 4 9 1 Primary XMC Connector P15 The MGT GTP links connected between the user FPGA and the Primary XMC connector P15 are compatible with PCI Express and Serial RapidlO Depending upon the carrier card they may also be used for user specific applications GTP FPGA Pin Number AC2 PGIERXOP PCIERXON F AF2 7 n ARE p 5 1 b POE POTN 42 AEI 2 L POIE RO P AW f n PCIERXZN 9g PCIE TXS N
7. Board WSSCHPLHOM tp 4 4 1 i L A IA 5 4 2 micis dam dei 6 4 2 1 Board Control 6 422 6 ce a ID 4 3 EE 8 4 3 1 Automatic Temperature 9 4 4 dup cec 9 am Ee T m TT 9 44 2 FBO M 9 4 5 Cr 10 bone EON 10 AS 2 AEP CK Aa 11 4 58 PCle Reference ClOCK utut itum 11 454 USE MOT GIOCKS 11 4 5 5 Clock 202 11 4 5 6 JXRM 0 in a a bae t 12 5 7 ARM Regional IOGKS extus detenti 12 45 9 PA d T BU uum 12 4 65 90 PELGIOEk CET 12 4 6 SE A i ee 13 4 0 1 13 4 0 2 VONAGCS B neh ete ec Ra eee in te
8. DMA and Interrupts are given in the Software Development Kit SDK 131 0 I 3 0 lads_ lblast Iready Iwrite PCI Bus Bridge Control User FPGA 0 0 Idrea 13 0 Virtex5 Virtex4 LX25 LXT SXT FXT Idack_I 3 0 fhold fholda A Y Ireset Iclk VV Figure 2 Local Bus Interface Signal Typ Purpose Table 1 Local Bus Interface Signal List ADM XRC 5TZ User Manual Version 2 0 Page 5 4 2 Flash Memory ADM XRC 5TZ User Manual The ADM XRC 5TZ is fitted with two separate Flash memories one connected to the Bridge Control FPGA and the other to the User FPGA 4 2 1 Board Control Flash A 256Mb Flash memory Intel Numonyx PC28F256P30 is used for storing Vital Product Data VPD programmable clock parameters and configuration bitstreams for the User FPGA Access to this flash device is only possible through control logic registers The flash is not directly mapped onto the local bus Programming erasing and verification of the flash are supported by the ADM XRC SDK and driver Utilities are provided to load bitstreams into the flash These also verify the bitstream is compatible with the target FPGA ADM XRC 5TZ User Manual Version 2 0 Page 6 Vital Product Data VPD LCLK Word 15 0 LCLK Word 31 16 MCLK Word 15 0 MCLK Word 31 16 res
9. 38 package The card uses an FPGA PCI bridge developed by Alpha Data supporting PCI X and PCI This allows high performance PCI X PCI operation without the need to integrate proprietary cores into the FPGA A high speed multiplexed address data bus connects the bridge to the target user FPGA The card can also be fitted with a Primary XMC connector to provide high speed serial link connections to the user FPGA 1 1 Specifications Physically conformant to VITA 42 XMC Standard Physically conformant to IEEE P1386 2001 Common Mezzanine Card standard with XMC connector removed 84 PCle Serial RapidlO connections to User FPGA connector 8 additional MGT links to User FPGA via front panel adaptor High performance PCI and DMA controllers Local bus speeds of up to 80 MHz Six independent banks of 2Mx36 ZBT SRAM 48MB total User clock programmable between 31 25MHz and 625MHz Stable low jitter 200MHz clock for precision IO delays User front panel adapter with up to 146 free IO signals User rear panel PMC connector with 6 free IO signals Programmable I O voltage on front interface 1 8V 2 5V 3 3V Supports 3 3V PCI or PCI X at 64 bits ADM XRC 5TZ User Manual Version 2 0 Page 1 ADM XRC 5TZ User Manual 2 Hardware Installation This chapter explains how to install the ADM XRC 5TZ onto a PMC motherboard or carrier 2 1 Handling instructions Observe SSD precautions when handling the cards to preven
10. 4 Table 8 XHRMTriterlace iuris 15 XBRM nterface 2 ee eei tec eva eee 16 Table 10 XRM menaces 17 Table 11 XRM Iintertrace IMGT 5 18 2 ASSIONIMIONI Si 225 5 4 tit 19 Tables XMG PS GONNEGHOMS cues A 20 Table 14 10146 Mictor Connector Pins 1 38 21 Table 15 10146 Mictor Connector Pins 39 76 04600000 21 Table 16 10146 Mictor Connector Pins 77 114 22 Table 7 160146 Mictor Connector Pins 115 1592 metas eb e dette o res 22 Table 18 XRM HSSDO2ZA 512 28 23 Table of Figures Figure 1 ADM XRC 5TZ Block 4 Figure 2 Local 5 GR ud dua 5 Figure 3 Board Control Flash 6 Figure 4 Power Up Configuration 7 FIGUKe 9 Niere mic LE 9 FOUS G GIOCK SUCUT 0 T naf 10 ADM XRC 5TZ User Manual Version 2 0 1 ADM XRC 5TZ User Manual Introduction The ADM XRC 5TZ is a high performance PCI Mezzanine Card PMC designed for applications using the Virtex 5 FPGAs from Xilinx This card supports all Virtex 5 LXT SXT and FXT devices with the FFG17
11. 41 AR42 P46 142 ATA2 N46 222 152 AU42 P48 dd 150 41 48 97 AE40 CLK4 E 99 40 01 5 Table 16 10146 Mictor Connector Pins 77 114 Samtec FPGAPin Signal 20 146 50 148 AB36 N50 PEN 1565 OBO 2222 154 AD37 N52 160 9 54 NM 158 AG3B IN 54 164 0 56 162 AP40 N 56 EY 1681 ATIS 166 9 58 5 i 1723 60___ eu 170 8 60 NE 176 AN39 P 62 MK 147 AP88 N 82 180 7 64 178 AL37 N64 med 102 40 01 6 104 9 CLK7 i 5V i Table 17 10146 Mictor Connector Pins 115 152 ADM XRC 5TZ User Manual Version 2 0 Page 22 ADM XRC 5TZ User Manual 5 XRM HSSDC2A Interface ee rm number in _ Number Pin XRM TXOP AA2 1128 0 4 en 1 ees ma T2 112A CN25 P26 XRMIXIN 02 7 P25 R2 1168 CN217 6 49 5 TGP K2 116A 221 46 XRMDGN 12 223 P45 XRMRXOP Yi 1128 0 22 2 Wi 4 XRMRXIP Ui 112A 26 P22 XRMRXIN Vi 8 P23 2 P1 1168 218 2
12. A from flash on power up if a valid bit stream is detected in the flash Booting from flash will also configure the programmable clocks See Section 4 2 1 1 4 6 2 Bank Voltages Bank Voltage Cr Configuration I F 1 5 6 18 19 21 23 24 25 26 ZBT SRAM A EG Table 6 User FPGA I O Bank Voltages 4 6 3 Memory Interfaces The ADM XRC 5TZ has six independent banks of ZBT SRAM Each bank has a 36 bit datapath Data bits 85 32 are parity bits where bit 32 is associated with bits 7 0 etc The board will support higher capacity devices when they become available 4 6 3 1 Memory Clocking Each memory bank has its own clock output from the target FPGA To allow these clocks to be de skewed they are fed back into GCLK inputs on the FPGA An example of this clock de skewing method is shown in the memory application in the Alpha Data SDK ADM XRC 5TZ User Manual Version 2 0 Page 13 ADM XRC 5TZ User Manual 4 7 XRM Bus and Front Panel I O A major benefit of the ADM XRC series of boards that use the XRM Bus interface is the versatility of I O options that result The ADM XRC 5TZ maintains this interface and thus compatibility with a wide range of I O modules to suit many diverse needs Standard signals and power on the XRM interface use the 180 pin Samtec QSH series connector CN1 MGT links use the 28 pin Samtec QSE DP connector CN2 4 7 1 XRM Signalling Voltage The
13. ADM XRC 5TZ PCI Mezzanine Card User Guide Version 2 0 DATA ADM XRC 5TZ User Manual Copyright 2007 2009 Alpha Data Parallel Systems Ltd All rights reserved This publication is protected by Copyright Law with all rights reserved No part of this publication may be reproduced in any shape or form without prior written consent from Alpha Data Parallel Systems Limited Alpha Data Alpha Data 4 West Silvermills Lane 2570 North First Street Suite 440 Edinburgh 5BD oan Jose CA 95131 UK USA Phone 44 0 131 558 2600 Phone 408 467 5076 Fax 44 0 131 558 2700 Fax 866 820 9956 Email support alphadata co uk Email support alpha data com ADM XRC 5TZ User Manual Version 2 0 ADM XRC 5TZ User Manual Table of Contents MRO 8 M E 1 1 1 SPCCINCAOMNGS a DV 1 2 Madwar INSTA AOA a tahoe 2 2 1 Handling 11 a 2 2 2 Motherboard Carrier nennen 2 2 3 PCI Mode 2 2 4 Installing the ADM XRC 5TZ onto a PMC motherboard 2 2 5 Installing the ADM XRC 5TZ if fitted to an 2 2 6 Cooling RE uireme tt 3 51 d l g ad 3 At
14. Bus RefClk PCI X CLK Zero delay Bridge Config Buffer Coolrunner PLL 2 A a Bridge FPGA CLK VALX25 XTAL 25 0 MH REFCLK_200M 2 Ctl Osc Femto clock Local Bus 26 5625 MHz ICS843034 01 USERMGT CLKB XTAL USERMGT_CLKA PCle RefCIk 100 MHz 2 XRM MGTREF te XRM_CLKIN XRM_PECL User FPGA Virtex5 CLKO P A LX220T A CLKTTN XRM Pn4 Connector LX330T N Connector 2 Samtec CLK4 P A KEY CLK5 Global Clock Inputs P A Clock Capable I O CLK7 N MGT Clock Inputs Figure 6 Clock Structure 4 5 1 The Local Bus clock LCLK is generated from a 200MHz reference by a DCM within the bridge FPGA The minimum LCLK frequency determined by the DCM specification is 32MHz The maximum is 80MHz The LCLK frequency is set by writing DCM multiply amp divide values to the LCLOCK register in the bridge See SDK for details and example application The default LCLK rate is 40MHz and is set on power up An alternative default rate can be stored in flash memory FlashAdr 0x400 DCM Multiplier Value 1 FlashAdr 0x402 DCM Divider Value 1 ADM XRC 5TZ User Manual Version 2 0 Page 10 ADM XRC 5TZ User Manual Note If the user FPGA application includes a DCM driven by LCLK or one of the other programmable clocks the clock frequency should be set prior to FPGA configurati
15. C feature by setting SW1A to ON See Section 4 2 1 2 for more details on OTC 2 4 Installing the ADM XRC 5TZ onto a PMC motherboard Note This operation should not be performed while the PMC motherboard is powered up The ADM XRC 5TZ must be secured to the PMC motherboard using M2 5 screws in the four holes provided The PMC bezel through which the I O connector protrudes should be flush with the front panel of the PMC motherboard 2 5 Installing the ADM XRC 5TZ if fitted to an ADC PMC The ADM XRC 5TZ can be supplied for use in standard PC systems fitted to an ADC PMC carrier board The ADC PMC can support up to two PMC cards whilst maintaining host PC PCI compatibility If you are using a ADC PMC refer to the supplied documentation for information on jumper settings All that is required for installation is a PCI slot that has enough space to accommodate the full length card The ADC PMC is compatible with 5V and 3V PCI 32 and 64 bit and PCI X slots It should be noted that the ADC PMC uses a standard bridge to provide a secondary PCI bus for the ADM XRC 5TZ and that some older BIOS code does not set up these devices correctly Please ensure you have the latest version of BIOS appropriate for your machine ADM XRC 5TZ User Manual Version 2 0 Page 2 ADM XRC 5TZ User Manual 2 6 Cooling Requirements The power consumption of the ADM XRC 5TZ is highly dependent on the user FPGA application With large FPGA applications it is possi
16. USERCODE readable using JTAG 0x4144DEAD 4 4 JTAG A JTAG header 43 is provided to allow download of the FPGA using the Xilinx tools and serial download cables This also allows the use of ChipScope PRO ILA to debug an FPGA design 2Z42R2 amp O Figure 5 JTAG Header J3 The VCC supply provided on J3 to the JTAG cable is 3 3V and is protected by a poly fuse with a rating of 350mA 4 4 1 Scan Chain Options The devices in the scan chain can be altered for board test purposes using switch SW1C The normal position for SW1C is open off In this position four devices will be detected when the scan chain is initialised If SW1C is closed on the ZBT memories will be included in the scan chain 4 4 2 FBS The FBS signal is an input to the control logic and provides control of the cold boot process By default with no link fitted the control logic will load a bitstream from flash into the FPGA if one is present Shorting FBS to the adjacent GND pin will disable this process and can be used to recover situations where rogue bitstreams have been stored in flash ADM XRC 5TZ User Manual Version 2 0 Page 9 ADM XRC 5TZ User Manual 4 5 Clocks The ADM XRC 5TZ is provided with numerous clock sources as shown in Figure 6 below PCI PCI
17. ble that the board may dissipate more than 15W Although the board is designed to handle this the user must ensure that it is adequately cooled To prevent damage through over heating an on board system monitor will automatically reconfigure the User FPGA with a low power bitstream if the FPGA reaches 85 C or if the board reaches 70 C 100 C and 85 C respectively for Industrial grade devices The FPGA temperature may be measured using a software application or with Xilinx Chipscope and a JTAG cable oee Section 4 3 for further details of the on board system monitor 3 Software Installation Please refer to the Software Development Kit SDK installation CD The SDK contains drivers examples for host control and FPGA design and comprehensive help on application interfacing ADM XRC 5TZ User Manual Version 2 0 Page 3 ADM XRC 5TZ User Manual 4 Board Description The ADM XRC 5TZ follows the architecture of the ADM XRC series and decouples the target FPGA from the PCI interface allowing user applications to be designed with minimum effort and without the complexity of PCI design A separate Bridge Control FPGA interfaces to the PCI bus and provides a simpler Local Bus interface to the target FPGA It also performs all of the board control functions including the configuration of the target FPGA programmable clock setup and the monitoring of on board voltage and temperature ZBT SRAM and serial flash memory connect t
18. ed with 16 pairs of XRM bus signals as shown in Table 5 below XRM Clocks FPGA Bank XRM bus pairs 0 8 1 Pair 0 2 amp 3 Pair 1 17 32 4 amp 5 Pair 2 33 48 6 amp 7 Pair 3 49 64 Table 5 XRM Bus Regional Clocks 4 5 8 Rear Pn4 Clocks Two pairs of signals from Pn4 are connected to clock capable inputs that can be used for regional clocking of the remaining Pn4 signals See Table 12 for details 4 5 9 PCI Clocks The PCI Interface within the bridge FPGA requires a regional clock input for 66MHz PCI operation or a global clock input for PCI X To comply with the single load requirement in the PCI specification a zero delay clock buffer is used to route the PCI clock to the two different clock inputs The clock buffer has a PLL with a minimum input frequency of 24MHz potentially causing problems in applications that use the PCI 33MHz mode with a slow clock In this case the buffer can be bypassed to provide full PCI 33MHz compatibility ADM XRC 5TZ User Manual Version 2 0 Page 12 ADM XRC 5TZ User Manual 4 6 User FPGA 4 6 1 Configuration The ADM XRC 5TZ performs configuration from the host at high speed using SelectMAP The FPGA may also be configured from flash or by JTAG via header J3 Download from the host is the fastest way to configure the User FPGA with 8 bit Select MAP mode enabled This permits an ideal configuration speed of up to 80MB s The ADM XRC 5TZ can be configured to boot the User FPG
19. erved Length 7 0 Boot Flag 0 Bitstream 0 Length 23 8 Target FPGA Bitstream 0 B1 Length 7 0 Boot Flag 1 Bitstream 1 Length 23 8 Target FPGA Bitstream 1 failsafe 0 0000 0000 0 0000 0 0000 0400 0 0000 0002 0 0000 0404 0 0000 0006 0 0080 0000 0 0080 0002 0 0082 0000 0x013F FFFE 0x0140 0000 0 0140 0002 0x0142 0000 1 FFFE Figure 3 Board Control Flash Organisation ADM XRC 5TZ User Manual 4 2 1 1 Power Up Sequence If valid data is stored in the flash memory the bridge will automatically set the programmable clock generators and configure the User FPGA at power up This sequence can be inhibited by shorting the FBS pin on JTAG connector J3 to GND See the description of the FBS signal in Section 4 4 for further information Note If an over temperature alert is detected from the System Monitor the target will be reloaded with the alternate failsafe bitstream C Power Up Bitstream Valid Config Tgt FPGA Set LCLK Set MCLK Figure 4 Power Up Configuration Sequence 4 2 1 2 One Time Configuration OTC If One Time Configuration OTC is disabled switch SW1A is OFF the power up configuration sequence will repeat each time PCI reset is asserted If the OTC feature is enabled switch SW1A is ON t
20. he bridge will only set the clocks and configure the User FPGA at power up Once the sequence has completed it will not repeat at PCI reset Note OTC only stops the user FPGA being reconfigured at PCI reset If does not affect the manual reload function in the bridge control registers or the over temperature reload circuit 4 2 2 User FPGA Flash An ST M25P32 flash memory with SPI interface is connected to the User FPGA for the storage of application specific information ADM XRC 5TZ User Manual Version 2 0 Page 7 4 3 Health Monitoring The ADM XRC 5TZ has the ability to monitor temperature and voltage to maintain a check on the operation of the board The monitoring is implemented by a National Semiconductor LM87 and is supported by the Bridge FPGA control logic using FC ADM XRC 5TZ User Manual The Control Logic scans the LM87 when instructed by host software and stores the current voltage and temperature measurements in a blockram This allows the values to be read without the need to communicate directly with the monitor The following supplies and temperatures as shown in Table 2 are monitored Monitor Purpose User FPGA Core Suppl Bridge FPGA Core Suppl Memories User FPGA Memory I O Local Bus I O Config CPLD Core Suppl LM87 on die temperature for board ambient Table 2 Voltage and Temperature Monitors An application is provided in the SDK that permits the reading of the health monitor The typ
21. ical output of the monitor is shown below provided by the SV SMON program SysMon T1VO 1V2 T1V8 2V5 3V0 5V FPIO SysMon Int Temp User FPGA Temp ADM XRC 5TZ User Manual Version 2 0 Page 8 Space Base Adr Control Space Base Adr Reading Reading Reading Reading Reading Reading Reading lt lt 44 4 lt 4 W W Q 0 A 00900000 00400000 ADM XRC 5TZ User Manual 4 3 1 Automatic Temperature Monitoring At power up the control logic sets temperature limits and enables the over temperature interrupt in the LM87 If the OTC feature is disabled the limits and interrupt will be re set after a PCI reset If OTC is enabled the limits and interrupt will only be set once at power up The temperature limits are shown in Table 3 below _ ee User FPGA Board LM87 internal 100 C Table 3 Temperature Limits If any limit is exceeded the User FPGA is automatically reconfigured with a low power failsafe bitstream The purpose of the failsafe mechanism is to protect the card from damage due to over heating It is possible that the reconfiguration will cause the user application and possibly the host computer to hang There are three ways to determine if the failsafe bitstream has been loaded 1 Data bit 30 in the FPCTL control register will be set 2 All local bus reads from the user FPGA will return OXCAFEFABz where 2 Adr 2 3 The device
22. o the target FPGA and are supported by Alpha Data or Xilinx IP IO functionality is provided using XRM modules MGT links are connected through a SAMTEC QSE DP connector CN2 Remaining signals are connected through a 180 pin SAMTEC QSH connector CN1 Bridge Programmable XRM Memory B Config 32MB Clocks us 146 bit Front PCI X gt Front Pn1 PCI64 66 User FPGA MGT XRM Pn2 a Bridge Control FPGA Local Bus 32 bit x8 Pn3 Virtex4 LX25 Virtex5 Serial Flash LXT SXT FXT Pn4 Rear I O 6 bit SRAM 15 PCle Serial RapidlO x8 ZBT 8MB System ZBT ZBT ZBT ZBT JTAG Monitor ae SRAM SRAM SRAM SRAM LM87 8MB 8MB 8MB 8MB Figure 1 ADM XRC 5TZ Block Diagram ADM XRC 5TZ User Manual Version 2 0 Page 4 ADM XRC 5TZ User Manual 4 1 Local Bus The ADM XRC 5TZ implements a multi master local bus between the bridge and the target FPGA using a 32 bit multiplexed address data path The bridge design is asynchronous and allows the local bus to be run faster or slower than the PCI bus clock to suit the requirements of the user design The local bus runs at 40 by default but this can be altered to different frequencies between 32MHz and 80MHz Full details of the local bus operation including timing constraints
23. on 4 5 2 REFCLK In order to make use of the IODELAY features of Virtex 5 a stable low jitter clock source is required to provide the base timing for tap delay lines in each IOB in the User FPGA The ADM XRC 5TZ is fitted with a 200MHz LVPECL LVDS optional oscillator connected to global clock resource pins This reference clock can also be used for application logic if required 4 5 3 PCle Reference Clock A 100MHz PCle reference clock input from the Primary XMC connector Pn15 is connected to one of the dedicated MGT clock inputs on the user FPGA See Table 4 for details of the MGT clock connections Note This clock is not generated on board It is only available if the carrier provides it and connector Pn15 is fitted 4 5 4 User MGT Clocks A programmable low jitter clock source is provided by an ICS843034 01 FemtoClocks frequency synthesiser The synthesiser has two source crystals one at 26 5625MHz for Fibre Channel applications and another at 25 0MHz suitable for PCle Gigabit Ethernet etc The synthesiser also has two clock outputs USERMGT CLKA is connected to an MGT clock input on the top half of the user FPGA It may be used as an alternative to the PCle reference for the MGTs connected to the Primary XMC USERMGT CLKB is connected to an MGT clock input on the bottom half of the user FPGA It may be used as the reference for the front user MGTs See Table 4 for details of the MGT clock connections
24. signalling voltage on the XRM connector and User FPGA Banks 11 13 15 amp 17 is selectable by jumper J2 XRM I O voltage Link p1 amp p2 Link p3 amp p4 Link p5 amp p4 Table 7 XRM I O Voltage Selection ADM XRC 5TZ User Manual Version 2 0 Page 14 ADM XRC 5TZ User Manual 4 7 2 XRM Interface Standard Signals and Power The XRM interface is implemented on CN1 a 180 pin Samtec connector type QSH with the pin out as detailed in tables Table 8 to Table 10 In turn the signals that connect to CN1 are provided in the main from four banks of the User FPGA Banks 11 13 15 8 17 These banks share a common VCCO that can be 1 8V 2 5V or 3 3V powered selectable with a jumper link on J3 Signal 7 FPGAPin SamtecPin FPGAPin Signal E N3 5 6 19 JP 9 7 18 0 NS 97 49 90 8 B R37 1 12 98 6 2 7 9 5 16 8 8 7 1 8 0 9 898 12 SERID 0 3 RESERVED 859 5 46 V 97 7 8 VBAT 7 9 0 9 51 552 XRMEVECION 9 53 4 2 PRESENCE K88 5 6 1 XRM_TCK 58 5 8 XRM TRST XRM 58 9 60 Table 8 XRM Interface part 1 012 0 2 0 2 0 2 41 4 Z 9242 1 1 41 1 1011 1 01 41 0 1 1 21012
25. sion 2 0 Page 17 ADM XRC 5TZ User Manual 4 7 3 XRM Interface MGT Links Eight lanes of user MGT GTP links are routed to the interface Lanes 0 6 are routed through Samtec QSE DP connector CN2 Lane 7 is routed through the Samtec QSH connector CN1 FPGA GTP Pin Number AA2 128 1 XRMTXON v2 j 3 XRMERXO P Y cn c 7 23 1 w J 4 ies 01 8 21 2112 12A 5 XRMTX N U2 XRMRXIP Ut 1 6 vt Jj 8 XRMTXON P2 19 XRMROP Pt Jj 18 XRM RX N J 20 XRMTIXSN t2 23 XRM RX P 22 J 24 TX4P 2 1208 9 XRMTXAN H2 Jj tf J XRMRXAP Ht Jj 10 XRMRXAN Jj 12 XRMIXSN E2 Jj 15 XRMRXSP Et Jj t4 Jj 16 J XRMTXGN 82 2 XRMRXGP A2 26 28 B6 124A CN1 117 B5 CND TI9 XRMRXZP A5 0 1 118 XEM RX N A4 0 120 Table 11 XRM Interface MGT Links ADM XRC 5TZ User Manual Version 2 0 Page 18 4 8 Pn4 ADM XRC 5TZ User Manual Up to 3 pairs of differential or 6 single ended signals are available on Pn4 and are sourced from Bank 10 of the User FPGA All of the signal traces are routed as 100 Ohm differential
26. t damage to components by electrostatic discharge Avoid flexing the board 2 2 Motherboard Carrier requirements The ADM XRC 5TZ is a 3 3V only PCI device and is not compatible with systems that use 5V signalling The ADM XRC 5TZ must be installed in a PMC motherboard or carrier that supplies 5 0V and 3 3V power to the PMC connectors Ensure that this requirement is satisfied before powering it up 12V and 12V may also be required for certain XRM modules The current requirements on each power rail are highly dependent on the user FPGA application A power estimator spreadsheet is available on request from Alpha Data This should be used in conjunction with Xilinx power estimation tools to determine the exact requirements for each power rail 2 3 PCI Mode selection Although the ADM XRC 5TZ automatically detects whether the board is connected to a PCI or PCI X bus the default initial type is determined by Switch SW1D If SW1D is OFF the bridge FPGA will be configured for PCI X mode after power up and altered at PCI reset if a PCI bus is detected If SW1D is ON the bridge FPGA will be configured for PCI mode after power up and altered at PCI reset if a PCI X bus is detected In most systems it is not essential to alter the position of this switch However systems with a PCle interface in the User FPGA should load the user bitstream in to flash memory set SW1D to match the bus type and enable the One Time Configuration OT
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