SMT364 User Manual - Sundance Multiprocessor Technology Ltd.
Contents
1. ack LOC R5 SHBA NET shba LOC 012 NET shba dk LOC E12 NET shba lt 59 gt LOC T1 NET shba 58 LOC shba 57 LOC R3 NET shba 56 LOC R2 shba 55 LOC R1 NET shba lt 54 gt LOC P6 shba 53 LOC P5 NET shba lt 52 gt LOC P4 NET shba lt 51 gt LOC NET shba 50 LOC P2 NET shba lt 49 gt LOC P1 NET shba 48 LOC N6 shba 47 LOC 5 NET shba 46 LOC N4 shba 45 LOC NET shba lt 44 gt LOC N2 shba 43 LOC N1 NET shba lt 42 gt LOC M6 NET shba lt 41 gt LOC M5 NET shba lt 40 gt LOC M4 shba lt 39 gt LOC NET shba lt 38 gt LOC M2 NET shba lt 37 gt LOC M1 NET shba lt 36 gt LOC L2 NET shba lt 35 gt LOC L3 NET shba lt 34 gt LOC L4 NET shba lt 33 gt LOC L5 Page 21 of 37 NET shba lt 32 gt LOC NET shba lt 31 gt LOC NET shba lt 30 gt LOC NET shba lt 29 gt LOC NET shba lt 28 gt LOC Le NET shba lt 27 gt LOC Ke NET shba lt 26 gt LOC K5 NET shba lt 25 gt LOC J5 NET shba lt 24 gt LOC J1 NET shba lt 23 gt LOC NET shba lt 22 gt LOC NET shba lt 21 gt LOC2. A1 T NET freq s clock adc LOC A1 NET freq np load CD LOC D1 CH NET freq np load adc LOC B1 8 NET freq master reset CD LOC 1 6 freq master reset LOC D1 6 NET freq sel adc CD lt 1 gt LOC E1 Ps NET freq sel adc CD 0 LOC E1 e NET freq sel adc lt 1 gt LOC F41 8 NET freq ck sel adc lt 0 gt LOC D21 i MISC NET ttls lt 3 gt LOC 15 NET ttls lt 2 gt LOC C15 NET ttls lt 1 gt LOC B15 NET lt 0 gt LOC D15 NET pxi trig4 LOC D18 Version 1 0 NET pxi trig3 LOC 21 pxi trig2 LOC C22 NET pxi trig1 LOC E18 NET pxi LOC C48 NET nreset LOC V12 NET leds 3 LOC F14 NET leds 2 LOC E15 NET leds 1 LOC A16 NET leds 0 LOC B16 NET iiofs lt 2 gt LOC 21 NET iiofs lt 1 gt LOC 20 NET iiofs 0 LOC W20 NET conf init LOC AA19 NET conf din LOC V18 NET clock LOC D11 NET adc trig CD LOC T21 NET adc trig AB LOC T2 COMMPORT A NET cp4 stb LOC A7 NET cp4 req LOC NET cp4 LOC D7 NET cp4 data 7 LOC D8 NET 4 data 6 LOC C8 NET cp4_data lt 5 gt LOC B8 NET cp4_data lt 4 gt LOC A8 NET cp4_data lt 3 gt LOC E9
3. H SUNDANCE 5 At power up and on reset At power up the FPGA is not configured and is waiting for a bit stream to be loaded By fitting Jumper J1 Figure 8 Connector Location it will allow the bit stream stored into the PROM to be loaded into the FPGA at power up and after every TIM reset If J1 is not fitted nothing happens This condition is useful when needing to configure the FPGA via JTAG Also at power up and on a carrier board reset signal the SMT364 expects receiving a dummy ComPort word any value and sends one back containing the Firmware version number It is a way of checking that the firmware is latest and that the board is responding and ready to work The format of that ComPort word is as follow OxFF364Fxy which means FPGA firmware version x y Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Version 1 0 Page 24 of 37 SMT364 User Manual Connector position J6 External J12 Externa J1 amp LEDs0 3 lriggerC amp D J4 JTAG J4 TTL I Os D Lt ed Bier 3 J13 Ext JiZ Clk A amp B 11 Ext A amp B Clk C amp D A C55 J2 SHBA J3 SHBB R3H R27 6291625 R26 RS 2 4 E J aoa J2 SHBA Ch A amp B 1 co SCH 2 211620 Ci ca J10 J i KH MEE Ch
4. NET shba lt 20 gt LOC H1 NET shba lt 19 gt LOC NET shba lt 18 gt LOC NET shba lt 17 gt LOC NET shba lt 16 gt LOC Je NET shba lt 15 gt LOC H5 NET shba 14 LOC G1 NET shba lt 13 gt LOC G2 NET shba 12 LOC NET shba lt 11 gt LOC NET shba 10 LOC F1 NET shba lt 9 gt LOC F2 NET shba lt 8 gt LOC NET shba lt 7 gt LOC F4 NET shba 6 LOC G5 NET shba lt 5 gt LOC F5 NET shba 4 LOC 1 NET shba lt 3 gt LOC E2 NET shba 2 LOC NET shba lt 1 gt LOC E4 NET shba lt 0 gt LOC D1 SMT364 User Manual Version 1 0 SHBB NET shbb clk1 LOC F13 NET shbb LOC B11 H NET shbb lt 59 gt LOC T22 NET shbb lt 58 gt LOC P17 NET shbb lt 57 gt LOC R18 NET shbb lt 56 gt LOC R19 NET shbb lt 55 gt LOC R20 NET shbb lt 54 gt LOC R21 NET shbb 53 LOC R22 NET shbb lt 52 gt LOC P19 NET shbb lt 51 gt LOC P20 NET shbb lt 50 gt LOC P21 shbb lt 49 gt LOC P22 NET shbb lt 48 gt LOC P18 NET shbb lt 47 gt LOC N18 NET shbb lt 46 gt LOC N19 NET shbb lt 45 gt LOC N20 NET shbb lt 44 gt LOC N21 NET shbb lt 43 gt LOC N22 NET shbb lt 42 gt LOC N17 NET shbb lt 41 gt L
5. V9 NET adcb data 13 2 LOC NET adcb_data lt 12 gt LOC U9 NET adcb data 112 LOC V8 adcb data 102 LOC Y8 NET adcb data 9 W8 NET adcb data 8 LOC AB8 NET adcb data 7 LOC AA8 NET adcb data 6 LOC YQ NET adcb data 5 LOC W9 NET adcb data 4 LOC ABQ adcb data 3 LOC AA9 NET adcb data x2 LOC Y10 adcb data 1 LOC W10 NET adcb data 0 LOC V10 ADCA NET adca gclk LOC Y11 NET adca LOC AB4 adca ovr LOC W7 adca data 13 LOC AA4 NET adca data 12 LOC Y4 NET adca_data lt 11 gt LOC NET lt 10 gt LOC 5 NET adca data 9 W5 NET adca data 8 LOC V7 NET adca data 7 LOC V6 NET adca data 6 LOC 5 NET adca_data lt 5 gt LOC 5 NET adca data 4 LOC Y6 NET adca lt 3 gt LOC 6 adca data 2 LOC AB6 Page 19 of 37 SMT364 User Manual NET adca_data lt 1 gt LOC AA6 NET adca lt 0 gt LOC CLOCK SYNTHESIZERS freq s load adc CD LOC C1 SCH NET freq s load adc LOC A1 8 freq s data adc CD LOC B1 NET freq s data adc LOC B1 NET freq s clock adc CD LOC
6. _ _ Ces S Ceas There is one external Trigger signal pair of ADCs Channels and B are coupled together So are Channels C and D Each trigger signal can be active high or low Version 1 0 30 of 37 SMT364 User Manual Data routes can also be configured vie Register Ox1 The following diagram shows all the possibilities Data go through a pipeline and can be added with each other Channel A 1 t Pipe Channel B 1 Pipe Pipe Pipe gt Pipe Data Flow B E Channel 2 Channel D Pipe 0 Pipe Data Flow D Figure 10 Data routing Version 1 0 Page 31 of 37 SMT364 User Manual Register 0x2 ADCC and ADCD Selection Modes and Decimation factors oma 8 CERS CECR an CERS CCS om 77 Decimation Factor of 0 default value does not have any effect on the data flow When it is set to 1 one sample out of two is trimmed out When it is set to 2 one out of three is trimmed out and so on The maximum value is 31 Version 1 0 32 37 SMT364 User Manual Channel selection O0 Channel disabled 01 216 bit counter on clock ADCA 10 Channel A two s complement en
7. to have external trigger signal synchronised to the sampling clock This external trigger also goes thought 7 latch stages Communication Ports ComPorts SMT364 provides 4 physical ComPorts 0 1 and 4 The default bit stream provided implements ComPort 4 Input at reset to load control registers A physical connection to ComPort 0 1 or 2 Output at reset is therefore necessary to an SMT365 for instance Please report to the part dealing with ComPorts Communication Ports ComPorts in this document for more details External triggering Two external trigger connectors J6 and J12 see Figure 8 Connector Location are available on the board to trigger converters from an external source The selection is made via a control register where channel selection can also be set There is one trigger per pair of ADC channels Triggering consists in enabling or stopping the converters This is available and accurate as long as the triggering signals are synchronised on the sampling clock Triggering signals can be set as active high or low in via the control register Each trigger input is clamped to 3 3 and Ground to avoid damaging the FPGA l Os This is achieved by using single diodes BAV99 These diodes can support as maximum 200mA of forward current and 70 Volts of reverse voltage It is to the customer to consider this when building a system using an SMT364 LEDs oeven LEDs Figure 8 Connector Location a
8. cp4 data 2 LOC F9 NET 4 data 1 LOC D9 NET 4 data 0 LOC NET cp4 ack LOC COMMPORT 3 NET cp3 stb LOC V19 NET cp3 req LOC V22 Page 20 of 37 NET cp3 LOC V20 cp3 data 7 LOC T20 cp3 data 6 LOC T19 NET cp3 data 5 LOC U22 NET cp3 data 4 LOC 021 NET cp3 data 3 LOC U20 NET cp3 data 2 LOC U19 NET cp3 data 1 LOC T18 NET cp3 data 0 LOC U18 cp3 LOC V21 COMMPORT 1 NET cp1 stb LOC C12 1 req LOC B13 NET cp1 LOC B12 NET cp1_data lt 7 gt LOC C13 NET cp1 data 6 LOC 013 NET cp1_data lt 5 gt LOC E13 NET cp1 lt 4 gt LOC E14 cp1 data 3 LOC A14 NET cp1 data 2 LOC B14 NET cp1 data 1 LOC C14 NET cp1 lt 0 gt LOC D14 NET cp1 ack LOC A13 COMMPORT 0 NET stb LOC req LOC T5 NET LOC T4 cpO data 7 LOC 01 NET cpO data 6 LOC U2 NET cpO data 5 LOC V1 NET lt 4 gt LOC V2 NET cpO data 3 LOC NET cpO data 2 LOC U4 SMT364 User Manual H Version 1 0 cp0_data lt 1 gt LOC 1 data 0 LOC W2
9. 5 001 2 010 011 4 100 6 101 8 Version 1 0 Page 28 of 37 SMT364 User Manual 110 or 12 111 See ICS8430 01 datasheet for more information performance Jitter etc The following diagram shows how clock signals can be routed on the PCB AC or DC AC or DC coupling coupling 2xAD6645 ADCs 14 bit 105MSPS 52 pin LQFP 30 I O pins 28 bit data ADC A ADC B 46 Clock feedbacks Xilinx FPGA 4 Clock synihe LO LO94 AT sizer Virtex Il FG456 ud Li O a e BUT XC2V1000 6 rae Fay Econ 0 Clock synthe 324 5 sizer 1 5V Core lt 3 30 I O pins 28 bit data ADCD g Clock feedbacks C and D 2xAD6645 ADCs 14 bit 105MSPS 52 pin LQFP RF RF transformer transformer Figure 9 Clock Routing The skew between ADC clock signals is negligible which means that samples coming from both converters can be considered as synchronised when Bit26 and Bit2 are the same Version 1 0 29 of 37 SMT364 User Manual Register 0x1 Channel data routing Triggers oma Ces Cen _ _ ma Ces 7 CCS omm 2 7 _ _
10. default configuration mode is from a PROM which contains the standard modes of operation as described in this document An on board LED indicates that the FPGA is configured Both devices FPGA and PROM are in the JTAG chain Four Communication links ComPorts following the Texas Instrument C4x standard are connected to the FPGA and will be used to receive control words or for other purpose They can achieve transfers at up to 20Mbytes s Two full SHB connectors 60 pin are accessible from the FPGA Both are output only and carry samples from ADCs There are two ADC data flows per SHB connector Please refer to the SHB specifications for more details about ways connectors can be configured Both SHB can be implemented as either two 16 bit interfaces or a single 32 bit interface In the case of a 32 bit interface both ADCs must receive the same sampling clock signal Four LEDs are driven by the FPGA Four LVTTL I Os for general purpose are also available No clamping diodes to 3 3 Volts and ground are available on the board to avoid damaging pads on the FPGA It is therefore to the customer to make sure the signals connected to these I Os are LVTTL and don t show overshoots External Clock trigger and analogue input signals are all single ended External connections to the board are all 50 Ohm terminated External triggers have clamping diodes to 3 3V and to Ground to avoid damaging the FPGA they are connected to A global reset si
11. 0x0 Clock management 26 Register 0x1 Channel data routing 29 Register 0 2 ADCC and Selection Modes and Decimation factors 31 Register 0x3 and ADCB Selection Modes and Decimation factors 33 Register OxD FPGA Global 35 Register Serial Interfaces 36 IVE FOS ACK AG eg 37 Table of figures FOUG T BIOCK RI Ce E 7 Figure 2 FPGA UNS ATOM 9 Figure CommPeort interface data path 13 Figure 4 SHB interface structure 4 13 Figure S5 ADC nelle 15 Figure 6 FFT ADC Channel On board clock 16 Figure 9 eor ne E 17 Figure 10 Connector el de ME 24 Figure 11 Clock DEE 28 Contacting Sundance You can contact Sundance for additional information by sending email to support sundance com Notes SMT364 denotes in this document 5 7364 The board in available in two options or DC coupled inputs ADC It is to be specified when placing an ordering SHB stands for Sundance High speed Bus ComPort denotes an 8 bit communication port following the C4x standards Version 1 0 Page 5 of 37 SMT364 User Manual Precautions In order to guarantee that the SMT364 functions correctly and to protect the module from damage the follo
12. 250 MHz External Clock DC coupled input Requires a External clock signal centered around OV Minimum voltage 0 2 Volt peak to peak minimum Maximum voltage 3 3 Volts Minimum voltage 3 3 Volts LVTTL 3 3 Volts format connected to 3 3V FPGA Clamp diodes to 3 3V and Ground Maximum sampling frequency Figure 5 ADC Performance Signal format Version 1 0 Page 16 of 37 SMT364 User Manual The following graphs gives the average FFT of sixteen 16K FFTs processed after capturing data from Channel B The on board sampling frequency set to 105 MHz A 21MHz sine signal is fed to the board The test has been performed without any input filter which explains the second peak due to harmonics at all and with a 35dBc harmonic performance signal generator lol x EE Edit Window Help FFT PLOT CHANNEL 0 20 A0 DU AMPLITUDE dB Seit 100 Malas 1 2 S d 8 ANALOGUE INPUT FREQUENCY Mrz S mu Figure 6 FFT ADC Channel On board clock Similar results are obtained when using an external clock It is recommended to use a low jitter clock and a filter on the ADC inputs They indeed have a large input bandwidth and therefore allow a high level of harmonics in The SMT6600 package provided with the SMT364 contains a documentation dealing with performance It shows some captures and FFT graphs at different frequencies Version 1 0 17 of 37 SMT364 User
13. Manual SHB pinout Signa Pn Sem cg ee 2 o _ owm e oo on Laf e o _ ag af we o _ e e sg vx 6 zb o zi ams ow ab e 7 pen ab e paco ore oer e was mmm af o al x a owes e _ oa ef mm _ ef mua mm os s ows oswwew me al nw all ws pm el Team Figure 7 SHB Pinout This standard is implemented using SAMTEC QSTRIP 0 50mm Hi speed connectors To improve electrical performances a ground plane is embedded in each QSTRIP connector For long distances micro coax ribbon cable is used to connect 2 QSTRIP connectors Version 1 0 SHB interface be 8 16 32 bit wide Page 18 of 37 SMT364 User Manual The default FPGA firmware implements 2 16 bit interfaces FPGA Pinout IHHHHHHHHHHHHHHHHHHHHHHHHHHHHHHBI Constraint File Virtex 11 for SMT364 Author Philippe ROBERT Date 23 07 2002 Version 1 0 Original draft Date 09 09 2002 Version 1 1 CP1 removed and Clock synthesizer changed Date 23 07 2002 Version 1 0 FloorPlanner Version 1 1 01 04 03 pinout reviewed Version 1 2 28 04 03 CommPort 1 and 4 added Sundance Technology THHHHHHHHHHHHHHHHHHHHHHBHHHHHHHHI Start of Constraints extracted by F
14. OC M17 NET shbb lt 40 gt LOC M18 NET shbb lt 39 gt LOC M19 NET shbb lt 38 gt LOC M20 NET shbb lt 37 gt LOC M21 NET shbb lt 36 gt LOC L22 NET shbb lt 35 gt LOC L21 NET shbb lt 34 gt LOC 120 shbb lt 33 gt LOC 119 NET shbb lt 32 gt LOC 118 NET shbb lt 31 gt LOC L17 Page 22 of 37 NET shbb lt 30 gt LOC K22 shbb lt 29 gt LOC K21 shbb lt 28 gt LOC K20 NET shbb lt 27 gt LOC K19 shbb lt 26 gt LOC K18 shbb lt 25 gt LOC K17 shbb lt 24 gt LOC J22 shbb lt 23 gt LOC J21 shbb lt 22 gt LOC J20 NET shbb lt 21 gt LOC J19 NET shbb lt 20 gt LOC J18 NET shbb lt 19 gt LOC J17 NET shbb lt 18 gt LOC 22 NET shbb lt 17 gt LOC H21 NET shbb lt 16 gt LOC H20 NET shbb 15 LOC H19 NET shbb lt 14 gt LOC G22 NET shbb 13 LOC G21 NET shbb 12 LOC G20 NET shbb lt 11 gt LOC G19 NET shbb lt 10 gt LOC H18 NET shbb 9 LOC G18 NET shbb 8 LOC F22 NET shbb 7 LOC F21 NET shbb lt 6 gt LOC F20 NET shbb lt 5 gt LOC F19 NET shbb lt 4 gt LOC E22 NET shbb lt 3 gt LOC E21 shbb lt 2 gt LOC E20 NET shbb lt 1 gt LOC E19 NET shbb lt 0 gt LOC D22 SMT364 User Manual
15. SMT365 or SMT365E or SMT374 it comes with Pegasus application and a 3L application
16. SUNDANCE 5 SMT364 User Manual Certificate Number FM 55022 User Manual QCF42 Version 3 0 8 11 00 Sundance Multiprocessor Technology Ltd 1999 Version 1 0 Page 2 of 37 SMT364 User Manual Revision History Date Comments Engineer Version 29 10 03 External trigger specifications corrected PSR 12 05 04 Power Consumption detailed Version 1 0 Page 3 of 37 SMT364 User Manual Table of Contents avida 2 Table OF Contehls EE 3 HE feel E EN 4 d O iR NRI 4 Kies 4 2 len EE 5 oume Ge Ser EE 6 Diagram EE e E 7 PGC IS SUAS DESCHDUON EE 8 e E EE 9 AE Let Mee EE 9 Ressource 9 EE 10 Clock nn EN e En EE 10 oundance High speed BUS SHB E 10 Communication Ports COMPOMS EE 11 z idaciligeor emwc HET 11 DEENEN 11 amp 12 HEV AIS Let Lee 12 Communication Ports LE e un Ee CH ET 12 Sundance High speed Bus GHP 13 Communication links implemented on the 5 64 13 For more details about ComPorts and GHP 14 ADC neige ne 15 SID DIMOU NETT 17 RE OUI EEN 18 on RT EE 23 O EE 24 Operating e CEET 25 Version 1 0 4 37 SMT364 User Manual zi 25 General e UE ME EC 25 ENEE MR 25 ele Ende 26 Register
17. annel GP ka Channel C CBS E mio T ial aes RS 1 Ri EGGS re hb HET wo zm H H4B B g w E EVER H Sie C4 i Hei d E D 114 J8 Channel B J9 Channel D Figure 8 Connector Location Version 1 0 Page 25 of 37 SMT364 User Manual The diagram below gives the position and the meaning of the connectors that the customer is likely to use Operating conditions Safety The module presents no hazard to the user EMC The module is designed to operate within an enclosed host system that provides adequate EMC shielding Operation within the EU EMC guidelines is only guaranteed when the module is installed within an appropriate host system The module is protected from damage by fast voltage transients introduced along output cables from outside the host system Short circuiting any output to ground does not cause the host PC system to lock up or reboot General Requirements The module must be fixed to a TIM40 compliant carrier board SMT364 module is a range of modules that must be supplied with a 3 3v power source In addition to the 5v supply specified in the TIM specification these new generation modules require an additional 3 3v supply to be presented on the two diagonally opposite TIM mounting holes The lack of this 3 3v power supply should not damage the module although it will obviously b
18. ce implemented into the FPGA DATA 000 31 Xo 26 32 2 NU J D A Control Logic and Status CLK WEN FEQ ACK Figure 4 SHB interface structure Communication links implemented on the SMT364 The SMT364 provides 4 ComPort links They are given the numbers 0 1 3 and 4 The default firmware provided with the board implements ComPort4 as a control Port x SHB A Version 1 0 14 of 37 SMT364 User Manual register communication port which means that every control register word has to be sent to ComPort4 on the SMT364 to be received The board also connects two full SHB connectors 60 bits to the FPGA The FPGA implements two 16 bit or one 32 bit unidirectional transmitter only interfaces per SHB connector to send out samples coming from ADCs For more details about ComPorts and SHB The following link Will give you more information External Interface User manual pdf Version 1 0 Page 15 of 37 SMT364 User Manual ADC Performance Analogue inputs 1 1 Volts peak to peak AC coupling Maximum voltage 2 2 Volts peak to peak DC coupling Gain 1 Specify ADC coupling when placing an order No anti aliasing filter on the board It is to the user to set one up if required Bandwidth Input transformers AC option 2 775 MHz Input opamps DC option 0 320 MHz A to D converters 0
19. coding i e samples go straight through as ADCs output samples in two s complement 14 bit format 14 bit samples coming from the ADC are extended to 16 bit on SHBA Bit13 is copied onto Bits14 and 15 11 Channel A binary encoding Binary conversion consists in inverting the MSB of each sample This operation introduces a DC offset of half the full scale which can be removed by subtracting 8192 decimal of each sample Version 1 0 Page 33 of 37 SMT364 User Manual Register 0x3 ADCA and ADCB Selection Modes and Decimation factors oma OSS omm 788 omm _ _ om 27777 T A Decimation Factor of O default value does not have any effect on the data flow When it is set to 1 one sample out of two is trimmed out When it is set to 2 one out of three is trimmed out and so on The maximum value is 31 Version 1 0 Page 34 of 37 SMT364 User Manual Channel selection O0 Channel disabled 01 216 bit counter on clock ADCA 10 Channel A two s complement encoding i e samples go straight through as ADCs output samples in two s complement 14 bit format 14 bit samples coming from the ADC are extended to 16 bit on SHBA Bit13 is copied onto Bits14 and 15 11 Channel A binary encoding Binary conversion consists in inverting the MSB of each sample This operation introduces a DC offset of half the full scale which can be removed by subtracting 8192 decimal of each sa
20. e inoperable prolonged operation under these circumstances is not recommended 5 1364 is compatible with all Sundance TIM carrier boards It is a 5v tolerant module and as such it may be used in mixed systems with older TIM modules carrier boards and modules It is anyway recommended to use the SMT364 connected to SHB TIM module such as SMT365 SMT365E or 5 374 in order to get better transfer performance The external ambient temperature must remain between 0 and 40 C and the relative humidity must not exceed 95 non condensing Power Consumption The power consumption of this TIM is dependent on the operating conditions in terms of core activity and I O activity The maximum power consumption is 10 95W which is 7OOmA under 12Volts 180mA under 5Volts and 500mA under 3 3Volts Version 1 0 26 of 37 SMT364 User Manual Register settings Register 0 0 Clock management Version 1 0 Page 27 of 37 SMT364 User Manual 9 B NM KR mm mam p Clock synthesizer N divider Bit2 ADC CD Clock synthesizer divider Bit ADC CD Clock synthesizer divider ADC CD Clock synthesizer divider Bit2 ADC AB Clock synthesizer divider ADC AB Clock synthesizer divider Bit0 ADC AB Fsynthesizea M N MHz With 500 lt M lt 250 binary encoding and can take one of the following values 1 000 1
21. ersion 1 0 Block Diagram Architecture Page 7 of 37 The following diagram shows the architecture of the SMT364 SMT364 User Manual 3 Power J2 Bottom Primary TIM supply Connector LEDs 2x CommPorts SDLs 1 amp 4 configured LED 9 n On board Oscillator 50 2 5 12 or DC DC 4 LEDs or coupling coupling 4 LVTTL I O pins FPGA PROM e 2xAD6645 ADCs A B T f 28 bit data 1 4 14 bit 105MSPS Clock feedback 52 pin LQFP 6 pin JTAG _ TT TTT TTI Xilinx FPGA leader Virtex Il FG456 Clock 2xClock Filler XC2V1000 4 parameters synthesizers Clock 2 Sundance High speed 120 I O pins 324 I O Pins Clock selection Multiplexer Filter Bus connector 2 x 60 bits 1 5V Core 3 3V I O 30 pins 28 bit data 2 06645 ADCs and D 14 bit 105MSPS 46 Clock feedback 52 pin LQFP S e AC or DC AC or DC p coupling coupling EQ 3 8 N X CN J1 Top Primary Connector 2x CommPorts SDLs 0 amp 3 Figure 1 Block Diagram Connections to the outside world are greyed out Option to the board Main parts of the board are descr
22. gnal is mapped to the FPGA from the top TIM connector to reset the FPGA and reload the FPGA Version 1 0 Page 9 of 37 SMT364 User Manual Virtex FPGA What the FPGA does SMT364 is populated with a Xilinx Virtex FPGA XC2V1000 4FG456 This device controls major functions on the module like CommPorts and SHB communications data flows from the converters and clock management This FPGA needs being configured after power up and after a module reset This operation is possible thanks to the on board Xilinx PROM This operation can be done automatically when jumper J1 Figure 8 Connector Location is fitted If it is not fitted no configuration is loaded into the FPGA and allows therefore the user to program the FPGA via JTAG with no possible conflict Four control registers are implemented into this FPGA to set up converters their data format clock synthesizers CommPort and SHB Some more details are given in the next parts of this document The FPGA is serially programmed using the dedicated pins The PROM is originally programmed with a default bit stream which implements all features mentioned in this document Ressource occupied default firmware as it comes with the board uses FPGA resources such as Ram Blocks Flip flop Slices pads The following table gathers all of them Number Out of Percentage used of utilisation External IOBs Number of 40 0 RAMB16s Number of 753 5120 14 SLICEs Number
23. ibed in the next part of this document Version 1 0 Page 8 of 37 SMT364 User Manual Architecture Description The module consists of a Xilinx Virtex ll FPGA four Analog Devices 14 bit monolithic sampling Analog to Digital converters AD6645 The AD6645 is a 14 bit monolithic sampling analog to digital converter The chip provides CMOS compatible digital outputs It is the Analog Devices fourth generation of wideband ADCs The AD6645 maintains outstanding AC performance up to input frequencies of 200 MHz which makes it suitable for multi carrier 3G applications The AD6645 is able to sample from 30 up to 105 MHz Nevertheless it is possible to reduce that rate by performing decimation on the data flow Parallel busses connect ADCs to the FPGA which is responsible for transferring samples from the converters Two on board frequency synthesizers generate differential encode lines sampling clocks to feed the converters two connectors for two external clocks is also available Each analogue signal input to the ADCs goes through an extra stage which can be an opamp DC coupling or an RF transformer AC coupling The option must be defined when ordering a SMT364 ADCs can be coupled together i e they have the same sampling clock or have separate clocks one external and one coming from the on board clock synthesizer The Xilinx FPGA Virtex ll is configured via a 6 pin JTAG header or from the on board Xilinx PROM XC18V04 at startup The
24. led SHBA J2 and SHBB J3 see Figure 8 Connector Location SHBA and SHBB are set as transmitter only to transfer data coming from the Analogue to Digital Converters to an external SHB module for instance SMT3695 SMT365E or SMT374 Transfers at up to 100 MHz are supported on these two SHB connectors The FPGA routes the data lines coming from ADCA and ADCB to SHBA and from ADCC and ADCD to SHBB The board offers to possibility to output data in either two s complement or binary format It is also possible to output a 16 bit counter on each SHB half for system testing purpose It then becomes easier to detect any missing data The board can also be enabled to add channels with each other ADCA ADCB and or ADCC ADCD and or ADCA ADCB ADCC ADCD in binary format only On each data path decimators can be set to trim samples out Decimators are independent If both decimators of a pair of channel channels A and B or Channels C and D are set with the same values and if the sampling clocks Channel A and Channel B or Channel C and Channel D are the same data streams of a same SHB connector can be considered as synchronised and therefore the two 16 bit data streams can be considered as a single 32 bit data stream It is possible to control start stop the data flow by the way of an external trigger for which the active level high or low can be set in a control register It is recommended Version 1 0 11 of 37 SMT364 User Manual
25. loorplanner from the Design ADCD NET adcd rdy gclk LOC AB12 NET adcd rdy LOC AA16 NET adcd ovr LOC V17 NET adcd lt 13 gt LOC AB16 data 12 2 LOC W16 NET adcd data 112 LOC Y16 NET adcd data 102 LOC V16 adcd data 9 LOC V15 generated with Multiprocessor adcd data 8 LOC AA17 NET adcd data 7 LOC AB17 NET lt 6 gt LOC AA18 adcd data 5 LOC AB18 adcd data 4 LOC W17 NET adcd data 3 LOC Y17 NET adcd data 2 LOC W18 NET adcd data 1 LOC Y18 adcd_data lt 0 gt LOC 19 ADCC NET adcc gclk LOC Y12 NET LOC AA13 NET adcc ovr LOC Y15 NET adcc data 13 LOC AB13 NET adcc data 12 LOC U13 NET adcc data 11 LOC V13 NET adcc data 10 LOC W13 NET adcc data 9 LOC Y13 NET adcc data 8 LOC 14 NET adcc data 7 LOC AB14 NET adcc data 6 LOC W14 NET adcc data 5 LOC Y14 NET adcc_data lt 4 gt LOC U14 NET adcc data 3 LOC V14 NET adcc data 2 LOC AA15 NET adcc data 1 LOC AB15 NET adcc data 0 LOC W15 ADCB Version 1 0 adcb rdy gclk LOC V11 NET adcb LOC adcb ovr LOC
26. mple Version 1 0 Page 35 of 37 SMT364 User Manual Register OxD FPGA Global Reset Bit By sending this control word the gets reset Every single register in the is reset The FPGA transmit that command to the Clock synthesizers which keep the internal register values but does not output any signal Clock multiplexers which take there default state external clocks routed to ADCs interface implemented in the FPGA including CommPort interface It is note recommended to proceed to an FPGA global reset while communications are happening It might stick the other end into an unknown state After a Reset command the SMT364 expects receiving a dummy ComPort word any value and sends one back containing the Firmware version number It is a way of checking that the firmware is latest and that the board is responding and ready to work The format of that ComPort word is as follow OxFF364Fxy which means FPGA firmware version x y Version 1 0 Page 36 of 37 SMT364 User Manual Register OxF Serial Interfaces load Bit The clock synthesizers a Serial Port Interface sending this control word the FPGA serialises Register OxO and sends it to both clock synthesizers Version 1 0 37 of 37 SMT364 User Manual SMT364 package The SMT364 comes with an install package SMT6600 that contain examples and a C header file When ordered with either
27. of DCMs Number of 0 External DIFFMs Number of 0 External DIFFSs 0 Number of 5 16 31 GCLKs Figure 2 FPGA utilisation Version 1 0 10 of 37 SMT364 User Manual Most of the resources are not used by the default firmware which allows the user to implement some extra processing such as digital filters ADCs The SMT364 is populated with four AD6645s For more details about these converters inner characteristics please refer to the manufacturer Analog Devices datasheets Data and control lines of the converters are all connected to the FPGA Clock management The 5 1364 has two identical on board low jitter clock synthesizers one per pair of ADCs Both have a Serial Port Interface The FPGA 15 responsible for setting them to the correct values loaded into a control register A wide range of frequencies can be set this way The 5 write only i e they can t be read back Clock multiplexers are also available on the board to route the appropriate clock signal from external or on board source to the converters It is usual to have both ADOs fed with the same sampling clock but it is possible to have an ADC receiving the external clock and the second one receiving the on board clock In this particular case two 16 bit interfaces are necessary to transfer samples to an external TIM Sundance High speed Bus SHB The SMT364 provides 2 full SHB Sundance High speed Bus connectors label
28. re available on the board Four denoted O 1 2 and 3 on the PCB top left of them green are driven by the FPGA In the default bitstream they indicate what follows 0 gt Flashing under the ADCA sampling clock it can be useful to check that the LED is flashing when using an external sampling clock signal 1 gt Flashing under the ADCB sampling clock 2 gt Flashing under the ADCB sampling clock gt Flashing under the ADCB sampling clock Two green LEDs located at the bottom left and right of the board indicate the status of the power supplies Both should be on when the board is under power A red LED located on the top right of the board indicated when the FPGA is not programme In normal operation i e J1 fitted Figure 8 Connector Location it flashes once at power up and after a module reset Just after a reset TIM or FPGA Global Reset the LEDs display the Firmware version Version 1 0 Page 12 of 37 SMT364 User Manual TTL I Os Four TTL I Os see Figure 8 Connector Location are connected directly to the FPGA They support LVTTL signals is recommended to make sure the lines connected to these pins LVTTL compatible in order not to damage the FPGA pads as lines are not clamped Sundance Standards Communication Ports ComPorts According to the board you can get up to six 8 bit data parallel inter processor links that follow Texas Instruments TMS320C4x Communication Port
29. standard Additional information on the standard is available the TMS320C4x User s Guide chapter 12 Communication ports and the Texas Instrument Module Specification The standard gives a TIM six links numbered from O to 5 Each link can be a transmitter or a receiver and will switch automatically between these states depending on the way you use it Writing to a receiver or reading from a transmitter will cause a hardware negotiation token exchange that will reverse the state of both ends of the link Following a processor reset the first three links 0 1 and 2 initialise as transmitters and the remainder 3 4 and 5 initialise as receivers When you wire TIMs together you must make sure that you only ever connect links initialising as transmitters to links initialising as receivers never connect two transmitters or two receivers For example connecting link O of one TIM to link 4 of another is safe connecting link O of one TIM to link 2 of another could damage the hardware Always connect ComPort 0 1 or 2 to ComPort 3 4 or 5 On most carrier board the physical connection between ComPorts is made with FMS cables Ref SMT3xx FMS You must be careful when connecting the cables the make sure that one end is inserted in the opposite sense to the other One end must have the blue backing facing out and the other must have the silver backing facing out The SMT310Q SMT320 motherboard communicates with the host PC using ComPor
30. t 3 of the site 1 TIM You should not make any other connections to this ComPort ComPorts Communication ports links follow Texas Instrument C4x standard They are 8 bit parallel inter processor ports of the C4x processors ComPorts drive at 3 3v signal levels The FPGA can implement up to two FIFO buffered ComPort interfaces fully compliant with the TIM standard They are guaranteed for a transfer rate of 20MB s The FIFOs are useful to maintain a maximum bandwidth and to enable parallel transfers Version 1 0 Page 13 of 37 SMT364 User Manual Therefore as an example each CommPort can be associated with two 15x32 bit unidirectional FIFOs implemented into the one for input and one for output An additional one word buffer makes them appear as 16x32 bit FIFOs DATA Figure 3 CommPort interface data path he FIFO 16 x 32x 2 Control Logic and Status STRB RDY REQ ACK A Sundance High speed Bus SHB Both SHB buses are identical and 60 bit wide SHBs are parallel communication links for synchronous transmissions Each SHB can be divided into two independent 8 bit buses Each 8 bit bus includes a clock and three control signals write enable request and acknowledge An SHB bus can also be divided into two 16 bit buses and one 8 bit bus Here is the architecture of the SHB interfa
31. wing precautions should be taken SMT364 is a static sensitive product and should be handled accordingly Always place the module in a static protective bag during storage and transition SMT364 reaches a temperature close to the maximum temperature ratings of the ADCs FPGA and DC DC when operated in a closed environment By mounting a fan inside the PC case it increases the airflow and therefore reduces the board temperature down away from the maximum ratings It is to the customer s responsibility to make sure that a minimum airflow circulates along the carrier board where the SMT364 seats Version 1 0 Page 6 of 37 SMT364 User Manual Outline description The SMT364 is a quad high speed ADC module offering the following features Four 14 bit ADCs AD6645 105 sampling at up to 105MHz Single width module Two Sundance High speed Bus SHB connectors Four 20 MegaByte s communication ports Low jitter on board system clock Xilinx Virtex Ill FPGA 50 Ohm terminated analogue inputs and outputs external triggers and clocks via MMBX Huber and Suhner connectors User defined pins for external connections Compatible with a wide range of Sundance SHB modules TIM standard compatible Default FPGA firmware implementing all the functions described along this documentation Power consumption 10 95 Watts in total which is 7OOmA under 12 Volts 180mA under 5Volts and 500mA under 3 3Volts V
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