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1. SSC Waveforms at Different Modulation Speeds Time usec Figure 6 Programmable SSC generation Per Lane Clock Recovery and Unique Dual Path Architecture Like pre emphasis conventional tools often require separate clock recovery instrumentation In the SV1C each receiver has its own embedded analog clock recovery circuit Additionally the clock recovery is monolithically integrated directly inside the receiver s high speed sampler thus offering the lowest possible sampling latency in a test and measurement instrument The user does not have to make special connections or carefully match cable lengths The monolithic nature of the SV1C clock recovery helps achieve wide tracking bandwidth for measuring signals that possess spread spectrum clocking or very high amplitude wander Figure 7 shows a block diagram of the clock recovery capability inside the SV1C Personalized SerDes Tester Page introspect technology SV1C Introduction and Features Also shown in Figure 7 is the dual path receiver architecture of the SV1C This unique architecture allows the SV1C to operate as both a digital capture analysis instrument and an analog measurement instrument A feature rich clock management system allows for customization of the SV1C to specific customer requirements Data Path Capture Logic A Clock Management Measurement Path Precision V High BW Channel DSP Sampler 8 Analysis Logic rxChannelList
2. e PCI Express PCIe e HDMI e UHS 2 e Thunderbolt e MIPI M PHY e XAUI e CPRI e JESD204B e USB e SATA Interface test of electrical optical media such as e Backplane e Cable e CFP MSA SFP MSA SFP MSA Plug and play system level validation such as e PCI Express e DisplayPort sink source e MIPI M PHY Timing verification e PLLtransfer function measurement e Clock recovery bandwidth verification e Frequency ppm offset characterization Mixed technology applications e High speed ADC and DAC JESD204 data capture and or synthesis e FPGA based system development e Channel and device emulation e Clock recovery triggering for external oscilloscope or BERT equipment Page 3 inGrospect technology SV1C Introduction and Features Features Multi Lane Loopback The SV1C is the only bench top tool that offers instrument grade loopback capability on all differential lanes The loopback capability of the SV1C includes e Retiming of data for the purpose of decoupling DUT receiver performance from DUT transmitter performance e Arbitrary jitter or voltage swing control on loopback data Figure 1 shows two common loopback configurations that can be used with the SV1C In the first configuration a single DUT s transmitter and receiver channels are connected together through the SV1C In the second configuration arbitrary pattern testing can be performed on an end to end communications link The SV1C is used to p
3. and CMOS Table 2 Transmitter Characteristics Output Coupling DC common mode voltage 750 mV typical reduced offsets are firmware programmable AC Output Differential Impedance 100 Ohm typical Voltage Performance Minimum Differential Voltage Swing 20 mV Maximum Differential Voltage Swing 1000 mVpp 312 5 Mbps to 5 Gbps 50 ohm AC coupled termination 800 mVpp 5Gbpsto 12 5 Gbps 50 ohm AC coupled termination Differential Voltage Swing Resolution 20 mV larger of 10 of programmed value and 10mV Accuracy of Differential Voltage Swing Page 11 introspect technology Rise and Fall Time 50 ps 75 ps Pre emphasis Performance Pre Emphasis Pre Tap Range Pre Emphasis Pre Tap Resolution Range 32 Pre Emphasis Post1 Tap Range Oto6 Pre Emphasis Post1 Tap Resolution Range 32 Pre Emphasis Post2 Tap Range 4 to 4 Pre Emphasis Post2 Tap Resolution Range 32 Jitter Performance Random Jitter Noise Floor Minimum Frequency of Injected Deterministic Jitter Maximum Frequency of Injected Deterministic Jitter Frequency Resolution of Injected Deterministic Jitter Maximum Peak to Peak Injected Deterministic Jitter Magnitude Resolution of Injected Deterministic Jitter Injected Deterministic Jitter Setting Common Maximum RMS Random Jitter 0 1 Injection Magnitude Resolution of Injected 0 1 Jitter Accuracy of Injected Jitter Magnitude larger of 10 of programmed value and 10 ps In
4. Pattern Memory Total Available Memory Individual Force Pattern Individual Expected Pattern Minimum Pattern Segment Size Maximum Pattern Segment Size Total Memory Space for Transmitters Total Expected Memory Space for Receivers Pattern Sequencing Sequence Control Number of Sequencer Slots per Pattern Generator Maximum Loop Count per Sequencer Slot Additional Pattern Characteristics Pattern Switching Raw Data Capture Length PRBS 23 PRBS 31 Per transmitter Per receiver Automatic seed generation for PRBS 2 Per transmitter Per receiver 512 65536 1 1 Loop infinite Loop on count Play toend 4 Tai Wait to end of segment Immediate 8192 SV1C Specifications Automatically aligns to PRBS data patterns Memory allocation is customizable Contact factory Memory allocation is customizable Contact factory Memory allocation is customizable Contact factory This refers to the number of sequencer slots that can operate at any given time The instrument has storage space for 16 different sequencer programs When sourcing PRBS patterns this option does not exist Table 6 Measurement and Throughput Characteristics BERT Sync Alignment Modes Minimum SYNC Error Threshold Maximum SYNC Error Threshold Minimum SYNC Sample Count Maximum SYNC Sample Count SYNC Time Pattern PRBS 3 4294967295 1024 3 20 Module can align to any user pattern or preset pattern Assumes a PRBS7 patt
5. Phase of Receiver Sampling Point a b Figure 10 Screen capture of Introspect ESP user environment Page 10 introspect technology Table 1 Specifications General Specifications SV1C Specifications Number of Differential Transmitters Number of Differential Receivers Number of Dedicated Clock Outputs Number of Dedicated Clock Inputs 1 Number of Trigger Input Pins Multiple Number of Flag Output Pins Multiple Data Rates and Frequencies Minimum Programmable Data Rate Maximum Programmable Data Rate Maximum Data Rate Purchase Options Data Rate Field Upgrade Frequency Resolution of Programmed Data Rate Individually synthesized frequency and output format Used as external Reference Clock input Consult user manual for included capability Contact factory for customization Consult user manual for included capability Contact factory for customization Contact factory for extension to lower data rates Contact factory for details Finer resolution is possible Contact factory for customization Minimum External Input Clock Frequency Maximum External Input Clock Frequency Supported External Input Clock I O Standards LVDS typical 400 mVpp input LVPECL typical 800 mVpp input Minimum Output Clock Frequency Maximum Output Clock Frequency Output Clock Frequency Resolution Supported External Input Clock I O Standards Support for LVDS LVPECL CML HCSL
6. address the growing need of a parallel system oriented test methodology while offering world class signal integrity features such as jitter injection and jitter measurement With a small form factor an extensive signal integrity feature set and an exceptionally powerful software development environment the SV1C is not only suitable for signal integrity verification engineers that perform traditional characterization tasks but it is also ideal for FPGA developers and software developers who need rapid turnaround signal verification tools or hardware software interoperability confirmation tools The SV1C integrates state of the art functions such as digital data capture bit error rate measurement clock recovery jitter decomposition and jitter generation True parallel bit error rate measurement across 8 lanes Fully synthesized integrated jitter injection on all lanes Fully automated integrated jitter testing on all lanes Optimized pattern generator rise time for receiver stress test applications Flexible pre emphasis and equalization Flexible loopback support per lane Hardware clock recovery per lane State of the art programming environment based on the highly intuitive Python language Integrated device control through SPI I2C or JTAG e Reconfigurable protocol customization on request Page 2 introspect technology Applications SV1C Introduction and Features Parallel PHY validation of serial bus standards such as
7. lanes r DV1600 GPI BertScarViewer HH Zum A S i Bathtub Plot Jitter Histogram cht Do Men Ochs Des Ochs Ich7 chs Al ch 9 ch 10 ch 11 ch 12 ch 13 ch 14 ch 15 ch 16 None RJ ps 4 70 Channel 3 1 62 65 87 lt lt 1 00E 020 Bathtub Plot BER nta l Zoom V Center Bert Scans DJ ps TJ le 12 Estimated BER Eye Center ps 28 00 L Voltage mv a T r ad Analogue Capture Viewer AE Analogue Data Capture 400 200 200 400 1000 1500 time ps 2000 2500 3000 r DV1600 GPI EyeScanViewer EJ zon Eye Height mV Eye Width ps 687 0 586 0 Eye Diagram BER Plot BER Contour r a Pattern Viewer Eye Diagram Channel 3 0 10 20 30 40 Drag axis to zoom in and out voltage mv Figure 9 Sampling of analysis and report windows Page 9 introspect technology SV1C Introduction and Features Automation The SV1C is operated using the award winning Introspect ESP Software It features a comprehensive scripting language with an intuitive component based design as shown in the screen shot in Figure 10 a Component based design is Introspect ESP s way of organizing the flexibility of the instrument in a manner that allows for easy program development It highlights to the user only the parameter
8. Introspect Gechnology Ready Locked DO NOV AWNWN User SV1C Personalized SerDes Tester Data Sheet N introspect A technology SV1C Personalized SerDes Tester Data Sheet Revision 1 4 2014 04 15 Revision Revision History Date 1 0 Document release Feb 27 2013 1 1 Updated jitter injection specs SSC specs clock Oct 07 2013 recovery specs added block diagram descriptions 12 Minor edits Oct 07 2013 1 3 Update to specifications Nov 12 2013 1 4 Update to specifications Apr 15 2014 The information in this document is subject to change without notice and should not be construed as a commitment by Introspect Technology While reasonable precautions have been taken Introspect Technology assumes no responsibility for any errors that may appear in this document No part of this document may be reproduced in any form or by any means without the prior written consent of Introspect Technology Product SV1C Personalized SerDes Tester Status Released Copyright 2014 Introspect Technology ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V E readily accumulate on the human body and test eguipment and can discharge without _ detection Permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality intro
9. al Time Base Number of Internal Freguency Relevant for future customization References Embedded Clock Applications Transmit Timing Modes Extracted Clock can be extracted from one of the data receiver channels in order to drive all transmitter channels Receive Timing Modes System Extracted All channels have clock recovery for extracted mode operation Lane to Lane Tracking Bandwidth Single Lane CDR Tracking Bandwidth Forwarded Clock Applications Transmit Timing Modes Forwarded Channel 1 acts as forwarded clock for samplers Receive Timing Modes System Forwarded Channel 1 acts as forwarded clock for samplers Clock Tracking Bandwidth 4 Second order critically damped response Spread Spectrum Support Receive Lanes Track SSC Data Requires operation in extracted clock mode Transmit Lanes Generate SSC Data Consult factory for availability Minimum Spread Maximum Spread Spread Programming Resolution Minimum Spreading Frequency Maximum Spreading Frequency Table 5 Pattern Handling Characteristics Loopback Rx to Tx Loopback Capability Per channel Lane to Lane Latency Mismatch 0 Ul Maintained across cascaded modules Preset Patterns Standard Built In Patterns All Zeros D21 5 K28 5 K28 7 DIV 16 DIV 20 DIV 40 DIV 50 PRBS 5 PRBS 7 PRBS 9 PRBS 11 PRBS 13 PRBS 15 PRBS 21 Page 14 introspect technology Pattern Choice per Transmit Channel Pattern Choice per Receive Channel BERT Comparison Mode User programmable
10. ass data through from a traffic generator such as an end point on a real system board to the DUT while stressing the DUT receiver with jitter skew or voltage swing Traffic Generator a b Figure 1 Illustration of loopback applications Multiple Source Jitter Injection The SV1C is capable of generating calibrated jitter stress on any data pattern and any output lane configuration Sinusoidal jitter injection is calibrated in the time and frequency domain in order to generate high purity stimulus signals as shown in Figure 2 Page 4 introspect technology SV1C Introduction and Features Injected Jitter ps Time ns Figure 2 Illustration of calibrated jitter waveform The jitter injection feature is typically exploited in order to perform automated jitter tolerance testing as shown in the example in Figure 3 As is the case for other features in the SV1C Personalized SerDes Tester jitter tolerance testing happens in parallel across all lanes For advanced applications the SV1C also includes RJ injection and a third source arbitrary waveform jitter synthesizer E Introspect ESP Shoo Viewer shmool a chl ch ch O ha z T ch che Colorhlap brwoColorlinear Mr 0 O Mec 1 Logarithme 25 3 jitterFrequency Figure 3 Illustration of jitter tolerance curve Page 5 introspect technology SV1C Introduction and Features Pre Emphasis Generation Conventionally offere
11. ct ESP user environMent ccccccsssssesssseeeeeeees 10 introspect technology Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 SV1C Introduction and Features List of Tables Earl AMS 11 Transmitter CH A000 rra 11 Receiver Characteristics MAA and ae eee er een l ode d 13 CIO AAA MR R R O V E OAA EAO A N E 14 Palt rn Handling Charaelerist OS aia ii iii 14 Measurement and Throughput Characteristics ssccccccccceeeeesssseeeeeeeeeees 15 Instruction Sequence F cher ee 16 MIRE M oko Jy 11101 PO PP N O O O RR 17 Page 1 introspect technology Overview Key Benefits SV1C Introduction and Features Introduction The SV1C Personalized SerDes Tester is an ultra portable high performance instrument that creates a new category of tool for high speed digital product engineering teams It integrates multiple technologies in order to enable the self contained test and measurement of complex SerDes interfaces such as PCI Express Gen 3 MIPI M PHY Thunderbolt or USB3 Coupled with a seamless easy to use development environment this tool enables product engineers with widely varying skills to efficiently work with and develop SerDes verification algorithms The SV1C fits in one hand and contains 8 independent stimulus generation ports 8 independent capture and measurement ports and various clocking synchronization and lane expansion capabilities It has been designed specifically to
12. d as a separate instrument per lane pre emphasis control is integrated on the 8 lane SV1C tester The user can individually set the transmitter pre emphasis using a built in Tap structure Pre emphasis allows the user to optimize signal characteristics at the DUT input pins Each transmitter in the SV1C implements a discrete time linear egualizer as part of the driver circuit An illustration of such equalizer is shown in Figure 4 and sample synthesized waveform shapes are shown in Figure 5 OUT Post Tap 1 Pre Tap 1 Post Tap 2 Figure 4 Illustration of pre emphasis design Figure 5 Illustration of multiple waveform shapes that can be synthesized using the pre emphasis function of the SV1C Page 6 introspect technology SV1C Introduction and Features Programmable SSC Generation and Frequency Synthesis Frequency Deviation MHz 15 The SV1C incorporates precision frequency synthesis technology that allows for the generation of programmable SSC waveforms at any data rate The SSC waveforms are superimposed on the pattern generator outputs and they coexist with other jitter injection sources of the SV1C Thus a truly complete jitter cocktail can be produced for the most thorough receiver validation Figure 6 illustrates the SSC capability of the SV1C In the figure the SV1C is programmed to synthesize four slightly different modulation frequencies showcasing the precision programmability of the tool
13. ern that is stored in a user pattern segment and worst case misalignment between DUT pattern and expected pattern data rate is 3 25 Gbps Page 15 introspect technology SV1C Specifications BERT Error Counter Size 32 bits Sample counts in the BERT are programmed in increments of 32 bits Maximum Single Shot Duration 17179869184 bits Repeat mode is available to continuously count over longer durations Continuous Duration Indefinite Alignment CDR Lock Time us Self Alignment Time ms Test Sequences Total Jitter Measurement Time ms This includes measurement time and processing time to extract jitter values on eight simultaneous lanes The extraction algorithm is based on O scale analysis Data rate is 3 25 Gbps Single Point Pass Fail Jitter Test Time ms Assumes a BERT SYNC has already been performed This test sets the Rx phase generators in the middle of the eye and performs a BERT measurement Data rate is 3 25 Gbps DUT Transmit Skew Test Time ms Assumes a BERT SYNC has been performed This test divides the DUT UI into 16 intervals for the purpose of skew measurement Data is post processed in the test system software Data rate is 3 25 Gbps DUT 6 Point Mask Test Time ms Assumes a BERT SYNC has been performed This test programs the six mask locations and performs a 1 shot BERT at each location Data rate is 3 25 Gbps Time to Change Jitter Parameters ms Time to Change Data Rate ms This is a typical number and appl
14. gt rxClockMode globalClockConfig gt systemRefClockSource Figure 7 Per lane clock recovery and dual path architecture Auxiliary Control Port The SV1C includes a low speed auxiliary control port that is based on a standard SCSI connector Figure 8 This port enables controlling DUT registers through JTAG I2C or SPI Additionally the port includes reconfigurable trigger and flag capability for synchronizing the SV1C with external tools or events Figure 8 Photograph of the auxiliary control port on the SV1C Page 8 introspect technology Analysis SV1C Introduction and Features The SV1C instrument has an independent Bit Error Rate Tester BERT for each of its input channels Each BERT compares recovered retimed data from a single input channel against a specified data pattern and reports the bit error count Apart from error counting the instrument offers a wide range of measurement and analysis features including e Jitter separation e Eye mask testing e Voltage level pre emphasis level and signal parameter measurement e Frequency measurement and SSC profile extraction Figure 9 illustrates a few of the analysis and reporting features of the SV1C Starting from the top left and moving in a clock wise manner the figure illustrates bathtub acquisition and analysis waveform capture raw data viewing and eye diagram plotting As always these analysis options are executed in parallel on all activated
15. ies for ATE applications in which data rate caching is enabled Table 7 Instruction Sequence Cache Simple Instruction Cache Instruction Learn mode Instruction Advanced Instruction Cache Local Instruction Storage 1M Instructions Instruction Sequence Segments 1000 Page 16 introspect technology SV1C Specifications Table 8 DUT Control Capabilities DUT SPI Port Option SPI Signals Voltage Swing Fixed DUT IEEE 1149 1 JTAG Port Option JTAG Port Transmit Signals JTAG Port Receive Signals JTAG Port Transmit Voltage Swing V Fixed JTAG Port Receive Max Voltage Swing V TDI Bit Memory TDO Bit Memory Page 17 Introspect Gechnology Introspect Technology 642 Rue de Courcelle Suite 315 Montreal Quebec Canada H4C 3C5 http introspect ca
16. jected Random Jitter Setting Common Transmitter to Transmitter Skew Performance Lane to Lane Integer Ul Minimum Skew Lane to Lane Integer Ul Maximum Skew Effect of Skew Adjustment on Jitter Injection Lane to Lane Skew SV1C Specifications Typical 500 mVpp signal 20 80 50 ohm AC coupled termination Typical 500 mVpp signal 10 90 50 ohm AC coupled termination Both high pass and low pass functions are available This is the smallest achievable range based on worst case conditions Typical operating conditions result in wider pre emphasis range Only high pass function is available This is the smallest achievable range based on worst case conditions Typical operating conditions result in wider pre emphasis range Both high pass and low pass functions are available This is the smallest achievable range based on worst case conditions Typical operating conditions result in wider pre emphasis range Based on measurement with high bandwidth scope and with first order clock recovery Contact factory for further customization Contact factory for further customization This specification is separate from low frequency wander generator and SSC generator Jitter injection is based on multi resolution synthesizer so this number is an effective resolution Internal synthesizer resolution is defined in equivalent number of bits Common across all channels within a bank Common across all channels within a ba
17. nk Page 12 introspect technology SV1C Specifications Table 3_ Receiver Characteristics Input Coupling AC Input Differential Impedance 100 Ohm AC Performance Minimum Detectable Differential Voltage Maximum Allowable Differential Voltage Minimum Programmable Comparator Threshold Voltage Maximum Programmable Comparator Threshold Voltage Differential Comparator Threshold 10 Voltage Resolution Differential Comparator Threshold larger of 10 of Voltage Accuracy programmed value and 10mV Measured Eye Width Accuracy 10 Maximum error 312 5 Mbps 2 0 Gbps 200 mVpp minimum input amplitude 15 Maximum error 2 0 Mbps 5 Gbps 200 mVpp minimum input amplitude 25 Maximum error 5 Gbps 12 5 Gbps 200 mVpp minimum input amplitude Resolution Enhancement amp Equalization DC Gain CTLE Maximum Gain CTLE Resolution DC Gain Control Per receiver Equalization Control Per receiver Jitter Performance Input Jitter Noise Floor in System Reference Mode Input Jitter Noise Floor in Extracted Clock Mode Timing Generator Performance Resolution at Maximum Data Rate 31 25 Resolution as a percentage of Ul improves for lower data rate Contact factory for details Differential Non Linearity Error 0 5 Integral Non Linearity Error 5 Range Unlimited Lane to Lane Skew Measurement Accuracy Page 13 introspect technology SV1C Specifications Table 4 Clocking Characteristics Intern
18. s that are needed for any given task thus allowing program execution in a matter of minutes For further help the SV1C features automatic code generation for common tasks such as Eye Diagram or Bathtub Curve generation as shown in Figure 10 b E y DV1600 GPI BERT Scan Wizard Untitled lt EE DFT microsystems K DV1600 GPI test RXTG bathtub gt O O0 A File Edit DV1600 Wizards Help m Log Results Components bertEngine1 properties class Bert Engine S continuous Duration 1000 BERT Setup bert Scan2520Mbps mode single Shot Duration in bits 110 000 000 bertScan4960Mbps nmChannellist mChannel List 1 bertScan5040Mbps single Shot Length 1000000 globalClockConfig syncError Threshold 3 Phase Sweep Setup mChannelList 1 txChannelList 1 Start Phase 300 41 ps End Phase 300 ps Step Phase 13 ps continuousDuration duration in milliseconds for continuous BERT measurements Input Digital Signal Add Remove Test Procedure txphase end 310 txphase step 10 Output BER Bathtub E22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22 2 2 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 22 22 2 2 22 22 23 2 2 2 2 22 2 2 2 RRR RRR RR R R E set datarate to 2480Mbps globalClockConfig dataRate 2480 0 v o i o u m Setup data rate and source Tx pattern globalClockConfig setup txChannelListi setup
19. spect technology Table of Contents Table of Contents o BRNO R O E O ae oes ernest O O 2 A ag cts goa ph tac NY SPOR SME A ees 2 E 1 o o cls eed A 2 a PTE ENTEN POEIER A O AENT A O O pares 3 PON sein E EEEE EEEE 4 NEMEL LOOPT ASA 4 RKO Sec JIB 11 GET ee 4 Pre Pomphasis Genera croata iaa 6 Programmable SSC Generation and Frequency Synthesis ccccsssssssseeecceeeeeeeeseees 7 Per Lane Clock Recovery and Unique Dual Path Architecture 00000 7 AA EEA 8 O A A 9 A tara 10 Jr AA O O O O A 11 Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 List of Figures Illustration of loopback 21 EI O os dlen odk ed 4 Illustration of calibrated jitter waveform cccccccssssssseeeccccceeeeessesesccceceeeees 5 Ustration of iiiter tolerance CHV ection iaa 5 Illustration of pre emphasis design ccssssssssscccccssccssssssssscecscecesssessssccceseees 6 Illustration of multiple waveform shapes that can be synthesized using the pre emphasis function of the SV1C sssssssssccsssccsssssssscccecseceesssssssscessees 6 Programmable SSC generation nun 7 Per lane clock recovery and dual path architecture ccccccccccesessseeeeeeees 8 Photograph of the auxiliary control port on the SVIC 8 Sampling of analysis and report windows ccccccccssssssseececceceeeeessseeeceeeeeeeees 9 Figure 10 Screen capture of Introspe

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