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USER`S MANUAL

1. 3N bh Bl EIS T sin SNe lt TH9 vT9 EE0T Ge E E 9 1191051 73NNUH2 017 290052 921 7007 8569 9601 yTS EEOT ON Ese 2102 T vT9 EEOT ON dg in 8 T 1191051 TANNUHI OL 290052 vTH gt 92T TOOT 96 bTHD STHO 9821 1901 96h 0E0T da 814 STHO 0121 00512 104100 104 1 1911910 2Unesz 48 15 1400 21631409 kal DNS LIS 07 1 71911910 03191051 faraona al 4 4 Eed eg HA 519 0 EI Eeer Ka 9 911914 11 LAdNI 1910 9 9 0H 26891 SNOT 4 9 N3d0 5 x 0H9 2EU vd THI 29 00 SHOT JnT e N3d0 T a SHOT ANT Q N3d0082 D 2H9 EHI S22 001T 3119 N3d0 99 to a S2U bd 1191051 TANNUHI 01 TINNUHI 290052 289 v00T 14071052 1ndlnO lndNI 19119104 290052 a 929 100T 49 ze 0 1 WLISIG 83191051 2920 S
2. 129 007 O 0T sta N3d0 STI HESSE 2TNI adm 5 ns 2THO wen eee eee mm 1191051 13 9 2 OL 13 9 2 290052 i ETHO STS EEOT 8224 9011 129 001 630T EF anyo N3d0 9T2 S ns 22r ETHO H eed 1191051 OL J3NNUHO 290052 si PTH2 N as m a SHOT i ATH Panta N3d0 LT9 e 5 05 4 1191051 OL 290052 8246 9011 T29 v00T SHOT 814 V TSTNI 31179 N3d0 8TO5 S as STHO 1191051 3NNUHO OL TANNUHI 290052 1191061 104100 104 1 71911910 290052 52 Terri 0119501 51894 ONY 2210143115 44908 1140 031 PES 8TOT 0 08 D d sch e 16616 YSN IN uoXrm vES 8TOT T I bt63HnU S I3NNUHO LNdNI STANNSHD 1041 0 ST ET 2T TT OT 6 2 98 S E 2 ST ET 2T TT OT 6 8 2 8 S T Q 214 8 ETA
3. 001222 5 9596 non condensing Physical Double Eurocard Length eerta 9 187 233 3 WV EE 6 299 160 0 mm Board Thickness aden Aem tg 0 062 in 1 59 mm Component Height 0 0 550 13 97 Recommended Card 0 800 20 32 Mating Connectors EE tein dore E 96 pin 603 2 IEC class 2 UE HE ee lala Not Used E mA Cate IS RE PL I ten Panduit No 100 532 033 Type B Male Connectors rows A amp B equipped even pins only 32 pins total Power Requirements 5 Volts 595 adc RE KA 1 0A typical 1 5 maximum 2 0 0 no load VME COMPLIANCE Meets or exceeds all written VME specifications per revision C 1 dated October 1985 and IEC 821 1987 Data Transfer BUS i A24 A16 D16 D08 EO DTB slave VMEbus Access 580nS typical all registers Measured from the falling edge of DSx to the falling edge of DTACK Address Modifier COdES 29H 2DH 39H 3DH Memory Map inerte tede te Standard or short address space Supervisory or non privileged access Occupies 1K byte Base address jumper selectable Interruptsl 1 7 request levels single or multiple interrupt vectors D08 O interrupter Relea
4. 928 941 1001 EON B z enz 9H T Sn 1191051 3NNUHO 010 IBNNUHO 290052 1 9 0 ON EF oine T 1191051 OL C3NNUHO 2904052 1 818 9821 1901 8g 96 Ha 14012051 118110 118 1 71911910 2900582 46 B 6281 1058 Zg Xb 63H09 sum Quvog O I 7911910 03191051 AM MOX 1 8 6 12022 BO WOOLY LL 1 a vT9 EE0T T 8H9 ONNOZ9 191920 821 901 60 96 09 ve 8 1012 052 3NNUHO 01 TANNYHD 290052 8H2 S2 T TOOT era 96 90 uz 913 6H2 300135 HLNOM SLINDAIS gt peeieeeeeeeREHI 11911914 Per 9 d Q 13538 8668 0601 231 HINON T seda 6908 NOILYIOSI J3NNUHO OL T3NNUHO 290052 ERAN 5 STd8 8 222 01 9LT T907 929 h001 1 rn 2 Ser geet 916 TTHO oer i 00 7 Sat 623 01191051 104100 104 1 71911910 2904052 ns 1 2 94 99 09 94 5022 TY 47 e2T Tesve x a Tre 08 0 1 19119104 03191051 mu CECAK a Pd sva EL CHE EE Yu 025290 V 26 190 73 Bowoby LL TL LL SLINDAIS 40 00 1611910
5. 9 5 LNIOd LNdNI e 1911919 Gat AT IMIS Te wisa 117143115 1NIOd LNdNI EPH ttt 1911914 Xbb63H0nU 6 2 330914 0055 9 gut 97 Sansz r Y NIN vg NOILISOd 2 6 UTI Xkb6 06 Xbb6 S39NUM 3199 21901 NI HO 411921140 2 1102412 NIn SEH A 104100 NI HO 21901 2 6 540151534 453 1400 YOLISNNOD 9 11805 39NU3 SONYA 1 dNI CSTH2 0H2 vd 1901191051 33 j MERAKI SNOILYYNOIANOD 1 104 041 911914 85 011943 91 4 LNIOd LNdNI 19 d M 119104 Xbb63M0U b 2 330913 39N333434 ATddNS 33inS0 19 LOVLNOD 55 NS n nme a CATddNS NOHH09 39N333434 5 3415010 LOVLNOD lt 440 0 0 INOW 3991100 2 ID 2 AlddNS 03197051 WW C30N343334 AlddNS Y0193NN09 ems dat 1911914 We 3405079 19U1NO2 0 008 653409 I3NUd 1101041153 1491 8869 AlddNs 9 34 GRAN mese TE 21043115 LNIOd 104100 719119104 05312215 Bpwoiz EM 111135 LNIOd 104100 1911910 Q3IJI dMIS 3 S 2 NO HOLIMS 1101 440 HOLIMS 20088 1090 39NUM 1 04 T 1no 21901 31031N02 1NOn 1001 13NNUHI 2 3933033 100 914 134 08 3504 30123NNO9
6. S cea 5 crea da GEES da TU Y SE Keele S I3NNUHO 104100 ST3INNVHO LNdNI o 40 B 621 105 4 2 AIMS QNUOB O I WLISTG 03191051 9715561 uu 1698 6 HN gt lt 550 a 0 uia D ANNOYS 911914 as etl ke 52910 Ng 944 si bs 11943545 8501 880 031 N3399 Nagao T 505 310N 335 431 261 1001 2 33S 5801139493 5594 8 UNOILIQQU nS 828 01 E8E voor ros eee Sl Dik Di ns 1 lt D D tea T 4 199 36 ON ONT vad 119035 eta rd ONCE 18 14 238 1218 14 W3Q0U3H 95338 Y ONITIWISNI ONY 3015 830105 NO 2N 19359 E08 td OML N33ml38 1104 Y 9NILLN 298 14 37891237135 3QUM NYJ 71194545 310N 6 8 198 19 NAST 13534555 672 59 1 7 NI52UI 8 d Ta ESH 2555 NOT CSR i S d p 2098 081 260 or EST t 5 sn o z u Q 5 8 9908 Toda 2008 amp 908 9008 2008 8908 11 1 08 tn
7. 220 E20 v20 520 920 820 620 114 53 ale ae rT 0119201 51394 ONU 22 43115 0 908 1140 031 sa 21 11597 0350 8 SI 08908 1119819 G3SLNIYd lb GET TOOT 9UHONDU 349 HOnONHLI 86T TOOT 99 0429 3NU STO TO 72 SYZENNN 1494 OUMWONDU 349 5 1494 11914 N303S TW T 1S3LON 1 9 1 00 50 0 E a 05 4 2 06p 00TT 1 05 ES 625556 2 9269 9011 2n ONO 0T CON9 0T 05 220 02 220 02 6 21 5401129492 56504348 30170 Sh9 h00T 2 9E9 00TT 05 Svr S vooT 65 3 SES OOTT 54 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS APPENDIX A A 0 CABLE AND TERMINATION PANELS A 1 CABLE MODEL 9944 x Type Ribbon Cable 64 wire Header Header This cable connects the 6985 16Dx termination panel to the AVME944x board The length of the cable in feet is indicated by the x in the model number 9944 x 12 feet maximum It is recommended that this length be kept to a minimum to reduce noise pickup and power loss especially important for output channels since their currents can reach 1 Amp DC
8. 335 9 TOUH ST EH 862 EEOT 2098 XXS P208 Cova oT vous ZER 5098 5 ST 2008 20 94 2008 Seng F TUTT 2098 20y yoda 5 5 Se 27 coud EB 50048 also 68 _ DA 8008 2 yT Sova 2 OL 8340 FII bal e 084908 0 1 71911910 43191051 OND Eb QNO Eb BT ELL re anu 68 deo o npe speres DOWODY ce 89848 588998 Steve 9 8 St 02 64 02 St 9T St 07 64 02 S 9T 88858 Stee St b2 S Stace St 22 291 090 880 981 ESN Biel gt ssn psn 2800 180 ONNOSO 19 12910 8 2 1 5 01129490 SSUdAG 030 SU Ld39XI 39170 SES v205 SN SEN 8r 4035 LON 0 353 6591 S2r 5 1 S9N 0 ETO 5 1 PED OEY 116971 ETT TOOT I 393 814 2219 1129 3155 FINISM 98 TINIGI 9219 lINISM 89 lINION ES H3389 20 033 82 ANTON 6219 9008 CANO EbbE3WNY SIGLA EAL Toda ser 1003591 Tp 8 87 2008 3ININM 2810 alte 008
9. Clear the global interrupt enable bit in the Board Status Register by writing a 0 to bit 3 Write vector into the Digital Input Channel Interrupt Vector Register associated with channel 7 Select polarity level interrupts for channels by writing 0 to each channel s associated bit in the Digital Input Channel Interrupt Type Select Register Select the desired polarity level for input channel interrupts by writing or 1 to each channel s associated bit in the Digital Input Channel Interrupt Polarity Register Disable individual input channel interrupts by writing 0 to each channel s associated bit in the Digital Input Channel Interrupt Enable Register Enable input pattern detection interrupts by writing 1 to each channel s associated bit in the Digital Input Channel Interrupt Pattern Enable Register Clear pending interrupt inputs by writing 1 to each channel s associated bit in the Digital Input Channel Interrupt Status Register Enable interrupts from the board by writing a 1 to bit 3 the global interrupt enable bit in the Board Status Register Interrupts may now occur from the board 3 3 4 Sequence of Events For an Interrupt 1 2 3 The AVME944x interrupter board makes an interrupt request asserts IRQx The host interrupt handler asserts IACK and the level of the interrupt it is seeking on A01 A03 When the asserted IACKIN signal daisy chained is passed to the 944x the board will put t
10. 104100 03191051 S1H2 0H2 411921140 Ed 35 Lud FET TOSP T40 T SNA AS sus SNOILYYNDI ANO LNIOd 104100 91910 30123NNO2 104100 1911914 44908 Xbb63Hnu 5 0119 0913 02 1 104 104100 1911910 463 0 972 AlddNs 8 NOIlUNIH331 0091 9869 01 8 NOD OL 8 540151538 S3QOIQ SuUadWnr TVIWLSNI 01 1 NO 51015 CATddNS 11041402 1102 CAlddNS 031910512 1103 AYA 30010 140130 931 14915 361 1310N 36 LET TOSb ose N AIMS SONINI 3 819 915 SOND ANY 2 111 OL 32934 1 XpH6INNY 272 330913 8 ir Li ILs P H sua SoSTr vd 3a Ol po 0123NNO2 WLISIG 9 110 11701424 3 1091 8869 43 1dn0201dO 315193 LNdNI 1910 HI 201 104100 1911910 S3 gt 21901 GO 40123NNO2 104100 911910 vostre ES 449084 01631401 8 TINVd ns 1101041143 0091 4869 37 CERCA PIZZI ONIWIL ldON31NI ONY ISNOdSIY 104 1 nu Wad 1 Sup 14 OL 576 3411 3SNOdSIY 12 19101 5045 32Nn0830 SmO1104 59261 01 SMT AU T30 21901 ld089331NI 3184193135 YISN SUpPS T OL 50
11. 2 404 431S193N 3718UN3 N 311Ud 1A4NYYILNI 2 403 431851933 1 21901 21901 ONY 300930 5535009 sna 3344n8 sna 9194 508 CS 831d08331NI OOT ATAT 020 HHAOH LO 39018 2 HD 331851938 ALTYYTOd LdNBYIANI 2 0 304 5 401230 AdNYNIINI L 0H9 404 43181938 123135 34AL 1 ANdNI 804 431S1934 501915 43151933 7911910 43151934 501915 auvoa N3340 U g 8894 194 T t 3340914 4 0H2 21901 1 31U1S 30 39NUH2 I 73NNUHO 1NdNI e 1102912 ST 0H2 ST 0H2 arta NOI19313S 2 2 101 SONYA LODNI ANO I L amp V 63H09 9 80123NNO2 ANANI 7911910 ET ED ST 0H2 SAU134 ST 0H2 104100 31916 01108 104100 929120 1921140 7 I Ebb63WNY i 9 N3IMNUH 1191051 WLIDIO 1921140 E etot 0631400 RIES EH 071 71911910 43191051 fona wl e pw prn 16 HA SAVOY 21601 26 190 22 LLLI Il Le uu Sowosy SES 8T0T 08 7274 4116 314010 GS G B B Cir 24 ag
12. FIGURES 2 1 AVME944X JUMPER LOCATION DRAWING 4501 130 ss 2 2 AVME944X I L LED EXPANSION BOARD ASSEMBLY 4501 125 2 3 AVME944X SIMPLIFIED DIGITAL INPUT POINT SCHEMATIC 4501 131 2 4 AVME944X DIGITAL INPUT POINT CONFIGURATIONS 4501 132 2 5 AVME944X SIMPLIFIED DIGITAL OUTPUT POINT SCHEMATIC 4501 133 2 6 AVME944X DIGITAL OUTPUT POINT CONFIGURATIONS 4501 134 2 7 944 INTERFACE TO TTL AND CMOS SIGNALS 4501 137 3 3 AVME944X INPUT RESPO NSE AND INTERRUPT TIMING DIAGRAM 4501 124 4 1 AVME944X BLOCK DIAGRAM 4501 12 AVME944X SCHEMATIC PART LOCATION DRAWING 4501 129 AVME944X LED EXPANSION BOARD SCH amp PART LOC DRAWING 4501 136 APPENDIX A 0 CABLE AND TERMINATION 5 CABLE MODEL 9944 x A 2 TERMINATION PANELS MODELS 6985 16DI AND 6985 16 9944 FLAT 64 PIN CABLE 4501 135 6985 16DX SCHEMATIC amp PART LOCATION DRAWING 4501 126 6985 16DX MOUNTING CLEARANCE ELECTRICAL CONNECTIONS 4501 127 AVME9440 9
13. Part numbers are given below for the various cable components Use these references if you wish to assemble your own cables MODEL 9944 x 0011 100 Use to connect 6985 16Dx termination panel to the AVME944x board both have 64 pin connectors CaO tre 64 wire flat ribbon cable 28 gauge Acromag Part 2002 210 3M Type C3365 64 or equivalent Length Last field in part number designates length in feet specified by user 12 feet maximum Headers Both Ends 64 pin header female includes strain relief Header Acromag Part 1004 686 Panduit Type 120 064 435 or equiv Strain Relief Acromag Part 1004 682 Panduit Type 120 000 032 or equiv 66000 Headers both ends have polarizing key to prevent improper installation Schematic and Mech Dimensions See Drawing 4501 135 Shipping 1 0 pounds 0 5Kg packed A 2 TERMINATION PANELS MODELS 6985 1601 AND 6985 16DO Type Termination Panels For AVME944x Board 6985 1601 6985 1600 panel facilitates the connection of up to 16 field input output signals and connects to the AVME944x board via a flat ribbon cable Model 9944 x Field signals are accessed via screw terminal strips Optionally the user may connect a 5 to 55 DC supply to the B and B power screw terminals to provide a common supply reference for 1 channels e g a 5V DC supply would be usefu
14. 10 Each model has a unique number uL Cee o f 3 of KILOBYTES of address space used lt lt lt pedi 21 dit Undefined Reserved 15 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 3 1 2 Board Status Register read write 81H The Board Status Register reflects and controls functions globally on the board MSB LSB 7 6 5 4 3 2 1 0 lt Reserved Software Global Global Green Red Reset Int Int LED LED Enable Pending Where Bits 7 6 5 Reserved for future use equal 0 if read Bit 4 Software Reset W writing a 1 to this bit causes a software reset Writing 0 or reading the bit has no effect The effect of a software reset on the various registers is described in the description of each register Reset Condition Set to 0 Bit 3 Global Interrupt Enable R W writing a 1 to this bit enables interrupts to be serviced provided the interrupt level IRQx is selected A 0 disables servicing interrupts Reset Condition Set to 0 interrupts disabled Bit 2 Global Interrupt Pending R this bit will be a 1 when there is an interrupt pending This bit will be 0 when there is no interrupt pending Polling this bit will reflect the board s pending interrupt status even if the Global Interrupt Enable bit is set to O Reset condition Set to O Bit 1 Green LED R W when w
15. board be returned to Acromag for repair Acromag uses tested and burned in parts and in some cases parts that have been selected for characteristics beyond that specified by the manufacturer Acromag has automated test equipment that thoroughly checks the performance of each board When a board is first produced and when any repair is made it is tested placed in a burn in room at elevated temperature and retested before shipment Please refer to Acromag s Service Policy Bulletin or contact Acromag for complete details on how to obtain parts and repair 5 2 PRELIMINARY SERVICE PROCEDURE Before beginning repair be sure that all of the procedures in Chapter 2 Preparation For Use have been followed The procedures are necessary since the board has jumpers that must be properly configured CAUTION POWER MUST BE OFF BEFORE REMOVING OR INSERTING BOARDS Note It has been observed that on occasion a boot program for a disk operating system will hang waiting for the VMEbus SYSFAIL signal to be released by an intelligent disk controller board Acromag s non intelligent slave boards assert SYSFAIL signal as described in the VMEbus Specification Rev C 1 and therefore the disk operating system will remain hung The best solution to this problem is to correct the boot program so that itis no longer dependent upon the SYSFAIL signal When this solution is not practical it is possible to disconnect the SYSFAIL from the circuitry on t
16. input and enable bits Hence an input channel that does not have interrupts enabled cannot have its interrupt pending bit set to a 1 An individual channel s interrupt can be cleared by writing a 1 to its bit position in the interrupt status register However if the condition which caused the interrupt remains or reappears a new interrupt will be generated To permanently disable a channel s interrupt the corresponding bit in the channel interrupt enable register must be cleared followed by writing a 1 to the channel s bit position in the channel interrupt status register to clear the interrupt This is known as the Release On Register Access RORA method as defined in the VME system architecture Bit 7 of this register has a dual purpose In addition to indicating an interrupt for channel 7 it is also used to indicate an input channel bit pattern match see the digital input channel interrupt pattern enable register All interrupts are cleared following a reset NOTE Interrupts are prioritized via hardware within the card Channel 7 is the highest priority and channel 0 is the lowest If multiple input channel interrupts become pending simultaneously the vector corresponding to the 17 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS highest numbered channel will be delivered first After the highest channel s interrupt is serviced and cleared an additional interrupt will be generated for the next highest priority interru
17. 2 31400830 CHAWIXBN 502 SMT 3 42 3SNOdS3Y LNdNI HGAO LO Ldf331NI ONY RECEN 3SNOdS34 104 1 6340 3930914 k 9914 140 44 TINNOHI 1 71911914 318173 0 311 TINNOHO 1 71911914 015 21901 1 0111 1911914 b s a E kO 911241 LANYMILNI ONY 35 04534 0411 5532044 3NNUHO 10 11 1611919 15 a31s1933 sniuisL LaNAXILNI indNI 91910 H 5 51935 NOIlU NOI12313S 1 1 1 49130 LAdNI Eu 10911910 91901 1109419 4 0 3141 31400830 43151934 3718UN3 43151934 1 9194 TINNOHI 40 111 40 1 1911914 1911914 32019 31000830 1 918 1 1941919 0314008930 10141530 2 32012 19 915 80123NN02 1fldNI 31u9 1911914 21901 bd 11921140 011051 44908 03191051 0 3333308 194915 LNdNI 71911914 191051 SNINWILS 13 9 104 1 719119140 19 915 50101115 1 1911914 38 Xrre3unu d Pea CE WUZIOVIO 52018 COCR ANCER E CON WON 2
18. 24 9234 PO Box 437 Wixom MI 48393 7037 USA Copyright 1992 1995 Acromag Inc Printed in USA Data and specifications subject to change without notice AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS TABLE OF CONTENTS CHAPTER 1 0 GENERAL 000 INTRODUC TON EN 1 2 DIGITAL INPUT FEATURES 9440 1 8 9447 1 3 DIGITAL OUTPUT FEATURES 9440 1 amp 9443 1 1 4 VMEbus INTERFACE FEATURES n 18 11 trt Plan tii ave EE 1 5 2 Digital OUtpUts edet A ETHER aa 2 0 PREPARATION FOR USE ii 2 1 UNPACKING AND 2 2 CARD CAGE CONGIDERATIONS 2 3 BOARD CONFIGURATION i 2 3 1 Default Jumper Configuration a nennen nnns 2 3 1 1 Digital Input Default Configuration i 2 3 1 2 Digital Output Default Contftouraton 2 4 VMEbus CONFIGURATION i 2 4 1 Address Decode Jumper Configuration 2 4 2 Address Modifier Jumper 2 4 3 Interrupt Level Select Jumper Configuration 2 5 DIGITAL INPUT CONFIGURATION 9440 1 amp 9447 2 5 1 Digital Input Threshold Deiecton 2 5 2 Sensing Contact Closures and Gwiiches a 2 5 8 Debounce Delay Selecti
19. 3INIGN ES EZ 1208 ns Lea 1000 1008 Her 5008 210 Ke Sod8 Hino 13S 529 ST 2008 HInon 69 F Tova HINON 8 0 2v 2098 1110135 0210 gus eeor LES Cova 29 ren 8 08 JINON 9 5098 H9813S 8 9 T SLING CEN 590 909 GES 650 2 209 INTE 5 8 809 a 28 5 609 H8 8210 EE GIONI 35809 28 28 NODI dINISM 95 dINIGN ER SS TSd 13538 sE d ZE EE 82 St THY A 4 DYIILNI de ES 249 016 OTt SINTEM S2 i St OT voor SINIGH o5 ES 1103 SU 03 sr 8 9r NDIOUI SE FE ON EE SEC ON 13534545 62 H8 IS 05 3515501 95 dN NS p 928 9944 300930 5534409 8 4 1 INN 909 P00T 1389206 221d 361 42 2 63140 1 se een 0 0 2 1911910 03191051 1 2920 2 6d 4 T 6d is3Dhb GT 1150 901110 EONIA PONTO SONIO 391110 91120 8eNIO TINIQ 2TNIG ETNIG Bak Ee AS d 3Nod I 3155 62 1004 TT PS ns SE SS 1 ITE MEE ON 88 I PE ON Zeil Lee oN ss 155 2 23 1 SS ON ONES 426 007 A ON INTE ES 01350 di ES 1359 NTS 271350 SE te Pao N27 ste ceor EL Au vr ET van The N OT Ilse 31848 1 Hee MET 90141 050 Er TONI 95 0 25 CONI S
20. 443 9447 ISOLATED DIGITAL I O BOARDS 1 0 GENERAL INFORMATION 1 1 INTRODUCTION The AVME944x Series of VME cards offer a variety of features which make them an ideal choice for many industrial and scientific applications Digital In m Out EA EE _AVME9443 9 43 14 1 AW MIE 44 zi 7594 x General Features All Digital Inputs and Outputs are optically isolated from the VMEbus and from each other 250 VAC Field connections accessible through connectors mounted on the Front Panel Can be interfaced to TTL amp CMOS logic PASS FAIL status indicator LEDs on the front panel Optional Termination Panels 1 2 DIGITAL INPUT FEATURES 9440 1 amp 9447 1 16 input points configured as a 16 bit word Input range of up to 55 VDC over 2 selectable ranges Optically coupled logic gates Adjustable debounce circuitry Generation of interrupts for channels 0 through 7 input Change Of State COS input level polarity match or input pattern detection e Input channel ON indicating LEDs with L option 1 3 DIGITAL OUTPUT FEATURES 9440 1 8 9443 1 e 16 output points configured as a 16 bit word e Ability to read back output states for complete confidence in the output setting the output should be fed back to an input point and the input point monitored Outputs sink up to 1 Amp DC from up to a 55 VDC source e Solid State Re
21. A08 31A 12V 32A 5V Indicates that the signal is active low WINI 4A 5A 6A 8A gt gt N T e 12A MA LA 16A LL TA a ee 20A 12232142 22A l NEC le red __ lt 32 __ Refer to the VMEbus specification for additional information on the VMEbus signals 2 9 POWER UP TIMING AND LOADING The 944x board uses a Logic Cell Array to handle the bus interface and control logic timing Upon power up the Logic Cell Array automatically clocks in configuration vectors from a local PROM to initialize the logic circuitry for normal operation This time is measured as the first 145 mS typical after the 5 Volt supply raises to 32 5 Volts at power up If a data transfer is attempted during this time it will simply be ignored and the board will not respond This should not be a problem because the VME specification requires that the bus master drive the system reset for the first 200 mS after power up thus inhibiting any data transfers from taking place 12 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS Digital input and output channels are reset to the OFF state following a power up sequence External input signals above threshold levels can then drive inputs ON Likewise writing to the digital output registers can program outputs ON 2 10 DATA TRANSFER TIMING Data tra
22. Acromag Series 9440 9443 9447 Isolated Digital I O Board USER S MANUAL ACROMAG INCORPORATED 30765 South Wixom Road P O BOX 437 Wixom MI 48393 7037 U S A Tel 248 624 1541 Fax 248 624 9234 8500 309 D01E001 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS The information in this manual is subject to change without notice Acromag Inc makes no warranty of any kind with regard to this material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Further Acromag Inc assumes no responsibility for any errors that may appear in this manual and makes no commitment to update nor keep current the information contained in this manual No part of this manual may be copied or reproduced in any form or by any means without the prior written consent of Acromag Inc IMPORTANT SAFETY CONSIDERATIONS It is very important for the user to consider the possible adverse effects of power wiring component sensor or software failures in designing any type of control or monitoring system This is especially important where economic property loss or human life is involved It is important that the user employ redundancy and comprehensive failure analysis to insure a safe and satisfactory overall system design It is agreed between the Buyer and Acromag that this is the Buyer s responsibility ACROMAG INCORPORATED Tel 248 624 1541 30765 South Wixom Road Fax 248 6
23. ES creat v pe 100 e SOW OLY 51109413 LNdNI 1911914 FH 28 Leica 9 29 5 ns STS EEOT SH2 TSONI STS EEOT 9H2 N3d0 69 5 ns Di F a str 9H2 1191051 T3NNVHO OL 290082 STS EEOT Dm LONI EA N3d0 OTD S 5 8206 9011 128 001 gtr 1191051 TINNUHI Ol 13 9 2 290082 01291051 10d100710dNI WLISTA 290052 50 A 44908 0 1 71911910 03191051 QNhONO 1911910 51102419 LNdNI 1911914 8HO 9Ta vd 8 STU bd 6 vTa vd N3d0 219 6H9 P TU bd NOILY OSI TINNVHO 01 290042 1 1 1 t STS EEOT S22 901T 522 0011 Men 128 01 KEEN S28 rooT EB a TTHO 9 1191051 713NNUHO Ol TANNYHD 2900682 D D D D D D 0 D 0 D D 0 D D D D 4 D D 0 D 0 a D D D D D 1402 051 104100 104 1 1911919 290082 51 pe cem IE 08 O I 71811910 03191051 DD java fora al bw A ONNOZ9 911914 51102419 LNdNI 1911914
24. I ino 100 100 100 NI 1no 110 SEST OL FREI 894 01 229 186 01 SEE NI ino ino 100 8 01 9 9338 Y 8521998 Sn SHIA er er er Aviad iT 310N 01123135 930 300930 20 55 02 NSz v var er T3NNeHO 19013135 73031 1404431 1 4908 Ten en erra Teen een Teen er TIC ETT str IC 6 cer Ten en em en em em OTT ZIC DIC 02 ber 31 4501 125 944 WIXOM MICH OUTPUT CHANNELS i AVME944x AVME944x AVME944x FRONT PANEL MAIN BOARD LED BOARD STEP 1 NYLON 6 D INSERT NYLON SCREWS ITEM A THRU PLACES MAIN BOARD INTO SPACERS ITEM B 3 PLACES AND TIGHTEN EJECTOR KNOBS REMOVED FOR CLARITY STEP 2 INSERT LED BOARD S LEDS INTO FRONT PANEL LED INSERTION HOLES ROTATE LED BOARD TOWARDS MAIN BOARD CAREFULLY ALIGN FOUR 4 9 PIN SOCKETS TO FOUR 4 9 PIN HEADERS amp GENTLY PRESS LED BOARD ONTO MAIN BOARD UNTIL SOCKETS AND HEADERS ARE SEATED STEP 3 INSERT NYLON SCREWS ITEM A THRU LED BOARD INTO SPACERS ITEM B 3 PLACES AND TIGHTEN FIGURE 2 2 AVME 944x LED BOARD TO MAIN BOARD MECHANICAL ASSEMBLY FOLLOW STEPS IN REVERSE ORDER FOR DISASSEMBLY 82 m TEI TOS r40 T 2 3 AIMS
25. NOI 104 1 ONY S 3NNUHO HIHI SQU31 251 143229 HOnONHl WNOILdO SI OSY 349 TY TES F00T 9UMONDU 3 881 1900 TEL 1894 9UHONDU 349 SYSEWAN 11910 13035 7119 9 5 2 E 931014 STT TOOT QU 054 XS 87 9 310N 335 5 00 QN9 8 DIMENSIONS INCHES MILLIMETERS TOLERANCE 0 020 0 5 CONTACT CLOSURE ISOLATED SUPPLY 6985 16Dx TERMINATION PANEL MOUNTING CLEARANCE AND ELECTRICAL CONNECTIONS 60 WIXOM MICH Acromag ovs CLOSURE COMMON SUPPLY
26. NSPECTION Inspect the shipping carton immediately upon receipt for evidence of mishandling during transit If the shipping carton is severely damaged or water stained request that the carrier s agent be present when the carton is opened If the carrier s agent is absent when the carton is opened and the contents of the carton are damaged keep the carton and packing material for the agent s inspection AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS For repairs to a product damaged in shipment refer to the Acromag Service Policy to obtain return instructions It is suggested that salvageable shipping cartons and packing material be saved for future use in the event the product must be shipped The board is physically protected with foam and electrically protected with an antistatic bag during shipment It is advisable to visually inspect the board for evidence of mishandling prior to applying power CAUTION SENSITIVE ELECTRONIC DEVICES USE ANTI STATIC HANDLING PROCEDURES 2 2 CARD CAGE CONSIDERATIONS Refer to the specifications for bus loading and power requirements Be sure that the system power supplies are able to accommodate the additional requirements within the voltage tolerances specified Adequate air circulation must be provided to prevent a temperature rise above the maximum operating temperature Large and continuing fluctuations in ambient air temperature should be avoided If the installation is in an industrial environment a
27. O 9565 5205 1712 60 9944 91901 TANNUHD 112 44 leet 83 wl o ke vo BEE 16 AM WLISTG 19 60 ON 8 96r 0otoT y TS EEOT 921 TeoT gz 24 011971051 OL TANNYHD 2901052 511 3419 19 00 LNdino 2H9 1911914 9821 1001 S6 OEOT S23 vooT 2H9 1191051 J3NNUHO OL 290052 927 7007 8668 0601 1191051 J3NNUHO 017 IANNYHD 2900420 289 5001 EE 402 1092 104100 104 1 7911914 290052 ns 1 0022 2 bows ns 7100135 771700 13938 110035 0008 Toda coda 008 veda 5006 eaa 008 1 1 x A B 621 1089 61102 48908 0 1 71911910 03191051 pu sive Slee 15613 DOWODY LIII LL suol FT9 EEQT 92 1 1001 EON sa 2 nz 96b 0EOT S ua SS 5 An NOIL1U1OSI 01 n 290082 i FTS EEOT SH2 941 1001 sa r 2 ena 85 0 01 T 5 T 8n NOILU10SI 13 01 7 5111981 MANNYHI 290082 i 104110 SE SC LV ID H 1 11914 i
28. PARTS UNIQUE TO THIS MODEL COMPONENT ACROMAG PART NUMBER DESCRIPTION UT DR RR i NUMBER he a 9 1004410 POSTS 1 ROW2PO0S TABLE 5 10 PARTS LIST FOR MODEL AVME9447 I MAIN BOARD PARTS UNIQUE TO THIS MODEL COMPONENT ACROMAG PART NUMBER DESCRIPTION REFERENCE NUMBER RES FILM 5 25W 2 7K OHM po 1004410 POSTS 1 ROW2POS 27 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS TABLE 5 2A PARTS LIST FOR MODEL AVME9440 I L LED EXPANSION BOARD PARTS UNIQUE TO THIS MODEL COMPONENT ACROMAG PART NUMBER DESCRIPTION wi NUMBER ua 1033 279 IC SN74LS645ND 1100 636 RES NET 2 9 COM 560 OHM 1100 490 RES NETWORK 9 1K TABLE 5 2B PARTS LIST FOR MODEL AVME9443 I L LED EXPANSION BOARD PARTS UNIQUE TO THIS MODEL COMPONENT ACROMAG PART NUMBER DESCRIPTION e NUMBER R2 1100 636 RES NET 2 9 560 OHM 01 16 1001 198 DIODE RED 3MM 1004 645 SOCKET 9 PIN SINGLE ROW TABLE 5 2C PARTS LIST FOR MODEL AVME9447 I L LED EXPANSION BOARD PARTS UNIQUE TO THIS MODEL COMPONENT ACROMAG PART NUMBER DESCRIPTION a E NUMBER VEER 1 1033 279 IC SN74LS645ND 1100 490 RES NETWORK 9 1K 1002 530 CAP MONO 0 1UF 100V Z5U D17 32 1001 199 DIODE GREEN 3MM 1004 645 SOCKET 9 PIN SINGLE ROW 28 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 6 0 SPECIFICATIONS Operating Temperature 0 to 70 deg C Storage Temperature 25 to 85 deg C Relative
29. VMEbus INTERFACE The VMEbus interface is composed of three functional circuit areas e Data buffers U54 U55 e interrupter 051 056 057 062 063 Address decode and bus control logic 951 058 059 060 4 1 1 VMEbus Control Logic The Data Transfer Acknowledge DTACK signal is generated by the logic timing circuitry 051 058 on the board for handshaking with the bus master during data transfer cycles The DTACK signal will be asserted after the card address has been properly decoded and either of the data strobes DS1 050 is asserted The amount of delay before DTACK is asserted is controlled by circuitry within 051 which uses the SYSCLK 16MHz provided on the VMEbus to derive a fixed time delay AVME944x does not use assert the VME BERR signal as permitted in the VMEbus specification If the bus master improperly addresses the board it will not get a response however the VMEbus Bus Timer located in the System Controller will time out and cause an end to the cycle 4 1 2 VME Interrupter The interrupt level IRQx associated with the card is programmable via a jumper on the board The card will return an 8 bit interrupt vector during the interrupt acknowledge cycle Each interrupting channel can have its own interrupt vector The interrupt release mechanism is the Release On Register Access RORA type This means that an interrupter will release the interrupt request line IRQx after the interrupt has been c
30. al relay contacts or switches are used as inputs it is strongly recommended that a debounce delay longer than the maximum expected bounce time be used If the bounce time cannot be determined then the maximum debounce delay should be selected The debounce delay time is jumper programmable J7 on a global basis for all input channels i e all input channels will have the same delay as shown in the following table Debounce Delay J7 J7 J7 J7 Time uS 1 amp 2 38 4 58 6 7 amp 8 NOTE One of the debounce delay times must be selected If none or more than one delay time is selected the input signals will not pass through the debounce circuit 2 6 DIGITAL OUTPUT CONFIGURATION 9440 amp 9443 1 The Digital Outputs are designed to control valves switch counters mechanical relays optical relays indicator lamps etc Each digital output can be written to and then read back immediately for verification purposes but for complete confidence in the output setting the output should be fed back to an input point and the input point monitored See Figure 2 5 for the simplified schematic of a digital output point Outputs include reverse bias protection and a replaceable fuse requires soldering Output loads of up to 1 Amp DC and voltages up to 55V DC are supported 2 6 1 Relay Coils and Other Inductive Loads When driving relay coils or other inductive loads diodes should be placed across each load to limit the voltage spike generate
31. ctor gt RIW Int Vector CH5 gt Vector CHE RIW Int Vector CH7 2 B1 Undefined Undefined Undefined Interrupt Status Register CH7 CHO C1 R W Digital Input Channel Undefined Interrupt Enable Register CH7 CHO C3 Undefined R W Digital Input Channel Interrupt Polarity Register CH7 CHO C5 Undefined R W Digital Input Channel Interrupt Type Select Register CH7 Int Pattern Enable Register CH7 CHO ee R Digital Input Channel Data Register R W Digital Output Channel Data Register CF Undefined Undefined JU 3FF 14 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 3 1 1 Board Identification PROM read only 01H through odd The board contains an identification section This section of data describes the board model number and the manufacturer The identification section starts at the board s base address plus 1 and is 32 bytes in length Bytes are addressed using only the odd addresses between 1 and 63 The PROM contents are shown in Figure 3 2 for an AVME9440 I L each model has a unique PROM Figure 3 2 AVME9440 I L Board Identification PROM From Board ASCII Base Address Character OH V 56H Allboadshave VMEID OH LML 4DH ra 0 OA ea FA Eo fera zi Manufacturer s LD ACR for Acromag OH 52H RM prin i UH 19 39H Board Model Number 6 characters TH
32. cuit board Thickness 0 063 inches OPERATING CONDITIONS Operating Temperature 0 to 70 deg C Storage Temperature 25 to 85 deg C 56 ESSO z ERE S Sof 8 rs 2 2 z 5 lt amp _ o 2 HE Oo 3 56 9 Pi ox 8 z z AN t 2 5 2 d ae 555 3 UE TIT 52 88 lt zzo 588 8 E lt ul m o z z EN e a gt gt i 8 xk 8 qu 5 5 3 pu lt il z 9 9 9359 9 999 9 A Z SS 2 2 papast 73 a X ZA ALY v 2 Bet 2225 og gt MODEL 9944 x SCHEMATIC 57 Lad 2407 awn saki 19301 518494 ONY 5 011040 3 XGST S869 nu 8 REE SES 8TOT 0 08 I d 091 5869 Hen MOXIM OUT o r gt z m 5 8 4 8 5 r E T 9 58 Tree 119301 513494 ONY OIIUHJ3HOS 1011904 43 XOST S9869 suma ve e gt pruon 16 ay SES 8TOT SI 884908 I d 681 OND Ol N31S3HHU Y N04 1015 9 ONY 499 UdS F90 0 9 SNIVI
33. d when an inductive load is switched off quickly See Figure 2 6 Digital Output Point Configurations for connections for different output types AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 2 7 DIGITAL INPUT OUTPUT INTERFACE TO TTL AND CMOS SIGNALS Logic level inputs can be interfaced to the board by the use of common logic elements such as the 741505 74HC05 open collector drain inverter gates See Figure 2 7 Interface to TTL and CMOS Signals for connection information Applying a logic 1 to the input of the inverter gate sinks the current required to turn the optically coupled logic gate on using the lowest input voltage range and yields a logic 1 for the corresponding input channel register bit position Logic level outputs are easily interfaced by the use of 74LS04 or 74 04 inverter gates Programming a logic 1 in the corresponding output channel register bit position turns on the output SSR which pulls the input to the inverter gate low This yields a logic 1 at the output of the inverter gate 2 8 CONNECTORS 2 8 1 Digital Input Connector Digital inputs are connected to the 944x via connector P4 lower connector as viewed from the front Table 2 1 defines the assignment These connections are easily accommodated through the use of Acromag termination panels and flat cable assemblies or through the use of a user defined termination panel P4 Panduit No 100 532 053 Series 100 Type B Male Connectors r
34. e 1 tick of uncertainty NOTE 2 Input Data Register Response time is derived by multiplying the period of the selected debounce clock by one NOTE 3 Total Input Channel Response time is calculated by summing the input optical gate debounce and data register response times for the debounce clock selected DIGITAL OUTPUTS Output Points per Card 5 16 9440 1 amp 9443 1 QuIput SAN eee teret adi qued Solid State Relay 558 Form A SPST NO Single Pole Single Throw Normally Open Output OFF Voltage Hangoe 0 to 55V DC in a single range Output OFF Leakage Current 5uA DC maximum 55V DC Output ON Current Range 0 to 1 Amp DC 0 to 40 deg C Derate ON Current Above 40 C 10mA per deg C Output ON Voltage 1 Amp 0 5V DC maximum Output Response Time 1 Amp 2 0mS maximum Logic Compatibility esce Can be interfaced to TTL and CMOS See Section 2 7 Output cameo gest temet teme aueh vus F1 16 PICO 2 AMP No 255002 Output ON Indicating LED 16 red LEDs front panel driven by the input signal to the SSR with L option only ISOLATION VOLTAGE Between individual digital I O channels and between all digital 1 chann
35. e J2 and J1 decode the fourteen most significant address lines A10 through A23 to provide segments of 1K address space The configuration of the jumpers for different base address locations is shown below IN means that the pins are shorted together with a shorting clip OUT indicates that the clip has been removed J2 decodes address lines A10 through A15 and J1 decodes Address lines A16 through A23 Therefore when configured for the Short 1 Address space only J2 needs to be configured Pins of J2 BASE ADDR A15 A14 A13 A12 A11 A10 HEX 11 amp 12 10 amp 9 8 amp 7 6 amp 5 4 amp 3 2 amp 1 OUT OUT our OUT OUT Ern i ls lr al Pins of J1 BASE ADDR A23 A22 A21 A20 A19 A18 A17 A16 HEX 15 amp 16 K 381 14 re 1 12 0 7 amp 8 5 amp 6 3 amp 4 1 amp 2 TESE E a ai a AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 2 4 2 Address Modifier Jumper Configuration The VMEbus Address Modifier jumpers J3 J5 and J6 permit the board to respond to the various Address Modifier Codes Pins of J3 J5 J6 J3 J5 J6 2 amp 3 1 amp 2 1 amp 2 Address Modifier Code Function IN IN IN samana and Short Non privileged Access IN IN OUT 3DH amp 39H Standard Supervisory Data Access _ and Standard Non privileged Data Access 2 4 8 Interrupt Level Select Jumper Configuration The board Interr
36. e B and B power screw terminals User Configurable Panel Circuits See Drawing 4501 126 Slots to add pull up down resistors or jumpers or protection diodes from each channel to the B and B terminals Elte u ec c e e eee 250VAC or 354V DC Between all digital UO channels 250VAC or 354V DC Between all digital I O channels and the ground terminal Input Output Transient Protection See Drawing 4501 127 Connect a wire from chassis ground to the ground GND screw terminal on the panel PHYSICAL CHARACTERISTICS Shipping Weight 1 25 pounds 0 6Kg packed Mountings cars Surface mounting Leave sufficient space around the termination panel for wiring Mounting Hardware The termination panel is supplied with 0 375 inch standoffs All standoffs should be secured using No 6 hardware to provide maximum physical strength Field Power Wiring Terminal blocks with screw clamps Wire range 14 to 26 AWG Connections to AVME944x P1 Panduit No 100 532 033 Type B Male Connector rows A amp B equipped even pins only 32 pins total Use Acromag 9944 x cable keyed to connect panel to VME board Keep cable short to reduce power loss and noise Mechanical Dimensions See Drawing 4501 127 Printed Circuit Military grade FR 4 epoxy glass cir
37. eads low the LEDs will both be lit and SYSFAIL low This indicates the board is undergoing a diagnostic checkout If the status register bits 1 and 0 read high the green LED will be lit with the red LED off and SYSFAIL high This indicates the board is fully functional Status Bits Possible Usage Bit 0 Bit 1 Red LED Green LED SYSFAIL Description 0 on 0 off Failed or reset condition 3 1 3 Interrupt Vector Registers read write A1H to AFH Odd addresses The interrupt vector registers maintain the 8 bit interrupt vector numbers for each of the 8 digital input channel interrupt lines Note that interrupts can only be generated for digital input channels 0 7 The appropriate vector is provided to the VMEbus Interrupt Handler when an interrupt is being serviced This allows each digital input channel interrupt to be serviced by its own software handler If desired a single handler can be used by making all of the vectors the same In this case the handler will have to determine the interrupting channel by examining the interrupt status register The register content is undefined upon reset 3 1 4 Digital Input Channel Interrupt Status Register read write C1H The digital input channel interrupt status register reflects the status of the 8 input channels ch 0 7 A 1 ina bit position indicates an interrupt is pending for the corresponding channel Each bit is derived from the logical AND of its associated interrupt
38. els and the VMEbus 250V AC or 354V DC on a continuous basis will withstand 1500V AC dielectric strength test for one minute without breakdown Complies with test requirements outlined in ANSI C39 5 1974 for the voltage rating specified 30 0119201 0119201 33dHhf un 553229 9198 Q393 71InISNd NON QNUQONUIS ONY 553229 VIVO AYOSINYIANS QNUONUIS HSE 9 553229 9194 0 5 AINO HOE 553229 Q393InIHd NON LYOHS ONU 553229 51083405 LYOHS 62 553229 AMOSINYIINS LYOHS 100 NI ino NI 100 NI 100 100 100 NI 1no 1no 90 1 Q710HS33H1 3011ISOd 1406949999 149984999 1499149999 11909 9906 1190239990 1499919999 1490999999 1499899999 1499199990 1499999909 25311936 3 2101 9 61219 55384009 919 TTY ety FIH STU 598 30 SNId T 3014 335 2 455 1909994090 1499993499 1499990400 1499902499 1499996999 1499902999 1499991990 1199999999 29 Tj 96 8951892 0196 219 TTT SET 919 ST 5538909 STU 219 819 619 Tey 3508 Tf 30 SNId 9121 542 ONY 3015 3 JHL NO 5494 OML 11330 38 7103 Y ONILLND 3786193735 38 NUDO 119455 5 1no NI NI 100 01123135 TIOHS33H1 104 1 1911914 42 6 31400 T 2 3 914 1no 1no 100 N
39. en to the value written is represented on the output channels A 0 means that the corresponding output channel s Solid State Relay SSR is open off A 1 means that the SSR is closed on 19 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS Each digital output can be written to and then read back immediately for verification purposes but for complete confidence in the output setting the output should be fed back to an input point and the input point monitored MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH15 CH14 13 CH12 CH11 CH10 CH9 CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CHO All bits are set to 0 following a reset which means that the output SSR is OFF 3 2 GENERAL PROGRAMMING CONSIDERATIONS 3 2 1 Board Diagnostics The board is a non intelligent slave and does not perform self diagnostics It does however provide a standard interface architecture which includes a Board Status Register useful in system diagnostics Status bits control of front panel LEDs and control of the SYSFAIL signal are provided through the Board Status Register Bits 0 and 1 may be used as follows Bit 1 Bit 0 Green Red Signal lm ER Off On On has not been tested Board is being tested On Board has passed test Off Off At power up the system diagnostic software can test each non intelligent Slave sequencing the status bits to indicate undergoing test and then to passed or failed After testing each board the sy
40. errupt Example For Input Level Polarity Match Set interrupt level IRQx associated with the board via jumper J4 Clear the global interrupt enable bit in the Board Status Register by writing a 0 to bit 3 Write vectors into the Digital Input Channel Interrupt Vector Registers Select polarity level interrupts for channels by writing 0 to each channel s associated bit in the Digital Input Channel Interrupt Type Select Register N 24 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS Select the desired polarity level for input channel interrupts by writing 0 or 1 to each channel s associated bit in the Digital Input Channel Interrupt Polarity Register Disable input pattern detection interrupts by writing 0 to each channel s associated bit in the Digital Input Channel Interrupt Pattern Enable Register Enable individual input channel interrupts by writing 1 to each channel s associated bit in the Digital Input Channel Interrupt Enable Register Clear pending interrupt inputs by writing 1 to each channel s associated bit in the Digital Input Channel Interrupt Status Register Enable interrupts from the board by writing a 1 to bit 3 the global interrupt enable bit in the Board Status Register Interrupts may now occur from the board 3 3 83 Interrupt Example For Input Pattern Match Of Multiple Channel Levels 1 2 3 Set interrupt level IRQx associated with the board via jumper J4
41. hat an interrupt will only be generated if all enabled channels at least 1 and up to 8 channels forming the pattern meet the level requirements specified in the digital input channel interrupt polarity register providing that the global interrupt enable bit is set Note that when pattern interrupts are desired the digital input channel interrupt type select register bits must be set to 0 interrupt on input level not on change of state Note also that the interrupt generated will result in setting the status bit in the digital input channel interrupt status register which corresponds to channel 7 i e the highest priority channel All input channel pattern enable bits are masked 0 following a reset 3 1 9 Digital Input Channel Data Register read CAH amp CBH The digital input channel data register represents the actual state of the 16 digital input channels at the time the register is read note that the debounce circuit will insert a delay dependent on the degree of debounce selected A 0 means that the signal across the board s input channel connector is below threshold A 1 means that the signal is above threshold Note that the threshold voltage i e range is selectable MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 CH14 13 CH12 CH11 10 CH9 CH8 CH7 CH6 CH5 CH4 CH2 CH1 CHO 3 1 10 Digital Output Channel Data Register read write CCH amp CDH When the digital output channel data register is writt
42. he appropriate interrupt vector on the bus 000 007 if the level of the interrupt matches that sought by the host Note that IRQx remains asserted The host uses the vector to point at which interrupt handler to execute and begins its execution Example of Generic Interrupt Handler Actions A Disable the interrupting channel s by writing a O to the appropriate bits in the interrupt enable register B Clear the interrupting channel s by writing a 1 to the appropriate bits in the interrupt status register C Enable the interrupting channel s by writing a 1 to the appropriate bits in the interrupt enable register If the input stimulus has been removed and no other channels have interrupts pending the interrupt cycle is completed i e the board negates its interrupt request IRQx 22 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS A If the input stimulus remains a new interrupt request will immediately follow If the stimulus cannot be removed then the channel should be disabled or reconfigured e g for the opposite polarity B If other channels have interrupts pending then the interrupt request IRQx will remain asserted This will start a new interrupt cycle 4 0 THEORY OF OPERATION This chapter describes the circuitry that is used on the board A block diagram is shown in Figure 4 1 Parts lists are in chapter 5 and the schematic amp part location drawings are near the end of this manual 4 1
43. he Acromag board by cutting a PC board foil near the P1 connector on the solder side Caution should be exercised so as not to cut any other foils nor damage the board in any other way Call Acromag s Applications Engineering Department for assistance 5 3 PARTS LISTS Parts Lists are provided as an aid to the user in troubleshooting the Board also reference the schematic and part location drawings Tables 5 1A to 5 1D list the parts installed on the main board for the various models similarly Tables 5 2A to 5 2C list parts for the LED expansion board Replacement parts and repair services are available from Acromag Changes are sometimes made to improve the product to facilitate delivery or to control cost It is therefore important to include the Component Reference Number the Acromag Part Number the Board Model Number and the Board Serial Number when providing information to order parts 25 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS TABLE 5 1A PARTS LIST FOR MODEL AVME944x 1 MAIN BOARD PARTS COMMON TO ALL MODELS COMPONENT ACROMAG PART NUMBER DESCRIPTION Nc RR RN NUMBER i TT RES FILM 5 25W 180 OHM TABLE 5 18 PARTS LIST FOR MODEL AVME9443 I MAIN BOARD PARTS UNIQUE TO THIS MODEL COMPONENT ACROMAG PART NUMBER DESCRIPTION ei NUMBER U2 RES NET 2 9 COM 270 OHM 26 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS TABLE 5 1C PARTS LIST FOR MODEL 9440 1 MAIN BOARD
44. i i 09 29 EONI i 5810 les PONT OL SONI IN 08 SONI ili 920 22 ZONI Ge S SONT BE Ise SONI 10 E OTNI 260 ES TIN o 8 2TNI 22 Pa ETNI 610 3 V TNI 219 Sr STNI 08 133208 2214 361 9944 31400830 TINNOHI LOdNI 10911914 43 VECI 75 O I 1911910 03191051 pss RIM ta 4 1 1220 0008 6 Teaa8 er 2008 TT ET 1 08 5208 ST 9008 9T 2008 21 n ETT TOOT 13538 era Nall Soran 2 o galo 57 Suen lo 13s33Sn S 0 im zi se 1NISOHOn 0 NS NGI 8 EE NSAI a zs 82 NE 5 OE 13538 2 865 ONSET 8 MER ST pE aiz ENKEN T ST INTE 21 OVI DES DUJINI TZ ES Nall I 84S EEOT I ON Tova 62 ean S I 0 2098 es SES Eva RI Ty 8 E o o 92 99 ZUXAN 95 7 6 0 29 SE 15 INI 1124 I Kaz ST ANIG 2811 vs SINTAM IES 51410 F I IININM 6611 ES 110168 E 1128 JINIM 92 2 SINIGN ET SL SE 1 dINIGN oT 1118 SINTAM 8 168 SINIGN 6 TS 133205 5 02 ns ATI TTOS 9908 1908 2008 eaa voda 908 9908 2004 8008 6908 2108 1108 S108 991410 TONIO 191410 91420 01420 891410 TINIQ STNI
45. iated with the interrupting channel and assert the DTACK signal The interrupt vector registers are contained in U62 Both U51 and U63 control the addressing of the vector registers The board status register is in U51 All other interrupt configuration and status registers as well as input channel interrupt logic and priority encoding are in U63 U56 performs the board interrupt level decoding and U57 checks for a match of the bus interrupt level to the board interrupt level The IACKIN signal is monitored by 051 which controls both IACKOUT and DTACK signals 4 2 REGISTER LOCATION SUMMARY Local memory locations are implemented in various data registers on board The registers are located in the following devices Board Identification PROM U61 Board Status Register U51 Interrupt Vector Registers U62 Digital Input Channel Interrupt Status Register U63 Digital Input Channel Interrupt Enable Register U63 Digital Input Channel Interrupt Polarity Register U63 Digital Input Channel Interrupt Pattern Enable Register U63 Digital Input Channel Interrupt Type Select Register U63 Digital Input Channel Data Register U63 Digital Output Channel Data Register U1 U2 4 3 ISOLATION BARRIER Optical isolation is used to isolate all digital input and output channels from each other channel to channel and from the logic and VMEbus circuits 4 4 DIGITAL INPUT SECTION 9440 1 amp 9447 1 There are 16 digital input chan
46. ital Input Channel Interrupt Type Select 3 1 8 Digital Input Channel Interrupt Pattern Enable 3 1 9 Digital Input Channel Data Register 3 1 10 Digital Output Channel Data Register 3 2 GENERAL PROGRAMMING 0 3 2 1 Board DiagnosticS eene eee AAA C1 C1 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS CHAPTER TABLE OF CONTENTS 3 3 GENERATING INTERRUPTS i 3 3 1 Interrupt Example For 3 3 2 Interrupt Example For 3 3 3 Interrupt Example For Change Of State CO Input Level Polarity Match Input Pattern Match eene 3 3 4 Sequence of Events For an Interrupt i 4 0 THEORY OF OPERATION 4 1 VMEbus INTERFACE 4 1 1 VMEbus Control Logic 4 1 2 VME Interrupter 4 2 REGISTER LOCATION SU 4 3 ISOLATION BARRIER 4 4 DIGITAL INPUT SECTION EE 9440 1 amp DAAT 4 5 DIGITAL OUTPUT SECTION 9440 1 amp 9443 02 5 0 SERVICE AND REPAIR INFORMATION menn 5 1 SERVICE AND REPAIR ASSISTANCE i 5 2 PRELIMINARY SERVICE PROCEDURE 5 3 PARTS LISTS 6 0 SPECIFICATIONS
47. l for interfacing to TTL signals as shown in Figure 2 7 The panels have slots to add pull up down resistors or jumpers or protection diodes from each channel to the B and B terminals See Drawing 4501 126 6985 16Dx Schematic and Part Location Drawing for specifics Typical input and output channel configurations are shown in Figures 2 4 and 2 6 respectively If the application requires that channel to channel isolation be maintained then do not compromise this by making connections to a common supply i e the B and B terminals 55 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS Before connecting the 6985 16Dx termination panel to the AVME944x board connect a wire from chassis ground to the ground GND screw terminal on the panel see Drawing 4501 127 6985 16Dx Mounting Clearance amp Electrical Connections This wire ties the input output transient protection circuitry to ground MODELS 6985 16DI and 6985 16DO FEATURES Digital Input Channels Up to 16 channels with 6985 16DI Digital Output Channels Up to 16 channels with 6985 16DO Wiring Connectons See Drawing 4501 127 POWOL ipsc t E Optional user supply terminals B andB do not use if channel to channel isolation is required Supply Range 5 to 55V DC 3 Amps maximum for pc board foil traces Power On LED Illuminates if a 5 to 55V DC supply is connected to th
48. lays SSRs operate as Single Pole Single Throw SPST Form A relays Output channel ON output switch closed indicating LEDs with L option AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 1 4 VMEbus INTERFACE FEATURES Slave module A24 A16 D16 D08 EO Short I O Address Modifiers 29H 2DH H Hex Standard Address Modifiers 39H H Hex 1 1 7 interrupter jumper programmable interrupt level software programmable interrupt vectors for digital input channels 0 7 interrupt release mechanism is Release On Register Access RORA type e Decode on 1K byte boundaries 1 5 FIELD COMPATIBILITY See APPENDIX A for more information on compatible products 1 5 1 Digital Inputs Directly compatible with Acromag input termination panel Cable Model 9944 X Flat 64 pin cable female connectors at both ends for connecting the 944 to the 6985 1601 termination panel Termination Panel Model 6985 16DI Sixteen channel input digital termination panel 1 5 2 Digital Outputs Directly compatible with Acromag output termination panel Cable Model 9944 X Flat 64 pin cable female connectors at both ends for connecting the 944 to the 6985 16DO termination panel Termination Panel Model 6985 16DO Sixteen channel output digital termination panel 2 0 PREPARATION FOR USE This chapter provides information about preparing the Isolated Digital I O Board for system operation 2 1 UNPACKING AND I
49. leared by writing a 1 to the appropriate bit position in the input channel interrupt status register Interrupts can be generated by any of 8 digital inputs channels 0 7 Interrupt on selected input channel COS or polarity level match can be selected Alternatively interrupts on a pattern match of selected input channel polarities levels can be programmed Interrupts occur on a first come first served basis unless they occur at the same time If two or more interrupts occur at the same time then channel 7 has the highest priority channel 0 has the lowest If an input channel pattern match is generated the interrupt will appear in the channel 7 highest priority position Input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a specific input channel this could happen if multiple changes occur before the channel s interrupt is serviced 23 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS When an input channel interrupt condition is satisfied the interrupter logic will assert the pre programmed interrupt request level IRQ7 IRQ1 and then monitor the Interrupt Acknowledge Input IACKIN signal When IACKIN is asserted the logic compares the VMEbus address lines A1 to the pre programmed board interrupt level If the lines are not equal it will pass the signal along by asserting IACKOUT If the lines are equal it will then drive the data bus D08 O with the vector assoc
50. nd the board is exposed to environmental air careful consideration should be given to air filtering 2 3 BOARD CONFIGURATION The board may be configured in a variety of ways for many different applications Each possible jumper setting will be discussed in the following sections The jumper locations are shown in Figure 2 1 Note that if you have a model containing the LED Expansion Board L suffix it must be removed to change the digital input channel range jumpers J9 J24 See Figure 2 2 for the LED Expansion Board assembly instructions 2 3 1 Default Jumper Configuration VMEbus INTERFACE CONFIGURATION When a board is shipped from the factory it is configured as follows e VMEbus Short I O Address of 0000H e Set to respond to both Address Modifiers 29H and 2DH e Interrupt Level none Therefore even if interrupts are enabled no interrupts will be caused 2 3 1 1 Digital Input Default Configuration e 16 dedicated digital input points numbered 0 through 15 e All channels factory configured via jumpers for the 4 25V DC input range Minimum input debounce selected 2 3 1 2 Digital Output Default Configuration e 16 dedicated digital output points numbered 0 through 15 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 2 4 VMEbus CONFIGURATION 2 4 1 Address Decode Jumper Configuration The board interfaces with the VMEbus as a 1K block of address locations in the VMEbus Short I O Address Space or Standard Address Spac
51. ndition will be recognized Likewise if an input channel stimulus is programmed to the polarity level which should not cause an interrupt the board user should wait for the response time to pass before enabling interrupts from the channel see Figure 3 3 To do otherwise will capture an old signal which has not completely propagated through the circuit and cause an unwanted interrupt 3 3 1 Interrupt Example For Change Of State COS 1 Set interrupt level IRQx associated with the board via jumper J4 2 Clear the global interrupt enable bit in the Board Status Register by writing a 0 to bit 3 3 Write vectors into the Digital Input Channel Interrupt Vector Registers 4 Select COS interrupts for channels by writing 1 to each channel s associated bit in the Digital Input Channel Interrupt Type Select Register 5 Disable input pattern detection interrupts by writing 0 to each channel s associated bit in the Digital Input Channel Interrupt Pattern Enable Register 6 Enable individual input channel interrupts by writing 1 to each channel s associated bit in the Digital Input Channel Interrupt Enable Register 7 Clear pending interrupt inputs by writing 1 to each channel s associated bit in the Digital Input Channel Interrupt Status Register 8 Enable interrupts from the board by writing a 1 to bit 3 the global interrupt enable bit in the Board Status Register Interrupts may now occur from the board 3 3 2 Int
52. nels available on the board A jumper J9 J24 is used to select the DC input voltage range for each channel and an optically coupled logic gate U19 U34 detects the input state Input channel debounce circuitry is also provided U64 for each channel to eliminate glitches from the input signals These glitches are frequently caused by contact bounce in mechanical relays and switches Eliminating these glitches is desirable to prevent erroneous channel data and spurious interrupts The debounce delay time is jumper programmable J7 on a global basis for all input channels i e all input channels will have the same delay 4 5 DIGITAL OUTPUT SECTION 9440 amp 9443 1 There are 16 digital output channels available on the board Optically coupled Solid State Relays SSRs provide the single pole single throw normally open SPST NO relay function U3 U18 The SSRs cover the wide DC output voltage range without requiring range jumpers Digital outputs may be read back prior to the optical isolation for verification purposes Reverse polarity protection and a replaceable fuse soldering required are also provided for each channel 24 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 5 0 SERVICE AND REPAIR INFORMATION This chapter provides instructions on how to obtain service and repair assistance service procedures and component parts lists 5 1 SERVICE AND REPAIR ASSISTANCE It is highly recommended that a non functioning
53. nsfer time is measured from the falling edge of DSx to the falling edge of DTACK during a normal data transfer cycle REGISTER DATA TRANSFER TIME All Registers 580nS typical 2 11 FIELD GROUNDING CONSIDERATIONS The board is designed to isolate every input and output channel from each other as well as from the VMEbus This is intended to protect each channel and the VMEbus from voltage spikes and transients such as those caused by ground currents and pick up The isolation provides the ability to earth ground the field wiring without the concern of ground currents damaging the card cage electronics 3 0 PROGRAMMING INFORMATION This chapter provides the specific information necessary to operate the Isolated Digital I O Board 3 4 MEMORY MAP The board is addressable on 1K byte boundaries in the Short I O Address Space or Standard Address Space All Acromag VMEbus non intelligent slaves have a standard interface configuration which consists of a 32 byte board ID PROM and a Board Status register The rest of the 1K byte address space contains registers or memory specific to the function of the board The memory map is shown in Figure 3 1 Addresses in Hex 13 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS Figure 3 1 Board Memory Map Address Address Base Base HEX m D7 HEX DO 50 1 Undefined Board ID PROM sE EM Undefined Undefined 7E 7F 81 Let a Undefined Undefined gt TTT Int Ve
54. on 2 6 DIGITAL OUTPUT CONFIGURATION 9440 amp 9443 1 2 6 1 Relay Coils and Other Inductive 2 7 DIGITAL INPUT OUTPUT INTERFACE TO TTL AND CMOS SIGNALS 2 8 CONNECTORS devi e eee ita Pe T TO 2 8 1 Digital Input Connector 2 8 2 Digital Output 2 8 3 VMEbus 2 9 POWER UP TIMING AND LOADING 2 10 DATA TRANSFER TIMING 2 11 FIELD GROUNDING CONGIDERATIONS sss senses 3 0 PROGRAMMING 4 4 2 0222222 3 1 MEMORY MAP 3 1 1 Board Identification PDPROM a 3 1 2 Board Status 51 21 St tus BitsS USag6 ees 3 1 3 Interrupt Vector RegisterS ssn 3 1 4 Digital Input Channel Interrupt Status 890 3 1 5 Digital Input Channel Interrupt Enable 3 1 6 Digital Input Channel Interrupt Polarity 3 1 7 Dig
55. ows A amp B equipped even pins only 32 pins total Table 2 1 PA CONNECTOR 6B 10 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 2 8 2 Digital Output Connector Digital outputs are connected to the 944x via connector P3 upper connector as viewed from the front Table 2 2 defines the assignment These connections are easily accommodated through the use of Acromag termination panels and flat cable assemblies or through the use of a user defined termination panel P3 Panduit No 100 532 053 Series 100 Type B Male Connectors rows A amp B equipped even pins only 32 pins total Table 2 2 P3 CONNECTOR EEE 2 8 3 VMEbus Connections Table 2 3 indicates pin assignments for the VMEbus signals at the P1 connector The P1 connector is the upper connector on the 944x board as viewed from the front The connector consists of 32 rows of three pins labeled A B and C Pin A1 is located at the upper left hand corner of the connector 11 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS TABLE 2 3 P1 BUS CONNECTIONS NUMBER NUMBER NUMBER MNEMONIC MNEMONIC MNEMONIC DO 18 BBS 10 Do D10 D11 005 DI bdo 78 BGIOUT D D15 GND 9B BG2OUT 9C 10A SYSFAIL BERR 12A SYSRESET 13A LWORD 14A AMS 15A A23 16A A22 17A A21 18A A20 19A A19 20A A18 21A A17 22A A16 23A A15 25A A13 26A A12 27A A11 29A A09 30A
56. pt pending channel NOTE Input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a specific input channel this could happen if multiple changes occur before the channel s interrupt is serviced 3 1 5 Digital Input Channel Interrupt Enable Register read write C3H The digital input channel interrupt enable register provides a mask bit for each of the 8 input channels ch 0 7 A 0 in a bit position will prevent the corresponding input channel from causing an external interrupt A 1 will allow the input channel to cause an interrupt providing that the global interrupt enable bit is set All input channel interrupts are masked 0 following a reset 3 1 6 Digital Input Channel Interrupt Polarity Register read write 5 The digital input channel interrupt polarity register determines the level that will cause a channel interrupt for each of the 8 input channels ch 0 7 A 0 in a bit position means an interrupt will occur when the input channel is below threshold i e a 0 in the digital input channel data register A 1 in a bit position means interrupt will occur when the input channel is above threshold i e a 1 in the digital input channel data register Note that interrupts will not occur unless they are enabled The interrupt polarity register will have no effect if Change Of State COS interrupts are selected see the digital input channel interrupt type select
57. put channel 0 7 However if the user programs the same vector into all of the vector registers then the board will have a single interrupt handler The digital input channels are prioritized with respect to their interrupts Channel 7 is the highest priority and channel 0 is the lowest If multiple input channel interrupts become pending simultaneously the vector corresponding to the highest numbered channel will be delivered first After the highest channel s interrupt is serviced and cleared an additional interrupt will be generated for the next highest priority interrupt pending channel If an input channel pattern match is generated the interrupt will appear in the channel 7 i e the highest priority position in the interrupt status register Input channel bandwidth should be limited to reduce the possibility of missing channel interrupts For a specific input channel this could happen if multiple changes occur before the channel s interrupt is serviced When configuring and enabling interrupts the response time of the input channels should be considered The digital input channel response time is the sum of the response times of the optically coupled logic gate 1uS typical 705 maximum the debounce circuit 705 to 1 54mS user selected and the interrupt logic circuit 1uS to 192uS follows debounce selection as illustrated in Figure 3 3 The total response time must pass before an input channel stimulus matching an interrupt co
58. register All bits are set to 0 following a reset which means that the inputs will cause interrupts when they are below threshold 3 1 7 Digital Input Channel Interrupt Type Select Register read write C7H The digital input channel interrupt type select register determines the type of input channel behavior that will cause a channel interrupt for each of the 8 input channels ch 0 7 A 0 in a bit position means an interrupt will be generated when the input channel level specified by the digital input channel interrupt polarity register occurs A 1 in a bit position means an interrupt will occur when a Change Of State COS occurs at the input channel either low to high or high to low 18 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS Note that interrupts will not occur unless they are enabled All bits are set to 0 following a reset which means that the inputs will cause interrupts for the input channel levels specified by the digital input channel interrupt polarity register 3 1 8 Digital Input Channel Interrupt Pattern Enable Reg read write COH The digital input channel interrupt pattern enable register provides a mask bit for each of the 8 input channels ch 0 7 A 0 in a bit position will prevent the corresponding input channel from being part of a pattern of channels bits which can cause an interrupt A 1 will allow the input channel to be a component of a pattern which can cause an interrupt Note t
59. ritten this bit will control the state of the green LED on the front panel A 1 will turn it on a 0 will turn it off Reading it will reflect its current state Reset Condition Set to 0 green LED off Bit 0 Red LED R W when written this bit will control the state of the red LED on the front panel and the state of the VMEbus SYSFAIL signal A 1 will turn the LED off and set SYSFAIL high a 0 will turn the LED on and set SYSFAIL low Reading it will reflect its current state See Section 5 2 for additional information on using SYSFAIL Reset Condition Set to 0 red LED lit and SYSFAIL is set low 3 1 2 1 Status Bits Usage The status register bits 1 and 0 along with the green and red LEDs provide the user with a means of keeping track of a board s functionality in the system Since there is no intelligence on the board the host computer controls these bits The following paragraphs and summary table describe possible uses of the bits in the status register and the LEDs on the front panel On power up the bits in the status register read low with the green LED off the red LED lit and SYSFAIL low This indicates that the board has failed or that it has not been tested yet If the status register bit 1 reads low and Bit 0 reads high the LEDs will both be off and SYSFAIL high This indicates an inactive board 16 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS If the status register bit 1 reads high and Bit 0 r
60. se On Register Access type RORA user control of priority sense and enable DIGITAL INPUTS Input Points per Card 16 9440 1 amp 9447 1 Input Voltage 2 Selectable Ranges via jumper 4 25V DG 20 55V DC Kul e DEE 4 DC maximum 4 25V DC range 20V DC maximum 20 55V DC range 29 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS INputGurent ery ee 18 4mA DC typ 25V 4 25V DC range 4 7mA DC typ 55V 20 55V DC range Input Optical Gate Response 1uS typ 705 maximum Input Debounce Time See Note 1 4 Selectable Ranges via jumper 7 8uS 1 MHz debounce clock 336 to 38405 20 83KHz clock 672 to 76805 10 415KHz clock 1 344 to 1 536mS 5 208KHz clock Input Data Register Response 105 to 19205 See Note 2 Total Input Channel Response Time 9uS to 1 74mS See Note 3 Logic Compatibility eec Can be interfaced to TTL and CMOS See Section 2 7 Input ON Indicating LETe 16 green LEDs front panel driven by the optical gate outputs with L option only NOTE 1 Input Debounce times are derived by multiplying the period of the selected debounce clock by 7 to 8 i
61. stem software records which boards have failed and sets their status to indicate inactive By setting the board s status to inactive the SYSFAIL signal is released and may then be useful for an on line indication of failure by other boards Alternatively the system software could simply set the bits and therefore front panel LEDs to passed test as a visual indication that the presence of the board is recognized 3 3 GENERATING INTERRUPTS Digital input channels 0 7 can cause interrupts to be generated for a wide variety of conditions These include interrupts for e Change Of State COS of selected input channels Input level polarity match of selected input channels e Input pattern match of the levels of multiple input channels The interrupt level IRQx associated with the card is programmable via a jumper on the board The interrupt release mechanism is the Release On Register Access RORA type This means that the interrupter will release the interrupt request line IRQx after the interrupt has been cleared by writing a 1 to the appropriate bit position in the input channel interrupt status register 20 AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS The user has the option of having a single interrupt handler for the entire board or having each channel serviced by a separate software handler This is determined by what is written into the interrupt vector registers There is a unique register for each digital in
62. upt Level is selected by configuring jumper J4 as follows Interrupt 44 44 J4 Level 586 384 182 pg IN UE iN 2001 00 pror E gy seni INLINE 2 5 DIGITAL INPUT CONFIGURATION 9440 amp 9447 1 Selectable input threshold voltages make the digital input points adaptable to almost any application The inputs are designed for use with contact closures switches alarm trips and power supply ON OFF monitoring Input points are optically isolated from each other and from the VMEbus See Figure 2 3 for the simplified schematic of a digital input point Input channel debounce circuitry with selectable delay is also provided for each channel to eliminate glitches from the input signals These glitches are frequently caused by contact bounce in mechanical relays and switches AVME9440 9443 9447 ISOLATED DIGITAL I O BOARDS 2 5 1 Digital Input Threshold Selection Two input threshold voltages are selectable on a per channel basis by J9 to J24 to cover the input ranges from 4 to 55V DC as shown in the following table Channel Range J9 J24 J9 J24 Positive Threshold 182 283 Voltage Maximum 4 25V DC 20 55V DC 20V DC 2 5 2 Sensing Contact Closures and Switches The input voltage should be within the range listed in the previous table See Figure 2 4 Digital Input Point Configurations for connections for different input types 2 5 3 Debounce Delay Selection If mechanic

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