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1. Figure 2 3 gives the block diagram of the VEEK MT C5SOC board VEEK MT C5SOC is a Cyclone V SoC development board and a Multi touch LCD Camera Card MTLC combination connected via the HSMC connector MTLC module is not only equipped with a 7 LCD screen it also equips a 5 Megapixel digital image sensor module G sensor and Light sensor All these sensors connect to the FPGA device via the HSMC connector so they can be controlled and directly used by the FPGA device HSMC Cyclone V SOC Development Board CMOS Sensor ATERA Cyclone v Soc Mulit Touch NE Figure 2 3 Block Diagram of VEEK MT C5SOC KajasiC Terasic VEEK MT C5SOC User Manual 9 www terasic com Chapter 3 Using VEEK MT C5SOC This section describes the detailed information of the components connectors and pin assignments of the VEEK MT C5SOC 3 1 Using the Cyclone V SX SoC FPGA The VEEK MT C5SOC is composed of Cyclone V SoC development board and 7 touch panel daughter card In this combination the Cyclone V SoC development board which equips the FPGA device is considered as the main part Therefore it can refer to the User Guide http www altera com literature ug ug cv soc dev kit pdf of Cyclone V SoC development board on the FPGA device configuration and board setup 3 2 Using the 7 LCD Capacitive Touch Screen The VEEK MT C5SOC features a 7 inch capacitive amorphous TFT LCD panel The LCD touch screen offers resolution of 800x480 to provide
2. aei E ERR tas ana Naa EH eid ei E ere ED aa 17 4 2 Painter Demonstration 454500 p 17 4 3 Camera AppliCation ie Ere rere asas an Bb agama ass 21 4 4 Digital Accelerometer Demonstration oooooo nana 25 CHAPTER 5 APPENDIX sii 28 SM REVISION sU EIUS 28 5 2 Copyright State Meme 501i eh engan eerte aa HAN aa Ae eg Ye duree E Bala EE UU awe eng Nan 28 asic Terasic VEEK MT C5SOC User Manual www terasic com Chapter 1 Introduction of the VEEK MT C5SOC The Video and Embedded Evaluation Kit Multi touch on Cyclone amp V SOC Development Board VEEK MT C5SOC is a comprehensive design environment with everything embedded developers need to create processing based systems VEEK MT CSSOC delivers an integrated platform that includes hardware design tools intellectual property IP and reference designs for developing embedded software and hardware platform in a wide range of applications The fully integrated kit allows developers to rapidly customize their processor and IP to best suit their specific application The VEEK MT C5SOC features the Altera Cyclone amp V SoC development board targeting the Altera Cyclone V SX SoC FPGA as well as a capacitive LCD multimedia color touch panel which natively supports multi touch gestures A 5 megapixel digital image sensor ambient light sensor and 3 axis accelerometer make up the rich feature set The all in one embedded solution offered
3. ANY TS OK SIGN 1177 818B 8DA8 A068 5C33 BES 9139 77D8 4 C855 3B4B 6582 721C 9562 CD64 A358 OB19 40C2 15C8 B6C8 CASB 1 5 B549 C994 C296 DSFD ES3C SADE 3D83 8952 EDCF 0843 Figure 1 3 Content of license multi touch dat 2 Open your Quartus II license dat file in a text editor 3 Copy everything under license multi touch dat and paste it at the end of your Quartus II license file Note Do not delete any FEATURE lines from the Quartus II license file Doing so will result in an unusable license file 4 Save the Quartus II license file Terasic VEEK MT C5SOC User Manual www terasic com ANU S RAN 1 3 Getting Help Here is the contact information should you encounter any problem e Terasic Technologies e Tel 4886 3 575 0880 e Email support terasic com www terasic com Chapter 2 Architecture This chapter describes the architecture of the VEEK MT CSSOC including block diagram and components 2 1 Layout and Components The picture of the VEEK MT C5SOC is shown in Figure 2 1 and Figure 2 2 It depicts the layout of the board and indicates the locations of the connectors and key components 5 Megapixel Digital Camera Ambient Light Sensor 7 LCD Touch Panel ferasIC Figure 2 1 VEEK MT C5SOC PCB and Component Diagram top view asic Terasic VEEK MT C5SOC User Manual 8 www terasic com Figure 2 2 VEEK MT C5SOC PCB and Component Diagram bottom view 2 2 Block Diagram of the VEEK MT C5SOC
4. Demo Batch File Folder Painter Nemo batch The demo batch file includes the following files e Batch File test bat test bashrc e FPGA Configure File Painter sof e Nios II Program Painter elf B Demonstration Setup e Make sure Quartus II and Nios II are installed on your PC Power on the Cyclone V SoC development board e Connect USB Blaster to the Cyclone V SoC development board and install USB Blaster driver if necessary Terasic VEEK MT C5SOC User Manual 18 www terasic com ND S RA Execute the demo batch file test bat under the batch file folder Painter Nemo batch After Nios II program is downloaded and executed successfully you will see a painter GUI in the LCD Figure 4 2 shows the GUI of the Painter Demo The GUI is classified into three areas Palette Canvas and Gesture Users can select pen color from the color palette and start painting in the Canvas area If gesture is detected the associated gesture symbol is shown in the gesture area To clear canvas content click the Clear button Figure 4 3 shows the photo when users paint in the canvas area Figure 4 4 shows the phone when counter clockwise rotation gesture is detected Figure 4 5 shows the photo when zoom in gesture is detected Figure 4 2 GUI of Painter Demo Terasic VEEK MT C5SOC User Manual 19 www terasic com Figure 4 3 Single Touch Painting Figure 4 4 Counter clockwise Rotation Gesture Terasic VEEK MT C5SOC User Manual 20 www te
5. Valid tvd 480 th Setup time Tdsu 8 ns DATA Hold time Tdsu 8 ns Table 3 2 Pin assignment of the LCD touch panel Signal Name ins in Description I O Standard LCD BO C4 LCD blue data bus bit 0 2 5V LCD B1 D5 LCD blue data bus bit 1 2 5V LCD B2 A3 LCD blue data bus bit 2 2 5V LCD B3 A4 LCD blue data bus bit 3 2 5V LCD B4 E11 LCD blue data bus bit 4 2 5V LCD_B5 F11 LCD blue data bus bit 5 2 5V LCD B6 F8 LCD blue data bus bit 6 2 5V LCD_B7 F9 LCD blue data bus bit 7 2 5V LCD_DCLK E6 LCD Clock 2 5V LCD_DE C3 Data Enable signal 2 5V LCD_DIM F13 LCD backlight enable 2 5V LCD DITH H8 Dithering setting 2 5V LCD_GO D12 LCD green data bus bit 0 2 5V LCD G1 E12 LCD green data bus bit 1 2 5V LCD G2 D10 LCD green data bus bit 2 2 5V MajasiC Terasic VEEK MT C5SOC User Manual www terasic com ND S RA LCD G3 D11 LCD green data bus bit 3 2 5V LCD_G4 D9 LCD green data bus bit 4 2 5V LCD G5 E9 LCD green data bus bit 5 2 5V LCD_G6 B5 LCD green data bus bit 6 2 5V LCD G7 B6 LCD green data bus bit 7 2 5V LCD_HSD C12 Horizontal sync input 2 5V LCD MODE G8 DE SYNC mode select 2 5V LCD POWER CTL G10 LCD power control 2 5V LCD_RO A13 LCD red data bus bit 0 2 5V LCD R1 B13 LCD red data bus bit 1 2 5V LCD R2 C9 LCD red data bus bit 2 2 5V LCD R3 C10 LCD red data bus bit 3 2 5V LCD R4 B8 LCD red data bus bit 4 2 5V LCD_R5 C8 LCD red data bus bit 5 2 5V LCD R6 A8 LCD red data bus bit 6 2 5V LCD_R7 A9 LCD red data bus bit 7 2 5V LCD_RSTB Bl Global rese
6. applications include medical instrumentation industrial instrumentation personal electronic aid and hard disk drive protection etc Some of the key features of this device are listed below For more detailed information of better using this chip please refer to its datasheet which is available on manufacturer s website or under the datasheet folder of the system CD ILijaslC Terasic VEEK MT C5SOC User Manual 13 www terasic com ANI S RA Table 3 4 contains the pin names and descriptions of the G sensor module Signal Name FPGA Pin No Description YO Standard GSENSOR INT1 E3 Interrupt 1 output 2 5V GSENSOR INT2 E2 Interrupt 2 output I2 5V GSENSOR CS n D4 Chip Select 2 5V GSENSOR_ALT_ADDR E1 I2C Address Select 2 5V GSENSOR SDA SDI SDIO D1 Serial Data 2 5V GSENSOR_SCL_SCLK D2 Serial Communications Clock 2 5V 3 5 Using the Ambient Light Sensor The APDS 9300 is a low voltage digital ambient light sensor that converts light intensity to digital signal output capable of direct I2C communication Each device consists of one broadband photodiode visible plus infrared and one infrared photodiode Two integrating ADCs convert the photodiode currents to a digital output that represents the irradiance measured on each channel This digital output can be input to a microprocessor where luminance ambient light level in lux is derived using an empirical formula to approximate the human eye response For more detailed information of better usi
7. displayed if the license file is not added before compiling projects using Terasic Multi touch IP The license file is located at VEEK MT C5SOC System CDXicenseNicense multi touch dat There are two ways to install the License The first one is to add the license file license multi touch dat to the licensed file listed in Quartus II as shown in Figure 1 3 General License Setup EDA Tool Options Fonts f amp c i Jii Headers amp Footers Settings License file 1800 192 168 1 56C altera M 1 0 Vicense multi touch dat Internet Connectivity C Use LM LICENSE FILE variable Libraries License Setup Current license Preferred Text Editor Web License Update Processing License Type Full Version Tooltip Settings inti Pn Aan Eh Messages EPEDLGDEGIIEOEUEANI Begin 30 day Grace Period Suppression Host ID Type NIC ID ura Host ID Value 0018f3ca7326 C wait for floating licenses Figure 1 2 License Setup The second way is to add license content to the existing license file The procedures are listed below Use Notepad or other text editing software to open the file license multi touch dat 1 The license contains the FEATURE lines required to license the IP Cores as shown in Figure 1 3 license multi touch dat 10 20 30 40 50 60 70 1 FEATURE 535C 0018 alterad 9999 12 12 jan 9999 uncounted 3F15022F111E 1 z VENDOR STRING 142cZ2K2979gj 7hoTVOtLcnySBti7hPsnSaeyATv8c8VS5OsL3 yOgoc 1DdCIZ 3 HOSTID
8. from the VEEK MT C5SOC system CD to your host computer 4 2 Painter Demonstration This chapter shows how to control LCD and touch controller to establish a paint demo based on Qsys and Altera VIP Suite The demonstration shows how multi touch gestures and single touch coordinates operate Figure 4 2 shows the hardware system block diagram of this demonstration For LCD display processing the reference design is developed based on the Altera Video and Image Processing Suite VIP The Frame Reader VIP is used for reading display content from the associated video memory and VIP Video Out is used to display the display content The display content is filled by NIOS II processor according to users input For multi touch processing a Terasic Memory Mapped IP is used to retrieve the user input including multi touch gesture and single touch resolution Note the IP is encrypted so the license should be installed before compiling the Quartus II project For IP usage details please refer to the section 3 7 Using Terasic Multi touch IP in this document asic Terasic VEEK MT C5SOC User Manual www terasic com FPGA SOPC 4 Avalon Interconnect Fabric Avalon Memory Mapped Bus Avalon Streaming Bus Figure 4 1 Block diagram of the Painter demonstration B Demonstration Source Code e Project directory Painter e Bit stream used Painter sof e Nios II Workspace Painter Software B Demonstration Batch File
9. it s then converted to RGB data streams by the RAW2RGB block After that the Multi Port SDRAM Controller acquires and writes the RGB data streams to the SDRAM which performs as a frame buffer The Multi Port SDRAM Controller has two write ports and read ports also with 16 bit data width each The writing clock is the same as CMOS sensor pix clock and the reading clock is provided by the LCD Controller which is 33MHz Finally the LCD controller fetches the RGB data from the buffer and displays it on the LCD panel continuously Because the resolution and timing of the LCD is compatible with WVGA 2800 480 the LCD controller generates the same timing and the frame rate can achieve about 25 fps For the objective of a better visual effect the CMOS sensor is configured to enable the left right mirror mode User could disable this functionality by modifying the related register value being written to CMOS controller chip LCD CMOS RAW2RGB Controller Capture v D lj 12C Configuration Mult Port SDRAM MTLC Figure 4 6 Block diagram of the digital camera design B Demonstration Source Code e Project directory Camera e Bit stream used Camera sof Terasic VEEK MT C5SOC User Manual 22 www terasic com AOTER B Demonstration Batch File Demo Batch File Folder CameraMemo batch The demo batch file includes the following files Batch File test bat FPGA Configure File Camera sof Demonstration Setup Load the bit
10. terasic com WWW Table 3 7 Gestures Gesture ID hex One Point Gesture North 0x10 North East 0x12 East 0x14 South East 0x16 South 0x18 South West Ox1A West 0x1C North West Ox1E Rotate Clockwise 0x28 Rotate Anti clockwise 0x29 Click 0x20 Double Click 0x22 Two Point Gesture North 0x30 North East 0x32 East 0x34 South East 0x36 South 0x38 South West 0x3A West 0x3C North West 0x3E Click 0x40 Zoom In 0x48 Zoom Out 0x49 Note The Terasic IP Multi touch IP can also be found under the MP folder in the system CD as well as the MP folder in the reference designs asic Terasic VEEK MT C5SOC User Manual 16 www terasic com www Chapter 4 VEEK MT C5SOC Demonstrations This chapter gives detailed description of the provided bundles of exclusive demonstrations implemented on VEEK MT C5SOC These demonstrations are particularly designed or ported for VEEK MT C550OC with the goal of showing the potential capabilities of the kit and showcase the unique benefits of FPGA based SOPC systems such as reducing BOM costs by integrating powerful graphics and video processing circuits within the FPGA 4 1 System Requirements To run and recompile the demonstrations you should e Install Altera Quartus II 13 0 and NIOS II EDS 13 0 or a later edition on the host computer e Install the USB Blaster II driver software e Copy the entire demonstrations folder
11. users the best display quality for developing applications The LCD panel supports 24 bit parallel RGB data interface The VEEK MT CS5SOC is also equipped with a Touch controller which can read the coordinates of the touch points through the serial port interface of the Touch controller To display images on the LCD panel correctly the RGB color data along with the data enable and clock signals must act according to the timing specification of the LCD touch panel as shown in Table 3 1 Table 3 2 gives the pin assignment information of the LCD touch panel Table 3 1 LCD timing specifications ITEM SYMBOL MIN TYP MAX UNIT NOTE Dot Clock 1AtCLK 33 MHZ DCLK DCLK pulse duty Tcwh 40 50 60 96 Setup time Tesu 8 ns Hold time Tehd 8 ns Horizontal period tH 1056 tCLK DE Horizontal Valid tHA 800 tCLK iLiaslC Terasic VEEK MT C5SOC User Manual 10 www terasic com JADE RA Horizontal Blank tHB 256 tCLK Vertical Period tV 525 tH Vertical Valid tVA 480 tH Vertical Blank tVB 45 tH HSYNC setup time Thst 8 ns HSYNC hold time Thhd 8 ns VSYNC Setup Time Tvst 8 ns VSYNC Hold Time Tvhd 8 ns Horizontal Period th 1056 tCLK Horizontal Pulse Width thpw 30 tCLK thb thpw 46DCLK Horizontal Back Porch thb 16 tCLK is fixed Horizontal Front Porch thfp 210 tCLK Horizontal Valid thd 800 tCLK Vertical Period tv 525 th Vertical Pulse Width tvpw 13 th tvpw tvb 23th Vertical Back Porch tvb 10 th is fixed Vertical Front Porch tvfp 22 th SYNC Vertical
12. K and IC2 SDAT pins should be connected of the TOUCH INT n TOUCH DC SCL and TOUCH DC SDA signals in the 2x20 GPIO header respectively When oREADY rises it means there is touch activity and associated information is given in the OREG X1 oREG Y1 oREG X2 oREG Y2 oREG TOUCH COUNT and oREG_GESTURE pins For the control application when touch activity occurs it should check whether the value of oREG GESTURE matched a pre defined gesture ID defined in Table 3 7 If it is not a gesture it means a single touch has occurred and the relative X Y coordinates can be derived from oREG X1 and oREG Yl Table 3 6 Interface Definitions of Terasic Multi touch IP Pin Name Direction Description iCLK Input Connect to 50MHz Clock iRSTN Input Connect to system reset signal iTRIG Input Connect to Interrupt Pin of Touch IC oREADY Output Rising Trigger when following six output data is valid oREG X1 Output 10 bits X coordinate of first touch point oREG Y1 Output 9 bits Y coordinate of first touch point oREG X2 Output 10 bits X coordinate of second touch point oREG Y2 Output 9 bits Y coordinate of second touch point oREG TOUCH COUNT Output 2 bits touch count Valid value is 0 1 or 2 oREG GESTURE Output 8 bits gesture ID See Table 3 5 l2C SCLK Output Connect to I2C Clock Pin of Touch IC I2C SDAT Inout Connect to I2C Data Pin of Touch IC The supported gestures and IDs are shown in Table 3 7 asic Terasic VEEK MT C5SOC User Manual 5 www
13. S RA O O C serial electrically erasable PROM EEPROM One Micro SD flash memory card e Switches and Indicators O O O O O O 000000000 00 00 0 0 0 LEDs and displays Eight user LEDs One configuration load LED One configuration done LED One error LED Three configuration select LEDs Four on board USB Blaster II status LEDs One HSMC interface LED Two UART data transmit and receive LEDs One power on LED One two line character LCD display Push buttons One CPU reset push button One MAX V reset push button One program select push button One program configuration push button Six general user push buttons DIP switches One MAX V CPLD System Controller control switch One JTAG chain control DIP switch One mode select DIP switch One general user DIP switch e On board Clocking Circuitry O O 1570 81571 and 815338 programmable oscillators 25 MHz 50 MHz 100 MHz 125 MHz 148 50 MHz and 156 25 MHz e Oscillators O SMA input LVCMOS e Communication Ports 000000000 One PCI Express x4 Genl socket One universal HSMC port One USB 2 0 on the go OTG port One Gigabit Ethernet port Dual 10 100 Ethernet ports One SDI port option for SMA connection One controller area network CAN port One RS 232 UART through the mini USB port One real time clock asic Terasic VEEK MT C5SOC User Manual 3 www terasic com ND S RA Power o 14 20 V laptop DC input Mechanical o 5 2 x 8 2 rectang
14. VEEK MiI 5SOC VEEK with Multi touch Capacitive Panel User Manual ATERA www terasic com Copyright 2003 2013 Terasic Technologies Inc All Rights Reserved CONTENTS SSS CHAPTER 1 INTRODUCTION OF THE VEEK MT C5SOO animal 1 1 1 Cyclone V SX SoC Development Board eese 2 1 2 Setup License for Terasic Multi touch IP eese eene eene rennen 6 1 3 Getting Help ooi rto et eine ied bas e ace shee sce eric ast ioo dea 7 CHAPTER 2 ales nm nba anna nga gak aka gas aan 8 2 1 Layout and Comrpohents aan aaa aia ai aie i eai ia aeia 8 2 2 Block Diagram of the VEEK MT CSSOC o ooooWooo nana 9 CHAPTER 3 USING VEEK MI C5SOC wiseccvscessecvvvassesvevsttenceveeseveveesuensvesetenevsvitsaeeeeenererevsnsteves settee 10 3 1 Using the Cyclone V SX SoC FPGA eeseeseesseeeseeeeeee eerte enne nennen enne nnne nete E nnne 10 35 2 Using the 7 LCD Capacitive Touch Screen eh rtr een retia hei eo indes 10 3 3 Using 5 megapixel Digital Image Sensor essere rennen 12 3 4 Using the Digital Accelerometer ooooooom enne nnne nennen rennen eren nennen nennen 13 3 5 Using th Ambient Light Sensor eres en una Et rop HEP E HE EEE Crab e ELE RR CE anu EUR SEES ae ede 14 3 6 Using Terasic Multi touch IP ien ehh th cna dito igh spans P ER maan gaharu 14 CHAPTER 4 VEEK MT C5SOC DEMONSTRATIONS inn noona 17 Al System Requirements
15. e CMOS sensor Parameter Active Pixels Pixel size Color filter array Shutter type Maximum data rate master clock Full resolution Frame rate VGA mode ADC resolution Responsivity Pixel dynamic range SNRMAX Supply Voltage power B Digital Accelerometer o Up to 13 bit resolution at 16g o SPI 3 and 4 wire digital interface o Flexible interrupts modes B Ambient Light Sensor Approximates human eye response O O O O 0 0 50 60 Hz lighting ripple rejection Value 2592Hx1944V 2 2umx2 2um RGB Bayer pattern Global reset release GRR 96Mp s at 96MHz Programmable up to 15 fps Programmable up to 70 fps 12 bit 1 4V lux sec 550nm 70 1dB 38 1dB 3 3V 1 7V 3 1V Precise luminance measurement under diverse lighting conditions Programmable interrupt function with user defined upper and lower threshold settings 16 bit digital output with I2C fast mode at 400 kHz Programmable analog gain and integration time Q for more detailed information of the LCD touch panel and CMOS sensor module please refer to their datasheets respectively WWW Tiasic Terasic VEEK MT C5SOC User Manual 5 www terasic com AOTER 1 2 Setup License for Terasic Multi touch IP To utilize the multi touch panel in a Quartus II project a Terasic Multi Touch IP is required After a license file for Quartus II is installed there is one more license file needed to implement Terasic s Multi touch IP Error messages will be
16. ng this chip please refer to its datasheet which is available on manufacturer s website or under the datasheet folder of the system CD Table 3 5 contains the pin names and descriptions of the ambient light sensor module Signal Name FPGA Pin No Description VO Standard LSENSOR_ADDR_SEL A6 Chip select 2 5V LSENSOR INT B7 Interrupt output 2 5V LSENSOR SCL A5 Serial Communications Clock 2 5V LSENSOR SDA C7 Serial Data 2 5V 3 6 Using Terasic Multi touch IP Terasic Multi touch IP is provided for developers to retrieve user inputs including multi touch gestures and single touch The file name of this IP is i2c touch config and it is encrypted To compile projects with the IP users need to install the IP license first For license installation please refer to section 1 2 Setup License for Terasic Multi touch IP in this document The license file is located at VEEK MT C5SOC System CDXicenseNicense multi touch dat The IP decodes I2C information and outputs coordinate and gesture information The IP interface is shown below kajasiC Terasic VEEK MT C5SOC User Manual 14 www terasic com module i2c touch config Host Side iCLE iRSTN iTRIG oREADY oREG Xi oREG Yi oREG X2 oREG Y2 oREG TOUCH COUNT oREG GESTURE I2C Side I2C SCLK I2C SDAT The signal purpose of the IP is described in Table 3 6 The IP reguires a 50 MHz signal as a reference clock to the iCLK pin and system reset signal to iRSTN iTRIG I2C SCL
17. ogram G_sensor elf B Demonstration Setup Load the bit stream into the FPGA on the VEEK MT C5SOC Run the Nios II Software under the workspace G sensor VSoftware Note After the Nios II program is downloaded and executed successfully a prompt message will be displayed in nios2 terminal its ADXL345 s ID e5 Tilt the VEEK MT C55SOC to all directions and you will find that the angle of the g sensor and value of light sensor will change When turning the board from 80 to 10 and from 10 to 80 in Y axis or from 10 to 80 and from 80 to 10 in Y axis the image will invert Figure 4 10 shows the demonstration in action Figure 4 10 Digital Accelerometer demonstration asic Terasic VEEK MT C5SOC User Manual 26 www terasic com JA DTE RYAN Q Note Execute G sensor Memo batchNest bat to download sof and elf files Terasic VEEK MT C5SOC User Manual 27 www terasic com Chapter 5 Appendix 5 1 Revision History Version Change Log V1 0 Initial Version Preliminary 5 2 Copyright Statement Copyright 2013 Terasic Technologies All rights reserved www terasic com
18. on the VEEK MT C5SOC in combination of the LCD touch panel and digital image module provides embedded developers the ideal platform for multimedia applications with unparallel processing performance Developers can benefit from the use of FPGA based embedded processing system such as mitigating design risk and obsolescence design reuse reducing bill of material BOM costs by integrating powerful graphics engines within the FPGA and lower cost Figure 1 1 shows a photograph of VEEK MT C5SOC asic Terasic VEEK MT C5SOC User Manual www terasic com Figure 1 1 The VEEK MT C5SOC board overview The key features of the board are listed below 1 1 Cyclone V SX SoC Development Board e Cyclone V SX SoC 5CSXFC6D6F31C8NES Oo O O O 110K LEs 41509 ALMs 5140 M10K memory blocks 224 18x18 Multiplier 6 FPGA PLLs and 3 HPS PLLs e Configuration Sources O O Active Serial AS x1 or x4 configuration EPCQ256SI16N MAX V CPLD 5M2210ZF256I5N in a 256 pin FBGA package as the System Controller Flash fast passive parallel FPP configuration MAX II CPLD EPM570GM100 as part of the embedded USB BlasterTM II for use with the Ouartus II Programmer e Memory Devices o O O O O One 1 024 Mbyte MB HPS DDR3 SDRAM with error correction code ECC support One 1 024 MB FPGA DDR3 SDRAM One 256 Megabit Mb quad serial peripheral interface QSPI flash One 512 Mb CFI flash One 32 Kb I2 www terasic com ANU
19. rasic com www teresic com Figure 4 5 Zoom in Gesture Q Note execute the test bat under Picture ViewerMemo batch will automatically download the sof and elf file 4 3 Camera Application This demonstration shows a digital camera reference design using the 5 Megapixel CMOS sensor and 8 inch LCD modules on the VEEK MT C5SOC The CMOS sensor module sends the raw image data to FPGA on the Altera Cyclone amp V SoC board the FPGA on the board handles image processing part and converts the data to RGB format to display on the LCD module The RC Sensor Configuration module is used to configure the CMOS sensor module Figure 4 8 shows the block diagram of the demonstration As soon as the configuration code is downloaded into the FPGA the I2C Sensor Configuration block will initial the CMOS sensor via I2C interface The CMOS sensor is configured as follow Row and Column Size 800 480 Exposure time Adjustable Pix clock MCLK 2 25 2 50MHz Readout modes Binning Mirror mode Line mirrored ILjjasiC Terasic VEEK MT C5SOC User Manual 2 www terasic com AOTER According to the settings we can calculate the CMOS sensor output frame rate is about 44 4 fps After the configuration The CMOS sensor starts to capture and output image data streams the CMOS sensor Capture block extracts the valid pix data streams based on the synchronous signals from the CMOS sensor The data streams are generated in Bayer Color Pattern format So
20. ration asic Terasic VEEK MT C5SOC User Manual 24 www terasic com ANU S RN 4 4 Digital Accelerometer Demonstration This demonstration shows a bubble level implementation based on a digital accelerometer We use PC protocol to control the ADXL345 digital accelerometer and the APDS 9300 Miniature Ambient Light Photo Sensor The LCD displays the interface of our game When tilting the VEEK MT C5SOC the ADXL345 measures the static acceleration of gravity In our Nios II software we compute the change of angle in the x axis and y axis and show angle data in the LCD display The value of light sensor will change as the brightness changes around the light sensor Figure 4 9 shows the hardware system block diagram of this demonstration The system is clocked by an external 50MHz Oscillator Through the internal PLL module the generated 150MHz clock is used for Nios II processor and other components and there is also 10MHz for low speed peripherals E ADXL345 APDS 9300 Figure 4 9 Block diagram of the digital accelerometer demonstration B Demonstration Source Code e Project directory G sensor e Bit stream used G_sensor sof e Nios II Workspace G_sensor Software Terasic VEEK MT C5SOC User Manual 25 www terasic com B Demonstration Batch File Demo Batch File Folder G sensordemo batch The demo batch includes the following files Batch File G_sensor bat test bashrc FPGA Configure File G sensor sof Nios II Pr
21. stream into FPGA by executing the batch file test bat under Camera demo_batch folder The system enters the FREE RUN mode automatically Press S6 on the Altera Cyclone V SoC board to reset the circuit User can use the SW1 5 and S5 to set the exposure time for brightness adjustment of the image captured When SW1 5 is set to Off the brightness of image will be increased as S5 is pressed longer If SW1 5 is set to On the brightness of image will be decreased as S5 is pressed shorter User can use SW1 8 to mirror image of the line However remember to press S6 after toggle SWI 8 Qo execute the test bat under Camera demo_batch will automatically download the sof file Table 4 2 and Figure 4 7summarizes the functional keys of the digital camera Figure 4 8 gives a run time photograph of the demonstration Table 4 1 The functional keys of the digital camera demonstration Component Function Description S6 Reset circuit S5 Set the new exposure time use with SW1 5 Off Extend the exposure time SW1 5 On Shorten the exposure time S1 8 Mirror image use with S6 asic Terasic VEEK MT C5SOC User Manual 23 www terasic com S6 Reset Circuit S5 Set the New SW1 8 Exposure time Mirror Image SW1 S Extend ShortenEx posure Time ij m ame U x NM NM NM NM NM N CH ARARAAE xia Figure 4 7 Block diagram of the digital camera design Figure 4 8 Screen shot of the VEEK MT C5SOC camera demonst
22. t pin 2 5V LCD_SHLR B3 Left or Right Display Control 2 5V LCD_UPDN B2 Up Down Display Control 2 5V LCD VSD B11 Vertical sync input 2 5V TOUCH I2C SCL F14 touch I2C clock 2 5V TOUCH I2C SDA F15 touch I2C data 2 5V TOUCH INT n B12 touch interrupt 2 5V 3 3 Using 5 megapixel Digital Image Sensor The VEEK MT C5SCC is equipped with a 5 megapixel digital image sensor that provides an active imaging array of 2 592H x 1 944V It features low noise CMOS imaging technology that achieves CCD image quality In addition it incorporates sophisticated camera functions on chip such as windowing column and row skip mode and snapshot mode The sensor can be operated in its default mode or programmed by the user through a simple two wire serial interface for frame size exposure gain settings and other parameters Table 3 3 contains the pin names and descriptions of the image sensor module i iaslC Terasic VEEK MT C5SOC User Manual 2 www terasic com Signal Name I O Standard Pixel data bit 11 Snapshot strobe Serial clok aW 3 4 Using the Digital Accelerometer The VEEK MT C5SCC is equipped with a digital accelerometer sensor module The ADXL345 is a small thin and ultralow power consumption 3 axis accelerometer with high resolution measurement Digitalized output is formatted as 16 bit twos complement and could be accessed either using SPI interface or I2C interface This chip uses the 3 3V CMOS signaling standard Main
23. ular form factor Capacitive LCD Touch Screen Equipped with an 7 inch Amorphous TFT LCD Thin Film Transistor Liquid Crystal Display module Module composed of LED backlight Support 24 bit parallel RGB interface Converting the X Y coordination of touch point to its corresponding digital data via the Touch controller Table 1 1 shows the general physical specifications of the touch screen Note Table 1 1 General physical specifications of the LCD Item Specification Unit LCD size 7 inch Diagonal Resolution 800 x3 RGB x 480 dot Dot pitch 0 1926 H x0 1790 V mm Active area 154 08 H x 85 92 V mm Module size 164 9 H x 100 0 V x 5 7 D mm Surface treatment Glare Color arrangement RGB stripe Interface Digital B 5 Megapixel Digital Image Sensor Superior low light performance High frame rate Global reset release which starts the exposure of all rows simultaneously Bulb exposure mode for arbitrary exposure times Snapshot mode to take frames on demand Horizontal and vertical mirror image Column and row skip modes to reduce image size without reducing field of view Column and row binning modes to improve image quality when resizing Simple two wire serial interface Programmable controls gain frame rate frame size exposure asic Terasic VEEK MT C5SOC User Manual www terasic com JAN DTE RYA Table 1 2 shows the key parameters of the CMOS sensor Note Table 1 2 Key performance parameters of th

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