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MN101C78A/F78A LSI User`s Manual - Digi-Key

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4. Ep Reset R 2 Nch open drain control 40 Q Wek VR Reset R Pull up pull down resistor selection WEK VR VV Reset Pull up pull down resistor control VR CEU p DIR2 I O direction control M Wek VR 5 S P T2 om Port output data grt DQ 08 aj WEK VR mix PIN Schmitt trigger input Port input data lt B dli d Serial 3 reception data input Serial 3 IIC3 clock output SC3MD1 SC3SBTS Reset T COMSL2 LCD output control Common output control Common output data LCD clock 3160 0431000 Vict Y Vic2 Y Vica Figure 4 4 3 Block Diagram P32 At common output port I O direction control is forcefully set to input mode pull up resistor is disabled and common output is executed by the common output control Port 3 Chapter 4 Ports IV 35 Chapter 4 Ports Reset R PSODC3 R Y get PSDWN R Reget PSPLUDS R Nch open drain control 2 Pull up pull down resistor selection Yo c Y Pull up pull
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6. Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x03F7C TM7PR2L TM7PR2 TM7PR2 TM7PR2 TM7PR2 TM7PR2 TM7PR2 TM7PR2 TM7PR2 VI 10 L7 L6 L5 L4 L3 L2 L1 LO x x X x x x x x Timer 7 preset register 2 lower 8 bits 0x03F7D TM7PR2H TM7PR2 TM7PR1 TM7PR2 TM7PR2 TM7PR2 TM7PR2 TM7PR2 TM7PR2 VI 10 H7 H6 H5 H4 H3 H2 H1 HO x x x x x x x x Timer 7 preset register 2 upper 8 bits Ox03F7E TM7DPR1 TM7DPR TM7DP TM7DP TM7DP TM7DP TM7DP TM7DP TM7DP VI 12 17 R16 R15 R14 R13 R12 R11 R10 x x x x x x x x Timer 7 preset register 1 Ox03F7F TM7DPR2 TM7DPR TM7DP TM7DP TM7DP TM7DP TM7DP TM7DP TM7DP VI 12 27 R26 R25 R24 R23 R22 R21 R20 x x x x x x x x Timer 7 preset register 2 0x03F80 TM8BCL TM8BCL TM8BCL TM8BCL TM8BCL TM8BCL TM8BCL TM8BCL TM8BCL 15 7 6 5 4 3 2 1 0 x x x x x x x x Timer 8 binary counter lower 8 bits 0x03F81 TM8BCH TM8BCH TM8BC TM8BC TM8BC TM8BC TM8BC TM8BC TM8BC VI 15 7 H6 H5 H4 H3 H2 H1 HO x x x x x x x x Timer 8 binary counter upper 8 bits 0x03F82 TM8OC1L TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 13 L7 L6 L5 L4 L3 L2 L1 LO x x x x x x x x Timer 8 compare register 1 lower 8 bits 0x03F83 TM8OC1H TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 TM8OC1 13 H7 H6 H5 H4 H3 H2 H1 H0 x x x x x x x x Timer 8 compar
7. HuoJuouAS x andu OIEIALL XJ 490 q SVOEIAL N3EIA L 2MOEIAL OMOEWL 5 1 3 Timer 2 and 3 Block Diagram Figure Overview V 6 Chapter 5 8 bit Timers 5 2 Control Registers Timer 0 to 3 consist of the binary counter TMnBC and the compare register TMnOC And they are controlled by the mode register TMnMD When the prescaler output is selected as the count clock source of timer 0 to 3 they should be controlled by the prescaler selection register CKnMD 5 2 1 Registers Table 5 2 1 shows registers that control timer 0 to timer 3 Table 5 2 1 8 bit Timer Control Registers Register Address Function TMOBC 0x03F50 Timer 0 binary counter TMOOC 0x03F52 Timer 0 compare register TMOMD 0x03F54 Timer 0 mode register CKOMD 0x03F56 Timer 0 prescaler selection register TMOICR OxOSFE7 Timer 0 interrupt control register 1 OxO3F1C Port 1 output mode register P1DIR 0x03F31 Port 1 direction control register P5OMD OxO3F2C Port 5 output mode register P5DIR 0x03F35 Port 5 direction control register Timer 1 TM1BC 0x03F51 Timer 1 binary counter TM10C 0x03F53 Timer 1 compare register TM1MD 0x03F55 Timer 1 mode register CK1MD 0x03F57 Timer 1 prescaler selection regis
8. NER Segment output control Wy Segment output data VLC1 Y LCD clock o Y 5 57 VLE 2 1 amp o 5 t zL vics_ e l 4 El i Figure 4 6 1 Block Diagram P70 Atsegment output port I O direction control is forcefully set to input mode pull up resistor is disabled and segment output is executed by the segment output control IV 58 Port 7 4 Reget PZDWN Pull up pull down resistor selection T wer VR Reset P Pull up pull down resistor control 7PLUD1 M P Wek R Reset P7DIR 4 direction control 5 1 2 ie wee mi ewe 2 Port output data sty ZOUTI M o WEK R PX Reget Y Port output control e Rol LOMB m WEK R Schmitt trigger input A P7IN1 Frl Port input data ar A Key interrupt input Timer 3 input Timer 3 input LCD output control Segment output control wi JH M Segment output data VLC1 Y LCD clock o Y VLC2 AMT e 3 2 Y VL C3 i e 5 k up 1 Figure 4 6 2 Block Diagram P71
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10. Reget 5 5 Pull up pull down resistor control d P 1PLUb4 9 wx Reset HN o 00 01 10 0 direction control M gt M a gt Wek x EX X 5 14 S P M Le Port output data 19014 004 y Py y nui 1 4 Port output control Wek R 2 Schmitt trigger input Port input data lt Timer 0 input Timer 0 remote control carrier output Reset 1 03 2 Output control 2 WOK y m m id LC2SL7 LCD output control Segment output control W Segment output data Vici 3 LCD clock 1 5 1 8 Y Vica Y Figure 4 2 5 Block Diagram 14 At segment output port I O direction control is forcefully set to input mode pull up resistor is disabled and seg ment output is executed by the segment output control IV 18 Port 1 Chapter 4 Ports Nch open drain control Pull up pull down resistor selection P1PLUDS Pull up pull down resistor control WEK R et 84 P1DIR5 direction control DQ 2 WEK R Port outpu
11. 7 Reset R P7DWN Pull up pull down resistor selection TP WEK R lt Reset Pull up pull down resistor control P7PLUD3 2 M ud WEK R mb ree P7DIR direction control x WEK ZAR Lx P E S P7OUT Y Port output data o OUTS o WEK R Schmitt trigger input P7IN3 Port input data lt Key interrupt input Reset LC2SL0 LCD output control Q NER Fi Segment output control aq W Segment output data VLC1 Y m LCD clock o Y 5 VLC2 4 5 e 5 t zi 5 u VL Y gt d EH Figure 4 6 4 Block Diagram P73 Atsegment output port I O direction control is forcefully set to input mode pull up resistor is disabled and segment output is executed by the segment output control Port 7 Chapter 4 Ports IV 61 Chapter 4 Ports RA P7DWN Pull up pull down resistor selection T P Wek R S7 Reset lto Pull up pull down resistor control T D Q WEK N R direction control D vs Port output data 70674 o WEK R Y gt Schmitt trigger input
12. Setup item Set to Serial data input pin Select SBI1 3 channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Output edge Rising edge Clock Clock Slave Clock source fs 2 Clock source dividing Not divided Used pin A port 1 SBT1 SBO pin style Nch open drain 5871 pin pull up resistor Added SBO1 pin pull up resistor Added Serial 1 communication complete interrupt Enable SBO1 output after last data output 1 H fix An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation 1 Set the SC1PSCE flag of the SC1MD3 register to 1 to SC1MD3 0x03F9C select prescaler operation bp3 SC1PSCE 1 2 Select the clock source 2 Set the SC1PSC2 to 0 flag of the SC1MDS3 register to SC1MD3 0x03F9C 100 to select the fs 2 to clock source bp2 0 SC1PSC2 0 100 3 SBO1A output control after the last data 3 Set the SC1FDC1 to 0 flag of the SC1MDS3 register to output 00 to select 1 High fix of the SBO1 last data SC1MD3 0x03F9C output bp7 6 SC1FDC1 0 200 4 Select used pin 4 Set the SC1SL flag of the SC1SEL register to 0 to SCSEL 0x03F90 select A port 1 as I O pin bp1 SC1SL 0 5 Control the pin style 5 Set the P1ODC7 P10ODC5 flag of the P1ODC register to P10DC 0x03F 1B 1 1 to select Nch open drain to SBTO pin Set the bp7 P1ODC7 21
13. PIDIR direction control M M gt gt wbx VR 1 EX Y P10UT7 L Port output data t a 2 M 4 WE I YR mx pix Reset Port output control Rd 1 __ Wek R Schmitt trigger input Port input data lt T LJ ur Serial 1 clock input Serial 1 clock output a SC1MD1 SC1SBTS Timer 2 output LCD output control Segment output control H W Segment output data Vis 1 LCD clock 3160 indino Figure 4 2 8 Block Diagram P17 At segment output port I O direction control is forcefully set to input mode pull up resistor is disabled and seg ment output is executed by the segment output control Port 1 IV 21 Chapter 4 Ports 4 3 Port2 4 3 1 Description General Port Setup P27 is reset pin When the software is reset write 0 to the bp7 of the port 2 output register PZOUT Also P27 is always added pull up resistor 4 3 2 Registers Table 4 3 1 shows the registers that control the port 2 Table 4 3 1 Port 2 Control Register P2OUT 0x03F12 Port 2 output register IV 22 R W Readable Writable Port 2 Output Register P2OUT 0x03F 12
14. The lower 2 bits results from A D conversion are stored to this register ANBUFO7 ANBUFO6 Reset X fuese ENNIO CNN CNN _ _ A D Conversion Data Storage Buffer ANBUF1 0x03FCF The upper 8 bits results from A D conversion are stored to this register Flag ANBUF17 ANBUF16 ANBUF15 ANBUF14 ANBUF13 ANBUF12 ANBUF11 ANBUF10 X X R R R Reset X X X X X X Access R R R R R Control Registers XV Chapter 15 A D Converter 15 3 Operation Description of A D converter circuit setup procedure is as follows 1 Setthe analog pins Set the analog input pin set at the procedure 2 to special function pin by the port A input mode register PAIMD Setup of the port A input mode register should be done before analog voltage is put to pins 2 Select the analog input pin Select the analog input pin from AN6 to ANO by the ANCHS2 0 flag of the A D converter control register 3 Select the A D converter clock Select the A D converter clock by the ANCK1 flag of the A D converter control register 0 ANCTRO Converter clock T Ap should not be less than 800 ns by any oscillator 4 Setthe sample hold time Set the sample hold time by the ANSHI ANSHO flag of the A D converter control register 0 ANCTRO The sample hold time should be based on analog input impedance Procedures 2 to 4 can be set in any ord
15. P30DC P30DC2 Output mode Output mode P3DIR P3DIR3 P3DIR P3DIR2 Pull up Added Added P3PLU P3PLU3 P3PLU P3PLU2 B Pin Setup 2 channels at reception Table 13 3 17 shows the pins setup in serial interface reception with 2 channels SDA3 pin SCL3 Table 13 3 17 Pin Setup 2 channels at reception Item Data pin Clock output pin SDA3 pin SCL3 pin Pin P33 P32 SDA3 SCL3 pins SBI3 SBO3 pin connection SC3MD1 SC3IOM Function Port Serial clock output SC3MD1 SC3SBOS SC3MD1 SC3SBTS Serial data input SC3MD1 SC3SBIS Type N ch open drain N ch open drain P30DC P30DC2 Output mode Output mode P3DIR P3DIR3 P3DIR P3DIR2 Pull up Added Added P3PLU P3PLU3 P3PLU P3PLU2 Operation XII 45 Chapter 13 Serial Interface 3 13 3 4 Setup Example OOS Master Transmission Setup Example The setup example for the transmission of several bytes data to the all the devices on IIC bus with IIC serial Inter face 3 is shown Table 13 3 18 shows the conditions at communication Table 13 3 18 Conditions Single Master Communication Setup Item Set to SBI3 SBO3 pins Connection 2 channels Transfer bit count 8 bits Start condition Enable disable after second communication First transfer bit MSB ACK bit Enable communication mod
16. Capture trigger source Timer 7 mode regis Timer 7 mode Timer 8 mode regis Timer 7 mode ter 2 register 1 ter 2 register 2 T7ICT1 0 T7ICED T7ICEDG1 T8ICT1 0 T8ICED T8ICEDG1 GO GO IRQO falling edge O0 IRQO 1 0 OO IRQ0 1 0 IRQO rising edge OO IRQ0 1 1 O00 IRQO 1 1 IRQO both edges OO IRQ0 O x OO IRQ0 0 x IRQ1 falling edge O1 IRQ1 1 0 O1 IRQ1 1 0 IRQ1 rising edge O1 IRQ1 1 1 01 IRQ1 1 1 IRQ1 both edges 01 IRQ1 0 x 01 IRQ1 0 x IRQ2 falling edge 10 IRQ2 1 0 10 IRQ2 1 0 IRQ2 rising edge 10 IRQ2 1 1 10 IRQ2 1 1 IRQ2 both edges 10 IRQ2 0 x 10 IRQ2 0 x 16 bit Timer Capture VI 49 Chapter 6 16 bit Timers If the system clock fs is selected as the capture clock and the capture operation is done during the TMnIO input or operation with fosc an incomplete value at the count up of the binary counter may be written to the input capture register To prevent this use fx or syn chronous TMnIO input as the count clock of the capture clock selected by the TMnCKSMP flag of the TMnMD3 register Therefore even capture trigger is input the value of the binary counter is not loaded to the capture reg ister until the rising edge of the next capture clock If the clock which is slower than CPU operation speed fs is set as the timer source clock set the TMnCKSMP of the TMnMD3 register to fs Also the interval of each capture t
17. Figure 2 3 1 Functional Block Diagram of the Bus Controller Bus Interface 19 Chapter 2 CPU Basics 2 3 2 Control Registers Bus interface is controlled by the memory control register MEMCTR Memory Control Register MEMCTR Table 2 3 1 Memory Control Register MEMCTR 0x03F01 4 3 1 0 Reserved Reserved Reserved Reserved 0 1 1 1 Description Wait cycles when accessing special register Bus cycle at 10 MHz oscillation area 00 No wait cycles 200 ns 01 1 wait cycle 300 ns 10 2 wait cycles 400 ns 11 3 wait cycles 500 ns Base address setting for interrupt vector table Interrupt vector base 0x04000 Interrupt vector base 0x00100 Reserved Set always to 0 Reserved Set always to 17 IRWE Software write enable flag for interrupt request flag Software write disable Even if data is written to each interrupt control register xxxICR the state of the interrupt request flag will not change Reserved Set always to 11 The IOW1 IOWO wait settings affect accesses to the special registers located at the addresses 0x3F00 0x3FFF After reset MEMCTR specifies the fixed wait cycle mode with three wait cycles Wait setting of IOW is a function which CPU supports for special use for example when special function register or I O is expanded to external For this LSI wait cycle setting is not always necessa
18. P7IN4 Port input data lt 1 4A uli Key interrupt input Reset LC1SL3 LCD output control VER Segment output control H l Segment output data VLC1 LCD clock VLC2 E Y Y 8 Y VLCS i Figure 4 6 5 Block Diagram 74 Atsegment output port I O direction control is forcefully set to input mode pull up resistor is disabled and segment output is executed by the segment output control 62 Port 7 Chapter 4 Ports R P7ZODC5 Nch open drain control q WEK R Y Reset PZDWN Pull up pull down resistor selection WEK R NA Reset 4 P Pull up pull down resistor control FT 5 Wek R 1 P7DIRS i direction control WEK R X E 9 Gil Y gt P75 D P Port output data q 7 5 4 pa Y H gt P7IN5 Schmitt trigger input T P Port input data lt 1 LJ Key interruptinput Serial 0 reception data input Serial 0 UARTO transmission data output SCOMD1 SCOSBOS LCD output control ex
19. 0 TONNI 5 5 21 Y x X possess eda eaW ZW n SH 55 1082W 91 N3189i1 gt d Lin 6 Jejunoo 91 64 n x W Indu EN 1 wt en 2t _ n 1 s s 5 i x s xk 4 yore Jajeosaid 4q p IW n 980 W Lag HIOOZWIL Lt 2 151 91 we Lael i i pes peot 5180 NSOIZL 2101 090302141 IN OL i aiqesip a qeua 1 51 195 924 91 9 uogoejep n ndeg x J n yog 7 In LISHIZWL IN 00ul NSOILL HOWL payloads Buum T TIOL 1 516 1 eunjdeo 91 adeg 1918168 eanjdeg 012 1 12 1 0 51099021 JDA 3E WZ 05039121 OT mem 0 19039121 9 zx s iagram 7 Block D 6 1 1 Timer Figure Overview VI 4 Chapter 6 16 bit Timers Timer 8 Block Diagram 185IN 8NMdAndino OISNL
20. R PBPLUG Wek R Reset PSDIRE u VR D gt dPsoure s Wek R BAIN Schmitt trigger input lt Figure 4 5 7 Block Diagram P56 P56 Chapter 4 Ports 4 6 Port 7 4 6 1 Description General Port Setup To output data to pin set the control flag of the port 7 direction control register P7DIR to 1 and write data to the port 7 output register P7OUT To read input data of pin set the control flag of the port 7 direction control register P7DIR to 0 and read the value of the port 7 input register P7IN Each bit can be set individually to either an input or output by the port 7 direction control register P7DIR The control flag of the port 7 direction control register P7DIR is set to 1 for ouput mode and 0 for input mode Each bit can be set individually if pull up pull down resistor is added or not by the port 7 pull up pull down resistor control register PZPLUD Set the control flag of the port 7 pull up pull down resistor control register P7PLUD to 1 to add pull up resistor Port 7 can be selected to add pull up resistor or pull down resistor by bp1 of the pull up pull down resistor selec tion register SELUD Each bit can be selected individually as output mode by the port 7 output mode register P7OMD The control flag of the port 7 output mode register P7OMD is set to 1 to output the special function data and
21. 5 R Nch open drain control K Reset PADWN R Pull up pull down resistor selection K Reset bs PAPLUD5 R Pull up pull down resistor control K Reset PADIRS R direction control K PA5 PAOUTS5 o R Port output data 1 Reset RJ 5 D R Input mode control K Schmitt trigger input v4 Port input data BAINS Analog input Serial 1 reception data input Serial 1 UART1 transmission data output SC1MD1 SC1SBOS Figure 4 8 6 Block Diagram 5 IV 80 Port A Chapter 4 Ports Reset Rd PAODCO K Reset PADWN K Nch open drain control Pull up pull down resistor selection Reset 6 PAPLUDe K Pull up pull down resistor control Reset R PADIRG ID K direction control snq PA6 o R Port output data Input mode control Schmitt trigger input Port input data T Analog input Serial 1 clock input Serial 1 clock output SC1MD1 SC1SBTS Figure 4 8 7 Block Diagram PA6 Port A IV 81 Chapter 4 Ports 82 4 9 Real Time Output Control P12 P14 P16 have the real time output function that can switch pin output at the falling edge event of the exter nal interrupt 0 pin P54 IRQO The real time control is the function that can change the timer output signal PWM output timer pulse output remote control
22. bp7 6 1 0 200 5 Set the interrupt level ADICR 0x03FF4 bp7 6 ADLV1 0 00 6 Enable the interrupt ADICR 0x03FF4 bp1 ADIE 1 7 Set the A D ladder resistance ANCTRO 0x03FCB bp3 ANLADE 1 8 Start A D conversion operation ANCTR2 0x03FCD bp7 ANST 1 ANBUF1 9 Complete A D conversion operation 1 Set the analog input pin set at the procedure 2 as the special function pin by the port A input mode register PAIMD Also disable pull up resistor by the port A pull up resistor control register PAPLUD 2 Select the analog input pin from AN6 to ANO by the ANCH2 0 flag of the A D converter control register1 ANCTR1 3 Select the A D converter clock by the ANCK1 ANCKO flag of the A D converter control ANCTRO 4 Set the sample hold time by the ANSH1 ANSHO flag of the A D converter control registerO ANCTRO 5 Set the interrupt level by the ADLV1 0 flag of the A D conversion complete interrupt control register ADICR If any interrupt request flag is already set clear the flag 6 Set the ADIE flag the ADICR register to 1 to enable the interrupt Chapter 3 3 1 4 Interrupt Flag Setup 7 Set the ANLADE flag of the A D converter control registerO ANCTRO to 1 to send a current to the ladder resistance for the A D conversion 8 Set the ANST flag of the A D converter control register2
23. uomnipuoo uelis INOI OS L YIGeEOS 8S1 78SIN 5 wa EE luaAWDE tI 59 1595 Figure 13 1 1 Serial Interface 3 Block Diagram XIII 3 Overview Chapter 13 Serial Interface 3 13 2 Control Registers 13 2 1 Registers List Table 13 2 1 shows the registers that control serial interface 3 Table 13 2 1 Serial Interface 3 Control Registers List Register Address Function Page SC3MDO OxO3FAO Serial interface 3 mode register 0 XIII 6 SC3MD1 0x03FA1 Serial interface 3 mode register 1 XIII 7 SC3MD3 OxO3FA2 Serial interface 3 mode register 3 XIII 8 SC3STR 0x03FA3 Serial interface 3 status register XIII 9 SC3TRB 4 Serial interface 3 transmission reception shift register XIII 5 TXBUF3 Ox03FA5 Serial interface 3 transmission data buffer XIII 5 SC3CTR Ox03FA6 Serial interface 3 control register XIII 10 P30DC 0x03F3B Port 3 N ch open drain control register IV 30 P3DIR 0x03F33 Port 3 direction control register 27 0x03F43 Port 3 pull up control register IV 28 SC3ICR Ox03FF3 Serial interface 3 interrupt control register III 36 R W Readable Writable R Readable XIII 4 Control Registers 13 2 2 Data Buffer Register Serial interface 3 has a 8 bit serial data buffer register for transmission Serial Interface 3 Transmission Data Buffer 0x03FA5 bp 7
24. bp 7 6 5 4 3 2 1 0 Flag T7OC2LV T7OC2LV T7OC2IE T7OC2IR 1 0 At reset 0 0 0 0 Access R W Description T70C2LV1 Interrupt level flag T7OC2LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to to interrupt requests T7OC2IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt T7OC2IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 31 Chapter 3 Interrupts III 32 Serial 0 UART Reception Interrupt Control Register SCORICR The serial 0 UART reception interrupt control register SCORICR controls interrupt level of timer 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 15 Serial 0 UART Reception Interrupt Control Register SCORICR 0x03FEF 7 6 1 0 SCORLV1 SCORLVO SCORIE SCORIR 0 0 0 0 SCORLV1 SCORLVO Description Interrupt level flag interrupt requests This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 3 to SCORIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SCORIR Control Registers Interrupt request flag 0 No interrupt request 1 Interrupt request generated Serial 0 UART Transmiss
25. f Yo Reset 1 R Di P5LED1 R 25 2 Port output control Re 777 LED output control Schmitt trigger input Port input data zA Timer 7 output Figure 4 5 2 Block Diagram P51 Port 5 IV 45 Chapter 4 Ports Reset LU2 Pull up resistor control D R DIR2 direction control PS Hh R X 5 i Y gt P52 J T2 Port output data S PSOD 2 a Wek ZR P5OMD2 Port output control 2 b Wek R P5LED2 E LED output control Wek R Schmitt trigger input Port input data lt Timer 2 output Figure 4 5 3 Block Diagram P52 Reset Pull up resistor control t Ro oe gt Le WCK R E P5DIR direction control Ro 8 2 Wi 1 D WEK R lt X Le S P50UT3 a Port output data dP 2 a Wek R PX PSOMD3 E Port output control WEK R P5LED 2 LED output control Ro 2 3 WEK R BIN Schmitt trig
26. 3 3 1111 0110 lt d4 gt 2 MOVW An d4 SP 16 44 5 3 1111 010A lt d4 gt 2 MOVW DWn d8 SP DWn mem16 d8 SP 5 4 0010 1111 0110 lt 8 gt 3 MOVW An d8 SP An mem16 d8 SP 5 4 0010 1111 010A d8 gt 3 MOVW DWn d16 SP DWn mem16 d16 SP 7 5 0010 1111 0010 di6 rad MOVW 916 3 AnGmemt6 d16 SP 7 5 0010 1111 di6 gt MOVW DWn abs8 DWn mem16 abs8 4 3 1101 0110 abs 8 gt MOVW An abs8 An mem16 abs8 41 3 1101 010A abs 8 gt MOVW DWn abs16 _ DWn memt16 abs16 Seer 0010 1101 011D abs 16 m MOVW An abs16 An mem16 abs16 7 5 0010 1101 010A abs 16 gt MOVW DWn HA DWn mem16 HA 2 3 1001 010D MOVW An HA 2 1001 011A MOVW imm8 DWm sign imm8 gt DWm 4 2 0000 1104 lt 8 gt 15 MOVW imm8 Am zero imm8 Am 4 2 0000 111a 8 gt 6 MOVW imm16 DWm imm16 5DWm 6 3 1100 111d H6 Instruction Set 1 d8sign extension 4 A An a Am 2 d4zero extension 5 8 sign extension 3 d8zero extension 6 8 zero extension Chapter 17 Appendix MN101C SERIES INST
27. 101 32 dividing 9 100 64 dividing 111 128 110 System clock fs OSCSEL1 OSCSELO OSCDBL Figure 2 5 1 Clock Switching Circuit OSCSEL1 OSCSELO OSCDBL Oscillating frequency 0 0 0 2 0 0 1 1 0 1 0 8 0 1 1 4 1 0 0 32 1 0 1 16 1 1 0 128 1 1 1 64 Figure 2 5 2 Setting Division Factor at NORMAL mode by combination of OSCSEL and OSCDBL flag at the same time with the setting of clock switching functions OSCDBL flag OSCSEL1 a Do not change the setting of standby functions STOP flag HALT flag OSC1 flag OSC2 flag OSCSELO flag OSCDBL flag OSCSEL1 flag and OSCSELO flag can be changed at the same time Clock Switching II 29 Chapter 2 CPU Basics 2 6 Heset 2 6 1 Reset operation The CPU contents are reset and registers are initialized when the NRST pin is pulled to low Initiating a Reset There are two methods to initiate a reset 1 Drive the NRST pin low NRST pin should be held low for more than OSC 4 clock cycles 100 ns at a 10 MHz NRST 4 Oscillating clock 400 ns at 10 MHz Figure 2 6 1 Minimum Reset Pulse Width 2 Setting the PZOUTT flag of the P2OUT register to 0 outputs low level at P27 NRST pin And transferring to reset by program software reset can be executed If the internal LSI is reset and
28. 58010 0192 OV uono l p Buisiy snouo4 uou s SION 5 Figure 3 3 1 External Interrupt 0 Interface Block Diagram External Interrupts III 42 Chapter 3 Interrupts B External Interrupt 1 Interface Block Diagram JejsueJ eyeq 1senbeij 1dnuueiur LOHI Buisiu N9119 snouoJuou S uonoejep 5800 0197 OV 27 jeuBis gpuels ELNE 9798 HOILOHI Yno uono l p OSIN yen uono l p snouol qou S OSION 5 PX a 19 a Figure 3 3 2 External Interrupt 1 Interface Block Diagram 43 External Interrupts Chapter 3 Interrupts B External Interrupt 2 Interface Block Diagram a 801204 uonoejep JejsueJ die ae senbaei jdnueju ZOYI cOul 9S8d Figure 3 3 3 External Interrupt 2 Interface Block Diagram
29. RMOUT output 1 3 duty Figure 8 3 3 Output Wave of RMOUT Output Pin Setup Procedure Description 1 Disable the remote control carrier output 1 Set the RMOEN flag of the remote control carrier output RMCTR 0x03F6C control register RMCTR to 0 to disable the remote bp3 RMOEN 0 control carrier output 2 Select the base cycle setup timer 2 Set the RMBTMS flag of the RMCTR register to 0 to RMCTR 0x03F6C select the timer 0 as the setup timer of the base cycle RMBTMS 0 3 Select the carrier output duty 3 Set the RMDTY1 0 flag of the RMCTR register to 0 1 RMCTR 0x03F6C to select the duty to 1 3 bp2 1 RMDTY1 0 01 4 Confirm the counter stop 4 Set the TMOEN flag of the timer 0 mode register TMOMD 0x03F54 TMOMD to 0 to stop counting of the timer 0 bp3 TMOEN 0 5 Set the remote control carrier output of the b Set the P1OMDA flag of the port 1 output mode register special function pin P1OMD to 1 to set P14 pin to the particular function P1OMD 0x03F1C pin bp4 P1OMD4 1 Set the P1DIR4 flag of the port 1 direction control P1DIR 0x03F31 register P1DIR to 1 to set the output mode bp4 P1DIR4 1 Set the TMORM flag of the RMCTR register to 1 to RMCTR 0x03F6C select the remote control carrier output bp4 TMORM 1 6 Select the timer general operation 6 Set the TMOPWM flag and the TMOMOD flag of the TMOMD 0x03F54 TMOMD register to 0 to select the timer general
30. 38 18 lt SBTOA PA2 AN2 COM1 P31 SBI3 lt 39 MN101C78A 17 _ RXDOA SBIOA PA1 AN1 COM2 P32 SBT3 SCL3 40 44 pin LCD version 16 lt TXDOA SBOOA PAO ANO COM3 P33 SB03 SDA3 lt 41 15 Vref P34VLC3 lt 42 14 lt P11 SCL4A P35 VLC2 4 9 43 13 lt gt P10 SDA4A P36VLC1 lt 44 12 lt NRST P27 vss ___ 5 OSC2 lt 6 OSC1 7 VDD 8 XI P90 lt 9 XO lt 10 MMOD 11 TMOOA LEDO P50 lt gt 1 TM7O LED1 P51 lt gt 2 TM2OA LED2 P52 lt y 3 TM8O LED3 P53 _ gt 4 Figure 1 3 2 Pin Configuration 44QFP TOP VIEW Pin Description 1 11 Chapter 1 Overview 1 3 2 Pin Specification Table 1 3 1 Pin Specification Pins Special Functions y o Direction Pin Functions Description Control Control P10 SDA4A in out P1DIRO P1PLUO SDA4A IIC4 Data P11 SCL4A in out P1DIR1 P1PLU1 SCL4A IIC4 Clock I O P12 8 BUZZER in out P1DIR2 P1PLU2 8 Timer 8 I O BUZZER Buzzer output P13 TM7IO NBUZZER in out P1DIRS P1PLUS TMT7IO Timer 7 I O NBUZZER Buzzer reverse output CLKOU CLKOUT Frequency output T P14 RMOUT in out P1DIR4 P1PLU4 TMOIO Timer 0 I O RMOUT Remote control carrier output SEG11 SEG11 Segment output P15 TMOOB SBO1A in out P1DIR5 P1PLUS TMOOB Timer 8 I O 5 Serial interface transmission data output TXD1A SEG10 TXD1A UART1 transmission data SEG10 Segment output output P16 2 SBHA
31. 6 1 1 3bias 1 4duty 1 83bias Vop VLcp MN101C78 5 L Vici R C Vica R ieee Vss Ill Figure 16 3 5 LCD Power Supply Connection XVI 18 Operation Chapter 16 LCD 16 3 3 Frame Cycle Setup of the LCD frame cycle The clock fosc or fx is divided by the prescaler and supplied as the LCD clock Set the LCD clock by the bit0 to bit3 of the LCDMDI register and set the LCD frame cycle by the bit4 to bit5 of the LCDMDI register Fig ure 16 3 6 shows reference input frequencies and the matching of the LCD clock and the LCD frame cycle Input frequency Input cloci duty 10 MHz 8 MHz 4MHz 2 MHz 32 768 kHz LCDCKS to 0 LCDTY1 to 0 frame LCDdek frame frame LCDclock frame LCDckock frame 00 1 4 duty 1221 Hz 977 Hz 488 Hz 244 Hz 0000 01 1 3 duty 1628 Hz 1302 Hz 651 Hz 326 Hz 0501 27 10 1 2 duty 4883 Hz 3441 Hz 9906Hz 1955 Hz 1953 Hz 977 977 HZ 11 static 4883 Hz 3906 Hz 1953 Hz 977 Hz bo 1 4 duty 610 Hz 488 Hz 244 Hz 122 Hz 0001 b1 1 3 duty 814 Hz 651 Hz 3
32. 2 0 KEY4 interrupt selection 0 Disable 1 Enable External Interrupts 51 Chapter 3 Interrupts 3 3 4 Programmable Active Edge Interrupt Programmable Active Edge Interrupts External interrupts 0 to 2 The programmable active edge interrupt can select the rising falling edge about the signal which is input from the external interrupt input pin and generate the interrupt at the selected edge Also if the value which is set to the external interrupt valid edge specify flag and the level of the external interrupt pin are matched it is possible from the standby mode the external interrupt pin level are matched the interrupt is generated refer to Figure 3 3 1 a At the standby mode if the value that is set to the external interrupt valid specified flag and to Figure 3 3 5 Chapter 3 3 3 9 External Interrupt At the Standby Mode Programmable Active Edge Interrupt Setup Example External interrupt 0 to 2 External interrupt 0 IRQO is generated at the rising edge of the input signal from P54 The table below shows a setup example of IRQO Setup Procedure Description 1 Specify the interrupt active edge IRQOICR 0x03FE2 bp5AFREDGO 1 2 Set the interrupt level IRQOICR 0x03FE2 bp7 6 IRQOLV1 0 10 3 Enable the interrupt IRQOICR 0x03FE2 bp1 IRQOIE 1 1 Set the REDGO flag of the external interrupt 0 control register IRQOICR to 1 to sp
33. Setup example of the LCD 1 4 duty An example of setup procedure to display 23 on a 2 digit 8 segment type LCD panel with both segment signals SEGO to SEG4 and common signals COMO to COM3 in 1 4 duty 1 3 bias using an external dividing resistor 18 shown below Chapter 16 4 7 LCD Display 1 4 duty Clock source fosc 4 MHz LCD clock source fosc 2P 122 Hz and flame cycle 31 Hz are selected in this example Setup Procedure Description 1 Stop the LCD operation LCDMD 1 X 3FCO bp7 LCDEN 0 2 Set the display duty LCDMD 1 bp5 4 LCDDTY1 0 00 3 Select the LCD clock source LCDMD 1 bp3 0 LCDCK3 0 0100 4 Select the segment output port pin Select the common output port pin LCCTR1 X 3FC2 bp3 0 COMSL3 0 1111 bp7 4 LC1SL3 0 1111 5 Set the LCD panel display data Segment output latch SEG1 0 X 2E00 X 5E Segment output latch SEG3 2 X 2E01 X 7C 6 Start the LCD operation LCDMD1 X 3FC0 bp7 LCDEN 1 1 Set the LCDEN flag of the LCD mode control register 1 LCDMD1 to 0 to stop the LCD operation 2 Set the LCDTY1 to LCDTYO of the LCD mode control register 1 LCDMD1 to 00 to enter 1 4 duty driving mode 3 Select fosc 2 as the LCD clock source by the LCDKC3 to LCDCKO flags of the LCD mode control register 1 LCMD1 4 Select SEG7 to SEGO and to COMO by the output control register LC
34. 4 electrode 2 5 5 ight OFF Light OFF SSeS pee ELE Srey iene Ses See L ight OFF L B electrode COM1 SEG5 EE gt 1 4 Light ON Light OFF Light OFF Figure 16 4 3 LCD Display 1 3 duty Display XVI 28 Chapter 16 LCD 16 4 6 Setup Example 1 3 duty B 2 1 Setup example of the LCD 1 3 duty An example of setup procedure to display 23 on a 2 digit 8 segment type LCD panel with both segment signals SEGO to SEG7 and common signals COMO using an external dividing resistor is shown below Chapter 16 4 5 LCD Display 1 3 duty Clock source fosc 4 MHz LCD clock source fosc 2P 122 Hz and flame cycle 41 Hz are selected in this example Setup Procedure Description 1 Stop the LCD operation 1 Set LCDEN flag of the LCD mode control register LCDMD1 X S3FCO LCDMD1 1 to stop the LCD operation bp7 LCDEN 0 2 iSet the display duty 2 Set the LCDTY1 to LCDTYO flags of the LCD mode LCDMD1 X 3FCO0 control register 1 LCMD1 to 01 to enter 1 3 duty bp5 4 LCDDTY1 0 01 driving mode 3 Select the LCD clock source 3 Select fosc 2 as a LCD clock source by LCDCK3 LCDMD1 X 3FCO0 to LCDCKO flags of
35. 5 ENSIS XAN 1 60911 4 041900 49091 2 m 2349091 0935 1936 LL03S r 50391 DES o meinen 7 2 d 039091 Lanao 4 24 xnw lt Oll lt 250 Figure 16 1 1 LCD Driver Circuit Block Diagram 5 Functions Chapter 16 LCD 16 2 Control Registers The LCD is controlled by LCD mode control register 1 LCDMD1 LCD mode control register 2 LCDMD2 LCD output control register 1 LCCTR1 LCD output control register 2 LCCTR2 and LCD output control reg ister 3 LCCTR3 The LCD display data is stored in the segment output latch 16 2 1 Registers Table 16 2 1 shows the LCD control registers Table 16 2 1 LCD Control Registers List Register Address Function LCDMD1 X 03FCO LCD mode control register 1 LCDMD2 X 03FC1 LCD mode control register 2 LCCTR1 X 03FC2 LCD output control register 1 LCCTR2 X 03FC3 LCD output control register 2 LCCTR3 X 03FC4 LCD output control register 3 R W Readable Writable Address x 02E00 to 02 05 are assigned to the segment output latch Chapter 16 2 7 Segment Output Latch XV
36. 93 0 9VDD n 1101 0 1VDD twh2 gt lt twi2 gt twf2 lt twc2 gt Figure 1 5 4 XI Timing Chart Electrical Characteristics 27 Chapter 1 Overview 1 5 3 DC Characteristics 40 to 85 Rating Parameter Symbol Conditions Unit MIN Power supply current 7 NORMAL mode fs fosc 2 SLOW mode fs fx 2 fosc 10 MHz 1 1551 Double speed mode fs fosc 2 5 5 5 Vpp 3 0 V fosc 8 5 MHz 2 1502 Double speed mode fs fosc Vpp 3 0 V 1503 fosc 4 25 MHz 3 Double speed mode fs fosc 1 0 2 2 mA Vpp 3 0 V Ipp4 fosc 8 5 MHz Normal mode fs fosc 2 1 2 2 6 Vpp 3 0 V 1505 fosc 4 25 MHz 5 Normal mode fs fosc 2 0 6 1 4 Vpp 3 0 V 1x 32 768 kHz Vpp 3 0 V DD 4 15 i bpe fs fx 2 Ta 25 C 7 1x 32 768 kHz 3 V _ _ 50 DD7 fs fx 2 85 C fosc 5 MHz 8 1508 Double speed mode fs fosc 2 4 t b d Vpp 3 3 V fosc 4 25 MHz 9 Double speed mode fs fosc 2 1 t b d Vpp 3 0 V 15910 fosc 10 MHz 10 Flash EEPROM version Normal mode fs fosc t b d Power supply current Vpp 3 3 V 15511 fosc 8 5 MHz 11 Normal mode fs fosc 2 2 3 t b d Vpp 3 0 V fx 32 768 kHz Vpp 3 0 V 15 i tuo Ta 25 C peo 1x232 768 kHz Vpp 3 V 1 gt t b d 0013 tfs tx Ta 85 C 2 0 4 0 Mask ROM version Power supply current mA
37. Description Output data 0 Output L VSS level 1 Output H VDD level O O Q O IV 22 Port 2 Chapter 4 Ports 4 3 3 Block Diagram NE P20UT7 go Port output data c Sq a Schmitt trigger input Reset Figure 4 3 1 Block Diagram 27 Port 2 IV 23 Chapter 4 Ports IV 24 4 4 Port 4 4 1 Description General Port Setup To output data to pin set the control flag of the port 3 direction control register P3DIR to 1 and write the value of the port 3 output register To read input data of pin set the control flag of the port 3 direction control register P3DIR to 0 and read the value of the port 3 input register P3IN Each bit can be set individually as either an input or output by the port 3 direction control register P3DIR The control flag of the port 3 direction control register P3DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up pull down resistor is added or not by the port 3 pull up pull down resistor control register P3PLUD Set the control flag of the port 3 pull up pull down resistor control register P3PLUD to 1 to add pull up resistor Port 3 can be selected to add pull up resistor or pull down resistor by bp3 of the pull up pull down resistor selec tion register SELUD For P32 and P33 eac
38. Description Serial data input selection 0 Data input from SBI1 RXD1 1 Data input from SBO1 TXD1 SC1SBTS SBT1 pin function selection 0 Port 1 Transfer clock I O SC1SBIS Serial input control selection 0 Input 1 1 Input serial SC1SBOS SBO1 TXD1 pin function 0 Port 1 Output serial data SC1CKM Transfer clock dividing selection 0 Not divided 1 Divided by 8 SC1MST Clock master slave selection 0 Clock slave 1 Clock master SC1DIV Transfer clock dividing selection 0 Devided by 8 1 Devided by 16 XII 8 SC1CMD Control Registers Synchronous serial duplex UART selection 0 Synchronous serial 1 Duplex UART Chapter 12 Serial interface 1 Serial interface 1 Mode Register 2 SC1MD2 0x03F9B bp 7 6 5 4 3 1 0 Flag SC1FM1 SC1FMO SC1PM1 SC1PMO 1 SC1BRKF SC1BRKE Reset 0 0 0 0 0 0 0 Access R Description Frame mode specification 00 7 data bit 1 stop bit 01 7 data bit 2 stop bit 10 8 data bit 1 stop bit 11 8 data bit 2 stop bit SC1FM1 SC1FMO Added bit specification Transmission Reception SC1PM1 00 Add 0 Check for 0 SC1PMO 01 Add 1 Check for 1 10 Add odd parity Check for odd parity 11 Add even parity Check for even parity Parity enable SC1NPE 0 Enable parity bit 1 Disable parity bit Break status receive monitor SC1BRKF 0 Data reception 1 Break reception
39. Timer 1 and timer 2 can be used as a baud rate timer Refer to Chapter 5 5 8 Serial Transfer Y Clock Output Operation XI 62 Operation Chapter 12 Serial interface 1 Chapter 12 Serial interface 1 XII 2 12 1 Overview This LSI contains a serial interface 1 that can be used for both communication types of clock synchronous and UART duplex Also the used pins can be switched to A port 1 P15 TMOOB SBOIA TXDI A SEGI P16 TM2IO SBIIA RXDIA SEGO P17 TM20B SBT1A SEG8 or to B Port A PAS ANS SBOIB TXDIB PA6 AN6 SBT1B PA4 ANA SBIIB RXDIB VPP On this text if there are not much difference between port A and port B on the operation port Y A and B are omitted age select A as the used pin a Operation with the used pin B is available for 48 pin package product only For 44 pin pack 1211 Functions Table 12 1 1 shows functions of serial interface 1 Table 12 1 1 Serial Interface 1 functions Communication style Clock synchronous UART duplex Interrupt SC1TIRQ SC1TIRQ on transmission completion SC1RIRQ on reception completion Used pins 5 1 5 1 5 TXD1 RXD1 3 channels type 2 channels type O SBO1 SBT1 1 channel type TXD1 Specification of transfer bit count Frame 1108 bits 7 bit 1STOP selection 7 bit 28TOP 8 bit 1 STOP 8 bit 28TOP Selection of parity bit bit control 0
40. Operation stop HALT 0801 osco asoa apu NORMAL 0 0 0 QscillationOscillation OSCI Operating IDLE 0 0 0 1 Oscillation Oscillation XI Operating SLOW 0 0 1 1 Halt Oscillation XI Operating HALTO 0 1 0 QscillationOscillation OSCI Halt HALT1 0 1 1 1 Halt Oscillation XI Halt STOPO 1 0 0 0 Halt Halt Halt Halt STOP1 1 0 1 1 Halt Halt Halt Halt Status in NORMAL mode and HALT mode differ depending upon the XSEL XSEL 0 Halt XSEL 1 Oscillation Figure 2 4 2 Operating Mode and Clock Oscillation CPUM 0x3F00 The procedure for transition from NORMAL to HALT or STOP mode is given below 1 If the return factor is a maskable interrupt set the MIE flag in the PSW to 1 and set the interrupt mask IM to a level permitting acceptance of the interrupt 2 Clear the interrupt request flag xxxIR in the maskable interrupt control register xxxICR set the interrupt enable flag xxxIR for the return factor and set the IE flag in the PSW 3 Set CPUM to HALT or STOP mode flag at the same time with the setting of clock switching functions OSCDBL flag OSCSEL1 lt Do not change the setting of standby functions STOP flag HALT flag OSC1 flag OSC2 OSCSELO flag Set the IRWE flag of the memory control register MEMCTR to clear interrupt request flag by software Il 24 Standby Function Chapter 2 CPU Basics 2 4 3 Transition between
41. XIII 10 D S 0 0 0 0 0 0 0 0 Serial Start Stop Commun Transmis Synchro ACK ACK bit bus sta condi condi ication sion enable level tus tion tion mode Recep selection selection tion mode selection OxO3FA7 SCA4ADO I2CAD7 I2CAD5 I2CAD6 12 4 12 I2CAD2 I2CAD1 I2CADO XIV 6 0 0 0 0 0 0 0 0 Serial interface 4 address setup OxO3FA8 SC4AD1 SELI2C I2CMON 12 I2CADM I2CAD9 I2CAD8 XIV 6 0 0 0 0 0 0 Reset Pin mon Commun Address Serial interface 4 control itor ication mode address setup mode selection selection OxO3FA9 SC4RXB I2CRXB7 2 I2CRXB I2CRXB I2CRXB I2CRXB I2CRXB I2CRXB XIV 5 6 5 4 3 2 1 0 x x x x x x x x Serial interface 4 reception data buffer OxO3FAA SC4TXB I2CTXB7 2 6 2 5 12 4 I2CTXB3 2 2 I2CTXB1 I2CTXBO XIV 5 0 0 0 0 0 0 0 0 Serial interface 4 transmission data buffer XVII 22 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SC4STR WRS I2CINT STRT RSTRT I2CBSY SLVBSY ACKVAL XIV 7 ID 1 0 0 0 0 0 0 Data Interrupt Start Re start Bus Slave ACK transfer detec condi condi busy flag busyflag detec direction tion flag tion tion tion flag determi detection
42. abs 8 gt 1 mem8 abs8 bp BSET abs16 bp mem8 abs16 amp bpdata PSW 7 6 0011 1100 Obp abs 16 um 1 mem8 abs16 bp BCLR io8 bp mem8 IOTOP i08 amp bpdata PSW 0 e 0 5 5 0011 1000 10 lt 08 gt 0 meme8 IOTOP io8 bp BCLR abs8 bp mem8 abs8 amp bpdata PSW 01 274 4 1011 1bp abs 8 gt 0 mem8 abs8 bp BCLR abs16 bp mem8 abs16 amp bpdata PSW 7 6 0011 1100 1bp lt abs 16 m 0 mem8 abs16 bp BTST BTST imm8 Dm Dm amp imm8 PSW 08 0 0653 0010 0000 11Dm lt 8 gt BTST abs16 bp mem8 abs16 amp bpdata PSW 0 67 5 0011 1101 abs 16 gt Branch insti Bcc ructions label if ZF 1 PC 3 d4 label H PC 3 2 3 1001 000H lt d4 gt if ZF 0 3 gt label if ZF 1 PC 4 d7 label H PC 4 2 3 1000 1010 d7 2 if ZF 0 4 label if ZF 1 PC 5 d11 labelj H PC 5 2 8 1001 1010 lt 11 sH 3 if ZF 0 5 BNE label if ZF 0 PC 3 d4 label H PC 3 2 3 1001 001H lt d4 gt 1 if ZF 1 BNE label if ZF 0 PC 4 d7 label H PC 4 2 3 1000 1011 d7 H 2 if ZF 1 4 BNE label if ZF 0 PC 5 d11 labelj H PC 5 2 3 1001 1011 lt d11 19 if ZF 1 5 BGE label if VF NF 0 PC 4 d7 label H
43. Set as TM7OC2 value lt TM70C1 value When TM7OC2 value gt TM70C1 value the IGBT output waveform is fixed to H 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively VI 59 Chapter 6 16 bit Timers One Shot Pulse Output of High Precision IGBT Output At Normal Timer 7 mor Hear S TM7EN Flag Compare 55 IEEE CES Register E EM p o4 3 M Register i i i IGBT Binary Counter 0000 X 0001 X 0002 1 2 NH N 0000 TM7IO output IGBT output 8 output IGBT output Figure 6 9 4 One Shot Pulse Output of High Precision IGBT Output At Normal Timer 7 One Shot Pulse Output of High Precision IGBT Output When the compare register 2 is X 0000 Timer 7 TM7EN Flag Compare i Register 1 i I i i Compare Register 2 IGBT Trigger Binary Counter 0000 X 0001 X 0002 NN X X 0000 TM71O output IGBT output 8 output IGBT output Figure 6 9 5 One Shot Pulse Output of High Precision IGBT Output When the compare register 2 is X 0000 Timer 7 VI 60 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively Chapter 6 16 bit Timers One Shot Pulse Output of High Precision IGBT Output When compare register 2 compare register 1 Timer 7 TM7EN Flag C
44. bp Flag Description O OQ Q O Port 7 P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIR0 mode selection 0 Input mode 1 Output mode Port 7 Pull up pull down Resistor Control Register P7PLUD 0x03F47 P7PLUD7 P7PLUD6 P7PLUD5 P7PLUD4 P7PLUD3 P7PLUD2 P7PLUD1 Chapter 4 Ports P7PLUDO 0 0 0 0 0 0 0 0 bp Flag Description O Q O P7PLUD7 P7PLUD6 P7PLUD5 P7PLUD4 P7PLUD3 P7PLUD2 P7PLUD1 P7PLUD0 1 Added Pull up pull down resistor selection 0 Not added Port 7 Output Mode Register P7OMD 0x03F3C Flag 5 s P7OMD1 P7OMDO At reset 0 0 Access R W R W port TMSIO selection 0 port 1 port 1 selection 0 port P7OMD1 P7OMDO Port 7 IV 53 Chapter 4 Ports Port 7 Nch Open drain Control Register P70DC 0x03F1D P77ODC P76ODC P750DC 0 0 0 P7PLUD7 P7PLUD6 Nch open drain output selection 0 Push pull output 1 Nch open drain output Flag PADWN P3DWN P9DWN P7DWN P1DWN At reset 1 1 1 0 0 Access R W R W R W R W R W Port A pull up pull down selection 0 Pull up 1 Pull down Port 3 pull up pull down selecti
45. 0010 0110 1ADM lt 916 gt MOV d4 SP Dm mem8 d44SP Dm cm 78 2 0110 01Dm lt d4 gt 2 MOV d8 SP Dm mem8 d8 SP Dm 5 3 0010 0110 01Dm lt 8 gt 3 MOV ae Dm mem8 d16 SP Dm 0010 0110 00Dm lt di6 gt MOV i08 mem8 lIOTOP i08 Dm 4 2 0110 00Dm lt 08 gt Dm mem8 abs8 gt Dm 41 2 0100 01Dm abs 8 gt MOV abs12 Dm mem8 abs12 5 Dm 5 2 0100 00Dm abs 12 gt MOV abs16 Dm memB8 abs16 Dm 7 4 0010 1100 00Dm abs 16 gt MOV Dn Am Dn mem8 Am 2 2 0101 1aDn MOV Dn d8 Am Dn mem8 d8 Am f 4 2 0111 1aDn dB gt 1 MOV Dn d16 Am Dnmem8 d16 Am 7 4 0010 0111 1aDn lt 916 nay udo MOV Dn d4 SP Dn mem8 d4 SP 3 2 0111 O1Dn lt d4 gt 2 MOV Dn d8 SP Dn mem8 d8 SP ice fen ee 5 8 0010 0111 01Dn lt 08 gt Dn d16 SP 416 5 7 4 0010 0111 00 d 6 Rue m MOV Dn io8 Dn mem8 IOTOP io8 4 2 0111 000 lt 08 gt MOV Dn abs8 Dn mem8 abs8 4 2 0101 01Dn abs 8 gt MOV Dn abs12 Dnmem8 abs12 5 2 0101 000 abs 12 gt MOV Dn abs16 Dnmem8 abs16 7 4 0010 1101 00Dn abs 16 MOV imm8 i08 imm8 mem8 IOTOP io8 6 3 0000 0010 lt 08 gt lt gt MOV imm8 a
46. 3 The written value is readable only after IIC communication is generated XIII 10 Control Registers Chapter 13 Serial Interface 3 13 3 Operation Serial interface 3 is used as both clock synchronous single master IIC serial interface 13 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 13 3 1 shows the activation source for communication At master a transfer clock is generated by setting data to the transfer data buffer TXBUF3 or by enabling start condition Signals input from SBT3 pin inside serial interface are masked to prevent operating errors by noise except during communication This mask is automati cally released by setting data to TXBUF3 access to the TXBUF3 register or enabling start condition to the data input pin Therefore at slave communication set data to TXBUF3 or input start condition before input external clock However the external clock should be input after more than 3 5 transfer clock interval after the data set to TXBUF3 This wait time is needed to load the data from TXBUF3 to the internal shift register Operation 11 Chapter 13 Serial Interface 3 XIII 12 Table 13 3 1 Synchronous Serial Interface Activation Factor and Cautions Clock Communication type Start condition Activation source of communication Master Transmission Enabled Set transmission data 1 Disabled Set tr
47. IICSREX 0 9 Initialize the monitor flag SC3CTR 0x03FA6 bp6 IIC3STC 0 10 Set the SC3MDO register Select the transfer bit count SC3MDO 0x03FA0 bp2 0 SC3LNG2 0 111 Select the start condition SC3MDO 0x03FA0 bp3 SC3STE 1 Select the first transfer bit SC3MDO 0x03FA0 bp4 SC3DIR 0 Select the IIC communication edge SC3MD0 0x03FA0 bp6 SC3CE1 1 11 Set the SC3MD1 register Select the transfer clock SC3MD1 0x03FA1 bp2 SC3MST 1 Control the pin function SC3MD1 0x03FA1 bp4 SC3SBOS 1 bp5 SC3SBIS 1 bp6 SC3SBTS 1 bp7 SC3IOM 1 12 Set the interrupt level SCSICR 0x03FF3 bp7 6 SC3LV1 0 10 b Set the IIC3ACKS flag of the serial control register SC3CTR to 1 to select enable ACK bit ACK bit is received at transmission that setup of the ACK bit level with the IIC3ACKS flag is not necessary 6 Set the IIC3TMD flag of the serial 3 control register SC3CTR to 0 to select NORMAL mode 7 Set the SC3CMD flag of the serial 3 control register SC3CTR to 1 to select 8 Set the IIC3REX flag of the serial 3 control register SC3CTR to 0 to select the transmission mode 9 Set the IIC3STC flag of the serial control register SC3CTR to 0 0 to initialize the start condition detection flag 10 Set the SC3LNG2 0 flag of the serial 3 mode register SC3MDO to 111 to set the transfer bit count as 8 bits Set the SC3STE flag of th
48. VIII 1 8 1 OVERVIEW geo eo UO ODD EDD I e e P a e a prd erede VIII 2 8 1 T Functions ai eee cete n tetro aps tee I de ses it Be VIII 2 S L Block entiende eg vt eee eee dede ird VIII 3 8 2 ControL Reglsters oe ect E ERU UU RU NU REC au is iQ VIII 4 8 2 Control Registers eR ee VIII 4 8 2 2 Remote Control Carrier Output Control Register essere VIII 5 8 3 Operations c recte qoe ee Een t e VIII 6 8 3 1 Operations ese esiti rui eto f p eg HR saga e e ll ehe VIII 6 8 3 2 Setup EX8mpl s uenerit ten T VIII 8 Chapter 9A Time s pes fo ga deii Sauna LU IX 1 DEV OVerVIe Wa etes en EROR et ni ARGUI Libres IX 2 YEI Functions Hep RERO eiae IX 2 9 1 2 Block Diagr m eee deberet ete ee abana IX 3 9 2 Control Register a oce e ie cae iet prb D e teet Re db ce 4 921 Control Registers i pneoee ord ofr ei re dep 4 9 2 2 Watchdog Timer Control 4 9 J Operation er Ee t RE eese E 5 PENES u 5 9 32 Setup Example a A S n IX 7 Chapter 10 P 1 OVeryVI6 Wo eir t ote PU eie eda cdi e tes veo ee bereit ed 2
49. WDEN fs 26 _ DLYCTR 15 22 7 10 15 220 15 218 _ WDIRQ 15 216 Figure 9 1 1 Block Diagram Watchdog Timer The watchdog timer is also used as a timer to count the oscillation stabilization wait time This is used as a watch dog timer except at recovering from STOP mode and at reset releasing The watchdog timer is initialized at reset or at STOP mode and counts system clock fs as a clock source from the initial value 0x0000 The oscillation stabilization wait time is set by the oscillation stabilization control reg ister DLYCTR Overview IX 3 Chapter 9 Watchdog Timer 9 2 Control Register The watchdog timer is formed by the control register WDCTR 9 2 1 Control Registers Table 9 2 1 shows the registers that control the watchdog timer Table 9 2 1 Watchdog Timer Control Register Functions OxOSF02 Watchdog timer control register 9 2 2 Watchdog Timer Control Register The watchdog timer is controlled by the watchdog timer control register WDCTR Watchdog Timer Control Register WDCTR 0x03F02 Flag Reserved Reserved Reserved At reset 0 0 0 Access Description Reserved Set always to 0 Watchdog time out period setup WDTS1 00 28 of system clock WDTSO 01 2 8 of system clock 1 220 of system clock Watchdog timer enable 0 Watchdog timer is stopped 1 Watchdog timer is operate
50. HA 28 Electrical Characteristics Chapter 1 Overview 1 8 to 3 6V Vss 0V Ta 40 C to 85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX 1x232 768 kHz Vpp 3 0V uA 14 Supply current during 15614 Ta 25 i 4 mode m fx 32 768 kHz Vpp 3 0 V PES 85 fosc stop 16 Supply current during STOP 10016 Vpp 3V 25 5 5 2 17 Ipp17 Vpp 3 V Ta 85 C H 30 7 Measured under conditions without load 25 pull up pull down resistors are unconnected The supply current during operation Ipp to Ipps and to are measured under the following conditions After all I O pins are set to input mode and the oscillation is set to lt NORMAL mode the MMOD pin is at level the input pins are at Vpp level and a 10 MHz 8 50 MHz 5 MHz 4 25 MHz square wave of and amplitudes is input to the OSCI pin The supply current during operation Ippe and Ipp12 Ippis are measured under the following conditions After all I O pins are set to input mode and the oscillation is set to lt SLOW mode the MMOD pin is at level the input pins at level and 32 768 kHz square wave of Vpp Vss amplitudes is input to the XI pin The supply current during HALT1 mode Ipp 4 5015 are measured under the follow
51. R 3 R 2 R 1 R 0 TM3BC7 TM3BC6 TM3BC5 TM3BC4 TM3BC3 TM3BC2 TM3BC1 TM3BCO 0 0 0 0 0 0 0 0 R R R R R R R R Control Registers V 13 Chapter 5 8 bit Timers 5 2 4 Timer Mode Registers j as s Timer mode register is readable writable register that controls timer 0 to 3 Timer 0 Mode Register TMOMD 0x03F54 14 6 5 4 2 1 0 TMOMOD TMOPWM TMOCK2 TMOCK1 TMOCKO Access Description TMOPOP Output signal start polarity selection 0 Timer output PWM 1 Timer output PWM LH TMOMOD Pulse width measurement control 0 Normal timer operation 1 P54 pulse width measurement TMOPWM Timer 0 operation mode selection 0 Normal timer operation 1 PWM operation Timer 0 count control 0 the count 1 Operate the count TMOCK2 TMOCK1 TMOCKO Control Registers Clock source selection X00 fosc X01 TMOPSC Prescaler output 010 fx 011 Synchronous fx 110 TMOIO input 111 Synchronous TMOIO output Chapter 5 8 bit Timers Timer 1 Mode Register TM1MD 0x03F55 bp 4 2 1 0 Flag TM1CAS TM1CK2 TM1CKO At reset 0 0 0 0 Access Description 7 5 4 TM1CAS Timer 1 operation mode selection 0 Normal tim
52. R W Readable Writable R Readable only XV 4 Control Registers Chapter 15 A D Converter 15 2 2 Control Registers A D Converter Control RegisterO ANCTRO 0x03FCB m p p BR F E p p Wie ANGE 0 0 0 0 0 5 Reset Access R W R W R W R W R W Description Sample hold time 00 Tap x2 01 Tap x6 10 Tap 18 11 Tap 18 A D conversion clock 1 00 fs 2 01 fs 4 10 fs 8 11 fx x 2 as gt 800 ns A D ladder resistance control ANLADE 0 A D ladder resistance OFF 1 A D ladder resistance ON Control Registers XV Chapter 15 A D Converter A D Converter Control Register ANCTR1 0x03FCC Flag ANSHS2 ANSHS1 ANSHSO Reset 0 0 0 Access bp Flag Description 7 3 E Analog input channel 000 ANO 001 AN1 ANSHS2 010 AN2 5 51 011 AN3 ANSHSO 100 AN4 101 AN5 110 AN6 111 Reserved A D Converter Control Register2 ANCTR2 0x03FCD Flag Reserved Reset 0 Access A D conversion status ANST 0 Finish Hold 1 Start Converting ANSTSEL A D conversion start factor selection 0 Set ANST flag to 1 1 External interrupt 2 Reserved Set always to 0 6 Control Registers Chapter 15 A D Converter 15 2 3 Data Buffers A D Conversion Data Storage BufferO
53. fosc 32 12 300 fosc 64 fs 2 103 300 25 1202 12 2404 fs 4 51 300 12 1202 4 19 fosc 135 963 108 1201 54 2381 fosc 4 108 300 33 963 fosc 16 fosc 32 fosc 64 fs 2 108 300 33 963 fs 4 54 298 16 963 8 00 fosc 207 1202 103 2404 51 4808 fosc 4 207 300 64 962 51 1202 25 2404 12 4808 fosc 16 51 300 12 1202 fosc 32 25 300 fosc 64 12 300 fs 2 207 300 64 962 51 1202 25 2404 12 4808 fs 4 103 300 25 1202 12 2404 8 38 fosc 217 1201 108 2403 54 4761 fosc 4 217 300 67 963 54 1190 fosc 16 54 298 16 963 fosc 32 fosc 64 fs 2 217 300 67 963 54 1190 fs 4 108 300 33 963 10 00 fosc 129 2404 64 4808 fosc 4 80 965 64 1202 fosc 16 64 300 fosc 32 fosc 64 fs 2 80 965 64 1202 fs 4 129 300 Operation XII 58 Chapter 12 Serial interface 1 XII 54 Table 12 3 24 Setup Value of Serial Interface Transfer Speed 2 When Setting UART Inter Clock to Divided by 16 decimal Transfer speed bit s fosc MHz Clock source Timer 300 960 1200 2400 4800 Set value Calculate d value Set value Calculate d val
54. 16 2 2 Memory Space 2 2 1 Memory Mode ROM is the read only area and RAM is the memory area which contains readable writable data In addition to these peripheral resources such as memory mapped special registers are allocated The MN101C series supports three memory modes single chip mode memory expansion mode processor mode in its memory model This LSI supports one memory modes single chip mode in its memory model Setting of each mode is different In single chip mode the system consists of only internal memory Memory Space Chapter 2 CPU Basics 2 2 2 Mode Jd M M ___ __ In single chip mode the system consists of only internal memory This is the optimized memory mode and allows construction of systems with the highest performance The single chip mode uses only internal ROM and internal RAM The MNIOIC series devices offer up to 11 75 KB of RAM and up to 224 KB of ROM This LSI offers 1 5 KB of RAM and 32 KB of ROM 0 00000 RAM short addressing area Internal RAM 0 00100 2 Data 16 kB 0x00600 0x02E00 LCD display data 0x02E05 256B 0x03F 00 Special function register area Y I O short addressing area 0 04000 Interrupt A 128 B vector table 64 B 0 04080 Sub routine vector table Internal ROM 48kB 0 040 4 48 Instruction code Ta
55. 7 6 5 4 3 2 1 0 TM6OC7 6 6 TM6OC5 TM6OC4 TM6OC3 6 2 TM6OC1 TM6OCO X X X X X X X X Time base timer can be reset its operation by the software Time base timer can be cleared by writing an arbitrary value to the time base timer clear control register TBCLR Time Base Timer Clear Control Register TBCLR 0x03F63 7 6 5 4 3 2 1 0 TBCLR7 TBCLR6 TBCLR5 TBCLR4 TBCLR3 TBCLR2 TBCLR1 TBCLRO w w VII 6 Control Registers Chapter 7 Time Base Timer Free running Timer 7 2 8 Timer 6 Enable Registers B 4 This register controls the starting operation of the timer 6 and the time base timer Timer 6 Enable Registers TM6BEN 0x03F64 Access Description Time base timer operation control 0 Stop 1 Operation Timer 6 operation control 0 Stop 1 Operation a Timer 6 does not start operating unless the TM6EN flag of the TM6BEN register is set to 1 a Time base timer does not start operating unless the TBEN flag of the TM6BEN register is set to 1 Control Registers VII 7 Chapter 7 Time Base Timer Free running Timer 7 2 4 Timer Mode Registers This is readable writable register that controls timer 6 and time base timer Timer 6 Mode Register TM6MD 0x03F62 7
56. Atsegment output port I O direction control is forcefully set to input mode pull up resistor is disabled and segment output is executed by the segment output control Port 7 Chapter 4 Ports IV 59 Chapter 4 Ports Pull up pull down resistor selection 2 lt Few Reset Pull up pull down resistor control e P7PLUD2 we Va gt 2 Lo 2 5 0 an 9 2 direction control 9 WEK 1531 72 Port output data SH B we yn Y Es gt 5 gt Schmitt trigger input 1 P7IN2 Port input data lt I AN Key interrupt input Reget LCD output control Pa WEK Segment output control 02511 m d Segment output data VLC1 Y pu LCD clock o VLC2 E Y a 8 Y VLC3 i e e Y dim Figure 4 6 3 Block Diagram P72 Atsegment output port I O direction control is forcefully set to input mode pull up resistor is disabled and segment output is executed by the segment output control IV 60 Port 7
57. Cascade Connection V 49 Chapter 5 8 bit Timers V 50 Cascade Connection Chapter 6 16 bit Timers Chapter 6 16 bit Timers 6 1 Overview This LSI contains two general purpose 16 bit timers Timer 7 Timer 8 The 16 bit timer has compare register with double buffer Timer 7 High precision 16 bit timer contains 2 sets of compare registers with double buffer ing and 2 sets of independent interrupt functions such as Timer 7 interrupt and Timer 7 compare register 2 match interrupt Timer 8 High precision 16 bit timer contains 2 sets of compare registers with double buffering and 2 sets of independent interrupt functions such as Timer 8 interrupt and Timer 8 compare register 2 match interrupt 6 1 1 Functions 6 1 1 shows the functions of each timer Table 6 1 1 16 bit Timer functions Timer 7 High precision 16 bit timer Timer 8 High precision 16 bit timer Timer pulse output O TM7IO output TM7O output Input source TM7IRQ TM8IRQ T70C2IRQ T8OC2IRQ Timer operation Event count 7 input 8 input 8 output 8 output PWM output duty is changeable O TM71O output TM7O output O 8 output TM8O output High precision PWM output duty cycle are changeable TM71O output TM7O output O 8 output TM8O output Timer operation Event count PWM output High precision PWM output Capture func
58. Data set to TXBUFO Interrup SCOTIRQ Figure 11 3 13 Reception Timing at falling edge start condition is disabled XI 26 Operation Chapter 11 Serial interface 0 Transmission Reception Timing As data is received at the opposite edge of the transmission clock set the polarity of reception data input edge to opposite polarity of the transmission data output edge When transmission and reception are executed at the same time set the start condition to disable to prevent abnormal operation SBTO pin Data is received at the rising edge of clock SBIO pin Data is output at the falling edge of clock Figure 11 3 14 Transmission Reception Timing Reception at rising edge Transmission at falling edge SBTO pin Data is received at the rising edge of clock SBIO pin Data is output at the falling edge of clock SBOO pin Figure 11 3 15 Transmission Reception Timing Reception at falling edge Transmission at rising edge Operation XI 27 Chapter 11 Serial interface 0 Communication Function at Standby Mode This serial interface is capable of slave reception in STANDBY mode CPU operation status can be recovered from standby to normal by the communication complete interrupt SCOTIRQ that is generated after the slave reception In STANDBY mode continuous reception is disabled after data of transfer bit count set by SCOLNG2 0 flags of the SCOMDO register is received The received dat
59. Event count operation means that the binary counter TMnBC counts the input signal from external to the TMnIO pin If the value of the binary counter reaches the setting value of the compare register TMnOC inter rupts can be generated at the next count clock Table 5 5 1 Event Count Input Clock Timer 0 Timer 1 Timer 2 Timer 3 Event input TMOIO input TM1IO input 21 input TMSIO input P14 P70 P16 P71 Synchronous Synchronous Synchronous Synchronous TMOIO input TM11O input 210 input input Count Timing of TMnIO Input Timer 0 1 2 and 3 When TMnIO input is selected TMnIO is input to the count clock of the timer n The binary counter is started to count up at the falling edge of the TMnIO input signal TM71IO Input TM7EN E Flag Compare P N 5 Reiser M Ne X gt ele Counter Interrupt Request Flag Figure 5 5 1 Count Timing of TMnIO Input Timer 0 1 2 and 3 8 bit Event Count Chapter 5 8 bit Timers When the TMnIO input is used as the count clock source the value of the binary counter may reach to an unexpected value To prevent select synchronous TMOIO input lt When is used as the count clock source and the compare register is rewritten during the count operation it may not operate properly To prevent use synchronous TMnIO When the TMnIO input is selected fo
60. Timer 8 compare register 2 lower 8 bits TM8OC2H OxOSF8B Timer 8 compare register 2 upper 8 bits TM8PR2L OxOSF8C Timer 8 preset register 2 lower 8 bits TM8PR2H OxOSF8D Timer 8 preset register 2 upper 8 bits TM8MD3 OxOSF8F Timer 8 mode register 3 TM8MD4 OxOSF6F Timer 8 mode register 4 TM8ICR OxOSFF6 Timer 8 interrupt control register T8OC2ICR OxOSFF7 Timer 8 compare register 2 match interrupt control register P1OMD 0x03F1C Port 1 output mode register P1DIR 0x03F31 Port 1 direction control register P5OMD 0x03F2G Port 5 output mode register P5DIR VI 8 Control Registers 0x03F35 Port 5 direction control register 6 2 2 Programmable Timer Registers Chapter 6 16 bit Timers Timer 7 has a set of 16 bit programmable timer registers which contains a compare register a preset register a binary counter and a capture register Each register has 2 sets of 8 bit register Operate these registers by 16 bit access A compare register is a 16 bit register which stores comparative value of the compare register and the binary counter Timer 7 Compare Register 1 TM7OC1 Table 6 2 3 Timer 7 Compare Register 1 Lower 8 bits TM7OC1L 0x03F72 7 6 5 4 3 2 1 TM7OC1L 7 TM7OC1L 6 TM7OC1L 5 TM7OC41L 4 TM7OC1L 3 TM70C1L 2 TM7OC1L 1 X X X
61. fosc 32 fosc 64 fs 2 fs 4 4 19 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 8 00 fosc 51 9615 31250 fosc 4 12 9615 31250 fosc 16 fosc 32 fosc 64 fs 2 12 9615 31250 fs 4 31250 8 38 fosc 54 9523 fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 10 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 Operation Chapter 12 Serial interface 1 Table 12 3 23 Setup Value of Serial Interface Transfer Speed 1 When Setting UART Inter Clock to Divided by 16 decimal Transfer speed bit s 300 960 1200 2400 4800 fosc Clock source MHz Timer Set value Calculate Set value Calculate Set value Calculate Set value Calculate Set value Calculate d value d value d value d value d value 2 00 fosc 64 962 51 1202 25 2404 12 4808 fosc 4 51 300 12 1202 fosc 16 12 300 fosc 32 fosc 64 fs 2 51 300 12 1202 fs 4 25 300 4 00 fosc 129 962 103 1202 51 2404 25 4808 fosc 4 103 300 25 1202 12 2404 fosc 16 25 300
62. in out P7DIRO P7PLUO Timer 1 I O KEYO Key interrupt input 0 SEG7 SEG7 Segment output P71 KEY1 in out P7DIR1 P7PLU1 TMSIO Timer 1 I O KEY1 Key interrupt input 1 SEG6 SEG6 Segment output P72 KEY2 SEG5 in out P7DIR2 P7PLU2 KEY2 Key interrupt input 2 SEG5 Segment output P73 KEYS SEG4 in out P7DIR3 P7PLUS Key interrupt input SEG4 Segment output P74 KEY4 SEG3 in out P7DIR4 P7PLU4 KEY4 Key interrupt input 4 SEG3 Segment output 1 12 Pin Description Chapter 1 Overview Pins Special Functions yo Direction Pin Functions Description Control Control P75 SBOOB TXDOB in out P7DIR5 P7PLUS SBOOB Serial interface 0 TXDOB UARTO transmission data transmission data output output KEY5 SEG2 KEY5 Key interrupt input 5 SEG2 Segment output P76 SBIOB RXDOB in out P7DIR6 P7PLU6 SBIOB Serial interface 0 reception RXDOB UARTO reception data data input input SDA4B KEY6 SDA4B 1IC4 data I O KEY6 KEY interrupt input 6 SEG1 SEG1 Segment output P77 SBTOB SCL4B in out P7DIR7 P7PLU7 SBTOB Serial interface 0 clock I O SCL4B IIC4 clock I O KEY7 SEGO KEY7 Key interrupt input 7 5 0 Segment 0 output P90 XI in P9DIRO P9PLUO Low speed frequency input pin SBOOA TXDOA in out PADIRO PAPLUO SBOOA Serial interface 0 data output TXDOA UARTO transmission data output ANO ANO Analog 0 input PA1 SBIOA RXDOA in out PADIR1 PAPLU1 SBIOA Serial interface 0 data input RXDOA UAR
63. to bp6 of RXBUFO in this order RXBUFO B C D igo RXBUFO G F E D C B Figure 11 3 19 Transfer Bit Count and First Transfer Bit starting with LSB Operation XI 47 Chapter 11 Serial interface 0 XI 48 The following items are the same as clock synchronous serial B First Transfer Bit Setup Refer to XI 15 B Transmission Data Buffer Refer to XI 15 B Received Data Buffer Refer to XI15 Transfer Bit Count and First Transfer Bit Refer to XI 17 B Transmission Buffer Empty Flag Refer to X1 20 B Emergency Reset Refer to XI 21 Operation Chapter 11 Serial interface 0 Transmission Timing TXDO pin Parity Stop gt Stop bit bit bit SCOTBSY Data set to 1 Interrupt SCOTIRQ Figure 11 3 20 Transmission Timing parity bit is enabled T TXDO pin Stop Stop bt bit SCOTBSY Data setto TXBUFO 1 Interrupt SCOTIRQ Figure 11 3 21 Transmission Timing parity bit is disabled Operation XI 49 Chapter 11 Serial interface 0 Reception Timing Tmin 0 5T T Stop RXDO pin bit SCORBSY u Input start condition Interrupt RENE SCORIRQ Figure 11 3 22 Reception Timing parity bit is enabled Tmin 0 5T f I Parity Stop Stop RXDO pin bt bt SCORBSY A Input start condition Interrupt a SCORIRQ Figure 11 3 23
64. 11044 LNOld 104007 3 9 2 YLOWSW X34380 X34680 X84 0 60 6 60 X83 0 X43 0 9 50 XSAE0 60 X 4 0 Xc4 0 X13 0 X04860 2 2 2 Register Map Figure Memory Space 18 Chapter 2 CPU Basics 2 3 Bus Interface 2 3 1 Bus Controller The MNIOIC series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation There are three such buses ROM bus RAM bus and peripheral expansion bus I O bus They connect to the internal ROM internal RAM and internal peripheral circuits respectively The bus control block controls the par allel operation of instruction read and data access A functional block diagram of the bus controller is given below Instruction Program address Operand address Interrupt queue control k Bus controller Interrupt bus Address decode Address decode Memory mode setting Bus access wait control emory control register Instruction input Bus Data input bus Data output bus
65. 3408 lt 1 woo 99098 20025 Xle i 3HO008 Jonuoo ig 3dN09S Y n 383005 x n T 0 HIS00S 4 lt 5195005 i wit Y Y x 9185005 991005 gqyoos 0402 uoissiusueJ uonipuoo Hes Jus uondeoeg X x 0085 1 4 a x h n 1505 9209 218008 03n8XL uollo l p 5085005 Jeyjng uoissiLusuei Jeyng uonpuoo uelis 4 9105 sigsoos 2 0990058 1000005 2200095 9100095 851 lt gt 86 dVMS n 024005 10204005 0 eawoos 11 1 1 Serial interface 0 Block Diagram Figure Overview Xl 4 Chapter 11 Serial interface 0 11 2 Control Registers 11 2 1 Registers Table 11 2 1 shows registers to control serial interface 0 Table 11 2 1 Serial interface 0 Control Registers Register Address Function SCOMDO OxOSF91 Serial interface 0 mode register 0 SCOMD1 OxOSF92 Serial interface 0 mode register 1 SCOMD2 0x03F93 Serial interface 0 mode register 2 SCOMD3 0x03F94 Serial interface 0 mode register 3 SCOSTR OxOSF95 Serial interface 0 status register RXBUFO 0x03F96 Serial interface 0 reception data buffer TXBUFO 0x03F97 Serial interface 0 transmission data buffer SCSEL OxOSF90 Serial interface pins switching control register PAODC 0x03F2
66. Binary 0000 0001 0002 OS 00004 0001 counter Interrupt request flag Figure 6 4 1 Count Timing TMnIO Input Timer 7 Timer 8 16 bit Event Count VI 29 Chapter 6 16 bit Timers VI 30 If the binary counter is read out during operation incorrect data at counting up may be read Also the binary counter may have unexpected value at the timer stopped To prevent this use the event count by the synchronous TMnIO input which is shown in the following page q When using TMnIO input after selecting fs as the count clock first then set each mode regis ter and preset register After that operate the timer on selecting TMnIO input Do not write any data to the preset register on the operation Only TMnIO input can recover from STOP mode in 16 bit timer q When using the event input TMnIO input clear the binary counter before starting the timer operation Also when setting 0x0000 to the compare register use the event count by TMnlO input which is shown below q When the event input TMnIO input is selected as the count clock source even if the set value is written to the preset register at the timer stop the same set value may not be loaded to the compare register To prevent this select the system clock fx for the count clock source once write the set value to the preset register then select the event input TMnIO as the clock source to start the timer operation lt The
67. C2 4 E Port Vss Figure 16 3 2 LCD Power Supply Connection 2 The LCD power supply V to Vi is supplied as shown in the following Figure 16 3 3 Vi cp value varies depending on the type of LCD Refer to the specifications of LCD for the appropriate value Vici Vico Vss Vica 2 3 Vi Vss Vica 1 3 Vicp Vss Usually Vpp Vss are divided by resistors and supplied to the LCD Standard resistance voltage ranges from tens to several hundreds kW In Figure 16 3 3 a bypass capacitor C 0 01 mF to 0 1 mF is used to lower the impedance of power supply R 4 R EGE Figure 16 3 3 Supplying Voltage to VI to Vi c 16 Operation Chapter 16 LCD B Supplying voltage when using the internal voltage driving circuit Supply the voltage as shown in Table 16 3 3 Table 16 3 3 Static 1 2 bias 1 8 bias Vici Disabled Vicp Vicp Vice Connect VI to Vi 1 2 Vi cp is output 2 3 cp is output Vica j 1 3 cp is output dropped depending on a used LCD panel and that may lower the brightness of LCD display a When internal voltage dividing resistor is used voltages of Vi c4 Vice and Vj could be Use the external divider resistor when this happens ports However depending on the panel if LCD display does not have enough brightness due to the lack of connect
68. Chapter 3 3 1 4 Setup Operation XII 37 Chapter 12 Serial interface 1 XII 38 Note Each procedure 1 to 3 7 8 9 to 10 can be set at the same time At the reception with the start condition input set the SCOSTE flag to 1 and the start condition to enable in step 7 In step 11 execute the start condition input instead of dummy data setting After the start condition input 0 5 or more transfer clock is needed before the clock input At the reception with the start condition input set the SCOSTE flag to 1 to select start condi tion enable at the step 7 in the setup procedure At the step 11 execute the start condition input instead of setting dummy data After start condition input more than 0 5 transfer clock is required for the clock input For transmission with 3 channels set the SC1SBIS of SC1MD1 register to 1 to set the serial input 1 input SBI1 can be used as a general port For reception with chan nels set the SC1SBOS of SC1MD1 register 10 0 to select port SBO1 pin can be used as a general port For communication with 2 channels serial data is input output from the SBO1 pin Input out put is switched by the port direction control register P1DIR At reception set always SC1SBIS of the SC1MD1 register to 1 to select serial input The can be used as a general port This serial interface c
69. Chapter 8 Remote Control Carrier Functions FE Chapter 8 Remote Control Carrier Functions 8 1 Overview Remote control carrier output functions can generate the carrier wave for the remote control and output 8 1 1 Functions Table 8 1 1 shows the remote control carrier output functions Table 8 1 1 The remote control carrier output functions Remote control carrier output base timer Timer 0 selection Timer 3 Duty selection 1 2 1 8 Timer output Remote control carrier output enable factor RMOEN Remote control carrier output enable L level output Remote control carrier output P14 special function selection Timer 0 Remote control carrier output a This function is not available the STOP HALT mode VIIL 2 Overview Chapter 8 Remote Control Carrier Functions 8 1 2 Block Diagram Remote Control Carrier Output Block Diagram Remote control career output TimerO output RMDTYO RMDTY1 Reserved CS 2 gt o x E Figure 8 1 1 Remote Control Carrier Output Block Diagram Overview VIII 3 Chapter 8 Remote Control Carrier Functions 8 2 Control Registers 8 2 1 Control Registers Table 8 2 1 shows the registers that control the remote control carrier output Table 8 2 1 Control Registers Registers Address Function 0x03F6C Remote control carrier output control register
70. Level judgement Accepted if IL IM xxxIE A Generated interrupt level IL Figure 3 1 4 Determination of Interrupt Acceptance lt Acceptance of an interrupt does not reset the corresponding interrupt enable to 0 8 Overview Chapter 3 Interrupts 0 and interrupts are disabled when MIE in PSW is reset to 0 by a program Reset is detected MIE 1 and interrupts are enabled when MIE in the PSW is set to 1 by a program The interrupt mask level IM IMO in the processor status word PSW changes when The program alters it directly A reset initializes it to 0 00b Maskable interrupt is accepted the interrupt level becomes the interrupt mask level Execution of the RTI instruction at the end of an interrupt service routine restores the processor status word PSW and thus the previous interrupt mask level The MN101C series does not reset the maskable interrupt enable MIE flag of the processor Y status word PSW to 0 when accepting interrupts Non maskable interrupts have priority over maskable ones Overview 9 Chapter 3 Interrupts Ill 10 Interrupt Acceptance Operation When accepting an interrupt this LSI hardware saves the handy address register the return address from the pro gram counter and the processor status word PSW to the stack and bran
71. N register i at noo us ME 4555 55871558 counter Capture trigger Synchronous to writing signal Captu re 0000 0114 5558 register Figure 6 8 4 Capture Count Timing Triggered by Writing Software Timer 7 Timer 8 The capture trigger is generated at the writing signal to the input capture register The writing signal is generated at the last cycle of the writing instruction In synchronized with this capture trigger the value of the binary counter 15 loaded to the input capture register The value is depending on the value of the binary counter at the falling edge of the capture trigger The other timing is the same as the timer operation The writing to the input capture to generate the capture trigger should be done with 8 bit access instruction of the TMnICL register or the TMnICH register At this time data is not actually written to the TMnIC register On hardware there is no flag to disable the capture operation triggered by writing software Capture operation is enabled regardless of the flag of the TMnMD register 16 bit Timer Capture 6 8 2 Setup Example Capture Function Setup Example Chapter 6 16 bit Timers interrupt interrupt External interrupt 0 IRQO input Pulse width to be measured Figure 6 8 5 Pulse Width Measurement of External Interrupt 0 Setup Procedure Description 1 Stop the counter TM7MD1 0x03F78 bp4 TM7EN 0 2 Disabl
72. OxOSFE1 R W Non maskable interrupt control register 111 19 xxxICR OxOSFE2 R W Maskable interrupt control register 111 20 to 40 ROEE Reserved OxOSFFF Reserved For reading interrupt vector a 1 apart of bitis for read only Overview Chapter 2 CPU Basics 2 1 3 Instruction Execution Controller Rc M The instruction execution controller consists of four blocks memory instruction queue instruction registers and instruction decoder Instructions are fetched in 1 byte units and temporarily stored in the 2 byte instruction queue Transfer is made in 1 byte or half byte units from the instruction queue to the instruction register to be decoded by the instruction decoder Memory B 15 0 1 byte half byte Instruction register E Instruction decoder 9 Instruction decoding CPU control signals Instruction queue Figure 2 1 2 Instruction Execution Controller Configuration Overview 1 7 Chapter 2 CPU Basics 1 8 2 1 4 Pipeline Process TT Pipeline process means that reading and decoding are executed at the same time on different instructions then instructions are executed without stopping Pipeline process makes instruction execution continual and speedy This process is executed with instruction queue and instruction decoder Instruction queue is buffer that fetches the second instruction in advance That
73. PAPLUD 0x03F4A Port A pull up pull down resistor control register SELUD 0x03F4B Pull up pull down resistor selection register PAIMD 0x03F4E Port A input mode register PAODC 0x03F2D R W Readable Writable R Readable only Overview PortA Nch open drain control register Chapter 4 Ports 42 Port 1 4 2 1 Description General Port Setup To output data to pin set the control flag of the port 1 direction control register PIDIR to 1 and write the value of the port 1 output register PLOUT To read input data of pin set the control flag of the port 1 direction control register PIDIR to 0 and read the value of the port 1 input register Each bit can be set individually as either an input or output by the port 1 I O direction control register PIDIR The control flag of the port 1 direction control register PI DIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up or pull down resistor is added or not by the port 1 pull up pull down resistor control register PIPLUD Set the control flag of the port 1 pull up pull down resistor control register PIPLUD to 1 to add pull up or pull down resistor Port 1 can be selected to add pull up resistor or pull down resistor by bpO of the pull up pull down resistor selec tion register SELUD Each bit can be selected individually as inpu
74. TM8OC1L 7 TM80C1L 6 TM80C1L 5 TM80C1L 4 TM80C1L 3 TM80C1L 2 TM80C1L 1 X X X X X X X R 7 6 5 4 3 2 1 0 TM8OC1 H7 TM80C1 H6 TM8OC1 H5 8 1 H4 TM80C1 H3 TM80C1 H2 TM80C1 H1 TM80C1 HO X X X X X X X X R Timer 8 Compare Register 2 TM8OC2 Table 6 2 19 Timer 8 Compare Register 2 Lower 8bits TM8OC2L 0x03F8A 7 6 5 4 3 2 1 TM8OC2L 7 TM8OC2L 6 TM8OC2L 5 TM8OC2L 4 TM8OC2L 3 TM8OC2L 2 TM8OC2L 1 X X X X X X X R Timer 8 Compare Register 2 Upper 8bits TM8OC2H 0x03F8B 7 6 5 4 3 2 1 0 TM7OC2 H7 TM7OC2 H6 TM7OC2 H5 TM7OC2 H4 TM7OC2 H3 TM7OC2 H2 TM7OC2 H1 TM7OC2 HO X X X X X X X X R Control Registers VI 13 Chapter 6 16 bit Timers Timer 8 preset register 1 and 2 are buffer registers of the compare registers 1 2 of timer 8 If the set value is writ ten to the timer 8 preset registers 1 2 when the counting is stopped the same set value is loaded to the timer 7 compare register If set value is written to the timer 8 preset registers 1 2 during counting the set value of the timer 8 preset registers 1 2 is loaded to the timer 8 compa
75. To prevent noise malfunction of Mask ROM design the circuit of the target board carefully for the signal used for the serial writer Onboard Serial Programming Mode Chapter 17 Appendix 17 3 3 Built in Hardware for Onboard Programming iiiII s i 1 I F The following built in hardware is used as the I F for serial programming of Flash EEPROM One 8bit serial interface Use serial 0 External clock for data transmission reception LSB first transmission bit clock speed can be selected from 500 kbps 250kbps 125kbps or 62 5kbps Input output is positive logic Two channels serial interface SBTOB SBOOB Three I O pins SBTOB SBOOB and P76 serve for both serial interface port and I O port 2 I F Block Diagram SBTOB P77 40pin SBOOB SBOOB 1 sBoo amp P75 38pin PB6 w UJ pve 39pin NRST lt 1210 8 bit Serial Serial Interface 0 Figure 17 3 2 Block Diagram To prevent the other user circuits on the target board shown on the Figure 17 3 2 from communicating SBTOB SBOOB and P76 pins should be reserved for serial programming or the circuit of the target board should be designed for normal communication with serial writer Onboard Serial Programming Mode XVII 7 Chapter 17 Appendix 17 3 4 MN101CF78A Clock on the Target Board B r Use the existing clock on the target board for the clock sup
76. b Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing as the count clock source by the 7 51 to 0 flag 6 Set IGBT timer startup factor to timer 7 count operation 16 bit Standard PWM Output Only duty can be changed consecutively Chapter 6 16 bit Timers Setup Procedure Description 7 Set H period of the PWM output TM7PR1 0x03F75 0x03F74 0x4FFF 8 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 65536 set as operate the timer 7 7 Set H period of the PWM output to the timer 7 preset register 1 TM7PR1 To set 1 4 duty of the full count 65536 4 1 16383 0 0 At the same time the same value is loaded to the timer 7 compare register 1 TM7OC1 and the timer 7 binary counter 7 is initialized to 0 0000 8 Set the TM7EN flag of the TM7MD1 register to 1 to TM7BC counts up from 0x0000 The source waveform outputs until TM7BC reaches the set value of the TM7OCI register then after the match it outputs L After that TM7BC continues to count up Once a overflow occurs the PWM source waveform outputs H again and TM7BC counts up from 0x0000 again 16 bit Standard PWM Output Only duty can be changed consecutively VI 43 Chapter 6 16 bit Timers VI 44 6 7 16 bit High Precision PWM Output Cycle Duty can be changed consec utively The TMnIO pin outpu
77. fosc 32 fosc 64 fs 2 fs 4 8 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 8 38 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 10 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 Operation XI 55 Chapter 11 Serial interface 0 XI 56 B Pin Setup with 1 2 channels at transmission Table 11 3 25 shows the pins setup for UART serial interface transmission The pins setup is common to the TXDO pin RXDO pin regardless of whether the pins are independent connected Table 11 3 25 UART Serial Interface Pin Setup with 1 2 channels at transmission PAPLU PAPLUO P7PLU P7PLUS Setup item Data output pin Data input pin TXDO pin RXDO pin Port pin 75 PA1 P76 Port pin setup Select pin A B SCSEL SCOSL Serial data input selection RXDO SCOMD1 SCOIOM Function Serial data output 1 output SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Push pull N ch open drain PAODC PAODCO P7ODC P7ODC5 y o Output mode PADIR PADIRO P7DIR P7DIR5 Pull up setup Added not added Operation B Pin Setup with 2 channels at reception Chapter 11 Serial interface 0 Table 11 3 26 shows the pins setup for UART serial interface reception with 2 channels TXDO pin RXDOpin
78. port LED3 selection P5LED3 0 port 1 LEDS large current output port LED2 selection P5LED2 0 port 1 LED2 large current output port LED1 selection PBLED1 0 0 port 1 LED1 large current output port LEDO selection P5LEDO 0 0 port 1 LEDO large current output port TM8O selection P5OMDS 0 port 1 TM8O port TM2O selection P50MD2 0 port 1 TM2O port TM7O selection P5OMD 0 port 1 TM7O port TMOO selection P5OMDO 0 port 1 00 IV 44 Port 5 Chapter 4 Ports 4 5 3 Block Diagram gt Pull up resistor control D 8 PSDIRO 0 direction control Q Wok e UTO gt Y Port output data eeg co ce e 5 Y gt Port output control D Q LED output control D Q 184 Wok VR Schmitt trigger input Port Input Data Timer 0 output Figure 4 5 1 Block Diagram P50 P5PLU1 R O Pull up resistor control Re o P5DIR1 R 20 direction control Ato lt lt gt oe P5OUTI Port output data sng
79. 1 1 1 1 1 1 I I 1 I 1 1 1 1 I 1 i I 1 I 1 I 1 I 1 1 Des I A h Additional bit H H II I U UU Additional bit During 4 cycles of the PWM basic waveform additional pulses 1 256 pulse width of PWM basic waveform can be added in any of the periods 0 to 3 Figure 5 7 4 5 7 3 Setup Example Chapter 5 8 bit Timers B PWM Output Setup Example Timer 0 and 2 The 1 4 duty cycle output waveform is output from the TMOIO output pin at 19 53 Hz by using the timer 0 Fs 2 oscillates at 5 MHz Cycle period of PWM output waveform is decided by the overflow of the binary counter period of the PWM output waveform is decided by the setting value of the compare register An example setup procedure with a description of each step is shown below TMOIO output 19 58 Hz gt Figure 5 7 5 Output Waveform of TMOIO Output Pin Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 2 iSelect the special function pin to output P1OMD 0x03F1C P1OMDO 1 P1DIR 0x03F31 P1DIRO 1 3 Select the PWM operation TMOMD 0x03F54 bp4 TMOPWM 1 bp5 TMOMOD 0 bp6 0 4
80. 41 5 8 T Operation eigene ea aut ah Ava ee heroes d re 41 5 82 Setup Example nie eret RAT ege envies teamed teens V 42 5 9 Simple Pulse Width V 43 S 9 T estie recette Le e eeu E dnce V 43 5 92 Setup sc ae eee nis a Respeto toa ies V 44 5 10 Cascade Connection reete I de ERR EU V 46 5 10 1 Operations ic ee ea pred ete OI ORE V 46 5 1022 Setup Example 5 opti etes eee sheep heut ee teuer rete V 48 Chaplet 16 bit TINETS u qa VI 1 SE SE 1 2 6 1 Eunctions Ute ne RII Ep Us roster VI 2 6 1 2 Block Diagram nete eet edo eie Ree tedden das e RR VIA 6 2 Control Registers ioo dne e e Date ea e P eee VI 6 6 2 T Registers cios cere TO DB Ue OA eie eee ty VI 7 6 2 2 Programmable Timer Registers VI 9 6 2 3 Timer Mode Registers VI 16 6 DS aS S SSO aS a a a e Ree teed VI 24 631 ss e e rt ote i celi VI 24 Contents 5 6 3 2 Setup Example 5 oe er D po E Pe e VI 28 6 4 16 bit Event Count regt rege ien ime e ehem VI 29 6 4 ID Operation xe eU RU RD Dei qiiae ete ien VI 29 6 4 2 Setup Example ee HERR RR eee oerte eU VI 33 6 5 J6
81. External Interrupts 44 Chapter 3 Interrupts jsenboiJ jdnuejur yeubis 0 ELAJA aniz LA3M uonoejep uonoejep 1In2419 Figure 3 3 4 External Interrupt 4 Interface Block Diagram 45 External Interrupts B External Interrupt 4 Interface Block Diagram LA3M Chapter 3 Interrupts 3 3 3 Control Registers The external interrupt input signals which passed through each internal interrupt interface 0 to 2 and 4 generate interrupt requests External interrupt 0 to 2 and 4 interface are controlled by the external interrupt control register IROnICR External interrupt interface 0 to 1 are controlled by the noise filter control register NFCTR and the prescaler control register PSCMD and external interrupt interface 2 is controlled by the both edges interrupt control reg ister EDGDT and external interrupt interface 4 is controlled by the key interrupt control register 1 KEYT3 1IMD and the key interrupt control register 2 KEYT3 21MD Table 3 3 2 shows the list of registers which control external interrupt 0 to 2 and 4 Table 3 3 2 External Interrupt Control Register External Register Address R W
82. Function Page interrupt External inter IRQOICR OxO3FE2 R W External interrupt O control register 1 20 TES NFCTR OxO3F2E R W Noise filter control register 111 48 PSCMD Ox03F6D R W Prescaler control register 1 47 External inter IRQ1ICR OxO3FES R W External interrupt 1 control register 11 21 is NFCTR OxO3F2E R W Noise filter control register 11 48 PSCMD Ox03F6D R W Prescaler control register 11 47 External inter IRQ2ICR OxO3FE4 R W External interrupt 2 control register 1 22 is EDGDT OxOSF1E R W Both edges interrupt control register 11 53 IRQ4ICR OxOSFE6 R W External interrupt 4 control register 23 11 R W Key interrupt control register 1 1 50 _21 OxOSFSF R W Key interrupt control register 2 11 51 R W Readable Writable Ill 46 External Interrupts Chapter 3 Interrupts Prescaler Control Register PSCMD Prescaler control register enables or disables the prescaler count Prescaler is used when the dividing clock of fs base is used at IRQO IRQI Table 3 3 3 Prescaler Control Register PSCMD 0x03F6D Prescaler count control 0 Disable count 1 Enable count External Interrupts Ill 47 Chapter 3 Interrupts Noise Filter Control Register NFCTR The noise filter control register NFCTR sets the noise remove function to IRQO and IRQI and also selects the sampling c
83. Pull up setup Added Not added Added Not added PAPLU PAPLU2 P7PLU P7PLU7 Operation Pins Setup with channels transmission reception Chapter 11 Serial interface 0 Table 11 3 9 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO SBTO pin at transmission reception Table 11 3 9 Setup for Synchronous Serial Interface Pin with 3 channels at transmission reception PAPLU PAPLUO P7PLU P7PLUS5 Setup item Data output pin Data input pin Clock pin SBOOA pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin 75 PA1 P76 PA2 P77 Port pin setup Select pin A B SCSEL SCOSL Serial data input SBIO selection SCOMD1 SCOIOM Function Serial data output Serial input Transfer clock I O Transfer clock SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Style Push pull N ch Push pull N ch open Push pull N ch open open drain drain drain PAODC PAODCO PAODC PAODC2 P7ODC P7ODC5 P7ODC P7ODC7 Input mode Output mode Input mode PADIR PADIRO PADIR PADIR1 PADIR PADIR2 P7DIR P7DIR5 P7DIR P7DIR6 P7DIR P7DIR7 Pull up setup Added Not added Added Not added Added Not added PAPLU PAPLU2 P7PLU P7PLU7 Operation XI 31 Chapter 11 Serial interface 0 XI 3
84. SBOO output after the data SCOFDC1 flag SCOFDCO flag output holding period of the last bit 0 0 Fixed to 1 High output 1 0 Last data holding 0 1 Fixed to 0 Low output 1 1 Reserved Operation XI 21 Chapter 11 Serial interface 0 Other Control Flag Setup Table 11 3 6 shows the flags that do not required to be set or monitored as the flags are not used at clock synchro nous communication Table 11 3 6 Other Control Flag Register Flag Detail SCOMD2 SCOBRKE Break status transmission control SCOBRKF Break status reception monitor SCONPE Parity enable SCOPM1 to 0 Added bit specification SCOFM to 0 Frame mode specification SCOSTR SCOPEK Parity error detection SCOFEF Frame error detection XI 22 Operation Chapter 11 Serial interface 0 Transmission Timing At master At slave Tmax 25T T T f f e U Clock SBTO pin Output pin SBOO pin Transfer bit counter SCO TBSY Data set to TXBUFO Interrupt SCOTIRQ Figure 11 3 6 Transmission Timing at falling edge start condition is enabled At master At slave 3 5 T f f f f f Tmax 2T Clock SBTO pin Output pin 5800 pin Transfer bit counter SCO TBSY Data set to Interrupt SCOTIRQ Figure 11 3 7 Transmission Timing at falling edge start condition is disabled Operation XI 23 Chapter 11 Serial
85. Stop bit 1 2 bits The SCOFM1 to 0 flag of the SCOMD2 register sets the frame mode Table 11 3 17 shows the UART serial inter face frame mode settings If the SCOCMD flag of the SCOMDI register is set to 1 UART communication is selected the transfer bit count on the SCOLNG2 to 0 flag of the SCOMDO register is no longer valid 11 3 17 UART Serial Interface Frame Mode SCOMD register Frame mode SCOFM1 SCOFMO 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits Stop bit 2 bits Operation XI 45 Chapter 11 Serial interface 0 Parity bit is to detect wrong bits with transmission reception data Table 11 3 18 shows types of parity bit The SCONPE SCOPMI to 0 flag of the SCOMD2 register set parity bit Table 11 3 18 Parity Bit of UART Serial Interface SCOMD2 Parity bit Setup SCONPE SCOPM1 SCOPMO 0 0 0 Fixed to 0 Set parity bit to 0 0 0 1 Fixed to 1 Set parity bit to 1 0 1 0 Odd parity Control that the total of 1 of parity bit and character bit should be odd 0 1 1 Even parity Control that the total of 1 of parity bit and character bit should be even 1 None Do not add parity bit Break Status Transmission Control Setup The SCOBRKE flag of the SCOMD2 register generates the brake status If SCOBRKE is set to 1
86. TM7PR1 TM7PR1 TM7PR1 VI 10 H7 H6 H5 H4 H3 H2 H1 H0 x x x x x x x x Timer 7 preset register 1 upper 8 bits OxO3F76 TM7ICL TM7ICL7 TM7ICL TM7ICL TM7ICL TM7ICL TM7ICL TM7ICL TM7ICL VI 11 6 5 4 3 2 1 0 x x x x x x x x Timer 7 input capture register lower 8 bits 0x03F77 TM7ICH TM7ICH7 TM7ICH TM7ICH TM7ICH TM7ICH TM7ICH TM7ICH TM7ICH VI 11 6 5 4 3 2 1 0 x x x x x x x x Timer 7 input capture register upper 8 bits 0x03F78 TM7MD1 Reserved T7ICED TM7CL TM7EN TM7PS1 TM7PSO TM7CK1 TM7CKO VI 16 G1 0 0 1 0 0 0 0 0 Set Capture Timer Timer Count clock selection Clock source selec alwaysto trigger output count tion 0 reset control signal 0x03F79 TM7MD2 T7ICED TM7PW TM7BC TM7PW TM7IRS T7ICEN T7ICT1 T7ICTO VI 17 GO MSL R M 1 0 0 0 0 0 0 0 0 Capture PWM TM7 Timer Timer 7 Input Capture trigger trigger mode count output interrupt capture edge selection clear wave factor opera selection factor form selection tion selection selection enable OxO3F7A TM7OC2L TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 VI 9 L7 L6 L5 L4 L3 L2 L1 10 x x x x x x x x Timer 7 compare register 2 lower 8 bits OxO3F7B TM7OC2H TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 TM7OC2 VI 9 H7 H6 H5 H4 H3 H2 H1 HO x x x x x x x x Timer 7 compare register 2 upper 8 bits XVII 16 Special Function Registers List Chapter 17
87. WK VR gt x ep uem s Port output data grt ae WEK R V FEF Schmitt trigger input 3 P3IN4 y Port input data lt ui av Reset i vices LCD output control g WEK R o VLC3 Figure 4 4 5 Block Diagram P34 Reget PSDWN Pull up pull down resistor selection R N Reset Pull up pull down resistor control pR PSPLUDS P P3DIRS R direction control o amp Yo Yo 5 5 L je P3OUT5 i R gt Port output data snq eq 5 Schmitt trigger input lt lt Port input data lt PONS R A 5 Reset VLC2SL LCD output control D Q WEK N FR U VLC2 Figure 4 4 6 Block Diagram P35 Port 3 IV 37 Chapter 4 Ports Pull up pull down resistor selection Pull up pull down resistor control direction control Reset 1o P3DWN H R r 2 paq PSPLUDE 2 Wek LEX Reset P3DIR6 ony U X Port output data 0 qo 11 WEK V
88. Winitiating a Reset There are two methods to initiate areset 1 Drive the NRST pin low for at least four clock cycles NTST pin should be holded low for more than 4 clock cycles 200 ns a ta 20 NRST pin 4 clock cycles 200 ns at a 20 MHz Figure 2 8 1 Minimum Reset PUlse Width 2 Setting the 2 7 flag of the P2OUT register to 0 outputs low level at P 27 NRST pin And transfering to reset by program software reset can be executed If the internal LSI is reset and register is initiated the 2 Important information from the text footer Page and section title About This Manual 1 gt 7 flag becomes 1 and reset is released On this LSI the starting mode is NORMAL mode that high oscillation i 4 5 the base clock When the power voltage low circuit is connected to NTST pin circuit t hat gives pulse for enough low level time at sudeen unconnected And r set be generated even if its pulse is low level as the oscillation clock is under 4 clocks take notice of noise 11 48 Reset Main text Precautions and warnings Precautions are listed in case Be sure to read these of lost functionality or damage mFinding Desired Information This manual provides three methods for finding desired information quickly and easily 1 Consult the index at the front of the manual to locate the begin
89. rupt mask level in PSW Machine cycles until accepted 12 12 12 PWS status after acceptance All flags are cleared to 0 The interrupt mask level flag in PSW is cleared to 00 Values of the interrupt level flag xxxLVn are set to the interrupt mask level mask ing all interrupt requests with the same or the lower priority Overview 3 Chapter 3 Interrupts 3 1 2 Block Diagram PSW 7 654 3 2 MIE IM1 IMO Level deter mination IRQNMI gt Interrupt CPU core Vector 1 IRQLVL 2 0 WDOG 7 6 IRGOIGR Peripheral J J function xxxLV Interrupt Level XxxlE Interrupt Enab XXXIR Interrupt Reques xxxLV1 0 function VO xxxLV Interrupt Level xxxIE Interrupt Enable xxxIR Interrupt Request Figure 3 1 1 Interrupt Block Diagram 4 Overview Chapter 3 Interrupts 3 1 8 Operation HE 2 2 m lt lt 2 Interrupt Processing Sequence For interrupts other than reset th
90. 0 and data line 5813 pin 3 channels or SBO3 pin 2 channels changes from H to L while the clock line SBT3 pin is H It is also detected when the SC3CEI flag of the SC3MDO register is set to 1 and data line SBI3 pin 3 channels or SBO3 pin 2 channels changes from H to L while the clock line SBT3 pin is L Set the SC3SBOS flag of the SC3MDI register to 0 before change the start condition edge When transmission and reception are executed at the same time set the start condition to disable in order to pre vent abnormal operation First Transfer Bit Setup The SC3DIR flag of the SC3MDO register sets the first bit to be transferred LSB or MSB can be selected B Transmission Data Buffer The transfer data buffer TXBUF3 is the spare buffer which stores data to be loaded to internal shift register Set the data to be transferred to transfer data buffer TXBUF3 and the data is automatically loaded to internal shift register The data loading takes more than 3 transfer clocks cycles Data setting to TXBUF3 again during data loading may not be operated properly You can determine whether or not data loading is in progress by monitoring transfer buffer empty flag SC3TEMP of the SC3STR SC3TEMP flag is set to 1 when data is set to TXBUF3 and cleared to 0 when data loading ends Set data to TXBUF3 Y i Clock x Prescaler output SC3TEMP Clock SBT3 pin e Data loading time
91. 1 1 1 0 0 Access R W R W R W R W R W Port A pull up pull down selection 0 Pull up 1 Pull down Port 3 pull up pull down selectionl 0 Pull up 1 Pull down Port 9 pull up pull down selectionl 0 Pull up 1 Pull down Port 7 pull up pull down selectionl 0 Pull up 1 Pull down Port 1 pull up pull down selectionl 0 Pull up 1 Pull down Port 1 IV 11 Chapter 4 Ports Port 1 Real Time Output Control Register 0 P1CNT0 0x03F3D P1CNTO05 04 P1CNTO3 02 PICNTO1 P1CNTOO 0 0 0 0 0 0 Description P16 real time control 00 port real time control disabled 0171 High output 1070 Low output 11 Hi z output P1CNTO05 P1CNT04 P14 real time control 00 port real time control disabled 0171 High output 1070 Low output 11 Hi z output 1 P1CNTO2 P12 real time control 00 port real time control disabled 0171 High output 1070 Low output 11 2 output P1CNTO1 1 00 12 Port 1 Chapter 4 Ports Clock Output Control Register 0 P1CNT0 0x03F3D SCHMITT CLKSEL 0 0 Description Port 1 Port 3 Port A input level switching SCHMITT 0 VIH 0 8 VDD VIL 0 2 VDD 1 VIH 0 54 VDD VIL 0 3 VDD Clock output capability 0 general port output capability 1
92. 1 2 duty Vicp Display Chapter 16 LCD XVI 25 Chapter 16 LCD 16 4 4 Setup Example 1 2 duty C M P nn Setup example of the LCD 1 2 duty An example of setup procedure to display 23 on a 2 digit 8 segment type LCD panel with both segment signals SEGO to SEG7 and common signals COMO using an external dividing resistor is shown below Chapter 16 4 3 LCD Display 1 2 duty Clock source fosc 4 MHz a LCD clock source 215 122 Hz flame cycle 61 Hz are selected in this example Setup Procedure Description 1 Stop the LCD operation 1 Set the LCDEN flag of the LCD mode control register LCDMD1 X SFCO LCDMD1 to 0 to stop the LCD operation bp7 LCDEN 0 2 Set the display duty 2 Set the LCDTY1 to LCDTYO flags of the LCD mode LCDMD1 X SFCO control register LCDMD1 to 10 to enter 1 2 duty bp5 4 LCDDTY1 0 10 driving mode 3 Select the LCD clock source 3 Select fosc 2 as a LCD clock source by the LCDCK3 LCDMD1 X 3FC0 to LCDCKO flags of the LCD mode control register 1 bp3 0 LCDCK3 0 0100 LCDMD1 4 Select the segment output port pin 4 Select the SEG3 to SEGO and to COMO by the Select the common output port pin LCD output control register 1 LCCTR1 and SEG7 to LCCTR1 X 3FC2 SEGA by the LCD output control register 2 LCCTR2 bp7 0 SC1SL3 0 COMSL3 0 11110011 LCCTR2 X 3FC3 bp3 0 SC2
93. 5 22 Timer Prescaler Registers rv vO 1 Timer prescaler selection register selects the count clock for 8 bit timer The register which selects prescaler output is consisted by the timer prescaler selection register CKnMD Timer 0 prescaler selection register CK0MD 0x03F56 bp 5 4 3 2 1 0 Flag TMOADD TMOADD TM0ADDEN TM0PSC1 TMOPSCO TMOBAS At reset Access Description Additional pulse position within PWM 4 periods 00 None 01 2nd period 10 1st 3rd periods 11 1st 2nd 3rd periods TM0ADD1 TM0ADD0 TM0ADDEN Additional pulse method PWM output control 0 Disabled 8 bit PWM output 1 Enabled Clock source selection 000 fosc 4 TM0PSC1 TMOPSCO TMOBAS 010 fosc 16 100 fosc 32 110 fosc 64 X01 fs 2 X11 fs 4 Control Registers Chapter 5 8 bit Timers Timer 1 Prescaler Selection Register CK1MD 0x03F57 2 1 0 TM1PSC1 TM1PSCO TM1BAS 0 0 0 Description V 10 TM1PSC1 TM1PSC0 TM1BAS Control Registers Clock source selection 000 fosc 4 010 fosc 16 100 fosc 64 110 fosc 128 X01 fs 2 X11 fs 8 Chapter 5 8 bit Timers B Timer 2 Prescaler Selection Register CK2MD 0x03F5E 5 4 3 2 1 0 TM2ADD TM2ADD TM2ADDEN TM2PSC1 TM2PSCO TM2BAS Description TM2ADD1 TM2ADDO Additional pulse position within PWM 4 p
94. Capture 8 Timer 8 Timer 8 sampling count output output PWM selection edge selection control output selection at timer polarity 8 halt selection OxO3F90 SCSEL TMPSC1 TMPSC1 TMPSC TMPSC SC4SL SC1SL SCOSL 12 2 1 2 O1 0 0 0 0 0 0 0 Serial 1 Timer 2 output Serial 0 timer 2 output Serial 4 Serial 1 Serial 1 dividing selection dividing selection pin pin pin Switch switch switch ing ing ing 0x03F91 SCOMDO SCOCE1 SCODIR SCOSTE SCOLNG SCOLNG SCOLNG XI 7 2 1 0 0 0 0 1 1 1 Transmis Transfer Start Synchronous serial transfer bit sion bit speci condi selection Recep fication tion tion edge selection selection OxO3F92 SCOMD1 SCOIOM SCOSBT SCOSBI SCOSBO SCOCK SCOMST SCODIIV SCOCM XI 8 S S S M D 0 0 0 0 0 0 0 0 Serial SBT Serial SBOO Transfer Clock Transfer Synchro data function input function clock master clock nous input selection control selection dividing slave dividing URT selection selection Selection selection selec tion 1 8 1 16 OxO3F93 SCOMD2 SCOFM1 SCOFMO SCOPM1 SCOPMO SCONPE SCOBRK SCOBRK XI 9 F E 0 0 0 0 0 0 0 Frame mode specifi Added bit specifica Parity Bread Break cation tion enable status status recep trans tion mission monitor control Special Function Registers List XVII 19 Chapter 17 Appendix Bit Symb
95. Flag Compare I PON Register 1 i i i i I I M Register 2 i i i i i i IGBT Trigger er won Ka CY Yorn m Counter TM7IO output IGBT Output 8 b E A TM8IO output IGBT Output Figure 6 9 1 Count Timing of High Precision IGBT Output At Normal A When IGBT trigger is input IGBT operation becomes valid after 1 count clock After IGBT output is valid it is L until the next count clock B When IGBT trigger is valid it is H during the period when the value of the binary counter reaches that of TM70OC2 from X 0000 H output from X 0001 at the first operation cycle C After the TM7OC2 compare match it is L and the binary counter counts up until the counter reaches the compare register to be cleared D When the binary counter is cleared it becomes H again E When IGBT trigger becomes invalid the timer is initialized and IGBT output forcibly becomes L Count Timing of High Precision IGBT Output When the compare register 2 is X 0000 Timer 7 The following shows the count timing as the compare register 2 is set to X 0000 Count Clock TM7EN Flag Compare Register 1 Compare Register 2 IGBT Trigger x x x x x x diy er 0000 0001 X 0002 0000 X 0001 X MX 0000 TM7IO output IGBT output TM8IO output IGBT output Figure 6 9 2 Count Timing of High P
96. LCD clock F1 5 Vic2 4 ee S gt 2 Vica e Figure 4 4 1 Block Diagram At common output port I O direction control is forcefully set to input mode pull up resistor is disabled and common output is executed by the common output control Port 3 IV 33 Chapter 4 Ports 2 Ha PSDWN Pull up pull down resistor selection P3PLUD1 gt Pull up pull down resistor control SEES al Rege VO direction control 2 M M y Wek VR pg rp S P3OUT1 L Port output data g a o yw Schmitt trigger input Port input data lt a Ca 2 Serial 3 reception data input COMSL1 Q LCD output control VER m Common output control W Common output data m 1 LCD clock Vica RN 2 Vic3 Y i o Figure 4 4 2 Block Diagram P31 At common output port I O direction control is forcefully set to input mode pull up resistor is disabled and common output is executed by the common output control IV 34 Port 3
97. Overview 1 4 Timer interrupts gt Timer 0 interrupt 8 bit timer Timer 1 interrupt 8 bit timer TM2IRQ Timer 2 interrupt 8 bit timer Timer interrupt 8 bit timer TM7IRQ Timer 7 interrupt 16 bit timer T7OC2IRQ Timer 7 compare register 2 interrupt 16 bit timer Timer 8 interrupt 16 bit timer T8OC2IRQ Timer 8 compare register 2 interrupt 16 bit timer TM6IRQ Timer 6 interrupt 8 bit timer TBIRQ Time base timer interrupt Serial interface interrupts gt SCORIRQ Serial interface 0 interrupt UART reception SCOTIRQ Serial interface 0 interrupt UART transmission synchronous SC1RIRQ Serial interface 1 interrupt UART reception SC1TIRQ Serial interface 1 interrupt UART transmission synchronous SC3IRQ Serial interface 3 interrupt Single master synchronous SC4IRQ Serial interface 4 interrupt Slave IIC Watchdog timer interrupt NMI Non maskable interrupt A D conversion end interrupt ADIRQ A D conversion interrupt A D converter 10 bit x 7 channels Timer counter 9 timers All timer counters generate interrupt Timer 0 8 bit timer for general use Square wave output PWM output Event count Simple pulse width measurement Clock source fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 fx external clock P50 of the large current pin or 15 TMOOB for PWM output Timer 1 8 bit timer for general use or UAR
98. P7ODC registers and pull up resistor can be enabled by the P1PLUD P7PLU registers Select output mode by the P1DIR P3DIR P7DIR registers These can be used as normal I O pins when the serial interface is not used Pin Description Chapter 1 Overview Name TQFP 48 Pin No QFP44 Pin No Other Function Function Description 5013 SCL4A SCL4B 43 14 40 40 37 Input P32 SBT3 COM2 P11 P77 KEY7 SBTOB SEGO clock I O pins Clock I O pin for serial interface 3 4 in IIC mode The output configuration Nch open drain can be selected by P1ODC P3ODC P7ODC registers and pull up resistor can be enabled by the P1PLUD P3PLUD P7PLUD regis ters Select output mode by the P1DIR P3DIR P7DIR registers and select clock I O by the serial mode register 3 SC3MD1 and the serial I O switching control register SCSEL These can be used as normal I O pins when the serial interface is not used TMOIO TM1IO 2 29 33 31 34 26 30 31 Vo P14 RMOUT SEG11 P70 KEYO SEG7 P16 RXD1A SBI1A SEG9 P71 KEY1 SEG6 Timer I O pins Event counter clock input pin timer output and PWM signal output pin for 8 bit timer 0 to 3 To use this pin as event clock input configure this as input by the P1DIR register In the input mode pull up pull down resistors can be selected by the P1PLUD P7PLUD register For timer output PWM
99. SCOLNG2 0 111 Select the start condition SCOMDO 0x03F91 SCOSTE 0 Select the first bit to be transferred SCOMDO 0x03F91 bp4 SCODIR 0 Select the transfer edge SCOMDO 0x03F91 bp7 SCOCE1 1 8 Set the SCOMD1 register Select the communication style SCOMD1 0x03F92 SCOCMD 0 Select the transfer clock SCOMD1 0x03F92 bp2 SCOMST 1 SCOCKM 0 Select the transfer clock SCOMD1 0x03F92 bp4 SCOSBOS 1 bp5 SCOSBIS 1 bp6 SCOSBTS 1 bp7 SCOIOM 0 9 Set the interrupt level SCOTICR OxO3FFO bp7 6 SCOLV1 0 10 4 Set the SCOSL flag of the SCSEL register to 0 to select port A as I O pin b Set the PAODC2 PAODCO flag of the PAODC register to 1 1 and select Nch open drain to SBOO SBTO pin Set the PAPLU2 PAPLUO flag of the PAPLU register to 1 1 to enable the pull up resistor 6 Set the PADIR2 PADIRO flag of the Port A pin direction control register PADIR to 1 1 and the PADIR1 flag to 0 to set PA2 PAO to the output mode to the input mode 7 Set the SCOLNG2 to 0 flag of the serial 0 mode register 0 SCOMDO to 111 to set the transfer bit count as 8 bits Set the SCOSTE flag of the SCOMDO register to 0 to disable the start condition Set the SCODIR flag of the SCOMDO register to O to set MSB as a transfer first bit Set the SCOCE1 flag of the SCOMDO register to 1 to set the reception data input edge falling and the transmission data ou
100. SOLWL 1 Y eiu wpeeu 1401 4 0 158 agJjAO 29141001901 SOOWL Ja si6o1 WMdoWL eMOOWL LADONL 901 H 0DuI 0320IA L QINOIN L SY LNL l uojiuou s X x juosyoukS X indu ONL IN x 490 94 OMOLA L Figure 5 1 2 Timer 0 and 1 Block Diagram V 5 Overview Timer 2 and Block Diagram Chapter 5 8 bit Timers of 5 09SdolA L 9592 01 OMOCWL 015 0 cOul 9G6d 2 4049 endu OIZNL Z 1ndino OIZNL P asind uo py I x n N sind jeuonippyv XJ 56 OUYIEWL 050 YyOO d 1 z elt C
101. TMOPWM 0 operation bp5 TMOMOD 0 VIII 8 Operations Chapter 8 Remote Control Carrier Functions Setup Procedure Description 7 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 8 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 0 TMOBAS 1 9 Set base cycle of the remote control carrier TMOOC 0x03F52 20x36 10 Start the timer operation TMOMD 0x03F54 bp3 TMOEN 1 11 Enable the remote control carrier output RMCTR 0x03F6C bp3 RMOEN 1 7 Select the prescaler output to the clock source by the TMOCk2 to 0 of the TMOMD register 8 Select the fs 2 to the prescaler output by the TMOPSC1 to 0 flag TMOBAS flag of the timer 0 prescaler selection register 9 Set the base cycle of the remote control carrier by writing 0x36 to the timer 0 compare register TMOOC To divide fs 8 MHz to get 1 2 dividing of 36 7 kHz 73 4 kHz the setup value should be fs 2 MHz 73 4 kHz 1 54 0x36 10 Set the TMOEN flag of the TMOMD register to 1 to start the timer 0 11 Set the RMOEN flag of the RMCTR register to 1 to enable the remote control carrier output TMOBC starts the count up from 0x00 As the base cycle pulse that is set at the TMOOC is output from the timer 0 1 3 of the remote control carrier pulse signal is output If the RMOEN flag of the RMCTR register is set to 0 the output signal of the re
102. Table 11 3 26 UART Serial Interface Pin Setup with 2 channels at reception Setup item Data output pin Data input pin TXDO pin RXDO pin Port pin PAO P75 PA1 P76 Port pin setup Select pin A B SCSEL SCOSL Serial data input selection RXDO SCOMD1 SCOIOM Function Port Serial data input SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Input mode PADIR PADIR1 P7DIR P7DIR6 Pull up setup Operation XI 57 Chapter 11 Serial interface 0 B Pin Setup with 1 channel at reception Table 11 3 27 shows the pin setup for UART serial interface reception with 1 channel TXDO pin The RXDO pin can be used as a port as it is not used Table 11 3 27 UART Serial Interface Pin Setup with 1 channel at reception Setup item Data output pin Data input pin TXDO pin RXDO pin Port pin 75 1 76 Port pin setup Select pin A B SCSEL SCOSL Serial data input selection TXDO SCOMD1 SCOIOM Function Port Serial data input SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Input mode PADIR PADIRO P7DIR P7DIR5 Pull up setup XI 58 Operation B Pin Setup with 2 channels at transmission reception Chapter 11 Serial interface 0 Table 11 3 28 shows the pin setup for UART serial interface transmission reception with 2 channels TXDO pin pin Table 11 3 28 UART Se
103. The RXD1 pin can be used as a general port This serial interface contains emergency reset function If communication need to be stopped by force set SC1SBOS and SC1SBIS of the SC1MD1 register to Each flag should be set as the setup procedure in order Activation of communication should be operated after all control registers refer to Table 12 2 1 TXBUF1 RXBUF1 are set Timer 1 and timer 2 can be used as a baud rate timer Refer to Chapter 5 5 8 Serial Transfer Y Clock Output Operation Operation XII 61 Chapter 12 Serial interface 1 XII 62 Operation Chapter 13 Serial Interface 3 Chapter 13 Serial Interface 3 XIII 2 13 1 Overview This LSI contains a serial interface 3 that is capable of both clock synchronous IIC single master serial commu nication 13 1 1 Functions Table 13 1 1 shows the serial interface 3 functions Table 13 1 1 Serial Interface 3 Functions Communication style Clock synchronous single master external clock timer 2 output timer 3 output Interrupt SC3IRQ SC3IRQ Pins SBO3 SBI3 SBT3 SDA3 SCL3 3 channels type 2 channels type SBO3 SBT3 Transfer bit count 1 to 8 bit 1 to 8 bit Start condition First transfer bit Input edge Output edge SBO3 output control after final data is H L last data hold transferred Function in STANDBY mode Slave recep
104. The other count timing is the same as the count timing of the timer operation When the binary counter is used as a free counter which counts 0x0000 to OxFFFF set the compare register 1 to OxFFFF set the TMnBCR flag of the TM7MD2 to 0 Even if an event is generated before the value of the input capture register is read out the value of the input capture register can be rewritten In the initial state after releasing the reset the generation of trigger by the external interrupt signal is disabled Set the TnICEN flag of the TMnMD register to 1 to enable the trigger generation 16 bit Timer Capture VI 51 Chapter 6 16 bit Timers Capture Operation as Timer 0 and 1 interrupts are selected as Trigger Timer 7 Timer 8 A capture trigger of the input capture function is generated by the timer 0 and 1 interrupts signals Select the cap ture trigger by the timer mode register 2 TMnMD2 and the timer mode register 4 TMnMD4 When the timer 0 and 1 interrupts signals are selected as the capture trigger the edges of the capture trigger are disabled Count Clock TM7EN Flag Compare Register 1 Binary Counter Timer 0 1 Interrupt Capture trigger Capture register T 0000 0114 5558 Figure 6 8 2 Capture Operation as Timer 0 and 1 interrupts selected as Trigger Timer 7 Timer 8 input capture function is generated by the timer 0 and 1 interrupts signals Se
105. Time base timer Clock source fosc fx Interrupt enable for source clock at the dividing output of 1 27 1 28 1 2 1 219 1 2 3 1 2 Watchdog timer Watchdog timer frequency can be selected from 15 2 5 15 218 fs 2 Buzzer output Inverted buzzer output Output frequency can be selected from fosc 2 fosc 2 fosc 2 fosc 2 fosc 2 fx 2 Remote control carrier output Based on the timer 0 and timer 3 output a remote control carrier with duty cycle of 1 2 or 1 3 can be output Clock output OSC oscillation source or system clock output can be selected Clock source 1 1 1 2 1 4 1 16 of any one of fosc fx or external clock Hardware Functions 1 5 Chapter 1 Overview Serial interface 4 types Serial interface 0 1 2 channels CHO Duplex UART Synchronous serial interface Transfer clock focs 2 focs 4 focs 16 focs 64 fs 2 fs 4 1 2 of timer 1 timer 2 output Timer 1 or timer2 is used as baud rate timer at UART MSB LSB can be selected as the first bit to be transferred An arbitrate transfer size from 1 to 8 bits can be selected It can be used as parity check overrun error framing error detection or 2 channels serial interface CH1 Duplex UART Synchronous serial interface Transfer clock focs 2 focs 4 focs 16 focs 64 fs 2 fs 4 1 2 of timer 1 timer 2 output Timer 1 or timer2 is used as baud rate timer at UART MSB LSB can be selected as the first bit to be transferred An
106. VO Other Function Function Description SBIOA SBIOB SBHA SBHB 1 5813 17 39 31 20 42 17 36 28 39 Input PA1 SBIOA AN1 P76 SBIOB SEG1 P16 2 SBI1A SEG9 4 DBI1B P31 Serial interface reception data output pins Reception data output pins for serial interface 0 1 3 Pull up and pull down resistors can be selected by the P1PLUD P3PLU P7PLUD PAPLU registers Select input mode by the P1DIR P3DIR P7DIR PADIR registers and serial input mode by the serial mode register 1 SCOMD1 SC1MD1 SC3MD1 These can be used as normal I O pins when the serial interface is not used SBTOA SBTOB SBT1A SBT1B 1 SBT3 18 40 32 22 43 18 37 29 40 2 2 P77 KEY7 50148 SEGO P17 2 SEG8 PA6 AN6 P32 SCL3 COM2 Serial interface clock I O pins Clock I O pins for serial interface 0 1 3 The output configuration either COMS push pull or Nch open drain can be selected at the P1ODC P30DC P7ODC PAODC registers Pull up and pull down registers can be selected by the P1PLUD P3PLU P7PLUD PAPLU registers Select clock I O for each communication mode by the P1DIR P3DIR P7DIR PADIR PADIR registers and the serial mode register 1 SCOMD1 SC1MD1 SC3MD1 These can be used as normal I O pins when the serial interface is not used TXDOA TXDOB TXD1A TXD1B 1 16 38 30 21 16 35 27 Output P
107. When crystal oscillator or ceramic oscil lator is used the frequency is changed depending on the condenser rate Therefore consult the manufacturer of the pin for the appropriate external capacitor Electrical Characteristics 1 25 Chapter 1 Overview 26 Vpp 1 8V to 3 6V 40 to 85 Rating Parameter Symbol Conditions Unit MIN External clock input 1 OSC1 OSC2 is unconnected 27 Clock frequency fosc 1 0 10 0 MHz 28 level pulse width 6 twh1 90 Figure 1 5 3 29 Low level pulse width 6 twit 90 ns 30 Rising time t 10 3 a Figure 1 5 3s 31 Falling time twf 10 External clock input 2 XI XO is unconnected 32 Clock frequency fx 32 768 100 kHz 33 High level pulse width 6 twh2 4 5 Figure 1 5 4 us 34 Low level pulse width 6 2 4 5 35 Rising time 7 t 20 2 Figure 1 5 4 ns 36 Falling time 7 twf2 20 6 The clock duty rate in the standard mode should be 45 to 55 Electrical Characteristics Chapter 1 Overview 1 0 9 lt twh1 gt lt twit gt twr twf1 lt twc1 gt 1 5 3 OSC1 Timing Chart 4
108. avozi odvoel oavros uollo3l p snq sng uonogjes Buissejppy OL esedwoo 5 19151691 145 uondaeoaJ uoISSIUISUPJ Jaying Jayng UOISSIUISUEJ uondeoau 90157815 5 lt 5 x L 0 rosan zoosami ioosani 715795 75105 15025 14525 9 gt Figure 14 1 1 Serial Interface 4 Block Diagram XIV 3 Overview Chapter 14 Serial Interface 4 14 1 3 Control Registers Table 14 1 2 shows the registers that control serial interface 4 Table 14 1 2 Serial Interface 4 Control Registers List Register Address Function SC4AD0 7 Serial interface 4 addressing register 0 SC4AD1 0x03FA8 Serial interface 4 addressing register 1 SC4TXB Ox03FAA Serial interface 4 transmission data buffer SC4RXB Ox03FAQ Serial interface 4 reception data buffer SC4STR 0x03FAB Serial interface 4 status register SCSEL OxO3F90 Serial interface I O pin switching control register P1ODC 0x03F1B Port 1 N ch open drain control register P7ODC OxOSF1D Port 7 N ch open drain control register P1DIR 0x03F31 Port 1 direct
109. condition Data ACK condition Figure 13 3 20 Communication Sequence on Each Transfer Format Figure 13 3 21 Master Transmission Timing Figure 13 3 22 Master Reception Timing Clock Setup The transfer clock for IIC communication is obtained by dividing clock source by 8 inside this serial The clock source is selected from the dedicated prescaler timer 2 or 3 output by the SC3MD3 register The clock source should be set in such a way that the transfer rate is under 100 kHz in NORMAL mode 400 kHz in high speed mode with the SC3MD3 register The dedicated prescaler starts as this register selects prescaler Count Enable Set the SC3MST flag of the SC3MDI register to 1 to select the internal clock clock master This interface can not be used with external clock clock slave Table 13 3 15 Serial Interface Clock Sources Single master Clcok source fosc 2 internal clock fosc 4 fosc 8 fosc 32 fs 2 15 4 timer 2 output timer 3 output Operation Chapter 13 Serial Interface 3 source should be set in such a way that the transfer rate is under 100 kHz in NORMAL mode a The transfer rate in communication is obtained by dividing clock source by 8 The clock 400 kHz in high speed mode with the SC3MD3 register a Set the SC3MST flag of the SC3MD1 register to 1 to select internal clock clock master Set the SC3SBIS an
110. is set to 1 to output the special function data and 0 to use as the general port P13 is used as the output pin of the system clock as well The output mode can be selected by bpO of the clock output control register CLKOUT by each bit The of the clock output control register CLKOUT is set to 1 to output the special function data and 0 to use as the general port P12 P14 P16 have the functions of the real time output control and can switch pin output to 0 1 Hi imped ance Hi z at the event generation timing of the falling edge of the external interrupt 0 The real time control is the function which can change the output signal without the interposition with synchronized to the interrupt event P12 is used as buzzer output pin as well When the bp7 of the oscillation stabilization wait control register DLYCTR is set to 1 and the of the port 1 output mode register PLOMD are set to 01 buzzer out put is enabled P13 is used as inverse buzzer output pin as well When the bp7 of the oscillation stabilization wait control regis ter DLYCTR is set to 1 and the 6 2 of the port 1 output mode register PIOMD are set to 01 inverse buzzer output is enabled P15 is used as the output pin of the serial 1 transmission data and UARTI transmission data as well When the SCISBOS flag of the serial interface 1 mode register 1 SCIMDI is 1 P15
111. of parity bit and character bit is odd SC1FEF Framing error Stop bit is not detected B Judgement of Break Status Reception Reception at break status can be judge If all received data from start bit and stop bit is 0 the SCIBRKF flag of the SCIMD2 register is set and determines the break status The SCIBRKF flag is set when the reception com plete interrupt is generated Operation XII 45 Chapter 12 Serial interface 1 XII 46 Continuous Communication This serial interface has continuous communication function When data is set to the transmission data buffer TXBUFI during communication the transmission buffer empty flag SC1TEMP is automatically set to communi cate continuously This does not generate any blank in communication Set data to TXBUF between previous data setup and generation of the communication complete interrupt SCITIRQ Clock Setup Transfer clock is not necessary for UART communication itself but necessary for setup of data transmission reception timing in the serial interface Select the timer to be used as a baud rate timer by the SC1MD3 register Reception Bit Count and First Transfer Bit At reception when the transfer bit count is 7 bits the data storing method to the received data buffer RXBUFI is different depending on the first transfer bit selection At MSB first data is stored to the upper bits of RXBUFI When the transfer bit count is 7 bits as shown
112. prescaler selection register CK2MD at the bit 5 4 When the CKOMD and the CK2MD register bit 5 and 4 are set as 00 no additional pulse is added to the basic PWM cycle When set as 117 3 out of the 4 periods in the basic PWM cycle are each added with an additional bit pulse Table 5 7 2 shows the relationship between values of CKOMD and CK2MD bits 5 and 4 and the additional pulses Figure 5 7 4 shows the relationship between values of and CK2MD bits 6 and 7 and the position of the additional pulses Table 5 7 2 CKnMD register set value Additional pulse position PWM basic wave form 4 periods bit7 bite 0 0 No additional pulse 0 1 2 period 1 0 1 and 3 period 1 1 1 2 and 3 period Interrupt generates at the 4th cycles of the basic waveform 8 bit PWM Output V 37 Chapter 5 8 bit Timers CKOMD CK2MD bit 5 4 00 No additional pulse CK0MD CK2MD bit 5 4 01 CKOMD CK2MD bit 5 4 40 Interrupt Request Flag V 38 8 bit PWM Output PWM basic waveform 4 periods additional it PWM basic waveform 1 256 pulse widt lt E 1 I 1 i i I 1 1 I PWMbasic wavelorm 8bit 256 resolution 1 1 1 1 I 1 1 1
113. release the reset of the timer pulse output by setting the TMnCL flag of the TMnMD 1 register to 0 Regardless of whether the binary counter is stopped or operated the timer output is L when the TMnCL flag of the TMnMD 1 register is set to 1 a Reset release of the timer pulse output should be done when the timer count is stopped When the prescaler is operated by the timer pulse output set the prescaler dividing rate after Y the reset release of the timer pulse output VI 36 16 bit Timer Pulse Output Chapter 6 16 bit Timers 6 5 2 Setup Example s Timer Pulse Output Setup Example TM71O output pin outputs a 50 kHz pulse using timer 7 For this select fosc as the clock source and set 1 2 cycle 50 kHz to the timer 7 compare register at fosc 10 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counting TM7MD1 0x03F78 bp4 TM7EN 0 2 Set the special function pin P1OMD 0x03F1C bp3 P1OMD3 1 bp2 NBUZSEL 1 P1DIR 0x03F31 bp3 P1DIR3 1 3 Set the timer pulse TM7MD2 0x03F79 bp4 TM7PWM 0 4 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 5 Release the reset of the timer pulse TM7MD1 0x03F78 bp5 TM7CL 0 6 Select the count clock source TM7MD1 0x03F78 bp
114. the binary counter is cleared to 0x0000 at capture by setting the register Timer 8 Binary Counter TM8BC Table 6 2 25 Timer 8 Binary Counter Lower 8 bits TM8BCL 0x03F80 7 6 5 4 3 2 1 0 TM8BCL7 TM8BCL6 TM8BCL5 TM8BCL4 TM8BCL3 TM8BCL2 TM8BCL1 TM8BCLO X X X X X X X X R 7 6 5 4 3 2 1 0 TM8BCH 7 TM8BCH 6 TM8BCH 5 TM8BCH 4 TM8BCH 3 TM8BCH 2 TM8BCH1 TM8BCH 0 X X X X X X X R Input capture register is a register that holds the value loaded from a binary counter by a capture trigger cap ture trigger is generated by an input signal from an external interrupt pin the timer 0 interrupt the timer 1 inter rupt and when an arbitrary value is written to an input capture register Directly writing to the register by program 15 disabled Timer 8 Input Capture Register TM8IC Table 6 2 27 Timer 8 Input Capture Register Lower 8 bits TM8ICL 0x03F86 bp 7 6 5 4 3 2 1 0 Flag TMB8ICL7 TM8ICL6 TM8ICL5 TM8ICL4 TM8ICL3 TM8ICL2 TM8ICL1 TM8ICLO At reset X X X Access Table 6 2 28 Timer 8 Input Capture Register Upper 8 bits TM8ICH 0x03F87 7 6 5 4 3 2 1 0 TM8ICH7 TM8ICH6 TM8ICH5 TM8ICH4 TM8ICH3 TM8ICH2 T
115. x 3F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 00 1 Set the TM7EN flag of the timer 7 mode register TM7MD1 to 0 the TM8EN flag of the timer 8 mode register TM8MD1 to 0 to stop the timer 7 and the timer 8 counting 2 Set the P10MD2 BUZSEL flags of the port 1 output mode register P1OMD to 1 to set the P12 pin as the special function pin Set the P1DIR2 flag of the port 1 direction control register P1DIR to 1 to set the output mode Add pull up pull down register if necessary Chapter 4 Ports 3 Set the TM8CAS flag of the TM8MD3 register to 1 to connect the timer 7 and the timer 8 to the cascade 4 Set the TM7PWM flag of the timer 7 mode register 2 TM7MD2 to 1 to select the PWM output 5 Set the TM7BCR flag of the TM7MD2 register to 1 to select the TM7OC1 compare match as the binary counter clear source Also set the T7PWMSL flag to 1 to select the TM7OC2 compare match as the duty of the PWM output 6 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing as the count clock source by the TM7PS1 to 0 flag 16 bit Timer Cascade Connection VI 83 Chapter 6 16 bit Timers Setup Procedure Description 7 Set the PWM output cycle 7 Set the PWM output cycle to the timer 7 preset register 1 TM7PR1 x 75 3F74 x 37FF 7 1 and the timer 8 preset register 1 8 1 TM8
116. 0 2 Disable the interrupt TM6ICR 0x03FEB bp1 TM6IE 0 3 Select the clock source TM6MD 0x03F 62 bp3 1 TM6CK3 1 001 4 Set the interrupt generation cycle TM6OC 0x03F61 0xF9 5 Enable the interrupt request TM6MD 0x03F 62 bp7 TM6CLRS 1 6 Set the interrupt level TM6ICR 0x03FEB bp7 6 TM6LV1 0 01 7 Enable the interrupt TM6ICR 0x03FEB bp1 TM6IE 1 8 Start the TM6 operation TM6BEN 0x03F64 bp0 TM6EN 1 1 Set the TM6CLRS flag of the timer 6 mode register TM6MD to 0 At the time the initialization of the timer 6 binary counter TM6BC is enabled 2 Set the TMG6IE flag of the TM6ICR register 0 to disable the interrupt 3 Clock source can be selected by the TM6CKS to 1 flag of the TM6MD register Actually fx is selected 4 Set the interrupt generation cycle to the timer 6 compare register TM6OC At that time TM6BC is initialized to 0x00 5 Set the TM6CLRS flag of the TM6MD register to 1 to enable the interrupt request generation 6 Set the interrupt level by the TM6LV1 to 0 flag of the timer 6 interrupt control register TM6ICR If the interrupt request flag may be already set clear them Chapter 3 3 1 4 Interrupt Flag Setup 7 Set the TM6IE flag of the TM6ICR register 1 to enable the interrupt 8 Set the TM6EN flag of the TM6BEN register to 1 to start the timer 6 As TM60C is set TM6BC is initialized to 0x00 to count
117. 0 0000 9 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 16 bit Timer Pulse Output VI 37 Chapter 6 16 bit Timers TM7BC counts up from 0x0000 If TM7BC reaches the set value of the TM7OCI register and TM7BC is cleared to 0x0000 the signal of the TM71IO output is inverted and TM7BC counts up from 0x0000 again VI 38 16 bit Timer Pulse Output Chapter 6 16 bit Timers 6 6 16 bit Standard PWM Output Only duty can be changed consecutively TMnIO pin outputs the standard PWM output which is determined by the overflow timing of the binary counter and the match timing of the timer binary counter and the compare register 6 6 1 Operation 16 bit Standard PWM Output Timer 7 Timer 8 PWM waveform with an arbitrary duty is generated by setting a duty of PWM H period to the compare register 1 Its cycle is the time of the 16 bit timer full count overflow Table 6 6 1 shows the PWM output pin Table 6 6 1 PWM Output Pin Timer 7 Timer 8 Pulse out TM7IO output P13 output P12 put pin 7 output P51 TM8O output P53 Count Timing of Standard PWM Output at Normal Timer 7 Timer 8 TMnEN flag Compare P M ZEE register 1 Binary 0000 0001 zmomo E FFFF 0000 0001 N 1 counter TMnIO output PWM outpu A 2 A Setup time for compare regis 8 1 PWM basic co
118. 1 Error SC1ORE Overrun error detection 0 No error 1 Error SC1ERE Error monitor flag 0 No error 1 Error Control Registers XII 11 Chapter 12 Serial interface 1 Serial interface I O pin switching control Register SCSEL 0x03F90 7 6 5 4 1 0 TEMPSC 12 TEMPSC 11 TEMPSC2 TEMPSC1 SC1ORE SC1ERE 0 0 0 0 0 0 Description Serial 1 used timer 2 output dividing switching XO0 Timer 2 output 01 Timer 2 output divided by 2 11 Timer 2 output divided by 8 TMPSC12 TMPSC11 Serial 0 used timer 2 output dividing switching XO0 Timer 2 output 01 Timer 2 output divided by 2 11 Timer 2 output divided by 8 02 5 01 Serial 4 pin switching 0 A P10 P11 1 B P76 P77 Serial 1 pin switching 0 A P15 to P17 1 B PA4 to PA6 Serial 0 I O pin switching 0 A PAO to PA2 1 B P75 to P77 XII 12 Control Registers Chapter 12 Serial interface 1 12 3 Operation Serial interface 1 can be used for both clock synchronous and duplex UART 12 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 12 3 1 shows activation factors for communication At master communication the transfer clock is gener ated by setting data to the transmission data buffer TXBUFI or by receiving a start condition Except during communication the input
119. 1 Port 7 Control Register Registers Address Function P7OUT 0x03F17 Port 7output register P7IN 0x03F27 Port 7 input register P7DIR 0x03F37 Port 7 direction control register P7PLUD 0x03F47 Port 7 pull up pull down resistor control register P7OMD OxO3F3C Port 7 output mode register P7ODC 0x03F1D Port 7 Nch open drain control register SELUD 0x03F4B Pull up pull down resistor control register SCSEL 0x03F90 Serial pin switching control register LCCTR1 0x03FC2 LCD output control register 1 LCCTR2 0x03FC3 LCD output control register 2 R W Readable Writable Port 7 output register P7OUT 0x03F 17 lee ds Se Flag P7OUT7 P7OUT6 P7OUT5 P7OUT4 P7OUT3 P7OUT2 P7OUT1 P7OUTO At reset x x x x x x x x m bp Flag Description P7OUT7 P7OUT6 P7OUT5 P7OUT4 P7OUTS P7OUT2 P7OUT1 P7OUTO Output data 0 Output L VSS level 1 Output H VDD level IS G Q O Port 7 IV 51 Chapter 4 Ports Port 7 Input Register P7IN 0x03F27 bp Flag Description 7 P7IN7 6 P7IN6 5 P7IN5 Input data 4 P7IN4 0 Pin is L VSS level 3 P7INS 4 Pin is H VDD level 2 P7IN2 1 0 P7INO Port 7 Direction Control Register P7DIR 0x03F37 52 P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIRO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W
120. 13 3 3 shows the internal clock source which can be set with the SC3MD3 register Table 13 3 3 Synchronous Serial Interface Inside Clock Source Serial 3 Clock source fosc 2 Internal clock fosc 4 fosc 8 fosc 32 fs 2 fs 4 timer 2 output timer 3 output XIII 16 Operation Chapter 13 Serial Interface 3 a Set 0 to the SC3SBIS and SC3SBOS flags of the SC3MD register before change the clock setup munication the system configuration is needed to notify the master of the readout comple a When the slave reception is executed with the start condition enable at the continuous com tion Without the notification the data before readout may be overwritten Data Input Pin Setup There are 2 communication modes to be selected 3 channels clock pin SBT3 pin data output pin SBO3 pin data input pin SBI3 pin 2 channels clock pin SBT3 pin data I O pin SBO3 pin The SBI3 pin can be used only for serial data input The 5 pin can be used for serial data input and output The SC3IOM flag of the SC3MDI register selects either serial data is input from the SBI3 pin or the SBO3 pin When data input from the 5 pin is selected for communication with 2 channels the P3DIR3 flag of the P3DIR register is used to switch the transmission reception of the SBO3 pin The SBI3 pin not used at that time can be used as a general port Maximum transfer
121. 16 fs fs 2 15 4 15 16 7 input TM7IO input 2 TM7IO input 4 input 16 fosc Machine clock High frequency oscillation fs System clock Chapter 2 2 5 Clock Switching At cascade connection timer 8 interrupt factor is only counter clear At cascade connection the binary counter and the compare register are operated as a 32 bit register At operation set the TM7EN flag of the lower 16 bit timers to 1 to be operated Also select the clock source with the lower 16 bit timer Other setup and count timing are the same as the 16 bit timer at independently operation 16 bit Timer Cascade Connection VI 79 Chapter 6 16 bit Timers When timer 7 and timer 8 are used in the cascade connection timer 8 is used as the interrupt request flag Timer pulse output of timer 7 is L fixed output Timer 7 interrupt should be disabled as the interrupt request of timer 7 is generated once that if the loading timing from the preset register to the compare register occurs at the a The preset registers TM7PR1 and TM8PR1 TM7PR2 and TM8PR2 cannot be written at same time as the writing timing of the preset register the correct data may not be loaded VI 80 16 bit Timer Cascade Connection Chapter 6 16 bit Timers 6 12 2 Setup Example Timer Operation Cascade Connection Timer Setup Example Timer 7 Timer 8 Setting example of timer function that the interrupt is
122. 2 lt lt Interrupt 2 generated xxxLV1 0 10 2 RTI Interrupt acceptance IM1 0 10 cycle Cinterrupt service routine 2 RTI IM1 0 11 Not accepted bcause IM IL Interrupt generated xxxLV1 0 11 Y Parentheses indicates hardware processing 1 If during the processing of the first interrupt an interrupt request with an interrupt level IL numerically lower than the interrupt mask IM arrives it is accepted as a nested interrupt If IL gt IM however the interrupt is not accepted 2 The second interrupt postponed because its interrupt level IL was numerically greater than the interrupt mask IM for the first interrupt service routine is accepted when the first interrupt handler returns Figure 3 1 6 Processing Sequence for Maskable Interrupts Ill 12 Overview Chapter 3 Interrupts B Multiplex Interrupt of Maskable Interrupt When this LSI accepts an interrupt it automatically disables acceptance of subsequent interrupts with the same or lower priority level When the hardware accepts an interrupt it copies the interrupt level xxxLVn for the inter rupt to the interrupt mask IM in the PSW As a result subsequent interrupts with the same or lower priority lev els are automatically masked Only interrupts with higher priority levels are accepted The net result is that interrupts are normally processed in decreasing ord
123. 2 3 Data nte pe ete pe EPA XIII 5 Contents 8 13 2 4 Serial interface 3 Mode Register sess rennen entren XIII 6 13 3 Operati n ide ee Ren e RN edades eg XIII 11 13 3 1 Clock Synchronous Serial Interface essere XIII 11 13 3 2 Setup Example cene perite RO HERR ORE XIII 28 13 3 3 Single Master Serial Interface XIII 37 13 3 4 Setup Example idit e Hen ee Her bl e i XIII 46 Chapter 14 Serial XIV 1 14 1 OVerview Oe eO RR etn deett XIV 2 14 1 1 Functions cubes deo ete f XIV 2 14 12 Block Diagrams oett onte ote e eei t p eec i p entend XIV 3 14 1 3 Control XIV 4 14 14 Buffer ADOS I gra reir reuera XIV 5 14 1 5 Mode Register oi necu ree XIV 6 14 2 Oper ti n intet p e e ERU PU pre Rs XIV 9 14 2 1 Setup Example of the Slave Serial Interface sse XIV 11 Chapter 5 A D Convertery osos a S Am mao Suay 1 PS P 2 15 1 1 Functions Eee tee repe eee PRESE XV 2 15 1 2 Block Diagram rie XV 3 15 2 Control Registers URP em eta dte d eicit emet dee te 4 15 21 Registers nni nec RERO D qr Oe ERE REA E ae 4 15
124. 21 011 fosc 2 100 05 210 101 fosc 29 110 fx 24 111 fx 22 Oscillation stabilization wait period selection 00 fs 21 01 15 210 10 15 28 1 11 6 2 1 1 Do not use in high speed operation NORMAL mode Use in low speed operation SLOW mode Reset 33 Chapter 2 CPU Basics Il 34 Control the Oscillation Stabilization Wait Time At recovering from STOP mode the bit 3 2 DLYS1 DLYSO of the oscillation stabilization wait time control register can be set to select the oscillation stabilization wait time from 214 210 26 22 x system clock The DLYCTR register is also used for controlling of buzzer functions At releasing from reset the oscillation stabilization wait time is fixed to 215 system clock System clock is determined by the CPU mode control register CPUM Table 2 6 2 Oscillation Stabilization Wait Time DLYS1 DLYSO Oscillation stabilization wait time 0 0 21 x System clock 0 1 210 x System clock 1 0 26 x System clock 1 1 1 2 x System clock 1 Do not use in high speed operation NORMAL mode Use in low speed operation SLOW mode Reset Chapter 3 Interrupts Chapter 3 Interrupts III 2 31 Overview This LSI speeds up interrupt response with circuitry that automatically loads the branch address to the corre sponding interrupt service routine from an interrupt vector table reset non maskable interrupts NMJ 4
125. 22 Control Registers uoce eee Oe AAA E RELIER e teh XV 5 15 2 3 Data p e Fer al o e Het e einem XV 7 15 3 Operation etre e eet o e dee RU em baec tub eec te tice XV 8 153 1 Setup an eee XV 10 15 3 2 Set p Example t pee eadeni enge eie pere aeree tue ants XV 12 5 3 3 Cautions i RR TR DDR RU e RI XV 14 Chapter 16 EG bem M M XVI 1 16 1 Fun CHONS aise qp Reed ave ices Slee P epis ere XVI 2 ene one ende erac ifie sae er e eines XVI 2 16 1 2 LCD Operation in Standby Mode sese eere XVI 3 16 123 Maximum Pixels en e o tete a tee eet XVI 4 16 1 4 Switching I O ports and LCD segment XVI 4 16 1 5 Switching I O Ports and LCD 1 XVI 4 16 1 6 Block ient c oo eet b e egi ceci XVI 5 16 2 Control Registets rti eee dine et ed eee deos e d cte nee XVI 6 Contents 9 gt 16 21 Registers ioi DR Dir XVI 6 16 2 2 Mode Control Register 1 LCDMDI esee nennen enne XVI 7 16 2 3 Mode Control Register 2 2 2 XVI 8 16 2 4 Output Control Register 1 XVI 9 16 2 5 Output Control Register 2 2 XV
126. 6 5 4 3 2 1 0 At reset TM6CLR TM6IR2 TM6IR1 TM6IRO TM6CK3 TM6CK2 TM6CK1 TM6CKO Access TM6CLRS Description Timer 6 binary counter clear selection flag 0 Enable the initialization of TM6BC as TM6OC is written 1 Disable the initialization of TM6BC as TM6OC is written TM6IRQ is disable as TM6CLRS 0 TM6IRQ is enable as TM6CLRS 1 TM6IR2 TM6IR1 TM6IRO Time base timer interrupt cycle selection 000 Time base selection clock 1 27 001 Time base selection clock x 1 28 010 Time base selection clock x 1 29 011 Time base selection clock x 1 210 10 Time base selection clock X 1 21 11 Time base selection clock X 1 219 TM6CK3 TM6CK2 TM6CK1 Timer 6 clock source selection 000 fosc 001 fs 010 fx 011 Synchronous fx 100 Time base selection clock 1 213 101 Synchronous time base selection clock 1 2 3 110 Time base selection clock X 1 27 111 Synchronous time base selection clock 1 27 TM6CKO Control Registers Time base timer clock source selection 0 fosc 1 fx Chapter 7 Time Base Timer Free running Timer 7 3 8 bit Free running Timer 7 3 1 Operation 8 bit Free running Timer Timer 6 The generation cycle of the timer interrupt should be set in advance by the set value of the compare register and the clock source selection When the binary counter TM6BC reaches the set value of the com pare register an
127. 8 10 to 11 12 to 13 can be set at the same time be operated after all control registers refer toTable 13 2 1 except are set a Each flag should be set as this setup procedure in order Activation of communication should Operation Chapter 13 Serial Interface 3 13 3 3 Single Master Serial Interface B s T Tq 1 Serial interface 3 is capable of IIC serial communication in single master Communication of this IIC interface is based on the IIC BUS data transfer format of Phillips Table 13 3 14 shows the functions of IIC serial interface Table 13 3 14 IIC Serial Interface Functions Communication type Single master IIC Interrupt SC3IRQ Pins SDA3 SCL3 Transfer bit count specification 1 to 8 bit First transfer bit specification ACK bit selection bit level selection Clock source fosc 2 fosc 4 fosc 8 fosc 32 fs 2 fs 4 timer 2 output timer 3 output The transfer rate is the clock source divided by 8 Activation factor for Communication Set data at transmission or dummy data at reception to the transmission reception shift register TXBUF3 Start condition and transfer clock are generated to start communication regardless of transmission reception This serial interface can not be used for slave communication B Start Condition Setup In IIC communication enable start condition by the SC3STE flag of the SC3MDO register at
128. 9 Set the SCORIE flag of the SCORICR register to 1 and SCOTIE flag of the SCOTICR register to 1 to enable the interrupt request If the interrupt request is already set clear it Operation XI 61 Chapter 11 Serial interface 0 Setup Procedure Description 10 Start the serial transmission 10 When the transmission data is set to the serial The transmission TXBUFO 0x03F97 transmission data buffer TXBUFO the transmission is The reception data input to RXDO started When the transmission is finished the serial 0 transmission interrupt SCOTIRQ is generated Also after the received data is stored to the RXBUFO the serial 0 reception interrupt SCORIRQ is generated Note Procedures 6 7 8 can be set at the same time When the TXDO RXDO pin are connected for communication with 1 channel serial data is input output from the TXDO pin Input output can be switched by the port direction control register PADIR At reception set SCOSBIOS of the SCOMD1 register to 1 to select serial data input The RXDO pin can be used as a general port This serial interface contains emergency reset function If communication should be stopped by force set SCOSBOS and SCOSBIS of the SCOMD1 register to 0 Each flag should be set as the setup procedure in order Activation of communication should be operated after all control registers refer to Table 11 2 1 TXBUFO RXBUFO are set
129. AN6 Low speed High speed CPU 4 9 SBT1B SBO1B PAS ANS PA4 AN4 RXD1B SBI1B SDA4A P10 4 85 SCL4A P11 Oscillator Oscillator NBUZZER PTTMZIOICLKOUT 24 idus PASANG SBTOA PA2 AN2 SEG11 P14 TMOIO RMOUT lt p SEG10 P15 TMOOB TXD1A SBO1A t hm ROM RAM RXDOA SBIOA PA1 AN1 SEG9 P16 TM2IO RXD1A SBH A 32 kB 1 5 kB TXDOA SBOOA PAO ANO SEG8 P17 SBT1A TM20B SEGO9 P16 TM2IO RXD1A SBH A XI P90 8 bit Timer 0 Serial Interface 0 8 bit Timer 1 Serial Interface 1 8 bit Timer 2 Serial Interface 3 NRST P27 8 bit Timer 3 Serial Interface 4 SEGO P77 KEY7 SBTOB SCLAB SEG1 P76 KEY6 RXDOB SBIOB SDA4B SEG2 P75 KEY5 TXDOB SBOOB SEG3 P74 KEY4 SEG4 P73 KEY3 SEG5 P72 KEY2 SEG6 P71 KEY1 TM3IO SEG7 P70 KEYO TM1IO 16 bit Timer 7 Time Base Timer 6 16 bit Timer 8 Watchdog Timer External Interrupt LCD COMO P30 COM1 P31 SBI3 COM2 P32 SBT3 SCL3 a mm 33 5803 5 3 lt P34 VLC3 P35 VLC2 P36 VLC1 4 M P37 M 5 gt a P A D Converter D P56 IRQ2 TMOOA LEDO P50 TM7O LED1 P51 2 2 52 TM8O LED3 P53 P54 IRQO ACZO P55 IRQ1 ACZ1 Figure 1 4 1 Block Diagram Differs depending upon the model Refer to 1 1 2 Product Summary 20 Block Diagram Chapter 1 Overview 1 5 Electrical Characteristics This LSI manual describ
130. ANCTR2 to 1 to start the A D conversion 9 When A D conversion is completed the result is stored to the A D buffer ANBUFO 1 and the ANST flag of the A D converter control register2 ANCTR2 is cleared to 0 Then A D conversion complete interrupt is generated The procedures 3 to 4 can be set at the same time Operation Chapter 15 A D Converter After A D conversion is completed when A D conversion is re started with a different setup set the ANLADE of the A D converter control ANCTRO to 0 and confirm the ana log stop before changing the setup Operations of other procedures are not guaranteed Operation XV 18 Chapter 15 A D Converter 15 3 3 Cautions A D conversion can be damaged by noise easily Therefore anti noise measures should be taken adequately Anti noise measures For A D input analog input pin add capacitor near the Vss pins of micro controller XV 14 Operation T Digital Analog Power supply Vss Set near the Vss pin Figure 15 3 2 A D Converter Recommended Example 1 Power supply Set near the Vss pin Figure 15 3 3 A D Converter Recommended Example 2 Chapter 15 A D Converter For high precision of A D conversion the following cautions on A D converter should be kept 1 The input impedance of A D input pin should be
131. Break status transmit control SC1BRKE 0 Data transmission 1 Break transmission Control Registers XII 9 Chapter 12 Serial XII 10 interface 1 Serial interface 1 Mode Register 3 SC1MD3 0x03F9C bp 7 6 3 2 1 0 Flag SC1FDC1 SC1PSC SC1FDCO SC1PSC2 SC1PSC1 SC1PSCO Reset 0 0 0 0 0 Access SC1FDC1 SC1FDCO Description Output selection after SBO1 final data transmission 00 Fix to 1 High output 01 Hold final data 10 Fix to 0 Low output 11 Reserved SC1PSCE Prescaler count control 0 Disable the count 1 Enable the count SC1PSC2 SC1PSC1 SC1PSCO Control Registers Selection clock 000 fosc 2 001 fosc 4 010 fosc 16 011 fosc 64 100 fs 2 101 fs 4 110 Timer 1 output 111 Timer 2 output Serial interface 1 Status Register SC1STR 0x03F9D 7 6 5 4 3 2 1 Chapter 12 Serial interface 1 0 SC1TBS SC1RBSY SC1TEMP SC1REMP SC1FEF SC1PEK SC1ORE SC1ERE SC1TBSY Description Serial bus status 0 Other use 1 Serial transmission in progress SC1RBSY Serial bus status 0 Other use 1 Serial reception in progress SC1TEMP Transmission buffer empty flag 0 Empty 1 Full SC1REMP Reception buffer empty flag 0 Empty 1 Full SC1FEF Framing error detection 0 No error 1 Error SC1PEK Parity error detection 0 No error
132. COMO using an external dividing resistor is shown below Chapter 16 4 1 LCD Display static Clock source fosc 4 MHz LCD clock source fosc 2P 122 Hz and flame cycle 122 Hz are selected in this example Setup Procedure Description 1 Stop the LCD operation 1 Set 0 to the LCDEN flag of the LCD mode control LCDMD1 X SFCO register LCDMD1 to 1 to stop the LCD operation bp7 LCDEN 0 2 Set the display duty 2 Set the LCDTY1 to LCDTYO flags of the LCD mode LCDMD1 X SFCO control register LCDMD1 to 11 to enter the static bp5 4 LCDDTY1 0 11 driving mode 3 Select the LCD clock source 3 Select fosc 2 as a LCD clock source by the LCDCK3 LCDMD1 X 3FC0 to LCDCKO flags of the LCD mode control register bp3 0 LCDCK3 0 0100 LCDMD 4 Select the segment output port pin 4 Select SEGO to SEG3 by the LCD output control register Select the common output port pin 1 LCCTR1 and SEGA to SEG7 by the COMO and the LCCTR1 X 3FC2 LCD output control register 2 LCCTR2 bp7 0 SC1SL3 0 COMSL3 0 11110001 LCCTR2 X 3FC3 bp3 0 SC2SL3 0 1111 5 Set the LCD panel display data 5 Display 23 on the display panel by the address X 2E00 Segment output latch SEG1 0 to X 2E03 of the segment output latch SEGO to SEG7 X 2E00 00 Chapter 16 4 1 Static Segment output latch SEG3 2 X 2E01 X 11 Segment output latch SEG5 4 X 2E02 X 10 Segment output latch SEG7 6 X 2E03
133. COMSL2 COMSL1 COMSLO 0 0 0 0 0 0 0 0 Description SEG3 P74 7 LC1SL3 74 1 SEG3 SEG2 P75 6 LC1SL2 0 P75 1 SEG2 SEG1 P76 5 LC1SL1 0 P74 1 SEG1 SEGO0 P77 4 LC1SLO 0 P77 1 SEG3 COM3 P33 3 COMSLS 0 P33 1 COM3 COM2 P32 2 COMSL2 0 P32 1 COM2 COM1 P31 1 COMSL1 0 P31 1 COM1 0 0 COMSLO 0 30 1 COMO Port 3 IV 31 Chapter 4 Ports 32 LCD Output Control Register 3 LCCTR3 X 3FC4 R W LC3SL2 LC3SL1 LC3SLO 0 0 0 Description LC3SL2 VLC3 P34 0 P34 1 VLC3 LC3SL1 VLC2 P35 0 P35 1 VLC2 Port 3 LC3SLO VLC1 P36 0 P36 1 VLC1 Chapter 4 Ports 4 4 3 Block Diagram Pull up pull down resistor selection f Wek VR V Reget PSPLUDO 0 T gt Pull up pull down resistor control t Q gt Wek VR X p DIR direction control SPIRO a m ne t S P T Port output data ort 2000 WEK R P3IN Schmitt trigger input Port input data q So JA J R LCD output control m Common output control MW Common output data 1
134. Compare Register 1 IGBT Trigger Counter TM71O Output IGBT output A B C D E Figure 6 10 1 Count Timing of Standard IGBT Output At Normal A When IGBT trigger is input IGBT operation becomes valid after 1 count clock After IGBT output is valid it is L until the next count clock B When IGBT trigger is valid it is H during the period when the value of the binary counter reaches that of TM70OC2 from X 0000 H output from X 0001 at the first operation cycle C After the TM7OC2 compare match it 15 L and the binary counter counts up until the counter reaches the compare register to be cleared D When the binary counter is cleared it becomes again E When IGBT trigger becomes invalid the timer is initialized and IGBT output forcibly becomes L 16 bit Standard IGBT Output Only duty can be changed consecutively VI 67 Chapter 6 16 bit Timers Count Timing of Standard IGBT Output When the compare register 1 is X 0000 Timer 7 The following shows the count timing as the compare register is set to X 0000 TM7EN Flag Compare Register 1 0000 IGBT Trigger Counter H TM7IO Output IGBT output EEUU Figure 6 10 2 Count Timing of Standard IGBT Output When the compare register 1 is X 0000 When TM7EN flag is set to 0 stop status IGBT output is Count Timing of Standard IGBT Output When the compar
135. Data is output at the falling edge of the clock 5 Figure 13 3 15 Transmission Reception Timing Reception Falling edge Transmission Rising edge Operation XII 23 Chapter 13 Serial Interface 3 B Communication in STANDBY mode This serial interface is capable of slave reception in STANDBY mode CPU operation status can be recovered from standby to normal by the communication complete interrupt SC3TIRQ that is generated after the slave reception In STANDBY mode continuous reception is disabled after data of transfer bit count set by SC3LNG2 0 flags of the SC3MDO register is received The received data should be read out from the transmission reception shift reg ister SC3TRB after recovering to NORMAL mode In STANDBY mode reception with start condition is not available thus disable start condition And set dummy data to transmission data buffer TXBUF3 before transition to STANDBY mode NORMAL mode STANDBY mode NORMAL mode gt Oscillation stabilization T f f f waittime Clock SBT3 pin Input pin 5813 pin Transfer bit counter SC3BSY 4 Write data to Interrupt SC3IRQ Figure 13 3 16 Reception Timing Rising edge Start condition is disabled XIII 24 Operation B Pins Setup 3 channels transmission Chapter 13 Serial Interface 3 Table 13 3 6 shows the pins setup at synchronous serial interface transmission with 3 channels SBO
136. IRQOICR valid edge of IRQO is only the falling edge port 1 output register P1OUT in advance and clear the information of the edge event hold a When the real time output control function is used writing operation should be done to the function Timing of Real Time Output Control P1CNTO setvalue 0 Low output Timer output External interrupt 0 IRQO i P1TCNT Timer output set value P1n output n22 4 6 Write operation to P1OUT register P1TCNT W 14 Timer output 399 8 get value Figure 4 9 1 Timing of Real Time Output Control Real Time Output Control IV 83 Chapter 4 Ports IV 84 Real Time Output Control Chapter 5 8 bit Timers Chapter 5 8 bit Timers V 2 51 Overview This LSI contains one general purpose 8 bit timers Timer 0 and three 8 bit timers combined baud rate timers Timer 1 Timer 2 Timer 3 Timer 0 and timer 1 or timer 2 and timer 3 can be used as 16 bit timer with cascade connection In a cascade connection timer and timer 2 form the timer 0 or the lower 8 bits of 16 bit counter and timer 1 and timer 3 form the timer 1 or the upper 8 bits 8 bit timer contains two prescalers which can use at the same time Each prescaler counts fosc fs as the base clock Configurations of hard ware are shown below Prescaler 0 fosc base 7 bits Prescaler Prescaler 1 fs base 3 bits P
137. NOS N System Clock fs Synchronous I j I RO SLIL ji PLA Ly Ly count clock Register ps mf 7 00 Counter Interrupt Request Flag Figure 5 5 2 Count Timing of Synchronous TMnIO Input Timer 0 1 2 and 3 counter counts up in synchronization with system clock therefore the correct value is always a When the synchronous TMnIO input is selected as the count clock source the timer n read out V 28 8 bit Event Count 5 5 2 Setup Example Chapter 5 8 bit Timers Event Count Setup Example Timer 0 1 2 and 3 If the falling edge of the TMnIO input pin signal is detected 5 times an interrupt is generated A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 2 Enable the interrupt TMOICR 0x03FE7 bp1 TMOIE 0 3 _Set the special function pin to input P1DIR 0x03F31 P1DIRO 0 4 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 5 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 0 TMOBAS 1 6 set the interrupt generation cycle TMOOC 0x03F52 0x04 7 Select the normal timer operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 0 8 Select the count clock source TMOMD 0x03F54 bp2 0 TMOCK2 0 110 9 Set th
138. OxO3F2A PAIN PAING PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAINO 75 1 1 1 x x x x Port A input data Special Function Registers List XVII 11 Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3F2C P50MD P5LED3 P5LED2 P5LED1 P5LEDO P5OMD P5OMD P5OMD P5OMD IV 44 3 2 1 0 0 0 0 0 0 0 0 0 LEDS LED2 LED1 LEDO port port port port large large large large Timer 8 Timer2A Timer 7 Timer 0A current current current current output output output output output output output output Selection selection selection selection selection selection selection selection OxO3F2D PAODC PA6ODC 2 PAOODC 77 0 0 0 0 PA6 PA5 PA2 drain drain drain drain control control control control OxO3F2E NFCTR 551 NF1SCK NF1SCK NF1EN P54IM NFOSCK NFOSCK NFOEN 48 1 0 1 0 0 0 0 0 0 0 0 0 2 1 IRQ1 noise sampling IRQ1 ACZO IRQO noise sampling IRQO enable frequency noise fil enable frequency noise fil ter ter 0x03F31 P1DIR P1DIR7 P1DIR6 P1DIR5 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIRO 8 0 0 0 0 0 0 0 0 Port 1 direction control OxO3F33 P3DIR P3DIR7 P3DIR6 P3DIR5 P3DIR4 P3DIR3 P3DIR2 P3DIR1 P3DIRO 27 0 0 0 0 0 0 0 0 Port direction
139. P30DC P30DC2 Input mode Output mode Input mode P3DIR P3DIR1 P3DIR P3DIR2 Pull up added not added added not added P3PLU P3PLU2 Operation 25 Chapter 13 Serial Interface 3 XIII 26 Pins Setup 3 channels at reception transmission Table 13 3 8 shows the setup for synchronous serial interface pin with channels SBO3 pin SBI3 pin SBT3 pin at transmission reception Table 13 3 8 Synchronous Serial Interface Pins Setup 3 channels at transmission reception Item Data output pin Data input pin Clock pin SBOS pin 5813 pin SBT3 Clock master Clock slave Port Pin P33 P31 P32 Serial data input SBI3 selection SC3MD1 SC3IOM Function Serial data output Serial data input Serial clock I O Serial clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBTS Type Push pull N ch open Push pull N ch open Push pull N ch open drain drain drain P30DC P30DC2 Input mode Output mode Input mode P3DIR P3DIR3 P3DIR P3DIR1 P3DIR P3DIR2 Pull up added not added added not added added not added P3PLU P3PLU3 P3PLU P3PLU2 Operation B Pins Setup 2 channels transmission Chapter 13 Serial Interface 3 Table 13 3 9 shows the pins setup at synchronous serial interface transmission with 2 channels SBO3pin SBT3 pin The 5813 pin is not use
140. PC 4 2 3 1000 1000 d7 2 if VF NF 1 PC 4 PC BGE label if VF NF 0 PCs5sdiiabe amp HPC 5 2 8 1001 1000 dii H if VF NF 1 PC45 PC BCC label if CFz0 PC 4 d7 label H PO 4 2 3 1000 1100 d7 H 2 if CF 1 PC 4 gt PC BCC label if CF 0 PC 5 d11 labe H gt PC 5 2 3 1001 1100 dii H E if CF 1 5 BCS label if CF 1 PC 4 d7 label H PC 4 2 3 1000 1101 d7 H 12 if CF 0 4 BCS label if CF 1 5 911 5 2 3 1001 1101 lt 11 H 59 if CF 0 5 BLT label if VE NF 1 PC 4sd7 labe sH3PC 4 2 3 1000 1110 lt 07 2 0 4 BLT label if VF NF t PC 5sdt 1 5 2 8 1001 1110 dii H 3 0 5 BLE label if VF NF ZF 1 PC 4sd7 labe H Pd 4 23 1000 1111 lt 97 if VF NF IZF 0 PC 4 PC BLE label I VF NPJZF 1 PC Ssdit abe sHPO 5 2 8 1001 1111 dii H 3 if VF4NF ZF 0 PC 53PC BGT label if VF NF ZF 0 PC 54d7 label H9Pd 5 3 4 0010 0010 0001 lt 97 2 if VF NF IZF 1 PC 5 PC XVII 30 Instruction Set 1 d4sign extension 2 47 sign extension 3 411 sign extension Chapter 17 Appendix MN101C SERIES INSTRU
141. RMOUT pin P14 Timer base cycle Timer base cycle Timer output RMOUT 1 2 duty RMOUT 1 3 duty Figure 8 3 1 Remote Control Carrier Output Signal Duty Ratio Count Timing of Remote Control Carrier Output Functions Timer base cycle Timer output output ON output OFF RMOUT 1 8 duty 1 Figure 8 3 2 Count Timing of Remote Control Carrier Output Functions 1 Even if the RMOEN flag is switched OFF at the carrier output the carrier wave is held by the synchro nous circuit VIII 6 Operations Chapter 8 Remote Control Carrier Functions When RMOEN flag is changed the base cycle and the duty selection timer should not be changed at the same time as the carrier pulse may not be output correctly Set the timer output over 1 cycle of the system clock The remote control carrier output may Y be executed incorrectly when the timer output is set under 1 cycle Operations VIII 7 Chapter 8 Remote Control Carrier Functions 8 3 2 Setup Examples Setup Example of the Remote Control Carrier Output Functions Timer 0 Timer 3 The setup examples that 1 3 duty carrier pulse signal is output as 36 7 kHz for H period from the RMOUT pin with the timer 0 are shown below The clock source of the timer 0 is selected as fs 2 at fs 8 MHz An example setup procedure with a description of each step is shown below Timer 0 base cycle 36 7 kMz gt Timer 0
142. Registers Serial 0 I O pin switching 0 A PAO to PA2 1 B P75 to P77 Chapter 11 Serial interface 0 11 3 Operation Serial interface 0 can be used for both clock synchronous and duplex UART 11 3 1 Clock Synchronous Serial Interface Activation Factor for Communication Table 11 3 1 shows activation factors for communication At master communication the transfer clock is gener ated by setting data to the transmission data buffer TXBUFO or by receiving a start condition Except during communication the input signal from SBTO pin is masked to prevent operating errors by noise This mask can be released automatically by setting a data to TXBUFO access to the TXBUFO register or enabling a start condition to the data input pin Therefore at slave communication set data to TXBUFO or input an external clock after a start condition is input However the external clock should be input after 3 5 transfer clock interval past from the data set to TXBUFO This period is for loading the data from TXBUFO to the internal shift register Table 11 3 1 Synchronous Serial Interface Activation Factor and Cautions Clock Communication type Start condition Activation factor of communication Master Transmission Enabled Set transmission data 1 Disabled Set transmission data 2 Reception Enabled Input start condition 3 Set dummy data 2 Disabled Set dummy data 2 Transmiss
143. Reset input pin 1 1 Oscillation pin 1 pin is used as pin 4 4 Power supply pin 3 3 1 8 Hardware Functions Pin switching Serial interface I O Serial interface 0 Synchronous UART Serial interface 1 Synchronous UART Serial interface 3 Synchronous single master Serial interface 4 slave Timer I O Timer 0 Timer 1 Timer 2 Timer 3 Timer 7 Timer 8 Option 1 SBTOA SBOOA TXDOA STIOA RXDOA SBT1A SBO1A TXD1A STHA RXD1A SBT3 SBT03 SBI3 SDA4A SCL4A D Wire for onboard serial programming Option 1 I O TMOIO TM1IO 2 TM7IO Option 2 SBTOB SBOOB TXDOB STIOB RXDOB UART for onboard serial programming SBT1B SBO1B TXD1B STHB RXD1B 44 pin version available SDA4B SCL4B Option 2 output 1 TMOOA 2 TM7O 8 Chapter 1 Overview Option 3 Option 3 output 2 TMOOB 2 Hardware Functions 9 Chapter 1 Overview 1 3 Pin Description 1 3 1 Pin configuration lt 58 c 22524 gt 225568058 X e N ui Ee Ss ENTE m SEG3 P74 KEY4 lt 37 24 4 gt 20 SEG2 P75 KEY5 TXDOB SBOOB lt 38 23 VDD
144. SC1RIR 0 0 0 0 SC1RLV1 SC1RLV0 Description Interrupt level flag interrupt requests This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to SC1RIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SC1RIR Control Registers Interrupt request flag 0 No interrupt request 1 Interrupt request generated Serial 1 UART Transmission Interrupt Control Register SC1TICR Chapter 3 Interrupts The serial 1 UART transmission interrupt control register SC1TICR controls interrupt level of timer 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 18 bp Serial 0 UART Transmission Interrupt Control Register SCOTICR 0x03FF2 7 6 1 0 Flag SC1TLV1 SC1TLVO SC1TIR At reset 0 0 0 0 Access SC1TLV1 SC1TLVO Description Interrupt level flag interrupt requests This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to SC1TIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SC1TIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers Ill 35 Chapter 3 Interrupts Serial 3 Interrupt Control
145. SLOW and NORMAL This LSI has two CPU operating modes NORMAL and SLOW Transition from SLOW to NORMAL requires passing through IDLE mode A sample program for transition from NORMAL to SLOW mode is given below Program 1 MOV 00 Set SLOW mode MOV DO CPUM Transition from NORMAL to SLOW mode when the low frequency clock has fully stabilized can be done by writing to the CPU mode control register In this case transition through IDLE is not needed For transition from SLOW to NORMAL mode the program must maintain the idle state until high frequency clock oscillation is fully stable In IDLE mode the CPU operates on the low frequency clock as that after reset Software must count that time We recommend selecting the oscillation a For transition from SLOW to NORMAL oscillation stabilization waiting time is required same stabilization time after consulting with oscillator manufacturers Sample program for transition from SLOW to NORMAL mode is given below Program 2 MOV 1 00 Set IDLE mode MOV DO CPUM Program 3 DO A loop to keep approx 6 7ms with low frequency clock 32 kHz 1 DO operation when changed to high frequency clock 10 MHz LOOP 00 DO DO CPUM Set NORMAL mode Standby Function 25 Chapter 2 CPU Basics 26 2 4 4 Transition to STANDBY Modes HR m The program initiates transitions from a CPU operatin
146. Set as the set value of TMnOC2 lt the set value of TMnOC1 If it is set as the set value of TMnOC2 gt the set value of TMnOC1 the PWM output is a H fixed output 16 bit High Precision PWM Output Cycle Duty can be changed consecutively Chapter 6 16 bit Timers 6 7 2 Setup Example eS High Precision PWM Output Setup Example Timer 7 Timer 8 The TM71O output pin outputs the 1 4 duty PWM output waveform at 400 Hz with the timer 7 Select fosc 2 at fosc 10 MHz as the clock source One cycle of the PWM output waveform is decided by the set value of the compare register 1 period of the PWM output waveform is decided by the set value of the compare register 2 An example setup procedure with a description of each step is shown below TM7IO output 152 6 Hz Figure 6 7 4 Output Waveform of TM7IO Output Pin Setup Procedure Description 1 Stop the counter 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD 1 0x03F 78 TM7MD1 to 0 to stop the timer 7 counting bp4 TM7EN 0 2 Set the special function pin to output 2 Set the P1OMDS flag of the porti output mode register P1OMD 0x03F1C P1OMD to 1 the NBUZSEL flag to 1 to set P13 pin bp3 P1OMD3 1 as the special function pin Set the P1DIR3 flag of the bp2 NBUZSEL 1 port 1 direction control register P1DIR to 1 to set the P1DIR 0x03F31 output mode bp3 P1DIR3 1 Chapter 4 Ports 3 Set the
147. Set the SC3CMD flag of the SC3CTR register to 0 to select serial data tansmission 7 Set the SC3MST flag of the SC3MD1 register to 0 to select clock slave external clock Set the SC3SBIS SC3SBTS flags of the SC3MD1 register to 1 to set the 5813 pin to serial data input the SBT3 pin to serial clock I O Set the SC3BOS flag to 0 to set the SBOS pin to the port Set the SC3IOM flag to 0 to set serial data input from the SBIS pin 8 Set the interrupt level by the SC3LV1 0 flag of the serial interrupt control register SC3ICR 9 Set the SC3IE flag of the SC3ICR register to 1 to enable the interrupt If the interrupt request flag SC3IR of the SC3ICR register is already set clear SC3IR before enabling interrupt 10 Set the dummy data to the serial transmission data buffer Wait 3 5 or more transfer clock after the dummy data setting and execute the clock input Then the reception starts After the reception completes the serial 3 interrupt SC3IRQ is generated Chapter 3 3 1 4 Setup Note Procedures 1 to 2 5 6 and 7 can be set at the same time Note Procedures 8 and 9 can be set at the same time At the reception with the start condition input set the SC3STE flag to 1 and the start condition to enable in step 5 In step 10 execute the start condition input instead of dummy data setting After the start condition input 0 5 or more transfer clock is requ
148. Timer 0 and 2 Here is the count timing when the compare register is set to 0 00 TMnEN flag EE SENE T gm zu 3 E register E EC MEO REA L d wA 5 MEE 80200 P vid n counter H TMnIO output PWM output Figure 5 7 2 Count Timing of PWM Output when compare register is 0x00 When TMhnEN flag is stopped 0 PWM output 15 Count Timing of PWM Output when the compare register is OxFF Timer 0 and 2 Here is the count timing when the compare register is set to OxFF Count clock flag 21 Campare ME ME register EE ee MM BEC DEINEN EP 6 9 counter TMnIO output PWM output Figure 5 7 3 Count Timing of PWM Output when compare register is OXFF 36 8 bit PWM Output Chapter 5 8 bit Timers 5 7 2 PWM Output with Additional Pulse B PWM Output with Additional Pulse Method Timer 0 and 2 In the additional pulse method an additional bit is added to the 8 bit basic PWM output The to 3 can be added during 4 cycle of basic PWM output Whether or not and to which the additional bit is added during 4 cycles of basic PWM output can be controlled with the timer 0 mode register TMOMD bit 6 7 and the timer 2 mode register TM2MD bit 6 7 Setting the position of the Additional Pulses The positions of the additional pulse is set in the timer 0 prescaler selection register CKOMD and the timer 2
149. Timers Chapter 7 Time Base Timer Free running Timer Chapter 8 Remote Control Career Chapter 9 Watchdog Timer Chapter 10 Buzzer Chapter 11 Serial Interface 0 Chapter 12 Serial Interface 1 um Pony 321 5 291 m E Chapter 13 Serial Interface 3 Chapter 14 Serial Interface 4 Chapter 15 A D Converter Chapter 16 LCD Chapter 17 Appendix me mM me NIOO BI Oo Contents Contents Chapter yy am t nok a n a aa Sm b a ATS O a m 1 1 1 2 T T I Overview inp eee HT Oeo esq 1 2 1 12 Product Summary uti t c titt t e cae derbi ees 1 2 1 2 Hardware Functions eg po me RR ei REIR RU ett REA I 3 1 3 Pin ten Ret GA OE Aes ER e HUE psc cb d I 10 1 3 1 Pin configuration iier dee I 10 1 3 2 Pin Specification pe RR Ee iere ieee eel I 12 133 En Functions haste Ub dee dide I 14 1 4 Block Dia eta oerte toit eode He ete eed E Hed I 20 14 1 Block Diagram eere eet OR qp ee aves I 20 1 5 Electrical Characteristics mte ee Ero Peer reti op cene lec Rr ette ct I 21 1 5 1 Absolute Maximum Ratings 2 3 1 22 1 5 2 Operating Conditions NORMAL mode fs fosc 2 SLOW mode fs fx 2 I 23 15 3 DC Characteristics aa needed de Hie eb nie cb on rests 1 28 154 A C Conver
150. W R W R W R W R W R W bp Flag Description P5OUT6 5 P5OUT4 P5OUTS P5OUT2 P5OUTO Output data 0 Output L VSS level 1 Output H VDD level O IS Q Port 5 IV 41 Chapter 4 Ports Port 5 Input Register P5IN 0x03F25 bp Flag Description 7 6 P5IN6 5 P5IN5 Input data 4 P5IN4 0 Pin is L VSS level 3 P5IN3 1 Pin is H VDD level s 2 P5IN2 1 P5IN1 0 P5INO Port 5 Direction Control Register P5DIR 0x03F35 IV 42 Flag P5DIR6 P5DIR5 P5DIR4 P5DIR3 P5DIR2 P5DIR1 P5DIRO At reset 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W bp Flag Description O OQ Q O Port 5 P5DIR6 P5DIR5 P5DIR4 P5DIR3 P5DIR2 P5DIR1 P5DIR0 mode selection 0 Input mode 1 Output mode Chapter 4 Ports Port 5 Pull up Resistor Control Register PBPLU OxOSF45 P5PLU6 P5PLU5 P5PLU3 P5PLU2 P5SPLU1 P5PLU0 0 0 0 0 0 0 0 Description 7 g 6 P5PLU6 gt POP ELS Pull up pull down resistor selection 4 P5PLU4 0 Not added 3 P5PLU3 1 Added 2 P5PLU2 1 P5PLU1 0 Port 5 IV 43 Chapter 4 Ports Port 5 Output Mode Register PSOMD 0x03F2C P5LED3 2 P5LED1 P5LEDO P5OMD2 P5OMD1 PSOMDO 0 0 0 0 0 0 0 0 Description
151. X X X X R 7 6 5 4 3 2 1 0 At reset TM7OC1 H7 TM7OC1 H6 TM7OC1 H5 TM7OC1 H4 TM7OC1 H3 TM7OC1 H2 TM7OC1 H1 TM7OC1 HO Access Timer 7 Compare Register 2 Lower 8 bits TM7OC2 Table 6 2 5 Timer 7 Compare Register 2 Lower 8 bits TM7OCS2L 0x03F7A 7 6 5 4 3 2 1 TM7OC2L 7 TM7OC2L 6 TM7OC2L 5 TM7OC2L 4 TM7OC2L 3 TM7OC2L 2 TM7OC2L 1 X X X X X X X R 7 6 5 4 3 2 1 0 TM7OC2 H7 TM7OC2 H6 TM7OC2 H5 TM7OC2 H4 TM7OC2 H3 TM7OC2 H2 TM7OC2 H1 TM7OC2 HO X X X X X X X X R Control Registers VI 9 Chapter 6 16 bit Timers Timer 7 preset register 1 and 2 are buffer registers of the compare registers 1 2 of timer 7 If the set value is writ ten to the timer 7 preset registers 1 2 when the counting is stopped the same set value is loaded to the timer 7 compare register If set value is written to the timer 7 preset registers 1 2 during counting the set value of the timer 7 preset registers 1 2 is loaded to the timer 7 compare registers 1 2 at the timing that the timer 7 binary counter is cleared Also If the set value is written to the timer 7 preset register 1 and 2 during IGBT operation the set value of the timer 7 preset reg
152. X 3FC2 At reset these ports are set to the input port Output Control Register 1 LCCTR1 X SFC2 R W Table 16 2 4 LCD Output Control Register 1 Le cH o e eo Flag LC1SL3 LC1SL2 LC1SL1 LC1SLO COMSL3 COMSL2 COMSL1 COMSLO Reset 0 0 0 0 0 0 0 0 Flag Description SEG3 P74 selection LC1SL3 0 P74 1 SEG3 SEG2 P75 selection LC1SL2 0 P75 1 SEG2 SEG1 P76 selection LC1SL1 SEGO P77 selection LC1SLO 0 P77 1 SEGO selection COMSLS3 0 P33 1 COM3 COM2 P32 selection COMSL2 0 P32 1 COM2 COM1 P31 selection COMSL1 0 P31 1 1 COMO P30 selection COMSLO 0 P30 1 COMO Control Registers XVI 9 Chapter 16 LCD 16 2 5 Output Control Register 2 LCCTR2 The LCD output control register 2 LCCTR2 switches port I O P73 to P70 port I O P14 to P17 and segment output SEGA to SEG11 The address is assigned to X 3FC3 At reset these ports are set to the input port Output Control Register 2 LCCTR2 X 3FC3 R W Table 16 2 5 LCD Output Control Register 2 p E um us coe eel 156 7 Flag LC2SL7 LC2SL6 LC2SL5 LC2SL4 LC2SL3 LC2SL2 LC2SL1 LC2SLO Reset 0 0 0 0 0 0 0 0 m Flag Description SEG11 P14 selection LC2SL7 0 P14 1 SEG11 SEG10 P15 selection LC2SL6 0 P15 1 SEG10 SEG9 P16 selection LC2SL5 0 P16 1 SEG9 SEG8 P17 selection LC2SL4 0 P17 1 SEG8 SEG7 P70 selection LC2SL3 0
153. and after 1 count clock falling edge of the next count clock count clock x value of the dead time preset register 1 1 output voltage of TM7IO is increased C Atter the compare matching the value of the binary counter matches that of TM7OC2 and after 1 count clock output voltage of TM7IO is decreased D After 7 output voltage is decreased and after count clock x value of the dead time preset register 2 1 output voltage of TMSIO is increased E After the compare matching the value of the binary counter matches that of TM7OCI1 and after 1 count clock output voltage of TMSIO is decreased F After 8 output voltage is decreased and after count clock x value of the dead time preset register 1 1 output voltage of TM7IO is increased G When IGBT trigger becomes invalid both TM7IO and TM8IO become L right away Set as TM7OC2 value x TM7OC1 value When TM7OC2 value gt TM7OC1 value the IGBT output waveform is fixed as P13 L P12 L at falling edge standard lowing cases may occur the value set in the preset register during IGBT operation may not be loaded to the compare register the value set in the dead time preset register during IGBT operation may not be reflected a If IGBT trigger is enabled within 2 cycles of count clock after IGBT trigger is disabled the fol occur when IGBT trigger is disabled the value set in the preset register during IGBT operation may not b
154. arbitrate transfer size from 1 to 8 bits can be selected It can be used as parity check overrun error framing error detection or 2 channels serial interface Serial interface 1 I O SBO1 581 SBT1 can be switched to P15 to P17 or 5 to 7 48 pin version only Serial interface 0 I O 5800 5810 SBTO can be switched to P75 to P77 or to 2 44 pin version 48 version Serial interface 3 1 channel Single master Synchronous serial interface Single master handling communication enable with ACK 9 bits are transferred Transfer clock focs 2 focs 4 focs 16 focs 32 focs 64 fs 2 fs 4 timer 2 timer 3 output MSB LSB can be selected as the first bit to be transferred An arbitrate transfer size from 1 to 8 bits can be selected Serial interface 4 1 channel slave interface high speed transfer mode communication speed 400 kbps 7 bit or 10 bit of slave address can be set General call communication mode handling SCL pin SDA pin can be switched to P10 P11 or P76 P77 1 6 Hardware Functions Chapter 1 Overview LED driver 4 pins LCD driver pins Segment output 12 pins max SEGO to SEG11 SEGO to SEG11 are switchable to ports in unit of 1 pin Note At reset SEGO to SEG11 are input pors Common output pins 4 pins COMO to are switchable to I O port in 1 pin unit Display mode selection Static 1 2 duty 1 2 bias 1 8 duty 1 3 bias 1 4 duty 1 4 bias L
155. bit Timer Pulse Output reete Der Ino ROO e uere freies VI 35 6 5 T Operation ene amu saepe e EE OE I eu VI 35 6 5 2 Setup Example oe oe Eoo ei o UP eatis VI 37 6 6 16 bit Standard PWM Output Only duty can be changed VI 39 6 6 1 Operation ect W ee o ep eee Ee ee e VI 39 6 6 2 Setup Example iion oa eoe VI 42 6 7 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VI 44 6 71 Operation ocio te eee ER e P EE eee VI 44 6 7 2 Setup Example rea ete need Sinan arin VI 47 6 8 16 bit Timer oe ee deh te RERUM ER tebe ie EE VI 49 6 8 Operation 1 49 6 82 Setup Example eue A ME ERs 1 55 6 9 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively VI 57 6 9 1 io eei prr emet lees e ut tae te tle etes VI 57 6 9 2 Setup cerei eS Cen rre ete re oU ee epe VI 62 6 10 16 bit Standard IGBT Output Only duty can be changed consecutively 1 65 6 10 1 Operation itte cete ee Meee VI 65 6 10 2 Setup Example irem eie pee DPI pU DEO Her epi VI 70 6 11 Dead Time IGBT Output iore teet e aspa OPEP enit Pete VI 72 6 TIL Operation nest ee eee VI 72 6 1
156. by setting the flag LC2SL6 flag of the LCD output control register 2 LCCTR2 to 1 Port and segment switching can be selected by each bit At segment output it is forcefully set to input mode and pull up resistor is disabled P16 is used as LCD segment output pin as well The 5209 pin selection can be done by setting the bp5 flag LC2SL5 flag of the LCD output control register 2 LCCTR2 to 1 Port and segment switching can be selected by each bit At segment output it is forcefully set to input mode and pull up resistor is disabled P17 is used as LCD segment output pin as well The SEGS pin selection can be done by setting the bp4 flag LC2SLA flag of the LCD output control register 2 LCCTR2 to 1 Port and segment switching can selected by each bit At segment output it is forcefully set to input mode and pull up resistor is disabled Port 1 Chapter 4 Ports 4 2 2 Registers O 1 Table 4 2 1 shows registers that control the port 1 Table 4 2 1 Port 1 Control Register Registers Address Function P1OUT Ox03F 11 Port 1 output register 0x03F21 R Port 1 input register 8 P1DIR 0x03F31 R W Port 1 direction control register IV 8 0x03F41 R W Port 1 pull up pull down resistor control register IV 9 1 OxO3F1C R W Port 1 output mode register IV 10 P1ODC 0x03F1B R W Port 1 Nch open drain control register IV 11 SELUD 0x03F4B R W
157. career output synchronized with the external event without the interposition Switchable output values at the event generation are 0 1 Hi impedance Hi z 4 9 1 Registers lt Table 4 9 1 shows the real time output control registers of port 1 Table 4 9 1 Real Time Output Control Registers Register Address R Function Page w Port 1 P1OUT 0x03F11 R Port 1 output register IV 7 w P1DIR 0x03F31 R Port 1 direction control register IV 8 w P1PLUD 0x03F41 R Port 1 pull up pull down resistor control IV 9 1 0x03F39 R Pull up pull down resistor 9 W selection register P1CNTO 0x03F3D R Port 1 real time output control register IV 11 W 4 9 2 Operation _____________ _ _ __________________________________________ Real Time Output Pin Setup The real time output pin setup should be done at the port 1 output control register PICNTO Selectable pins are P12 P14 P16 and each of them can be specified by each bit The output mode should be selected at the port 1 direction control register PIDIR The pin output that is switched at the falling edge event of the external interrupt 0 pin P54 IRQO is 0 1 Hi impedance Port is input mode at the hi impedance The real time control is the function that changes the timer output signal PWM output timer pulse output remote control career output synchronized with the external eve
158. clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 10 bp3 2 TM7PS1 0 00 9 Set the interrupt level TM7ICR 0x03FED bp7 6 TM7LV1 0 10 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Set the TM7IE flag of the TM7ICR register 0 to disable the interrupt 3 Set the P1DIR3 flag of the port 1 direction control register P1DIR to 0 to set P13 pin to the input mode Add pull up pull down resistor if necessary Chapter 4 ports 4 Select fs to the clock source by the TM7CK1 to 0 flag of the TM7MD1 register Besides select 1 1 to the count clock source by the TM7PS1 to 0 flag 5 Set IGBT timer startup factor to timer 7 count operation 6 Set the interrupt generation cycle to the timer 7 preset register 1 TM7PR1 The set value should be 4 because the counting is 5 times At that time the same value is loaded to the timer 7 compare register 1 7 1 and the timer 7 binary counter TM7BC is initialized to 0x0000 7 Set the TM7BCR flag of the timer 7 mode register 2 TM7MD2 to 1 to select the compare match as a binary counter clear source 8 Select TM7IO to the clock source by the TM7CK1 to 0 flag of the TM7MD1 register Besides select 1 1 no dividing to the count clock source by the TM7PS1 to 0 flag 9 Set the interrupt level by the TM7LV1 to 0 flag of the timer 7 interrupt control register TM7ICR If the interrupt requ
159. constantly generated by cascade connection of timer 7 and timer 8 as 32 bit timer is shown An interrupt is generated in every 100000 cycles 40 ms by selecting source clock to fs 2 fosc 10 MHz fs fosc 2 An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD 1 x 3F78 bp4 TM7EN 0 TM8MD 1 88 bp7 TM8EN 0 2 Select the timer clear source TM7MD2 x 3F88 bp5 TM7BCR 1 3 Select the normal lower operation TM7MD2 x 3F79 bp2 T7ICEN 0 4 Set the cascade connection TM8MD3 x 3F8 bp0 TM8CAS 1 5 Select the count clock source TM7MD1 x 3F78 bp1 0 TM7CK1 0 01 bp3 2 TM7PS1 0 01 6 Set the interrupt generation cycle TM7PR1 x 3F75 x 3F74 2x 869F TM8PR1 x 3F85 x 3F84 x 0001 7 Disable the lower timer interrupt TM7ICR x 3FED bp1 TM7IE 0 8 Set the upper timer interrupt level TMBICR x 3FF6 bp7 6 TM8LV1 0 10 1 Set the TM7EN flag of the timer 7 mode register TM7MD1 to 0 and the TM8EN flag of the timer 8 mode register TM8MD1 to 0 to stop the timer 7 and the timer 8 counting 2 Set the TM7BCR flag of the TM7MD2 register to 1 to select the compare match as the binary counter clear source 3 Set the T7ICEN flag of the TM7MD2 register to 0 to select the normal timer operation 4 Set the TM8CAS flag of the TM8MD3 register to 1 to c
160. control EDGDT 0x03F2E register EDGDT to 1 to select the both edges bp2 EDGSEL2 1 interrupt 2 Set the interrupt level 2 Set the interrupt level by the IRQ2LV1 to 0 flag of the IRQ2ICR 0x03FE3 IRQ2ICR register The interrupt request flag of the bp7 6 IRQ2LV1 0 10 IRQ2ICR register may be set so make sure to clear the interrupt request flag IRQ2IR Chapter 3 3 1 4 Interrupt flag setup 3 Enable the interrupt 3 Set the IRQ2IE flag of the IRQ2ICR register to 1 to IRQ2ICR 0x03FE3 enable the interrupt bp1 IRQ2IE 21 At the both edges of the input signal from P56 pin an external interrupt 2 is generated External Interrupts 53 Chapter 3 Interrupts When the both edges interrupt is selected the interrupt request is generated at the both edge regardless of the REDGn flag of the external interrupt control register IRQnICR request flag before the interrupt acceptance Also select the both edges interrupt before the a The interrupt request flag may be set at switching the interrupt edge So clear the interrupt interrupt acceptance The external interrupt pis is recommended to be pull up in advance 54 External Interrupts Chapter 3 Interrupts 3 3 6 Key Input Interrupt Key Input Interrupt External interrupt 4 This LSI can set port 7 P70 to P77 pin by 1 bit to key input pin An interrupt can be generated at the falling edge if at least 1 key inpu
161. control OxO3F35 P5DIR P5DIR6 P5DIR5 P5DIR4 P5DIR3 P5DIR2 P5DIR1 P5DIRO 42 0 0 0 0 0 0 0 Port 5 I O direction control OxO3F37 P7DIR P7DIR7 P7DIR6 P7DIR5 P7DIR4 P7DIR3 P7DIR2 P7DIR1 P7DIRO 52 0 0 0 0 0 0 0 0 Port 7 direction control OxO3F39 P9DIR P9DIRO 68 Port 9 I O direction control OxO3F3A PADIR PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIRO 75 0 0 0 0 0 0 0 Port A I O direction control XVII 12 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3F3B P32ODC 30 0 0 m P33 P32 open open drain drain control control P7OMD P7OMD P7OMD 53 1 0 0 0 port port Timer 3 Timer 1 output output selection selection OxO3F3D P1CNTO P1CNTO P1CNTO P1CNTO P1CNTO P1CNTO P1CNTO IV 12 5 4 3 2 1 0 0 0 0 0 0 0 P16 real time control P14 real time control P12 real time control KEYT3_1IMD KEYT3S KEYT3_ _ _ KEYT3_ 50 EL 1EN3 1 2 1ENO 0 0 0 0 0 Key inter KEY3 KEY2 KEY1 KEYO rupt con key inter keyinter key inter key inter trol rupt rupt rupt rupt selection selection selection selection OxO3F3F KEYT3_2
162. control register LCCTR1 Vici 45 42 P36 LCD power pins Supply for LCD power Apply voltage 3 6 V 2 Vice 46 43 P35 Vici 2 Vice 2 Vica 20V Vie 47 44 P34 When the booster voltage circuit is used Vice pins are selected as the reference input pins When the internal voltage divider circuit is used Vi c4 is selected as the reference input pin When the LCD functions are unused can be used as a normal port by setting the LCD mode control register 3 LCDMD3 SEGO 40 37 Output P77 SBTOB SCL4B KEY7 LCD segment These pins output the segment signal with SEG1 39 36 P76 SBIOB RXDOB 5 4 output pins the required timing for the LCD display KEY6 Connect to the segment pins of the LCD SEG2 38 35 panel SEG3 37 34 P75 SBOOB TXDOB KEYS When the LCD display is turned off Vgg level SEG4 36 33 P74 KEY4 is output SEGS 35 32 P73 KEY3 It can be used as a normal port by setting of SEG6 34 31 P72 KEY2 the LCD output control register LCCTR1 SEG7 33 30 P71 TM3IO KEY1 LCCTR2 LCCTR3 LCCTR4 SEG8 32 29 P70 TM1IO KEY0 Segment pin and normal port are switchable SEG9 31 28 P17 TM2OB SBI1A by each bit from SEGO to SEG11 SEG10 30 27 P16 TM2IO SBI1A RXD1A SEG11 29 26 P15 TMOOB SBO1A 1 Not available for 44 pin QFP package P14 TMOIO RMOUT Pin Description 1 19 Chapter 1 Overview 1 4 Block Diagram 1 4 1 Block Diagram 90 OSC1 OSC2 55 SBT1B PA6
163. description of each step is shown below Setup Procedure Description 1 Select the prescaler operation SC1MD3 0x03F9C bp3 SC1PSCE 1 2 Select the clock source SC1MD3 0x03F9C bp2 0 SC1PSC2 0 100 3 SBO1A output control after the last data output SC1MD3 0x03F9C bp7 6 SC1FDC1 0 00 1 Set the SC1PSCE flag of the SC1MD3 register to 1 to select prescaler operation 2 Set the SC1PSC2 to 0 flag of the SC1MD3 register to 100 to select the fs 2 to clock source 3 Set the SC1FDC1 to 0 flag of the SC1MD3 register to 00 to select 1 High fix of the SBO1 last data output Operation XII 38 Chapter 12 Serial interface 1 Setup Procedure Description 4 Select the used pin SCSEL 0x03F90 SC1SL 0 5 Control the pin style P10DC 0x03F 1B bp7 P10DC7 1 bp5 P10DC5 1 P1PLUD 0x03F41 bp7 P1PLUD7 1 bp5 P1PLUD5 1 6 Control the pin direction P1DIR 0x03F31 bp7 P1DIR7 1 bp6 P1DIR6 0 bp5 P1DIR5 1 7 Set the SC1MDO register Select the transfer bit count SC1MDO 0x03F99 2 0 SC1LNG2 0 111 Select the start condition SC1MDO 0x03F99 bp3 SC1STE 0 Select the first bit to be transferred SC1MDO 0x03F99 bp4 SC1DIR 0 Select the transfer edge SC1MDO 0x03F99 bp7 SC1CE1 1 8 Set the SC1MD1 register Select the communication style SC1MD1 0x03F9A SC1CMD 0 Select the transfer clock SC1MD1 0x03F9A bp2 SC1MST 1 bp3 SC1C
164. description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 TM1MD 0x03F55 bp3 TM1EN 0 2 Select the normal lower timer operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 0 3 Set the cascade connection TM1MD 0x03F55 bp4 TM1CAS 1 4 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 5 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 X0 TMOBAS 1 6 Set the interrupt generation cycle TMnOC 0x03F52 0x03F53 0x09C3 7 Disable the lower timer interrupt TMOICR 0x03FE7 bp1 TMOIE 0 8 Set the level of the upper timer interrupt TM1ICR 0x03FE8 bp7 6 TM1LV1 0 10 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 the TM1EN flag of the timer 1 mode register 10 0 to stop the timer 0 and the timer 1 counting 2 Set the TMOPWM flag and the TMOMOD flag of the TMOMD register to 0 to select the normal timer 0 operation 3 Set the TM1CAS flag of the TM1MD register to 0 to connect the timer 1 and the timer 0 to the cascade 4 Select the prescaler to the clock source by the 2 to 0 flag of the TMOMD register 5 Select fs 2 to the prescaler output by the TMOPSC1 to 0 flag and the TMOBAS flag of the timer 0 prescaler selection register CKOMD 6 Set the timer 1 compare register timer 0 compare register TM1OC TMOOO to the interrupt
165. detection nation flag OxO3FCO LCDMD1 LCDEN Reserve LCDTY1 LCDTYO LCDCK3 LCDCK2 LCDCK1 LCDCKO XVI 7 d 0 0 0 0 0 0 0 0 LCDstart Set LCD display duty Source clock always selection to 0 OxO3FC1 LCDMD2 Reserve Reserve LCRHL LCREN Reserve Reserve XVI 8 d d d d 0 0 0 0 0 0 Set always to 0 Internal Dividing Set always to 00 voltage voltage dividing resistor resistor connec value tion selection selection OxO3FC2 LCCTR1 LC1SL3 LC1SL2 LC1SL1 LC1SLO COMSL COMSL COMSL COMSL XVI 9 3 2 1 0 0 0 0 0 0 0 0 0 P74 P75 P76 77 P33 P32 P31 P30 SEG3 SEG2 SEG1 SEGO COM3 COM2 1 COMO selection selection selection selection selection selection selection selection OxO3FC3 LCCTR2 LC2SL7 LC2SL6 LC2SL5 02514 02513 02512 02511 02510 XVI 10 0 0 0 0 0 0 0 0 P14 P15 P16 P17 P70 P71 P72 P73 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 selection selection selection selection selection selection selection selection 0x03FC4 LCCTR3 LC3SL2 LC3SL1 LC3SLO XVI 11 0 0 0 P34 P35 P36 VLC2 VLC1 selection selection selection ANCTRO ANSH1 ANSHO ANCK1 ANCKO ANLADE XV 5 B 0 0 0 0 0 Sample and hold time A D conversion clock A D lad der resis tance control Special Function Registers List XVII 23 Chapter 17 Appendix Bit Symbol Address Register Page Bit
166. down resistor control D ae Reset P3DIR Rd 3DIR3 direction control snq E Ly Y yY Y gt P30UT3 Port output data D gt V Yo gt yw Schmitt trigger input Port input data lt Fo T J R X Serial 3 IIC3 reception data input Serial 3 IIC3 reception data output SC3MD1 SC3SBOS COMSL3 LCD output control VER D 9 Common output control NM Common output data LCD clock 1 E Vica 9 i Ly o 3 1 ep 5 Vica 5 Y Figure 4 4 4 Block Diagram P33 At common output port I O direction control is forcefully set to input mode pull up resistor is disabled and common output is executed by the common output control IV 36 Port 3 Chapter 4 Ports Reset P3DWN Pull up pull down resistor selection D 4 Wek R V Reset Pull up pull down resistor control P3PLUD4 al Wek R Reget direction control
167. down up down up down up down up down Ox03F4C XSEL XSEL IV 70 P91 XI selection Ox03F4E PAIMD PAIMD7 PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMDO 76 0 0 0 0 0 0 0 Analog input pin selection OxO3F50 TMOBC TMOBC7 TMOBC6 TMOBC5 TMOBC4 TMOBC3 TMOBC2 TMOBC1 TMOBCO V 13 0 0 0 0 0 0 0 0 Timer 0 binary counter 0x03F51 TM1BC TM1BC7 TM1BC6 TM1BC5 TM1BC4 TM1BC3 TM1BC2 TM1BCO V 13 0 0 0 0 0 0 0 0 Timer 1 binary counter 0 03 52 TMOOC TMOOC7 TMOOC6 TMOOC5 TMOOC4 TMOOC3 TMOOC2 TMOOC1 TMOOCO V 12 x x x x x x x x Timer 0 compare register 0x03F64 TM6BEN TBEN TM6EN VII 7 0 0 Time TM6 base opera timer tion con opera trol tion con trol XVII 14 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ox03F6C RMCTR Reserve TMORM RMOEN RMDTY RMDTY RMBTM VIII 5 d 1 0 S 0 0 0 0 0 0 Set P14spe Remote Remote control Remote always cial func control career duty selection control to 0 tion career career output output base selection enable timer selection OxO3F6D PSCMD PSCEN 47 i 2 Prescale r count control OxO3F6E TM7MD4 T7ONES T7NODE T7IC
168. external interrupts and 17 internal interrupts peripheral function interrupts For interrupts other than reset the interrupts processing sequence consists of interrupt request interrupt accep tance and hardware processing After the interrupt is accepted the program counter PC and processor status word PSW and handy addressing data are saved onto the stack And an interrupts handler ends by restor ing using the POP instruction and other means the contents of any registers used during processing and then exe cuting the return from interrupt RTI instruction to return to the point at which execution was interrupted Max 12 machine cycles before execution and max 11 machine cycles after execution Each interrupt has a interrupt control register which controls the interrupts Interrupt control register consists of the interrupt level field LV1 to 0 interrupt enable flag IE and interrupt request flag IR Interrupt request flag IR is set to 1 by an interrupt request and cleared to 0 by the interrupt acceptance This flag is managed by hardware but can be rewritten by software Interrupt enable flag IE is the flag that enables interrupts in the group There is no interrupt enable flag in non maskable interrupt NMI Once this interrupt request flag is set it is accepted without any conditions Interrupts enable flag is set in maskable interrupt Interrupt enable flag of maskable interrupt is valid when th
169. from the internal shift register When data is stored to RXBUFI from the shift register the reception buffer empty flag SCIREMP of the SCISTR register is setto 1 That indicates that the received data is going to be read out SCIREMP is cleared to 0 by reading out the data of RXBUFI Reception BUSY Flag When the start condition is recognized the SCIRBSY flag of the SCISTR register is set to 1 When the recep tion complete interrupt SC1TIRQ is generated the flag is cleared to 0 If the SCISBIS flag is set to 0 during reception the SCIRBSY flag is reset to 0 B Transmission BUSY Flag When data is set to TXBUFI the SCITBSY flag of the SCISTR register is set to 1 When the transmission complete interrupt SCITIRQ is generated the flag is cleared to 0 During continuous communication the SCITBSY flag is always set If the transmission buffer empty flag SCITEMP is set to 0 as the transmission complete interrupt SC1TIRQ is generated the 5 is cleared to 0 If the SCISBOS flag is set to 0 the SCITBSY flag is reset to 0 Operation XII 48 Chapter 12 Serial interface 1 B Frame Mode and Check Setup Figure 11 3 17 shows the data format at UART communication Frame Character bit Figure 12 3 17 UART Serial Interface Transmission Reception Data Format The transmission reception data consists of start bit character bit parity bit and stop bit Table 1
170. fx BUZS2 BUZS1 BUZSO Buzzer output frequency 10 MHz 0 0 0 2 44 kHz 10 MHz 0 0 1 4 88 kHz 10 MHz 0 1 0 9 76 kHz 8 39 MHz 0 1 0 2 05 kHz 8 39 MHz 0 1 1 4 1 kHz 2 MHz 1 0 0 1 95 kHz 2 MHz 1 0 1 3 91 kHz 32 kHz 1 1 0 2 kHz 32 kHz 1 1 1 4 kHz Operation Chapter 10 Buzzer 10 3 2 Setup Example Setup Example Buzzer outputs the square wave of 2 kHz from P12 pin It is used 8 39 MHz as the high oscillation clock fosc An example of setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the buzzer frequency 1 Set BUZS2 to BUZSO flag of the oscillation stabilization DLYCTR 0x03F03 wait control register DLYCTR to 010 to select fosc bp6 4 BUZS2 0 010 212 to the buzzer frequency When the high oscillation clock fosc is 8 39 MHz the buzzer output frequency is 2 05 kHz 2 Set P12 pin 2 Set BUZSEL flag of port 1 output mode register P1OMD 0x03F1C P1OMD to 1 to set P12 to special function pin Set BUZSEL 1 P1DIR2 flag of port 1 direction control register P1 DIR P1DIR 0x03F31 to 1 to set output mode then low level is output from bp2 P1DIR2 1 P12 3 Buzzer output ON 3 Set the BUZSE flag of the oscillation stabilization wait DLYCTR 0x03F03 control register DLYCTR to 1 to output the square bp7 BUZOE 1 wave of the buzzer output frequency set by P12 pin 4 Buzzer output OFF 4 Set the BUZOE fla
171. in out P1DIR6 P1PLU6 TM2IO Timer 2 I O SBI1A Serial interface 1 reception data input RXD1A SEG9 in out RXD1A UART1 reception data input SEG9 Segment output P17 TM2OB SBTIA in out P1DIR7 P1PLU7 2 Timer 2 output SBT1A Serial interface 1 clock I O SEG8 8 Segment output P27 NRST in NRST Reset COMO in out P3DIRO PSPLUO COMO LCD common output P31 SBIS in out PSDIR1 P38PLU1 COM 1 LCD common output SBI3 Serial interface 3 reception data input P32 SBT3 SCL3 in out P3DIR2 P3PLU2 COM2 LCD common output SBT3 Serial interface 3 clock I O COM2 SCL3 IIC3 clock output P33 SBO3 SDA3 in out P3DIR3 PSPLUS COM3 LCD common output 5803 Serial interface 3 transmission data output COMS SDAG Serial data I O P34 VLC3 in out VLC3 LCD power P35 VLC2 in out VLC2 LCD power P36 VLC1 in out VLC1 LCD power P37 1 in out P3DIR7 P3PLU7 P50 TMOOA LEDO in out P5DIRO P5PLUO TMOOA Timer 0 output LEDO LED driver pin 0 P51 TM70 LED1 in out P5DIR1 PS5PLU1 TM70 Timer 7 output LED1 LED driver pin 1 P52 TM2OA LED2t in out P5DIR2 P5PLU2 TM20OXA Timer 2 output LED2 LED driver pin 2 P53 TM8O LED3 in out P5DIRS P5PLU3 TM8O Timer 8 output LED3 LED driver pin 3 P54 IRQO ACZO in out P5DIR4 P5PLU4 IRQO External interrupt 0 ACZO Zero cross input 0 P55 IRQ1 ACZ1 in out P5DIR5 P5PLUS IRQ1 External interrupt 1 ACZA Zero cross input 1 P56 IRQ2 in out P5DIR6 P5PLU6 IRQ2 External interrupt 2 P70 TM1IO
172. input edge O rising 1 falling SCOCE1 First bit to be transferred SCODIR 0 MSB first 1 LSB first Start condition selection SCOSTE 0 Disabled 1 Enabled Transfer bit 000 1bit 001 2bit SCOLNG2 010 3bit SCOLNG1 011 4bit SCOLNGO 100 5bit 101 6bit 110 7bit 111 8bit Control Registers Xl 7 Chapter 11 Serial interface 0 Serial interface 0 Mode Register 1 SCOMD1 0x03F92 bp 7 6 5 4 3 2 1 0 Flag SCOIOM SCOSBO SCOSBTS SCOSBIS SCOCKM SCOMST SCODIV SCOCMD Reset 0 0 0 0 0 0 0 Access SCOIOM Description Serial data input selection 0 Data input from SBIO RXDO 1 Data input from SBOO TXDO SCOSBTS SBTO pin function selection 0 Port 1 Transfer clock I O SCOSBIS Serial input control selection O Input 1 1 Input serial SCOSBOS SBOO TXDO pin function 0 Port 1 Output serial data SCOCKM Transfer clock dividing selection 0 Not divided 1 Divided SCOMST Clock master slave selection 0 Clock slave 1 Clock master SCODIV Transfer clock dividing selection 0 Devided by 8 1 Devided by 16 8 SCOCMD Control Registers Synchronous serial duplex UART selection 0 Synchronous serial 1 Duplex UART Chapter 11 Serial interface 0 Serial interface 0 Mode Register 2 SCOMD2 0x03F93 bp 7 6 5 4 3 1 0 Flag SCOFM1 SCOFMO SCOPM1 SCOPMO SCONPE SCOBRKF SCOBR
173. interrupt group There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority For example if a vector 3 set to level 1 and a vector 4 set to level 2 request interrupt simultaneously vector 3 will be accepted Vector 1 Non maskable Priority Interrupt vector No 1 Vector 1 Level 0 Vector 2 5 6 2 Vector 2 3 Vector 5 5 Level 1 Vector 3 4 Vector 6 5 Veclor 3 5 Level 2 Vector 4 8 6 Vector 4 7 Vector 8 Figure 3 1 3 Example of Interrupt Level Overview III 7 Chapter 3 Interrupts Determination of Interrupt Acceptance The following is the procedure from interrupt request input to acceptance 1 The interrupt request flag xxxR in the corresponding external interrupt control register IRQnICR and inter nal interrupt control register xxxICR are set to 1 2 An interrupt request is input to the CPU If the interrupt enable flag xxxIE of the same register is 1 3 The interrupt request signal is set for each interrupt The interrupt level IL is input to the CPU 4 The interrupt request is accepted If IL has higher priority than IM and MIE is 1 5 Acceptance of an interrupt does not reset the corresponding interrupt enable flag xxxIE to 0 Current interrupt mask level IM ZF PSW NF CF
174. interrupt request is generated at the next count clock and the binary counter is cleared to restart count up from 0x00 Table 7 3 1 shows selectable clock source Table 7 3 1 Clock Source at Timer Operation Timer 6 Clock source One count time At fosc 10 MHz At fosc 8 39 MHz At fosc 2 MHz fosc 100 ns 119 1 ns 500 ns fx 30 5 us fs 200 ns 238 3 ns 1000 ns fosc x 1 27 12 8 us 15 2 us 64 us fosc x 1 213 819 2 us 976 4 us 4096 us fx x 1 27 3 9 ms bx 1 213 250 ms fx 2 32 768 KHz fs fosc 2 fosc 20 MHz 8 39 MHz 2 MHz 8 bit Free running Timer VII 9 Chapter 7 Time Base Timer Free running Timer 8 bit Free running Timer as a 1 Minute timer a 1 Second timer Table 7 3 2 shows the clock source selection and the TM6OC register setup when a 8 bit free running timer is used as a 1 minute timer a 1 second timer Table 7 3 2 1 Minute timer 1 Second timer Timer 6 Setup ded Generation Clock source TM6OC Register 1 min fx x 1 213 OxEF 15 fx x 1 213 0x03 fx 32 768 kHz When the 1 minute timer 1 m is set on Table 7 3 2 the bp2 waveform frequency cycle of the TM6BC register is 1 Hz 1 s So that can be used for adjusting the seconds TM6BC 1Hz 1s Figure 7 3 1 Waveform of TM6BC Register bp2 Timer 6 a For proper count count clock should be switched after the timer stops its operation VII 10 8 bit Free running Time
175. interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 39 Chapter 3 Interrupts Timer 8 Compare Register 2 match Interrupt Control Register T8OC2ICR The timer 8 compare register 2 match interrupt control register T8OC2ICR controls interrupt level of timer 8 compare register 2 match interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 23 Timer 8 Compare Register 2 match Interrupt Control Register T8OC2ICR 0x03FF7 bp 7 6 5 4 3 2 1 0 Flag T8OC2LV T8OC2LV T8OC2IE 8 2 1 0 At reset 0 0 0 0 Access R W Description T80C2LV1 Interrupt level flag T8OC2LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to to interrupt requests T8OC2IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt T8OC2IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated 40 Control Registers Chapter 3 Interrupts 3 3 External Interrupts There are 4 external interrupts in this LSI The circuit external interrupt interface operates the external interrupt input signal is built in between the external interrupt input
176. is cleared to 0 as the commu nication complete interrupt SCITIRQ is generated SCIRBSY is cleared to 0 If the SCISBIS flag is set to 0 during communication the SCIRBSY flag is cleared to 0 Operation XII 19 Chapter 12 Serial interface 1 XII 20 B Transmission BUSY Flag When the SCISBOS flag of the SCOMDI register is set to serial data output and the data is set to TXBUFI or the start condition is recognized the SCITBUSY flag of the SCISTR register is set if the SCISBOS flag of the SCIMDI register is 1 The flag is cleared to 0 after the communication complete interrupt SC1TIRQ is gen erated During continuous communication the SCITBSY flag is always set If the transmission buffer empty flag SCITEMP is cleared to 0 as the communication complete interrupt SC1TIRQ is generated SCITBSY is cleared to 0 If the SCISBOS flag is set to 0 during communication the SCITBSY flag is cleared to 0 B Forced Reset This serial interface contains forced reset for abnormal operation For forced reset the SCISBOS flag and the SCISBIOS flag of the SCIMDI register should be set to 0 SBOI pin port input data 1 input At forced reset the status register the SCIBRKF flag of the SCIMD2 register all flags of the SCISTR register are initialized as they are set at reset but the control register holds the set value B Last Bit of Transmission Data Table 12 3 4 shows the data output holding period of the las
177. is controlled to fetch the next instruction when instruction queue is empty at each cycle on execution At the last cycle of instruction execution the first word operation code of executed instruction is stored to instruction register At that time the next oper and or operation code is fetched to instruction queue so that the next instruction can be executed immediately even if register direct da or immediate imm is needed at the first cycle of the next instruction execution But on some other instruction such as branch instruction instruction queue becomes empty on the time that the next operation code to be executed is stored to instruction register at the last cycle Therefore only when instruction queue is empty and direct address da or immediate data imm are needed instruction queue keeps waiting for a cycle Instruction queue is controlled automatically by hardware so that there is no need to be controlled by software But when instruction execution time is estimated operation of instruction queue should be into consideration Instruction decoder generates control signal at each cycle of instruction execution by micro program control Instruction decoder uses pipeline process to decode instruction queue at one cycle before control signal is needed 2 1 5 Registers for Address Registers for address include program counter PC address registers AO 1 and stack pointer SP Program Counter This register gives
178. low voltage Vi 3 0 0 2Vpp 29 Input leakage current li 0 V to Vpp t2 30 Pull up resistor 30 100 300 31 Output high voltage Vous Vpp 3 0 V 2 0 mA 2 4 32 Output low voltage Vois Vpp 3 0 V loj 22 0 mA 0 4 Input pin 4 P54 P55 Used 33 2 1 9 High level detection voltage 34 2 Vpp 3 0 1 1 35 Figure 1 5 5 2 7 a 36 Low level detection voltage UA 37 Input leakage current li 42 0 V to Vpp 2 38 Input clamp current lc42 Vi gt Vpp Vj 0V 400 us Input pin 5 P27 NRST 39 Input high voltage Vins 0 8Vpp 40 low voltage Vils 0 0 15Vpp 41 Pull up resistor 5 30 100 300 pin 6 P10 to P17 P70 to P77 Schmitt trigger input 42 Input high voltage Vine 0 8Vpp M 43 low voltage Vite 0 0 2Vpp 44 Input leakage current li ko V 0 V to Vpp 2 45 Pull up resistor IRH6 3 0 Vi Vss 30 100 300 Electrical Characteristics Chapter 1 Overview Vpp 1 8V to 3 6V Ta 40 C to 85 Rating Parameter Symbol Conditions Unit MIN MAX 3 0 DD I V DD 46 Pull down resistor RL6 Pull down resistor ON 30 100 300 47 Output high voltage Vous Vpp23 0 2 0 mA 24 48 Output low voltage
179. mode P33 P31 to input mode Operation Chapter 13 Serial Interface 3 Setup Procedure Description 5 Select the transfer bit count SC3MDO 0x03FA0 2 0 SC3LNG2 0 111 6 Select the start condition SC3MDO 0x03FA0 bp3 SC3STE 0 7 Select the first transfer bit SCS3MDO 0x03FA0 bp4 SC3DIR 0 8 Select the transfer edge SC3MDO 0x03FA0 bp6 SC3CE1 1 9 Select the communication type SC3CTR 0x03FA6 SC3CMD 0 10 Select the transfer clock SC3MD1 0x03FA1 bp2 SC3MST 0 11 Control the pin function SC3MD1 0x03FA1 bp4 SC3SBOS 0 bp5 SC3SBIS 1 bp6 SC3SBTS 1 bp7 5 0 12 Set the interrupt level SCSICR 0x03FF3 bp7 6 SC3LV1 0 10 13 Enable the interrupt SC3ICR 0x03FF3 bp1 SCSIE 1 SC3IR 0 14 Set the activation factor for serial communication Dummy data gt 0x03FA5 15 Transition to STOP mode CPUM 0x03F00 bp3 STOP 1 16 Start serial reception Transfer clock Input to SBT3 pin Reception data Input to 5813 pin 5 Set the SC3LNG2 0 flags of the serial 3 mode register SC3MDO to 111 to set the transfer bit count as 8 bits 6 Set the SC3STE flag of the SC3MD0 register to 0 to disable start condition 7 Set the SC3DIR flag of the SC3MD0 register to 0 to set MSB as the first transfer bit 8 Set the SC3CE1 flag of the SC3MD0 register to 1 to set the reception data in
180. of TM70C1L TM70C1H TM80C1L TM8OCI1H register the timer 8 interrupt request flag is set at the next count clock and the value of TM7BCL TM7BCH TM8BCL TM8BCH becomes X 00000000 to restart count up 16 bit Timer Cascade Connection Chapter 6 16 bit Timers 6 12 3 Setup Example PWM Operation Cascade Connection PWM Output Setup Example Timer 7 Timer 8 TMSIO output pin outputs the 1 10 duty PWM output waveform at 1 60 Hz with the cascade connection of timer 7 and timer 8 as a 32 bit timer Select fosc 1 fosc 8 MHZ at operation as the clock source One cycle of the PWM output waveform is depending on the set value of the compare register 1 period of the output waveform is depending of the set value of the compare register 2 An example setup procedure with a description of each step is shown below Tio cupa 1 60 Hz 60 seconds Figure 6 12 1 Output Waveform of TM8IO Output Pin Setup Procedure Description 1 Stop the counter TM7MD 1 x 3F78 bp4 TM7EN 0 TM8MD1 x 3F88 bp7 TM8EN 0 2 Set the special function pin to output P1OMD x 3F1C bp1 P1OMD2 1 bp0 BUZSEL 1 P1DIR 1 bp2 P1DIR2 1 3 Set the cascade connection TM8MD3 x 3F8F bp0 TM8CAS 1 4 Set the PWM output TM7MD2 x 3F79 bp4 TM7PWM 1 5 Set the high precision PWM output operation TM7MD2 x 3F79 bp5 TM7BCR 1 bp6 T7PWMSL 1 6 Select the count clock source TM7MD1
181. of 8 bit timer are set to 0 and stop all timer counting Count Timing of Prescaler Operation Prescaler 0 to 1 Prescaler 0 counts up at the falling edge of fosc Prescaler 1 counts up at the rising edge of fs Peripheral Functions Peripheral functions which can use the prescaler output dividing clock or registers which control the dividing clock selections are shown below Timer 0 Count Clock CKOMD Timer 1 Count Clock CK1MD Timer 2 Count Clock CK2MD Timer 3 Count Clock CK3MD Start the timer operation after the prescaler setup Also at the timer the prescaler output should be set up by the timer mode register The prescaler starts counting at the start of the timer operation Prescaler V 19 Chapter 5 8 bit Timers 5 3 2 Setup Example Se Prescaler Operation Setup Example fs 2 clock which is output from the prescaler 1 is selected to the count clock of the timer 0 A setup procedure example with a description of each step in shown below Setup Procedure Description 1 Select the prescaler output 1 Select fs 2 to the prescaler output by the TMOPSC 1 to CKOMD 0x03F56 0 TMOBAS flag of the timer 0 prescaler selection bp2 1 TMOPSC1 0 0 register TMOBAS 1 At the timer prescaler output selection should be set up by the timer mode register V 20 Prescaler Chapter 5 8 bit Timers 5 4 8 bit Timer 5 4 1 8 bit Timer Operation Timer opera
182. of the TM7MD1 register to 1 to start the timer 7 11 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD1 register Also select 1 2 dividing as the count clock source by the 7 51 to 0 flag 12 Set the IGBT output cycle to the timer 7 preset register 1 TM7PR1 To set 400 Hz by dividing MHz set as 25000 1 24999 x61a7 At the same time the same value is loaded to the timer 7 compare register 1 TM7OC1 and the timer 7 binary counter TM7BC is initialized to x 0000 13 Set the H period of the IGBT waveform to the timer 7 preset register 2 TM7PR2 To set 1 4 duty of 25000 dividing set as 25000 4 6250 186 At the same time the same value is loaded to the timer 7 compare register 2 TM7OC2 14 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 TM7BC counts up from x 0000 The IGBT output waveform outputs H until TM7BC matches the set value of the TM7OC2 register Once they match it outputs L After that TM7BC continues to count up Once TM7BC value matches the register value to be cleared the IGBT output waveform outputs and TM7BC counts up from x 0000 again 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively VI 63 Chapter 6 16 bit Timers To output the IGBT output waveform from the large current pin 70 set the special function pin to output mode as follows refer
183. or output by the P5DIR register A pull P53 4 4 TM8O LED3 up resistor for each bit can be selected P54 24 21 IRQO ACZO individually by the register P55 25 22 IRQ1 ACZ1 Also at output LED direct drive is enabled P56 26 23 IRQ2 for P50 to P53 At reset the input mode is selected and pull up resistors are disabled output H Hi Z P70 33 30 1 KEYO SEG7 port 7 8 bit COMS tri state port P71 34 31 KEY1 SEG6 Each bit can be set individually as either an P72 35 32 KEY2 SEG5 input or output by the P7DIR register A pull P73 36 33 SEG4 up pull down resistor for each bit can be P74 37 34 4 SEG3 selected individually by the P7PLU register A P75 38 35 SBOOB TXDOB KEY5 SEG2 pull up pull down resistor for each port can P76 39 36 SBIOB RXDOB SDA4B be selected individually by the SELUD KEY6 SEG1 register However pull up and pull down P77 40 37 SBTOB SCL4B KEY7 SEGO resistors cannot be mixed At reset the input mode is selected and pull up resistors are disabled output H Hi Z P90 9 9 VO XI port 9 8 bit COMS tri state I O port Each bit can be set individually as either an input or output by the P9DIR register A pull up pull down resistor for each bit can be selected individually by the P9PLU register Also by XSEL register the pin can be Switched to oscillation input pin which con nects to crystal oscillators for low frequency clock operation If
184. output Port output selection Buzzer output Buzzer output 103 214 frequency selection fosc 213 fosc 21 211 fosc 210 fosc 29 fx 24 fx 28 Oscillation stabilization fg o14 wait cycle selection fg 210 15 26 1 16 22 1 1 Do not use at high speed operation NORMAL mode Use at slow speed operation SLOW mode a When BUZOE flag is set to 0 buzzer output becomes Low Overview Chapter 10 Buzzer 10 1 2 Block Diagram Buzzer Block Diagram fosc 3 1 210 1 2 fx R fosc 2 4 fosc 213 055 22 d BUZZER 11 X fosc 2 gt fosc 210 MUX 44 NBUZZER DLYCTR 4 ose 4 Memes Count clear Le DUE control circuit fx 28 _DLYS1_ BUZS0_ T _BUZS1_ Buzsz BUZOE 7 Figure 10 1 1 Buzzer Block Diagram Overview X 8 Chapter 10 Buzzer 10 2 Control Register Buzzer is formed by the control register DLYCTR 10 2 1 Registers Table 10 2 1 shows the buzzer control register Table 10 2 1 Buzzer Control Register DLYCTR 0x03F03 Oscillation Stabilization Wait Time Control Register P10MD OxO3F1C Port 1output mode register Control Register Chapter 10 Buzzer 10 2 2 Oscillation Stabilization Wait Time Control Register DLYCTR Oscillation Stabilization Wait Tim
185. parity 1 parity odd parity even parity Selection of start condition Only enable start condition is available Specification of the first transfer bit O O Specification of input edge output edge 5 Overview Chapter 12 Serial interface 1 SBO1 output control after final data is transferred H L final data hold Function in STANDBY mode Only slave reception is available Internal clock dividing value Not divided Divided by 8 Divided by 8 Divided by 16 Divided by 16 Clock source fosc 2 fosc 2 fosc 4 fosc 4 fosc 16 fosc 16 fosc 64 fosc 64 fs 2 fs 2 15 4 15 4 External clock Timer 1 output Timer 2 output Timer 1 output Timer 2 output Maximum transfer rate 5 0 MHz 300 kbps fosc Machine clock High speed oscillation fs System clock Overview XII 3 Chapter 12 Serial interface 1 12 1 2 Block Diagram B Serial interface 1 Block Diagram
186. pin Buzzer output is available Driving frequency can be set by the DLYCTR register The driving frequency can be selected by the DLYCTR register To select buzzer output for port 0 select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register At the same time select buzzer output by the oscillation stabilization wait control register DLYCTR These can be used as normal I O pins when the serial interface is not used Pin Description 1 17 Chapter 1 Overview Name is VO Other Function Function Description Pin No Pin No TM7IO 28 25 VO P13 NBUZZER CLKOUT Timer I O pins Event counter clock input pin timer output TM8IO 27 24 P12 BUZZER and PWM signal output pin for 16 bit timer 7and 8 To use this pin as event clock input configure this as input by the P1DIR register In the input mode pull up pull down resistors can be selected by the P1PLU register For timer output PWM signal output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register These can be used as normal I O pins when the serial interface is not used TM7O 2 Output P51 LED1 Timer output pins Timer output PWM signal output pin for 16 TM8O 4 P53 LED3 bit timer 7 and 8 To select timer output and PWM signal output select the special function pin at t
187. pin selection can be done by setting the flag LC2SL 1 of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forcefully set to input mode and pull up resistor is disabled P73 can be used as the LCD segment output pin as well The SEG4 pin selection can be done by setting the bpO flag LC2SLO of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forcefully set to input mode and pull up resistor is disabled P74 can be used as the LCD segment output pin as well The SEG3 pin selection can be done by setting the bp7 flag LC1SL3 of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forcefully set to input mode and pull up resistor is disabled P75 can be used as the LCD segment output pin as well The 5202 pin selection can be done by setting the bp6 flag LCISL2 of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forcefully set to input mode and pull up resistor is disabled P76 can be used as the LCD segment output pin as well The SEGI pin selection can be done by setting the bp5 flag LCISL 1 of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forceful
188. register can set the transfer bit MSB first or LSB first can be selected Operation Chapter 12 Serial interface 1 B Transmission Data Buffer The transfer data buffer TXBUFI is the spare buffer which stores data to be loaded to internal shift register Set the data to be transferred to transfer data buffer TXBUF1 and the data is automatically loaded to internal shift register The data loading takes more than 3 transfer clocks cycles Data setting to TXBUF1 again during data loading may not be operated properly You can determine whether or not data loading is in progress by monitoring transfer buffer empty flag SCITEMP of the SCISTR SCITEMP flag is set to 1 when data is set to TXBUFI and cleared to 0 when data loading ends Data set to 1 I x Clock prescaler output SC1TEMP Clock SBT1 pin Data road period Figure 12 3 1 Transmission Data Buffer Reception Date Buffer The reception data buffer RXBUFI is the spare buffer that pushed the received data in the internal shift register After the communication complete interrupt SCITIRQ is generated all data stored in the internal shift register is stored to the received data buffer RXBUFI automatically RXBUFI can store data up to 1 byte RXBUFI is rewritten every time communication is completed Data of RXBUFI should be read out before the next reception is completed The received data buffer empty flag SC1REMP is set to 1 a
189. register to SCOMD3 0x03F94 100 to select fs 2 as the clock source bp2 0 SCOPSC2 0 100 3 Select the pin 3 Set the SCOSL flag of the SCSEL register to 0 to select SCSEL 0x03F90 A port A as I O pin SCOSL 0 4 Control the pin style 4 Set the PAODC2 PAODCO flag of the PAODC register PAODC 0x03F2D to 0 0 to select Push pull to SBOO SBTO pin Set the bp2 PAOD2 0 PAPLU2 PAPLUO flag of the PAPLU register to 0 0 to bp0 PAODC0 0 disenable the pull up resistor PAPLU 0x03F4A bp2 PAPLU2 0 0 XI 40 Operation Chapter 11 Serial interface 0 Setup Procedure Description 5 Control the pin direction PADIR 0x03F3A bp2 PADIR2 0 bp1 PADIR1 0 PADIRO 1 6 Select the transfer bit count SCOMDO 0xOSF91 bp2 0 SCOLNG2 0 111 7 Select the start condition SCOMD0 0x03F91 bp3 SCOSTE 0 8 Select the first bit to be transferred SCOMD0 0x03F91 bp4 SCODIR 0 9 Select the transfer edge SCOMD0 0x03F91 bp7 SCOCE1 1 10 Select the communication type SCOMD1 0x03F92 SCOCMD 0 11 Select the transfer clock SCOMD1 0x03F92 bp2 SCOMST 0 bp3 SCOCKM 0 12 Control the pin function SCOMD1 0x03F92 bp4 SCOSBOS 0 bp5 SCOSBIS 1 bp6 SCOSBTS 1 bp7 SCOIOM 0 13 Set the interrupt level SCOTICR OxO3FFO bp7 6 SCOLV1 0 10 14 Enable the interrupt SCOTICR OxOSFFO bp1 SCOTIE 1 SCOTIR 0 15 Set the start
190. request flag is operated by the hardware That is set to 1 when any interrupt factor is generated and cleared to 0 when the interrupt is accepted If you want to operate it by the software the IRWE flag of MEMCTR should be set to 1 Interrupt Flag Setup Procedure A setup procedure of the interrupt request flag set by the hardware and the software shows as follows Setup Procedure Description 1 Disable all maskable interrupts PSW bp6 MIE 0 2 Select the interrupt factor 3 Enable the interrupt request flag to be rewritten MEMCTR 0 03F01 bp2 IRWE 1 4 Rewrite the interrupt request flag xxxICR bp0 xxxIR 5 Disable the interrupt request flag to be rewritten MEMCTR 0 03F01 bp2 IRWE 0 6 Set the interrupt level xxxICR bp7 6 xxxLV1 0 PSW bp5 4 IM1 0 7 Enable the interrupt xxxICR bp1 xxxlE 1 8 Enable all maskable interrupts PSW bp6 MIE 1 1 Clear the MIE flag of PSW to disable all maskable interrupts This is necessary especially when the interrupt control register is changed 2 Select the interrupt doctor such as interrupt edge selection or timer interrupt cycle change 3 Set the IRWE flag of MEMCTR to enable the interrupt request flag to be rewritten This is necessary only when the interrupt request flag is changed by the software 4 Rewrite the interrupt request flag xxxIR of the interrupt control register XxxICR 5 Clear the IR
191. serial data output the SBI1 pin to the serial input SBT1 pin to the transfer clock input output Set the SC1IOM flag 0 to set the serial data input from the SBI1 pin 9 Set the interrupt level by the SC1TLV1 to 0 flag of the serial 1 transmission interrupt control register SC1TICR Operation Chapter 12 Serial interface 1 Setup Procedure Description 10 Enable the interrupt SC1TICR OxOSFF2 bp1 SC1TIE 1 SCOTIR 0 11 Start the serial transmission Transmission data TXBUF1 0x03F9F Reception data input 5 pin 10 Set the SC1TIE flag of the SC1TICR register to 1 to enable the interrupt If any interrupt request flag SC1TIR of the SC1TICR register is already set clear SC1TIR before the interrupt is enabled 11 Set the transmission data to the serial transmission data buffer TXBUF1 The transmission or reception is started by the internal clock generation When the transmission is finished the serial 1 UART transmission interrupt SC1TIRQ is generated Chapter 3 3 1 4 Setup Note Procedures 1 to 3 5 6 7 to 8 can be set at the same time Operation XII 35 Chapter 12 Serial interface 1 Reception Setup Example The setup example for clock synchronous serial communication with serial 1 is shown Table 12 3 12 shows the conditions at Reception Table 12 3 13 Setup Examples for Synchronous Serial Interface Reception
192. setup procedure in order Activation of communication should be operated after all control registers refer to Table 11 2 1 except TXBUFO are set Transfer rate of transfer clock set by the SCOMD3 register should not exceed 5 0 MHz Operation XI 39 Chapter 11 Serial interface 0 B Transmission Reception Setup Example Standby Mode Reception The setup example for clock synchronous serial communication with serial 0 is shown Table 11 3 14 shows the condition at standby mode reception Table 11 3 14 Setup Examples for Synchronous Serial Interface Transmission Reception Standby Mode Reception Setup item Set to Serial data input pin Select SBIO 3 channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Clock Clock slave Operation mode Stop mode Clock source fs 2 Clock source dividing Not divided Pin A port A SBTO SBOO pin style Push pull SBTO pin pull up resistor Not added 5800 pin pull up resistor Not added serial 0 communication complete Enable interrupt An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation 1 Set the SCOPSCE flag of the SCOMDS register to 1 to SCOMD3 0x03F94 select prescaler operation bp3 SCOPSCE 1 2 Select the clock source 2 Set the SCOPSC2 to 0 flag of the SCOMDS
193. signal from SBT1 pin is masked to prevent operating errors by noise This mask can be released automatically by setting a data to TXBUF1 access to the TXBUFI register or enabling a start condition to the data input pin Therefore at slave communication set data to TXBUF1 or input an external clock after start condition is input However the external clock should be input after 3 5 transfer clock interval past from the data set to TXBUF1 This period is for loading the data from TXBUFI to the internal shift register Table 12 3 1 Synchronous Serial Interface Activation Factor and Cautions Clock Communication type Start condition Activation source of communication Master Transmission Enabled Set transmission data 1 Disabled Set transmission data 2 Reception Enabled Input start condition 3 Set dummy data 2 Disabled Set dummy data 2 Transmission Reception Enabled 4 Disabled Set transmission data 2 Slave Transmission Enabled Input clock after transmission data is set 5 Disabled Input clock after transmission data is set 6 Reception Enabled Input clock after start condition is input 7 Or Input clock after dummy data is set 6 Disabled Input clock after dummy data is set 6 Transmission Reception Enabled 4 Disabled Input clock after transmission data is set 6 Operation XII 18 Chapter 12 Serial interface 1 XII 14 41 After
194. signal output select the special function pin by the port 1 output mode register P1OMD and the port 7 output mode register PZOMD and set to the output mode by the P1DIR P7DIR registers These can be used as normal I O pins when the serial interface is not used TMOO TM20 2 2 27 29 Output P50 LEDO P70 SBO1A TXD1A SEG10 P52 LED2 P17 SBT1A Timer output pins Timer output PWM signal output pin for 8 bit timer 0 and 2 To select timer output and PWM signal output select the special function pin by the port 5 output mode register PSOMD and port 7 output mode register P7OMD and set to the output mode by the P5DIR P7DIR register These can be used as normal I O pins when the serial interface is not used RMOUT 29 26 Output P14 TMOIO SEG11 Remote control transmission signal output pins Output pin for remote control transmission signal with a carrier signal For remote control carrier output select the special function pin by the port 1 output mode register P1OMD and set to the output mode by the P1DIR register At the same time select remote control carrier output by the remote control carrier output control register RMCTR These can be used as normal pins when the serial interface is not used BUZZERA NBUZZERA 27 28 24 25 Output 12 TM8IO P13 TM7IO CLKOUT Buzzer outputs Piezoelectric buzzer driver
195. speed should be under 5 0 MHz If transfer clock exceeds 5 0 MHz data Y may not be transferred properly In reception you can use 5813 pin as general port by setting SC3IOM of the SC3MD 1 regis ter to 1 to select serial data input from SBOS pin Transmission Buffer Empty Flag If any data is set to TXBUF3 during communication after setting data to TX BUF3 before generating the commu nication complete interrupt SC3IRQ the transmission buffer empty flag SC3TEMP of the SC3STR register is set to 1 That indicates that the next transmission data is going to be loaded Data is loaded to inside shift register from TXBUF3 by generation of SC3TIRQ and the next transfer is started as SC3TEMP is cleared to 0 BUSY flag If data is set to the transmission reception shift register TXBUF3 or start condition is enabled the busy flag SC3BSY is set That is cleared to 0 by the generation of the communication end interrupt SC3IRQ The SC3BSY flag setup is maintained during continuous communication If transmission buffer empty flag SC3TEMP is 0 when communication end interrupt SC3IRQ is generated SC3BSY is cleared to 0 B Forced Reset You can shut down the communication by setting both of the SC3SBOS flag and the SC3SBIS flag of the SC3MDI register to 0 the SBO3 pin function port input data input 1 and SC3BSY flag of the SC3MDO register When a forced reset is done the SC3BSY flag of the SC3MDO register is cle
196. standby mode A wait period is inserted for oscillation stabilization at reset and when returning from STOP mode but not when returning from HALT mode High low frequency oscillation mode is automatically returned to the same state as existed before entering standby mode To stabilize the synchronization at the moment of switching clock speed between high speed Y oscillation fosc and low speed oscillation fx fosc should be set to 2 5 times or higher a Set of XSEL register before changing to the low speed oscillation mode Standby Function Chapter 2 CPU Basics P90 can be used as the low speed oscillation as well Set the low speed oscillation selection register XSEL for SLOW mode setting BM Low Speed Oscillation Selection Register XSEL Table 2 4 1 Low Speed Oscillation Selection Register XSEL 0x03F4C P90 I O port low speed oscillation selection 0 port 1 Low speed oscillation Set the of XSEL register before changing to the low speed oscillation mode Standby Function 23 Chapter 2 CPU Basics 2 4 5 Mode Control Register O Transition from one mode to another mode is controlled by the CPU mode control register CPUM 7 6 5 4 3 2 1 0 CPUM Reserved OSCSEL1 OSCSEL0 OSCDBL STOP HALT OSC1 OSCO At reset 0 0 0 0 0 0 0 0 m
197. termination set the flag to 0 The ports used for communication can be used as general ports while the serial interface is not in operative state When the SELI2C register is set to 0 SCAADO register SCATXB register and SCARXB register is auto matically cleared B Slave Address Setup This serial interface can select either 7 bits or 10 bits slave address To select 7 bits slave address set the I2CADM flag of the SCAADI register to 0 to select 7 bits address mode and set the slave address to upper 7 bits of the I2CADO register I2CAD7 to IZ2CAD1 To select 10 bits slave address set the I2CADM flag of the SCAADI reg ister to 1 to select 10 bits address mode and set the upper 2 bits of the slave address to lower 2 bits of the I2CADI register 2 9 I2CADS and set the lower 8 bits of the slave address to I2CADO register When 10 bits address mode is selected this serial interface circuit is capable of data reception only General Call Communication This serial interface is compatible with general call communication mode Set the I2CGEM flag of the SC4AD1 register to 1 to select general call communication mode In this mode slave address set in the SCAADO and 5 registers are invalid Data Transmission Reception This serial interface enables automatic address determination after detection of start condition on IIC bus Serial interface 4 interrupt SCAIRQ is generated only when address transmitted from maste
198. the IGBT output TM7PR2 X SF7D 7 2710 11 Set the dead time TM7DPR1 x 3F7E x 50 TM7DPR2 x 3F7F x 9F 12 Set the IGBT output TM7MD2 x 3F79 bp4 TM7PWM 1 TM7MD3 x 3F8E bp2 T7IGBTEN 1 TM8MD3 x 3F8F bp2 TM8SEL 1 13 Set the special function pin to output P1OMD x 3F1C bp3 P1OMD3 1 bp2 NBUZSEL 1 bp1 P1OMD2 1 bp0 BUZSEL 1 P1DIR 1 P1DIR3 1 bp2 P1DIR2 1 6 Set the interrupt level by the IRQ1LV1 to 0 flag of the IRQOICR register If any interrupt request flag is already set clear it 7 Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt 8 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing as the count clock source by the TM7PS1 to 0 flag 9 Set the IGBT output cycle to the timer 7 preset register 1 TM7PR1 To set 200 Hz by dividing 8 0 MHz set as 40000 1 39999 0 9 At the same time the same value is loaded to the timer 7 compare register 1 7 1 and the timer 7 binary counter 7 is initialized to 0 0000 10 Set the H period of the IGBT waveform to the timer 7 preset register 2 TM7PR2 To set 1 4 duty of 40000 dividing set as 40000 4 10000 0x2710 At the same time the same value is loaded to the timer 7 compare register 2 TM7OC2 11 Set the period from the falling of the TM8IO to the rising o
199. the LCD mode control register 1 bp3 0 LCDCK3 0 0100 LCDMD1 4 Select the segment output port pin 4 Select the SEG3 to SEGO and COM2 to COMO by the Select the common output port pin LCD output control register 1 LCCTR1 and SEG to LCCTR1 X 3FC2 SEGA by the LCD output control register 2 LCCTR2 bp7 0 SC1SL3 0 COMSL3 0 11110111 LCCTR1 X 3FC3 bp3 0 LC1SL3 0 111 5 Set the LCD panel display data 5 Display 23 on the display panel by the address X 2E00 Segment output latch SEG1 0 to X 2E03 of the segment output latch SEG7 to SEGO 2 007 76 Chapter 16 4 5 1 3 duty Segment output latch SEG3 2 X 2E01 X 40 Segment output latch SEG5 4 2 02 X 27 6 Start the LCD operation 6 Set the LCDEN flag of the LCD mode control register 1 LCDMD1 X 3FCO0 LCMD1 to 1 to start the LCD operation bp7 LCDEN 1 Display XVI 29 Chapter 16 LCD 16 4 7 1 4 duty 1 4 duty MN101C78 SegmentLatch 2 01 X 2E01 X 2E00 X 2E00 0 0 1 bit7 bit3 1 bit6 bit2 1 bit5 bit1 bit4 bitO A electrode B electrode Light OFF LCDPANEL LCD ON COM S COM S COM N LCD OFF SEG S SEG S SEG N SEG N LCD clock uncertain Data 1 0 Vict Vic2 Vics Vss COM Vici Vice2 Vics Vss SEG Vico COM SEG 1 3VLc
200. the address of the currently executing instruction It is 19 bits wide to provide access to a 256 KB address space in half byte 4 bit increments The LSB of the program counter is used to indicate half byte instruction The program counter after reset is stored from the value of vector table at the address of 0x04000 18 Program PG counter Figure 2 1 3 Program Counter Overview Chapter 2 CPU Basics Address Registers 0 1 These registers are used as address pointers specifying data locations in memory They support the operations involved in address calculations i e addition subtraction and comparison Those pointers are 2 bytes data Transfers between these registers and memory are always in 16 bit units Either odd or even address can be trans ferred At reset the value of address register is undefined 15 0 1 A Figure 2 1 4 Address Registers Stack Pointer SP This register gives the address of the byte at the top of the stack It is decremented during push operations and incremented during pop operations Ar reset the value of SP is undefined 15 0 Stack pointer Figure 2 1 5 Stack Pointer 2 1 6 Registers for Data Registers for data include four data registers DO D1 D2 D3 Data Registers DO D1 02 03 Data registers DO to D3 are 8 bit general purpose registers that support all arithmetic logical and shift operations registers can be used for data tran
201. the internal shift register If data is stored to the shift register RXBUFO when the SCOSBIS of the SCOMDI register is set to serial input the reception buffer empty SCOREMP of the SCOSTR register is set to 1 This indicates that the reception data is going to be read out SCOREMP is cleared to 0 by reading out the data of RXBUFO B Transmission Buffer Empty Flag During the communication after the data is loaded to the internal shift register and before the communication complete interrupt SCOTIRQ is generated if any data is set to TXBUFO again the transmission buffer empty flag SCOREMP of the SCOSTR register is set to 1 This indicates that the next transmission data is going to be loaded Data is loaded to the internal shift register from TXBUFO by generation of SCOTIRQ and the next trans fer is started as SCOTEMP is cleared to 0 Overrun Error and Error Monitor Flag After reception complete if the next data has already been received before reading out of the data of the received data buffer RXBUFO overrun error is generated and the SCOORE flag of the SCOSTR register is set to 1 At the same time the error monitor flag SCOERE is set to indicate a reception error The SCOERE flag is cleared after the data of RXBUFO is read out and the next communication complete interrupt SCOTIRQ is generated SCOERE is cleared as SCOORE flag is cleared These error flags have no effect on communication operation Reception BUSY Fl
202. the output is on at reset set them open Pins used as both LCD and port pins should be set to open to be used as LCD output pins Output Control some 10 Output Control Output OFF Output OFF Data Data some 10 kQ Input Output OFF Output OFF Data some 10 kQ some 10 kQ Figure 1 7 3 Unused l O Pins high impedance output at reset Cautions for Circuit Setup 1 37 Chapter 1 Overview 1 7 3 Power Supply l usr E B The Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on If this order is reversed the destruction of micro controller by a large current flow could be occurred Input Input Protection Resistance Forward current generates VDD Figure 1 7 4 Vpp and Input Pin Voltage The Relation between Vpp and Reset Input Voltage After power supply is on reset pin voltage should be low for sufficient time before rising in order to be recog nized as a reset signal Refer to Chapter 1 1 1 2 Product Summary Power Voltage __ Reset Input Voltage Reset pins Low Level Under Input Voltage Enough time is necessary to recognize as reset Figure 1 7 5 Power Supply and Reset Input Voltage 1 38 Cautions for Circuit Setup Chapter 1 Overview 1 7 4 Power Supply Circuit zas 2 Cautions for Setting Circuit with Vpp The MOS logic such a microcomputer is high speed and high d
203. the start condition output the transfer clock is output after 1 transfer clock interval 2 After setting transmission data dummy data the transfer clock should be output after 3 5 transfer clock interval at the maximum The system configuratioin is required so that the transmission data dummy data are written after the master receives the information of slave data load completion 3 After the start condition input output the transfer clock after 2 5 transfer clock interval at the maximum When receiving data continuously the system configuration is required to notify the master of the readout completion Without the notification the data before readout may be overwritten 4 When the start condition is set to enable transmission and reception should not be excuted at the same time 5 After setting the transmission data output the start condition and wait until the master excutes the clock input At the clock input 1 or more transfer clock interval is required after the start condition output 6 At the clock input 3 5 or more transfer clock interval is required after setting transmission data dummy data The system configuration is required to notify the master of the data load completion 7 At the clock input 0 5 or more transfer clock interval is required after the start condition input When receiving data continuously the system configuration is required to notify the master of the readout completion Without th
204. to internal shift register and before communication end interrupt SC3IRQ is generated In master communication communication blank from SC3IRQ generation to next transfer clock output is 4 transfer clock Operation XIII 15 Chapter 13 Serial Interface 3 Input edge output edge Setup The 5 flag of the SC3MDO register sets the output edge of the transmission data and the input edge of the received data Data at transmission is output at the falling edge of clock as the SC3CEI flag 0 and at the ris ing edge of clock as the SC3CEI 1 Data at reception is input at the rising edge of clock as the SC3CEI 0 and at the falling edge of clock as the SC3CEI flag 1 Table 13 3 2 Input Edge Output Edge of Transmission and Reception Data SC3CE1 Transmission data output edge Received data input edge 0 Y 1 1 Y Clock Setup Clock source is selected from the dedicated prescaler and timers 2 3 output 2 channels with the SC3PSC3 to 0 of the SC3MD3 register The dedicated prescaler is started by selecting count enable with the SC3PSCE of the SC3MD3 register The SC3MST flag of the SC3MDI register selects the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock with same frequency to the external clock with the SC3MD3 register as the interrupt flag SC3IRQ is generated by the internal clock
205. transmission Serial transmission starts 15 19 lt Transmission ends gt lt communication end processing Set the IIC3STPC flag SC3CTR 0x03FA6 bp5 IIC3STPC 1 13 Set the SC3IE flag of the SC3ICR register to 1 to enable the interrupt If the interrupt request flag SC3IR of the SCS3ICR register is already set clear SC3IR before the interrupt is enabled Chapter 3 3 1 4 Interrupt Flag Setup 14 Set the transmission data to the transmission data buffer TXBUF3 Then the transfer clock is generated to start transmission If the ACK bit is received after data transmission the communication complete interrupt SCSIRQ is generated 15 Confirm the IIC3STC flag of the serial 3 control register SC3CTR When the previous transmission is completed properly IIC3STC 0 If IICSSTOC 1 the communication should be re executed 16 Confirm the level of the ACK bit received by the 5 flag of the serial control register SC3CTR When SC3ACKO 0 the transmission can be continued When SC3ACKO 1 the reception at slave may not be operated properly so finish the communication 17 To change the transfer count bit set the transfer count bit by the SC3LNG2 0 flag of the serial 3 mode register SC3MDO 18 Set the transmission data to to start the transmission 15 19 Set the IIC3STPC flag of the serial 3 control register SC3CTR 1 Stop con
206. transmission reception reception in STANDBY mode Item set to Serial data input pin 5813 3 channels Transfer bit count 8 bit Start condition Disabled First transfer bit MSB Input edge Falling Clock Clock slave Operation mode STOP mode Clock source fs 2 SBTS SBOS3 pin type Push pull SBT3 pin pull up resistor Not added 5813 pin pull up resistor Not added Serial interface 3 communication com Enabled plete interrupt An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation SC3MD3 0x03FA2 bp3 SC3PSCE 1 2 Select the clock source SC3MD3 0x03FA2 bp2 0 SC3PSC2 0 100 3 Control the pin type 0x03F3B 2 PSODC2 0 P3PLU 0x03F43 bp2 P3PLU2 0 4 Control the pin direction P3DIR 0x03F33 bp2 P3DIR2 1 bp1 P3DIR1 0 bp3 P3DIR3 0 1 Set the SC3PSCE flag of the SC3MD3 register to 1 to select prescaler operation 2 Set the SC3PSC2 0 flag of the SC3MD3 register to 100 to select fs 2 as the clock source 3 Set the PSODC2 flags of the PSODC register to 0 0 to select push pull for the pin type Set the P3PLU2 P3PLUS flags of the register to 0 0 not to add pull up resistor 4 Set the P3DIR2 P3DIR3 flags of the Port pin control direction register P3DIR to 1 0 to set P32 to output
207. under 500 and the external capacitor C more than 1000 pF under 1 uF should be connected to it 2 The A D conversion frequency should be set in regard to R C 3 At the A D conversion if the input level of microcontroller is changed or the peripheral added circuit is switched to ON OFF the A D conversion could work wrongly as the analog input pins and power pins cannot be fixed At the setup checking confirm the wave form of analog input pins Equivalent circuit block that outputs analog signal microcontroller ANW A D input pin HT 5777 55 Figure 15 3 4 Recommended Circuit Operation XV 15 Chapter 15 A D Converter XV 16 Operation Chapter 16 LCD Chapter 16 LCD 16 1 Functions This LSI contains an internal LCD driver circuit with 12 segment pins and 4 common pins The LCD driver con tains of a segment output latch LCD control registers a prescaler a timing control circuit a multiplexer segment drivers common drivers and voltage divider resistors 16 1 1 Functions Table 16 1 1 shows the functions of the LCD driver circuits Table 16 1 1 LCD Functions LCD Duty Static 1 2 duty 1 3 duty 1 4 duty Segment Output Pins SEGO to SEG11 Common Output Pins COMO to COM3 LCD Power Supply Vici to Vi LCD Voltage Divider Resistor Vici input voltage can be divided into 2 8 1 3 Selectable from high resistance or low resistance Clock Sourc
208. 0 2 Disable the interrupt TBICR Ox03FEC bp1 TBIE 0 3 Select the interrupt generation cycle TM6MD 0x03F 62 bp6 4 TM6IR2 0 100 4 Initialize the time base timer 0 03 63 20x00 b Set the interrupt level TBICR OxOEFC bp7 6 TBLV1 0 01 6 Enable the interrupt TBICR 0xOSFEC bp1 TBIE 1 7 Start the time base timer operation 6 0 03 64 1 1 1 Select fosc as a clock source by the TM6CKO flag of the timer 6 mode register TM6MD 2 Set the TBIE flag of the TBICR register to 0 to disable the interrupt 3 Select the selected clock X 1 21 as an interrupt generation cycle by the TM6IR2 to 0 flag of the TM6MD register 4 Write value to the time base timer clear control register TBCLR to initialize time base timer b Set the interrupt level by the TBLV1 to 0 flag of the time base interrupt control register TBICR If any interrupt request flag may be already set clear them Chapter 3 3 1 4 Interrupt Flag Setup 6 Set the TBIE flag of the TBICR register to 1 to enable the interrupt 7 Set the TBEN flag of the TM6BEN register to 1 to start the time base timer When the selected interrupt generation cycle is passed the interrupt request flag of the time base interrupt con trol register TBICR is set to 1 Time Base Timer VII 17 Chapter 7 Time Base Timer Free running Timer VII 18 Time Base Timer
209. 0 to use as the general port For P75 P76 and P77 each bit can be selected individually as Nch open drain output by the port 7 Nch open drain control register P ODC The control flag of the port 7 Nch open drain control register P7ODC is set to 1 Nch open drain output and 0 for push pull output B Special Function Pin Setup P70 can be used as the timer 1 I O pin as well Each bit can be selected individually as output mode by the bpO of the port 7 output mode register P7OMD When the bp0 of the port 7 output mode register P7OMD is set to 1 for the special function data output and 0 to use as the general port P71 can be used as the timer 3 I O pin as well Each bit can be selected individually as output mode by the of the port 7 output mode register P7OMD When the of the port 7 output mode register P7OMD is set to 1 for the special function data output and 0 to use as the general port P75 can be used as output pin of the serial 0 transmission data and UARTO transmission data as well When SCOSBOS flag of the serial interface 0 mode register 1 SCOMD1 is set to 1 P75 is the serial data output pin Push pull output Nch open drain output can be selected by setting the port 7 Nch open drain control register P7ODC P76 can be used as input pin of the serial 0 reception data and UARTO reception data as well P77 can be used as the serial 0 clock input pi
210. 0 MHz fx 32 768 kHz 0 fosc 10 MHz 100 ns 1 fosc 27 78 125 kHz 12 80 us 0 fosc 28 39 062 kHz 25 60 us 1 fosc 29 19 521 kHz 51 20 us External Interrupts Chapter 3 Interrupts Noise Remove Function Operation External interrupts 0 and 1 After sampling the input signal to the external interrupt pins IRQO IRQ1 with the set sampling time if the same level comes continuously three times that level is sent to the inside of LSI If the same level does not come con tinuously three times the previous level is sent It means that only the signal with the amplitude of longer than Sampling time X 3 sampling clock can pass through the noise filter and other signals with amplitude shorter than this are removed because those are regarded as noise cm CC EE A IRQn pin input signal Signal after filtering noise 0 0 1 1 1 1 1 0 0 Figure 3 3 5 Noise Remove Function Operation Noise filter cannot be used at STOP mode and HALT mode a Noise filter can be uses at the SLOW mode However sampling timing gets slow extremely External Interrupts Ill 57 Chapter 3 Interrupts Noise Filter Setup Example External interrupt 0 and 1 Noise remove function is added to the input signal from P54 pin to generate the external interrupt 0 IRQO at the rising edge The sampling clock is set to fosc 2 and the operation state is fs 10 MHz An example setup pro cedure with a descri
211. 0 x 2 x 8 1 207 OxCF Timer clock source and the set value of timer compare register at the standard rate are shown in the following page 1 Transfer rate should not exceed 300 kbps XII 50 Operation Chapter 12 Serial interface 1 Table 12 3 21 Setup Value of Serial Interface Transfer Speed 1 When Setting UART Inter Clock to Divided by 8 decimal Transfer speed bit s 300 960 1200 2400 4800 fosc Clock source MHz Timer Set value Calculate Set value Calculate Set value Calculate Set value Calculate Set value Calculate d value d value d value d value d value 2 00 fosc 129 962 103 1202 51 2404 25 4808 fosc 4 103 300 25 1202 12 2404 fosc 16 25 300 fosc 32 12 300 fosc 64 fs 2 103 300 25 1202 12 2404 fs 4 51 300 12 1202 4 00 fosc 207 1202 103 2404 51 4808 fosc 4 207 300 64 962 51 1202 25 2404 12 4808 fosc 16 51 300 12 1202 fosc 32 25 300 fosc 64 12 300 fs 2 207 300 64 962 51 1202 25 2404 12 4808 fs 4 104 297 25 1202 12 2404 4 19 fosc 217 1201 108 2403 54 4761 fosc 4 217 300 67 963 fosc 16 16 963 6 2338 fosc 32 fosc 64 fs 2 217 300 67 963 fs 4 108
212. 00 dividing set as 25000 4 6250 0x1869 At the same time the same value is loaded the timer 7 compare register 2 TM7OC2 9 Start the timer operation 9 Set the TM7EN flag of the TM7MD1 register to 1 to TM7MD1 0x03F78 operate the timer 7 bp4 TM7EN 1 TM7BC counts up from 0x0000 The PWM source waveform outputs until TM7BC matches the set value of the TM7OC2 register Once they matches it outputs L After that TM7BC continues to count up Once TM7BC matches the register to be cleared the PWM output waveform outputs again and TM7BC counts up from 0x0000 again VI 48 16 bit High Precision PWM Output Cycle Duty can be changed consecutively Chapter 6 16 bit Timers 6 8 16 bit Timer Capture 6 8 1 Operation The value of the binary counter is read out at the timing of the external interrupt input signal which is synchro nized to fosc fs or the external event signal at the timing of the timer 0 and timer 1 interrupts or at the timing of the writing operation with any value to the capture register Capture Operation with External Interrupt Signal as the Trigger Timer 7 Timer 8 Input capture trigger is generated at the external interrupt signal The capture trigger is selected by the timer 7 mode register 1 TMnMD1 and the timer mode register 2 TMnMD2 Selectable capture triggers and the interrupt flag setup are shown below Table 6 8 1 Capture Trigger
213. 0x03F54 Timer 0 mode register 0x03F52 Timer 0 compare register 0x03F56 Timer 0 prescaler selection register 0x03F1C Port 1 output mode register 0x03F31 Port 1 direction control register VIII 4 Control Registers Chapter 8 Remote Control Carrier Functions 8 2 2 Remote Control Carrier Output Control Register Remote Control Carrier Output Control Register RMCTR 0x03F6C m p p F F E E p p WHEN RVDTYI OTE WITH 0 0 0 0 0 0 At reset Access R W R W R W R W R W R W R W R W Description Reserved Set always to 0 P14 special functions output selection TMORM 0 TMOIO 1 RMOUT Remote control carrier output enable 0 L level output 1 remote control carrier output Remote control carrier duty selection RMDTY1 00 1 2 duty RMDTYO 01 1 3 duty 1 Timer output Remote control carrier base timer selection RMBTMS 0 Timer 0 output selection 1 Timer 3 output selection Control Registers VIII 5 Chapter 8 Remote Control Carrier Functions 8 3 Operations 8 3 1 Operations Remote control carrier output functions can generate the carrier pulse for the remote control Operation of the remote control carrier output Remote control carrier can be created by using the output signals of timer 0 and timer 3 Duty ratio can be selected from 1 2 1 3 Timer output Remote control carrier output signal is output from the
214. 1 0 10 If the interrupt request has been already set clear the interrupt request flag IRQOIR 4 Enable the interrupt 4 Set the IRQOIE flag of the IRQOICR register to 1 to IRQOICR 0x03FE2 enable the interrupt bp1 IRQOIE 1 b Set the STOP mode b Transfer to the STOP mode by setting STOP flag of the CPUM 0x03F00 CPU mode control register CPUM to 1 bp3 STOP 1 Chapter 2 2 4 4 Transition to Standby Modes When the low level signal is input to P54 and the value of the external interrupt valid edge specify flag REDGO matches the external interrupt 0 the external interrupt 0 is accepted and recover from the STOP mode External Interrupts 61 Chapter 3 Interrupts 62 External Interrupts Chapter 4 Ports Chapter 4 Ports 2 4 1 Overview 4 1 1 I O Port Overview A total of 40 pins on this LSI including those shared with special function pins are allocated for the I O ports of port 1 port 2 port 3 port 5 port 7 port 9 and port A 4 1 2 Port Status at Reset Table 4 1 1 I O port status at reset single chip mode Port mode Pull up Pull down resistor port special functions Port 1 Input mode P17 to P12 port No pull up pull down resistor P11 P10 Pull up pull down resistor Port 2 Input mode P27 Pull up resistor port Port 3 Input mode P30 to P36 No pull up resistor port P37 Pull down resistor Port 5
215. 1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 00 7 Select IGBT timer startup factor TM7MD3 0x03F8E bp1 0 T7IGBT1 0 00 8 Set the timer pulse output generation cycle TM7PR1 0x03F75 0x03F74 x00C7 9 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Set the P1OMDS flag of the port 1 output mode register P1OMD to 1 the NBUZSEL flag to 1 to set P13 as the special function pin Set the P1DIRS flag of the port 1 direction control register P1DIR to 1 to set the output mode Chapter 4 Ports 3 Set the TM7PWM flag of the timer 7 mode register 2 TM7MD2 to 0 to select the timer pulse output 4 Set the TM7BCR flag of the TM7MD2 register to 1 to select the compare match as the binary counter clear Source 5 Set the TM7CL flag of the TM7MD1 register to 0 to enable the pulse output 6 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing as the clock source by the 7 51 to 0 flag 7 Set IGBT timer startup factor to timer 7 count operation 8 Set 1 2 of the timer pulse output cycle to the timer 7 preset register 1 TM7PR1 To set 50 kHz by dividing 10 set as 200 1 199 0xC7 At the same time the same value is loaded to the timer 7 compare register 1 TM7BC and the timer 7 binary counter TM7BO is initialized to
216. 1 Operate the count 2 Clock source selection TMS3CK1 X00 fosc TMS3CKO X01 TM3PSC Prescaler output 010 Synchronous fx 110 input 111 Synchronous TMSIO input Control Registers V 17 Chapter 5 8 bit Timers Port 1 Output Mode Register P1OMD 0x03F1C 18 7 6 5 4 3 2 1 0 P1OMD7 P1OMD6 P1OMD5 P1OMD4 P1OMD3 NBUZSEL P1OMD2 BUZSEL 0 0 0 0 0 0 0 0 P1OMD7 R W Description I O port TM2OB selection 0 l O port 1 TM20B P1OMD6 port TM2IO selection 0 port 1 TM2IO P1OMD5 port TMOOB selection 0 port 1 TMOOB P1OMD4 port TMOIO RMOUT selection 0 l O port 1 TMOIO RMOUT P1OMD3 I O port TM7IO selection 0 l O port 1 TM7IO NBUZSEL port NBUZZER selection 0 l O port 1 NBUZZER P1OMD2 port TM8IO selection 0 l O port 1 TM8IO BUZSEL Control Registers port BUZZER selection 0 l O port 1 BUZZER Chapter 5 8 bit Timers 5 3 Prescaler 5 3 1 Prescaler Operation Prescaler Operation Prescaler 0 to 1 Prescaler 0 prescaler 1 are each free run counter of 7 bits 3 bits and output the dividing clock of the reference clock This count up operation starts automatically when any TMnEN flags of 8 bit timer are set to 1 and ate the timer n counting Also it stops automatically when all TMnEN flags
217. 10 1 sie ae atid tere ein akin X 2 10 1 2 Block Diagrama Renee RR RENI D ee 3 10 2 Control Register eot dep Rennen pem eerte er tot ene er niente ier eerte enn X 4 10 2 ec aide let e erede X 4 10 2 2 Oscillation Stabilization Wait Time Control Register DLYCTR X 5 10 3 Operation v de hu u q s Ee a tbe ea X 6 Contents 7 19 31 Op ration terea dee PU ENTERO DUREE X 6 10 3 2 Setup Example us nm huu ashuan Sate iota ee tatc 7 Chapter T1 Serial interface Diss coe Bett ed Rer Door 1 ENS MIDI M XI 2 LETT ee Se oa eee as a A 2 52 679 lt ia 4 1H 2 Control Registers neto et ER ati aia bed XI 5 112 1 Registers asna pan DEPO EORR D REO e DO XI 5 11 2 2 Data Buffer Registers ter e ce ete ene e eee deae be a bh pas eA 6 11 23 Mode een ae ti dpi t XI 7 113 Operation ined te ATE bei A t XI 13 11 3 1 Clock Synchronous Serial Interface a XI 13 11 3 2 Exam ples rt e eoe rede
218. 12 Setup Example eire erepti er aen eet ote ien nee toc ee go VI 76 6 12 16 bit Timer Cascade oce eee ie epe ERU Leiter ser VI 79 6 12 Operations dre DERI dE RE dece VI 79 6 12 2 Setup Example Timer VI 81 6 12 3 Setup Example PWM VI 83 Chapter 7 Time Timer Free running Timer efe tee de 1 Rem 2 2 2 Block Diagram zer qaq VII 4 7 2 Control Registers oos egent tero gene la eden VII 5 1 2 1 Control Registers EU edere eC eiie Bela uto eel iat VII 5 7 2 2 Programmable Timer Registers isisisi eiseres kerri sess e iba kes sestese VII 6 7 2 3 Timer 6 Enable Registersa a s s on a 7 7 24 Timer Mode e pelos rt pee e dpi de VII 8 Contents 6 gt 7 3 8 bit Free running Timer eite eer Re a terere n e pei e Peer VII 9 7 3 Operation aspa Sumu athe ha MO ect oes mee VII 9 7 3 2 Setup Exarnple esteem onn eH epe aere 13 TA Ime Base Timer ease Maat nit VII 15 TA Operation 5 Bie ba eae EBM HIERBA VII 15 T A Setup Example itte ti ede e ene pa etes 17 Chapter 8 Remote Control Carrier Functions
219. 12 Block iti te tile ene eee i e rte eei rented 4 52 s oue eed erbe Seele denial ees 7 S 21 ee Re Ep 7 Contents 4 gt 5 2 2 Timer Prescaler Registers eee nece e 9 5 2 3 Programmable Timer Registers V 12 5 2 4 Timer Mode Registers eunte ree e rnt V 14 9 3 uie aeo ch BOR be er t t ede HER po s V 19 5 91 Prescaler Operation cis aene E RE i ele a V 19 3 32 Set p Example eget ei ed gu ee pt enn ees V 20 TIMET 21 5 4 1 8 bit Timer Operation 21 542 Setup Example ce 24 5 5 8 bit Event Count eec bei e obi pe V 26 5 5 J Operation s u s uu uuu vede ei upto pH eet eem V 26 5 3 2 Setup Example e dete a ie ad Rk dacs V 29 516 8 bit Timer Pulse Output iere skies cti cases bee 31 31 2 6 2 Example ende Ie et 32 5 7 S bit PWM eee Pete ep A q T ae ie ashe V 34 91 eats 34 5 7 2 PWM Output with Additional Pulse n ener nennen V 37 573 Setup Example eoe eR Sm amer e V 39 5 8 Serial Transfer Clock Output 5 tiet terere Te EH
220. 2 B Pins Setup with 2 channels at transmission Table 11 3 10 shows the setup for synchronous serial interface pin with 2 channels SBOO pin SBTO pin at trans mission SBIO pin can be used as a port Table 11 3 10 Setup for Synchronous Serial Interface Pin with 2 channels at transmission PAPLU PAPLUO P7PLU P7PLUS5 Setup item Data output pin Serial unused pin Clock I O pin SBOOA pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin PAO P75 PA1 P76 PA2 P77 Port setup Select pin A B SCSEL SCOSL Serial data input SBOO selection SCOMD1 SCOIOM Function Serial data input 1 input Transfer clock I O Transfer clock I O SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBIS Style Push pull N ch open Push pull N ch open Push pull N ch open drain drain drain PAODC PAODC2 P7ODC P7ODC5 P7ODC P7ODC7 Input mode PADIR PADIRO PADIR PADIR2 P7DIR PADIRS5 P7DIR P7DIR7 Pull up setup Added Not added Added Not added Added Not added PAPLU PAPLU2 P7PLU P7PLU7 Operation B Pins Setup with 2 channels at reception Chapter 11 Serial interface 0 Table 11 3 11 shows the setup for synchronous serial interface pin with 2 channels SBOO pin SBTO pin at reception SBIO pin can be use
221. 2 1 1 Serial interface 1 Block Diagram Figure Overview XII 4 12 2 Control Registers 12 2 4 Registers Table 12 2 1 shows registers to control serial interface 1 Table 12 2 1 Serial interface 1 Control Registers Function Chapter 12 Serial interface 1 Serial interface 1 mode register 0 Serial interface 1 mode register 1 Serial interface 1 mode register 2 Serial interface 1 mode register 3 Serial interface 1 status register Serial interface 1 received data buffer Serial interface 1 transmission data buffer Serial interface I O pins switching control register Port 1 Nch open drain control register Port 1 direction control register Port 1 pull up pull down control register Register Address SC1MDO 0x03F99 SC1MD1 SC1MD2 0x03F9B SC1MD3 OxO3F9C SC1STR 0x03F9D RXBUF1 TXBUF1 SCSEL 0x03F90 P10DC 0x03F1B P1DIR 0x03F31 P1PLUD 0 03 41 SC1RICR Ox03FF1 SC1TICR OxO3FF2 R W Readable Writable R Readable only Serial 1 UART reception interrupt control register Serial 1 UART transmission interrupt control register Control Registers XII 5 Chapter 12 Serial interface 1 12 2 2 Data Buffer Registers Serial interface 1 has one each of 8 bit data buffer register for transmission and for reception Serial interface 1 Reception Data Buffer RXBUF1 0x03F9E 7 6 5
222. 2 24 12 2 3 figures COMO to COM1 to bit4 to bit5 1 3 36 12 3 4 figures COMO to 2 bitO to bit2 bit4 to bit6 1 4 48 12 4 6 figures COMO to to bit3 bit4 to bit7 16 1 4 Switching I O ports and LCD segment pins NS EEE Switching of general port and LCD segment is controlled by the LCD output control register 1 2 LCCTRI LCCTR2 Chapter 16 16 2 Control Registers Port 7 1 SEGO to SEG11 are switchable to I O port in 1 bit unit Port 3 COMO to COMO is switchable to I O port in 1 bit unit 16 1 5 Switching Ports and LCD Voltage s Switching of general ports P34 to P36 and LCD voltage ca to Vr c are controlled by the LCD control register3 LCDMD2 16 2 Control Registers Only when the LCD functions are unused general ports P34 to P36 are available When general ports P34 to P36 are used set the VLC3SL to VLCISL flags of the LCD control register 3 LCCTR3 to 0 and select P34 to P36 Functions Chapter 16 LCD 16 1 6 Block Diagram HNOO 8 09 SSA 0935 1935 1193 11A ENA zt esed JeAuq 1 tawaoi
223. 2 3 16 shows its types to be set Table 12 3 16 UART Serial Interface Transmission Reception Data Start bit 1 bit Character bit 7 8 bit Parity bit fixed to 0 fixed to 1 odd even none Stop bit 1 2 bits 5 to 0 flag of the SCIMD2 register sets the frame mode Table 12 3 17 shows the UART serial inter face frame mode settings If the SCICMD flag of the SCIMDI register is set to 1 and UART communication is selected the transfer bit count on the SCILNG2 to 0 flag of the SCIMDO register is no longer valid Table 12 3 17 UART Serial Interface Frame Mode SC1MD2 register Frame mode SC1FM1 SC1FMO 0 0 Character bit 7 bits Stop bit 1 bit 0 1 Character bit 7 bits Stop bit 2 bits 1 0 Character bit 8 bits Stop bit 1 bit 1 1 Character bit 8 bits Stop bit 2 bits XII 44 Operation Chapter 12 Serial interface 1 Parity bit is to detect wrong bits with transmission reception data Table 12 3 18 shows types of parity bit The SCINPE SCIPMI to 0 flag of the SCIMD2 register set parity bit Table 12 3 18 Parity Bit of UART Serial Interface SC1MD2 Parity bit Setup SC1PM1 SC1PMO 0 0 0 Fixed to 0 Set parity bit to 0 0 0 1 Fixed to 1 Set parity bit to 1 0 1 0 Odd parity Control that the total of 1 of parity bit and character bit should be odd 0 1 1 Even parity Control that the total of 1 of parity bit and ch
224. 26 Hz 163 Hz OSCi 27 1 2 duty 2441 Hz 1551 Hz 1953 Hz Hz 9 7 Hz Hz 488 Hz 244 Hz 11 static 2441 Hz 1953 Hz 977 Hz 488 Hz bo 1 4 duty 305 Hz 244 Hz 122 Hz 61 Hz 0010 b1 1 3 duty 407 Hz 326 Hz 163 Hz 81 Hz 08 1 218 0 1 2 duty 1221 Hz Ferg Hz 9 7 HZ 488 Hz 244 Hz 122 Hz 11 static 1221 Hz 977 Hz 488 Hz 244 Hz bo 1 4 duty 153 Hz 122 Hz 61Hz 31 Hz 0011 D1 1 3 duty 203 Hz 163 Hz 81 Hz 41 Hz 08 1 24 0 1 2 duty 810 Hz 205 Hz 48842 244 Hz 12242 61Hz 11 static 610 Hz 488 Hz 244 Hz 122 Hz po 1 4 duty 76Hz 61 Hz 31 Hz 15 Hz 0100 01 1 3 duty 102 Hz 81 Hz 41 Hz 20 Hz 0 1 2 5 0 1 2 duty 305 Hz Tea 24442 12242 gaz 9112 11 static 305 Hz 244 Hz 122 Hz 61 Hz bo 1 4 duty 38 Hz 31 Hz 15 Hz 8 Hz 0101 D1 1 3 duty 51 Hz 41 Hz 20 Hz 10 Hz 08 1 2 0 1 2 duty 193 Hz 7 122Hz oraz 9182 31 15g 11 static 153Hz 122Hz 61Hz 31Hz po 1 4 duty 19Hz 15Hz 8Hz 4 Hz 0110 D1 1 3 duty 25 Hz 20 Hz 10 Hz 5 Hz OSCi 2 HO 1 2 duty 76 2 9182 31H2 198 gp 11 static 76 Hz 61 Hz 31 Hz 15 Hz 00 1 4 duty 10Hz 8Hz 4Hz 2Hz 0111 01 1 3 duty 13Hz 10Hz 5Hz 3Hz OSC1 218 1 2 duty 31Hz ee anz GET 11 static 38Hz 31Hz 15Hz 8Hz 00 1 4 duty 128Hz 1X00 1 3 duty 171Hz 26 HO 1 2 duty 512 Hz 556 Hz 11 static 512
225. 3 SBI3 pin SBT3 pin Table 13 3 6 Synchronous Serial Interface Pins Setup 3 channels at transmission Item Data output pin Data input pin Clock pin 5803 pin 5 pin SBT3 pin Clock master Clock slave Port Pin P33 P31 P32 Serial data input SBI3 selection SC3MD1 SC3IOM Function Serial data output 1 input Serial clock I O Serial clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBTS Type Push pull N ch open Push pull N ch open Push pull N ch open drain drain drain P30DC P30DC3 P30DC P30DC2 Output mode Input mode P3DIR P3DIR3 P3DIR P3DIR2 Pull up added not added added not added added not added P3PLU P3PLU3 P3PLU P3PLU2 Pins Setup 3 channels at reception Table 13 3 7 shows the pins setup at synchronous serial interface reception with 3 channels SBO3 pin SBI3 pin SBT3 pin Table 13 3 7 Synchronous Serial Interface Pins Setup 3 channels at reception Item Data output pin Data input pin Clock pin SBOS pin 5813 pin SBT3 Clock master Clock slave Port Pin P33 P31 P32 Serial data input SBI3 selection SC3MD1 SC3IOM Function Port Serial data input Serial clock I O Serial clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBTS Type Push pull N ch open Push pull N ch open drain drain
226. 3 Interrupts 3 2 2 Interrupt Control Registers Ba saw The interrupt control registers include the non maskable interrupt control register NMICTR the external inter rupt control register and the internal interrupt control registers Non maskable Interrupt Control Register NMICR 0x03FE1 The non maskable interrupt control register NMICTR is stored the non maskable interrupt request When the non maskable interrupt request is generated the interrupt is accepted regardless of the interrupt mask level IMn of PSW The hardware then branches program to the address stored at location 0x04004 in the interrupt vector table The watchdog timer overflow interrupt request flag WDIR is set to 1 when the watchdog timer over flows The program interrupt request flag PIR is set to 1 when the undefined instruction is executed Setting PIR or WDIR flag to be 1 enable non maskable interrupt request to be set compulsory Table 3 2 2 Non maskable Interrupt Control Register NMICR 0x03FE1 bp 2 1 0 Flag IRQNPG IRQNWDG Reserved At reset 0 0 0 Access Description IRQNPG Program interrupt request flag 0 No interrupt request 1 Interrupt request generated IRQNWDG Watchdog interrupt request flag 0 No interrupt request 1 Interrupt request generated Reserved Set always to 0 interrupt at the same time of the setting of the program interrup
227. 3 Interrupts 3 3 8 AC Zero Cross Detector s s A This LSI has AC zero cross detector circuit The P54 ACZO and P55 ACZI pins are the input pins of AC zero cross detector circuit AC zero cross detector circuit output the high level when the input level is at the middle and outputs the low level at other level AC Zero Cross Detector External interrupt 0 and 1 AC zero cross detector set the IRQI pin to the high level when the input signal P54 70 55 71 pins is at intermediate range by AC zero cross detector circuit At the other level pin set to the low level AC Zero cross detector is set by setting the P55IM flag of the noise filter control register NFCTR to 1 Also it is possible to recover from the standby mode approx 10 ms at 50 Hz approx 8 3 ms at 60 Hz AC line waveform lt Ideal i IRQ1 Actual IRQI Point Point B Figure 3 3 6 AC Line Waveform and IRQ1 Generation Timing Actual IRQI interrupt request is generated several times at crossing the AC line waveform and the intermediate level point A and B So the filtering operation by the program is needed The interrupt request is generated at the rising edge of the AC zero cross detector signal The interrupt request is output at H level of the AC zero cr
228. 300 33 963 13 2338 8 00 fosc 207 2404 103 4808 fosc 4 129 962 103 1202 51 2404 25 4808 fosc 16 103 300 25 1202 12 2404 fosc 32 51 300 12 1202 fosc 64 25 300 fs 2 129 962 103 1202 51 2404 25 4808 fs 4 207 300 64 962 51 1202 25 2404 12 4808 8 38 fosc 217 2403 108 4805 fosc 4 135 963 108 1201 fosc 16 108 300 33 963 13 2338 fosc 32 16 963 6 2338 fosc 64 fs 2 135 963 108 1201 fs 4 217 300 67 963 10 00 fosc 129 4808 fosc 4 162 959 129 1202 64 2404 fosc 16 129 300 fosc 32 64 300 fosc 64 fs 2 162 959 129 1202 64 2404 fs 4 64 1202 Operation XII 51 Chapter 12 Serial interface 1 XII 52 Table 12 3 22 Setup Value of Serial Interface Transfer Speed 2 When Setting UART Inter Clock to Divided by 8 decimal Transfer speed bit s fosc MHz Clock source Timer 300 960 1200 2400 4800 Set value Calculate d value Set value Calculate d value Set value Calculate d value Set value Calculate d value Set value Calculate d value 2 00 fosc 12 9615 3 31250 fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 4 00 fosc fosc 4 fosc 16
229. 3DIR4 P3DIR3 P3DIR2 P3DIR1 P3DIRO mode selection 0 Input mode 1 Output mode Port 3 IV 27 Chapter 4 Ports Port 3 Pull up Resistor Control Register P83PLU 0x03F43 PSPLUD7 P3PLUD6 P3PLUD5 P3PLUD4 P3PLUD3 P3PLUD2 P3PLUD1 PSPLUDO 1 0 0 0 0 0 0 0 O Q O IV 28 Port 3 PSPLUD7 P3PLUD6 P3PLUD5 P3PLUD4 P3PLUD3 P3PLUD2 P3PLUD1 PSPLUDO Description Pull up pull down resistor selection 0 Not added 1 Added Chapter 4 Ports Pull up pull down Resistor Selection Register SELUD 0x03F4B Port A Pull up pull down selection 0 Pull up 1 Pull downd Port 3 Pull up pull down selection 0 Pull up 1 Pull downd Port 9 Pull up pull down selection 0 Pull up 1 Pull downd Port 7 Pull up pull down selection 0 Pull up 1 Pull downd Port 1 Pull up pull down selection 0 Pull up 1 Pull downd Port 3 IV 29 Chapter 4 Ports Port 3 Nch Open drain Control Register P3ODC 0x03F3B P3SODC P320DC 0 0 O Q O IV 30 Port 3 P3SODC P320DC Description Nch open drain output selection 0 Push pull output 1 Nch open drain output Chapter 4 Ports LCD output Control Register LECCTR1 X 3FC2 R W LC1SL3 LC1SL2 LC1SL1 LC1SLO COMSL3
230. 3MD1 SC3SBIS SC3MD1 SC3SBIS Type Push pull N ch open Push pull N ch open drain drain P30DC P30DC2 Input mode Output mode Input mode P3DIR P3DIR3 P3DIR P3DIR2 Pull up added not added added not added P3PLU P3PLU2 Operation XIII 27 Chapter 13 Serial Interface 3 13 3 2 Setup Example B Transmission Reception Setup Example The setup example for clock synchronous serial communication with serial 3 is shown Table 13 3 11 shows the conditions at transmission reception Table 13 3 11 Conditions for Synchronous Serial Interface at transmission reception Item set to Serial data input pin 5813 3 channels Transfer bit count 8 bits Start condition Disabled First transfer bit MSB Input edge Falling Output edge Rising Clock Clock master Clock source fs 2 SBT3 SB03 pin type N ch open drain SBTS pull up resistor Added 5803 pull up resistor Added Serial interface 3 communication end Enabled interrupt An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation 1 Set the SC3PSCE flag of the SC3MD3 register to 1 to SC3MD3 0x03FA2 select prescaler operation bp3 SC3PSCE 1 2 Select the clock source 2 Set the SC3PSC2 0 flag of the SC3MD3 register to SC3MD3 0x03FA2 100 to select fs 2 for clock source bp2 0 SC3PSC2 0 100 3 Cont
231. 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 10 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 Operation XI 58 Chapter 11 Serial interface 0 Table 11 3 23 Setup Value of Serial Interface Transfer Speed 1 When Setting UART Inter Clock to Divided by 16 decimal Transfer speed bit s 300 960 1200 2400 4800 fosc source MHz Timer Set value Calculate Set value Calculate Set value Calculate Set value Calculate Set value Calculate d value d value d value d value d value 2 00 fosc 64 962 51 1202 25 2404 12 4808 fosc 4 51 300 12 1202 fosc 16 12 300 fosc 32 fosc 64 fs 2 51 300 12 1202 fs 4 25 300 4 00 fosc 129 962 103 1202 51 2404 25 4808 fosc 4 103 300 25 1202 12 2404 fosc 16 25 300 fosc 32 12 300 fosc 64 fs 2 103 300 25 1202 12 2404 fs 4 51 300 12 1202 4 19 fosc 135 963 108 1201 54 2381 fosc 4 108 300 33 963 fosc 16 fosc 32 fosc 64 fs 2 108 300 33 963 fs 4 54 298 16 9
232. 4 3 2 1 0 RXBUF17 RXBUF16 RXBUF15 RXBUF14 RXBUF13 RXBUF12 RXBUF 11 RXBUF10 Access Serial interface 1 Transmission Data Buffer TXBUF1 0x03F9F 7 6 5 4 3 2 1 0 TXBUF17 TXBUF16 TXBUF15 TXBUF 14 TXBUF13 TXBUF12 TXBUF11 TXBUF10 X X X X X X X X XII 6 Control Registers Chapter 12 Serial interface 1 12 2 3 Mode Registers Serial interface 1 Mode Register 0 SC1MD0 0x03F99 bp 7 6 5 4 3 2 1 0 Flag SC1CE1 SC1DIR SC1STE SC1LNG2 SC1LNG1 SC1LNGO 0 5 0 0 1 1 1 Reset Access R W R W R W R W R W R W bp Flag Description Transmission data output edge 1 Reception data input edge O rising 1 falling SC1CE1 First bit to be transferred SC1DIR 0 MSB first 1 LSB first Start condition selection 5 15 0 Disabled 1 Enabled Transfer bit 000 1bit 001 2bit SC1LNG2 010 3bit SC1LNG1 011 4bit SC1LNGO 100 5bit 101 6bit 110 7bit 111 8bit Control Registers XII 7 Chapter 12 Serial interface 1 Serial interface 1 Mode Register 1 SC1MD1 0x03F9A bp 7 6 5 4 3 2 1 0 Flag SC1IOM SC1SBO 5 15 5 SC1SBIS SC1CKM SC1MST SCIDIV SC1CMD Reset 0 0 0 0 0 0 0 Access SC1IOM
233. 4808 8 38 fosc 217 2403 108 4805 fosc 4 135 963 108 1201 fosc 16 108 300 33 963 13 2338 fosc 32 16 963 6 2338 fosc 64 fs 2 135 963 108 1201 fs 4 217 300 67 963 10 00 fosc 129 4808 fosc 4 162 959 129 1202 64 2404 fosc 16 129 300 fosc 32 64 300 fosc 64 fs 2 162 959 129 1202 64 2404 fs 4 64 1202 Operation Chapter 11 Serial interface 0 Table 11 3 22 Setup Value of Serial Interface Transfer Speed 2 When Setting UART Inter Clock to Divided by 8 decimal Transfer speed bit s fosc MHz Clock source Timer 300 960 1200 2400 4800 Set value Calculate d value Set value Calculate d value Set value Calculate d value Set value Calculate d value Set value Calculate d value 2 00 fosc 12 9615 3 31250 fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 4 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 4 19 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 8 00 fosc 51 9615 31250 fosc 4 12 9615 31250 fosc 16 fosc 32 fosc 64 fs 2 12 9615 31250 fs 4 31250 8 38 fosc 54 9523 fosc
234. 5 PA5 P16 PA4 P17 PA6 Port pin setup Select used pin A B SCSEL SC1SL Serial data input SBO1 selection SC1MD1 SC11OM Function Port Serial input Transfer clock I O Transfer clock I O SC1MD1 SC1SBO SC1MD1 SC1SBIS SC1MD1 SC1SBIS S Style Push pull Nch open Push pull Nch open drain drain P1ODC P1ODC7 PAODC PAODC6 Input mode Output mode Input mode P1DIR P1DIR5 P1DIR P1DIR7 PADIR PADIR6 PADIR PADIR5 Pull up setup Added Not added Added Not added P1PLUD P1PLUD7 PAPLU PAPLU6 Operation 12 3 2 Setup Example B Transmission Reception Setup Example The setup example for clock synchronous serial communication with serial 1 is shown Table 12 3 12 shows the conditions at transmission reception Chapter 12 Serial interface 1 Table 12 3 12 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item Set to Serial data input pin Select SBI1 3 channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Output edge Rising edge Clock Clock master Clock source fs 2 Clock source dividing Not divided Used pin A port 1 SBT1 SBO pin style Nch open drain 5871 pin pull up resistor Added SBO pin pull up resistor Added serial 1 communication complete interrupt Enable 5801 output after last data output 1 H fix An example setup procedure with a
235. 6 5 4 2 1 0 2 7 TM20C6 TM20C5 TM20C4 20 2 2 1 20 0 X X X X X X X Timer 3 Compare Register TM30C 0x03F5B 7 6 5 4 2 1 0 7 TM3OC6 TM3OC5 TM3OC4 TM3OC2 TM3OC1 TM3OC0 X X X X X X X V 12 Control Registers Chapter 5 8 bit Timers Binary counter is 8 bit up counter If any data is written to compare register the counting is stopped and binary counter is cleared to Ox00 Timer 0 Binary Counter TMOBC 0x03F50 7 6 5 4 3 2 1 0 TMOBC7 TMOBC6 TMOBC5 TMOBC4 TMOBC3 TMOBC2 TMOBC1 TMOBCO 0 0 0 0 0 0 0 0 R 7 R 6 R Timer 1 Binary Counter TM1BC 0x03F51 5 R 4 R 3 R 2 R 1 R 0 TM1BC7 TM1BC6 TM1BC5 TM1BC4 TM1BC3 TM1BC2 TM1BC1 TM1BCO 0 0 0 0 0 0 0 0 R 7 R 6 R Timer 2 Binary Counter TM2BC 0x03F58 5 R 4 R 3 R 2 R 1 R 0 TM2BC7 TM2BC6 TM2BC5 TM2BC4 TM2BC3 TM2BC2 TM2BC1 TM2BCO 0 0 0 0 0 0 0 0 R 7 R 6 R Timer 3 Binary Counter TM3BC 0x03F59 5 R 4
236. 6 5 4 3 2 1 Chapter 13 Serial Interface 3 0 Flag TXBUF37 TXBUF36 TXBUFS5 TXBUF34 TXBUF33 TXBUF32 1 TXBUF30 At reset Access 13 2 3 Data Register Serial interface 3 has 8 bit serial data register Serial Interface 3 Transmission Reception Shift Register SC3TRB 0x03FA4 bp 7 6 5 4 3 2 1 0 Flag SC3TRB7 SC3TRB6 SC3TRB5 SC3TRB4 SC3TRB3 SC3TRB2 SC3TRB1 SC3TRBO At reset Access Control Registers XIII 5 Chapter 13 Serial Interface 3 13 2 4 Serial interface 3 Mode Register Serial Interface Mode Register 0 SC3MDO 0x03FA0 bp 7 6 4 3 2 1 0 Flag SC3BSY SC3CE1 SC3DIR SC3STE SC3LNG2 SC3LNG1 SC3LNGO At reset 0 0 0 0 1 1 1 Access R R W R W R W R W R W R W Description Serial bus status in clock synchronous communication 0 Other use 1 Serial transnission is in progress SC3BSY Transmission data output edge Reception data input edge 0 Falling Rising 1 Rising Falling SC3CE1 First bit to be transferred 0 MSB first 1 LSB first SC3DIR Start condition 0 Disable start condition 1 Enable start condition 5 35 Transfer bit count 000 1 bit 001 2 bit SC3LNG2 SC3LNG1 SC3LNGO 6 Control Registers 010 3 bit 011 4 bit 100 5 bit 101 6 bi
237. 63 8 00 fosc 207 1202 103 2404 51 4808 fosc 4 207 300 64 962 51 1202 25 2404 12 4808 fosc 16 51 300 12 1202 fosc 32 25 300 fosc 64 12 300 fs 2 207 300 64 962 51 1202 25 2404 12 4808 fs 4 103 300 25 1202 12 2404 8 38 fosc 217 1201 108 2403 54 4761 fosc 4 217 300 67 963 54 1190 fosc 16 54 298 16 963 fosc 32 fosc 64 fs 2 217 300 67 963 54 1190 fs 4 108 300 33 963 10 00 fosc 129 2404 64 4808 fosc 4 80 965 64 1202 fosc 16 64 300 fosc 32 fosc 64 fs 2 80 965 64 1202 fs 4 129 300 XI 54 Operation Chapter 11 Serial interface 0 Table 11 3 24 Setup Value of Serial Interface Transfer Speed 2 When Setting UART Inter Clock to Divided by 16 decimal Transfer speed bit s fosc MHz Clock source Timer 300 960 1200 2400 4800 Set value Calculate d value Set value Calculate d value Set value Calculate d value Set value Calculate d value Set value Calculate d value 2 00 fosc 1 31250 fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 4 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 4 19 fosc fosc 4 fosc 16
238. 7 PAPLU PAPLUS Operation Pins Setup with 3 channels at reception Chapter 12 Serial interface 1 Table 12 3 8 shows the setup for synchronous serial interface pin with channels 5 pin SBII pin SBTI pin at reception Table 12 3 8 Setup for Synchronous Serial Interface Pin with 3 channels at reception Setup item Data output pin Data input pin Clock pin SBO1A pin SBO1B pin SBI1B pin SBT1A pin SBT1B pin Clock master Clock slave SC1SCMD1 SC1MST Port pin 15 16 17 Port setup Select used pin A B SCSEL SC1SL Serial data input SBI1 selection SC1MD1 SC1IOM Function Port Serial input Transfer clock I O Transfer clock I O SC1MD1 SC1SBOS SC1MD1 SC1SBIS SC1MD1 SC1SBTS Style Push pull Nch open Push pull Nch open drain drain P1ODC P1ODC7 PAODC PAODC6 y o Input mode Output mode Input mode P1DIR P1DIR6 P1DIR P1DIR7 PADIR PADIR6 PADIR PADIR4 Pull up setup Added Not added Added Not added P1PLUD P1PLUD7 PAPLU PAPLU6 Operation XII 29 Chapter 12 Serial interface 1 XII 30 Pins Setup with 3 channels at transmission reception Table 12 3 9 shows the setup for synchronous serial interface pin with channels 5 pin SBII pin SBTI pin at transmission reception Table 12 3 9 Setup for Synchronous Serial Interfa
239. 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ANCTR1 ANSHS2 ANSHS1 ANSHSO XV 6 0 0 0 Analog input channel ANCTR2 ANST ANSTSE Reserve XV 6 D L1 d 0 0 0 A D con A D con Set version version always status starting to 0 factor selection ANBUFO ANBUFO ANBUFO XV 7 E 7 6 x x x A D conversion data storage buffer 0 ANBUF1 ANBUF1 ANBUF1 ANBUF1 ANBUF1 ANBUF1 ANBUF1 ANBUF1 ANBUF1 XV 7 F 7 6 5 4 3 2 1 0 x x x x x x x x A D conversion data storage buffer 1 OxO3FE1 NMICR IRQNPG IRONW Reserve 19 d 0 0 0 Program Watch Set interrupt dog always request interrupt to 0 request Ox03FE2 IRQOICR IRQOLV1 IRQOLVO REDGO IRQOIE IRQOIR 20 0 0 0 0 0 Interrupt level specifi Interrupt Interrupt Interrupt cation flag valid enable request edge flag flag specifi cation flag OxOSFES IRQ1ICR IRQ1LV1 IRQ1LVO REDGO IRQ1IE IRQ1IR 21 0 0 0 0 0 Interrupt level specifi Interrupt Interrupt Interrupt cation flag valid enable request edge flag flag specifi cation flag XVII 24 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bi
240. 7BCR 1 bp6 T7PWMSL 1 3 Select IGBT timer startup factor TM7MD3 x 3F8E bp1 0 TM7IGBT1 0 01 4 Select the interrupt generation valid edge TM7MD3 x 3F8E bp4 T7IGBTTR 0 5 Set the dead time edge TM7MD3 x 3F8E bp3 T7IGBTDT 0 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Set the TM7BCR flag of the TM7MD2 register to 1 to select the TM7OC1 compare register match as the binary counter clear source Also set the T7PWMSL flag to 1 to select the TM7OC2 compare match as the duty decision source of the IGBT output 3 Select the external interrupt 0 IRQO input as the IGBT timer startup factor by the T7IGBT1 to 0 flag of the TM7MDS register 4 Set the T7IGBTTR flag of the TM7MDS register to 1 to select the rising edge as the interrupt generation valid edge 5 Set the T7IGBTDT flag of the timer 7 mode register 3 7 to 0 to select the falling standard as the dead time edge Dead Time IGBT Output 16 Chapter 6 bit Timers Setup Procedure Description 6 Set the interrupt level IRQOICR x 3FE2 bp7 6 IRQOLV1 0 10 7 Enable the interrupt IRQOICR x 3FE2 bp1 IRQ1IE 1 8 Select the count clock source TM7MD 1 x 3F78 bp1 0 TM7CK1 0 200 bp3 2 TM7PS1 0 00 9 Set the IGBT output cycle TM7PR1 x 3F75 x 3F74 2x 9C3F bp2 T7ICEN 1 10 Set H period of
241. 8IO outputs again and TM7BCL TM7BCH TM8BCL TM8BCH counts up from X 00000000 again In the initial state of the PWM output L output is changed to H output as the PWM output is selected by the TM7PWM flag of the TM7MD2 register Set value should be set as a TM7OC2L TM7OC2H TM8OC2L TM8OC2H lt TM7OCIL 7 TM8OC1L TM8OC1H If it is set as TM7OC2L TM7OC2H TM8OC2L TM8OC2H gt TM7OC1L TM7OC1H TM8OC1L TM80C1H the PWM output is a H fixed output 16 bit Timer Cascade Connection Chapter 7 Time Base Timer Free running Timer Chapter 7 Time Base Timer Free running Timer 71 Overview This LSI has a time base timer and a 8 bit free running timer timer 6 Time base timer is a 15 bit timer counter 7 1 1 Functions Table 7 1 1 shows the clock source and the interrupt generation cycle that timer 6 and time base timer 7 can use Table 7 1 1 Clock Source and Generation Cycle fosc x 1 219 fosc x 1 213 fosc x 1 215 fx x 1 27 fx x 1 28 fx x 1 29 fx x 1 210 fx x 1 213 fx x 1 215 Time base timer Hus 8 bit free running 8 bit timer operation x O Interrupt TBIRQ TM6IRQ Clock source fosc fosc fx fx fs fosc X 1 27 1 fosc x 1 213 41 fx X 1 27 2 fx x 1 213 2 Interrupt generation fosc X 1 27 The interrupt generation cycle fosc X 1 28 cycle is decided by the arbitrary value written to fosc 1 29 TM6OC fosc Machine cl
242. 920 Mexico Tel 52 3 671 1205 9 Brazil Sales Office Panasonic do Brasil Ltda PANABRAS Caixa Postal 1641 Sao Jose dos Campos Estado de Sao Paulo Brasil Fax 52 5 488 1073 Fax 52 3 671 1256 Tel 55 12 3935 9000 55 12 3931 3789 EUROPE Europe Sales Office Panasonic Industrial Europe GmbH Germany Sales Office Hans Pinsel Strasse 2 85540 Haar Germany Tel 49 89 46159 119 49 89 46159 195 PIE ASIA Singapore Sales Office Panasonic Semiconductor of South Asia PSSA 300 Beach Road 16 01 the Concourse Singapore 199555 the Republic of Singapore Tel 65 6390 3688 Malaysia Sales Office Panasonic Industrial Company M Sdn Bhd Head Office 15th Floor Menara IGB Mid Valley City Lingkaran Syed Putra 59200 Kuala Lumpur Malaysia Tel 60 3 2297 6888 Fax 60 6 2284 6898 Penang Office Suite 20 07 20th Floor MWE Plaza No 8 Lebuh Farquhar 10200 Penang Malaysia Tel 60 4 201 5113 Johore Sales Office Menara Pelangi Suite8 3A Level8 No 2 Jalan Kuning Taman Pelangi 80400 Johor Bahru Johor Malaysia Tel 60 7 331 3822 Fax 60 7 355 3996 Thailand Sales Office Panasonic Industrial Thailand Ltd 252 133 Muang Thai Phatra Complex Building 31st Floor Rachadaphisek Road Huaykwang Bangkok 10320 Thailand Tel 66 2 693 3400 to 3421 Fax 66 2 693 3422 to 3427 Philippines Sales Office Panasonic Industrial Sales Philippines PISP 102 Laguna Boulevard Bo Don Jose Laguna Technopark Sant
243. 991 ejeduio eui z 2 151 4 N3ZIALL Figure 6 11 2 Count Timing of Dead Time IGBT One Shot Pulse Output Timer 7 VI 75 Dead Time IGBT Output Chapter 6 16 bit Timers 6 11 2 Setup Example Dead Time IGBT Output Setup Example Timer 7 At the interrupt generation edge of the external interrupt 0 input signal 7 and TMSIO output pins output the waveform of 1 4 duty IGBT waveform at 200 Hz with 0 01 ms 0 02 ms dead time by the falling standard using the timer 7 Select fosc 1 at fosc 8 0 MHz as the clock source Required period for one IGBT output waveform cycle depends on the set value of the compare register 1 period of IGBT output standard waveform depends on the set value of the compare register 2 Dead time period depends on the value of the dead time preset register 1 and 2 An example setup procedure with a description of each step is shown below TM8IO output waveform 0 01 5 0 02 ms IGBT trigger P20 input IGBT waveform TM7IO output i waveform 0 01 ms 0 02 ms 0 01 ms 200 Hz Figure 6 11 3 Output Waveform of TM71O Output Pin and TM8IO Output Pin Setup Procedure Description 1 Stop the counter TM7MD1 x 3F78 bp4 TM7EN 0 2 Set the dead time IGBT output operation TM7MD2 x 3F79 bp5 TM
244. ADDUW 2 gt 3 3 0010 1000 1aDn 8 ADDSW ADDSW Dn Am Am sign Dn Am 3 3 O 0010 1001 taDn SUB SUB DnDm whenDnzDm Dm Dn 5 Dm 3 2 0010 1010 DnDm 508 0 010 1 211 1000 01Dn SUB imm8 Dm Dm imm8 5Dm 3 0010 1010 DmDm lt 8 gt SUBC SUBC Dn Dm Dm Dn CF gt Dm o 3 2 0010 1011 SUBW SUBW DWn DWm DWm DWn DWm 3 0010 0100 000 SUBW DWn Am Am DWn Am 3 0010 0100 10Da SUBW imm16 DWm DWm imm16 5DWm 4 0010 0100 010d lt 16 m SUBW imm16 Am Am imm16 Am 4 0010 0100 011 lt 16 gt MULU MULU Dn Dm Dm Dn DWk 0010 1111 111D 4 DIVU DIVU Dn DWm DWm Dn DWm DWm h 9 0010 1110 111d 5 CMP Dn Dm Dm Dn PSW 3 2 0011 0010 DnDm imm8 Dm Dm imm8 PSW 4 2 1100 00Dm lt 8 gt imma8 abs8 mem8 abs8 imm8 PSW eeee 0000 0100 abs 8 gt lt 8 gt 26512 mem8 abs12 imm8 PSW e eee7 0000 0101 abs 12 gt lt 8 gt imm8 abs16 memB8 abs16 imm8 PSW 9 5 0011 1101 1000 abs 16 gt lt 8 CMPW CMPW DWn DWm DWm DWn PSW 3 3 0010 1000 01Dd 1 CMPW DWn Am Am DWn PSW e eejo 3 0010 0101 11Da CMPW An Am Am An PSW 3 3 0010 0000 01 2 CMPW imm16 DWm DWm imm16 PSW 3 1100 110d lt 16 o C
245. ADICR ADLV1 ADLVO ADIE ADIR III 37 0 0 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag OxOSFF5 SC4ICR SC4LV1 SC4LVO SCAIE SC4IR III 38 0 0 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag OxOSFF6 TM8ICR TM8LV1 TM8LV0 TM8IE TM8IR III 39 0 0 i 5 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag OxOSFF7 T8OC2ICR T8OC2L T8OC2L T8OC2l T8OC2l 40 V1 VO E R 0 0 z 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag Special Function Registers List XVII 27 Chapter 17 Appendix 17 5 Instruction Set MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag Re Machine Code Notes VF NFICF zF Size peat Ex 1 2 3 4 5 6 7 8 9 10 11 Data Move Instructions MOV MOV Dn Dm Dn gt Dm 241 1010 DnDm imm8 Dm imm8 Dm 4 2 1010 DmDm lt 8 gt MOV Dn PSW DnoPSW 3 0010 1001 01Dn MOV PSW Dm PSW gt Dm 3 2 0010 0001 01Dm MOV An Dm 8 gt 2 2 0100 1ADm MOV d8 An Dm 48 0110 1ADm lt d8 gt 4 MOV d16 An Dm mem8 d16 An Dm
246. ADWN R Pull up pull down resistor selection K Re DR K et PAPLUDO R Pull up pull down resistor control Reset PADIRO R direction control K PAO PAOUTO or R x D Port output data K 1 Input mode control Schmitt trigger input v Port input data Analog input Serial 0 reception data input Serial 0 UARTO transmission data output SCOMD1 SCOSBOS Figure 4 8 1 Block Diagram PAO PADWN Pull up pull down resistor selection tpg Y Rese Pull up pull down resistor control 1 pPq PAPLUDI WEK R Rege direction control gt t Bau WEK VR S Pa Port output data D ples CLI E E PAIMD1 Input mode control WEK VR Schmitt trigger input PAIN1 Port input data lt Z i J R Analog input Serial 0 UARTO reception data input Figure 4 8 2 Block Diagram PA1 IV 78 Port A Chapter 4 Ports Reset PAODC2 R Nch open drain control K Reset PADWN R Pull up pull down resistor selection K Reset PAPLUD2 R Pull up pull down resistor control K Reset PADIR2 R direction control K PA2 PAOUT2 o R Port output data 1 Rese
247. AO SBOOA 75 5 SEG2 KEYS P15 TMOOB SBO1B SEG10 AN5 58018 UART transmission data output pins Transmission data output pin for serial inter face 0 1 in UART mode The output configuration either COMS push pull or Nch open drain can be selected at the P1ODC P7ODC PAODC registers Pull up and pull down registers can be selected by the POPLU P1PLUD PAPLU registers Select the output mode at the P1DIR P7DIR PADIR registers and serial data output mode by serial mode register 1 SCOMD1 SC1MD1 These can be used as normal I O pins when the serial interface is not used RXDOA RXDOB RXD1A RXD1B 1 17 39 31 20 17 36 28 Input PA1 SBIOA AN1 P76 SBIOB SEG1 KEY6 P16 TM2IO SBI1A SEG9 PA4 AN4 SBI1B UART reception data input pins Reception data input pin for serial interface 0 1 in UART mode Pull up and pull down registers can be selected by the P1PLUD P7PLUD PAPLU registers Select the input mode at the P1DIR P7DIR PADIR registers and serial input mode by serial mode register 1 SCOMD1 SC1MD1 These can be used as normal I O pins when the serial interface is not used SDA3 SDA4A SDA4B 44 13 39 41 13 36 Output P33 SBBO3 P10 P76 SBIOB RXDOB KEY6 data output pins Data output pin for serial interface 3 4 in IIC mode The output configuration Nch open drain can be selected by P1ODC P3ODC
248. BRA 411 d11 BNE 411 d11 BCS 911 411 MOV Dn Dm MOV 8 Dm BSET abs8 bp BCLR abs8 bp 8 Dm MOVW abs8 Am MOVW abs8 DWm CBEQ 8 Dm d7 CMPW 16 DWm MOVW 16 DWm MOV Dn HA MOVW An abs8 MOVW DWn abs8 CBNE 8 Dm d7 CMPW 16 16 Am MOVW An DWm MOVW d4 SP Am MOVW d4 SP DWm POP Dn ADDW 4 d4 MOVW DWn Am MOVW An d4 SP MOVW DWn d4 SP Extension code b 0010 2ndnible 3rd nibble 0 1 2 3 MOVW An Am CMPW An Am PUSH Dn 8 9 A B MOVW SP Am MOVW An SP ADDW 8 SP ADDW 4 SP JSRV 04 D E F BTST 8 Dm JMP A0 JSR AO JMP A1 JSR A1 MOV PSW Dm REP 3 BGT 7 BLS 07 BNC d7 BNS 47 BVC 47 BVS 47 ROR Dn BGT 911 d11 BLS 911 BNC 411 BNS 911 911 911 ASR Dn LSR Dn SUBW DWn DWm SUBW s16 DWm SUBW 16 Am SUBW DWn Am MOVW DWn Am ADDW DWn DWm ADDW 16 DWm ADDW 16 Am ADDW DWn Am CMPW DWn Am d16 SP Dm d8 SP Dm d16 An Dm Dn d16 SP MOV Dn d8 SP MOV Dn 916 MOVW DWn DWm CMPW DWn DWm ADDUW Dn Am EXT Dn DWm AND 8 PSWI OR 8 PSW MOV Dn PSW ADDSW Dn Am SUB Dn Dm SUB 8 Dm SUBC Dn Dm ab
249. BT1 0 flag of the TM7MDS register 16 bit Standard IGBT Output Only duty can be changed consecutively 16 Chapter 6 bit Timers Setup Procedure Description 6 Select the trigger level TM7MD3 x 3F8E bp4 T7IGBTTR 1 7 Select the dead time TM7MD4 x 3F6E bp3 T7NODED 1 8 Select the count clock source TM7MD1 x 3F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 01 9 Start the timer operation TM7MD1 x 3F78 bp4 TM7EN 1 6 Set the T7IGBTTR flag of the TM7MD3 register to 1 to set the IGBT trigger level to H 7 Set the T7NODED flag of the TM7MD4 register to 1 to select without dead time 8 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing as the count clock source by the TM7PS1 to 0 flag 9 Set the TM7EN flag of the TM7MD1 register to 1 to enable the operation of the timer 7 After H is input to the P54 IGBT is output from the P13 16 bit Standard IGBT Output Only duty can be changed consecutively VI 71 Chapter 6 16 bit Timers VI 72 6 11 Dead Time IGBT Output IGBT output with dead time generates the waveform inclusive ON or OFF time delay during the standard IGBT signal inversion And the formed waveform is output through TM7IO and TMSIO pins Startup trigger can be selected by the external interrupt 0 1 and 2 or starting of the timer 7 count operation 6 11 1 Op
250. C1 E LCD clock o Y Y VLC2 4 g 1 o 3 t p x vca e FLY amp 5 T 1 0 Figure 4 6 7 Block Diagram P76 Atsegment output port I O direction control is forcefully set to input mode pull up resistor is disabled and segment output is executed by the segment output control 64 Port 7 Chapter 4 Ports Nch open drain control T P 9 wor Vin Y Pull up pull down resistor selection edi Y Pull up pull down resistor control p s WEK N R direction control ul 2 3 9 D 18 pt Y UPC Port output data 2120 c N D f xcz Schmitt trigger input P7IN7 Port input data 2f clock input Key interruptinput Serial 0 clock input Serial O clock output SCOMD1 SCOSBTS LCD output control hg 88 Segment output control W Segment output data VLC1 t LCD clock o Y VLC2 E Y H 5 e 8 57 Y e 5 Y eL Figure 4 6 8 Block Diagram P77 Atsegment output port I O direction control is forcefully set to
251. C1SBIS Style Input mode gt P1DIR P1DIR5 PADIR PADIR5 Pull up setup Operation XII 57 Chapter 12 Serial interface 1 B Pin Setup with 2 channels at transmission reception Table 12 3 28 shows the pin setup at UART serial interface transmission reception with 2 channels pin RXDI pin Table 12 3 28 UART Serial Interface Pin Setup with 2 channels at transmission reception Setup item Data output pin Data input pin TXD1 pin RXD1 pin Port pin P15 PA5 16 4 Port pin setup Select used pin A B SCSEL SC1SL Serial data input selection RXD1 SC1MD1 SC1IOM Function Serial data output Serial data input SC1MD1 SC1SBOS SC1MD1 SC1SBIS Style Push pull Nch open drain P1ODC P1ODC5 PAODC PAODC5 y o Output mode Input mode P1DIR P1DIR5 PADIR PADIR5 P1DIR P1DIR6 PADIR PADIR7 Pull up setup Added not added P1PLUD P1PLUD5 PAPLU PAPLU5 XII 58 Operation 12 3 4 Setup Example B Transmission Reception Setup The setup example at UART transmission reception with serial 1 is shown Table 12 3 29 shows the condition at transmission reception Chapter 12 Serial interface 1 Table 12 3 29 UART Interface Transmission Reception Setup Setup item SEt to TXD1 RXD1 pin Independent with 2 channels Frame mode specification 8 bits 2 stop bits First trans
252. C6 WEK VR x Reset RJ P1DWN Pull up pull down resistor selection Wek R ree P1PLUD i gt 1 6 Pull up pull down resistor control 2 Wek VR pex Reset WP ss P1DIR6 o 00 01 10 0 VO direction control pD q M gt be WEK VR L x px Dx 1 11 1 P1 6 5 P1OUT6 0 00 Port output data Srt M sal e 5 pE gi Reget PIOMD 37 Port output control 10 06 WEK N R P1ING Schmitt trigger input Port input data lt 1 4 J R Serial 1 UART1 reception data input Timer 2 inpu Timer 2 outpu 4 Reset 2 1 05 4 Output contro WK LR m R 5 d LC2SLS LCD output contro D Q WEK R m Segment output contor is H a W Segment output data Vi i 1 LCD clock o y LC2 8 5 s 5 Y Y Vic3 i Y Figure 4 2 7 Block Diagram P16 At segment output port I O direction control is forcefully set to input mode pull up resistor is disabled and seg ment output is executed by the segment output control IV 20 Port 1 Chapter 4 Ports Nch open drain control Pull up pull down resistor selection t q wek YR y Reset Pull up pull down resistor control PIPLUD M K R WEK J
253. CD driver clock The source clock is the main clock fosc 128 1 27 1 26 1 25 1 2 1 2 1 2 1 2 The source clock is the sub clock fx 1 29 1 28 1 27 1 28 LCD power supply Available at VDD gt VLC1 External supply voltage is supplied by VLC1 VLC2 VLC3 pins or voltage applied to VLC1 is divided by internal resistance and supplied to VLC2 and VLC3 pins Hardware Functions 1 7 Chapter 1 Overview Port 48 pin 44 pin version version ports 39 pins 35 pins dual function dual function LED large current driver pin 4 pins 44 pins switchable to timer output LCD power supply pin 3 pins 3 pins A D input pin 1 pin 1 pin A D input Serial interface pin 6 pins 3 pins Timer LCD driver Remote control carrier output pin 1 pin 1 pin Timer output LCD driver Serial interface pin 2 pins 2 pins Timer LCD driver Serial interface pin 1 pin 1 pin Timer Buzzer output LCD driver pin 1 pin 1 pin Timer I O inverted buzzer output LCD driver pin 1 pin 1 pin IIC slave pin 2 pins 2 pins Key input LCD driver pin 3 3 Key input LCD driver PWM output pin 2 2 Key input LCD driver Serial interface pin 1 1 Key input LCD driver Serial interface slave pin 2 2 Common output pin 1 1 Common output Serial interface pin 3 3 External interrupt pin 3 3 2 pins are used as zero cross input pin ports 1 3 XI pin 1 1 Special pin 10 10 Analog reference voltage input pin 1 1 Operation mode input pin 1 1
254. CTION SET Group Mnemonic Operation Flag Re Fxten Machine Code Notes VFINF CF zF Size sion 1 2 3 4 5 6 7 8 9 10 11 BGT label if VF NF ZF 0 PC 6 d1 t label H3PC 0001 if VEANF ZF 1 PC 6 3PC BHI label if CFIZF 0 PC 5 d7 label H3PC 0 0010 if CFIZF 1 PC 5 gt PC BHI label if CFIZF 0 PC 6 d11 label eHPC 0010 if CFIZF 1 65 BLS label if CFIZF 1 PC 5 d7 label H PC 0011 if CFIZF 0 PC 5 gt PC BLS label if CFIZF 1 PC 6 d1 1 label H PC 0011 if CFIZF 0 PC 6 gt PC BNC label if NF 0 PC 5 d7 label H PC 0100 if NF 1 PC 53PC if NF 0 PC 6 d11 label H4PC 0100 1 6 BNS label if NF 1 PC 5 d7 label H PC 0101 if NF 0 PC 53PC BNS label if NF 1 PC 6 d11 label H4PC 0101 0 6 VF VF BNC label BVC label if VF20 PC 5 d7 label H2PC 0110 if VF 1 PC 5 gt PC BVC label if VF 0 PC 6 d11 label H gt PC 0110 if VF 1 PC 6 gt PC BVS label if VF 1 PC 5 d7 label H gt PC 0111 if VF 0 PC 5 gt PC BVS label 1 11 0111 if VF 0 PC 6 gt PC BRA label PC 3 d4 label H PC 111H BRA label PC 44d7 label amp H2PC 1001 BRA label PC 5 d11 label H PC 1001 CBEQ imm8 Dm label if Dmzimm8 PC 6 d7 label H3PC 10Dm if Dm4imm8 PC 62PC CBEQ imm8 Dm label if Dm imm8 PC 8 d1 1 label H2PC 10Dm if Dm4imm8 PC 82PC CBEQ imm8 abs8 label _ if mem8 abs8 imm8 PC 9 d7 la
255. CTR LCCTR2 LCCTR3 LCCTR4 5 Display 23 on the display panel by the address X 2E00 to X 2E01 of the segment output latch SEGO to SEG4 6 Set the LCDEN flag of the LCD mode control register 1 LCMD1 to 1 to start the LCD operation XVI 32 Display Chapter 17 Appendix Chapter 17 Appendix 17 1 Flash EEPROM 17 1 1 Overview The MN101CF78A is equivalent to MN101C78A except its Mask is substituted with 32 KB of flash EEPROM The MN101CF78A is programmed in the following modes PROM writer mode which uses a dedicated PROM writer for a microcontroller s stand alone programming Onboard programming mode which the CPU controls programming of a microcontroller on a target board User program area 32 KB 0x0000 to Ox7FFF This area stores an user program It is overwritten in both programming modes User Program Area Loader Program Area 0x0000 Programming Time Information Storage Area 0x0000 Block 1 Block 3 32 KByte 2 KByte MAIN area MO Boot area 0 07 Block 4 Ox3FFF 0x4000 2 KByte Boot area B1 Block 2 32 KByte MAIN area M1 Figure 17 1 1 Memory Map in Internal Flash EEPROM XVII 2 Flash EEPROM Chapter 17 Appendix One cycle of erase write process is counted as 1 programming in every block When sev eral blocks are programmed separately programming count is added by just the number of programming cycle For instance
256. CTXB1 I2CTXBO Serial interface 4 transmission data buffer Overview XIV 5 Chapter 14 Serial Interface 4 14 1 5 Mode Register EO See B Serial Interface 4 Addressing Register SC4AD0 0x03FA7 bp 7 6 5 4 3 2 1 0 Flag IPCAD7 I2CAD6 I2CAD5 I2CAD4 I2CADS I2CAD2 I2CAD1 I2CADO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description I2CAD7 I2CAD6 I2CAD5 2 4 I2CAD3 I2CAD2 I2CAD1 I2CADO Serial interface 4 addressing register Serial Interface 4 Addressing Register 1 SC4AD1 0x03FA8 bp 7 6 3 2 1 0 XIV 6 SELI2C 2 12 I2CADM 2 9 I2CAD8 At reset 0 0 0 0 0 0 Access SELI2C Description Reset control 0 Reset 1 Operational status 12 Monitor mode selection 0 Communication mode 1 Monitor mode 12 Communication mode selection 0 Normal communication mode 1 General call communication mode I2CADM Address mode selection 0 7 bits address mode 1 10 bits address mode Overview I2CAD9 I2CAD8 Address setup B Serial Interface 4 Status Register 1 SCASTR 0x03FAB bp 6 3 2 1 Chapter 14 Serial Interface 4 Flag I2CINT 2 SLVBSY ACKVALI At reset Access Description Data transfer direction determination fla
257. Control Registers Clock source selection 00 fosc 01 fs 10 TMB8IO input 11 Synchronous TMBIO input Chapter 6 16 bit Timers Timer 8 Mode Register 2 TM8MD2 Table 6 2 34 Timer 8 Mode Register 2 TM8MD2 0x03F89 7 6 5 4 3 2 1 0 T8ICEDG TM8PWM TM8BCR TM8PWM TM8IRS1 TM8ICEN TM8ICT1 TMBICTO SL 0 T8ICEDGO Description Capture trigger edge selection 0 Select the both edges 1 Select the specified edge TM8PWMS L PWM mode selection 0 Set duty by OC1 1 Set duty by OC2 TM8BCR Timer 8 count clear factor selection 0 Full count OVF 1 Match of BC and OC1 TM8PWM Timer output waveform selection 0 Output timer 1 Output PWM TM8IRS1 Timer 8 interrupt factor selection 0 Counter clear 1 Match of BC and OC1 TM8ICEN Input capture operation enable flag 0 Disable capture operation 1 Enable capture operation TM8ICT 1 TM8ICTO Capture trigger selection 00 External interrupt 0 input signal 01 External interrupt 1 input signal 10 External interrupt 2 input signal 11 Timer interrupt Control Registers VI 21 Chapter 6 16 bit Timers Timer 8 Mode Register 3 TM8MD3 Table 6 2 35 Timer 8 Mode Register TM8MD3 0x03F8F VI 22 7 4 3 2 1 0 TM8CKS MP TM8CKE TM8SEL TM8PWM DG F TM8PWM 8 0 0 0 0 TM8CKSMP Description Capture sampling selectio
258. D Port A Nch open drain control register PADIR Port A direction control register PAPLU OxOSF4A Port A pull up pull down control register SCORICR OxOSFEF Serial 0 UART reception interrupt control register SCOTICR OxO3FFO Serial 0 UART transmission interrupt control register R W Readable Writable R Readable only Control Registers 5 Chapter 11 Serial interface 0 11 2 2 Data Buffer Registers Serial interface 0 has one each of 8 bit data buffer register for transmission and for reception Serial interface 0 Reception Data Buffer RXBUFO 0x03F96 7 6 5 4 3 2 1 0 RXBUFO7 RXBUFO6 RXBUFO5 RXBUFO4 RXBUFOS RXBUFO2 RXBUFO1 RXBUFO0O Access Serial interface 0 Transmission Data Buffer 0 03 97 7 6 5 4 3 2 1 0 TXBUFO7 TXBUFO06 TXBUFO05 TXBUF04 TXBUFOS TXBUFO02 TXBUFO1 TXBUFOO X X X X X X X X XI 6 Control Registers Chapter 11 Serial interface 0 11 2 3 Mode Registers Serial interface 0 Mode Register 0 SCOMDO 0xOSF91 bp 7 6 5 4 3 2 1 0 Flag SCOCE1 5 SCODIR SCOSTE SCOLNG2 SCOLNG1 SCOLNGO 0 5 0 0 1 1 1 Reset Access R W R W R W R W R W R W bp Flag Description Transmission data output edge 1 Reception data
259. Figure 13 3 1 Transmission Data Buffer Operation XIII 13 Chapter 13 Serial Interface 3 Reception Data Buffer Use transmission reception shift register SC3TRB as reception data buffer The received data is stored to SC3TRB shifting by 1 bit mission and reception should not be executed at the same time in order to prevent abnormal a When the start condition is set to enable in the clock synchronous communication trans operation If start condition is input for activation during communication again the transmission data becomes invalid To transmit the data set it to TXBUF3 again SC3TRB is overwritten in every communication In sequence reception read out the data in SC3TRB before the next reception is started XIII 14 Operation Chapter 13 Serial Interface 3 Transmission Bit Count and First Transfer Bit When the transfer bit count is 1 to 7 bits data storage to the transmission reception shift register TXBUF3 depends on the first transfer bit When MSB is the first bit to be transferred the lower bits of TXBUF3 are used for storage In Figure 13 3 2 if data A to F are stored to bp2 to bp7 of SC3TRB as the transfer bit count is 6 bits data is transferred from F to A When LSB is the first bit to be transferred use the lower bits of TXBUF3 for storage In Figure 13 3 3 if data to F are stored to to bp5 of TXBUF3 as the transfer bit count is 6 bits data is transf
260. Hz 00 1 4 duty 64Hz 1X01 b1 1 3 duty 85 Hz 27 10 1 2 256 Hz Hz 11 static 256 Hz 00 1 4 duty 32Hz 1X10 01 1 3 duty 43 Hz X1 28 10 1 2 duty 128 Hz 11 static 128Hz 00 1 4 dut 16 Hz 1X11 01 1 3 dut 21 Hz X1 29 10 1 2 duty 64 Hz 22 pz 11 static 64 Hz Figure 16 3 6 Input Frequency and the LCD Clock Operation Chapter 16 LCD 16 3 4 Setup Example of the LCD Driver Circuit B Setup example of the internal voltage dividing resistor An example of setup procedure to display 23 on a 8 segment type LCD panel in 1 4 duty 1 3 bias with both seg ment signals SEGO to SEG3 common signals COMO to COMO using internal voltage divider circuit is shown below Refer to XIV 18 Figure 16 3 5 for the LCD power supply connection Refer to XIV 22 LCD display for con nection of LCD panel Setup Procedure Description 1 Select the internal voltage dividing resistor 1 Set the LCRHL flag of the LCD mode control register 2 LCDMD2 x 3FC1 LCDMD2 to 1 to set up the internal voltage dividing LCRHL 1 resistor to high resistor 2 Select the internal voltage dividing resistor 2 Set the LCREN flag of the LCD mode control register 2 connection LCDMD2 to 1 to connect the internal voltage LCDMD2 1 dividing resistor between V c4 and VI Vice and 2 LCREN 1 Vica and Vss 3 Set t
261. I 6 Control Registers Chapter 16 LCD 16 2 2 Mode Control Register 1 LCDMD1 The LCD mode control register 1 LCDMD1 is a 8 bit register that controls LCD clock LCD display ON OFF and display duty The address is assigned to 3FCO and read write can be done by the instruction to RAM I O The value of the LCDMDI register is initialized at reset Table 16 2 2 shows the LCD mode control register 1 Mode Control Register 1 LCDMD1 R W Table 16 2 2 LCD Mode Control Register 1 166 LCDEN Reserved LCDTY1 LCDTYO LCDCK3 LCDCK2 LCDCK1 LCDCKO 0 0 0 0 0 0 0 0 LCD driver circuit start flag LCDEN 0 Stop 1 Start Reserved Set always to 0 LCD display duty selection 00 1 4 duty 01 1 3 duty 10 1 2 duty 11 Static LCDTY1 LCDTYO LCD clock source selection 0000 OSC 1 2 0001 OSC 1 212 0010 050 1 2 3 0011 OSC1 2 4 0100 OSC1 215 0101 OSC1 2 6 LCDCKo 0110 OSC1 2 7 0111 OSC 1 218 1X00 26 1X01 27 1X10 28 1X11 XI 29 For transition to the mode with low speed oscillation set the bpO of the XI dual function selec Y tion register XSEL to 1 Control Registers XVI 7 Chapter 16 LCD XVI 8 16 2 3 Mode Control Register 2 LCDMD2 M The LCD mode control register 2 LCDMD2 is 8 bit register that contro
262. I 10 16 2 6 Output Control Register 3 XVI 11 16 2 7 Segment Output Latch ette ere XVI 12 16 3 Oper tion a e Foe tette tue nach bead ce ebat ue tes ct tt ons XVI 13 16 3 1 Operation e ete REDE 16 XVI 13 16 3 2 Power Supply ies RT IEEE E Pete E XVI 14 16 323 Frame Cycle s oec Bosco tret Uem XVI 19 16 3 4 Setup Example of the LCD Driver XVI 20 16 4 Display ae pne NONSE XVI 21 16 4 States rc e RU tete etu sp eod io tu en XVI 21 16 4 2 Setup Example Static XVI 23 16 4 3 1 2 AL EO ai Tan RE ERES XVI 24 16 4 4 Setup Example 1 2 duty eer meret iet tete eee XVI 26 16 4 5 1 3 duty ater RU ep RSG ated p IE XVI 27 16 4 6 Setup Example 1 3 duty iere eri eb Hep ae e EC ee XVI 29 16 4 7 1 4 duty e dere eet i terio eode XVI 30 16 4 8 Setup Example 1 4 duty rennen rennen nene XVI 32 Chapter L7 Appendix e te treu ones uoce tu qui Men too se ete dash cu vade 1 17 Elash BEPROM eere pri ede eade e tenes XVII 2 OVO O NUNG Ee XVII 2 172 PROM Water Mode uet phe pa pen pem ib eene 4 IFAT OVE EW 4 17 3 Onboard Seria
263. I RIRQ is generated Duplex communication On duplex communication the transmission and reception can be operated separately at the same time The frame mode and parity bit of the used data on transmission reception should have the same polarity B Transfer Bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the to 0 flag of the SCIMD2 register If the SCICMD flag of the SCIMDI register is set to 1 and UART communication is selected the setup by the synchronous serial transfer bit count selection flag SCILNG2 to 0 is no longer valid Data Input Pin Setup 2 channels type data output pin TXD1 pin data input pin RXD1 1 channel type data I O pin TXD1 pin be selected as a communication mode The RXD1 pin can be used only for serial data input The TXD1 can be used for serial data input or output Whether the serial data is input from RXD1 TXDI it can be selected by the SC1IOM flag of the SCIMDI register When data input from TXD1 pin is selected to set the 1 channel communication transmission reception can be switched by the TXDO pin direction control For TXDOA pin it can be done by the PADIR2 flag of the PADIR register For TXDOB by the P7DIRS flag of the P7DIR register At the same time RXD1 pin be used as a general port Reception Buffer Empty Flag When SCIRIRQ is generated data is stored automatically to RXBUF1
264. ICH7 TM7ICH6 TM7ICH5 TM7ICH4 TM7ICH3 TM7ICH2 TM7ICH1 TM7ICH 0 X X X X X X X X R Control Registers Chapter 6 16 bit Timers E Timer 7 Dead Time Preset Register 1 TM7DPR1 Table 6 2 15 Timer 7 Dead Time Preset Register 1 TM7DPR1 0x03F7E 7 6 5 4 3 2 1 0 TM7DPR 17 TM7DPR 16 TM7DPR 15 TM7DPR 14 TM7DPR 13 TM7DPR 12 TM7DPR1 1 TM7DPR 10 X X X X X X X X Timer 7 Dead Time Preset Register 2 TM7DPR2 Table 6 2 16 Timer 7 Dead Time Preset Register 2 TM7DPR2 0x03F7F 7 6 5 4 3 2 1 0 TM7IDPR 27 TM7IDPR 26 TM7IDPR 25 TM7IDPR 24 TM7IDPR 23 TM7IDPR 22 TM7IDPR 21 TM7IDPR 20 X X X X X X X X VI 12 Control Registers Chapter 6 16 bit Timers Timer 8 has a set of 16 bit programmable timer registers which contains a compare register a preset register a binary counter and a capture register Each register has 2 sets of 8 bit register Operate these registers by 16 bit access A compare register is a 16 bit register which stores comparative value of the compare register and the binary counter Timer 8 Compare register 1 TM8OC1 Table 6 2 17 Timer 8 Compare register 1 Lower 8 bits TM8OC1L 0x03F82 7 6 5 4 3 2 1
265. IMD KEYT3_ KEYT3_ _ _ 11 51 2 2EN2 2EN1 2ENO 0 0 0 0 KEY7 KEY6 KEY5 KEY4 key inter key inter key inter key inter rupt rupt rupt rupt selection selection selection selection 0x03F41 P1PLUD P1PLUD P1PLUD P1PLUD P1PLUD P1PLUD P1PLUD P1PLUD P1PLUD 9 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 1 Port 1 pull up pull down resistor 0x03F43 P3PLUD P3PLUD PSPLUD P3PLUD P3PLUD P3PLUD PS3PLUD P3PLUD IV 28 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 Port 3 pull up resistor pull down resistor OxO3F45 P5PLU6 P5PLU5 P5PLU4 P5PLU3 P5PLU2 P5PLU1 P5PLUO 43 0 0 0 0 0 0 0 Port 5 pull up resistor Special Function Registers List XVII 13 Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3F47 P7PLUD P7PLUD P7PLUD P7PLUD P7PLUD P7PLUD P7PLUD P7PLUD P7PLUD IV 53 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 Port 7 pull up pull down resistor OxO3F49 P9PLU P9PLUD 69 0 Port 9 pull up pull down resistor OxO3F4A PAPLUD PAPLUD PAPLUD PAPLUD PAPLUD PAPLUD PAPLUD IV 76 6 5 4 3 2 D 0 1 1 1 0 0 0 0 Port A pull up pull down resistor 0x03F4B SELUD PADWN P3DWN P9DWN P7DWN P1DWN 77 1 1 1 0 0 PA pull P3 pull P9 pull P7 pull P1 pull up
266. IOS flag of the SCOMDI register should be set to 0 SBOO pin port input data 1 input At forced reset the status register the SCOBRKF flag of the SCOMD2 register all flags of the SCOSTR register are initialized as they are set at reset but the control register holds the set value B Last Bit of Transmission Data Table 11 3 4 shows the data output holding period of the last bit at transmission and the minimum data input period of the last bit at reception At slave the internal clock should be set up to keep the data hold time at trans mission Table 11 3 4 Last Bit Data Length of Transfer Data The last bit data holding period at transmission The last data input period at reception At master 1 bit data length 1 bit data length Minimum At slave 1 bit data length of external clock x 1 2 4 internal clock cycle x 1 2 When start condition is disabled at SCOSTE flag 0 the 5800 output after the data output holding period of the final bit can be set by the setting value of the SCOFDCI to 0 flag of the SCOMD3 register as shown on Table 11 3 5 After releasing the reset despite the setting value of the SCOFDCI to 0 flag output before the serial transfer is When start condition is enabled at SCOSTE flag 1 despite the setting value of the SCOFDCI to 0 is output Table 11 3 5 SBOO Output after the Data Output Holding Period of the Last Bit without start condition
267. Input mode No pull up resistor port Port 7 Input mode No pull up pull down resistor port Port 9 Input mode P90 Pull down resistor port Port A Input mode to No pull up resistor port PA6 to 4 Pull down resistor Overview Chapter 4 Ports 4 1 3 Control Registers Port 1 port 2 port3 port5 port 7 port 9 and port A are controlled by the data output register PnOUT the data input register PnIN the I O direction control register PnDIR the pull up resistor control register PnPLU or the pull up pull down resistor control register PnPLUD and registers that control special function pin PnROMD PnIMD PnSYO PnSEV PnCNTO PnODC Table 4 1 2 shows the registers to control port 1 port 2 port3 port5 port 7 port 9 and port A Table 4 1 2 I O Port Control Registers List Register Address Function P1OUT Ox03F 11 Port 1 output register 0x03F21 Port 1 input register P1DIR 0x03F31 Port 1 direction control register P1PLUD 0x03F41 Port 1 pull up pull down resistor control register 1 0x03F1C Port 1 output mode register P10DC 0x03F1B Port 1 Nch open drain control register SELUD 0x03F4B Pull up pull down resistor selection register P1CNTO 0x03F3D Port 1 real time output control register 0 CLKOUT OxOSF1F Clock output control register 2 0x03F12 Port 2 output register P30UT 0x03F13 Port 3 output register P3IN 0x03F23 Port 3 i
268. KE Reset 0 0 0 0 0 0 0 Access R Description Frame mode specification 00 7 data bit 1 stop bit 01 7 data bit 2 stop bit 10 8 data bit 1 stop bit 11 8 data bit 2 stop bit SCOFM1 SCOFMO Added bit specification Transmission Reception SCOPM1 00 Add 0 Check for 0 SCOPMO 01 Add 1 Check for 1 10 Add odd parity Check for odd parity 11 Add even parity Check for even parity Parity enable SCONPE 0 Enable parity bit 1 Disable parity bit Break status receive monitor SCOBRKF _ 0 Data reception 1 Break reception Break status transmit control SCOBRKE 0 Data transmission 1 Break transmission Control Registers XI 9 Chapter 11 Serial XI 10 interface 0 Serial interface 0 Mode Register 3 SCOMD3 0x03F94 bp 7 6 3 2 1 0 Flag SCOFDC1 SCOPSC SCOFDCO SCOPSC2 SCOPSC1 SCOPSCO Reset 0 0 0 0 0 Access SCOFDC1 SCOFDCO Description Output selection after SBOO final data is transferred 00 Fix to 1 High output 01 Hold final data 10 Fix to 0 Low output 11 Reserved SCOPSCE Prescaler count control 0 Disable the count 1 Enable the count SCOPSC2 SCOPSC1 SCOPSCO Control Registers Selection clock 000 fosc 2 001 fosc 4 010 fosc 16 011 fosc 64 100 fs 2 101 fs 4 110 Timer 1 output 111 Timer 2 output 7 Serial interface 0 Status Regist
269. KM 0 Select the transfer clock SC1MD1 0x03F9A bp4 SC1SBOS 1 bp5 SC1SBIS 1 bp6 SC1SBTS 1 bp7 SC1IOM 0 9 Set the interrupt level SC1TICR 0x03FF2 bp7 6 SC1TLV1 0 10 4 Set the SC1SL flag of the SCSEL register to 0 to select A port A as I O pin b Set the P1 ODC7 P10ODC5 flag of the P1ODC register to 1 1 and select Nch open drain to SBO1 SBT1 pin Set the P1PLUD7 P1PLUD5 flag of the P1PLUD register to 1 1 to enable the pull up resistor 6 Set the P1DIR7 P1DIR5 flag of the Port 1 pin direction control register P1DIR to 1 1 and the P1DIR6 flag to 0 to set P17 P15 to the output mode P16 to the input mode 7 Set the SC1LNG2 to 0 flag of the serial 1 mode register 0 SC1MDO to 111 to set the transfer bit count as 8 bits Set the SC1STE flag of the SC1MDO register to 0 to disable the start condition Set the SC1DIR flag of the SC1MDO register to 0 to set MSB as a transfer first bit Set the SC1CE1 flag of the SC1MDO register to 1 to set the reception data input edge falling and the transmission data output edge rising 8 Set the SC1CMD flag of the SC1MD1 register to 0 to select the synchronous serial Set the SC1MST flag of the SC1MD1 register to 1 to select the clock master internal clock Set the SC1CKM flag to 0 to select not divided for the clock source Set the SC1SBOS SC1SBIS SC1SBTS flag of the SC1MD1 register to 1 to set the SBO1 pin to the
270. LCCTRI to 1 At common output it is force fully set to input mode and pull up resistor is disabled P32 is used as the LCD common output pin COMO as well The 2 pin selection can be done by setting the bit 2 flag COMSLO flag of the LCD output control register 1 LCCTRI to 1 At common output it is force fully set to input mode and pull up resistor is disabled P33 is used as LCD common output COMG as well The COM3 pin selection can be done by setting the bit 3 flag COMSLO flag of the LCD output control register 1 LCCTRI to 1 At common output it is force fully set to input mode and pull up resistor is disabled Port 3 Chapter 4 Ports P34 is used as voltage pin of the LCD driver circuit and VLC3 as well The VLC3 pin selection can be done by setting the bit 2 flag VLC3SL of the LCD output control register 3 LCCTR3 to 1 P35 is used as voltage pin of the LCD driver circuit and VLC3 as well The VLC2 pin selection can be done by setting the bit 1 flag VLC2SL of the LCD output control register 3 LCCTR3 to 1 P36 is used as voltage pin of the LCD driver circuit and VLC1 as well The VLCI pin selection can be done by setting the bit 0 flag VLCISL of the LCD output control register 3 LCCTR3 to 1 Port 3 IV 25 Chapter 4 Ports 4 4 2 Registers Table 4 4 1 shows the registers that control the port 3 Table 4 4 1 Port 3 Control Register Registers A
271. LCD 16 3 2 Power Supply The driver power pins are c and Vy This LSI contains the internal voltage dividing resistor to divide voltage for LCD drive There are two ways to supply voltage to the LCD driver to supply voltage to the Vic and Vj pins from external source when external voltage dividing resistor is used to supply voltage to Vic pin from external source and use internal divider resistor The power source for LCD drive and power supply for the micro controller are separated so that the voltage for LCD panel drive can be used at higher voltage than the V pp power supply usable at Vy cp Vpp 3 6 V The LCD driver voltage supplied through the LCD driver power pins Vr cy Vr c and Vr is converted by the LCD clock signal and the timing control signal and then supplied to the segment driver and the common driver Table 16 3 1 Supplying LCD drive voltage with 1 3 bias Reference voltage ts Supplying voltage supplying Description pin 1 Supply the driving Vici Supply voltage to VLC1 VLC2 VLC3 pins externally voltage directly Vic2 Vics 2 Use the external dividing Vici Supply the reference voltage to VLC1 pin externally and resistor Vice generate VLC2 VLC3 potentials at the external resistor divider then supply the voltage to each pin 3 Use the internal dividing Vici Supply the reference voltage to VLC1 externally and genera
272. M output is changed from L output to H output at the selection of PWM operation by the TMnPWM flag of the TMnMD register 40 8 bit PWM Output Chapter 5 8 bit Timers 5 8 Serial Transfer Clock Output 5 8 1 Operation Serial transfer clock can be created by using the timer output signal Serial transfer clock operation by 8 bit timer Timer 1 2 and 3 Timer 1 Serial 0 Timer 2 Serial 0 Serial 2 Timer 3 Serial 2 Timing of Serial Transfer Clock Timer 1 2 and 3 TMnEN flag Compare N register counter Interrupt request flag Timer output Figure 5 8 1 Timing of Serial Transfer Clock Timer 1 2 and 3 The serial transfer clock is the 1 2 of the frequency set to the compare register For the baud rate calculation and the serial interface setup refer to chapters for Serial Interface Serial Transfer Clock Output V 41 Chapter 5 8 bit Timers 42 5 8 2 Setup Example Serial Transfer Clock Setup Example Timer 2 How to create a transfer clock for half duplex UART Serial 0 using with the timer 2 is shown below The baud rate is selected to be 300 bps the source clock of timer 2 is selected to be fs 2 at fs 2 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM2MD 0x03F5C bp3 TM2EN 0 2 Select the normal timer operatio
273. M7MD3 x 3F8E bp1 0 T7IGBT1 0 01 6 Select the interrupt generation valid edge IRQOICR X 3FE2 bp5 REDGO 1 7 Select IGBT trigger generation level TM7MD3 x 3F8E bp4 T7IGBTTR 0 8 Select IGBT trigger generation edge TM7MD2 x 3F79 bp7 T7ICEDG 1 9 Set the interrupt level IRQOICR x 3FE2 bp7 6 IRQOLV1 0 10 10 Enable the interrupt IRQOICR x 3FE2 bp1 IRQOIE 1 11 Select the count clock source TM7MD 1 x 3F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 01 12 Set the IGBT output cycle TM7PR1 x 3F75 x 3F74 x 61a7 13 Set H period of the IGBT output TM7PR2 X SF7D 7 186 14 Start the timer operation TM7MD1 x 3F78 bp4 TM7EN 1 b Set the external interrupt O IRQO input as IGBT trigger generation factor by the T7IGBT1 0 flag of the TM7MD3 register 6 Set the REDGO flag of the external interrupt O control register IRQOICR to 1 to select the rising edge as the interrupt generation valid edge 7 Set the T7IGBTTR flag of the TM7MD3 register to 0 to set the IGBT trigger level to H 8 Set the T7ICEDG of the TM7MD2 register to 1 to select the external interrupt specified edge as the IGBT trigger generation factor 9 Set the interrupt level by the IRQ1LV1 to 0 flag of the IRQOICR register If any interrupt request flag is already set clear it Chapter 3 3 1 4 Interrupt Flag Setup 10 Set the TM7EN flag
274. M8ICHO X X X X X X X X R Control Registers Chapter 6 16 bit Timers VI 16 6 2 3 Timer Mode Registers This is a readable writable register that controls timer 7 E Timer 7 Mode Register 1 TM7MD1 Table 6 2 29 Timer 7 Mode Register 1 TM7MD1 0x03F78 7 6 3 2 1 0 At reset Reserved 1 T7ICEDG TM7PS1 TM7PSO TM7CK1 TM7CKO Access Reserved Description Set always 0 T7ICEDG1 Capture trigger edge selection 0 Falling edge 1 Rising edge Timer output reset signal 0 Operate timer output 1 Disable timer output Timer 7 count control 0 Halt the count 1 Operate the count TM7PS1 TM7PSO Count clock selection 00 1 1 of clock 01 1 2 of clock 10 1 4 of clock 11 1 16 of clock TM7CK1 TM7CKO Control Registers Clock source selection 00 fosc 01 fs 10 TM71O input 11 Synchronous TM7IO input Chapter 6 16 bit Timers Timer 7 Mode Register 2 TM7MD2 Table 6 2 30 Timer 7 Mode Register 2 TM7MD2 0x0O3F79 7 6 5 4 3 2 1 0 T7ICEDG T7PWMS TM7BCR TM7PWM TM7IRS1 T7ICEN T7ICT1 T7ICTO L 0 T7ICEDGO Description Capture trigger edge selection 0 Select the both edges 1 Select the specified edge T7PWMSL PWM mode selection 0 Set duty by OC1 1 Set duty by OC2 TM7BCR Timer 7 count clear factor selection 0 Full coun
275. MN101C LSI User s Manual Architecture Instructions Table 2 1 1 Basic Specifications Structure Load store architecture Six registers Data 8 bit x 4 Address 16 bit x 2 Instruction length Others PC 19 bit PSW 8 bit SP 16 bit Instructions Number of instructions 37 Addressing modes 9 Basic portion 1 byte min Extended portion 0 5 byte x n O n 9 Basic Internal operating frequency max 10 MHz performance Instruction execution Min 1 cycle Inter register operation Min 2 cycle Load store Min 2 cycle Conditional branch 2 to 3 cycles Pipeline 3 stage instruction fetch decode execution Address space 256 KB max 64 KB for data Instruction data space External bus Address 18 bit Data 8 bit Minimum bus cycle 1 system clock cycle Interrupt Vector interrupt 3 interrupt levels Overview Chapter 2 CPU Basics Low power con sumption mode STOP mode HALT mode Overview 3 Chapter 2 CPU Basics Il 4 2 1 1 Block Diagram ee Data registers Do Processor status word clksys Clock 4 Source oscillation Address registers D1 PSW generator Stack pointer 02 SP A1 D3 ABUS BBUS Program counter Incremente 1 Instruction execution controller Inst
276. MPW imm16 Am Am imm16 PSW eee e 1101 110a H6 m Logical manipulation instructions AND Dn Dm Dm amp Dn Dm 0011 0111 DnDm AND imm8 Dm Dm amp imm8 Dm 4 0001 11Dm lt 8 imm8 PSW PSW amp imm8 5PSW 5 0010 1001 0010 lt 8 OR Dn Dm DmlDn5Dm 0011 0110 DnDm OR 8 0 Dmlimm8 Dm 4 0001 10Dm lt 8 OR imm8 PSW PSWlimm8 PSW 5 0010 1001 0011 lt 8 XOR Dn Dm Dm Dn2Dm 0 0 3 0011 1010 DnDm XOR imm8 Dm Dm imm8 Dm 5 0011 1010DmDm lt 8 1 D DWn d DWm 5 D DWm 9 m n 2 a Am 6 4 sign extension 8 d DWm 7 8 sign extension 4 D DWk 8 Dn zero extension Instruction Set XVII 29 Chapter 17 Appendix MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag ge Re Exten Machine Code vFINF cFIzF Size son 1 2 3 4 5 6 r 8 9 10 11 NOT NOT Dn DnoDn 0e 0010 0010 10Dn ASR ASR Dn Dn msbtemp Dn Isb CF 0 eee 0010 0011 10Dn Dn gt gt 1 Dn temp Dn msb LSR LSR Dn Dn Isb gt CF Dn gt gt 1 Dn 0 0 3 2 0010 0011 11Dn 0 Dn msb ROR ROR Dn Dn Isbtemp Dn 1 Dn 0 e 2 0010 0010 11Dn CF gt Dn msb temp gt CF Bit manipulation instructions BSET BSET io8 bp mem8 IOTOP i08 amp bpdata PSW 0 e 01 5 5 0011 1000 io8 gt 1 meme8 IOTOP io8 bp BSET abs8 bp mem8 abs8 amp bpdata PSW 44 1011
277. No capability Clock type selection CLKSEL 0 System clock fx 1 High speed oscillation fosc Low speed oscillation fx Clock output permission 0 No 1 Oscillation output Port 1 13 Chapter 4 Ports IV 14 LCD Output Control Register 2 LCCTR2 X 3FC3 R W LC2SL7 LC2SL6 LC2SL5 LC2SL4 1 2513 LC2SL2 LC2SL1 LC2SLO 0 0 0 0 0 0 0 0 LC2SL7 Description SEG11 P14 selection 0 14 1 SEG11 LC2SL6 SEG10 P15 selection 0 P15 1 SEG10 LC2SL5 SEGO9 P16 selection 0 P16 1 SEG9 LC2SL4 SEG8 P17 selection 0 P17 1 SEG8 LC2SL3 SEG7 P70 selection 0 P70 1 SEG7 LC2SL2 SEGO P71 selection 0 71 1 SEG6 LC2SL1 SEG5 P72 selection 0 P72 1 SEG5 Port 1 LC2SLO SEG4 P73 selection 0 P73 1 SEG4 Serial Input output pin switching Control Register SCSEL 0x03F90 Chapter 4 Ports Description TEMPSC 2 TEMPSC 1 Timer 2 output dividing switch 00 Timer 2 output 01 Timer2 output 2 10 Reserved 11 Timer 2 output 8 Serial port 4 I O pin switch 0 A Port A 1 B Port 3 Serial port 1 pin switch 0 A Port A 1 B Port 1 Serial port 0 I O pin switch 0 A Port A 1 B Port 7 Port 1 IV 15 Chapter 4 Ports 4 2 3 Block Diagram Nch open drain control Pull up pull down resistor selection
278. OM2 COMSL1 COM1 P31 selection 0 P31 1 COM1 Port 7 COMSLO COMO P30 selection 0 P30 1 COMO Chapter 4 Ports LCD Output Control Register 2 LCCTR2 X 3FC3 R W 02517 LC2SL6 LC2SL5 LC2SL4 1 2513 LC2SL2 LC2SL1 LC2SLO 0 0 0 0 0 0 0 0 Description SEG11 P14 selection LC2SL7 0 14 1 SEG11 SEG10 P15 selection LC2SL6 0 P15 1 SEG10 SEG9 P16 selection LC2SL5 0 P16 1 SEG9 SEG8 P17 selection LC2SL4 0 P17 1 SEG8 SEG7 P70 selection LC2SL3 0 P70 1 SEG7 SEGO P71 selection LC2SL2 0 P71 1 SEG6 SEG5 P72 selection LC2SL1 0 P72 1 SEG5 SEG4 P73 selection LC2SLO 0 P73 1 SEG4 Port 7 IV 57 Chapter 4 Ports 4 6 3 Block Diagram 4 Reget RA P7DWN Y g Pull up pull down resistor control Rq EZEEUDO Pull up pull down resistor selection gt 2 x 3 9 D te direction control H E Port output data eeg O 5 Port output control gt WEK VR Schmitt trigger input Port input data v J R Key interrupt input Timer 1 input Timer 1 output Reget LC2SL3 LCD output control
279. OP mode the watchdog timer is cleared automatically 5 In STOP mode the watchdog interrupt cannot be generated 6 After recovering from STOP mode if the detection of the incorrect code execution is valid the counting is executed for the duration of the oscillation stabilization wait time If the detection is invalid the counting is stopped in the condition that the counting of the oscillation stabilization wait time is proceeded 7 After releasing reset the watchdog timer is cleared automatically and stop counting In the system that uses STOP mode whether the STOP mode is done or not is generally divided on the program execution However in this case the counting value of the watchdog timer differs Operation Chapter 9 Watchdog Timer 9 3 2 Setup Example l u cI E The watchdog timer detects errors In the following example the time out period is set to 218 x system clock An example setup procedure with a description of each step 15 shown below Initial Setup Program Watchdog Timer Initial Setup Example Setup Procedure Description 1 Set the time out period 1 Set the WDTS1 0 flag of the watchdog timer control WDCTR 0x03F02 register WDCTR to 01 to select the time out period bp2 1 WDTS1 0 01 to 21 x system clock 2 Start the watchdog timer operation 2 Set the WDEN flag of the WDCTR register to start the WDCTR 0x03F02 watchdog timer operation bp0 WDEN 1 B Main Routine Program Wat
280. P1PLUD2 P1PLUD1 Chapter 4 Ports P1PLUDO 0 0 0 0 0 0 1 1 O Q O P1PLUD7 P1PLUD6 P1PLUD5 P1PLUD4 P1PLUD3 P1PLUD2 P1PLUD1 P1PLUDO Description Pull up pull down resistor selection 0 Not added 1 Added Port 1 9 Chapter 4 Ports Port 1 Output Mode Register P1OMD 0x03F1C P1OMD7 P1OMD6 P1OMD5 P1OMD4 P1OMD3 L P1OMD2 BUZSEL 0 0 0 0 0 0 0 Description port TM2OB selection 7 P1OMD7 0 l O port 1 TM20B port TM2IO selection 6 P1OMD6 0 l O port 1 TM21IO port TMOOB selection 5 P1OMD5 0 port 1 TMOOB port TMOIO RMOUT selection 4 P1OMDA 0 port 1 TMOIO RMOUT 3 P1OMD3 P13 1 0 port TM7IO NBUZZER selection NBUZSE 1X TM7IO 2 L 01 NBUZZER 1 P1OMD2 P12 I O port 8 BUZZER selection 1X TM8IO 0 BUZSEL 01 BUZZER 00 port IV 10 Port 1 Port 1 Nch Open drain Control Register S1ODC 0x03F1B P17ODC P150DC P110DC Chapter 4 Ports P100DC 0 0 0 0 bp Flag Description O O Q O Pull up pull down Resistor Selection Register SELUD 0x03F4B P17ODG P150DC P110DC P100DC Nch open drain output selection 0 Push pull output 1 Nch open drain output Flag PADWN P3DWN P9DWN P7DWN P1DWN At reset
281. P1PLUD7 P1PLUD5 flag of the P1PLUD register to bp5 P1ODC5 1 1 1 to enable the pull up resistor P1PLUD 0x03F4A bp7 P10DC7 1 bp5 P1ODC5 1 XII 36 Operation Chapter 12 Serial interface 1 Setup Procedure Description 6 Control the pin direction P1DIR 0x03F31 bp7 P1DIR7 1 bp6 P1DIR6 0 bp5 P1DIR5 1 7 Set the SC1MDO register Select the transfer bit count SC1MDO 0x03F99 bp2 0 SC1LNG2 0 111 Select the start condition SC1MDO 0x03F99 bp3 SC1STE 0 Select the first bit to be transferred SC1MDO 0x03F99 bp4 SC1DIR 0 Select the transfer edge SC1MDO 0x03F99 bp7 SC1CE1 1 8 Set the SC1MD1 register Select the communication style SC1MD1 0x03F9A SC1CMD 0 Select the transfer clock SC1MD1 0x03F9A bp2 SC1MST 1 bp3 SC1CKM 0 Select the transfer clock SC1MD1 0x03F9A bp4 SC1SBOS 1 bp5 SC1SBIS 1 bp6 SC1SBTS 1 bp7 SC1IOM 0 9 Set the interrupt level SC1TICR 0x03FF2 bp7 6 SC1TLV1 0 10 10 Enable the interrupt SC1TICR OxOSFF2 bp1 SC1TIE 1 bp2 SCOTIR 0 11 Start the serial Reception dummy data gt TXBUF1 0x03F9F Received data input SBI1 pin 6 Set the P1DIR7 P1DIR5 flag of the Port 1 pin direction control register P1DIR to 1 1 and the P1DIR6 flag to 0 to set P17 P15 to the output mode P16 to the input mode 7 Set the SC1LNG2 to 0 flag of the serial 1 mode register 0 SC1MDO to 111 to set the transfer bit count a
282. P70 1 SEG7 SEGO P71 selection LC2SL2 0 P71 1 SEG6 SEG5 P72 selection LC2SL1 SEG4 P73 selection LC2SLO 0 P73 1 SEGA XVI 10 Control Registers Chapter 16 LCD 16 2 6 Output Control Register 3 LCCTR3 The LCD output control register 3 LCCTR3 switches port P34 to P36 and Vj c to Vr The address is assigned to X 3FC4 At reset these ports are set to the input port Output Control Register 3 LCCTRS3 X 3FCA R W Table 16 2 6 LCD Output Control Register 3 Flag LC3SL2 LCSSL1 LC3SLO Reset 0 0 0 Access VLC3 P34 selection LC3SL2 0 P34 1 VLC3 VLC2 P35 selection LC3SL1 0 P35 1 VLC2 VLC1 P36 selection LC3SLO 0 P36 1 VLC1 With the internal voltage dividing resistor P34 Vi P35 Vi P36 Vi can be used as a ports However depending on the panel if LCD display does not have enough brightness due to the lack of connection with a stabilizing capacitor connect with the stabilizing capaci tor or use an external voltage dividing resistor Control Registers XVI 11 Chapter 16 LCD 12 16 2 7 Segment Output Latch E 4 61 latch is allocated per segment BitO 14 read out at the timing of COMO bit5 are read out at the timing of COMI bit2 and bit6 are read out at the timing of COMO an
283. P77 Function Serial data Serial clock I O N ch open drain setup regis P1ODC ter P7ODC Pull up resistor control regis P1PLUD ter P7PLUD identifying reception data or by changing the slave address Including general call communi 1 This serial interface does not features the function that resets the serial interface circuit by cation mode reception data identification should be done by software XIV 10 Operation Chapter 14 Serial Interface 4 14 2 1 Setup Example of the Slave Serial Interface u s tj Setup Example of the Data Transmission The setup example for slave transmission with serial 4 is shown Table 14 2 2 shows the conditions at transmis sion Table 14 2 2 Conditions for Slave IIC Communication Item set to Data pin SDA P10 Clock pin SCI P11 Addressing mode 7 bits Slave address 0110011 Transmission data 55 Setup Procedure Description 1 Control the pin type 1 Set the P1ODCt1 flags of the P1ODC register P1ODC x 3F1B to 1 to select N ch open drain for P10 and P11 bp1 0 P1ODC1 0 11 Set the P1PLUDO P1PLUD1 flag of the PIPLUD P1PLUD x 3F417 register to 1 to add pull up resistor bp1 0 P1PLUD1 0 11 2 Control the pin direction 2 Set the P1DIRO P1DIR1 flags of the port 1pin direction P1DIR x 3F31 control register P1DIR to 1 to set P10 and P11 to bp1 0 P1DIR1 0 11 outp
284. PC if mem8 io bp 0 PC 82PC i mem8 abs16 bp 1 PC 9 d7 label HC if mem8 abs16 bp 0 PC 9PC 6 7 0011 0101 16 lt io8 gt dii 2 7 8 0011 1111 Obp abs 16 gt d x TBNZ abs16 bp label 6 1 PC 10 dt labe PC if mem8 abs16 bp 0 PC 10 PC 01 7 8 0011 1111 1bp abs 16 gt dii 2 JMP JMP An 0 17 16 gt 15 0 0 0010 0001 00A0 JMP label abs18 label HOPC 0011 1001 0 abs 18b 15 0 5 JSR JSR An SP 35SP PC 3 bp7 0 mem8 SP PC 3 bp15 8 mem8 SP 1 PC 3 H gt mem8 SP 2 bp7 0 mem8 SP 2 bp6 2 PC 3 bp17 16 smems SP 2 bp1 0 0 6 17 16 gt 5 15 0 0 0010 0001 00 1 JSR label SP 35P PC 5 bp7 02mem8 SP PC 5 bp15 8 mem8 SP 1 PC 5 H mem8 SP 2 bp7 0 8 2 6 2 PC 5 bp17 16 mem8 SP 2 bp1 0 PC 5 d12 label H PC 0001 000H lt d12 3 JSR label SP 355P PC 6 bp7 0 memB SP PC 6 bp15 8 mem8 SP 1 PC 6 H mem8 SP 2 bp7 0 8 2 6 2 PC 6 bp17 16 mem8 SP 2 bp1 0 PC 6 d16 label H5PC 0001 001H di6 4 JSR label SP 35SP PC 7 bp7 02mem8 SP PC 7 bp15 8 gt mem8 SP 1 PC 7 H mem8 SP 2 bp7 0 gt mem8 SP 2 bp6 2 PC 7 bp17 16 smem8 SP 2 bp1 0 absi8 labe
285. PR1 x 3F85 x 3F84 x 1C9C To set 1 60 Hz by dividing 8 MHz set as 480 000 000 1 479 999 999 x 1C9C37FF At the same time the same values are loaded to the timer 7 compare register 1 TM7OC1 and the timer 8 compare register 1 TM8OC1 and the timer 7 binary counter TM7BC and the timer 8 binary counter TM8BC are initialized to x 0000 8 Set H period of the PWM output 8 Set H period of the PWM output to the timer 7 preset TM7PR2 x 3F7D x 3F7C x 6C00 register 2 TM7PR2 and the timer 8 preset register 2 TM8PR2 x 3F8D x 3F8C x 02DC TM8PR2 To set 1 10 duty of 480 000 000 dividing set as 480 000 000 10 48 000 000 x 02DC6C00 At the same time the same values are loaded to the timer 7 compare register 2 TM7OC2 and the timer 8 compare register 2 TM8OC2 9 Start the timer operation 9 Set the TM7EN flag of the TM7MD1 register to 1 to TM7MD 1 x 3F78 operate the timer 7 and the timer 8 bp4 TM7EN 1 VI 84 TM7BCL TM7BCH TM8BCL TM8BCH counts up from X 00000000 as a 32 bit timer The TMSIO out puts until TM7BCL TM7BCH TM8BCL TM8BCH reaches the set value of the TM70C2L TM70C2H TM8OC2L TM8OC2H register Once they mach it outputs L After that TM7BCL TM7BCH TM8BCL TM8BCH continues to count up once TM7OCIL TM70C1H 8 reaches the TM7BCL TM7BCH TM8BCL TM8BCH register to be cleared the TM
286. PROM in devices that are already installed on a PCB board with internal serial interface Use the dedicated serial writer for programming controlled by the load program In this mode load program is write erase protected in the hardware Hardware and software requirements Hardware and software products required for onboard serial programming are as follows Hardware requirements Onboard serial writer Flash programming connectors or pins for target board Software requirements Load program installed in the internal flash EEPROM Load program should be programmed with PROM writer in advance The load program is attached to the serial writer Programming algorithm for operating onboard serial writer Built in hardware for onboard serial programming mode Use this LSI s serial interface 0 as a standard serial writer for programming the flash EEPROM in onboard serial programming mode Refer to Chapter 11 Serial Interface O be reserved as dedicated pins to prevent other user circuits from communicating with the device Alternatively design your target board to be capable of normal communication with serial writer a Serial interface I O pins SBTOB SBIOB P76 used for onboard serial programming should Onboard serial programming writer The onboard serial programming writer supports the following model Also the load program can be downloaded on the following website YDC AF220 B http ydc co jp micom p
287. PWM output 3 Set the TM7PWM flag of the timer 7 mode register 2 TM7MD2 0x03F 79 TM7MD2 to 1 to select the PWM output bp4 TM7PWM 1 4 Set the high precision PWM output 4 Set the P1DIR4 flag of the port 1 direction control TM7MD2 0x03F79 register P1DIR to 1 to select the TM7OC2 compare bp5 TM7BCR 1 match as the duty decision source of the PWM output bp6 T7PWMSL 1 5 Select the count clock source b Select fosc as the clock source by the TM7CK1 to 0 flag TM7MD 1 0x03F78 of the TM7MD 1 register Also select 1 1 dividing as bp1 0 TM7CK1 0 200 the count clock source by theTM7PS1 to 0 flag bp3 2 TM7PS1 0 200 6 Select IGBT timer startup factor 6 Set IGBT timer startup factor to timer 7 count operation TM7MD3 0x03F8E bp1 0 T7IGBT1 0 00 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VI 47 Chapter 6 16 bit Timers Setup Procedure Description 7 Set the PWM output cycle 7 Set the PWM output cycle to the timer 7 preset register 1 7 1 0x03F75 0x03F74 0 61 7 TM7PR1 To set 400 Hz by dividing 10 MHz set as 25000 1 24999 0 61 7 At the same time the same value is loaded to the timer 7 compare register 1 7 1 the timer 7 binary counter is initialized to 0x0000 8 Set the H period of the PWM output 8 Set H period of the IGBT output to the timer 7 preset TM7PR2 0x03F7D 0x03F7C 0x1869 register 2 TM7PR2 To set 1 4 duty of 250
288. Pana Series The One toWatch for Constant Innovation Making the Future ComeAlive MICROCOMPUTER MN101C MN101C78A F78A LSI User s Manual Pub No 21478 013E Panasonic PanaXSeries is a trademark of Matsushita Electric Industrial Co Ltd The other corporation names logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations Request for your special attention and precautions in using the technical information 1 2 3 4 5 6 7 8 and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the Foreign Exchange and Foreign Trade Law is to be exported or taken out of Japan The technical information described in this book is limited to showing representative characteristics and applied circuits examples of the products It neither warrants non infringement of intellectual property right or any other rights owned by our company or a third party nor grants any license We are not liable for the infringement of rights owned by a third party arising out of the use of the product or technologies as described in this book The products described in this book are intended to be used for standard applications or general electronic equipment such as office equipment communications e
289. Pull up pull down resistor control direction control P10 Port output data m E w Schmitt trigger input Port input data 104 reception data input transmission data output SC4AD1 I2CSEL Figure 4 2 1 Block Diagram P10 Nch open drain control Reset x b d P1DWN Rest bd P1PLUD1 5 4 WEK R Reset direction control t EADIE e ym XE P10UT1 4 Va Pull up pull down resistor selection Pull up pull down resistor control Port output data snq eg Schmitt trigger input Port input data lt IIC4 clock input Figure 4 2 2 Block Diagram P11 IV 16 Port 1 P11 i Edge event External interrupt 0 IRQ0 holding function R d P1DWN Pull up pull down resistor selection wed Yn Y re P1PLUD 1 2 Pull up pull down resistor control Rg WEK R Reset TE P1DIR2 Ori 00 01 10 direction control t Q gt M WCK R Lx x 1 11 g 1 Af 1 fi Y m M Port output data d 19012 TW 7 WEK VR nix Ji X Reget Y Buzzer output control t Rg BUZSEL WEK R Reset Port output control Rd P IOMD2 R Schmitt trigg
290. Pull up pull down resistor selection register IV 11 P1CNTO 0x03F3D R W Port 1 real time output control register 0 IV 12 CLKOUT OxOS3F1F R W Clock output control register IV 13 LCCTR2 0x03FC3 R W LCD output control register IV 14 SCSEL 0x03F90 R W Serial I O pin switching control register IV 15 R W Readable Writable Port 1 Output Register P1OUT 0x03F 11 gt p p x x x x x x x x At reset Access R W R W R W R W R W R W R W R W bp Flag Description P1OUT7 P1OUT6 P1OUT5 P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUTO Output data 0 Output L VSS level 1 Output H VDD level O IS Q Q O Port 1 7 Chapter 4 Ports Port 1 Input Register P1IN 0x03F21 bp Flag Description 7 P1IN7 6 P1IN6 2 is fe Input data 0 is L VSS level 3 4 Pin is H VDD level 2 P1IN2 1 0 P1INO Port 1 Direction Control Register P1DIR 0x03F31 8 Flag P1DIR7 P1DIR6 P1DIR5 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIRO At reset x x 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description O OQ Q O Port 1 P1DIR7 P1DIR6 P1DIR5 P1DIR4 P1DIR3 P1DIR2 P1DIR1 P1DIR0 mode selection 0 Input mode 1 Output mode Port 1 Pull up Pull down Resistor Control Register P1PLUD 0x03F41 P1PLUD7 P1PLUD6 P1PLUD5 P1PLUD4 P1PLUD3
291. R Schmitt trigger input Port input data lt ESING 27 U R V A Reset g VLC1SL LCD output control amp D Q g Wek VR NA VLC1 Figure 4 4 7 Block Diagram P36 NY Rese R_ P3DWN Pull up pull down resistor selection 17 p V Rege e 3 P3PLUD7 gt Pull up pull down resistor control 10 direction control Port output data Port input data IV 38 Port 3 R 20 Fo e P3DIR7 R P30UT7 ead P3IN7 Figure 4 4 8 Block Diagram P37 Schmitt trigger input E Chapter 4 Ports 4 5 Port 5 4 5 1 Description General Port Setup To output data to pin set the control flag of the port 5 direction control register PSDIR to 1 and write the value of the port 5 output register PSOUT To read input data of pin set the control flag of the port 5 direction control register PSDIR to 0 and read the value of the port 5 input register PSIN Each bit can be set individually as either an input or output by the port 5 I O direction control register PSDIR The control flag of the port 5 direction control register PSDIR is set to 1 for output mode and 0 for input mode Each bit can be set individually if pull up resistor is added or not by the port 5 pull up resistor control register PSPLU Set the control flag of the port 5 pu
292. R W R W R W R W R W Port A pull up pull down selection 0 Pull up 1 Pull down Port 3 pull up pull down selection 0 Pull up 1 Pull down Port 9 pull up pull down selection 0 Pull up 1 Pull down Port 7 pull up pull down selection 0 Pull up 1 Pull down Port 1 pull up pull down selection 0 Pull up 1 Pull down Port 9 IV 69 Chapter 4 Ports IV 70 Port 9 Oscillation Switching Register XSEL 0x03F4C XI dual purpose selection 0 P90 1 low speed oscillation input XI Port 9 Chapter 4 Ports 4 7 3 Block Diagram Res 5 PODWN Pull up pull down resistor selection f Q Wok R V Pull up pull down resistor control WK VR direction control D Q wek VR Port output data sng I O 02 s gt P90 XI Schmitt trigger input Port input data lt lt R Es XISEL AE camp K R s Oscillation STOP signal circuit Clock input X XO Figure 4 7 1 Block Diagram P90 Port 9 IV 71 Chapter 4 Ports IV 72 48 4 8 1 Description General Pin Setup To output data to pin set the control flag of the port A direction control register PADIR to 1
293. RUCTION SET Mnemonic Operation Machine Code 6 7 8 MOVW imm16 Am imm16 Am 63 1101 111a H6 gt MOVW 5 3 3 0010 0000 100a MOVW An SP gt 5 33 0010 0000 101A MOVW DWn DWm DWn DWm 313 0010 1000 00 MOVW DWn Am DWnAm 313 0010 0100 11Da MOVW An DWm An gt DWm 3 3 0010 1100 11Ad MOVW An Am 313 0010 0000 00Aa PUSH PUSH Dn SP 15SP Dn meme8 SP 2 3 1111 10Dn PUSH An SP 2 SP Anmem16 SP 255 0001 011A POP POP Dn mem8 SP Dn SP 1 SP 213 1110 10Dn POP An mem16 SP An SP 2 5SP 2 4 0000 011A EXT EXT Dn DWm sign Dn 2DWm 3 3 0010 1001 000d Arithmetic manupulation instructions ADD ADD Dn Dm Dm Dn gt Dm 2 0011 0011 DnDm ADD imm4 Dm Dm sign imm4 Dm 2 1000 00Dm lt gt ADD imm8 Dm Dm imm8 Dm 4 2 0000 10Dm lt 8 gt ADDC ADDC Dn Dm Dm Dn CF gt Dm 3 2 0 0011 1011 ADDW ADDW DWn DWm DWm DWn gt DWm e 3 3 O 0010 0101 00Dd 4 ADDW DWn Am Am DWn gt Am 3 3 0010 0101 10Da ADDW imm4 Am Am sign imm4 gt Am 2 1110 110a lt 4 gt 6 ADDW imm8 Am Am sign imm8 Am 5 3 0010 1110 110a 4 8 gt 7 ADDW imm16 Am 16 gt 7 4 0010 0101 Olla H6 mE ADDW imm4 SP SP sign imm4 SP 3 2 1111 1101 lt gt 6 ADDW imm8 SP SP sign imm8 SP 4 2 1111 1100 lt 8 gt 7 ADDW imm16 SP SP imm16 SP 714 0010 1111 1100 H6 ADDW imm16 DWm DWm imm16 5DWm 4 0010 0101 0104 H6 ADDUW
294. Rear be e P pda III 41 3 9 I OVerVIeW Lc cec RD gae eto ade ie dite aed III 41 3 32 Block Diagram eee peter ie pate te e nent orte Hee eee de e ne III 42 3 3 3 Control Registers RE a mee III 46 3 3 4 Programmable Active Edge III 52 3 3 5 Both Edges Interr pt eee tere ete ee R ER III 53 3 3 6 Key Input Interr pt URP retur edito tete e eto ea eter eei eh III 55 3 37 Noise Filters zie tog pP OF eR e pate tee III 56 3 3 8 AC Zero Cross III 59 3 3 9 External Interrupt At The Standby Mode eere III 61 Chapter PO Ports er oce ge De aia psit IV 1 4 T Overview gau eb Rete ee ara RO IV 2 4 1 1 I O Port Overview iiie eite etie IV 2 4 12 I O Port Status at Reset e rtt ct te e eee IV 2 Contents 3 4 1 3 Control Regist rs ute Pep oe P as e e IV 3 4D Port ioa eo Re v uUo IV 5 4 2 I Descrhption eA Reel nad asia IER IRE RUE IV 5 4 2 2 RegIStets ite RU REOS PRENDE IV 7 4 2 3 Block eget te ep eret estere e E as IV 16 4 F e A ARR E RETOUR RUE e E IV 22 4 3 T DescriptiOb o ro IV 22 4 3 2 Registers oso ee eee IV 22 4 3 3 Block Diagr m n CH UO UR EIE p RUE ERE IV 23 AA S aee
295. Reception Timing parity bit is disabled XI 50 Operation Chapter 11 Serial interface 0 B Transfer Speed Setup Baud rate timer timer 1 timer 2 can set any transfer rate Table 11 3 20 shows the setup example of the transfer speed Table 11 3 20 UART Serial Interface Transfer Speed Setup Register Page Serial 0 clock source timer 1 timer 2 SCOMDS 10 Clock source dividing SCOMD1 10 Timer 1 clock source TM1MD V 15 Timer 1 compare register TM10C V 12 Timer 2 clock source TM2MD V 16 Timer 2 compare register 2 12 Timer compare register is set as follows baud rate 1 overflow cycle x 2 x internal clock dividing overflow cycle set value of compare register 1 x timer clock cycle therefore set value of compare register timer clock frequency baud rate x 2 x internal clock dividing 1 For example if baud rate should be 300 bps at timer clock source fs 4 fosc 8 MHz fs fosc 2 when the inter nal clock dividing is set to 8 set value should be as follows Set value of compare register 8 x 106 2 4 300 x 2 x 8 1 207 OxCF Timer clock source and the set value of timer compare register at the standard rate are shown in the following page 1 Transfer rate should not exceed 300 kbps Operation XI 51 Chapter 11 Serial interface 0 XI 52 Table 11 3 21 Setup Value of Serial Interface Transfer Speed 1 When Setting
296. Register SC3ICR The serial 3 interrupt control register SC3ICR controls interrupt level of serial 3 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 19 Serial Interrupt Control Register SC3ICR 0x03FF3 7 6 SC3LV1 SC3LVO 0 0 Description SC3LV1 Interrupt level flag SC3LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated 36 Control Registers Chapter 3 Interrupts A D Conversion Interrupt Control Register ADICR The A D conversion interrupt control register ADICR controls interrupt level of A D conversion interrupt inter rupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW 15 0 Table 3 2 20 A D Conversion Interrupt Control Register ADICR 0x03FF4 Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Inter
297. SC3IRQ is generated Chapter 3 3 1 4 Setup Note Procedures 1 to 2 5 6 and 7 can be set at the same time Note Procedures 8 and 9 can be set at the same time Operation XIII 29 Chapter 13 Serial Interface 3 XIII 30 For communication with 3 channels set the SC3BIS of the SC3MD1 register to 0 to set the serial input to 1 The 5813 pin can be used as a general port For reception only set the SC3SBOS of the SC3MD1 register to 0 to select port The 5803 pin can be used as a gen eral port For communication with 2 channels set the SBO3 pin to serial data I O The port direction control register P3DIR switches the I O For reception set the SC3SBIS of the SC3MD1 reg ister to 1 to select serial input The 5803 pin can be used as a general port This serial interface contains a force reset function If the communication should be stopped by force set SC3SBOS and SC3SBIS of the SC3MD1 register to 0 Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers refer to Table 13 2 1 except are set Transfer rate of transfer clock set by the SC3MD3 register should not exceed 5 0 MHz Operation Reception Setup Example The setup example for clock synchronous serial communication with serial 3 is shown Table 13 3 12 shows the conditions at recept
298. SCOMD1 0x03F92 SCOCMD 1 Select the clock frequency SCOMD1 0x03F92 SCOCKM 1 bp2 SCOMST 1 bp1 SCODIV 0 Control the pin function SCOMD 1 0x03F92 bp4 SCOSBOS 1 bp5 SCOSBIS 1 bp7 SCOIOM 0 9 Enable the interrupt SCORICR 0x03FEF bp1 SCORIE 1 SCOTICR OxOSFFO bp1 SCOTIE 1 b Set the PADIRO flag of the Port A pin direction control register PADIR to 1 and the PADIR1 flag to 0 to set to the output mode to the input mode 6 Set the SCOSTE flag of the SCOMDO register to 1 to enable start condition Set the SCODIR flag of the SCOMDO register to 0 to select MSB as first transfer bit 7 Set the SCOBRKE flag of the SCOMD2 register to 0 to select the serial data transmission Set the SCOPM1 to 0 flag of the SCOMD register to 00 to select 0 parity and set the SCONPE flag to 0 to enable add parity bit Set the SCOFM1 to 0 flag of the SCOMD2 register to 11 to select 8 bits 2 stop bits for the flame mode 8 Set the SCOCMD flag of the SCOMD1 register to 1 to select duplex UART Set the SCOCKM flag of the SCOMD1 register to 1 to select divided at source clock Set the SCODIV flag to 0 to select divided by 8 as the source clock The SCOMST flag should always be set to 1 to select clock master Set the SCOSBOS SCOSBIS flag of the SCOMD1 register to 1 to set the RXDO pin to serial data output and the RXDO pin to serial data input
299. SCOTICR OxOSFFO bp1 SCOTIE 1 SCOTIR 0 11 Start the serial Reception dummy data gt 0 03 97 Received data input SBIO pin 6 Set the PADIR2 PADIRO flag of the Port A pin direction control register PADIR to 1 1 and the PADIR1 flag to to set PA2 PAO to the output mode to the input mode 7 Set the SCOLNG2 to 0 flag of the serial 0 mode register 0 SCOMDO to 111 to set the transfer bit count as 8 bits Set the SCOSTE flag of the SCOMDO register to 0 to disable the start condition Set the SCODIR flag of the SCOMDO register to 0 to set MSB as a transfer first bit Set the SCOCE1 flag of the SCOMDO register to 1 to set the reception data input edge falling and the transmission data output edge rising 8 Set the SCOCMD flag of the SCOMD1 register to 0 to select the synchronous serial Set the SCOMST flag of the SCOMD1 register to 0 to select the clock slave external clock Set the SCOCKM flag to 0 to select not divided for the clock source Set the SCOSBOS SCOSBIS SCOSBTS flag of the SCOMD1 register to 1 to set the SBOO pin to the serial data output the SBIO pin to the serial input SBTO pin to the transfer clock input output Set the SCOIOM flag 0 to set the serial data input from the 5810 pin 9 Set the interrupt level by the SCOTLV1 to 0 flag of the serial 0 UART transmission interrupt control register SCOTICR 10 Set the SCOTIE fla
300. SEG1 P76 KEY6 RXDOB SBIOB SDA4B gt 39 22 4 gt SBT1B PAG ANG6 SEGO P77 KEY7 SBTOB SCLAB lt gt 40 21 TXD1B SBO1B PA5 AN5 0 0 lt 41 20 gt RXD1B SBI1B PA4 AN4 COM1 P31 SBI3 42 MN101C78A 19 4 gt PA3 AN3 COM2 P32 SBT3 SCL3 lt gt 43 48 pin LCD version 18 lt SBTOA PA2 AN2 COM3 P33 SB03 SDA3 lt gt 44 17 lt RXDOA SBIOA PA1 AN1 P34VLC3 lt 45 16 lt P35 VLC2 lt 46 15 P36 VLC1 4 47 14 lt P11 SCL4A 37 gt 48 13 4 gt P10 SDA4A e QG Nos CRPPUDDOEROE UR O O x LE o a J 56456 SESE Euer Figure 1 3 1 Pin Configuration 48TQFP TOP VIEW 10 Pin Description Chapter 1 Overview 28 SEG9 P16 TM21O RXD1A SBIHA 27 SEG10 P15 TMOOB TXD1A SBO1A 26 lt gt SEG11 P14 TMOIO RMOUT 25 4 gt NBUZZER P13 TM7IO CLKOUT 24 lt gt BUZZER P12 TM8IO 31 lt gt SEGO P71 KEY1 TMS3IO 23 lt gt P56 IRQ2 30 lt SEG7 P70 KEYO TM11IO 29 lt gt SEG8 P17 SBT1A TM20B 33 lt gt SEG4 P73 KEY3 32 SEG5 P72 KEY2 SEG3 P74 KEYA lt 34 22 4 gt P55 IRQ1 ACZ1 SEG2 P75 KEY5 TXDOB SBOOB 35 21 lt P54 IRQO ACZO SEG1 P76 KEY6 RXDOB SBIOB SDA4B lt 36 20 VDD SEGO P77 KEY7 SBTOB SCLAB lt 37 19 lt gt
301. SL3 0 1111 5 Set the LCD panel display data 5 Display 23 on the display panel by the address X 2E00 Segment output latch SEG1 0 to X 2E03 of the segment output latch SEG7 to SEGO X 2E00 31 Chapter 16 4 3 1 2 duty Segment output latch SEG3 2 X 2E01 X 22 Segment output latch SEG5 4 X 2E02 X 30 Segment output latch SEG7 6 X 2E03 32 6 Start the LCD operation 6 Set the LCDEN flag of the LCD mode control register1 LCDMD1 X 3FD0 LCDMD1 to 1 to start the LCD operation bp7 LCDEN 1 XVI 26 Display Chapter 16 LCD 16 4 5 1 3 duty B 1 3 duty MN101C78 SegmentLatch 0 0 bit7 bit3 COM3 open bit6 bit2 COM2 bit5 bit1 bit4 bitO COMO 5 4 SEG3 SEG2 electrode electrode Bl Light OFF LCDPANEL LCD ON COM S COM S LCD OFF SEG S SEG S SEG N SEG N LCD clock uncertain Data 1 0 uncertain Vici COM Vic2 Vica Vss Vici SEG Vic2 Vica Vss comsegG 1 3Vicp 0 1 3Vicp Light ON Light OFF Light OFF Light OFF Light OFF S selected voltage N non selected voltage driver voltage Display XVI 27 Chapter 16 LCD Frame cycle COM2 COM1 Vici Vic2 COMO Vic2 SEG5 1 3Vucp 0 1 3 ViCD 1 3
302. Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 5 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 0 TMOBAS 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop the timer 0 counting 2 Set the P10MDO flag of the port 1 output mode register P10MD to 1 to set P10 pin to the special function pin Set the P1DIRO flag of the port 1 direction control register P1DIR to 1 for the output mode Chapter 4 Ports 3 Set the TMOPWM flag of the TMOMD register to 1 and the TMOMOD flag to 0 to select the PWM operation 4 Select the prescaler output to the clock source by the TMOCK to 0 flag of the TMOMD register 5 Select fs 2 to the prescaler output by the TMOPSC1 to 0 and TMOBAS flag of the timer 0 prescaler selection register 8 bit PWM Output 99 Chapter 5 8 bit Timers Setup Procedure Description 6 Set the period of PWM H output 6 Set the period of PWM output to the timer 0 compare TMOOC 0x03F52 20x40 register TMOOC The setting value is set to 256 4264 0x40 because it should be the 1 4 duty of the full count 256 At that time the timer 0 binary counter is initialized to 0 00 7 Start the timer operation 7 Set the TMOEN flag of the TMOMD register to 1 to TMOMD 0x03F54 operate the timer 0 bp3 TMOEN 1 The initial setting of PW
303. T baud rate timer Square wave output Event count Cascade connection to timer 0 Clock source fosc fosc 4 fosc 16 fosc 64 fosc 128 fs 2 fs 8 fx external clock Timer 2 8 bit timer for general use or UART baud rate timer Square wave output PWM output Event count Simple pulse width measurement Clock source fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 fx external clock Added pulse 2 bit system PWM P52 of the large current pin TM2OA or P16 2 for PWM output Hardware Functions Chapter 1 Overview Timer 3 8 bit timer for general use Square wave output Event count Cascade connection to timer2 Clock source fosc fosc 4 fosc 16 fosc 64 fosc 128 fs 2 fs 8 fx external clock Timer 6 8 bit timer for general use Combined with time base timer it can be set to measure one minute intervals Clock source fosc fs fx time base output 1 2 or 1 2 Timer 7 16 bit timer for general use Square wave output P51 of the large current pin TM7O for PWM output and IGBT control output Duty Cycle continuous variable Event count Pulse width measurement Input capture Cascade connection to timer 8 32 bit timer 32 bit PWM input capture can be used Clock source 1 1 1 2 1 4 1 16 of any one of fosc fx or external clock Timer 8 16 bit timer double buffering Square wave output P53 of the large current pin TM8O for PWM output Duty continuous variable Event count pulse width measurement Input capture
304. T2 T7CAPC VI 19 HOT D LR 0 0 0 0 1 shot Dead Capture BC clear pulse time trigger control selection selection selection at cap ture OxO3F6F TM8MD4 T8ICT2 T8CAPC VI 23 LR 0 0 2 P Capture BC clear trigger control selection at cap ture OxO3F70 TM7BCL TM7BCL TM7BCL TM7BCL TM7BCL TM7BCL TM7BCL TM7BCL TM7BCL VI 11 7 6 5 4 3 2 1 0 x x x x x x x x Timer 7 binary counter lower 8 bits 0x03F71 TM7BCH TM7BCH TM7BC TM7BC TM7BC TM7BC TM7BC TM7BC TM7BC VI 11 7 H6 H5 H4 H3 H2 H1 HO x x x x x x x x Timer 7 binary counter upper 8 bits 0x03F72 TM7OC1L TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 VI 9 L7 L6 L5 L4 L3 L2 L1 0 x x x x x x x x Timer 7 compare register 1 lower 8 bits 0x03F73 TM7OC1H TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 TM7OC1 VI 9 H7 H6 H5 H4 H3 H2 H1 H0 x x x x x x x x Timer 7 compare register 1 upper 8 bits Special Function Registers List XVII 15 Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x03F74 TM7PR1L TM7PR1 TM7PR1 TM7PR1 TM7PR1 TM7PR1 TM7PR1 TM7PR1 TM7PR1 VI 10 L7 L6 L5 L4 L3 L2 L1 LO x x x x x x x x Timer 7 preset register 1 lower 8 bits 0x03F75 TM7PR1H TM7PR1 TM7PR1 TM7PR1 TM7PR1 TM7PR1
305. TM7CK1 0 00 bp3 2 TM7PS1 0 01 5 Select IGBT timer startup factor TM7MD3 0x03F8E bp1 0 T7IGBT1 0 00 6 Set the interrupt generation cycle TM7PR1 0x03F75 0x03F74 0 03 7 7 Set the interrupt level TM7ICR 0x03FED bp7 6 TM7LV1 0 10 8 Enable the interrupt TM7ICR 0xOSFED bp1 TM7IE 1 9 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD to 0 to stop the timer 7 counting 2 Set the TM7IE flag of the TM7CIR register to 0 to disable the interrupt 3 Set the TM7BCR flag of the timer 7 mode register 2 TM7MD2 to 1 to select the compare match to the binary counter clear source 4 Select fosc to the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Besides select 1 2 fosc to the count clock source by the 7 51 to 0 flag b Set IGBT timer startup factor to timer 7 count operation 6 Set the interrupt generation cycle to the timer 7 preset register 1 TM7PR1 The cycle is 1000 The set value should be 1000 1 999 0x03E7 At the time the same value is loaded to the timer 7 compare register 1 TM7OC1 and the timer 7 binary counter TM7BC is initialized to 0x0000 7 Set the interrupt level by the TM7LV1 to 0 flag of the timer 7 interrupt control register TM7ICR If the interrupt request flag is already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 8 Set the TM7IC flag o
306. TO reception data input AN1 AN1 Analog 1 input PA2 SBTOA AN2 in out PADIR2 PAPLU2 SBTOA Serial interface 0 clock I O AN2 Analog 2 input PA3 in out PADIR3 __ PAPLUS Analog 3 input 4 in out PADIR4 PAPLUA Analog 4 input 74 SBI1B RXD1B SBI1B Serial interface 1 data input RXD1B UART1 reception data input PA5 SBO1B TXD1B in out PADIR5 PAPLUS5 SBO1B Serial interface 1 TXD1B UART1 transmission data 1 transmission data output output AN5 5 Analog 5 input PA6 58118 AN6 in out PADIR6 PAPLU6 SBT1B Serial interface 1 clock I O AN6 Analog 6 input 1 1 Not available for 44 pin QFP package Pin Description 13 Chapter 1 Overview 1 3 3 Pin Functions Table 1 3 2 Pin Functions TQFP48 QFP44 Name Pin Pin No Other Function Function Description Vss 5 5 Map 8 23 8 20 Vref 15 15 Power supply pins Supply 1 8 V to 3 6 V to Vpp and 0 V to Vss For MN101CF78A supply 2 7 V to 3 6 V to 0501 7 7 0562 6 6 Input Output Clock input pins Clock output pins Connect these oscillation pins to ceramic or crystal ocsillators for high frequency clock operation If the clock is an external input connect it to 0561 and leave OSC2 open The chip will not operate with an external clock when using either the STOP or SLOW modes XI 9 9 XO 10 10 Input Output P90 Clock input pins Clock output pins C
307. Table 4 7 1 shows the registers that control the port 9 Table 4 7 1 Port 9 Control Register Registers Address Function Page P9OUT 0x03F19 Port 9 output register 67 0 03 29 Port 9 input register P9DIR 0x03F39 Port 9 direction control register P9PLUD 0x03F49 Port 9 pull up pull down resistor control register SELUD 0x03F4B Pull up pull down resistor selection register XSEL 0x03F4G Port 9 oscillation switching register R W Readable Writable Port 9 output register P OUT 0x03F19 P9OUTO X Output data 0 Output L VSS level 1 Output H VDD level O gt O Q O P9OUTO Port 9 IV 67 Chapter 4 Ports IV 68 Port 9 Input Register P9IN 0x03F29 bp O Q O Input data 0 Pin is L VSS level 1 Pin is H VDD level Flag P9DIRO At reset 2 2 0 Access R W bp O IS OQ Q O Port 9 P9DIR0 mode selection 0 Input mode 1 Output mode Port 9 Pull up pull down Resistor Control Register P9PLUD 0x03F49 Chapter 4 Ports P9PLUDO 1 O O Q O Pull up pull down resistor selection 0 Not added 1 Added Flag PADWN P3DWN P9DWN P7DWN P1DWN At reset 1 1 1 0 0 Access
308. UART Inter Clock to Divided by 8 decimal Transfer speed bit s 300 960 1200 2400 4800 fosc Clock source MHz Timer Set value Calculate Set value Calculate Set value Calculate Set value Calculate Set value Calculate d value d value d value d value d value 2 00 fosc 129 962 103 1202 51 2404 25 4808 fosc 4 103 300 25 1202 12 2404 fosc 16 25 300 fosc 32 12 300 fosc 64 fs 2 103 300 25 1202 12 2404 fs 4 51 300 12 1202 4 00 fosc 207 1202 103 2404 51 4808 fosc 4 207 300 64 962 51 1202 25 2404 12 4808 fosc 16 51 300 12 1202 fosc 32 25 300 fosc 64 12 300 fs 2 207 300 64 962 51 1202 25 2404 12 4808 fs 4 104 297 25 1202 12 2404 4 19 fosc 217 1201 108 2403 54 4761 fosc 4 217 300 67 963 fosc 16 16 963 6 2338 fosc 32 fosc 64 fs 2 217 300 67 963 fs 4 108 300 33 963 13 2338 8 00 fosc 207 2404 103 4808 fosc 4 129 962 103 1202 51 2404 25 4808 fosc 16 103 300 25 1202 12 2404 fosc 32 51 300 12 1202 fosc 64 25 300 fs 2 129 962 103 1202 51 2404 25 4808 fs 4 207 300 64 962 51 1202 25 2404 12
309. V0 TBIE TBIR III 29 0 0 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag 0 0 TM7ICR TM7LV1 TM7LVO TMOIE TMOIR 11 30 0 0 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag 0x03FE T7OC2ICR T7OC2L T7OC2L T7OC2l T7OC2l 31 V1 VO E R 0 0 i P 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag Ox03FEF SCORICR SCORLV SCORLV SCORIE SCORIR III 32 1 0 0 0 i 3 i 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag Ox03FFO SCOTICR SCOTLV1 SCOTLV SCOTIE SCOTIR III 33 0 0 0 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag OxOSFF1 5 SC1RLV SCORIE SCORIR 11 34 1 0 0 0 i 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag OxOSFF2 SCITICR SC1TLV1 SC1TLV SC1TIE SC1TIR III 35 0 0 0 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag Ox03FF3 SCSICR SC3LV1 SC3LVO SC3IE 5 11 36 0 0 5 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag XVII 26 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
310. Voie 3 0 Io 22 0 mA 5 0 4 pin 7 P56 PAO to PA6 P30 to P37 Schmitt trigger input 49 Input high voltage 0 8 l 50 Input low voltage 0 5 0 2Vpp 51 Input leakage current V I 0 V to Vpp 2 uA Vpp 3 0 Vi Vss 52 Pull up resistor RH7 Pull up resistor ON 30 100 300 53 Output high voltage Vpp 23 0 2 0 mA 2 4 V 54 Output low voltage Vpp 3 0 1 2 0 0 4 pin 8 P50 to P53 Schmitt trigger input 55 Input high voltage Vins 0 8Vpp 56 Input low voltage Vig 0 0 2Vpp 57 Input leakage current Vi 0 V to Vpp z 2 3 0 Vi V DD I Vss 58 Pull up resistor RH8 Pull up resistor ON 30 100 300 59 Output high voltage Vous 3 0 2 0 mA 2 4 Output low voltage V 3 0 lg 22 0 mA 2 60 output at 2 mA TERR pp 3 0 loL 2 0 m 04 v 6 Output low voltage V erm 64 output at 8 mA ket Op enm Display output pin 1 to 62 Output impedance ZocoMi Vpp 3 0 10 HA 5 0 6 V Display output pin 2 SEGO to SEG11 63 Output impedance Zosea1 3 0 2 s 0 6 V Display power pin 1 Vi c4 Vi c2 Vi 64 25 142 5 285 570 65 Internal dividing resistor 2 2272 Between Vic Vss 15 30 60 8 However COMO to are also used as P30 to P33 9 However SEGO to SEG11 are also used
311. W Myo x W indui OI8NL a v n a s s s x 5 SM 5 xk 4 n n yew jq p IW 989 4 1 eda eqwew L i HIOOSWL x pt dino 91 WK zdaza nsw T c N39I8L 210181 4 0 od aan arqesip arqeue Areas Wedel 104 081 uopesado andeo v awe ASWMd8L 13481681 jes eud 91 x JESUS V n x X n Ns n W n uonoeap lt payloads N3OI8L TOIL 1815881 amde g 110181 91 LLOIBL 019181 010181 19661 9 o 1da zaWaw AWSHOBWL 09039181 1 T epeoseo WL OL x 19030181 imak eda je W SVOSWL iagram 8 Block D 6 1 2 Timer Figure VI 5 Overview Chapter 6 16 bit Timers VI 6 6 2 Control Registers Timer 7 contains the binary counter TM7BC the compare register 1 TM7OC1 with its double buffer preset register 1 TM7PR1 the compare register 2 TM7OC2 with its double buffer preset register 2 TM7PR2 the capture register TM7IC the dead time preset register 1 TM7DPR1 and the dead time preset register 2 TM7DPR2 Timer 7 is controlled by the mode re
312. WE flag so that interrupt request flag can not be rewritten by the software 6 Set the interrupt level by the xxxLV1 0 flag of the interrupt control register XxxICR Set the IM1 0 flag of PSW then the interrupt acceptance level of CPU should be changed 7 Set the xxxIE flag of the interrupt control register xxxICR to enable the interrupt 8 Enable all maskable interrupts PSW bp6 MIE 1 Overview 3 2 Control Registers 3 2 1 Registers List Chapter 3 Interrupts Table 3 2 1 Interrupt Control Registers Register Address Functions NMICR OxOSFE1 Non maskable interrupt control register IRQOICR OxOSFE2 External interrupt O control register IRQ1ICR External interrupt 1 control register IRQ2ICR 4 External interrupt 2 control register IRQ4ICR External interrupt 4 control register TMOICR 7 Timer 0 interrupt control register Timer 0 compare match TM1ICR 0x03FE8 Timer 1 interrupt control register Timer 1 compare match TM2ICR OxOSFE9 TMSICR OxOSFEA Timer 3 interrupt control register Timer 3 compare match TM6ICR 0x03FEB Timer 2 interrupt control register Timer 2 compare match Timer 6 interrupt control register Timer 6 compare match TBICR TM7ICR 0x03FED Time base interrupt control register Time base per
313. X 11 6 Start the LCD operation 6 Set the LCDEN flag of the LCD mode control register LCDMD1 X 3FCO0 LCDMD 1 to 1 to start the LCD operation bp7 LCDEN 1 Display XVI 23 Chapter 16 LCD 16 4 3 1 2duty 1 2 duty MN101C78 SegmentLatch 0 bit7 bit3 0 bit6 bit2 bit5 bit1 bit4 bitO SEG6 SEG5 SEG3 2 A electrode B electrode Light OFF LCDPANEL LCD ON COM S COM S COM N LCD OFF SEG S SEG S SEG N SEG N LCD clock mern Data uncertain Vici Mp de deeem COM Vice Vic3 4 Led Vss SEG 55 Vicp 1 2Vicp COM SEG 0 1 2 Light ON Light Light OFF Light OFF Light OFF S selected voltage N non selected voltage driver voltage XVI 24 Display Frame cycle Vict Vice Vica Vici COMO Vicez Vica Vss Vici paeem Vice Vica Vss 4 VLCD 1 2 A electrode i 1 0 COM1 SEG6 eee u ee 1 2 VLCD VLCD 4 CONCERN 1 2 B electrode _ 0 COMO SEG6 TENES 1 2 Light OFF Light FR Figure 16 4 2 LCD Display
314. XDO 3 channels type gt 2 channels type O SBOO SBTO 1 channel type TXDO Specification of transfer bit count Frame 1 to 8 bits 7 bit 1STOP selection 7 bit 28TOP 8 bit 1STOP 8 bit 25 Selection of parity bit O Parity bit control 0 parity 1 parity odd parity even parity Selection of start condition Only enable start condition is available Specification of the first transfer bit O Specification of input edge output edge 5800 output control after final data is H L final data hold transferred Function in STANDBY mode Only slave reception is available Internal clock Not divided Divided by 8 Divided by 8 Divided by 16 Divided by 16 Overview Chapter 11 Serial interface 0 Clock source fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 External clock Timer 1 output Timer 2 output fosc 2 fosc 4 fosc 16 fosc 64 fs 2 15 4 Timer 1 output Timer 2 output Maximum transfer rate 5 0 MHz 300 kbps fosc Machine clock High speed oscillation fs System clock Overview XI 3 Chapter 11 Serial interface 0 Block Diagram 11 1 2 Serial interface 0 Block Diagram
315. XIII 6 2 1 0 0 0 0 0 1 1 1 Clock Transmis Transfer Start Synchronous transfer bit specifica synchro sion bit speci condi tion nous Recep fication tion transmis tion selection sion edge serialbus selection status 0x03FA1 SC3MD1 SC3IOM SC3SBT SC3SBI SC3SBO SC3MST XIII 7 S S S 0 0 0 0 0 Serial SBT3 Serial SBO3 Clock data function input function master input selection control selection Slave selection selection OxO3FA2 SC3MD3 SC3FDC SC3FDC SC3PSC SC3PSC SC3PSC SC3PSC XIII 8 1 0 E 2 1 0 0 0 0 0 0 0 Output selection after Prescale Selection clock SBO final data trans r count mit control Special Function Registers List XVII 21 Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3FA3 SC3STR SC3TEM XIII 9 P 0 Transfer buffer empty flag OxO3FA4 TXBUF3 TXBUF3 TXBUF3 TXBUF3 TXBUF3 TXBUF3 TXBUF3 XIII 5 7 6 5 4 3 2 1 0 x x x x x x x x Serial interface 3 transmission data buffer OxO3FA5 SC3TRB SC3TRB SC3TRB 5 SC3TRB SC3TRB SC3TRB SC3TRB SC3TRB XIII 5 7 6 5 4 3 2 1 0 x x x x x x x x Serial interface 3 reception data buffer OxO3FA6 SC3CTR IIC3BSY IIC3STC IIC3STP IIC3TMD IIC3REX SC3CM SC3ACK 5
316. a Rosa Laguna 4026 the Philippines Tel 63 2 520 8615 China Sales Office Panasonic Industrial Shanghai Co Ltd Floor 12 China Insurance Building 166 East Road Lujiazui Pudong New District Shanghai 200120 China Tel 86 21 6841 9642 86 21 6841 9631 Panasonic Industrial Tianjin Co Ltd PI TJ Room No 1001 Tianjin International Building 75 Nanjin Road Tianjin 300050 China Tel 86 22 2313 9771 Fax 86 22 2313 9770 Panasonic SH Industrial Sales Shenzhen Co Ltd PSI SZ Shum Yip Centre Office 25F Shum Centre 5045 East Shennan Road Shenzhen China Fax 65 6390 3689 PICM Fax 60 4 261 9989 PICT Fax 63 2 520 8629 PI SH Tel 86 755 8211 0888 86 755 8211 0970 Panasonic Shun Hing Industrial Sales Hong Kong Co Ltd PSI HK 11th Floor Great Eagle Center 23 Harbour Road Wanchai Hong Kong Tel 852 2529 7322 Taiwan Sales Office Fax 852 2865 3697 Panasonic Industrial Sales Taiwan Co Ltd PIST Head Office 6F 550 Sec 4 Chung Hsiao E RD Taipei 110 Taiwan Tel 886 2 2757 1900 886 2 2757 1906 Kaohsiung Office 6th Floor Hsin Kong Bldg No 251 Chi Hsien 1st Road Kaohsiung 800 Taiwan Tel 886 7 346 3815 Fax 886 7 236 8362 Korea Sales Office Panasonic Industrial Korea Co Ltd PIKL Kukje Center Bldg 11th Floor 191 Hangangro 2ga Youngsan ku Seoul 140 702 Korea Tel 82 2 795 9600 Fax 82 2 795 1542 Semiconductor Company Matsushita E
317. a should be read out from the received data buffer RXBUFO after recovering to NORMAL mode In STANDBY mode reception with start condition is not available thus disable start condition And set dummy data to tramsmission data buffer TXBUFO before transition to STANDBY mode XI 28 Normal mode Standby mode Normal mode a a Oscillation M Stabilization wait Clock SBTO pin Input pin SBIO SBOO pin Transfer bit counter SCORBSY Data set to TXBUFO A Interrupt SCOTIRQ Figure 11 3 16 Reception Timing at Standby Mode Reception at rising edge start condition is disabled Operation B Pins Setup with channels at transmission Chapter 11 Serial interface 0 Table 11 3 7 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO SBTO pin at transmission Table 11 3 7 Setup for Synchronous Serial Interface Pin with 3 channels at transmission PAPLU PAPLUO P7PLU P7APLUS Setup item Data output pin Data input pin Clock pin SBOOA pin SBIOA pin SBTO pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin 75 1 76 2 77 Port pin setup Select pin A B SCSEL SCOSL Serial data input SBIO selection SCOMD1 SCOIOM Function Serial data output 1 input Transfer clock I O Tran
318. able interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers III 29 Chapter 3 Interrupts Timer 7 Interrupt Control Register TM7ICR The timer 7 interrupt control register TM7ICR controls interrupt level of timer 7 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 13 Timer 7 Interrupt Control Register TM7ICR 0x03FED 7 6 TM7LV1 TM7LVO 0 0 Description TM7LV1 Interrupt level flag TMOLVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated 30 Control Registers Chapter 3 Interrupts Timer 7 Compare Register 2 match Interrupt Control Register T7OC2ICR The timer 7 compare register 2 match interrupt control register T7OC2ICR controls interrupt level of timer 7 compare register 2 match interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 14 Timer 7 Compare Register 2 match Interrupt Control Register T7OC2ICR 0x03FEE
319. ag When the SCOSBIS flag of the SCOMDI register is set to serial data input and the data is set to TXBUFO or the start condition is recognized the BUSY flag SCORBSY of the SCOSTR register is set to 1 The flag is cleared to 0 after the communication complete interrupt SCOTIRQ is generated During continuous communication the SCORBSY flag is always set If the transmission buffer empty flag SCOTEMP is cleared to 0 as the communi cation complete interrupt SCOTIRQ is generated SCORBSY is cleared to 0 If the SCOSBIS flag is set to 0 during communication the SCORBSY flag is cleared to 0 Operation Chapter 11 Serial interface 0 B Transmission BUSY Flag When the SCOSBOS flag of the SCOMDI register is set to serial data output and the data is set to TXBUFO the start condition is recognized the SCOTBUSY flag of the SCOSTR register is set if the SCOSBOS flag of the SCOMDI register is 1 The flag is cleared to 0 after the communication complete interrupt SCOTIRQ is gen erated During continuous communication the SCOTBSY flag is always set If the transmission buffer empty flag SCOTEMP is cleared to 0 as the communication complete interrupt SCOTIRQ is generated SCOTBSY is cleared to 0 If the SCOSBOS flag is set to 0 during communication the SCOTBSY flag is cleared to 0 B Forced Reset This serial interface contains forced reset for abnormal operation For forced reset the SCOSBOS flag and the SCOSB
320. ag of the SC1MD3 register to 1 to SC1MD3 0x03F9C select prescaler operation bp3 SC1PSCE 1 2 Select the clock source 2 Set the SC1PSC2 to 0 flag of the SC1MDS3 register to SC1MD3 0x03F9C 100 to select fs 2 as the clock source bp2 0 SC1PSC2 0 100 3 Select the used pin 3 Set the SC1SL flag of the SCSEL register to 0 to select SCSEL 0x03F90 A port 1 as I O pin bp1 SC1SL 0 4 Control the pin style 4 Set the P1ODC7 P10DC5 flag of the P1ODC register to P10DC 0x03F 1B 1 to select Push pull to SBT1 pin Set the bp7 P10DC7 0 P1PLUD7 P1PLUD5 flag of the P1PLUD register to 1 bp5 P10DC5 0 to enable the pull up resistor P1PLUD 0x03F41 bp7 P1PLUD7 0 bp5 P1PLUD5 0 Operation XII 39 Chapter 12 Serial interface 1 Setup Procedure Description 5 Control the pin direction P1DIR 0x03F31 bp7 P1DIR7 0 bp6 P1DIR6 0 bp5 P1DIR5 1 6 Select the transfer bit count SC1MD0 0x03F99 bp2 0 SC1LNG2 0 111 7 Select the start condition SC1MDO 0x03F99 bp3 SC1STE 0 8 Select the first bit to be transferred SC1MD0 0x03F99 bp4 SC1DIR 0 9 Select the transfer edge SC1MD0 0x03F99 bp7 SC1CE1 1 10 Select the communication type SC1MD1 0x03F9A SC1CMD 0 11 Select the transfer clock SC1MD1 0x03F9A bp2 SC1MST 0 bp3 SC1CKM 0 12 Control the pin function SC1MD1 0x03F9A bp4 SC1SBOS 0 bp5 SC1SBIS 1 bp6 SC1SBTS 1 bp7 SC1IOM 0 13 S
321. al interrupt pin as well P56 is used as the external interrupt pin as well P54 is used as input pin of the AC zero cross 0 as well To read out the data of AC zero cross set the of the noise filter control register NFCTR to 1 and read out the value of port 5 input register PSIN P55 is used as input pin of the AC zero cross 1 as well To read out the data of AC zero cross set the bp7 of the noise filter control register NFCTR to 1 and read out the value of port 5 input register PSIN P50 is used as output pin of LEDO as well Each bit can be selected as output mode by bp4 of the port 5 output mode register PSOMD The port 5 output mode register is set to 1 for output pin of large current Nch Tr and 0 to use as output pin of general current The timer 0 output or the general port output can be set to large current with the combination of bpO of the port 5 output mode register P5OMD Port 5 IV 39 Chapter 4 Ports IV 40 P51 is used as output pin of LEDI as well Each bit can be selected as output mode by bp5 of the port 5 output mode register PSOMD The port 5 output mode register PSOMD is set to 1 for output pin of large current Nch Tr and 0 to use as output pin of general current The timer 0 output or the general port output can be set to large current with the combination of of the port 5 output mode register P5OMD P52 is used as outp
322. and reception are executed at the same time set the start condition to disable to prevent abnormal operation 5871 pin Data is received at the rising edge of clock SBI1 pin Data is output at the falling edge of clock Figure 12 3 14 Transmission Reception Timing Reception at rising edge Transmission at falling edge 5871 pin Data is received at the rising edge of clock SBI1 pin Data is output at the falling edge of clock SBO pin Figure 12 3 15 Transmission Reception Timing Reception at falling edge Transmission at rising edge XII 26 Operation Chapter 12 Serial interface 1 B Communication Function at Standby Mode This serial interface is capable of slave reception in STANDBY mode CPU operation status can be recovered from standby to normal by the communication complete interrupt SC1TIRQ that is generated after the slave reception In STANDBY mode continuous reception is disabled after data of transfer bit count set by SCILNG2 0 flags of the SCIMDO register is received The received data should be read out from the received data buffer RXBUFI after recovering NORMAL mode In STANDBY mode reception with start condition is not available thus disable start condition And set dummy data to transmission data buffer TXBUFI before transition to STANDBY mode Normal mode Standby mode Normal mode lt gt gt lt gt Oscillation T Stabilization wai
323. and write data to the port 8 output register PAOUT To read input data of pin set the control flag of the port A direction control register PADIR to 0 and read the value of the port A input register PAIN Each bit can be set individually to either an input or output by the port A direction control register PADIR The control flag of the port A direction control register PADIR is set to 1 for ouput mode and 0 for input mode Each bit can be set individually if pull up pull down resistor is added or not by the port A pull up pull down resistor control register PAPLUD Set the control flag of the port A pull up pull down resistor control register PAPLUD to 1 to add pull up pull down resistor The bp4 of the pull up pull down resistor selection register SELUD select if pull up resistor or pull down resis tor is added Each bit can be selected individually as input mode by the portA input mode register PAIMD The control flag of the portA input mode register PAIMD is set to 1 to input the special function data and 1 is read out from the portA input register PAIN and 0 to use as the general port For PA2 PAS and each bit can be selected individually as Nch open drain output by the port Nch open drain control register PAODC When the port A Nch open drain control register PAODC is set to 1 for Nch open drain output and to 0 for push pull output B Special Function Pi
324. ansmission data 2 Reception Enabled Input start condition 3 Set dummy data 2 Disabled Set dummy data 2 Transmission Enabled 4 Reception Disabled Set transmission data 2 Slave Transmission Enabled Input clock after transmission data is set 5 Disabled Input clock after transmission data is set 6 Reception Enabled Input clock after start condition is input 7 Input clock after dummy data is set 6 Disabled Input clock after dummy data is set 6 Transmission Enabled 4 Reception Disabled Input clock after transmission data is set 6 1 After the start condition output output the transfer clock 1 transfer clock later 2 After setting transmission data dummy data the transfer clock should be output after 3 5 transfer clock at the maximum The system configuratioin is needed so that the transmission data dummy data are written after the master receives the information of slave data load completion 3 After the start condition input output the transfer clock after 2 5 transfer clock at the maximum When receiving data continuously the system configuration is needed to notify the master of the readout completion Without the notification the data before readout may be overwritten 4 When the start condition is set to enable transmission and reception should not excuted at the same time 5 After setting the transmission data output the start condition and wait until the master excutes
325. ansmission of Confirming Bit of Data Reception Selection of enable disable of ACK bit is the same as the transmission When ACK bit is enabled ACK bit and clock are output after data 1 to 8 bits is received When the reception is continued ACK bit outputs L And when the reception is finished it outputs H The of the SC3CTR register sets the output ACK bit level Interrupt Data reception erio Bus release period To Tmax 1 2T m NACK ACK bit transfer clock UL Figure 13 3 19 Bit Transmission Timing after Reception of 8 Bit Data Operation XII 39 Chapter 13 Serial Interface 3 XIII 40 B Transfer Format There are two transfer format used on IIC bus are the addressing format that transmits receives data after 1 byte data address data that consists of slave address 7 bits and R W bit 1 bit 15 transferred after start condition and the free data format that transmits data right after the start condition The serial interface of this LSI supports 2 communication formats for only master transmission and master reception in IIC communication Sequence of communication is shown below The shaded part shows the data transferred from slave Start Stop c nditi n Slave address R W ACK Data ACK condition Start nO Stop condition Slave address R W ACK Data ACK condition Start Stop
326. anual MN101C78A F78A LSI User s Manual Record of Changes 1 MN101C78A F78A LSI User s Manual March 2004 1st Edition 3rd Printing Issued by Matsushita Electric Industrial Co Ltd O Matsushita Electric Industrial Co Ltd SALES OFFICES NORTH AMERICA U S A Sales Office Panasonic Industrial Company New Jersey Office 2 Panasonic Way Secaucus New Jersey 07094 U S A Tel 1 201 348 5257 Fax 1 201 392 4652 Chicago Office 1707 Randall Road Elgin Illinois 60123 7847 U S A Tel 1 847 468 5720 Fax 1 847 468 5725 San Jose Office 2033 Gateway Place Suite 200 San Jose California 95110 U S A PIC Tel 1 408 487 9510 Atlanta Office 1225 Northbrook Parkway Suite 1 151 Suwanee Georgia 30024 U S A Fax 1 408 436 8037 Tel 1 770 338 6953 San Diego Office 9444 Balboa Avenue Suite 185 San Diego California 92123 U S A Fax 1 770 338 6849 Tel 1 858 503 2910 Canada Sales Office Panasonic Canada Inc PCI 5770 Ambler Drive 27 Mississauga Ontario LAW 2T3 Canada Tel 1 905 238 2243 Fax 1 905 238 2414 Fax 1 858 715 5545 LATIN AMERICA Mexico Sales Office Panasonic de Mexico S A de C V PANAMEX Amores 1120 Col Del Valle Delegacion Benito Juarez C P 03100 Mexico D F Mexico Tel 52 5 488 1000 Guadalajara Office Sucursal Guadarajara Av Lazaro Cardenas 2305 Local G 102 Plaza Comercial Abastos Col Las Torres Guadalajara Jal 44
327. aracter bit should be even 1 None Do not add parity bit Break Status Transmission Control Setup The SCIBRKE flag of the SC1MD2 register generates the brake status If SCIBRKE is set to 1 to select the brake transmission all bits from start bits to stop bits transfer 0 Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be deter mined by the SCIORE 5 SCIFEF flag of the SCISTR register Even one of those errors is detected the SCIERE flag of the SCISTR register is set to 1 Among reception error flags the SCIPEK and the SCIFEF flags are renewed when the reception complete interrupt SCI RIRQ is generated The SCIORE flag is cleared at the same time of next communication complete interrupt SCIRIRQ generation after the data of the RXBUFI is read out The decision of the received error flag should be operated before the next communication is finished Those error flag has no effect on communication operation Table 12 3 19 shows the list of reception error source Table 12 3 19 Reception Error Source of UART Serial Interface Flag Error SC1ORE Overrun error Next data is received before reading the receive buffer SC1PEK Parity error at fixed to 0 when parity bit is 1 at fixed to 1 When parity bit is 0 Odd parity The total of 1 of parity bit and character bit is even Even parity The total of 1
328. ared but other control regis ters hold their set values B Last Bit of Transmission Data Table 13 3 4 shows last bit data output holding time at transmission and the minimum data input time of the last bit at reception At slave internal clock setup is necessary to reserve data holding time at data transmission Operation XII 17 Chapter 13 Serial Interface 3 XIII 18 Table 13 3 4 Last Bit Data Length of Transmission Data at transmission Last bit data holding period at reception Last bit data input period At master 1 bit data length 1 bit data length min At slave 1 bit data length of external clock x 1 2 internal clock cycle x 1 2 to 3 2 When start condition is disabled SC3STE flag 0 SBO3 output after last bit data output hold time can be set with SC3FDCI 0 of the SC3MD3 register as shown in Table 13 3 5 After reset release output before serial transfer is regardless of the set value of SC3FDC1 0 flags When start condition is enabled SC3STE flag 1 H is output regardless of the set value of SC3FDC1 0 flags Table 13 3 5 SBOS Output after Last Bit Data Output Hold Time without start condition SBO3 output after last bit SC3FDC1 flag SCS3FDCO flag data output hold time 0 0 Fixed to 1 High output 1 0 Fixed to O Low output 0 1 Hold last data Reserved Operation Chapter 13 Serial Interface 3 Transmission Tim
329. as P14 to P17 and P70 to P77 10 The summation of 3 resistors among Vic and VI Vice and Vi and Vss Electrical Characteristics 1 31 Chapter 1 Overview 32 1 5 4 A C Converter Characteristics 40 to 85 Rating Parameter Symbol Conditions Unit MIN TYP MAX ACZ pin 1 Rising time trs 30 Figure 1 5 5 2 Falling time tis 30 trs Input voltage level 2 Input voltage level 1 Output tfs Figure 1 5 5 XI Timing Chart Electrical Characteristics 1 5 5 40 to 85 A D Converter Characteristics c Hd s lt Chapter 1 Rating Parameter Symbol Conditions Unit MIN TYP MAX 1 Resolution 10 Bits 2 Non linearity error 1 Vpp 3 0 V Vss 0 V 3 Differential non linearity 0 V _ LSB error 1 TAp 800 ns T 4 Zero transition voltage Vpp 3 0 V Vgg 0 V 30 100 V 3 0 V mV Full scale transition REF 5 voltage 800 ns 2900 2970 6 Tap 800 ns 12 25 A D conversion time B 7 1x232 768 kHz 15 26 _ _ 778 31 ms ms 8 Tap 800 ns 1 6 14 4 Sampling time fx 32 768 kHz Tap 15 26 9 ps n 3052 274 68 ms 10 Reference voltage VREF 2 0 Vpp V 11 Analog input voltage Vss VREF i Anal
330. at the Standby Mode External interrupt 0 to 2 It is possible to recover from the standby mode by the external interrupt At the standby mode an interrupt is generated when the value set to the external interrupt valid edge specify flag matches the external interrupt pin level Therefore be aware of the value of the external interrupt valid edge spec ify flag and the external interrupt pin level at the transition to the standby mode If the value set to the external interrupt valid edge specify flag matches the external interrupt pin level at the transition to the standby mode it recovers from the standby mode right away Setup Examples of the External Interrupt at the Standby Mode Recovery from STOP mode can be done by generation of the external interrupt 0 IRQO by the low level signal input from P54 An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Specify the interrupt valid edge 1 Set the REDGO of the external interrupt O control register IRQOICR 0x03FE2 IRQOICR to 0 to specify the interrupt valid edge to bp5 REDGO 0 the rising edge 2 Set the external interrupt pin 2 The value of the REDGO flag of the IRQOICR register The external interrupt O pin is pulled up in and the external interrupt pin level is different advance 3 Set the interrupt level 3 Set the interrupt level by the IRQOLV1 to 0 flag of the IRQOICR 0x03FE2 IRQOICR register bp7 6 IRQOLV
331. ate the timer 7 TM7BC counts up from 0x0000 At the timing of the rising edge of the external interrupt 0 input signal the value of TM7BC is loaded to the TM7IC register At that time the pulse width between rising edge of the external interrupt input signal can be measured by reading the value of the TM7IC register through interrupt service rou tine and calculating the difference between the capture values 16 bit Timer Capture Chapter 6 16 bit Timers 6 9 16 bit High Precision IGBT Output Cycle Duty can be changed consec utively High precision IGBT output starts counting by the external interrupt input signal as the trigger Startup trigger can be selected by the external interrupt 0 1 and 2 or starting of the timer 7 count operation When counting starts the operation is the same as the high precision PWM output 6 9 1 Operation rw aaAaAnMiAbBB amp klLiaiaLLAAiwiAAULAiLCG eLLUOALL A PC 4 W4W4LL EE AY IGBT Trigger Selection IGBT trigger can be selected from IRQO IRQ1 IRQ2 and the start of the timer 7 count operation Setup should be done at the and T7IGBTI flag of the TM7MD3 register When the startup is controlled from external of the microcontroller one of IRQO to IRQ2 should be selected This trigger detects the input level before activation Either L level can be selected with the T7IGBTTR flag of the TM7MD3 register When 1 the rising edge is
332. ation fosc 10 MHz One cycle of the PWM output waveform is decided by the overflow of the binary counter period of the output waveform is decided by the set value of the compare register 1 An example setup procedure with a description of each step is shown below TM7IO output Figure 6 6 4 Output Waveform of Setup Procedure Description 1 Stop the counter TM7MD 1 0x03F78 bp4 TM7EN 0 2 Set the special function pin to output P1OMD 0 0 1 bp3 P1OMD3 1 bp2 NBUZSEL 1 P1DIR 0x03F31 bp3 P1DIR3 1 3 Set the PWM output TM7MD2 0x03F79 bp4 TM7PWM 1 4 Set the standard PWM output TM7MD2 0x03F79 bp5 TM7BCR 0 5 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 00 6 Select IGBT timer startup factor TM7MD3 0x03F8E bp1 0 T7IGBT1 0 00 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Set the P10MD3 flag of the port 1 output mode register P10MD to 1 NBUZSEL flag to 1 to set the P13 pin as a special function pin Set the P1DIR3 flag of the port 1 direction control register P1DIR to 1 to set the output mode Chapter 4 Ports 3 Set the TM7PWM flag of the timer 7 mode register 2 TM7MD2 to 1 to select the PWM output 4 Set the TM7BCR flag of the TM7MD2 register to 0 to select the full count overflow as the binary counter clear source
333. be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 7 Timer 0 Interrupt Control Register TMOICR 0x03FE7 7 6 TMOLV1 TMOLVO 0 0 Description TMOLV1 Interrupt level flag TMOLVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated 24 Control Registers Chapter 3 Interrupts Timer 1 Interrupt Control Register TM1ICR The timer 1 interrupt control register TM1ICR controls interrupt level of timer 1 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 8 Timer 1 Interrupt Control Register TM1ICR 0x03FE8 7 6 TM1LV1 TM1LVO 0 0 TM1LV1 TM1LVO Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 25 Chapter 3 Interrupts Timer 2 Interrupt Control Register TM2ICR The timer 2 interrupt co
334. bel H PC 1100 if mem8 abs8 zimm8 PC 92 PC CBEQ imm8 abs8 label _ if mem8 abs8 imm8 PC 10 d1 t label eH9PC 1101 if mem8 abs8 4imm8 PC 10 PC imm8 abs16 label if mem8 abs16 imm8 PC 11 d7 label HPC 1100 if mem8 abs16 4imm8 PC 1 1 2PC CBEQ imm8 abs16 label if mem8 abs16 imm8 PC t2 d1 abel H3PC 1101 if mem8 abs16 zimm8 PC 122PC CBNE imm8 Dm label if Dmzimm8 PC 6 d7 label H2PC 10Dm 8 6 CBNE imm8 Dm label if Dm4imm8 PC 8 d1 1 label H2PC 10Dm 8 8 imm8 abs8 label _ if mem8 abs8 4imm8 PC 9 d7 label H PC 1110 if mem8 abs8 imm8 PC 92 PC CBNE imm8 abs8 label _ if mem8 abs8 4imm8 PC 10 d1 t label eH PC 1111 if mem8 abs8 imm8 PC 10 PC CBNE imm8 abs16 label if mem8 abs16 4imm8 PC 11 d7 label H PC 1110 if mem8 abs16 imm8 PC 1 1 2PC CBNE imm8 abs16 label if mem8 abst6 mm8 PC t2 d11 label H3PC 1101 1111 if mem8 abs16 imm8 PC 12PC TBZ abs8 bp label if mem8 abs8 bp 0 PC 7 d7 label H PC 0000 Obp if mem8 abs8 bp 1 PC 73PC TBZ abs8 bp label if mem8 abs8 p 0 PC 8 d1 1 label H PC 0000 1bp if memB8 abs8 bp 1 PC 82PC 1 d4sign extension 2 d7 sign extension 8 411 sign extension Instruction Set XVII 31 Chapter 17 Appendix XVII 32 MN101C SERIES INSTRUCTION SET Grou
335. binary counter should not be read out after the timer operation is stopped when setting the event input TMnIO input as the count clock source as the binary counter may reach to an unexpected value 16 bit Event Count Chapter 6 16 bit Timers Count Timing of Synchronous TMnIO Input Timer 7 Timer 8 If the synchronous TMnIO input is selected the synchronizing circuit output signal is input to the timer n count clock The synchronizing circuit output signal is changed at the falling edge of the system clock after the TMnIO input signal is changed The binary counter counts up at the falling edge of the synchronizing circuit output signal or the synchronizing circuit output signal that passed through the division circuit TMnIO input System clock fs Synchronous circuit output count clock TMnEN flag Compare N register 1 i Binary 0000 0001 0002 0000 counter Interrupt request flag Figure 6 4 2 Count Timing of Synchronous TMnlO Input Timer 7 Timer 8 The timer n binary counter counts up the binary counter at the signal in synchronization with the system clock so that correct value is read out from the timer n binary counter 16 bit Event Count VI 31 Chapter 6 16 bit Timers VI 32 Count Timing of TMnIO Input Both edges selected When TMnIO input is selected TMnIO input signal is input to the timer n count clock The binary counter counts up at the falling
336. bit value of compare register binary counter counts up until overflow once 3 When using as the 16 bit timer with cascade connection if the upper 8 bit value of binary counter reaches the upper 8 bit value of compare register binary counter is cleared as the lower 8 bit of binary counter overflows If the interrupt is enabled the timer interrupt request flag should be cleared before timer is started u When a timer interrupt request flag is generated up to 3 system clock is required for the next flag generation Even if the binary counter reaches the value in the compare register a timer interrupt request flag is not generated When is used as the clock source clear the binary counter before starting the timer opera tion Also when 0x00 is set to the compare register use the synchronous fx Y count operation it may not operate properly To prevent use synchronous fx a When fx is used as the count clock source and the compare register is rewritten during the pected value To prevent select synchronous fx input a When synchronous fx is used as the count clock source binary counter may reach to unex 8 bit Timer 23 Chapter 5 8 bit Timers 5 4 2 Setup Example Timer Operation Setup Example Timer 0 1 2 and 3 Timer function can be set by using timer 0 that generates the constant interrupt Interrupt is generated every 250 cycles 200 us by selecting fs 2 a
337. ble data Y Y 0 0 000 0 10000 Ox3BFFR Figure 2 2 1 Single chip Mode The value of internal RAM is uncertain when power is applied to it Y It needs to be initialized before used 17 Chapter 2 CPU Basics Special Function Registers 2 2 3 in I O spaces at the addresses 0 03 00 to LSI are located as shown below registers The MNIOIC series locates the special funct 1S ion registers of th memory space The special funct 1041002 22081 39798 391598 394498 3914108 3914098 3909 22041 HOIOIAL 310041 YOIWN 101009 4 CH1ONV IHLONV OHLONV 91997 21021 81007 3 1 18195
338. bs8 imm8 memg8 abs8 6 3 0001 0100 abs 8 gt lt 8 gt MOV 26512 8 gt 8 5512 7 3 0001 0101 abs 12 gt lt 8 gt MOV imm8 abs16 8 gt 8 5516 9 5 0011 1101 1001 abs 16 gt B gt MOV Dnmem8 HA 2 2 1101 00Dn MOVW MOVW An DWm mem16 An 2DWm ex esse Pe 9 FS 1110 MOVW mem16 An 2Am 0010 1110 10Aa 4 MOVW d4 SP DWm mem16 d4 SP gt DWm 3 3 1110 0114 lt d4 gt 2 MOVW d4 SP Am mem16 d4 SP Am REESE 1110 010a lt d4 gt 2 MOVW d8 SP DWm mem16 d8 SP DWm 5 4 0010 1110 0114 d8 gt 3 MOVW d8 SP Am 16 98 5 gt 5 4 0010 1110 010a lt 8 gt 3 MOVW d16 SP DWm mem16 d16 SP DWm 7 5 0010 1110 0014 di 6 ENS MOVW d16 SP Am 16 416 5 7 5 0010 1110 000a di6 gt MOVW abs mem16 abs8 gt DWm 4 3 1100 0114 abs 8 gt MOVW abs8 mem16 abs8 Am 41 3 1100 010a abs 8 gt MOVW abs16 DWm memt6 abs16 DWm 7 5 0010 1100 0114 abs 16 gt MOVW abs16 Am 16 6516 7 5 0010 1100 010a abs 16 gt MOVW DWn Am DWn mem16 Am 213 1111 00aD MOVW 16 3 4 0010 1111 108A 4 MOVW DWn d4 SP DWn gt mem16 d4 SP
339. ce Pin with 3 channels at transmission reception P1PLUD P1PLUD5 PAPLU PAPLUS Setup item Data output pin Data input pin Clock I O pin SBO1A pin SBO1B pin SBI1B pin SBT1A pin SBT1B pin Clock master Clock slave SC1SCMD1 SC1MST Port pin P15 PA5 P16 PA4 P17 PA6 Port pin setup Select used pin A B SCSEL SC1SL Serial data input SBI1 selection SC1MD1 SC1IOM Function Serial data output Serial input Transfer clock Transfer clock SC1MD1 SC1SBOS SC1MD1 SC1SBIS SC1MD1 SC1SBTS Style Push pull Nch open Push pull Nch open Push pull Nch open drain drain drain P10DC P10DC5 P1ODC P1ODC7 PAODC PAODC6 PAODC PAODC5 Input mode Output mode Input mode P1DIR P1DIR5 P1DIR P1DIR6 P1DIR P1DIR7 PADIR PADIR6 PADIR PADIRS5 PADIR PADIR4 Pull up setup Added Not added Added Not added Added Not added P1PLUD P1PLUD7 PAPLU PAPLU6 Operation B Pins Setup with 2 channels at transmission Table 12 3 10 shows the setup for synchronous serial interface pin with 2 channels SBOI pin SBT1 pin at trans mission SBII pin can be used as a port Chapter 12 Serial interface 1 Table 12 3 10 Setup for Synchronous Serial Interface Pin with 2 channels at transmission Setup item Data
340. ception data buffer RXBUFO is the spare buffer that pushed the received data in the internal shift register After the communication complete interrupt SCOTIRQ is generated all data stored in the internal shift register is stored to the received data buffer RXBUFO automatically RXBUFO can store data up to 1 byte RXBUFO is rewritten every time communication is completed Data of RXBUFO should be read out before the next reception is completed The received data buffer empty flag SCOREMP is set to 1 at the same time SCOTIRQ is gener ated SCOREMP is cleared to 0 after is read out Operation XI 15 Chapter 11 Serial interface 0 mission and reception should not be executed at the same time to prevent abnormal opera a When the start condition is set to enable in the clock synchronous communication trans tion If the start condition is input to restart during communication the transmission data is not valid Set the transmission data to TXBUFO again to operate the transmission again RXBUFO is rewritten every time when communication is completed At continuous communi cation data of RXBUFO should be read out by the time the next reception completes XI 16 Operation Chapter 11 Serial interface 0 B Transmission Bit Count and First Transfer Bit At transmission when the transfer bit count is 1 bit to 7 bits the data storing method to the transmission data buffer TXBUFO is different depending
341. chdog Timer Constant Clear Setup Example Setup Procedure Description 1 Set the watchdog timer for the constant clear 1 Clear the watchdog timer by the cycle from 218 x system Writing to WOCTR 0x03F02 clock c f BSET WDCTR WDEN The watchdog timer clear should be inserted in the bp0 WDEN 1 main routine with the same cycle and to be the set cycle The recommended instruction is the bit set BSET does not change value for clear B Interrupt Service Routine Setup Setup Procedure Description 1 Set the watchdog interrupt service routine 1 If the watchdog timer overflows the non maskable NMICR 0xOSFE1 interrupt is generated TBNZ NMICR WDIR WDPRO Confirm that the WDIR flag of the non maskable interrupt control register NMICR is 1 on the interrupt service routine to manage the suitable execution The operation just before the watchdog interrupt may be executed wrongly Therefore if the Y watchdog interrupt is generated initialize the system Operation IX 7 Chapter 9 Watchdog Timer IX 8 Operation Chapter 10 Buzzer Chapter 10 Buzzer 10 1 Overview This LSI has a buzzer It can output the square wave that multiply by 1 2 to 1 214 of the high frequency oscilla tion clock or by 1 2 to 1 24 of the low frequency oscillation clock 10 1 1 Functions Table 10 1 1 shows the buzzer functions Table 10 1 1 Buzzer Functions P12 P13
342. ches program to the interrupt handler using the starting address in the vector table The following is the hardware processing sequence invoked by interrupt acceptance 1 the stack pointer SP is updated SP 6 SP 2 The contents of the handy address register HA are saved to the stack Upper half of HA SP 5 Lower half of HA SP 4 3 The contents of the program counter PC i e the return address are saved to the stack PC bits 18 17 and 0 SP 3 PC bits 16 9 SP 2 PC bits 8 1 SP 1 4 The contents of the PSW are saved to the stack PSW SP 5 The interrupt level xxxLVn for the interrupt is copied to the interrupt mask IMn in the PSW Interrupt level xxxLVn IMn 6 The hardware branches program to the address in the vector table 7 0 New SP PSW Lower after interrupt to 1 acceptance 16 19 POO reserved 1817 Address HA7 to 10 HA15 to 8 Higher Old SP before interrupt acceptance peu EE Figure 3 1 5 Stack Operation during Interrupt Acceptance Overview Chapter 3 Interrupts BM Interrupt Return Operation An interrupt handler ends by restoring the contents of any registers saved to the stack during processing by the POP instruction and other means and the RTI instruction restores the program to the point at execution was inter rupted The following is the processing sequence i
343. chronized with a When using TMnIO input or fx as the count clock source the value of the binary counter may foscor fx Simple Pulse Width Measurement V 45 Chapter 5 8 bit Timers 46 5 10 Cascade Connection 5 10 1 Operation Cascading timers 0 and 1 or timers 2 and 3 forms a 16 bit timer 8 bit Timer Cascade Connection Operation Timer 0 1 Timer 2 3 Timer 0 and timer 1 or timer 2 and timer 3 are combined to be a 16 bit timer Cascading timer is operated at the clock source of timer 0 or timer 2 which are lower 8 bits Table 5 10 1 Timer Functions at Cascade Connection Timer 0 Timer1 Timer 24 Timer 3 16 bit 16 bit Interrupt source TM1IRQ TMSIRQ Timer operation Event count TMOIO input TM2IO input PWM output Clock source fosc fosc fosc 4 fosc 4 fosc 16 fosc 16 fosc 32 fosc 32 fosc 64 fosc 64 fs 2 fs 2 fs 4 fs 4 fx fx TMOIO input TM2IO input fosc Machine clock High frequency oscillation fx Machine clock Low frequency oscillation fs System clock Chapter 2 2 5 Clock Switching At cascade connection the binary counter and the compare register are operated as a 16 bit register At oper ation set the TMnEN flag of the upper and lower 8 bit timers to 1 to be operated Also select the clock source by the lower 8 bit timer Other setup and count timing is the same to the 8 bit timer at independently operation Cascade Connectio
344. ck clock slave Even if the external clock is selected set the internal clock that has the same clock cycle or lower to the external clock by the SC1MD3 register as the interrupt flag SCITIRQ is generated by the internal clock The following is the internal clock source that can be set by the SC1MD3 register Also the SCICKM flag of the SCIMDI register can divide the internal clock SCIDIV flag can select the dividing ratio between divided by 8 and divided by 16 Table 12 3 3 Synchronous Serial Interface Clock Source serial 1 Clock source internal clock fosc 2 fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 1 output Timer 2 output Timer 2 output 2 Timer 2 output 8 Set always the SC1SBIS flag and SC1SBOS flag of the SC1MD1 register to 0 before switching the clock setup When the slave reception is executed with the start condition enable at the continuous com munication the system configuration is required to notify the master of the readout comple tion Without the notification the data before readout may be overwritten Operation Chapter 12 Serial interface 1 B Used Pin Switching Used pin can be switched to A SBO1A 5 SBT1A or B SBOIB SBIIB SBT1B by the SCISL flag of the SCSEL register Data Input Pin Setup 3 channels type clock pin SBTI pin data output pin 5 pin data input pin SBI1 pin or 2 channels type cloc
345. consecutively Chapter 6 16 bit Timers Count Timing of Standard PWM Output when compare register 1 is OXFFFF Timer 7 Timer 8 Here is the count timing at setting OxFFFF to the compare register 1 TMnEN flag Compare register 1 x Exe cce counter TMnIO output PWM output IFFFF L Figure 6 6 3 Count Timing of Standard PWM Output when compare register 1 is OXFFFF To output the standard PWM output set TMnBCR flag of the TM7MD2 or TM8MD2 regis ter to 0 to select the full count overflow as the binary counter clear source and the PWM output set H output source The TMnOC1 compare match or the TMnOC2 compare match can be selected as a PWM output reset L output source with the TRPWMSL flag of the TMnMD2 register In the initial state of the PWM output it is changed to H output from L output at the timing that the PWM operation is selected by the TMnPWM flag of the TMnMD2 register the preset register to clear the binary counter and the PWM waveform when restarting the a To guarantee the PWM waveform of the first cycle after PWM operation is stopped write to PWM operation 16 bit Standard PWM Output Only duty can be changed consecutively VI 41 Chapter 6 16 bit Timers 6 6 2 Setup Example Standard PWM Output Setup Example The TM71O output pin outputs the 1 4 duty PWM output waveform at 152 6 Hz with the timer 7 at the high fre quency oscill
346. cycle is 250 so that the setting value is set to 249 0x49 At that time the timer 0 binary counter is initialized to 0x00 7 Set the interrupt level by the TMOLV1 to 0 flag of the timer 0 interrupt control register TMOICR If the interrupt request flag may be already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 8 Set the TMOIE flag of the TMOICR register to 1 to enable the interrupt 9 Set the TMOEN flag of the TMOMD register to 1 to operate the timer 0 8 bit Timer Chapter 5 8 bit Timers The TMOBC starts to count up from 0x00 When the TMOBC reaches the setting value of the TMOOC register the timer 0 interrupt request flag is set at the next count clock then the value of the TMOBC becomes 0x00 and restart to count up When the TMnEN flag of the TMnMD register is changed at the same time to other bit binary counter may start to count up by the switching operation Do not operate the TMnEN flag and the TMnCK 2 to 0 flag of the TMnMD register at the Y same time That may lead the malfunction a Count clock source should be changed when the timer interrupt is disabled 8 bit Timer V 25 Chapter 5 8 bit Timers 26 5 5 8 bit Event Count 5 5 1 Operation Event count operation has 2 types TMnIO input and synchronous TMnIO input according to the clock source selection 8 bit Event Count Operation Timer 0 1 2 and 3
347. d 4 Control Register Chapter 9 Watchdog Timer 9 3 Operation 9 3 1 Operation The watchdog timer counts system clock fs as a clock source If the watchdog timer is overflowed the watch dog interrupt WDIRQ is generated as non maskable interrupt NMI At reset the watchdog timer is stopped but once the operation is enabled it cannot be stopped except at reset The watchdog timer control register WDCTR sets when the watchdog timer is released or how long the time out period should be When the watchdog interrupt WDIRQ is generated it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware a Once the watchdog timer starts operation it cannot be stopped Usage of Watchdog Timer When the watchdog timer is used constant clear in program is needed to prevent an overflow of the watchdog timer As a result of the software failure the software cannot execute in the intended sequence thus the watchdog timer overflows to detect errors Programming of the watchdog timer is generally done in the last step of program debugging How to Detect Incorrect Code Execution The watchdog timer is executed to be cleared in the certain cycle on the correct code execution In MN101C78A the watchdog timer detects errors when 1 the watchdog timer overflows When the watchdog timer detects any error the watchdog
348. d so that it can be used as a general port Table 13 3 9 Synchronous Serial Interface Pins Setup 2 channels at transmission Item Data pin Serial unused pin Clock I O pin SBOS pin 5 SBT3 pin Clock master Clock slave Port Pin 1 P32 Serial data input 5803 selection SC3MD1 SC3IOM Function Serial data output 1 input Serial clock I O Serial clock I O SC3MD1 SC3SBOS SC3MD1 SC3SBIS SC3MD1 SC3SBIS Type Push pull N ch open Push pull N ch open Push pull N ch open drain drain drain P30DC P30DC2 Input mode P3DIR P3DIR3 P3DIR P3DIR2 Pull up added not added added not added added not added P3PLU P3PLU3 P3PLU P3PLU2 Pins Setup 2 channels at reception Table 13 3 10 shows the pins setup at synchronous serial interface reception with 2 channels SBO3 pin SBT3 pin The 5813 pin is not used so that it can be used as a general port Table 13 3 10 Synchronous Serial Interface Pins Setup 2 channels at reception Item Data pin Serial unused pin Clock I O pin SBOS pin 5 SBT3 pin Clock master Clock slave Port Pin P33 P31 P32 Serial data input 5803 selection SC3MD1 SC3IOM Function Port Serial input Serial clock I O Serial clock I O SC3MD1 SC3SBOS SC
349. d SC3SBOS flags of the SC3MD1 register to 0 before change the Y clock setup B Transmission Reception Mode Setup and Operation The IIC3REX flag of the SC3CTR register selects the status of the transmission or the reception The first data is always added start condition for communication regardless of the setting value of the SC3STE The start condi tion is output from this serial master The start condition is not added over the second communication select the start condition none at the first set ting And the start condition is added over the second communication select the start condition enable at the first setting At addressing format slave address and R W bit are set to the first data after start condition for transmission At master reception switch to the reception mode at the interrupt transaction after the transmission of the first 1 byte data is finished after the ACK signal from slave is confirmed If the communication should be continued to other device without stop transmit slave address and R W bit again after start condition is generated again At recep tion the SDA line is automatically released to wait for reception After the storage of data is finished confirma tion of the reception ACK bit is output Figure 13 3 21 Master Transmission Timing Figure 13 3 22 Master Reception Timing Operation XII 41 Chapter 13 Serial Interface 3 XIII 42 B IIC BUSY Flag Operation When data is set to t
350. d as a port Table 11 3 11 Setup for Synchronous Serial Interface Pin with 2 channels at reception Setup item Data output pin Serial unused pin Clock pin SBOOA pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin PAO P75 PA1 P76 PA2 P77 Port pin setup Select pin A B SCSEL SCOSL Serial data input SBOO selection SCOMD1 SCOIOM Function Port Serial input Transfer clock I O Transfer clock I O SCOMD1 SCOSBO SCOMD1 SCOSBIS SCOMD1 SCOSBIS S Style Push pull N ch Push pull N ch open drain open drain PAODC PAODC2 P7ODC P70DC7 Input mode Output mode Input mode PADIR PADIRO PADIR PADIR2 P7DIR P7DIR5 P7DIR P7DIR7 Pull up setup Added Not added Added Not added PAPLU PAPLU2 P7PLU P7PLU7 XI 38 Operation Chapter 11 Serial interface 0 11 3 2 Setup Example ul s i s oa ol c Ss OPm F B Transmission Reception Setup Example The setup example for clock synchronous serial communication with serial 0 is shown Table 11 3 12 shows the conditions at transmission reception Table 11 3 12 Setup Examples for Synchronous Serial Interface Transmission Reception Setup item Set to Serial data input pin Select SBIO 3 channels Transfer bit count 8 bit Start condition None First transf
351. d bit3and bit7 are read out at the tim ing of COM3 If a bit points 1 the segment pin outputs the selected voltage and if a bit points 0 the seg ment pin outputs non selected voltage The assigned address are X 2E00 to X 2E05 and data reading writing can be done as RAM Segment output latch value is indefinite at reset Figure 16 2 1 shows the matching of the segment output latch and the segment common pins COM3 COM2 COM1 COMO T COM2 1 1 Address _ bit7 bit6 bitb bit4 bit3 bit2 bit bito 1 jJ SEGUP76 __ SEGO P77 2 7 3 _____ SEGGETA __ ___ ______ SEG 2 8765 20 11 1 5 5 72 1 SEG 4 P73 2 7 1 J SEG7P70 1 1 ___ SEG 6 71 2 04 1 1 1 SEG9PI6 SEG 8 17 11 1 __ 5 1 14 ___ __ 1 5 Used at Static Used at Static Used at 1 2 duty Used at 1 2 duty _ Used at 1 3 duty Used at 1 3 duty Used at 1 4 duty P Used at 1 4 duty Figure 16 2 1 Matching of the Segment Output Latch and the Segment Common Pins Control Registers Chapter 16 LCD 16 3 Operation 16 3 1 Operation The LCD driver is capable of static display and dynamic display 1 2 duty 1 2 bias 1 3 duty 1 3 bias 1 4 duty 1 3 bias through the segment output pins SEGO to SEGI1 and the common output pins COMO to COM B The LCD driver circuit operation The LCD driver circuit generates the timing signals which are n
352. ddress The I2CBSY flag is set to 1 during communication on bus In 10 bits address mode if the upper 2 bits address which is first to be transmitted from master matches the I2CADO 8 of the SCAADI register the SLVBSY flag is set to 1 but SCAIRQ is not generated If the lower 8 bits address which is next to be transmitted from master matches the I2CAD7 0 of the SCAADO register the SLVBSY flag is remained 1 and SCAIRQ is generated If these address mismatch the SLVBSY flag is cleared to 0 and SCAIRQ is not generated Operation XIV 9 Chapter 14 Serial Interface 4 B Bus Line Monitor General call communication can be monitored with the bus line OFF serial interface 4 is not activated For mon itoring while the SELI2C flag is set to 1 set the I2ZCGEM flag of the SCAADI register to 1 and set the I2CMON flag to 1 Though serial 4 interrupt SCAIRQ is generated at this time it does not output signal to the data and clock that it has no effect on the communication B Pin Setup Table 14 2 1 shows pin setup SDA SCL pins for serial interface 4 data transmission N ch open drain setup is always necessary for using this serial interface Use the pull up resistor control register PnPLU of each port for pull up resistor setup Input output of the transfer data is automatically switched Table 14 2 1 Pin Setup Item Data pin Clock output pin SDA pin SCL pin Port Pin P10 P11 P76
353. ddress Function Page PSIN 0x03F23 Port 3 input register AN P3OUT 0x03F13 R W Port 3 output register IV 26 R PSDIR 0x03F33 R W Port 3 direction control register P3PLUD 0x03F43 R W Port 3 pull up pull down control register SELUD 0x03F4B R W Pull up pull down resistor selection register P30DC 0x03F3B R W Port 3 Nch open drain control register LCCTR1 2 R W LCD output control register 1 LCCTR3 0x03FC4 R W Readable Writable Port 3 Output Register PSOUT 0x03F13 R W LCD output control register 3 P3OUT7 P3OUT6 P3OUT5 P3OUT4 PSOUT2 P30UT1 PSOUTO X X x x x x x x bp Description Output data 0 Output L VSS level 1 Output H VDD level IS O Q O IV 26 Port 3 Chapter 4 Ports Port 3 Input Register P3IN 0x03F23 bp Flag Description O Q O P3IN7 P3IN6 P3IN5 P3IN4 P3IN3 P3IN2 P3IN1 P3IN0 Input data 0 Pin is L VSS level 1 Pin is H VDD level Port 3 Direction Control Register P3DIR 0x03F33 Flag P3DIR7 P3DIR6 P3DIR5 P3DIR4 P3DIR3 P3DIR2 P3DIR1 P3DIRO At reset 0 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W R W bp Flag Description O OQ Q O P3DIR7 P3DIR6 P3DIR5 P
354. direct d16 An Register relative indirect d4 PC 17 0H s branch instructions only PC d4 97 PC 17 0H d ______ 7 _____ branch instructions only mE L 911 17 0H ______ 11 branch instructions only 3 d12 PC 17 0H i Po PC di2 branch instructions only PO di2 L T 916 17 0 I branch instructions only SP d4 Stack relative SP d8 15 0 16 916 5 _ Directly specifies the register Only internal registers can be specified Explanation Directly specifies the operand or mask value appended to the instruction code Specifies the address using an address register Specifies the address using an address register with 8 bit displacement Specifies the address using an address register with 16 bit displacement Specifies the address using the program counter with 4 bit displacement and H bit Specifies the address using the program counter with 7 bit displacement and H bit Specifies the address using the program counter with 11 bit displacement and H bit Specifies the address using the program counter with 12 bit displacement and H bit Specifies the address using the program counter with 16 bit displacement and H bit Specifies the address using the stack pointer with 4 bit displacement indirect i 15 0 Specifies the address using the stack poi
355. dition is automatically generated to finish the communication Note Procedures 1 2 can be set at the same time Note Procedures 5 to 9 can be set at the same time Note Procedures 10 11 can be set at the same time Note Procedures 12 13 can be set at the same time be operated after all control registers refer toTable 13 2 1 except are set a Each flag should be set as this setup procedure in order Activation of communication should Operation Chapter 14 Serial Interface 4 Chapter 14 Serial Interface 4 14 1 Overview This LSI contains a serial interface 4 which is compatible with IIC serial interface slave communication 14 1 1 Functions Table 14 1 1 shows the serial interface 4 functions Table 14 1 1 Serial Interface 4 Functions Communication style IIC slave Interrupt SC4IRQ Pins SDA SCL Addressing 7 bits 10 bits General call O Maximum transfer rate 400 kHz High speed mode Serial interface 4 is only available in NORMAL mode It is not available in other modes Y SLOW HALTO HALT1 STOP1 XIV 2 Overview Chapter 14 Serial Interface 4 14 1 2 Diagram B Serial Interface 4 Block Diagram OHlv oS 2 0 0 0 1HIS Lise sens E 961145 ozmas ntn waeoa savzi Lavros
356. e 0 235 us Vpp 1 8 to 3 6 V 1 t 470 3 g Normal mode fs fosc 2 QE Vpp 1 8 to 3 6 V t 19 93 Normal mode fs fx 2 2 sem Electrical Characteristics 23 Chapter 1 Overview 4 fosc Input clock frequency to OSC1 pin fx Input clock frequency to XI pin 5 te1 tO OSC1 is the CPU clock tes XI is the CPU clock 1 24 Electrical Characteristics Chapter 1 Overview Vpp 1 8V to 3 6V Vss 0V Ta 40 C to 85 C Rating Parameter Symbol Conditions Unit MIN TYP MAX Crystal oscillator 1 Figure 1 5 1 17 Vpp Within operation power sup 18 Crystal frequency ply voltage Refer to standard rat 1 0 10 0 MHz 19 ings B1 to B5 20 20 External capacitors pF 21 C12 20 22 Internal feedback resistor Rito 1 2 MQ Crystal oscillator 2 Figure 1 5 2 23 Crystal frequency 1 8 V to 3 6 V 32 768 kHz 24 Coy 20 External capacitors pF 25 Coo 20 26 Internal feedback resistor Roo 17 6 0 1 XI OSC2 Internal Feedback resistor Figure 1 5 1 Crystal oscillator 1 XO C22 C21 Internal Feedback resistor Figure 1 5 2 Crystal oscillator 2 Connect external capacitors that suits the used pin
357. e NORMAL mode Clock source fosc 32 SCL3 SDA3 pin type N ch open drain SCL3 pin pull up resistance Added SDAG3 pin pull up resistance Added An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select prescaler operation SC3MD3 0x03FA2 bp3 SC3PSCE 1 2 Select the clock source SC3MD3 0x03FA2 bp2 0 SC3PSC2 0 011 3 Control the pin type 0x03F3B bp2 P3ODC2 1 1 4 Control the pin direction P3DIR 0x03F33 bp2 P3ODC2 1 1 1 Set SC3PSCE flag of the SC3MD3 register to 1 to select prescaler operation 2 SC3PSC2 0 flags of the SC3MD3 register to 011 to select fs 32 as the clock source 3 Set the PSODC2 P3ODC3 flag of the P3ODC register to 1 1 to select N ch open drain for the SDA3 SCL3 pin type 4 Set the P3DIR2 P3DIR3 flag of P3 pin control direction register P3DIR to 1 1 to set P32 P33 to output mode XIII 46 Operation Chapter 13 Serial Interface 3 Setup Procedure Description b Set ACK bit SC3CTR 0x03FA6 SC3ACKO x 1 6 Select the communication mode SC3CTR 0x03FA6 IIC3TMD 0 7 Select the communication type SC3CTR 0x03FA6 bp2 SC3CMD 1 8 lt Transmission setup gt Select the transmission reception SC3CTR 0x03FA6
358. e LCDCLk fosc 2 fosc 2 fosc 213 214 215 216 217 fosc 2 8 fx 26 fx 27 fx 28 fx 29 fosc Machine clock High speed oscillation fx Machine clock Low speed oscillation LCDCLK LCD clock source selected with LCDCKO to LCDCK3 XVI 2 Functions Chapter 16 LCD a Use the LCD panel driver voltage Vi cp as Vi cp Vpp 3 6 v 16 1 2 LCD Operation in Standby Mode Certain LCD driver operation could be limited in standby mode Table 16 1 2 shows the LCD operation capabilities in standby mode Table 16 1 2 LCD Operation in Standby Mode CPU Mode LCD Clock fosc fx Operation Mode NORMAL SLOW X Standby Mode HALTO D D HALT1 D STOP Y O LCD Operation is available D Holding Display is available X LCD Operation is not available For transition to CPU mode in which LCD operation is not available turn the LCD off and Switch segment output to port in advance tion register XSEL to 1 a For transition to the mode with low speed oscillation set the bpO of the XI dual function selec Functions XVI 3 Chapter 16 LCD XVI 4 16 1 3 Maximum Pixels Table 16 1 3 shows the maximum pixels Table 16 1 3 Maximum Pixels Duty as Common Pins Segment Output Latch bits Static 12 12 1 1 figures COMO bitO bit4 1
359. e Control Register DLYCTR 0x03F03 7 s T s IL TL ILI eco NUS 0 0 0 0 0 0 at reset Access R W R W R W R W R W R W Description P12 P13 output selection 0 Port output 1 Buzzer output Buzzer output frequency selection 000 fosc 214 001 fosc 213 010 fosc 212 011 fosc 21 100 fosc 2 101 29 110 fx 24 111 fx 23 Oscillation stabilization wait period selection 00 fs 2 4 01 fs 2 10 15 26 51 11 fs 22 1 1 Do not use at high speed operation NORMAL mode Use at slow speed operation SLOW mode Control Register X 5 Chapter 10 Buzzer X 6 10 3 Operation 10 3 1 Operation B Buzzer Buzzer outputs the square wave having frequency 1 2 to 1 21 of the high oscillation clock fosc or 1 2 to 1 24 of the low oscillation clock fx The BUZS 2 1 0 flag of the oscillation stabilization wait control register DLYCTR set the frequency of the buzzer output The BUZOE flag of the oscillation stabilization wait control register DLYCTR sets buzzer output ON OFF B Buzzer Output Frequency The frequency of buzzer output is decided by the frequency of the high oscillation clock fosc or the low oscilla tion clock fx and the bit 6 5 4 80252 80251 BUZSO of the oscillation stabilization wait control register DLYCTR Table 10 3 1 Buzzer Output Frequency fosc
360. e SC3MD0 register to 0 to disenable start condition Start condition is not added after the second communication Set the SC3DIR flag of the SC3MDO register to 0 to set MSB as the first transfer bit In communication set always the SC3CE1 flag of the SC3MDO register to 1 11 Set the SC3MST flag of the SC3MD1 register to 1 to select clock master internal clock In communication do not select external clock Set the SC3SBOS SC3SBIS SC3SBTS flags of the SC3MD1 register to 1 to set the SDA3 pin SBO3 pin to serial data output the 5813 pin to serial data input and the SCL3 pin the pin to serial clock O Set the SC3IOM flag to 1 to set serial data input from the SDA3 pin the SBOS pin 12 Set the interrupt level by the SC3LV1 0 flag of the serial 3 interrupt control register SC3ICR Operation XIII 47 Chapter 13 Serial Interface 3 Setup Procedure Description 13 Enable the interrupt SC3ICR 0x03FF3 bp1 SCSIE 1 14 Start transmission Start serial transmission Confirm that SCL3 P32 is H Transmission data TXBUF3 0x03FA5 15 Transmission ends Setup the next data transmission Judge the monitor flag SC3CTR 0x03FA6 bp6 IIC3STC 16 Judge the ACK bit level SC3CTR 0x03FA6 SC3ACKO 17 Set the SC3MDO register Select the transfer bit count SC3MDO 0x03FA0 2 0 SCSLNG2 0 18 Start next data
361. e interrupt level TMOICR 0x03FE7 bp7 6 TMOLV1 0 10 1 Set the TMOEN flag of the timer 0 mode register to O to stop timer 0 counting 2 Set the TMOIE flag of the TMOICR register to 0 to disable the interrupt 3 Set the P1DIRO flag of the port 1 direction control register P1DIR to 0 to set P10 pin to input mode Chapter 4 Port Function 4 Select the prescaler output to the clock source by the 2 to 0 flag of the TMOMD register b Select the fs 2 to the prescaler output by the TMOPSC1 to 0 flag and the TMOBAS flag of the timer 0 prescaler selection register CKOMD 6 Set the interrupt generation cycle to the timer 0 compare register TMOOC Counting is 5 so the setting value should be 4 At the time the timer 0 binary counter is initializes to 0 00 7 Set the TMOPWM flag and the TMOMOD flag of the TMOMD register to 0 to select the normal timer operation 8 Select the TMOIO input to the clock source by the TMOCK to 0 flag of the TMOMD register 9 Set the interrupt level by the TMOLV1 to 0 flag of the timer 0 interrupt control register TMOICR If the interrupt request flag may be already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 8 bit Event Count 29 Chapter 5 8 bit Timers Setup Procedure Description 10 Enable the interrupt TMOICR 0x03FE7 bp1 TMOIE 1 11 Start the event count TMOMD 0
362. e interrupt processing sequence consists of interrupt request interrupt accep tance and hardware processing The program counter PC and processor status word PSW and hard addressing data HA are saved onto the stack and program is branched to the address specified by the corresponding inter rupt vector interrupt handler ends by restoring the contents of any registers used during processing and then executing the return from interrupt RTI instruction to return to the point at which execution was interrupted Interrupt service routine Main program Interrupt request flag cleared at head rs Hardware processing Save up PC PSW etc Interrupt generation Max 12 machine cycles 11 machine cycles Restart Restore PSW PC up etc Figure 3 1 2 Interrupt Processing Sequence maskable interrupts Overview 11 5 Chapter 3 Interrupts B Interrupt Group and Vector Addresses Table 3 1 2 shows the list of interrupt vector addresses and interrupt group Table 3 1 2 Interrupt Vector Addresses and Interrupt Group Vector Vector Interrupt group interrupt factor Control register address number addresses 0 0x04000 Reset 1 0x04004 Non maskable interrupt NMI NMICR Ox03FE1 2 0x04008 External interrupt 0 IRQO IRQOICR OxO3FE2 3 0x0400C External interrupt 1 IRQ1 IRQ1ICR OxO3FE3 4 0x04010 Ex
363. e interrupt service routine clear the timer interrupt request flag before the timer is started Operation Chapter 6 16 bit Timers When the binary counter is used as a free counter that counts 0x0000 to OxFFFF set OxFFFF to the compare register or set the TM7BCR of the TM7MD2 register to 0 When the TMnEN flag of the TMnMD register is changed with other bits the binary counter may count up by switching operation a Set up 16 bit timer counter clock should be done when the timer interrupt is disabled bits unit in LSI So when the digit is raised from lower 8 bits to upper 8 bits correct value cannot be read out Stop the timer to read out the correct value a When the binary counter is read out on the timer operation it is regarded as the data by 8 Operation VI 27 Chapter 6 16 bit Timers VI 28 6 3 2 Setup Example Timer Operation Setup Example Timer 7 generates an interrupt constantly for timer function Fosc 2 fosc 10 MHz at operation is selected as a clock source to generate an interrupt every 1000 cycles 200 ms An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD 1 0x03F78 bp4 TM7EN 0 2 Disable the interrupt TM7ICR OxOSFED bp1 TM7IE 0 3 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 4 Select the count clock source TM7MD1 0x03F78 bp1 0
364. e loaded to the compare register the value set in the dead time preset register during IGBT operation may not be reflected a If the event input TM71O is selected as the count clock source the following cases may entered on the dead time preset register while IGBT operation halt may not be reflected To prevent this select the system clock fs as the count clock source and enter the value on the dead time preset register Then select the event input TMnIO as the count clock source and start the IGBT operation a When the event input TTMnIO is selected as the count clock source the value which is When IRQO IRQ1 or IRQ2 is selected as the IGBT trigger the timing of IGBT operation start Y may delay up to 1 count clock Dead Time IGBT Output Chapter 6 16 bit Timers One Shot Pulse Output Setup One shot pulse can be output by setting the T7ONESHOT flag of the TM7MDA register to 1 00 00 XF Aas 10 X 00 1 en gt 2000 0000 a i 1 y y indino 1891 indino OISIALL 1851 peeq 1
365. e maskable interrupt enable flag MIE flag of PSW is 1 Maskable interrupts have had vector numbers by hardware but their priority can be changed by setting interrupts level field There are three hierarchical interrupt levels If multiple interrupts have the same priority the one with the lowest vector number takes priority Maskable interrupts are accepted when its level is higher than the inter rupt mask level IM1 to 0 of PSW Non maskable interrupts are always accepted regardless of the interrupt mask level Overview 3 1 1 Functions Chapter 3 Interrupts Table 3 1 1 Interrupt Functions Interrupt type Reset interrupt Non maskable interrupt Maskable interrupt Vector number Table address 0 0x04000 1 0x04004 2 to 23 0x04008 to 0x0405C Starting address Address specified by vector address Interrupt level Can be set to levels 0 to 2 by software Interrupt factor External RST pin input Errors detection inter rupt External pin input internal peripheral function Generated opera tion Accept operation Direct input to CPU core Always accepts Input to CPU core from non maskable interrupt control register NMICR Always accepts Input interrupt request level set in interrupt level flag xxxL Vn of maskable interrupt control register XxxICR to CPU core Acceptance only by the interrupt control of the reg ister xxxICR and the inter
366. e notification the data before readout may be overwritten B Transfer Bit Setup The transfer bit count is selected from 1 to 8 bits Set the transfer bit count by the SCILNG 2 to 0 flag of the SCIMDO register at reset 111 The SCILNG2 to 0 flag holds the former set value until it is set again Except during communication SBT1 pin is masked to prevent errors by noise At slave com Y munication set data to TXBUF1 or input a clock to SBT1 pin after a start condition is input To communicate properly more than 2 5 transfer clock interval after the data set to TXBUF1 is required to input the external clock B Start Condition Setup The SCISTE flag of the SCIMDO register sets whether a start condition is enabled or disabled The start condition is recognized when SCICEI flag of SCIMDO is set to 0 and a clock line SBTI pin is H data line 5 pin with 3 lines or SBO1 pin with 2 lines is changed from to L Also it is recognized when 5 flag is set to 1 and a clock line SBTI pin is L data line SBII pin with 3 lines SBOI pin with 2 lines is changed from to Both the SCISBOS flag and the SCISBIS flag of the SCIMDI register should be set to 0 before the start con dition setup is changed When transmission and reception are executed at the same time set the start condition to disable to prevent abnormal operation B First Transfer Bit Setup The SCIDIR flag of the SCIMDO
367. e register 1 is X FFFF Timer 7 The following shows the count timing as the compare register 1 is set to X FFFF TM7EN Flag Compare Register 1 E IGBT Trigger e CE SECO C CO CE Rcs ue CS C CD C CD C Counter TM71O Output IGBT output Figure 6 10 3 Count Timing of Standard IGBT Output When the compare register 1 is X FFFF VI 68 16 bit Standard IGBT Output Only duty can be changed consecutively Chapter 6 16 bit Timers full count overflow as the binary counter clear factor and the IGBT output set H output fac a For standard IGBT output set the TM7BCR flag of the TM7MD2 register to 0 and select the tor TM7OC1 compare match or TM7OC2 compare match can be selected as the IGBT output Y reset L output factor by the T7PWMSL flag of the TM7MD2 register 16 bit Standard IGBT Output Only duty can be changed consecutively VI 69 Chapter 6 16 bit Timers 6 10 2 Setup Example B Standard IGBT Output Setup Example Timer 7 At the interrupt generation edge of the external interrupt 0 input signal TM71IO output pins output the waveform of 1 4 duty IGBT waveform at 305 18 Hz using the timer 7 Frequency for high speed operation fosc is 20 MHz Required period for one IGBT output waveform cycle depends on the overflow time of the binary counter period of IGBT output waveform depends on the set value of the compare register 1 An example setup procedure with a descripti
368. e register 1 upper 8 bits 0x03F84 TM8PR1L TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 14 L7 L6 L5 L4 L3 L2 L1 0 x x x x x x x x Timer 8 preset register 1 lower 8 bits 0x03F85 TM8PR1H TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 TM8PR1 14 H7 H6 H5 H4 H3 H2 H1 H0 x x x x x x x x Timer 8 preset register 1 upper 8 bits Special Function Registers List XVII 17 Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 03 86 TM8ICL TM8ICL7 TM8ICL TM8ICL TM8ICL TM8ICL TM8ICL TM8ICL TM8ICL VI 15 6 5 4 3 2 1 0 x x X x x x x x Timer 8 input capture register 1 lower 8 bits 0x03F87 TM8ICH TM8ICH7 TM8ICH TM8ICH TM8ICH TM8ICH TM8ICH TM8ICH VI 15 6 5 4 3 2 1 0 x x x x x x x x Timer 8 input capture register 1 upper 8 bits 0x03F88 TM8MD1 Reserved T8ICED TM8CL TM8EN TM8PS1 TM8PSO TM8CK1 TM8CK0 VI 20 G1 0 0 1 0 0 0 0 0 Set Capture Timer Timer 8 Count clock selection Clock source selec alwaysto trigger output count tion 0 reset control signal 0x03F89 TM8MD2 T8ICED TM8PW TM8BC TM8PW TM8IRS T8ICEN T8ICTO VI 21 G1 MSL R M 1 0 0 0 0 0 0 0 0 Capture PWM Timer 8 Timer Timer 8 Input Capture trigger trigger mode count output interrupt capture edge selection clearfac wave
369. e the interrupt IRQOICR OxOSFE2 bp1 IRQOIE 0 3 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 4 Select the count clock source TM7MD1 0x03F78 bp1 0 TM7CK1 0 00 bp3 2 TM7PS1 0 00 5 Select IGBT timer startup factor TM7MD3 0x03F8E bp1 0 T7IGBT1 0 00 6 Set the compare register TM7PR1 0x03F75 0x03F74 OxFFFF 7 Select the capture trigger generation interrupt source TM7MD2 0x03F79 bp1 0 T7ICT1 0 00 8 Select the capture trigger generation edge TM7MD1 0x03F78 bp6 T7ICEDG1 1 TM7MD2 0x03F79 bp7 T7ICEDGO 1 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Set the IRQIE flag of the IRQOICR register 10 0 to disable the interrupt 3 Set the TM7BCR flag of the timer 7 mode register 2 TM7MD2 to 1 to select the compare match as the binary counter clear source 4 Select fosc as the clock source by the TM7CK1 to 0 flag of the TM7MD 1 register Also select 1 1 dividing of fosc as the count clock source by the TM7PS1 to 0 flag 5 Set IGBT timer startup factor to timer 7 count operation 6 Set OXFFFF to the timer 7 preset register 1 TM7PR1 At that time the same value is loaded to the timer 7 compare register 1 TM7OC1 the timer 7 binary counter 7 is initialized to 0 0000 7 Select the external interrupt 0 IRQO input as the capture trigger generation source by the T7ICT1 100 flag of the TM7MD2 reg
370. ecessary for controlling 1 2 duty 1 3 duty 1 4 duty and static at the timing control circuit based on the LCD clock divided by the prescaler and supplies them to the common driver and the multiplexer The common driver outputs the common signals which are necessary for the LCD display based on the voltage from the LCD power supply When the LCD is OFF Vss is output and the potential difference between the LCD electrodes becomes 0 V The multiplexer selects the segment output latched data in response to the signal from the timing control circuit and supplies it to the segment driver The segment driver converts the content of the segment output latch into the signals which is capable of driving the LCD based on the voltage supplied to LCD power supply then outputs the segment signal When the LCD is OFF Vss is output and the potential difference between the LCD electrodes becomes 0 V Therefore when reset input from external sources is long there could be some adverse a At reset common pins and segment pins become high impedance effects such as blinks of the LCD display In STOP mode supplies from the main clocks is stopped that the LCD drive cannot be oper Y ated Set 0 to the enable flag of the LCD driver circuit before entering STOP mode For transition to the mode with low speed oscillation set the bpO of the XI dual function selec Y tion register XSEL to 1 Operation XVI 13 Chapter 16
371. ecify the rising edge as the active edge for interrupts 2 Set the interrupt priority level in the IRQOLV1 to 0 flag of the IRQOICR register 3 Set the IRQOIE flag of the IRQOICR register to 1 enable the interrupt External interrupt 0 is generated at the rising edge of the input signal from P54 valid edge before the interrupt permission lt The interrupt request flag can be set at switching the interrupt edge so specify the interrupt The external interrupt pin is recommended to be pull up in advance 52 External Interrupts Chapter 3 Interrupts 3 3 5 Both Edges Interrupt Both Edges Interrupt External interrupt 2 Both edges interrupt can generate interrupt at both the falling edge and the rising edge by the input signal from external input pins CPU also can be returned from standby mode the external interrupt pin level are matched the interrupt is generated refer to Figure 3 3 1 to Figure 3 3 5 Chapter 3 3 3 9 External Interrupt At the Standby Mode a At the standby mode if the value that is set to the external interrupt valid specified flag and Both Edges Interrupt Setup Example External interrupt 2 External interrupt 2 IRQ2 is generated at the both edges of the input signal from P56 pin The table below shows a setup example of IRQ2 Setup Procedure Description 1 Select the both edges interrupt 1 Set the EDGSEL flag of the both edges interrupt
372. ed data is going to be read out SCOREMP is cleared to 0 by reading out the data of RXBUFO Reception BUSY Flag When the start condition is recognized the SCORBSY flag of the SCOSTR register is set to 1 When the recep tion complete interrupt SCOTIRQ is generated the flag is cleared to 0 If the SCOSBIS flag is set to 0 during reception the SCORBSY flag is reset to 0 B Transmission BUSY Flag When data is set to TXBUFO the SCOTBSY flag of the SCOSTR register is set to 1 When the transmission complete interrupt SCOTIRQ is generated the flag is cleared to 0 During continuous communication the SCOTBSY flag is always set If the transmission buffer empty flag SCOTEMP is set to 0 as the transmission complete interrupt SCOTIRQ is generated the SCOTBSY is cleared to 0 If the SCOSBOS flag is set to 0 the SCOTBSY flag is reset to 0 Operation Chapter 11 Serial interface 0 Frame Mode and Check Setup Figure 11 3 17 shows the data format at UART communication Frame Character bit Figure 11 3 17 UART Serial Interface Transmission Reception Data Format The transmission reception data consists of start bit character bit parity bit and stop bit Table 11 3 16 shows its types to be set Table 11 3 16 UART Serial Interface Transmission Reception Data Start bit 1 bit Character bit 7 8 bit Parity bit fixed to 0 fixed to 1 odd even none
373. edge of the TMnIO input signal or TMnIO input signal that passed the divider TMnlO input Count clock flag Compare register1 0000 0001 0003 sa N 0000 0001 Interrupt request flag Figure 6 4 3 Count Timing TMnIO Input Timer 7 Timer 8 oscillation Input from TMnIO should be done the waveform which has more than 2 times cycle than fosc when duty ratio is 5096 If the waveform which has less cycle is input it may not be counted correctly a When both edges are selected they are counted only at the normal operation high speed 16 bit Event Count 6 4 2 Setup Example Event Count Setup Example When the falling edge of the TM7IO input pin signal is detected 5 times using timer 7 an interrupt is generated Chapter 6 16 bit Timers An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TM7MD1 0x03F78 bp4 TM7EN 0 2 Disable the interrupt TM7ICR OxOSFED bp1 TM7IE 20 3 Set the special function pin to input P1DIR 0x03F31 bp3 P1DIR3 0 4 Select the count clock source TM7MD 1 0x03F78 bp1 0 TM7CK1 0 201 bp3 2 TM7PS1 0 200 5 Select IGBT timer startup factor TM7MD3 0x03F8E bp1 0 T7IGBT1 0 00 6 Set the interrupt generation cycle TM7PR1 0x03F75 0x03F74 0 0004 7 Select the timer clear source TM7MD2 0x03F79 bp5 TM7BCR 1 8 Select the count
374. egister If the interrupt request flag has been already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 6 Set the IRQAIE flag of the IRQ4ICR register to 1 to enable the interrupt Above 3 and 4 can be set at the same time If there is at least one input signal from the P70 to P73 pins shows low level the external interrupt 4 is generated at the falling edge The key input should be setup before the interrupt is accepted External Interrupts III 55 Chapter 3 Interrupts 56 3 3 7 Noise Filter 27 Noise Filter External interrupts 0 1 Noise filter reduce noise by sampling the input waveform from the external interrupt pins IRQO IRQ1 Its sam pling cycle can be selected from 4 types fosc fosc 2 fosc 25 fosc 2 Noise Remove Selection External interrupts 0 and 1 Noise remove function can be selected by setting the NFnEN flag of the noise filter control register NFCTR to gt Table 3 3 8 Addition of Noise Remove Function IRQ input P54 IRQ input P55 0 IRQO noise filter OFF IRQ1 noise filter OFF 1 IRQO noise filter ON IRQ1 noise filter ON B Sampling Cycle Setup External interrupts 0 and 1 The sampling cycle of noise remove function can be set by the NFnSCK2 to 0 flag of the NFCTR register Table 3 3 9 Sampling Cycle Time of Noise Remove Function NFnCKS1 NFnCKSO Sampling cycle fs 1
375. election Oscillation stabiliza output tion wait period selec selection tion OxO3F 11 P1OUT P1OUT7 1 6 P1OUT5 P1OUT4 P1OUT3 P1OUT2 P1OUT1 P1OUTO IV 7 x x x x x x x x Port 1 output data 0x03F12 P2OUT P2OUT7 IV 22 1 2 A Output data Reset output 0x03F13 P3OUT P3OUT7 P3OUT6 P3OUT5 P3OUT4 P3OUT3 P3OUT2 P3OUT1 P3OUTO IV 26 x x x x x x x x Port 3 output data Special Function Registers List XVII 9 Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3F15 P5OUT 6 5 P50UT3 P5OUT2 P5OUT1 P5OUTO IV 41 x x x x x x x Port 5 output data 0x03F17 P7OUT P7OUT7 P7OUT6 P7OUT5 P7OUT4 P7OUT3 P7OUT2 P7OUT1 P7OUTO IV 51 x x x x x x x x Port 7 output data 0x03F19 P9OUT 67 s s x Port 9 output data OxO3F1A PAOUT PAOUT6 5 PAOUT4 PAOUT3 PAOUT2 PAOUT1 PAOUTO IV 74 x x x x x x x Port A output data OxO3F1B P1ODC P17ODC P150DC P110DC P100DC IV 11 0 0 0 0 P17 P15 P11 P10 open open open open drain drain drain drain control control control control OxO3F1C P1OMD P1OMD7 P1OMD P1OMD P1OMD P1OMD NBUZSE P1OMD BUZSEL IV 10 6 5 4 3 L 2 0 0 0 0 0 0 0 0 port port port I O port port I O port I O po
376. ensity So the power circuit should be designed taking into consideration of AC line noise ripple caused by LED driver Figure 1 7 6 shows an example for a circuit with Vpp Emitter follower type B An Example for a Circuit with Vpp Emitter follower type Set condensors for noise filter near microcomputer power pins VDD Microcomputer Vss For Noise filter Figure 1 7 6 An Example for a Circuit of Vpp Supply Emitter follower type Cautions for Circuit Setup 1 39 Chapter 1 Overview 40 Cautions for Circuit Setup Chapter 2 CPU Basics Chapter 2 CPU Basics 1 2 2 1 Overview The MN101C CPU has a flexible and optimized hardware configuration It is a high speed CPU with a simple and efficient instruction set Specific features are as follows 1 Minimized code sizes with instruction lengths based on 4 bit increments The series keeps code sizes down by adopting a basic instruction length of one byte and variable instruction lengths based on 4 bit increments 2 Minimum execution instruction time is one system clock cycle 3 Minimized register set that simplifies the architecture and supports C language The instruction set has been determined depending on the size and capacity of hardware after on analysis of embedded application programing code and creation code by C language compiler Therefore the set is simple instruction using the minimal register set required for C language compiler
377. ent supply ability can be larger XVI 20 Operation 16 4 Display Chapter 16 LCD Figure 16 4 1 to Figure 16 4 4 show example of connections display and waveforms of the LCD panel in 1 2 duty 1 3 duty 1 4 duty and static 16 4 4 Static B Static SegmentLatch MN101C78 bit7 bit3 bit6 bit2 bit5 bit1 bit4 bit0 SEGG 5 SEG4 ISEG3 SEG2 SEG1 ISEGO A electrode B electrode Bl Light on Light OFF LCDPANEL LCD ON COM S COM S LCD OFF SEG S SEG N EER Uncertain Data 1 0 Uncertain COM SEG COM SEG Light ON Light OFF Light OFF S selected voltage N non selected voltage Vicp LCD driver voltage On static always outputs selected voltage Display XVI 21 Chapter 16 LCD COMO VLCD SEG4 data SEG6 data 1 55 pem MC ss s 4 VLCD A electrode 0 COMO SEG4 92751077574 Light OFF EM Vico 4 VLCD B electrode COMO SEG6 Light ON Figure 16 4 1 LCD Display in Static XVI 22 Display Chapter 16 LCD 16 4 2 Setup Example Static Him s sO u 2 3 2 Setup example of the LCD static An example of setup procedure to display 23 on single digit 8 segment type LCD panel with both segment signals SEGO to SEG7 and common signals
378. ent condition For example if the operation temperature is over the condition improper operation could be occurred 3 Operation voltage should be also well considered Each product has different operating range the operation voltage is over the operating range duration of the product could be shortened the operation voltage is below the operating range improper operation could be occurred Cautions for Circuit Setup 1 35 Chapter 1 Overview 1 7 2 Unused pins sr n st Unused Pins only for input Insert some 10 resistor to unused pins only for input for pull up or pull down If the input is unstable Pch transistor and Nch transistor of input inverter are on and through current goes to the input circuit That increases current consumption and causes power supply noise Input Pin some 10 ko Input some 10 Input Pin Figure 1 7 1 Unused Pins only for input Current Through Current Pch Input Pin Input Nch 0 3 Input Voltage 3 V Input Inverter Characteristics Input Inverter Organization Figure 1 7 2 Input Inverter Organization and Characteristics 36 Cautions for Circuit Setup Chapter 1 Overview Unused Pins for Unused pins should be set according to pins condition at reset If the output is high impedance Pch Nch transistor output off at reset to stabilize input set some 10 resistor to be pull up or pull down If
379. er B C E Interrupt request flag Figure 5 4 1 Count Timing of Timer Operation Timer 0 1 2 and 3 A If the value is written to the compare register during the TMnEN flag is stopped 0 the binary counter is cleared to 0 00 at the writing cycle B If the TMnEN flag is operated 1 the binary counter is started to count e the binary counter reaches the value of the compare register the interrupt request flag is set at the next count clock then the binary counter is cleared to 0x00 and the counting is restarted D Even if the compare register is rewritten during the TMnEN flag is enabled 1 the binary counter is not changed the TMnEN flag is stopped 0 the binary counter is stopped 8 bit Timer Chapter 5 8 bit Timers When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 If the compare register is set to smaller than the binary counter during the count operation the following operations occur by the values of binary counter and compare register 1 When using as the 8 bit timer binary counter counts up until overflow once 2 When using as the 16 bit timer with cascade connection if the upper 8 bit value of binary counter reaches the upper 8
380. er VII Chapter 7 Time Base Timer Free running Timer 15 Chapter 7 Time Base Timer Free running Timer Count Timing Timer Operation Time Base Timer The counter counts up with the selected clock source as a counter clock 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 13 10 9 8 7 1 2 1 2 1 2 1 2 1 2 1 2 Figure 7 4 1 Count Timing of Timer Operation Time Base Timer When the selected interrupt cycle is passed the interrupt request flag of the time base interrupt control register TBICR is set An interrupt may be generated at switching of the clock source Enable the interrupt after switching the clock source The initialization can be done by writing an arbitrary value to the time base timer clear control register TBCLR When fx is selected as a clock source the time base timer may not be initialized For pre Y vention write twice to the time base timer clear control register TBCLR VII 16 Time Base Timer 7 42 Setup Example Chapter 7 Time Base Timer Free running Timer Timer Operation Setup Time Base Timer An interrupt can be generated constantly with time base timer in the selected interrupt cycle The interrupt gener ation cycle is fosc x 1 213 1 ms fosc 8 192 MHz to generate interrupts An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the clock source TM6MD 0xOSF62 TM6CKO
381. er 3 and 4 can be set at the same time 5 Set the A D ladder resistance Set ANLADE flag of the A D converter control register 0 ANCTRO to 1 and a current flow through the ladder resistance and A D converter goes into the waiting 6 Start A D conversion Set the ANST flag of the A D converter control register 2 ANCTR2 to 1 to start A D converter Set the REDGO flag of the external interrupt 2 control register IRQ2ICR and the EDGSEL flag of the edge interrupt control register EDGDT to specify the valid edge 7l A D conversion After sampling by the sample hold time set at the procedure 4 A D conversion is decided in comparison with MSB in order 8 Complete the A D conversion When A D conversion is completed the ANST flag is cleared to 0 and the result of the conversion is stored to the A D buffer ANBUFO 1 Then the A D complete interrupt request ADIRQ is generated 8 Operation Chapter 15 A D Converter Set the ANLADE flag to 1 and wait 12 conversion clock to start A D conversion During A D conversion when the ANST flag is set to 0 to forcefully stop A D conversion more than 2 system clock 2 conversion clock time is required to restart A D conversion When A D conversion start factor is selected as start by external interrupt and ANST flag is Set to 0 to forcefully stop A D conversion set always A D conversion start factor 10 0 before clearing the ANST f
382. er IRQ2ICR or EDGSEL2 flag of the both edges interrupt control register EDGDT Specify the valid interrupt edge before selecting the interrupt factor by the A D conversion Y start factor A D Conversion Start Setup A D conversion start is set by the ANST flag of the ANCTR2 register The ANST flag of the ANCTR2 register is set to 1 to start A D conversion When selecting external interrupt 2 as the A D conversion start factor set the ANST flag of ANCTR2 register to 1 after the external interrupt 2 is generated Also during A D conver sion the ANST flag of the ANCTR2 register is set to 1 and cleared to 0 after the converted data is stored Operation XV 11 Chapter 15 A D Converter XV 12 15 3 2 Setup Example B Example of A D Converter Setup by Registers A D conversion is started by setting registers The analog input pins are set to ANO the converter clock is set to fs 4 and the sampling hold time is set to 2 Then A D conversion complete interrupt is generated example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the analog input pin PAIMD 0x03F4E PAIMDO 1 PAPLUD 0x03F4A PAPLUO 0 2 Select the analog input ANCTR1 0x03FCC bp2 0 ANCHS2 0 000 3 Select the A D converter clock ANCTRO 0x03FCB bp5 4 ANCK1 0 01 4 Set the sample hold time
383. er SCOSTR 0x03F95 6 5 4 3 2 1 Chapter 11 Serial interface 0 0 SCOTBS SCORBSY SCOTEMP SCOREMP SCOFEF SCOPEK SCOORE SCOERE 0 0 SCOTBSY R Description Serial bus status 0 Other use 1 Serial transmission in progress R SCORBSY Serial bus status 0 Other use 1 Serial reception in progress SCOTEMP Transmission buffer empty flag 0 Empty 1 Full SCOREMP Reception buffer empty flag 0 Empty 1 Full SCOFEF Framing error detection 0 No error 1 Error SCOPEK Parity error detection 0 No error 1 Error SCOORE Overrun error detection 0 No error 1 Error SCOERE Error monitor flag 0 No error 1 Error Control Registers XI 11 Chapter 11 Serial interface 0 XI 12 Serial interface I O pin switching control Register SCSEL 0x03F90 7 6 5 4 TEMPSC 12 TEMPSC TEMPSCO TEMPSCO 11 0 0 TMPSC12 TMPSC11 Description Serial 1 used timer 2 output dividing switching XO0 Timer 2 output 01 Timer 2 output divided by 2 11 Timer 2 output divided by 8 02 5 01 Serial 0 used timer 2 output dividing switching XO0 Timer 2 output 01 Timer 2 output divided by 2 11 Timer 2 output divided by 8 Serial 4 pin switching 0 A P10 P11 1 B P76 P77 Serial 1 pin switching 0 A P15 to P17 1 B PA4 to PA6 Control
384. er bit MSB Input edge Falling edge Output edge Rising edge Clock Clock master Clock source fs 2 Clock source dividing Not divided Pin A port A SBTO SBOO pin style Nch open drain SBTO pin pull up resistor Added SBOO pin pull up resistor Added serial 0 communication complete Enable interrupt SBOO output after last data output 1 H fix An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation 1 Set the SCOPSCE flag of the SCOMDS register to 1 to SCOMD3 0x03F94 select prescaler operation bp3 SCOPSCE 1 2 Select the clock source 2 Set the SCOPSC2 to 0 flag of the SCOMDS register to SCOMD3 0x03F94 100 to select the fs 2 as the clock source bp2 0 SCOPSC2 0 100 3 SBOOA output control after the last data is 3 Set the SCOFDC1 to 0 flag of the SCOMDS register to output 00 to select 1 High fix of the SBOO last data SCOMD3 0x03F94 output bp7 6 SCOFDC1 0 00 XI 34 Operation Chapter 11 Serial interface 0 Setup Procedure Description 4 Select the pin SCSEL 0x03F90 bp SCOSL 0 5 Control the pin style PAODC 0x03F2D bp2 PAODC2 1 bp0 PAODCO 1 PAPLU 0x03F4A bp2 PAPLU2 1 1 6 Control the pin direction PADIR 0x03F3A bp2 PADIR2 1 bp1 PADIR1 0 PADIRO 1 7 Set the SCOMDO register Select the transfer bit count SCOMDO 0x03F91 bp2 0
385. er input Port input data R BUZZER output Timer 8 input Timer 8 output eset S P1CNTO1 Q E R Output control K R Pull up pull down resistor selection Pull up pull down resistor control V O direction control Port output data Buzzer output control Port output control Port input data NBUZZER output Timer 7 input Timer 7 output fs fosc Clock type selection Clock output control 620 ur 2 z U o m E L XCE Figure 4 2 3 Block Diagram P12 P12 R Reset DAJ P1PLUD3 Y P1DIRS R 1 9 Ji gt fo a 19 XCE Reget P1OMD3 I xc R P1IN3 Schmitt trigger input Chapter 4 Ports P13 sng eeg Figure 4 2 4 Block Diagram P13 Port 1 IV 17 Chapter 4 Ports Edge event External interrupt 0 IRQ0 holding function Reset 100 4 Nch open drain control t Wek R Y Pull up pull down resistor selection 1 Wek R V
386. er of priority It is however possible to alter this arrangement 1 To disable interrupt nesting Reset the MIE bit in the PSW to 0 Raise the priority level of the interrupt mask IM in the PSW 2 enable interrupts with lower priority than the currently accepted interrupt Lower the priority level or the interrupt mask IM in the PSW Multiplex interrupts are only enables for interrupts with levels higher than the PSW interrupt mask level IM It is possible to forcibly rewrite IM to accept an interrupt with a priority lower than the interrupt being processed but the careful of stack overflow Do not operate the maskable interrupt control register xxxICR when multiple interrupts are Y enabled If operation is necessary first clear the PSW MIE flag Overview Ill 13 Chapter 3 Interrupts B Multiple Interrupt of Non maskable On the acceptance of nim interrupt when other nmi interrupt factor is generated this interrupt is processed right away Also when the same nmi interrupt factor is generated before nmi interrupt flag is be soft cleared it is not accepted Unless nmi interrupt clears the flag by the soft the following same nmi interrupt is not accepted and valid nmi interrupt A nmi interrupt A generation generation 7 gt nterrupt acceptance cycle nmi interrupt A service program himi interrupt B generation nterrupt acceptance cycle nmi interrupt A s
387. er operation 1 Cascade connection 3 TM1EN Timer 1 count control 0 Halt the count 1 Operate the count 2 0 TM1CK2 Clock source selection TM1CK1 X00 fosc TM1CKO X01 TM1PSC Prescaler output 010 fx 011 Synchronous fx 110 TM11O input 111 Synchronous TMOIO input Control Registers V 15 Chapter 5 8 bit Timers Timer 2 Mode Register TM2MD 0x03F5C V 16 bp 6 5 4 2 1 0 Flag TM2POP TM2MOD TM2PWM TM2CK2 TM2CK1 TM2CKO At reset 0 0 0 0 0 0 Access Description TM2POP Output signal start polarity selection 0 Timer output PWM 1 Timer output PWM LH TM2MOD Pulse width measurement control 0 Normal timer operation 1 P56 pulse width measurement TM2PWM Timer 2 operation mode selection 0 Normal timer operation 1 PWM operation TM2EN Timer 2 count control 0 Halt the count 1 Operate the count TM2CK2 TM2CK1 TM2CKO Control Registers Clock source selection X00 fosc X01 TM2PSC Prescaler output 010 fx 011 Synchronous fx 110 TM2IO input 111 Synchronous 2 output Chapter 5 8 bit Timers Timer 3 Mode Register TM3MD 0x03F5D 4 2 1 0 5 TM3CK2 TM3CK1 0 0 0 0 Description 5 Timer 3 operation mode selection 0 Normal timer operation 1 Cascade connection Timer 3 count control 0 Halt the count
388. eration Dead Time IGBT Output Operation Timer 7 Dead time IGBT output can be selected at the T7IGBTEN of the timer 7 mode register 3 TM7MD3 Also dead time can be set to the dead time preset register 1 and 2 TM7DEADPRI 2 Only the timer 7 of 16 bit timer can use dead time IGBT output functions IGBT Trigger Selection IGBT trigger can be selected from IRQO IRQ1 IRQ2 and the start of the timer 7 count operation Setup should be done at the T7IGBTO and T7IGBTI flag of the TM7MD3 register When the startup is controlled from external of the micro controller one of IRQO to IRQ2 should be selected This trigger detects the input level before activation Either L level can be selected with the T7IGBTTR flag of the TM7MD3 register When 1 is selected count operation continues while the trigger pin is H When 0 is selected count opera tion continues while the trigger pin is L To control the startup by the commands TM7EN count operation should be selected In that case timer count operation or IGBT output are controlled by the TM7EN flag of the TM7MDI register When 1 count opera tion is selected count continues counting until 0 count stop is set Make sure to set the TM7IGBTO 1 of the TM7MD3 register before operating the TM7EN flag of the TM7MDI register In that case setup of T7IGBTTR is neglected The binary counter is cleared as the counting stops The value is loaded fr
389. erations shift operations and calculates operand addresses for register relative indirect addressing mode Internal ROM RAM Assigned to the execution program data and stack region Address register Stores the addresses specifying memory for data transfer Stores the base address for register relative indirect addressing mode Overview Chapter 2 CPU Basics Data register Holds data for operations Two 8 bit registers can be connected to form a 16 bit register Interrupt controller Detects interrupt requests from peripheral functions and requests CPU shift to interrupt processing Bus controller Controls connection of CPU internal bus and CPU external bus Includes bus usage arbitration function Internal peripheral functions Includes peripheral functions timer serial interface A D converter D A converter etc Peripheral functions vary depending on the model Overview 1 5 Chapter 2 CPU Basics Il 6 2 1 2 This LSI locates the peripheral circuit registers in memory space 0x03F00 to with memory mapped CPU Control Registers O CPU control registers are also located in this memory space Table 2 1 3 CPU Control Registers data on interrupt process Registerss Address R W Function Pages CPUM 0x03F00 R W CPU mode control register 11 24 1 II 28 MEMCTR 0x03F01 R W Memory control register 11 20
390. eriods 00 None 01 2nd period 10 1st 3rd periods 11 1st 2nd 3rd periods TMOADDEN Additional pulse method PWM output control 0 Disabled 8 bit PWM output 1 Enabled TM2PSC1 TM2PSCO TM2BAS Clock source selection 000 fosc 4 010 fosc 16 100 fosc 32 110 fosc 64 X01 fs 2 X11 fs 4 Timer 3 Prescaler Selection Register CK3MD 0x03F5F 2 1 0 TM3PSC1 TM3PSCO TM3BAS 0 0 0 R W Description TM3PSC1 5 0 TM3BAS Clock source selection 000 fosc 4 010 fosc 16 100 fosc 64 110 fosc 128 X01 fs 2 X11 fs 8 Control Registers V 11 Chapter 5 8 bit Timers 9 2 9 Programmable Timer Registers Each of timer 0 to 3 has 8 bit programmable timer registers Programmable timer register consists of compare register and binary counter Compare register is 8 bit register which stores the value to be compared to binary counter are stocked Timer 0 Compare Register TMOOC 0x0O3F52 7 6 5 4 3 2 1 0 TMOOC7 TMOOC6 00 5 TMOOCA TMOOCS3 TMOOC2 TMOOC1 TMOOCO X X X X X X X X Timer 1 Compare Register TM1OC 0x03F53 7 6 5 4 2 1 0 1 7 TM10C6 TM10C5 TM10C4 10 2 TM10C1 10 0 X X X X X X X Timer 2 Compare Register TM2OC 0x03F5A 7
391. erred from A to F TXBUFS F E D C B Figure 13 3 2 Transfer Bit Count and First Transfer Bit MSB First C B Figure 13 3 3 Transfer Bit Count and First Transfer Bit LSB First Receive Bit Count and First Transfer Bit When the transfer bit count is 1 to 7 bits data storage to the transmit receive shift register SC3TRB depends on the first transfer bit When MSB is the first bit to be transferred the lower bits of SC3TRB are used for storage In Figure 13 3 4 as the transfer bit count is 6 bits data to are stored to bp5 to of SC3TRB and they are transferred from F to A When LSB is the first bit to be transferred use the upper bits of SC3TRB for storage In Figure 13 3 5 data A to F are stored to bp2 to bp7 of SC3TRB as the transfer bit count is 6 bits and they are transferred from A to F SC3TRB A B C D E F Figure 13 3 4 Receive Bit Count and First Transfer Bit MSB First 7 6 5 4 3 2 1 0 scarme F 3 Figure 13 3 5 Receive Bit Count and First Transfer Bit LSB First Continuous Transmission Serial interface 3 is capable of continuous transmission If data is set to transmission data buffer TXBUF3 during transmission transmission buffer empty flag SC3TEMP is set and the set data is automatically transmit Set data to TXBUF3 in the period that after data is loaded
392. errupt control ANCK1 Reserved y ANSHO ANSTSELIIL A D conversion ADIRQ i ANSH1 ANST gt control ANBUF1 ANBUFO 5 ANBUF10 5 3 ANBUFT1 ANBUF12 ANBUF13 ANBUF14 ANBUF15 ANBUF16 ANBUFO6 ANBUF17 ANBUFO7 7 7 Y 2 2 A D conversion 5 Y data upper 8 bits AN1 p an2 X MUX Sample and 10 bits A D MU hold comparator pni A D conversion AN5 data lower 2 bits AN6 Vss fs 2 15 4 4 12 gt fs 8 MUX fx 2 MUX 1 18 1 18 Figure 15 1 1 A D Converter Block Diagram Overview XV 3 Chapter 15 A D Converter 15 2 Control Registers A D converter consists of the register ANCTRn and the data storage buffer ANBUFn 15 2 1 Registers Table 15 2 1 shows the registers used to control A D converter Table 15 2 1 A D Converter Control Registers Register Address Function ANCTRO 0x03FCB A D converter control register 0 1 OxO3FCC A D converter control register 1 ANCTR2 OxO3FCD A D converter control register 2 ANBUFO A D converter data storage buffer 0 ANBUF 1 A D converter data storage buffer 1 ADICR Ox03FF4 A D converter interrupt control register IRQ2ICR Ox03FE4 External interrupt 2 control register EDGDT OxOSF1E Both edges interrupt control register PAIMD Ox03F4E Port A input mode register PAPLUD Ox03F4A Port A Pull up resistor control register
393. ers Serial interface Status Register SC3STR 0x03FA3 bp 5 Chapter 13 Serial Interface 3 Flag SC3TEMP At reset 0 Access R Description SC3TEMP Transfer buffer empty flag 0 Empty 1 Full Control Registers XIII 9 Chapter 13 Serial Interface 3 Serial interface Control Register SC3CTR OxO3FA6 bp 7 6 5 4 3 2 1 0 Flag IICSBSY IIC3STC IICSSTPC IICSTMD SC3CMD IICSACKS At reset 0 0 0 0 0 0 0 0 Access R IICSBSY Description Serial bus status in communication 0 Other use 1 Serial transnission is in progress IIC3STC Start condition 0 Disable start condition 1 Enable start condition 1 IICSSTPC Stop condition detection flag in communication 2 0 undetected 1 detected IICSTMD Communication mode 0 NORMAL mode 1 High speed mode IICSREX Transmission reception mode selection 0 Transmission 1 Reception SC3CMD Synchronous selection 0 Synchronous 1 bit enable 0 Disable 1 Enable bit level selection 3 0 L level 1 H level 1 1 is not writable 2 0 is not writable Also this is not writable at the forced reset when the SC3SBOS flag and SC3SBIS flag of SC3MD1register are 0
394. ervice program nmi interrupt A generation 2 Despite of nmi interrupt A flag nmi interrupt B is serviced with multiple interrupts If nmi interrupt A flag is cleared multipul interrupt generates nterrupt acceptance cycle nmi interrupt B service program If nmi interrupt A flag is not cleared it is invalidation absolutely RTI When nmi interrupt AZIRQNPG nmi interrupt BSIRQNWDG When nmi interrupt A IRQNWDG nmi interrupt B IRQNPG 14 Overview Chapter 3 Interrupts Figure 3 1 7 shows the processing sequence of the multiple interrupt multiple interrupt xxxLV1 to 0 10 xxxLV1 to 0 00 Main program IM1 0 11 Interrupt 1 generated z Accepted because IL lt IM xxxLV1 0 10 Interrupt acceptance cycle 1 1 0 0 Interrupt service program 1 Accepted because IL IM Interrupt 2 generated xxxLV1 0 00 Interrupt acceptance cycle 1 1 0 00 Interrupt service program 2 D Restart interrupt service program 1 RTI IM1 0 10 RTI IM1 0 11 Y Parentheses indicates hardware processing Figure 3 1 7 Processing Sequence for Non Maskable Multiple Interrupt Overview 15 Chapter 3 Interrupts 3 1 4 Interrupt Flag Setup B Interrupt Request Flag IR Setup by the Software The interrupt
395. es the standard specification Machine cycle system clock fs is described based on the standard mode 1 2 of high oscillation at NORMAL mode or on the clock frequency 1 2 of low oscillation at SLOW mode Please ask our sales offices for the prod uct specifications Model MN101C78A Structure CMOS integrated circuit Contents Application General purpose Function CMOS 8 bit single chip micro controller Electrical Characteristics 21 Chapter 1 Overview 1 5 1 Absolute Maximum Ratings 2 3 40 to 85 Parameter Symbol Rating Unit 1 Power supply voltage Vpp 0 3 to 44 6 V 2 Input clamp current lc 400 to 400 3 Input pin voltage Vi 0 3 to Vpp 0 3 4 Output pin voltage Vo 0 3 to 0 3 V 5 pin voltage 0 3 to Vpp 0 3 except ACZ 6 59000 lon peak 30 7 Peak output current 2 peak 10 to P53 8 All pins peak 10 9 5599 lot 20 Average output Other 10 current 1 than P50 loj 2 avg 5 to P53 11 All pins lon avg 5 12 Total output current 1 60 13 ITOH 60 14 Power dissipation 400 85 mW 16 Storage temperature Tstg 55 to 125 1 Applied to any 100 ms period 2 Connect at least one bypass capacitor of 0 1 uF or larger between the power supply pin and the ground for latch up prevention 3 T
396. est flag is already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 16 bit Event Count VI 33 Chapter 6 16 bit Timers VI 34 Setup Procedure Description 10 Enable the interrupt TM7ICR 0xO3FED bp1 TMT7IE 1 11 Start the event count TM7MD1 0x03F78 bp4 TM7EN 1 10 Set the TM7IE flag of the TM7ICR register to 1 to enable the interrupt 11 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 Every time TM7BC reaches the falling edge of the TM7IO input it counts up from 0x0000 When the TM7BC reaches the set value of the 7 register the timer 7 interrupt request flag is set at the next count clock and the value of TM7BC becomes 0x0000 to restart counting up Allow the setup procedures 4 to 8 to have the correct operation 16 bit Event Count Chapter 6 16 bit Timers 6 5 16 bit Timer Pulse Output 6 5 1 Operation TMnIO pin can output a pulse signal with a arbitrary frequency 16 bit Timer Pulse Output Operation Timer 7 Timer 8 These timers can output 2 x cycle signal compared with the set value of the compare register 1 TMnOC1 and the 16 bit full count Output pins are as follows Table 6 5 1 Timer Pulse Output Pin Timer 7 Timer 8 Pulse output TM7IO output 8 output pin P13 P12 7 output 8 output P51 P53 Table 6 5 2 shows the timer inte
397. et IGBT output TM7MD3 x 3F8E bp2 TM7IGBTEN 1 4 Set the high precision IGBT output operation TM7MD2 x 3F79 bp5 TM7BCR 1 bp6 T7PWMSL 1 TM7MD4 x 3F6E bp3 T7NODED 1 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Set the P1OMDS flag of the port 1 output mode register P1OMD to 1 the NBUZSEL flag to 1 to set the P13 pin to the special function pin Set the P1OMD2 flag of the port 1 output mode register to 1 the BUZSDEL flag to 1 to set the P12 pin to the special function pin Set the P1DIR3 flag of the port 1 direction control register P1DIR to 1 the P1DIR2 flag to 1 to set the output mode Add pull up pull down resistor if necessary Chapter 4 port 3 Set the T7IGBTEN flag of the timer 7 mode register 3 TM7MD3 to 1 to select IGBT output 4 Set the TM7BCR flag of the TM7MD2 register to 1 to select the TM7OC1 compare match as the clear factor of the binary counter Set the T7PWMSL flag to 1 to select the TM7OC2 compare match as the duty determination factor of IGBT output Set the T7NODED flag of the TM7MD4 register to 1 to select the IGBT waveform without dead time VI 62 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively Chapter 6 16 bit Timers Setup Procedure Description 5 Select IGBT trigger generation interrupt source T
398. et the interrupt level SC1TICR 0x03FF2 bp7 6 SC1LV1 0 10 14 Enable the interrupt SC1TICR OxOSFF2 bp1 SC1TIE 1 SC1TIR 20 15 Set the startup factor of the serial communication Dummy data gt TXBUF1 b Set the P1DIR7 P1DIR6 flag of the Port 1 pin direction control register P1DIR to 1 and the P1DIR5 flag to 1 to set P17 P16 to the input mode P15 to the output mode 6 Set the SC1LNG2 to 0 flag of the serial 1 mode register SC1MDO to 111 to set the transfer bit count as 8 bits 7 Set the SC1STE flag of the serial 1 mode register SC1MD O to 1 to disable the start condition 8 Set the SC1DIR flag of the SC1MDO register to 0 to set MSB as a transfer first bit 9 Set the SC1CE1 flag of the SC1MDO register to 1 to set the reception data input edge falling 10 Set the SC1CMD flag of the SC1MD1 register to 0 to select the synchronous serial 11 Set the SC1MST flag of the SC1MD1 register to 0 to select the clock slave external slave Set the SC1CKM flag to 0 to select not divided for the clock source 12 Set the SC1SBOS flag of the SC1MD1 register to 0 the SC1SBIS flag SC1SBTS flag to 1 to set the SBO1 pin to a general port the SBI1 pin to the serial data input the SBT1 pin to the transfer clock input output Set the SC1IOM flag 0 to set the serial data input from the 5 pin 13 Set the interrupt level by the SC1LV1 to 0 flag of t
399. etection circuit is not used this pin can be used as a normal P54 P55 input KEYO 33 30 Input P70 SEG7 Key interrupt input Input pins for interrupt based on ORed result KEY1 34 31 P71 SEG6 pins of pin inputs KEY2 35 32 P72 SEG5 Key input pin for 1 bit can be selected KEY3 36 33 P73 SEG4 individually by the key interrupt control KEY4 37 34 P74 SEG3 register KEYT3_1IMD KEYT3_2IMD KEY5 38 35 P75 SBOOB TXDOB SEG2 When not used for KEY input these pins can KEY6 39 36 P76 SBIOB RXDOB SDA4B be used as a normal I O pins SEG1 KEY7 40 37 P77 SBTOB SCL4B SEGO LEDO 1 1 VO P50 LED drive pins Large current output pins LED1 2 2 P51 7 When not used for LED output these pins LED2 3 3 P52 TM20A can be used as a normal I O pins LED3 4 4 P53 8 1 Not available for 44 pin QFP package 1 18 Pin Description Chapter 1 Overview Name Ga NC yo Other Function Function Description CLKOUT 28 25 Output P13 TM7IO NBUZZER Oscillation clock signal output pin COMO 41 38 Output P30 LCD common out These pins output the common signal with COM1 42 39 P31 SBI3 put pin the required timing for the LCD display COM2 43 40 P32 SBT3 SCL3 Connect to the common pins of LCD display COMS 44 41 P33 5803 SDA3 panel When the LCD display panel is turned off Vss is output When the LCD functions are unused they can be used as a normal port by setting the LCD output
400. etup Note Procedures 1 to 3 5 6 7 to 8 can be set at the same time Operation Reception Setup Example Chapter 11 Serial interface 0 The setup example for clock synchronous serial communication with serial 0 is shown Table 11 3 12 shows the conditions at Reception Table 11 3 13 Setup Examples for Synchronous Serial Interface Reception Setup item Set to Serial data input pin Select SBIO 3 channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Output edge Rising edge Clock Clock Slave Clock source fs 2 Clock source dividing Not divided Pin A port A SBTO SBOO pin style Nch open drain SBTO pin pull up resistor Added 5800 pin pull up resistor Added serial 0 communication complete interrupt Enable 5800 output after last data output 1 H fix An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation SCOMD3 0x03F 94 bp3 SCOPSCE 1 2 Select the clock source SCOMD3 0x03F 94 bp2 0 SCOPSC2 0 100 output SCOMD3 0x03F94 bp7 6 SCOFDC1 0 00 4 Select the pin SCSEL 0x03F90 SCOSL 0 5 Control the pin style PAODC 0x03F2D bp2 PAODC2 1 bp0 PAODCO 1 PAPLU 0x03F4A bp2 PAPLU2 1 1 3 SBOOA output control after the last data is select pre
401. external interrupt 1 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 4 External Interrupt 1 Control Register IRQ1ICR 0x03FE3 7 6 1 0 IRQ1LV1 IRQ1LVO IRQ1IE IRQ1IR 0 0 0 0 IRQ1LV1 IRQ1LVO Description Interrupt level flag The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interrupt requests REDG1 Interrupt valid edge flag at the standby mode 0 Falling edge low level 1 Rising edge high level IRQ1IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQ1IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 21 Chapter 3 Interrupts B External Interrupt 2 Control Register IRQ2ICR The external interrupt 2 control register IRQ2ICR controls interrupt level of external interrupt 2 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSE is 0 Table 3 2 5 External Interrupt 2 Control Register IRQ2ICR 0x03FE4 7 6 1 0 IRQaLV1 IRQ2LVO IRQ2IE IRQ2IR 0 0 0 0 Description IRQ2LV1 Interrupt level flag IRQ2LVO The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interru
402. f the TM7ICR register to 1 to enable the interrupt 9 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 TM7BC counts up from 0x0000 When TM7BC reaches the set value of the register the timer 7 inter rupt request flag is set at the next count clock and the TM7BC becomes 0x0000 and counts up again Operation Chapter 6 16 bit Timers 6 4 16 bit Event Count 6 4 1 Operation Event count operation has 2 types TMnIO input and synchronous TMnIO input These can be selected as the count clock Each type can select 1 1 1 2 1 4 or 1 16 as a count clock source Also it is possible to select the count edge the falling edge and the both edge at the normal operation are selectable 16 bit Event Count Operation Timer 7 Timer 8 The binary counter TMnBC counts the external signal input to the TMnIO pin If the binary counter reaches the set value of the compare register TMnOC an interrupt can be generated at the next count clock Table 6 4 1 Timer 7 Timer 8 Event input TM7IO input P13 input P12 Synchronous TM7IO Synchronous 8 input input Count Timing of TMnIO Input When TMnIO input is selected TMnIO input signal is input to the timer n count clock The binary counter counts up at the falling edge of the TMnIO input signal or TMnIO input signal that passed the divider TM7IO input TM7EN flag Compare register 1
403. f the TM7IO to the timer 7 preset register 1 TM7DEADPR1 and from the falling of the TM7IO to the rising of the TM8IO to the timer 7 preset register 2 TM7DEADPR2 To make dead time which is from the TM7IO falling to the 8 rising is 0 02 ms and from the 8 falling to the TM7IO rising is 0 01 ms set Ox4F to the timer 7 dead time preset register 1 and Ox9F to the timer 7 dead timer preset register 2 12 Set T7IGBTEN flag of the timer 7 mode register 3 TM7MDJ3 to 1 to select the dead time IGBT output Set T78SEL flag of the timer 8 mode register 3 to 1 to select the timer 7 IGBT output 13 Set the P1OMD3 flag NBUZSEL flag P1OMD2 flag and BUZSEL flag of the port 1 output mode register P1OMD to 1 to set P13 and P12 as the special function pins Set the P1DIR3 flag and P1DIR2 flag of the port 1 direction control register P1DIR to 1 to set the output mode Chapter 4 Ports Set P13 P12 as the special function pins after setup procedures 1 to 13 Dead Time IGBT Output VI 77 Chapter 6 16 bit Timers VI 78 Setup Procedure Description 14 Start the timer operation TM7MD1 x 3F78 bp4 TM7EN 1 14 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 After H is input to P54 pin IGBT is output from P13 P12 TM7BC counts up from X 0000 The IGBT output waveform outputs H until TM7BC matches
404. face 0 Clock Setup Clock source is selected from the dedicated prescaler and timers 1 2 output 2 channels with the SCOPSC2 to 0 of the SCOMD3 register The dedicated prescaler is started by selecting count enable with the SCOPSCE flag of the SCOMD3 register The SCOMST flag of the SCOMDI register can select the internal clock clock master or the external clock clock slave Even if the external clock is selected set the internal clock that has the same clock cycle or lower to the external clock by the SCOMD3 register as the interrupt flag SCOTIRQ is generated by the internal clock The following is the internal clock source that can be set by the SCOMD3 register Also the SCOCKM flag of the SCOMDI register can divide the internal clock SCODIV flag can select the dividing ratio between divided by 8 and divided by 16 Table 11 3 3 Synchronous Serial Interface Internal Clock Source Serial Interface 0 Clock source fosc 2 internal clock fosc 4 fosc 16 fosc 64 fs 2 fs 4 Timer 1 output Timer 2 output Timer 2 output 2 Timer 2 output 8 Set always the SCOSBIS flag and SCOSBOS flag of the SCOMD 1 register to 0 before Y switching the clock setup munication the system configuration is required to notify the master of the readout comple a When the slave reception is executed with the start condition enable at the continuous com tion Without the
405. factor opera selection tor form Selection tion selection selection enable TM8OC2L TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 VI 13 L7 L6 L5 L4 L3 L2 L1 LO x x x x x x x x Timer 8 compare register 2 lower 8 bits 0x03F8B TM8OC2H TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 TM8OC2 13 H7 H6 H5 H4 H3 H2 H1 H0 x x x x x x x x Timer 8 compare register 2 upper 8 bits 0x03F8C TM8PR2L TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 VI 14 L7 L6 L5 L4 L3 L2 L1 0 x x x x x x x x Timer 8 preset register 2 lower 8 bits OxO3F8D TM8PR2H TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 TM8PR2 VI 14 H7 H6 H5 H4 H3 H2 H1 HO x x x x x x x x Timer 8 preset register 2 upper 8 bits XVII 18 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3F8E TM7MD3 TM7CKS Reserve TM7CKE T7IGBT T7IGBT T7IGBT T7IGBT1 T7IGBTO VI 18 MP d DG TR DT EN 0 0 0 0 0 0 0 0 Capture Set TM7IO IGBT IGBT IGBT IGBT Timer trigger sampling always count trigger dead opera selection to O edge level time tion selection selection insert enable timing OxO3F8F TM8MD3 TM8CKS TM8CKE TM8SEL TM8PW TM8PW TM8CAS VI 22 MP DG MF MO 0 0 0 0 0 0
406. fer bit counter SC1TBSY Data set to TXBUF1 A Interrupt SC1TIRQ Figure 12 3 9 Transmission Timing at rising edge start condition is disabled Operation XII 23 Chapter 12 Serial interface 1 Reception Timing Clock 5811 pin Input pin 581 5801 Transfer bit counter SC1RBSY Interrupt SC1TIRQ Figure 12 3 10 Reception Timing at rising edge start condition is enabled At master Tmax 3 5T T Clock SBT1 pin Input pin 5811 5801 pin Transfer bit count SC1RBSY Data set to TXBUF 1 Interrupt SC1TIRQ Figure 12 3 11 Reception Timing at rising edge start condition is disabled XII 24 Operation Chapter 12 Serial interface 1 Clock SBT1 pin Input pin 581 SBO1 pin Transfer bit counter SC1RBSY Interrupt SC1TIRQ Figure 12 3 12 Reception Timing at falling edge start condition is enabled At master Tmax 3 5T Clock SBT1 pin Input pin 5 1 5801 pin Transfer bit counter SC1RBSY Data set to TXBUF1 A Interrupt SC1TIRQ Figure 12 3 13 Reception Timing at falling edge start condition is disabled Operation XII 25 Chapter 12 Serial interface 1 Transmission Reception Timing As data is received at the opposite edge of the transmission clock set the polarity of reception data input edge to opposite polarity of the transmission data output edge When transmission
407. fer bit MSB Clock source Timer 1 Clock source dividing Divided by 8 Used pin A port 1 TXD1 RXD1 pin type Nch open drain Pull up resistor of TXD1 pin Added Parity bit add check 0 added check Serial 1 transmission complete Enable interrupt Serial 1 reception complete interrupt Enable An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the baud rate timer 2 Select the clock source SC1MD3 0x03F9C bp2 0 SC1PSC2 0 110 3 Select the used pin SCSEL 0x03F90 bp1 SC1SL 0 4 Control the pin style P1ODC 0x03F1B bp5 P1ODC5 1 P1PLUD 0x03F41 bp5 P1PLU5 1 1 Set the baud rate timer by the TM1MD register the 1 register Set the TM1EN flag to 1 to start timer 1 Chapter 5 5 8 Serial Transfer Clock Output Operation 2 Set the bp2 to 0 flag of the SC1MD3 register to 110 to select Timer 1 output as a clock source 3 Set the SC1SL flag of the SCSEL register to 0 to select A port 1 as I O pin 4 Set the P1ODC5 flag of the P1ODC register to 1 to select Nch open drain to TXD1 pin Set the P1PLUD5 flag of the P1PLUD register to 1 to enable the pull up resistor Operation XII 59 Chapter 12 Serial interface 1 Setup Procedure Description 5 Control the pin direction P1DIR 0x03F31 bp5 P1DIR5 1 bp6 P1DIR6 0 6 Set the SC1MDO register Select the
408. g Tmin 0 5T T Stop RXD1 pin bit SC1RBSY A Input start condition Interrupt uM NE SC1RIRQ Figure 12 3 22 Reception Timing parity bit is enabled Tmin 0 5T T f f Parity Stop Stop RXD1 pin bit SC1RBSY A Input start condition Interrupt TE SC1RIRQ Figure 12 3 23 Reception Timing parity bit is disabled Operation XII 49 Chapter 12 Serial interface 1 Transfer Speed Setup Baud rate timer timer 1 timer 2 can set any transfer rate Table 12 3 20 shows the setup example of the transfer speed Table 12 3 20 UART Serial Interface Transfer Speed Setup Register Page Serial 1 clock source timer 1 timer 2 SC1MD3 10 Clock source dividing SC1MD1 XII 8 Timer 1 clock source TM1MD V 15 Timer 1 compare register TM10C 12 Timer 2 clock source TM2MD V 16 Timer 2 compare register TM20C V 12 Timer compare register is set as follows baud rate 1 overflow cycle x 2 x internal clock dividing overflow cycle set value of compare register 1 x timer clock cycle therefore set value of compare register timer clock frequency baud rate x 2 x internal clock dividing 1 For example if baud rate should be 300 bps at timer clock source fs 4 fosc 8 MHz fs fosc 2 when the inter nal clock dividing is set to 8 set value should be as follows Set value of compare register 8 x 106 2 4 30
409. g 0 Slave Master 1 MasterSlave I2CINT Interrupt detection flag 0 Undetected 1 Detected Start condition detection 0 Undetected 1 Detected Re start condition detection 0 Undetected 1 Detected I2CBSY Bus busy flag 0 Bus free status 1 Bus busy status SLVBSY Slave busy flag 0 Other than during data transfer 1 During data transfer ACKVALID ACK detection flag 0 Undetected 1 Detected Overview XIV 7 Chapter 14 Serial Interface 4 Serial Interface Input Output Pin Switching Control Register SCSEL 0x03F90 bp 7 6 5 4 Flag TMPSC12 TMPSC11 5 02 01 At reset 1 0 0 0 Access TMPSC12 TMPSC11 Description Serial interface 1 used timer2 output dividing switching XO0 Timer 2 output 01 Timer 2 output 2 11 Timer 2 output 8 02 5 01 Serial interfaceO used timer2 output dividing switching XO0 Timer 2 output 01 Timer 2 output 2 11 Timer 2 output 8 Serial interface 4 I O pin switching 10 P11 1 P76 P77 Serial interface 1 pin switching 0 15 to P17 1 PA4 to PA6 XIV 8 Overview Serial interface 0 pin switching 0 0 to PA2 1 P75 to P77 Chapter 14 Serial Interface 4 14 2 Operation Activation and Termination Factors Set the SELI2C flag of the SCAADI register to 1 to activate this serial interface For the
410. g mode to the corresponding STANDBY HALT STOP modes by specifying the new mode in the CPU mode control register CPUM Interrupts initiate the return to the former CPU operating mode Before initiating a transition to a STANDBY mode however the program must 1 Set the maskable interrupt enable flag MIE in the processor status word PSW to 0 to disable all maskable interrupts temporarily 2 Set the interrupt enable flags xxxIE in the interrupt control registers XxxICR to 1 or 0 to specify which interrupts do and do not initiate the return from the STANDBY mode Set MIE 1 to enable those maskable inter rupts NORMAL SLOW SLOW mode Clear MIE flag the PSW and all interrupt enable flags xxx IE isable all interrupts in the maskable interrupt control register Enable interrupt which Set the xxx IE of the return factor triggers return and set MIE flag in the PSW HALT STOP We timer STOP counter clear Set HALT STOP mod When returning from STOP mode wait for oscillation to stabilize x Return factor interrupt occured Watchdog timer NORMAL SLOW _ HALT restarts counting mode STOP continue counting Interrupt acceptance cycle Y Figure 2 4 3 Transition to from STANDBY Mode or higher than the mask level in PSW before transition to HALT or STOP mode it is impossi lt If the i
411. g of the SCOTICR register to 1 to enable the interrupt If any interrupt request flag SCOTIR of the SCOTICR register is already set clear SCOTIR before the interrupt is enabled 11 Set the dummy data to the serial transmission data buffer TXBUFO After the dummy data is set when clock input is done after more than 3 5 transfer clock reception is started When reception is finished the serial 0 UART transmission interrupt SCOTIRQ is generated Chapter 3 3 1 4 Setup Operation Chapter 11 Serial interface 0 Note Each procedure 1 to 3 7 8 9 to 10 can be set at the same time At the reception with the start condition input set the SCOSTE flag to 1 to select start condi tion enable at the step 7 in the setup procedure At the step 11 execute the start condition input instead of setting dummy data After start condition input more than 0 5 transfer clock is required for the clock input For communication with 2 channels serial data is input output from the SBOO pin Input out put is switched by the port direction control register PADIR At reception set always SCOSBIS of the SCOMD 1 register to 1 to select serial input The SBIO pin can be used as a general port This serial interface contains a force reset function If the communication should be stopped by force set SCOSBOS and SCOSBIS of the SCOMD1 register to 0 Each flag should be set as this
412. g of the oscillation stabilization wait DLYCTR 0x03F03 control register to DLYCTR 0 to clear and P12 pin bp7 BUZOE 0 outputs low level When the low oscillation clock fx dividing is selected as the buzzer output frequency and the buzzer output is switched ON from OFF the buzzer dividing counter is not cleared unless more than 1clock of the low oscillation clock is secured a Setup of the buzzer output ON should be done after setup of the buzzer frequency Operation X 7 Chapter 10 Buzzer X 8 Operation Chapter 11 Serial interface 0 Chapter 11 Serial interface 0 XI 2 11 1 Overview This LSI contains a serial interface 0 that can be used for both communication types of clock synchronous and UART duplex Also the used pins can be switched to A port A PAO SBOOA TXDOA ANO PAI SBIOA RXDOA ANI PA2 SBTOA AN2 or to B Port 7 P75 SBOOB TXDOB KEY5 SEG2 P76 SBIOB RXDOB KEY6 SDA4A SEG1 P77 SBTOB KEYT SCLAB SEGO A and B are omitted 1 On this text if there are not much difference between port A and port B on the operation port 11 1 1 Functions Table 11 1 1 shows functions of serial interface 0 Table 11 1 1 Serial Interface O functions Communication style Clock synchronous UART duplex Interrupt SCOTIRQ SCOTIRQ on transmission completion SCORIRQ on reception completion Pins SBOO SBIO SBTO TXDO R
413. generation cycle 0x09C3 2500 cycles 1 At that time timer 1 binary counter timer 0 binary counter TM1BC TMOBO are initialized to 0 000 7 Set the TMOIE flag of the timer O interrupt control register TMOICR to 0 to disable the interrupt 8 Set the interrupt level by the TM1LV1 to 0 flag of the timer 1 interrupt control register TM1ICR If any interrupt request flag may be already set clear all request flags Chapter 3 3 1 4 Interrupt Flag Setup Cascade Connection Chapter 5 8 bit Timers Setup Procedure Description 9 Enable the upper timer interrupt TM1ICR OxOSFE8 TM1IE 1 10 Start the upper timer operation TM1MD 0x03F55 bp3 TM1EN 1 11 Start the lower timer operation TMOMD 0x03F54 bp3 TMOEN 1 9 Set the TM1IE flag of the TM1ICR register to 1 to enable the interrupt 10 Set the TM1EN flag of the TM1MD register to 1 to operate the timer 1 11 Set the TMOEN flag of the TMOMD register to 1 to operate the timer 0 TMIBC TMOBC counts up from 0x0000 as a 16 bit timer When 1 TMOBC reaches the set value of TMIBC TMOBC register the timer 1 interrupt request flag is set at the next count clock and the value of TMIBC TMOBC becomes 0x0000 and restarts count up Use a 16 bit access instruction to set the TM1OC register Start the upper timer operation before the lower timer operation
414. ger input Port input data lt SINS dA R Timer 8 output IV 46 Port 5 Figure 4 5 4 Block Diagram P53 Chapter 4 Ports 1 P5PLU4 3 Pull up resistor control R D WEK R PES p DIR direction control gt G Wek VR 9 SS P54 S P5OUTA P Port output data grt au w ai input 0 M Port input data lt PSIN4 U J R Xf Intermediate value detection circuit NFCTR register bp3 External interrupt 0 input AC zero cross 0 input Figure 4 5 5 Block Diagram P54 BE pspLus Pull up resistor control gt WEK R Reset P DIR direction control SDIBS gt m we Va 5 PQP Port output data ary id input 0 M Port input data lt pains Ul J R X5 __ Intermediate value detection circuit register bp7 External interrupt 1 input AC zero cross 1 input Figure 4 5 6 Block Diagram P55 Port 5 IV 47 Chapter 4 Ports Pull up resistor control direction control Port output data eq Port input data External interrupt 2 input IV 48 Port 5 Reget
415. gister A pull up pull down resistor for each port can be selected individually by the SELUD register However pull up and pull down resistors cannot be mixed At reset the input mode is selected and P10 P11 are pull up resistor enable H output P12 to P17 are pull up resistor disable output H Hi Z MMOD 11 11 Input Memory mode setting pins Input always L level It is used for Flash programming only P27 12 12 Input NRST port 2 Port P27 has an N ch open drain configuration When 0 is written and the reset is initiated by software L level will be output 1 14 Pin Description Chapter 1 Overview Name i VO Other Function Function Description Pin No Pin No P30 41 38 COMO port 8 bit COMS tri state I O port P31 42 39 SBI3 COM1 Each bit can be set individually as either an P32 43 40 SBT3 SCL3 COM2 input or output by the P3DIR register A pull P33 44 41 5803 SDAS3 up resistor for each bit can be selected P34 45 42 VLC3 individually by the P3PLU register P35 46 43 VLC2 At reset the input mode is selected and P36 47 44 VLC1 P37is pull up resistor enable H output P37 1 48 P31 to P37 are pull up resistor disable output Hi Z P50 1 VO TMOOA LEDO port 5 7 bit COMS tri state I O port P51 2 2 TM70 LED1 Each bit can be set individually as either an P52 3 3 2 LED2 input
416. gister P3DIR to 1 1 to set P32 P33 to output mode to set P31 to input mode b Set SC3LNG2 0 flag of the serial 3 mode register SC3MDO to 111 to set the transfer bit count as 8 bits Set the SC3STE flag of the SC3MDO register to 0 to disable start condition Set the SC3DIR flag of the SC3MDO register to 0 to set MSB as the first transfer bit Set the SC3CE1 flag of the SC3MDO register to 1 to set the transmission data output edge to rising and the received data input edge to falling 6 Set the SC3CMD flag of the SC3CTR register to 0 to select serial data tansmission 7 Set the SC3MST flag of the SC3MD1 register to 1 to select clock master internal clock Set the SC3SBOS SC3SBIS SC3SBTS flags of the SC3MD1 register to 1 to set the SBOS pin to serial data output the 5813 pin to serial data input and the SBT3 pin to serial clock I O Set the SC3IOM flag to 0 to set serial data input from the SBI3 pin 8 Set the interrupt level by the SC3LV1 0 flag of the serial interrupt control register SC3ICR 9 Set the SC3IE flag of the SC3ICR register to 1 to enable the interrupt If the interrupt request flag SC3IR of the SCS3ICR register is already set clear SC3IR before enabling interrupt 10 Set the transmission data to the serial transmission data buffer TXBUFS The internal clock is generated to start transmission reception After communication the serial 3 interrupt
417. gister 1 TM7MD1 the mode register 2 TM7MD2 the mode register 3 TM7MD3 and the mode register 4 TM7MD4 Timer 8 contains the binary counter TM8BC the compare register 1 TM8OCI1 with its double buffer preset register 1 TM8PR1 the compare register 2 TM8OC2 with its double buffer preset register 2 TM8PR2 and the capture register TM8IC Timer 8 is con trolled by the mode register 1 TM8MD1 the mode register 2 TM8MD2 the mode register 3 TM8MD3 and and the mode register 4 TM8MD4 Control Registers Chapter 6 16 bit Timers 6 2 1 Registers Table 6 2 1 shows the registers that control timer 7 Table 6 2 1 16 bit Timer Control Registers 1 2 Register Address Function Timer 7 TM7BCL 0x03F70 Timer 7 binary counter lower 8 bits TM7BCH 0x03F71 Timer 7 binary counter upper 8 bits TM7OC1L 0x03F72 Timer 7 compare register 1 lower 8 bits 7 0x03F73 Timer 7 compare register 1 upper 8 bits TM7PR1L 0x03F74 Timer 7 preset register 1 lower 8 bits TM7PR1H 0x03F75 Timer 7 preset register 1 upper 8 bits TM7ICL 0x03F76 Timer 7 capture register 1 lower 8 bits TM7ICH 0x03F77 Timer 7 capture register 1 upper 8 bits TM7MD1 0x03F78 Timer 7 mode register 1 TM7MD2 0x03F79 Timer 7 mode register 2 TM7OC2L Ox03F7A Timer 7 compare register 2 lower 8 bits TM7OC2H 0x03F7B Timer 7 compare register 2 upper 8 bits TM7PR2L 0x03F7C Timer 7 preset register 2 lower 8 bits TM7PR2H 0x03F7D Timer 7 preset reg
418. gleschip Mod niii ceder ge eet hee eta 17 2 2 3 Special Function Registers 4 aeo tuner eh RH EH II 18 2 3 Bus Interface sis tonio deed epe rb p II 19 2 34 Bus Controller oi ee he es Ree eee Se II 19 2 3 2 Control RE SISCETS iu eere ee Hoe eae ii ie Pcia t eed tm t ees II 20 2 4 Standby Functionh ete E Rp II 21 2 A l Overvie wi l nee II 21 2 4 2 CPU Mode Control RegISfer a II 24 2 4 3 Transition between SLOW and NORMAL II 25 2 4 4 Transition to STANDBY Modes essent ener nennen nennen II 26 2 5 Clock Switching oe eee gu Ue II 28 2 6 RESCU II 30 216 1 Reset operation c ecco eet te os rode e tee He a eie o ete pun II 30 2 6 2 Oscillation Stabilization Wait 4 II 32 Chapter 5 Interrupts P M E III 1 SES Aa AE 2 3 1 L Functions u u etr eer epp III 3 3 12 Block Diagram ehe nen Eee eee che at a 4 3 13 Operation 5 ote eed III 5 3 14 Interrupt Flag Set p III 16 32 Control Registers onsec ere e RUDI eie mE Res III 17 3 2 I Registers List nne idee Oa ess Ie tei ete ce teles III 17 3 2 2 Interrupt Control Registers a a coectetuer trei get III 19 3 3 External Interrupts bae
419. h bit can be selected individually as Nch open drain output by the port 3 Nch open drain control register The control flag of the port 3 Nch open drain control register is set to 1 for Nch open drain output and 0 for push pull output Special Function Setup P31 is used as the serial 3 reception data input pin and IIC3 reception data input pin as well P32 is used as the serial 3 clock I O pin as well When SC3SBTS flag of the serial interface 3 mode register 1 SC3MDI is 1 P32 is the serial clock output pin Push pull output or Nch open drain output can be selected by setting the Port 3 Nch open drain control register PSODC P33 is used as the output pin of the serial 3 transmission data and IIC3 transmission data as well When SC3SBTS flag of the serial interface 3 mode register 1 SC3MD1 is 1 P32 is the serial data output pin Push pull output or Nch open drain output can be selected by setting the Port 3 Nch open drain control register P3ODC P30 is used as the LCD common output pin COMO as well The COMO pin selection can be done by setting the bit 0 flag COMSLO flag of the LCD output control register 1 LCCTRI to 1 At common output it is force fully set to input mode and pull up resistor is disabled P31 is used as the LCD common output pin COMI as well The COMI pin selection can be done by setting the bit 1 flag COMSL1 flag of the LCD output control register 1
420. h open drain control register PAODC Port A Chapter 4 Ports PAO is used as input pin for analog as well Each bit can be set individually as an input by the port A input mode register PAIMD When it is used as analog input pin set the port A input mode register to 1 Then the value of the port A input register is read to be 1 is used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as analog input pin set the port A input mode register to 1 Then the value of the port A input register is read to be 1 PA2 is used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as analog input pin set the port A input mode register to 1 Then the value of the port A input register is read to be 1 PA3 is used as input pin for analog as well Each bit can be set individually as an input by the port A input mode register PAIMD When it is used as analog input pin set the port A input mode register to 1 Then the value of the port A input register is read to be 1 PA4 is used as input pin for analog as well Each bit can be set individually as an input by the port input mode register PAIMD When it is used as analog input pin set the port input mode register to 1 Then the value of the port A in
421. he port 5 output mode register PSOMD and set to the output mode by the P5DIR register These can be used as normal I O pins when the serial interface is not used VREF 15 15 power supply for Reference power supply pins for the A D A D converter converter Normally the values of Vref is used ANO 16 16 Input PAO SBOOA TXDOA Analog input pins Analog input pins for 7 channel 10 bit A D AN1 17 17 PA1 SBIOA RXDOA converter AN2 18 18 PA2 SBTOA When not used for analog input these pins ANS 19 19 can be used as normal input pins 1 20 4 SBI1B RXD1B AN5 1 21 5 SBO1A TXD1B AN6 1 22 PA6 SBT1B IRQO 24 21 Input P54 ACZO External interrupt External interrupt input pins IRQ1 25 22 P55 ACZ1 input pins The valid edge for IRQO to 2 can be selected IRQ2 26 23 P56 by the IRQnICR register IRQ1 is an external interrupt pin that is able to determine AC zero crossings Both edge for IRQ2 is valid for interrupt When these are not used for interrupts these can be used as normal input pins ACZO 24 21 Input P54 IRQO AC zero cross An input pin for an AC zero cross detection ACZ1 25 22 P55 IRQ1 detection input circuit pins AC zero cross detection circuit outputs a high level when the input is at an intermediate level It outputs a low level at all other times ACZ input signal is connected to the P54 P55 input circuit and the IRQO IRQ1 interrupt circuit When the AC zero cross d
422. he serial 1 UART transmission interrupt control register SC1TICR Set level 2 14 Set the SC1TIE flag of the SC1TICR register to 1 to enable the interrupt If any interrupt request flag SC1TIR of the SC1TICR register is already set clear SC1TIR before the interrupt is enabled 15 Set the dummy data to the serial transmission data buffer TXBUF1 Operation Chapter 12 Serial interface 1 Setup Procedure Description 16 Transfer to STOP mode 16 Set the STOP flag of the CPUM register to 1 to CPUM 0x03F00 transfer to the stop mode bp3 STOP 1 17 Start the serial communication 17 Input the transfer clock to the SBT1 pin and transfer Dummy data TXBUF1 0x03F9F data to the SBI1 pin Reception data input SBI1 pin 18 Recover from the standby mode 18 The serial 1 UART transmission interrupt SC1TIRQ is generated at the same time of the 8 bits data reception After the oscillation stabilization wait CPU is recovered from the stop mode to the normal mode Note Procedure 1 2 6 to 9 10 to 12 13 to 14 can be set at the same time Each flag should be set as this setup procedure in order Activation of communication should Y be operated after all control registers refer to Table 12 2 1 except 1 are set Operation XII 41 Chapter 12 Serial interface 1 12 3 3 UART Serial Interface lt s uuu Serial 1 can be used f
423. he absolute maximum ratings are the tolerance for the LSI to be operated properly It does not guarantee the operation 22 Electrical Characteristics 1 5 2 mode fs fx 2 u rtt gri Ta 40 C to 85 C Operating Conditions NORMAL mode fs fosc 2 SLOW Chapter 1 Overview Rating Parameter Symbol Conditions Unit MIN TYP Power supply voltage 4 fosc lt 10 0 MHz V 1 DD1 Double speed mode fs fosc 50 3 fosc lt 8 5 MHz V g DB Double speed mode fs fosc ar 29 3 Mask ROM version V fosc 4 25 MHz 18 36 Power supply voltage DDS Normal mode fs fosc fosc lt 4 25 MHz V 2 DD4 Normal mode fs fosc 2 18 36 fx 32 768 kHz 5 Vops Normal mode fs fx 2 cS 3 6 fosc lt 5 MHz V Bee Double speed mode fs fosc 30 3 6 fosc lt 4 25 MHz V 5 DOT Double speed mode fs fosc e 36 8 Flash EEPROM version V fosc 10 MHz 3 0 I 36 Power supply voltage DDE Normal mode fs fosc 2 D fosc 8 5 MHz V DDS Normal mode fs fosc 2 27 6 fx 32 768 kHz 10 Vppto Normal mode fs fx 2 90 11 to maintain RAM epi At STOP mode ia l 3 6 Operation speed 5 Vpp 3 0 to 3 6 V 12 t 0 100 5 Double speed mode fs fosc Vpp 2 7 to 3 6 V 13 t 11 2 x Double speed mode fs fosc one 1 810 3 6 V 14 t 2 i nstruction execution time c3 Bia ble spesd mod
424. he communication after setting data to TXBUF1 and before the communication complete interrupt SCITIRQ is generated if any data is set to TXBUFI again the transmission buffer empty flag SCIREMP of the SCISTR register is set to 1 This indicates that the next transmission data is going to be loaded Data is loaded to the inside shift register from TXBUFI by generation of SCITIRQ and the next transfer is started as SCITEMP is cleared to 0 Overrun Error and Error Monitor Flag After reception complete if the next data has been already received before reading out of the data of the received data buffer RXBUFI overrun error is generated and the SCIORE flag of the SCISTR register is set to 1 At the same time the error monitor flag SCIERE is set to indicate a reception error The flag is cleared after the data of the RXBUFI is read out and the next communication complete interrupt SC1TIRQ is generated SCIERE is cleared as SCIORE flag is cleared These error flags have no effect on communication operation Reception BUSY Flag When the SCISBIS flag of the SCIMDI register is set to serial data input and the data is set to TXBUF1 or the start condition is recognized the BUSY flag SCIRBSY of the SCISTR register is set to 1 The flag is cleared to 0 after the communication complete interrupt SCITIRQ is generated During continuous communication the SCIRBSY flag is always set If the transmission buffer empty flag SCITEMP
425. he low speed clock fx and the event count TMnIO are selected as the clock source select fx and TMnIO as the clock source Simple Pulse Width Measurement V 43 Chapter 5 8 bit Timers 5 9 2 Setup Example B Setup Example of Simple Width Measurement by 8 bit Timer Timer 0 2 The pulse width of period of the external interrupt IRQO input signal is measured by the timer 0 The clock source of the timer 0 is selected to fs 2 A setup procedure example with description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 2 Set the pulse width measurement operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 1 3 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 4 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 0 bpO TMOBAS 1 5 Set the compare register TMOOC 0x03F52 x FF 6 Set the interrupt level IRQOICR 0x03FE2 bp7 6 IRQOLV1 0 7 Set the interrupt valid edge IRQOICR OxOSFE2 bp5 REDGO 1 8 Enable the interrupt IRQOICR 0x03FE2 bp1 IRQOIE 1 9 Enable the timer operation TMOMD 0x03F54 bp3 TMOEN 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop the timer 0 counting 2 Set the TMOPWM flag of the TMOMD register to O and TMOMOD flag to 1 to enable the timer operation during L period
426. he pins 3 Set COMSL3 to COMSLO flags of the LCD output control LCCTR1 x 3FC2 register 1 LCCTR1 to 1111 to set up the common bp3 0 COMSL3 0 1111 pins 3 to 0 LCCTR1 x 3FC2 Set LC1LS1 to LC1LSO flags of the LCD output control bp5 4 LC1SL 1 0 11 register 1 LCCTR1 to 1 to set up the segment pins to 0 4 Select the LCD clock source 4 Select 1 218 as the LCD clock source by LCDCK3 LCDMD 1 x 3FC0 to LCDCKO flags of the LCD mode control register 1 bp3 0 LCDCK3 0 0111 LCDMD1 5 Select the LCD display duty 5 Set LCDTY1 to LCDTYO flags of the LCD mode control LCDMD1 x 3FCO register 1 LCDMD1 to 00 to setup the display duty bp5 4 LCDTY1 0 00 6 Set the LCD panel display data 6 Set the display data on the address X 2E00 X 2E01 of 2 00 x 5E the segment output latch x 2E01 x 7C Refer to 16 4 LCD Display 7 Start the LCD drive circuit 7 Set the LCDEN flag of the LCD mode control register 1 LCDMD1 x 3FCO LCDMD 1 to 1 to start the LCD driver circuit bp7 LCDEN 1 If internal voltage booster circuit is used voltage of Vi c4 Vice and Vi could be dropped depending on the load of used LCD panel and that may lower the brightness of LCD display In this case set to the internal voltage dividing resistor selection bit of the LCD mode con trol register 2 LCDMD2 to select the low resistor By selecting the low resistor the curr
427. he transmission buffer TXBUF3 IIC3BSY flag of the SC3CTR register is set to 1 When ACK transmission reception with ACK enabled communication or the final bit communication with ACK dis abled communication completes the IIC3BSY flag is cleared to 0 Also when the stop condition generation flag is set to 1 IIC3BSY is set to 1 and cleared to 0 when stop condition is completed If start condition is detected during communication the communication end interrupt SC3IRQ is generated and the IIC3BSY flag is automatically cleared The following items are the same as clock synchronous serial B First Transfer Bit Setup Refer to XIII 13 B Transmission Data Buffer Refer to XIII 13 Reception Data Buffer Refer to XIII 13 Transfer Bit Count and First Transfer Bit Refer to XIII 15 B Continuous Communication Refer to XIII 15 B Forced Reset Refer to XIII 17 In communication set Nch open drain for pin type as the hardware switches if bus is used Y released In reception set the SDA3 pin the 5803 pin direction to output Operation Chapter 13 Serial Interface 3 Master Transmission Timing 1 Eo B 0 6 6 4 0 lt 80158 8 bits transmission lt lt transmission x SDA SCL Interrupt IIC3BSY x A Write data to TXBUF3 Write data to TXBUF3 IIC3STPC flag set Figure 13 3 21 Master Tra
428. hota Bk a h Oa de aceite IV 24 4 4 1 Descriptions iecore eo t DR pa EET HR CREER ER ERREUR IV 24 4 4 2 Registers eR RE EUER i edidi E IV 26 44 3 Block Diagram oe tpe UU REUS UR LAURENT IV 33 didum IV 39 454 D escriptionz uui ee Ri EHI Una aS IV 39 4 5 gt etu bae ine IV 41 4 5 3 Block Diagr m enini eerie te en cime pO IV 45 4 6 Port anna qa tem qt E aep aita red IV 49 4 6 T Description ed ete et e acte o o eredi ete rette IV 49 4 6 2 Registers oe v Pee demens IV 51 4 6 3 Block Diagram NS SS SSD Ut de sh ae ether Lese eter ete gere eere ER IV 58 4 Port ie Rat aa ee ee IV 66 471 Bb nupt IV 66 4 722 Registers oi Ree Re hse IV 67 4 7 3 Block Diagram ico taa ERU iecit e Mie Inr ben IV 71 AB oh ERE BE neo eR IV 72 4 8 T Description oie pe e re e DEPO E OO ERE SEU PES IV 72 ZBIAXTGa I MM EE IV 74 4 8 3 Block Dia prams eoe tbe dite i pie a ed n e p EE IV 78 4 9 Real Output COMMON EU i D IV 82 4 9 1 Registers septena detenido as IV 82 4 9 2 esaet te Pd enter Eee Eddie toe e toten IV 82 Chapter 1 ROMS Dau ERE V 2 54 b Functions tue tie ioa enitn ipt 3 23
429. ing at master at slave Tmax 25T T f f f Tmax 2T Clock 5 pin Output data 8803 Transfer bit counter SC3BSY Write data to Interrupt SC3IRQ Figure 13 3 6 Transmission Timing Falling edge Start condition is enabled at master at slave Tmax 3 5T T f f 2 HM U Clock SBT3 pin Output data 5 Transfer bit counter SC3BSY Write data to TXBUF3 Interrupt SC3IRQ Figure 13 3 7 Transmission Timing Falling edge Start condition is disabled Operation XII 19 Chapter 13 Serial Interface 3 at master at slave Tmax 25TT T f f Tmax 2T Clock SBT3 pin Output data SBO3 pin Transfer bit counter SC3BSY Write data to TXBUF3 Interrupt SC3IRQ Figure 13 3 8 Transmission Timing Rising edge Start condition is enabled at master at slave Tmax 3 5T T f I f 2 e Clock 5 pin Output data SBOS pin Transfer bit counter SC3BSY Write data to 7 Interrupt SC3IRQ Figure 13 3 9 Transmission Timing Rising edge Start condition is disabled XIII 20 Operation Chapter 13 Serial Interface 3 Reception Timing Clock 5 pin Input data 5813 pin Transfer bit counter SC3BSY Interrupt SC3IRQ Figure 13 3 10 Reception Timing Rising edge Start condition is enab
430. ing conditions After all I O pins are set to input mode and the oscillation is set to lt HALT mode the input pins at Vpp level and an 32 768 kHz square wave of V pp and amplitudes is input to the XI pin The supply current during STOP mode Ipp16 Ippi7 are measured under the following conditions After the oscillation is set to lt 5 mode MMOD pin is at level the input pins are at pp level and the OSCI and XI pins are unconnected Electrical Characteristics 1 29 Chapter 1 Overview 1 30 Vpp 1 8V to 3 6V 40 to 85 Pull up resistor ON Rating Parameter Symbol Conditions Unit MIN MAX Input pin 1 MMOD 18 Input high voltage 1 0 8Vpp 19 Input low voltage 1 Vint 0 0 2Vpp 20 Input leakage current 0 V to Vpp t2 Input 2 P54 Schmitt trigger input 21 Input high voltage Vino 0 8Vpp t 22 Input low voltage Vio 0 0 2Vpp 23 Input leakage current ko 0 V to Vpp t2 24 Pull up resistor RR 30 100 300 kQ 25 Output high voltage Vpp 3 0 V 2 0 mA 2 4 26 Output low voltage Vpp 3 0 V Io 22 0 mA 0 4 Input pin 3 P55 Schmitt trigger input 27 Input high voltage Vins 0 8Vpp 28 Input
431. input 1 or more transfer clock interval is required after the start condition output At the clock input 3 5 or more transfer clock interval is required after setting transmission data dummy data The system configuration is required to notify the master of the data load completion At the clock input 0 5 or more transfer clock interval is required after the start condition input When receiving data continuously the system configuration is required to notify the master of the readout completion Without the notification the data before readout may be overwritten B Transfer Bit Setup The transfer bit count can be set from 1 to 8 bits Set the transfer bit count by the SCOLNG 2 to 0 flag of the SCOMDO register at reset 111 The SCOLNG2 to 0 flag holds the former set value until it is set again munication set data to TXBUFO or input a clock to SBTO pin after a start condition is input a Except during communication SBTO pin is masked to prevent errors by noise At slave com is required to input the external clock a To communicate properly more than 2 5 transfer clock interval after the data set to TXBUFO Operation Chapter 11 Serial interface 0 Start Condition Setup The SCOSTE flag of the SCOMDO register sets the start condition whether it is enabled or disabled The start condition is recognized when SCOCEI flag of SCOMDO is set to 0 and a clock line SBTO pin is H data line SBIO pin with 3 lines
432. input mode pull up resistor is disabled and segment output is executed by the segment output control Port 7 IV 65 Chapter 4 Ports IV 66 4 Port9 4 7 1 Description General Port Setup To output data to pin set the control flag of the port 9 direction control register PODIR to 1 and write data to the port 9 output register POOUT To read input data of pin set the control flag of the port 9 direction control register PODIR to 0 and read the value of the port 9 input register POIN Each bit can be set individually to either an input or output by the port 9 direction control register PODIR The control flag of the port 9 direction control register PODIR is set to 1 for ouput mode and 0 for input mode Each bit can be set individually if pull up pull down resistor is added or not by the port 9 pull up pull down resistor control register POPLU Set the control flag of the port 9 pull up pull down resistor control register POPLU to 1 to add pull up resistor Pull up resistor or pull down resistor can be added to port 9 by setting the bp2 flag of the pull up pull down resis tor selection resister SELUD Special Function Pin Setup P90 can be used as low speed oscillation as well When the XISEL flag of the low speed oscillation selection register XSEL is set to 1 P90 can be used as low speed oscillation Port 9 Chapter 4 Ports 4 7 2 Registers
433. interface 0 At master At slave Tmax 25TT T f f f Tmax 2T lt q gt Clock SBTO Output pin 5800 pin Transfer bit counter SCOTBSY Data set to TXBUFO Interrupt SCOTIRQ Figure 11 3 8 Transmission Timing at rising edge start condition is enabled At master At slave Tmax 3 5T T f f f f Tmax 2T 4 5 4 5 Clock SBTO pin Output pin SBOO pin Transfer bit counter SCOTBSY Data set to TXBUFO A Interrupt SCOTIRQ Figure 11 3 9 Transmission Timing at rising edge start condition is disabled XI 24 Operation Chapter 11 Serial interface 0 Reception Timing Clock SBTO pin Input pin SBIO SBOO pin Transfer bit counter SCORBSY Interrupt SCOTIRQ Figure 11 3 10 Reception Timing at rising edge start condition is enabled At master Tmax 3 5T T Clock SBTO pin Input pin SBIO SBOO pin Transfer bit count SCORBSY Data set to TXBUFO Interrupt SCOTIRQ Figure 11 3 11 Reception Timing at rising edge start condition is disabled Operation XI 25 Chapter 11 Serial interface 0 Clock SBTO pin Input pin SBIO SBOO pin Transfer bit counter SCORBSY Interrupt SCOTIRQ Figure 11 3 12 Reception Timing at falling edge start condition is enabled At master Tmax 3 5T Clock SBTO pin Input pin SBIO SBOO pin Transfer bit counter SCORBSY
434. interrupt WDIRQ is generated as a non maskable interrupt NMI How to clear Watchdog Timer The watchdog timer can be cleared by writing to the watchdog timer control register WDCTR The watchdog timer can be cleared regardless of the writing data to the register The bit set BSET that does not change the value is recommended Operation IX 5 Chapter 9 Watchdog Timer IX 6 Watchdog Time out Period The watchdog time out period is decided by the bp2 1 WDTS1 0 of the watchdog timer control register WDCTR and the system clock fs If the watchdog timer is not cleared by the set value it is regarded as an error and the watchdog interrupt WDIRQ of the non maskable interrupt NMI is generated The system clock is decided by the CPU mode control register CPUM Chapter 2 2 5 Clock Switching The watchdog time out period is generally decided by the execution time for main routine of the program The period should be set longer than the execution time of main routine divided by natural number 1 2 Set command of the watchdog timer clear to the main routine as the value makes the same cycle Watchdog Timer and CPU Mode The relation between the watchdog timer and CPU mode features are as follows 1 In NORMAL IDLE SLOW mode the system clock is counted 2 The counting is continued regardless of swithching in NORMAL IDLE SLOW mode In HALT mode the watchdog timer is stopped 3 4 In ST
435. iod Timer 7 interrupt control register Timer 7 compare match T7OC2ICR OxOSFEE Timer 7 compare register 2 match interrupt control register SCORICR OxOSFEF Serial 0 UART reception interrupt control register SCOUART reception completion SCOTICR OxOSFFO Serial 0 UART transmission interrupt control register SCOUART transmission completion SC1RICR OxOSFF1 Serial 1 UART reception interrupt control register SC1UART reception completion SC1ITICR OxOSFF2 Serial 1 UART transmission interrupt control register SC1UART transmission completion SCSICR OxOSFFS3 Serial 3 interrupt control register SC3 transfer completion ADICR OxOSFF4 A D conversion interrupt control register A D conversion completion SC4ICR OxOSFF5 Serial 4 interrupt control register SC4 transmission completion T8ICR OxOSFF6 Timer 8 interrupt control register Timer 8 compare match T8OC2ICR OxOSFF7 Timer 8 compare register 2 match interrupt control register Control Registers 17 Chapter 3 Interrupts If the interrupt level flag xxxLVn is set to level 3 its vector is disabled regardless of inter Y rupt enable flag and interrupt request flag Writing to the interrupt control register should be done after that all maskable interrupts are set to be disable by the MIE flag of the PSW register 18 Control Registers Chapter
436. ion Table 13 3 12 Conditions for Synchronous Serial Interface at reception Item set to Serial data input pin 5813 3 channels Transfer bit count 8 bits Start condition Disabled First transfer bit MSB Input edge Falling Output edge Rising Clock Clock slave Clock source fs 2 SBTS SBO3 pin type N ch open drain plete interrupt SBT3 pin pull up resistor Added 5803 pin pull up resistor Added Serial interface 3 communication com Enabled An example setup procedure with a description of each step is shown below Chapter 13 Serial Interface 3 Setup Procedure Description 1 Select prescaler operation SC3MD3 0x03FA2 bp3 SC3PSCE 1 2 Select the clock source SC3MD3 0x03FA2 bp2 0 SC3PSC2 0 100 3 Control the pin type 0x03F3B bp2 P3ODC2 1 P3PLU 0x03F43 bp2 P3PLU2 1 4 Control of pin direction P3DIR 0x03F33 bp2 P3DIR2 1 bp1 P3DIR1 0 select prescaler operation 100 to select fs 2 as the clock source up resistor to output mode to set P31 to input mode 1 Set the SC3PSCE flag of the SCSMDS register to 1 to 2 Set the SC3PSC2 0 flag of the SC3MD3 register to 3 Set the PSODC flags of the P3ODC register to 1 to select N ch open drain for the SBT3 pin type Set the 2 flags of the register to 1 to add pull 4 Set the P3DIR2 flags of the Port 3 pin contr
437. ion Interrupt Control Register SCOTICR Chapter 3 Interrupts The serial 0 UART transmission interrupt control register SCOTICR controls interrupt level of timer 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 16 bp Serial 0 UART Transmission Interrupt Control Register SCOTICR OxOSFFO 7 6 1 0 Flag SCOTLV1 SCOTLVO SCOTIE SCOTIR At reset 0 0 0 0 Access SCOTLV1 SCOTLVO Description Interrupt level flag interrupt requests This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to SCOTIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt SCOTIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 33 Chapter 3 Interrupts 34 Serial 1 UART Reception Interrupt Control Register SC1RICR The serial 1 UART reception interrupt control register controls interrupt level of timer 0 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 17 Serial 1 UART Reception Interrupt Control Register SC1RICR 0x03FF1 7 6 1 0 SC1RLV1 SC1RLVO SC1RIE
438. ion Reception Enabled 4 Disabled Set transmission data 2 Slave Transmission Enabled Input clock after transmission data is set 5 Disabled Input clock after transmission data is set 6 Reception Enabled Input clock after start condition is input 7 Or Input clock after dummy data is set 6 Disabled Input clock after dummy data is set 6 Transmission Reception Enabled 4 Disabled Input clock after transmission data is set 6 Operation XI 18 Chapter 11 Serial interface 0 XI 14 After the start condition output the transfer clock is output after 1 transfer clock interval After setting transmission data dummy data the transfer clock should be output after 3 5 transfer clock interval at the maximum The system configuratioin is required so that the transmission data dummy data are written after the master receives the information of slave data load completion After the start condition input the transfer clock is output after 2 5 transfer clock interval at the maximum When receiving data continuously the system configuration is required to notify the master of the readout completion Without the notification the data before readout may be overwritten When the start condition is set to enable transmission and reception should not be excuted at the same time After setting the transmission data output the start condition and wait until the master excutes the clock input At the clock
439. ion control register P1PLUD 0x03F41 Port 1 pull up resistor control register P1OUT 0 03 11 Port 1 output control register P7DIR 0x03F37 Port 7 direction control register P7PLUD 0x03F47 Port 7 pull up resistor control register P7OUT 0x03F17 Port 7 output control register SC4ICR OxOSFF5 Serial interface 4 interrupt control register R W Readable Writable XIV 4 Overview Chapter 14 Serial Interface 4 14 1 4 Data Buffer Register Ba a 1 Serial interface 4 has one each of 8 bit serial data buffer register for transmission and for reception Serial Interface 4 Reception Data Buffer SCARXB OxOS3FA9 bp 7 6 5 4 3 2 1 0 Flag I2CRXB7 I2CRXB6 5 4 I2CRXB2 I2CRXB1 I2CRXBO At reset X X X X X X X X Access Description I2CRXB7 I2CRXB6 I2CRXB5 I2CRXB4 I2CRXB3 I2CRXB2 I2CRXB1 I2CRXBO Serial interface 4 reception data buffer B Serial Interface 4 Transmission Data Buffer SCATXB 0x03FAA bp 7 6 5 4 3 2 1 0 Flag 12 7 6 5 4 I2CTXB3 I2CTXB2 I2CTXB1 I2CTXBO At reset 0 0 0 0 0 0 0 0 Access Description I2CTXB7 I2CTXB6 I2CTXB5 12 4 2 2 2 I2
440. ion of the pulse signal input from the external interrupt pin B Simple Pulse Width Measurement Operation by 8 bit Timer Timer 0 2 When the input signal of the external interrupt pin simple pulse width is L the binary counter of the timer counts up Pulse width L period can be measured by reading the count of timer 8 bit timers that have the sim ple pulse width measurement function are the timer 0 and 2 Table 5 9 1 Simple Pulse Width Measurement Able Pins Timer 0 Timer 2 Simple pulse width External interrupt 0 External interrupt 2 measurement enable pin P54 IRQO P56 IRQ2 Count Timing of Simple Pulse Width Measurement Timer 0 2 re e TU UU UU Count Clock M i H External interrupt H IRQ n External interrupt 1 i Synchronous signal TMnEN p Flag Compare FF register Binary 00 01 02 o3 04 05 Counter Figure 5 9 1 Count Timing of Measurement of Simple Pulse Width External interrupt IRQ n is synchronized by the count clock source After the external interrupt IRQ n is set to count operation continues until the falling edge of the next count clock source the value of the binary counter cannot be guaranteed When measuring pulse width do not a When t
441. ion with a stabilizing capacitor connect with the stabilizing capaci tor or use an external voltage dividing resistor a With the internal voltage dividing resistor P34 Vi P35 P36 Vi ci can be used as The internal dividing resistor is formed of connecting between Vi c4 and Vice Vi co Vica Vics and Vss In the selection of the internal dividing resistor type when low resistor is selected about 10 kW resistor is connected between c4 and VI c Vice and Vi and Vss When high resistor is selected about 100 kW resistor is connected to each pin At low resistor At high resistor selection selection MN101C78 MN101C78 pin R about 10 R about 100 VLC2 pin VLC2 pin FraboutiQkQ R about 100 9 VLC3 VLC3 R about 10 E R about 100 Figure 16 3 4 Forming of Internal Dividing Resistor and Resistor Value Operation XVI 17 Chapter 16 LCD Figure 16 3 5 shows example of the LCD power supply connection Stabilizing capacitor for LCD power supply is recommended to be 0 1 mF Cv 0 1 mF should be connected as stabilization condenser Cv for Vpp power supply a 1 2duty 1 2bias Vpp Vucp MN101C78 aes Vici R L Vic2 1 1 R C Vica V u Vss
442. ired before the clock input Operation Chapter 13 Serial Interface 3 For communication with 3 channels set the SC3BIS of the SC3MD1 register to 0 to set the serial input to 1 The 5813 pin can be used as a general port For reception only set the SC3SBOS of the SC3MD1 register to 0 to select port The 5803 pin can be used as a gen eral port For communication with 2 channels set the SBO3 pin to serial data I O The port direction control register P3DIR switches the I O For reception set the SC3SBIS of the SC3MD1 reg ister to 1 to select serial input The 5803 pin can be used as a general port This serial interface contains a force reset function If the communication should be stopped by force set SC3SBOS and SC3SBIS of the SC3MD1 register to 0 Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers refer to Table 13 2 1 except are set Transfer rate of transfer clock set by the SC3MD3 register should not exceed 5 0 MHz Operation 33 Chapter 13 Serial Interface 3 XIII 34 B Transmission Reception Setup Example reception in STANDBY mode The setup example for clock synchronous serial communication with serial 3 is shown Table 13 3 13 shows the conditions at reception in STANDBY mode Table 13 3 13 Conditions for Synchronous Serial Interface at
443. is the serial data output pin Push pull output or Nch open drain output can be selected by setting the Port 1 Nch open drain control register P16 is used as the input pin of the serial 1 reception data UART1 reception data as well P17 is used as the serial 1 clock I O pin as well When the SCISBTS flag of the serial interface 1 mode register 1 SCIMDI is 1 P17 is the serial clock output pin Push pull output or Nch open drain output can be selected by setting the Port 1 Nch open drain control register The I O of the serial 4 can be selected as P10 P11 or P76 P77 by setting the serial selection register SCSEL The SC4SL flag of the serial selection register SCSEL is set to 0 P10 P11 are selected to 1 P76 P77 are selected The I O of the serial 1 can be selected as P15 to P17 or 4 to by setting the serial selection register SCSEL The SCASL flag of the serial selection register SCSEL is set to 0 P15 to P17 are selected to 1 4 to are selected P14 is used as LCD segment output pin as well The SEGII pin selection can be done by setting the bp7 flag LC2SL7 flag of the LCD output control register 2 LCCTR2 to 1 Port and segment switching can be selected by each bit At segment output it is forcefully set to input mode and pull up resistor is disabled P15 is used as LCD segment output pin as well The SEGIO pin selection can be done
444. ister 8 Set the T7ICEDG1 flag of the TM7MD1 register to 1 to select the rising edge as the capture trigger generation edge Also set the T7ICEDGO flag of the TM7MD2 register to 1 to enable the specify edge as the capture trigger generation source 16 bit Timer Capture VI 55 Chapter 6 16 bit Timers VI 56 Setup Procedure Description 9 Select the capture sampling TM7MD3 0x03F8E bp7 TM7CKSMP 0 10 Select the interrupt generation valid edge IRQOICR OxOSFE2 bp5 REDGO 1 11 Set the interrupt level IRQOICR OxOSFE2 bp7 6 IRQOLV1 0 10 12 Enable the interrupt IRQOICR OxOSFE2 bp1 IRQOIE 1 13 Enable the capture trigger generation TM7MD2 0x03F79 bp2 T7ICEN 1 14 Start the timer operation TM7MD1 0x03F78 bp4 TM7EN 1 9 Select the capture sampling as the count clock 10 Set the REDGO flag of the external interrupt 0 control register IRQOICR to 1 to select the rising edge as the interrupt generation valid edge 11 Set the interrupt level by the IRQOLV1 to 0 flag of the IRQOICR register If the interrupt request flag is already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup 12 Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt 13 Set the T7ICEN flag of the TM7MD2 register to 1 to enable the capture trigger generation 14 Set the TM7EN flag of the TM7MD1 register to 1 to oper
445. ister 2 upper 8 bits TM7MD3 Timer 7 mode register 3 TM7MD4 Timer 7 mode register 4 TM7ICR OxOSFED Timer 7 interrupt control register T7OC2ICR Timer 7 compare register 2 match interrupt control register P1OMD OxO3FIC Port 1 output mode register P1DIR OxOSF31 Port 1 direction control register P5OMD OxO3F2C Port 5 output mode register P5DIR 0x03F35 Port 5 direction control register TM7DPHR1 OxOSF7E Dead time preset register 1 TM7DPR2 0x03F7F Dead time preset register 2 Control Registers VI 7 Chapter 6 16 bit Timers Table 6 2 2 shows the registers that control timer 8 Table 6 2 2 16 bit Timer Control Registers 2 2 Register Timer 8 TM8BCL Address 0x03F80 Function Timer 8 binary counter lower 8 bits TM8BCH OxOSF81 Timer 8 binary counter upper 8 bits TM80C1L OxOSF82 Timer 8 compare register 1 lower 8 bits TM8OC1H 0x03F83 Timer 8 compare register 1 upper 8 bits TM8PR1L OxOSF84 Timer 8 preset register 1 lower 8 bits TM8PR1H 0 03 85 Timer 8 preset register 1 upper 8 bits TM8ICL 0x03F86 Timer 8 capture register 1 lower 8 bits TM8ICH OxOSF87 Timer 8 capture register 1 upper 8 bits TM8MD1 0x03F88 Timer 8 mode register 1 TM8MD2 0x03F89 Timer 8 mode register 2 TM80C2L
446. ister is loaded to the timer 7 compare register at the timing that the IGBT is dis abled Timer 7 Preset Register 1 TM7PR1 Table 6 2 7 Timer 7 Preset Register 1 Lower 8 bits TM7PR1L 0x03F74 bp 7 6 5 4 3 2 1 0 Flag TM7PR1L TM7PR1L TM7PR1L TM7PR1L TM7PR1L TM7PR1L TM7PR1L TM7PR1L 7 6 5 4 3 2 1 0 At reset X X X X X X X X Access R W Table 6 2 8 Timer 7 Preset Register 1 Upper 8 bits TM7PR1H 0x03F75 7 6 5 4 3 2 1 0 TM7PR1 H7 TM7PR1 H6 TM7PR1 H5 TM7PR1 H4 TM7PR1 H3 TM7PR1 H2 TM7PR1H 1 TM7PR1 HO X X X X X X X X Timer 7 Preset Register 2 TM7PR2 Table 6 2 9 Timer 7 Preset Register 2 Lower 8 bits TM7PR2L 0x03F7C 7 6 5 4 3 2 1 0 TM7PR2L 7 TM7PR2L 6 TM7PR2L 5 TM7PR2L 4 TM7PR2L 3 TM7PR2L 2 TM7PR2L 1 TM7PR2L 0 X X X X X X X X 7 6 5 4 3 2 1 0 TM7PR2 H7 TM7PR2 H6 TM7PR2 H5 TM7PR2 H4 TM7PR2 H3 TM7PR2 H2 TM7PR2H 1 TM7PR2 HO X X X X X X X X VI 10 Control Registers Chapter 6 16 bit Timers Binary counter is a 16 bit up counter If any data is written to a preset register when the counting is stopped the binary counter is cleared to Ox0000 At IGBT setti
447. k pin SBT1 pin data I O pin SBOI pin be selected as a communication mode SBII pin can be used only for serial data input SBO1 pin can be selected as serial data input or output Whether the serial data is input from SBII pin or 5 pin it can be selected by the flag of the SCIMDI register When data input from 5 pin is selected to set the 2 channels type transmission reception can be switched by the SBOI pin direction control For SBOIA pin it can be done by the PIDIR5 flag of the PIDIR register for SBOIB by the PADIRS flag of the PADIR register At this time pin can be used as a general port too The transfer speed should be up to 5 0 MHz If the transfer clock is over 5 0 the trans Y mission data may not be sent correctly At reception if SC1IOM of the SC1MD1 register is set to 1 and serial data input from SBO1 is selected SBI1 pin can be used as a general port Reception Buffer Empty Flag After reception is completed SCITIRQ is generated data is automatically stored to RXBUFI from the internal shift register If data is stored to the shift register RXBUF1 when the SCISBIS of the SCIMDI register is set to serial input the reception buffer empty flag SCIREMP of the SCISTR register is set to 1 This indicates that the reception data is going to be read out SCIREMP is cleared to 0 by reading out the data of RXBUFI B Transmission Buffer Empty Flag During t
448. l H2PC 0011 1001 1aaH abs 18b 15 0 5 JSRV 4 SP 3 9SP PC 3 bp7 0 smem8 SP 3 5 15 8 8 1 3 8 2 5 7 0 8 2 6 6 2 PC 3 bp17 16 mem8 SP 2 bp1 0 mem8 x 004080 tbl4 lt lt 2 gt PC bp7 0 mem8 x 004080 tbl4 lt lt 2 1 PC bp15 8 mem8 x 004080 tbl4 lt lt 2 2 bp7 PC H mem8 x 004080 tbl4 lt lt 2 2 bp1 0 gt PC bp17 16 1111 1110 lt 4 gt 25 0000 0000 Instruction Set 2 3 4 b d7 sign extension d11 sign extension d12 sign extension d16 sign extension aa abs18 17 16 Chapter 17 Appendix MN101C SERIES INSTRUCTION SET Group Mnemonic Operation Flag Re Exten Machine Code Notes zF Size peat so 1 2 3 4 5 6 7 8 9 10 11 mem8 SP PC bp7 0 Jo 0000 0001 mem8 SP 1 PC bp15 8 8 2 6 7 mem8 SP 2 bp1 0 PC bp17 16 SP 3 SP mem8 SP PSW 0000 0011 mem8 SP 1 PC bp7 0 memB8 SP 2 PC bp15 8 mem8 SP 3 bp7 PC H mem8 SP 3 bp1 0 PC bp17 16 8 5 4 8 5 5 gt 5 6 5 Contorl instructions REP imm3 imm3 1 RPC 0010 0001 lrep 1 no repeat whn imm3 0 rep imm3 1 as macro instructions Other than the instruction of MN101C Series the assembler
449. l 1 0 1 High NMI level 0 Mask level 2 1 0 Low NMI level 0 to 1 Mask level 3 1 1 Lowest NMI level 0 to 2 B Maskable Interrupt Enable MIE Maskable interrupt enable flag MIE enables disables acceptance of maskable interrupts by the CPU s internal interrupt acceptance circuit A 1 enables maskable interrupts a 0 disables all maskable interrupts regardless of the interrupt mask level IM1 IMO setting in PSW This flag is not changed by interrupts Overview 1 11 Chapter 2 CPU Basics 12 2 1 8 Address Space The address space of this LSI is 256 KB max The instruction and data areas are not separated The instruction area can be used as linear address space The data area needs bank specification in every 64 KB The initial value is first 64 KB space The data described in this section includes RAM data and ROM table data The data area consists of an area of 256 bytes that supports efficient access with RAM short addressing and an area of 256 bytes that supports efficient access with I O short addressing The memory control register controls memory to be expanded Overview i 4 n 256B pue RAM short addressing area 0x00100 16KB ial regi eee 64KB nterrupt 1258 vector table 48KB 64B 256KB Instruction code Table data Y Y 192KB Instruction code Ox3FFFF Figure 2 1 7 Address Space RAM space Spscial register a
450. l Programming Mode sss eee ene XVII 5 17 3 T Overview iso eee vim peo engem iie XVII 5 17 3 2 Circuit Requirements for the Target sss XVII 6 17 3 3 Built in Hardware for Onboard Programming eee 7 17 3 4 MN101CF78A Clock on the Target Board eee 8 17 4 Special Function Registers 461 220222000 XVII 9 17 5 Instr ction Set five eet uet ERE e lies XVII 28 17 6 Instruction Map e ert Diet Exe ee Ee een XVII 34 Contents 10 gt Chapter 1 Overview Chapter 1 Overview 1 1 Overview 1 1 1 Overview The MNIOIC series of 8 bit single chip microcomputers incorporate multiple types of peripheral functions This chip series is well suited for camera VCR MD TV CD LD printer telephone home automation pager air con ditioner PPC remote control fax machine music instrument and other applications This LSI brings to embedded microcomputer applications flexible optimized hardware configurations and a sim ple efficient instruction set The MN101C78A has an internal 32 KB of ROM and 1 5 KB of RAM Peripheral functions include 4 external interrupts 18 internal interrupts including NMI 9 timer counters 4 sets of serial interfaces A D converter watchdog timer buzzer output and remote control output The configuration of this microcomputer is well suited for ap
451. l up pull down resistor selection 0 Not added 1 Added O Q O Port A Input Mode Register PAIMD 0x03F4E Flag PAIMD6 PAIMD5 PAIMD4 PAIMD3 PAIMD2 PAIMD1 PAIMDO At reset 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W 7 3 6 PAIMD6 gt CAMS Analog input selection 4 PAIMD4 port PAMOS 1 Analog input 2 PAIMD2 1 PAIMD1 0 PAIMDO IV 76 Port A Port A Nch Open drain Control Register PAODC 0x03F2D PAODC6 PAODC5 PAODC2 Chapter 4 Ports PAODCO 0 0 0 0 bp Flag Description PAODC6 PAODC5 Nch open drain output selection 0 Push pull output PAODC2 1 Nch open drain output O O Q O PAODC0 Pull up pull down Resistor Selection Register SELUD 0x03F4B Flag PADWN P3DWN P9DWN P7DWN P1DWN At reset 1 1 1 0 0 Access R W R W R W R W R W Port A pull up pull down selection 0 Pull up 1 Pull down Port 3 pull up pull down selection 0 Pull up 1 Pull down Port 9 pull up pull down selection 0 Pull up 1 Pull down Port 7 pull up pull down selection 0 Pull up 1 Pull down Port 1 pull up pull down selection 0 Pull up 1 Pull down Port A IV 77 Chapter 4 Ports 4 8 3 Block Diagram Reset pRa PAODCO R Nch open drain control K Reset P
452. lag to 0 Tab 1 2 3 4 5 6 14 15 16 A D conversion clock m A D conversion complete ANST flag A D conversion start UN A D conversion time Ts T Samping Hold bit 9 comparison bit 8 comparison bit 0 comparison gt Determine Determine Determine Determine bit 9 bit 8 bit 1 bit 0 A D conversion complete A D interrupt ADIRQ 4 5 51 Figure 15 3 1 Operation of A D Conversion To read out the value of the A D conversion A D conversion should be done several times to prevent noise error by confirming the match of level by program or by using the average value From A D conversion start to the generation of A D conversion complete interrupt is the A D conversion period Re conversion is not executed if an external interrupt is generated between the instant when ANST flag is cleared and the instant when A D conversion com plete interrupt is generated However when ANST flag is set to 1 software start up re conversion is executed Operation XV 9 Chapter 15 A D Converter 15 3 1 Setup B Input Pins of A D Converter Setup Input pins for A D converter is selected by the ANCH2 0 flag of the ANCTRI register A D Converter Clock Setup The A D converter clock is set by the ANCK1 to ANCKO flag of the ANCTRO register Set the A D converter clock TAp more than 800 ns Table 15 3 1 shows the machine clock fosc fx fs and the A D converter cl
453. lec tion 1 8 1 16 OxO3F9B SC1MD2 SC1FM1 SC1FMO SC1PM1 SC1PMO SC1NPE SC1BRK SC1BRK XII 9 F E 0 0 0 0 0 0 0 Frame mode specifi Added bit specifica Parity Break Break cation tion enable status status recep trans tion mission monitor control XVII 20 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3F9C SC1MD3 SC1FDC SC1FDC SC1PSC SC1PSC SC1PSC SC1PSC XII 10 1 0 E 2 1 0 0 0 0 0 0 0 Output selection after Prescale Selection clock SBO final data trans r count mit control OxO3F9D SC1STR SC1TBS SC1RBS 5 SC1RE SC1FEF SC1PEK SC1OR SC1ERE XII 11 Y Y P MP E 0 0 0 0 0 0 0 0 Serial bus status Transmis Receptio Frame Parity Overrun Error sion n buffer error error error monitor buffer empty detection detection detection flag empty OxO3F9E RXBUF1 RXBUF1 RXBUF1 RXBUF1 RXBUF1 RXBUF1 RXBUF1 RXBUF1 RXBUF1 6 7 6 5 4 3 2 1 0 x x x x x x x x Serial interface 1 reception data buffer OxO3F9F TXBUF1 TXBUF1 TXBUF1 TXBUF1 TXBUF1 TXBUF1 TXBUF1 TXBUF1 TXBUF1 XII 6 7 6 5 4 3 2 1 0 x x x x x x x x Serial interface 1 transmission data buffer OxO3FAO0 SC3MDO SC3BSY SC3CE1 SC3DIR SC3STE SC3LNG SC3LNG SC3LNG
454. lect the capture a When the T7ICT1 0 flag of the timer mode register 2 is set to x 11 a capture trigger of the trigger by the timer mode register 2 TMnMD2 and the timer mode register 4 TMnMD4 When the timer 0 and 1 interrupts signals are selected as the capture trigger the edges of the capture trigger are disabled When setting the capture clock as the count clock to exe cute the event count operation the timer 0 1 interrupt signal may not be recognized To vent this select the synchronous TMnIO input as the clock source VI 52 16 bit Timer Capture Chapter 6 16 bit Timers Binary Counter Clearance at the Timing of Capture Timer 7 Timer 8 When selecting the external interrupt input signal or the timer 0 and 1 interrupts as the capture trigger the binary counter can be cleared during capture operation by setting the flag of the timer mode register 4 TMnMD4 to 1 The binary counter can be cleared during timer count operation only Count Clock 1 TM7EN MENU NES Flag Register 1 Binary Counter Capture trigger Capture 0002 0006 Register Figure 6 8 3 Binary Counter Clearance at the Timing of Capture Timer 7 Timer 8 16 bit Timer Capture VI 53 Chapter 6 16 bit Timers VI 54 B Capture Operation Triggered by Writing Software Timer 7 Timer 8 Count clock fs M DIM Ets TMnEN flag Compare
455. lectric Industrial Co Ltd Nagaokakyo Kyoto 617 8520 Japan Tel 075 951 8151 http panasonic co jp semicon e index html Printed in Japan
456. led at master 3 5 T TP Clock 5 pin Input data 5813 pin Transfer bit counter SC3BSY Write data to TXBUF3 Interrupt SC3IRQ Figure 13 3 11 Reception Timing Rising edge Start condition is disabled Operation XII 21 Chapter 13 Serial Interface 3 Clock SBT3 pin Input data SBI3 Transfer bit counter SC3BSY Interrupt SC3IRQ Figure 13 3 12 Reception Timing Falling edge Start condition is enabled at master 357 T 5 pin Input data SBI3 pin Transfer bit counter SC3BSY Write data to TXBUF3 4 Interrupt SC3IRQ Figure 13 3 13 Reception Timing Falling edge Start condition is disabled 22 Operation Chapter 13 Serial Interface 3 Transmission Reception As data is received at the opposite edge of the transmission clock set the polarity of reception data input edge to opposite polarity of the transmission data output edge When transmission and reception are executed at the same time set the start condition to disable to prevent abnormal operation SBTS Data is input at the rising edge of the clock 5813 pin Data is output at the falling edge of the clock Figure 13 3 14 Transmission Reception Timing Reception Rising edge Transmission Falling edge pin Data is input at the rising edge of the clock SBI3 pin
457. ll up pull down resistor control register SELUD 0x03F4B Pull up pull down resistor selection register PAIMD Ox03F4E Port A input mode register PAODC OxOSF2D Port A Nch open drain control register R W Readable Writable Port A output register PAOUT 0x03F1A bp Flag Description PAOUT6 5 PAOUT4 PAOUT2 PAOUT1 PAOUTO Output data 0 Output L VSS level 1 Output H VDD level O S O Q O Port A Chapter 4 Ports Port A Input Register PAIN 0x03F2A bp Flag Description gt 6 6 5 PAIN5 Input data 4 PAINA 0 Pin is L VSS level 3 PAINS bin is H VDD level 2 PAIN2 1 PAIN1 0 PAINO Port A Direction Control Register PADIR 0x03F3A Flag PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIRO At reset 0 0 0 0 0 0 0 Access R W R W R W R W R W R W R W bp Flag Description O OQ Q O PADIR6 PADIR5 PADIR4 PADIR3 PADIR2 PADIR1 PADIRO mode selection 0 Input mode 1 Output mode Port A IV 75 Chapter 4 Ports Port A Pull up pull down Resistor Control Register PAPLUD 0x03F4A PAPLUD6 PAPLUDS5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO 1 1 1 0 0 0 0 PAPLUD6 PAPLUD5 PAPLUD4 PAPLUD3 PAPLUD2 PAPLUD1 PAPLUDO Pul
458. ll up resistor control register PSPLU to 1 to add pull up resistor Each bit can be selected individually as output mode by the port 5 output mode regiser PSOMD The port 5 out put mode register PSOMD is set to 1 to output the special function data and 0 for the general port B Special Function Pin Setup P50 is uses as output pin of the timer 0 The output mode can be selected by each bit by bpO of the port 5 output mode register 5 The port 5 output mode register PSOMD is set to 1 to output the special function data and 0 for general port P51 is uses as output pin of the timer 7 The output mode can be selected by each bit by of the port 5 output mode register PSOMD The port 5 output mode register PSOMD is set to 1 to output the special function data and 0 for general port P52 is uses as output pin of the timer 2 The output mode can be selected by each bit by bp2 of the port 5 output mode register PSOMD The port 5 output mode register is set to 1 to output the special function data and 0 for general port P53 is uses as output pin of the timer 8 The output mode can be selected by each bit by bp3 of the port 5 output mode register PSOMD The port 5 output mode register PSOMD is set to 1 to output the special function data and 0 for general port P54 is used as the external interrupt pin as well P55 is used as the extern
459. ls internal voltage dividing resistor ON OFF and internal voltage dividing resistor type The address is assigned to X 3FC1 and read write can be done by the instruction to I O The value of the LCDMD2 register is initialized at reset Table 16 2 3 shows the LCD mode control register 1 B Mode Control Register 2 LCDMD2 X 03CF1 R W Table 16 2 3 LCD Mode Control Register 2 Flag Reserved Reserved Reset 0 0 Access 7 6 Description 5 4 Reserved Set always to 0 Internal voltage dividing resistor selection 0 Low resistance to Vi co Vi ca to Vi Vi o3 to Vss about 10 kW 1 High resistance 10 Vica Vice to Vica Vica to Vas about 100 kW Internal voltage dividing circuit connect selection 0 Unconnected 1 Connected With the internal voltage dividing resistor P34 Vi P35 P36 Vi can be used as ports However depending on the panel if LCD display does not have enough brightness due to the lack of connection with a stabilizing capacitor connect with a stabilizing capacitor or use an external voltage dividing resistor Control Registers Chapter 16 LCD 16 2 4 Output Control Register 1 LCCTHR1 The LCD output control register 1 LCCTR1 switches port I O P30 to P33 and common output COMO to port I O P74 to P77 and segment output SEGO to SEG3 The address is assigned to
460. ly set to input mode and pull up resistor is disabled P77 can be used as the LCD segment output pin as well The SEGO pin selection can be done by setting the bp4 flag LCISLO of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forcefully set to input mode and pull up resistor is disabled P76 can be used as the transmission reception data I O pin as well When SELI2C flag of the serial inter face 4 addressing register 1 is set to 1 P76 is the serial data I O pin Push pull output Nch open drain output can be selected by setting the port 7 Nch open drain control register P7ODC P77 can be used as the serial 4 clock I O pin as well When SELI2C flag of the serial interface 4 addressing reg ister 1 SC4AD1 is set to 1 P77 is the serial clock I O pin Push pull output or Nch open drain output can be selected by setting the port 7 Nch open drain control register P7ODC Serial 0 I O pin can be selected as PAO to PA2 or P75 to P77 by setting the serial selection register SCSEL When the SCOSL flag of the serial selection register SCSEL is set to 0 PAO to PA2 are selected to 1 P75 to P77 are selected For serial 4 I O pin when the serial selection register SCSEL is 0 for P10 P11 1 for P76 P77 Port 7 Chapter 4 Ports 4 6 2 Registers Table 4 6 1 shows the registers that control the port 7 Table 4 6
461. mote control carrier pulse is stopped Operations VIII 9 Chapter 8 Remote Control Carrier Functions VIII 10 Operations Chapter 9 Watchdog Timer Chapter 9 Watchdog Timer IX 2 9 1 Overview This LSI has a watchdog timer that is used to detect software processing errors It is controlled by the watchdog timer control register WDCTR When an overflow of watchdog timer is generated a watchdog interrupt WDIRQ is generated If the watchdog interrupt is generated twice in a row it is regarded to be an indication that the software cannot execute in the intended sequence thus a system reset is initiated by the hardware 9 1 1 Functions pn 7 i Table 9 1 1 shows watchdog timer functions Table 9 1 1 Watchdog Timer Functions Watchdog time out period setup selection 216 of system clock 218 of system clock 220 of system clock Watchdog timer enable Stop Operation Overview Chapter 9 Watchdog Timer 9 1 2 Block Diagram Watchdog Timer Block Diagram NRST STOP writeWDCTR HALT SW is 1 2 to 1 2 1 216 to 1 2 internal reset release 15 2154 internal reset TO 16 210
462. mponent overflow time of the binary counter Figure 6 6 1 Count Timing of Standard PWM Output at Normal 16 bit Standard PWM Output Only duty can be changed consecutively VI 39 Chapter 6 16 bit Timers VI 40 B Stop Condition of PWM Waveform Polarity Selection Timer 8 Select the 8 8 output waveform for the time when the PWM operation is stopped by the TM8PWMF of TM8MD3 register Select the polarity of PWM output by the TM8PWMO Before starting the second PWM or later clear the BC and PWM waveform by writing to the Y preset register as the PWM output waveform of the first cycle cannot be guaranteed PWM source waveform A shows until the binary counter reaches the compare register value from 0x0000 B shows after the compare match then the binary counter counts up till the overflow C shows again if the binary counter overflow Count Timing of Standard PWM Output when compare register 1 is 0x0000 Timer 7 Timer 8 Here is the count timing at setting 0x0000 to the compare register 1 Count clock TMnEN flag Compare register 1 mn is ud 7 DOO rer 2 counter H TMnIO output PWM Figure 6 6 2 Count Timing of Standard PWM Output when compare register 1 is 0x0000 0000 PWM output shows H when TMnEN flag is stopped at 0 16 bit Standard PWM Output Only duty can be changed
463. n Chapter 5 8 bit Timers When timer 0 and timer 1 are used in cascade connection timer 1 is used as an interrupt request flag Timer pulse output of timer 0 is L fixed output An interrupt request of timer 0 is not generated but the timer 0 interrupt should be disabled When timer 2 and timer 3 are used in cascade connection timer 3 is used as an interrupt request flag Timer pulse output of timer 2 is L fixed output An interrupt request of timer 2 is not generated but the timer 2 interrupt should be disabled At cascade connection when the clear of the binary counter is needed by rewriting the com pare register set the TMnEM flag of both the upper 8 bit timer and the lower 8 bit timer to 0 to stop counting out if it changes from lower 8 bit of upper 8 bit as it is treated as 8 bits of data in LSI internally a To read out the binary counter during the timer operation the correct value may not be read Stop the timer and read out to get the correct value Cascade Connection V 47 Chapter 5 8 bit Timers 5 10 2 Setup Example Cascade Connection Timer Setup Example Timer 0 Timer 1 Setting example of timer function that an interrupt is constantly generated by cascade connection of the timer 0 and the timer 1 as a 16 bit timer is shown An interrupt is generated 2500 times every 1 ms by selecting source clock fs 2 fs 5 MHz at operation An example setup procedure with a
464. n Chapter 6 16 bit Timers units even if it is a 16 bit MOVW instruction As a result it will read the data incorrectly if a carry from the lower 8 bits to the upper 8 bits occurs during counting operation To read the correct value of the 16 bit counting use the writing program function to the input capture register TMnIC By writing to the TMnIC the counting data of TMnBC can be stored to TMnIC to read out the correct counting value during timer operation Chapter 6 8 1 Operation a When the CPU reads the 16 bit binary counter TMnBC the read data is handled in 8 bits To count properly do not switch the count clock on the timer operation To switch the count Y clock stop the timer operation Table 6 3 2shows the clock source that can be selected Table 6 3 2 Clock Source at Timer Operation Timer 7 Timer 8 fs fosc 2 5 MHz Clock source 1 count time fosc 100 ns fosc 2 200 ns fosc 4 400 ns fosc 16 1 6 us fs 200 ns fs 2 400 ns fs 4 800 ns fs 16 1 6 us fosc 10 MHz Operation VI 25 Chapter 6 16 bit Timers VI 26 Count Timing of Timer Operation Timer 7 Timer 8 The binary counter counts up with the selected clock source as the count clock The basic operation of whole 16 bit timer functions is as below Count clock TM7EN flag Preset register Compare register A Binary 0000 0001X0002 s
465. n 0 Count clock 1 fs TM8CKEDG TMB8IO count edge selection 0 Falling edge 1 Both edges TM8SEL Timer 8 output selection 0 8 output 1 IGBT output TM8PWMF PWM output selection at timer 8 stopped 0 L 1 H TM8PWMO Timer 8 PWM output polarity selection 0 Normal turn 1 Reverse turn TM8CAS Control Registers Cascade selection 0 7 Timer 8 independence 1 Timer 7 Timer 8 cascade Timer 8 Mode Register 4 TM8MD4 Table 6 2 36 Timer 8 Mode Register 4 TM8MD4 0x03F6F 1 Chapter 6 16 bit Timers 0 T8ICT2 T8CAPCL R 0 Description 7 2 1 T8ICT2 Capture trigger selection 0 0 interrupt 1 Timer 1 interrupt 0 T8CAPCLR BC clearance at capture 0 Cleart 1 Unclear T7CAPCLR flag is effective when timer is operating The binary counter is uncleared when Y capturing at timer stop Control Registers VI 23 Chapter 6 16 bit Timers VI 24 6 3 Operation 6 3 1 Operation The timer operation can constantly generate interrupts 16 bit Timer Operation Timer 7 Timer 8 The generation cycle of an timer interrupt is set by the clock source selection and the set value of the compare reg ister 1 in advance When the binary counter TMnBC reaches the set value of the compare register l an interrupt is generated at the next count clock There are 2 source
466. n 0000 0001 0002 0003 counter A B E Interrupt request flag Figure 6 3 1 Count Timing of Timer Operation Timer 7 Timer 8 A When a data is written to the preset register while the TMnEN flag is stopped 0 the same value is loaded during the writing cycle and the binary counter is cleared to 0x0000 B When TMnEN flag is 1 the binary counter starts counting The counting starts at the rising edge of the count clock C Even if the preset register is rewritten when the TMnEN flag is 1 the binary counter is not changed D When the binary counter reaches value of compare register 1 the set value of the preset register is loaded to the compare register at the next count clock And the interrupt request flag is set at the next count clock and the binary counter is cleared to 0 0000 to restart counting up E When the TMnEN flag is 0 the binary counter is stopped When the binary counter reaches the value of the compare register the interrupt request flag is set to the next count clock and the binary counter is cleared So set the compare register as the set value of the compare register the counts till the interrupt generation 1 When the timer n compare register 2 match interrupt is generated and TMnOC1 compare match is selected as a binary counter clear source the set value of the compare register 2 should be smaller than the set value of the compare register On th
467. n TM2MD 0x03F5C bp4 TM2PWM 0 bp5 TM2MOD 0 3 Select the count clock source TM2MD 0x0F5C bp2 0 2 2 0 X01 4 Select and enable the prescaler output CK2MD 0x0F5E bp2 1 TM2PSC1 0 0 TM2BAS 1 5 Set the baud rate 2 0x0F5A 6 Start the timer operation TM2MD 0x0F5C bp3 TM2EN 1 1 Set the TM2EN flag of the timer 2 mode register TM2MD to 0 to stop the timer 2 counting 2 Set the TM2PWM flag and the TM2MOD flag of the TM2MD register to 0 to select the normal timer operation 3 Select the prescaler output to the clock source by the TM2CK to 0 flag of the TM2MD register 4 Select fs 2 to the prescaler output by the TM2PSC1 to 0 flag and the TM2BAS flag of the timer 2 prescaler selection register b Set the timer 2 compare register TM2OC such a value that the baud rate comes to 300 bps At that time the timer 2 binary counter 2 is initialized to 0 00 6 Set the TM2EN flag of the TM2MD register to 1 to operate the timer 2 TM2BC counts up from 0 00 Timer 2 output is the clock of the serial interface 0 at transmission and recep tion For the setup value of the compare register and the setup of the serial interface operation refer to Chapter 11 Serial interface 0 Serial Transfer Clock Output Chapter 5 8 bit Timers 5 9 Simple Pulse Width Measurement 5 9 1 Operation Timer measures the L durat
468. n as well When the SCOSBTS flag of the serial interface 0 mode register 1 SCOMD1 is set to 1 P77 is the serial clock output pin Push pull output or Nch open drain output can be selected by setting the port 7 Nch open drain control register P7ODC P70 can be used as the key interrupt input pin as well P71 can be used as the key interrupt input pin as well P72 can be used as the key interrupt input pin as well Port 7 IV 49 Chapter 4 Ports IV 50 P73 can be used as the key interrupt input pin as well P74 can be used as the key interrupt input pin as well P75 can be used as the key interrupt input pin as well P76 can be used as the key interrupt input pin as well P77 can be used as the key interrupt input pin as well P70 can be used as the LCD segment output pin as well The SEG7 pin selection can be done by setting the bp3 flag LC2SL3 of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forcefully set to input mode and pull up resistor is disabled P71 can be used as the LCD segment output pin as well The SEG6 pin selection can be done by setting the bp2 flag LC2SL2 of the LCD output control register 2 LCCTR2 to 1 Port segment switching can be selected by 2 bits At segment output it is forcefully set to input mode and pull up resistor is disabled P72 can be used as the LCD segment output pin as well The SEGS
469. n Setup PAO is used as ouput pin of the serial O transmission data and UARTO transmission data as well When the SCOSBOS flag of the serial interface 0 mode register 1 SCOMD1 is set to 1 PAO is the serial data output pin Push pull output or Nch open drain output can be selected by setting the port A Nch open drain control register PAODC can be used as input pin of the serial 0 reception data and UARTO reception data as well PA2 can be used as the serial 0 clock I O pin as well When the SCOSBTS flag of the serial interface 0 mode reg ister 1 SCOMDI is set to 1 PA2 is the serial clock output pin Push pull output or Nch open drain output can be selected by setting the port A Nch open drain control register PAODC PA4 can be used as input pin of the serial 1 reception data and UART 1 reception data as well PAS is used as ouput pin of the serial 1 transmission data and transmission data as well When the SCISBOS flag of the serial interface 1 mode register 1 SC1MD1 is set to 1 PAS is the serial data output pin Push pull output or Nch open drain output can be selected by setting the port A Nch open drain control register PAODC 6 can be used as the serial 1 clock I O pin as well When the SC1SBOS flag of the serial interfacel mode reg ister 1 SCIMDI is set to 1 PA2 is the serial clock output pin Push pull output or Nch open drain output can be selected by setting the port A Nc
470. nchronous communication Table 12 3 6 Other Control Flag Register Flag Detail SC1MD2 SC1BRKE Break status transmission control SC1BRKF Break status reception monitor SC1NPE Parity enable SC1PM1 to 0 Added bit specification SC1FM1 to 0 Frame mode specification SC1STR SC1PEK Parity error detection SC1FEF Frame error detection Operation XII 21 Chapter 12 Serial interface 1 Transmission Timing At master At slave Tmax 25T T T Tmax 2T Clock SBT1 pin Output pin 5801 pin Transfer bit counter SC1 TBSY Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 6 Transmission Timing at falling edge start condition is enabled At master At slave Tmax 3 5T T 2 Clock 5811 pin Output pin 5801 pin Transfer bit counter SC1 TBSY Data set to 1 1 Interrupt SC1TIRQ Figure 12 3 7 Transmission Timing at falling edge start condition is disabled XII 22 Operation Chapter 12 Serial interface 1 At master At slave Tmax 25TT 2 X Clock SBT1 pin Output pin SBO1 pin Transfer bit counter SC1TBSY Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 8 Transmission Timing at rising edge start condition is enabled At master At slave Tmax 3 5T T f f f 2 Clock SBT1 pin Output pin 5801 pin Trans
471. ncorrect value could be read out To prevent this select a synchronous fs as the count clock source q When fx is used to the clock source the binary counter should be cleared before starting the timer operation Also when 0x00 is set to the compare register the synchronous fx should be used If the smaller value than the binary counter is set to the compare register at counting opera tion the binary counter continues counting till overflow q When fx and time base selection clock at time base clock source is selected as fx are selected as clock sources the binary counter may not be cleared To prevent this select a synchronous fx and synchronous time base selection clock q When a timer interrupt request flag is generated up to 3 system clock is required for the next flag generation Even if the binary counter reaches the value in the compare register a timer interrupt request flag is not generated VII 12 8 bit Free running Timer Chapter 7 Time Base Timer Free running Timer 7 3 2 Setup Example A EE Timer Operation Setup Timer 6 Timer 6 generates interrupts constantly for timer function Interrupts are generated in every 250 dividing 25 us by selecting fs fs 10 MHz at operation as clock source An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Enable the binary counter TM6MD 0xOSF62 bp7 TM6CLRS
472. ncy oscillation fs System clock Chapter 2 2 5 Clock Switching When timer 3 is used as a baud rate timer for serial function it cannot be uses as a general timer Pulse width measurement function is not available at cascade connection 16 bit counter At cascade connection 16 bit counter when the clock source is fx and TMnIO input is selected set the synchronous fx and synchronous TMnIO input This function is not available when clock source is fx and TMnIO input is selected at cascade connection Overview Chapter 5 8 bit Timers V 4 5 1 2 Prescaler Block Diagram Block Diagram ETT NM eee an 7bit prescaler S 3bit prescaler fosc ck PSCO fs PSC1 2 M 4 L TM1BAS TM1PSC1 TMSPSCO TM3PSC1 Overview 4 1 1 ____ _____ _____ ____ c fs 8 fs 4 fs 2 fosc 128 fosc 64 fosc 32 fosc 16 fosc 8 fosc 4 fosc 2 Figure 5 1 1 Prescaler Block Diagram TMnEN Chapter 5 8 bit Timers Timer 0 and 1 Block Diagram OHI0A 1 OWMd Andino OIOW L N _ SVEOWL OOSdOWL LOSdOWL GOWOWL asma s euo X Hippy N indui LSH zx Buruy sind lt peey andino OWL mox peoy HSH OSLAL Jejunoo 8 yN
473. ng when IGBT operation is stopped the binary counter is cleared to 0x0000 Also by setting the register the binary counter is cleared to 0x0000 at capture Timer 7 Binary Counter TM7BC Table 6 2 11 Timer 7 Binary Counter Lower 8 bits TM7BCL 0x03F70 7 6 5 4 3 2 1 0 TM7BCL7 TM7BCL6 TM7BCL5 TM7BCL4 TM7BCL3 TM7BCL2 TM7BCL1 TM7BCLO X X X X X X X X R 7 6 5 4 3 2 1 0 TM7BCH 7 TM7BCH 6 TM7BCH 5 TM7BCH 4 TM7BCH 3 TM7BCH 2 TM7BCH1 TM7BCH 0 X X X X X X X R Input capture register is a register that holds the value loaded from a binary counter by a capture trigger cap ture trigger is generated by an input signal from an external interrupt pin the timer 0 interrupt the timer 1 inter rupt and when an arbitrary value is written to an input capture register Directly writing to the register by program 15 disabled Timer 7 Input Capture Register TM7IC Table 6 2 13 Timer 7 Input Capture Register Lower 8 bits TM7ICL 0x03F76 bp 7 6 5 4 3 2 1 0 Flag TM7ICL7 TM7ICL6 TM7ICL5 TM7ICL4 TM7ICL3 TM7ICL2 TM7ICL1 TM7ICLO At reset X X X Access R Table 6 2 14 Timer 7 Input Capture Register Upper 8 bits TM7ICH 0x03F77 7 6 5 4 3 2 1 0 TM7
474. ng communication the transmission buffer empty flag SC1TEMP is automatically set to communi cate continuously Data set to 1 should be done after the data is loaded to the internal shift register before the communication complete interrupt SC1TIRQ is generated At master communication suspension of commu nication between the SCITIRQ generation and the next transfer clock output is 4 transfer clocks Input Edge Output Edge Setup The 5 flag of the SCIMDO register set the output edge of the transmission data and the input edge of the received data Data at transmission is output at the falling edge of clock as the SCICEI flag 0 and at the ris ing edge of clock as the SCICEI 1 Data at reception is input at the rising edge of clock as the SCICEI 0 and at the falling edge of clock as the SCICEI flag 1 Table 12 3 2 Transmission Data Output Edge and Reception Data Input Edge SCACE1 Transmission data output edge Reception data input edge Lo 0 I L Operation XII 17 Chapter 12 Serial interface 1 XII 18 Clock Setup Clock source is selected from the dedicated prescaler and timers 1 2 output 2 channels with the SCIPSC2 to 0 of the SCIMD3 register The dedicated prescaler is started by selecting count enable with the SCIPSCE flag of the SCIMD3 register The SCIMST flag of the SCIMDI register can select the internal clock clock master or the external clo
475. ning of each section 2 Consult the table of contents at the front of the manual to locate desired titles 3 A chapter number and its chapter title are located at the top corner of each page and section titles are located at the bottom corner of each page mRelated Manuals Note that the following related documents are available e MNI101C Series LSI user s Manual Describes the device hardware e MNI101C Series Instruction Manual Describes the instruction set e Series C Compiler User s Manual Usage Guide Describes the installation the commands and options of the C Compiler e MN101C Series C Compiler User s Manual Language Description Describes the syntax of the C Compiler e MN101C Series C Compiler User s Manual Library Reference Describes the standard library of the C Compiler e MNIO0IC Series Cross assembler User s Manual Describes the assembler syntax and notation e MN101C Series C Source Code Debugger User s Manual Describes the use of C source code debugger e About This Manual MN101C Series PanaX Series Installation Manual Describes the installation of C compiler cross assembler and C source code debugger and the procedure for bringing up the in circuit emulator About This Manual 2 gt About This Manual 3 gt Contents Chapter 1 Overview Chapter 2 CPU Basics Chapter 3 Interrupts Chapter 4 Ports Chapter 5 8 Bit Timers Chapter 6 16 Bit
476. njury fire social damages for example by using the products When using products for which damp proof packing is required observe the conditions including shelf life and amount of time let standing of unsealed items agreed upon when specification sheets are individually exchanged This book may be not reprinted or reproduced whether wholly or partially without the prior written permission of Matsushita Electric Industrial Co Ltd If you have any inquiries or questions about this book or our semiconductors please contact one of our sales offices listed at the back of this book About This Manual mOrganization In this LSI manual this LSI functions are presented in the following order overview basic CPU functions interrupt functions port functions timer functions serial functions and other peripheral hardware functions Each section contains overview of function block diagram control register operation and setting example mManual Configuration Each section of this manual consists of a title summary main text key information precautions and warnings and references The layout and definition of each section are shown below Header Chapter number and Chapter title Section title Sub section title Key information chapter 2 Basic CPU 2 8 Reset 8 1 Reset operation the CPU contents are reset and registers are intialized when the NRST pin P 27 is pulled to low
477. notification the data before readout may be overwritten Operation XI 19 Chapter 11 Serial interface 0 XI 20 B Pin Switching Used pin can be switched to A SBOOA SBIOA SBTOA or B SBOOB SBIOB SBTOB by the SCOSL flag of the SCSEL register Data Input Pin Setup 3 channels type clock pin SBTO pin data output pin SBOO pin data input pin SBIO pin or 2 channels type clock pin SBTO pin data I O pin SBOO pin can be selected as a communication mode 5810 pin can be used only for serial data input SBOO pin can be selected as serial data input or output Whether the serial data is input from SBIO pin or SBOO pin it can be selected by the SCOIOM flag of the SCOMDI register When data input from SBOO pin is selected to set the 2 channels type transmission reception can be switched by the SBOO pin direction control For SBOOA pin it can be done by the PADIR2 flag of the PADIR register for SBOOB pin by the P7DIRS flag of the P7DIR At this time SBIO pin can be used a general port too The transfer speed should be up to 5 0 MHz If the transfer clock is over 5 0 the trans Y mission data may not be sent correctly At reception if SCOIOM of the SCOMD register is set to 1 and serial data input from 5800 is selected SBIO pin can be used as a general port Reception Buffer Empty Flag After reception is completed SCOTIRQ is generated data is automatically stored to RXBUFO from
478. nput register P3DIR 0x03F33 Port 3 direction control register P3PLUD 0x03F43 Port 3 pull up pull down resistor control register SELUD 0x03F4B Pull up pull down resistor selection register P30DC 0x03F3B Port 3 Nch open drain control register P5OUT 0x03F15 Port 5 output register P5IN 0 03 25 Port 5 input register P5DIR 0x03F35 Port 5 direction control register P5PLU 0x03F45 Port 5 pull up resistor control register P50MD 0x03F2C Port 5 output mode register P7OUT 0x03F 17 Port 7 output register P7IN 0x03F27 Port 7 input register P7DIR 0x03F37 Port 7 direction control register P7PLUD 0x03F47 Port 7 pull up resistor control register P7OMD 0x03F3C Port 7 output mode register P7ODC OxOSF1D Port 7 Nch open drain control register SELUD 0x03F4B Pull up pull down resistor selection register P9OUT 0x03F19 Port 9 output register Overview 3 Chapter 4 Ports IV 4 Register P9IN 0x03F29 Function Port 9 input register P9DIR 0x03F39 Port 9 direction control register P9PLUD 0x03F49 Port 9 pull up pull down resistor control register SELUD 0x03F4B Pull up pull down resistor selection register XSEL 4 Port9 oscillation switching register PAOUT OxOSF1A Port A output register PAIN OxOSF2A Port A input register PADIR Port A direction control register
479. nsmission SCORIRQ reception Pins TXDO output input RXDO input First transfer bit specification MSB LSB Parity bit selection bit control 0 parity 1 parity odd parity even parity Frame selection 7 bits 1 STOP 7 bits 2 STOP 8 bits 1 STOP 8 bits 2 STOP Continuous operation Maximum transfer rate 300 kbps standard 300 bps to 38 4 kbps with baud rate timer Operation XI 48 Chapter 11 Serial interface 0 XI 44 Activation Factor for Communication At transmission when data is set to the transmission data buffer TXBUFO start condition is generated to start transfer At reception when start condition is received communication is started At reception if the data length of L for start bit is longer than 0 5 bit it can be recognized as start condition B Transmission Data transfer is automatically started by setting data to the transmission data buffer TXBUFO When the trans mission is completed the serial 0 transmission interrupt SCOTIRQ is generated B Reception Once the start condition is recognized reception is started after the transfer bit counter that counts transfer bit is cleared When the reception is completed the serial 0 reception interrupt SCORIRQ is generated Duplex communication On duplex communication the transmission and reception can be operated separately at the same time The frame mode and parit
480. nsmission Timing 1 Output start condition 2 Bus released period ACK bit is received 3 Interrupt Set data to TXBUF3 4 Receive ACK bit 5 Interrupt Communication ends clear the IIC3BSY flag 6 Generates stop condition Operation XIII 43 Chapter 13 Serial Interface 3 Master Reception Timing 1 2 8 0 60 06 4 805 Sbiits transmission transmission SDA SCL Interrupt IIC3BSY Write data to Write data to IIC3STPC flag set Set dummy data Figure 13 3 22 Master Reception Timing 1 Output start condition 2 Bus released period ACK bit is received 3 Interrupt Set to reception mode 20 1 Set data to TXBUF3 4 Receive ACK bit 5 Interrupt Communication ends clear the IIC3BSY flag 6 Generates stop condition XIII 44 Operation B Pin Setup 2 channels at transmission Chapter 13 Serial Interface 3 Table 13 3 16 shows the pins setup in serial interface transmission with 2 channels SDA3 SCL3 Table 13 3 16 Pin Setup 2 channels at transmission Item Data pin Clock output pin SDA3 SCL3 pin Pin P33 P32 SDA3 SCL3 pins SBI3 SBO3 pin connection SC3MD1 SC3IOM Function Serial data output Serial clock output SC3MD1 SC3SBOS SC3MD1 SC3SBTS Serial data input SC3MD1 SC3SBIS Type N ch open drain N ch open drain
481. nsmission is operated from A to F TXBUF1 F E D C B Figure 12 3 2 Transmission Bit Count and First Transfer Bit starting with MSB TXBUF1 F E D C B Figure 12 3 3 Transmission Bit Count and First Transfer Bit starting with LSB Reception Bit Count and First Transfer Bit At reception when the transfer bit count is 1 bit to 7 bits the data storing method to the received data buffer RXBUF1 is different depending on the first transfer bit At MSB first data is stored to the lower bits of RXBUFI When the transfer bit count is 6 bits as shown on figure Figure 12 3 5 if data A to are stored to to bp5 of RXBUFI the transmission is operated from to A At LSB first data is stored to the upper bits of RXBUFI When there the transfer bit count is 6 bits as shown on Figure 12 3 4 if data A to F are stored to bp2 to bp7 of RXBUF1 the transmission is operated from to 1 B C D E F Figure 12 3 4 Reception Bit Count and First Transfer Bit starting with MSB bit 7 6 5 4 3 2 1 0 RXBUF1 F E D C B Figure 12 3 5 Reception Bit Count and First Transfer Bit starting with LSB bit XII 16 Operation Chapter 12 Serial interface 1 Continuous Transmission This serial interface has a function for continuous communication If data is set to the transmission data buffer TXBUFI duri
482. nt It is also available to normal port output When port real time control disabled is selected at the port 1 output control register PICNTO if switching event is generated the value is not be changed Set this mode when it is used as the general port Real Time Output Control Chapter 4 Ports Real Time Output Control Operation After the setup of the port 1 output control register PICNTO selected function at the port 1 output mode register PIOMD is output to the pin until the falling edge is generated at the external interrupt 0 pin P54 IRQO When the falling edge is generated pin output is switched to the set value The falling edge event is taken in the edge event hold function that is shown below and the setup value of the port 1 output control register PICNTO is held until that information is cleared Real Time Output Release Clearance of edge event hold function After the event generation when the write operation is done to the port output register P1OUT the informa tion of the edge event hold function is cleared and all output pins are reset to the output data before the event gen eration The event is generated again it is switched to the setup value of the port 1 output control register PICNTO When the real time control is canceled set the port 1 output control register PICNTO to I O port real time control disabled Regardless of the setup at the external interrupt 0 control register
483. nt and First transfer Bit starting with MSB bit RXBUFO F E D C B Figure 11 3 5 Reception Bit Count and First transfer Bit starting with LSB bit Operation XI 17 Chapter 11 Serial interface 0 XI 18 Continuous Transmission This serial interface has a function for continuous communication If data is set to the transmission data buffer TXBUFO during communication the transmission buffer empty flag SCOTEMP is automatically set to communi cate continuously Data setup to TXBUFO should be done after the data is loaded to the internal shift register before the communication complete interrupt SCOTIRQ is generated At master communication suspension of communication between the SCOTIRQ generation and the next transfer clock output is 4 transfer clocks Input Edge Output Edge Setup The SCOCEI flag of the SCOMDO register sets the output edge of the transmission data and the input edge of the reception data Data at transmission is output at the falling edge of clock as the SCOCEI flag 0 and at the ris ing edge of clock as the SCOCEI 1 Data at reception is input at the rising edge of clock as the SCOCEI 0 and at the falling edge of clock as the SCOCEI flag 1 Table 11 3 2 Transmission Data Output Edge and Reception Data Input Edge SCOCE1 Transmission data output edge Reception data input edge 0 qp 2 L Operation Chapter 11 Serial inter
484. nter with 8 bit displacement Specifies the address using the stack pointer with 16 bit displacement T 0 Absolute 9898 0 i m E ______20578 branch instructions only 4 Specifies the address using the operand value appended to the instruction code Optimum operand length can be used to specify the address RAM short abs8 7 0 short 15 0 IOTOP i08 Handy HA Figure 2 1 8 Address Space Overview Specifies an 8 bit offset from the address x 00000 Specifies an 8 bit offset from the top address x 03F00 of the special function register area Reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combined use with absolute addressing reduces code size 1 H half byte bit Chapter 2 CPU Basics 2 1 40 Machine Clock B 6 Machine clock is generated based on the system clock dividing the source oscillation frequency The machine clock is the base timing for control of CPU Internal Memory Access wait cycle NORMAL mode Source oscillation zT xr pers qe frequency System clock fs 1 machine clock 1 bus cycle Figure 2 1 9 Machine Clock no wait cycle Oscillation frequency of system clock differs depending on the CPUM register settings Y Chapter 2 2 5 Clock Switching Overview 15 Chapter 2 CPU Basics
485. nterrupt is enabled but interrupt priority level of the interrupt to be used is not equal to ble to return to CPU operation mode by maskable interrupt a Set the of XSEL register before changing to the low speed oscillation mode Standby Function Chapter 2 CPU Basics Transition to HALT modes The system transfers from NORMAL mode to HALTO mode and from SLOW mode to HALT mode The CPU stops operating but the oscillators remain operational There are two ways to leave a HALT mode a reset or an interrupt reset produces a normal reset an interrupt an immediate return to the CPU state prior to the transition to the HALT mode The watchdog timer if enabled resumes counting Program 4 x4 DO Set HALT mode MOV 00 CPUM NOP After written in CPUM some NOP NOP instructions three or less are NOP executed Transition to STOP mode The system transfers from NORMAL mode to STOPO mode and from SLOW mode to STOP mode In both cases oscillation and the CPU are both halted There are two ways to leave a STOP mode a reset or an interrupt When it changed to the stop mode watchdog timer counter is cleared Restart counting at the recovery and the oscillation stabilization wait is done The count is continued after the recovery to CPU operation mode Program 5 DO SetHALT mode MOV 00 CPUM NOP After written in CPUM some NOP NOP instructions three or les
486. nterrupt request generated Control Registers Ill 27 Chapter 3 Interrupts Timer 6 Interrupt Control Register TM6ICRB The timer 6 interrupt control register TM6ICR controls interrupt level of timer 6 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 11 Timer 6 Interrupt Control Register TM6ICR 0x03FEB 7 6 TM6LV1 TM6LVO 0 0 Description TM6LV1 Interrupt level flag TM6LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated 28 Control Registers Chapter 3 Interrupts Time Base Interrupt Control Register TBICR The time base interrupt control register TBICR controls interrupt level of time base interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 12 Time Base Interrupt Control Register TBICR 0x03FEC Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Dis
487. ntrol register TM2ICR controls interrupt level of timer 2 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 9 Timer 2 Interrupt Control Register TM2ICR 0x03FE9 7 6 TM2LV1 TM2LVO 0 0 Description 2 1 Interrupt level flag 21 0 This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated Ill 26 Control Registers Chapter 3 Interrupts Timer 3 Interrupt Control Register TM3ICR The timer 3 interrupt control register TM3ICR controls interrupt level of timer 3 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE or PSW is 0 Table 3 2 10 Timer 3 Interrupt Control Register TM3ICR 0x03FEA 7 6 TMSLV1 TMSLVO 0 0 TMSLV1 TMSLVO Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 I
488. nvoked by the RTI instruction 1 The contents of the PSW are restored from the stack SP 2 The contents of the program counter PC i e then return address are restored from the stack SP 1 to SP 3 3 The contents of the handy address register are restored from the stack SP 4 5 5 4 The stack pointer is updated SP 6 SP 5 Execution branches program to the address in the program counter The handy address register is an internal register used by the handy addressing function The hardware saves its contents to the stack to prevent the interrupt from interfering with operation of the function Registers such as data register or address register are not saved so that PUSH instruction Y from program should be used to save them onto stack if necessary The address bp6 to bp2 when program counter PC saved to the stack are reserved Y Do not change it by program Overview 11 Chapter 3 Interrupts B Maskable Interrupt Figure 3 1 6 shows the processing flow when a second interrupt with a lower priority level xxxLV1 xxxLV0 10 arrives during the processing of the with a higher priority level xxxLV1 xxxLV0 00 D 0 1 00 Set 0 11 Interrupt 1 generated 2 Accepted because IL lt MIE 1 xxxLV1 0 00 IM1 0 00 Interrupt acceptance cycle
489. ock TAp calculated as fs fosc 2 fx 4 Table 15 3 1 A D Conversion Clock and A D Conversion Cycle ANCK1 ANCKO A D conversion A D conversion cycle TAp un at high speed oscillation at low speed oscillation fosc 10 MHz fosc 8 38 MHz fosc 32 768 kHz 0 0 fs 2 400 ns no usable 477 33 ns no usable 244 14 us 1 fs 4 800 ns 954 65 ns 488 28 us 1 0 fs 8 1600 ns 1 91 us 976 56 us 1 fx 2 15 26 us 15 26 us 15 26 us For the system clock fs refer to Chapter 2 Clock Switching A D Converter Sampling Time Ts Setup The sampling time of A D converter is set by the ANSHI to 0 flag of the ANCTRO register The sampling time of A D converter depends on external circuit so set the right value by analog input impedance Table 15 3 2 Sampling Time of A D Conversion and A D Conversion Time ANSH1 ANSHO Sampling A D conversion time us time Ts at high speed at low speed at Tap 1600 at at Tap 1 91 at at ns Tap 954 65 us Tap 15 26 Tap 15 26 fs 5 MHz ns fs 4 19 us us fs 4 19 MHz fx 32 768 fx 32 768 MHz kHz kHz 0 0 Tap x 2 24 5 14 82 29 15 229 4 534 15 1 Tap X 6 30 9 18 64 36 79 290 44 595 19 1 0 Tap X18 50 1 30 09 59 71 473 56 778 31 1 Tap X18 50 1 30 09 59 71 473 56 778 31 Calculated as fs fosc 2 fx 4 XV 10 Operation Chapter 15 A D Converter sion start flag is enabled and the instant when the ac
490. ock High speed oscillation fx Machine clock Low speed oscillation fs System clock Chapter 2 2 5 Clock Switching 1 Can be used when a clock source of time base timer is selected to fosc 2 Can be used when a clock source of time base timer is selected to fx VII 2 Overview Chapter 7 Time Base Timer Free running Timer 1 When fs is used as a clock source it counts at rising of the count clock and in other uses it counts falling of the count clock 1 Count clock source should be changed when the timer interrupt is disabled Overview VII 3 Block Diagram Timer 6 Time Base Timer Block Diagram 7 1 2 Time Base Timer Free running Timer Chapter 7 Jou eseq Oula L mox 9 e 250 9891 0 N389AL Figure 7 1 1 Block Diagram Timer 6 Time Base Timer 2 oJuou S X eion HHI9INL SMOSW 209 1 1 arc 0 ISH O89NL Jejunoo 10 8 gt orem ei WpeeH 110 8 9 Overview VII 4 Chapter 7 Time Base Timer Free running Timer 7 2 Control Registers Timer 6 consists of binary counter TM6BC compare register TM6OC and is controlled by mode register TM6MD Time base timer is controlled by mode register TM6MD and
491. of this Series has the following instructions The assembler will interpret the macro instructions below the assembler instructions macro instructions replaced instructions remarks INC Dn ADD 1 Dn DEC Dn ADD 1 Dn INC An ADDW 1 An DEC An ADDW 1 An INC2 An ADDW 2 DEC2 An ADDW 2An CLR Dn SUB Dn Dm ASL Dn ADD Dn Dm LSL Dn ADD Dn Dm ROL Dn ADDC Dn Dm NEG Dn NOT Dn ADD 1 Dn NOPL MOVW _ DWn DWm MOV MOV 0 SP Dn MOV MOV Dn 0 SP MOVW 0 SP DWn MOVW MOVW DWn 0 SP MOVW MOVW 0 SP An MOVW MOVW An 0 SP Ver3 2 2002 01 31 Instruction Set XVII 33 Chapter 17 Appendix 17 6 Instruction Map XVII 34 MOV 48 o8 MN101C SERIES INSTRUCTION MAP 1stnibble 2nd nibble CMP 8 abs8 abs12 POP An ADD 8 Dm D E F MOVW 8 DWm MOVW 8 Am JSR d12 label JSR d16 label MOV 8 abs8 abs12 PUSH An OR 8 Dm AND 8 Dm When the exension code is b oo 0 When the extension code is b 00 11 MOV abs12 Dm MOV abs8 Dm An Dm MOV Dn abs12 MOV Dn abs8 MOV Dn Am MOV i08 Dm d4 SP Dm d8 An Dm MOV Dn io8 MOV Dn d4 SP MOV Dn d8 Am ADD 4 Dm SUB Dn Dn d7 BRA d7 d7 BNE d7 BCC d7 BCS d7 BLT d7 BEQ d4 BNE d4 MOVW DWn HA MOVW 411
492. og input leakage When channel is OFF _ 2 current Vapin 0 V to 3 V Reference voltage When is OFF m input leakage current VssSVnErF SVpp B 14 Ladder resistance 3 0 V Vss 0 V 10 30 60 11 TAD is A D converter clock cycle The values of 2 to 5 are guaranteed on the condition that Ver 23 0 V Vgg 0 V Electrical Characteristics Overview 33 Chapter 1 Overview 1 6 Package Dimension Package code TQFP048 P 0707B Units mm 9 00020 9 00 0 20 L ni mumHHHHHHH SEATING PLANE Figure 1 6 1 Package Dimension The external dimensions of the package are subject to change Before using this product Y please obtain product specifications from the sales offices 1 34 Package Dimension Chapter 1 Overview 1 7 Cautions for Circuit Setup 1 7 1 General Usage Connection of Vpp pin and Vss pin of the VDD and VSS pins should be connected directly to the power source and ground in the external Put them on printed circuit board after the location of LSI package pin is confirmed Connection error may lead a fusion and breakdown of a micro controller Cautions for Operation 1 If you install the product close to high field emissions under the cathode ray tube etc shield the package surface to ensure normal performance 2 Operation temperature should be well considered Each product has differ
493. ol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x03F94 SCOMD3 SCOFDC SCOFDC SCOPSC SCOPSC SCOPSC SCOPSC XI 10 1 0 E 2 1 0 0 0 0 0 0 0 Output selection after Prescale Selection clock 5800 final data trans r count mit control 0 03 95 SCOSTR SCOTBS SCORBS SCOTEM SCORE SCOFEF SCOPEK SCOOR SCOERE 11 Y Y P MP E 0 0 0 0 0 0 0 0 Serial bus status Transfer Receive Framing Parity Overrun Error buffer buffer error error error monitor empty empty detection detection detection flag OxO3F96 RXBUFO RXBUFO RXBUFO RXBUFO RXBUFO RXBUFO RXBUFO RXBUFO RXBUFO XI 6 7 6 5 4 3 2 1 0 x x x x x x x x Serial interface 0 reception data buffer 0x03F97 TXBUFO TXBUFO TXBUFO TXBUFO TXBUFO TXBUFO TXBUFO TXBUFO TXBUFO 6 7 6 5 4 3 2 1 0 x X X x x x x x Serial interface 0 transmission data buffer 0x03F99 SC1MD0 SC1CE1 SC1DIR SC1STE SCILNG SC1LNG SC1LNG XII 7 2 1 0 0 0 0 1 1 1 transmiss Transfer Start Synchronous transfer bit specifica ion bit speci condi tion recep fication tion tion edge selection selection SC1MD1 SC1IOM SC1SBT SC1SBI SC1SBO SC1CK SC1MST SC1DIV SC0CM XII 8 s s s M D 0 0 0 0 0 0 0 0 Serial SBT Serial SBO Transfer Clock Transfer Synchro data function input function clock master clock nous input selection control selection dividing slave dividing UART selection selection selection se
494. ol direction register P3DIR to 1 and set P3DIR1 to 0 to set P32 Operation XIII 31 Chapter 13 Serial Interface 3 Setup Procedure Description 5 Set the SC3MDO register Select the transfer bit count SC3MDO 0x03FA0 bp2 0 SC3LNG2 0 111 Select the start condition SC3MDO 0x03FA0 bp3 SC3STE 0 Select the first transfer bit SC3MDO 0x03FA0 bp4 SC3DIR 0 Select the transfer edge SC3MDO 0x03FA0 bp6 SC3CE1 1 6 Set the SC3CTR register SC3CTR 0x03FA6 bp2 SC3CMD 0 7 Set the SC3MD1 register Select the transfer clock SC3MD1 0x03FA1 bp2 SC3MST 0 Control the pin function SC3MD1 0x03FA1 bp4 SC3SBOS 0 bp5 SC3SBIS 1 bp6 SC3SBTS 1 bp7 SC3IOM 0 8 Set the interrupt level SC3ICR 0 0 bp7 6 SC3LV1 0 10 9 Enable the interrupt SC3ICR SCSIE 1 bp0 SCSIR 0 10 Start serial reception dummy data 0x03FA5 Reception data Input to 5813 pin XIII 32 5 Set the SC3LNG2 0 flag of the serial 3 mode register SC3MDO to 111 to set the transfer bit count as 8 bits Set the SC3STE flag of the SC3MDO register to 0 to disable start condition Set the SC3DIR flag of the SC3MDO register to 0 to set MSB as the first transfer bit Set the SC3CE1 flag of the SC3MDO register to 1 to set the transmission data output edge to rising and the reception data input edge to falling 6
495. om the preset register to the compare register in synchronization with the counter clock Dead Time Count Dead time counter counts the timer clock source When the dead time insert is set as rising standard set the period from the falling of TMSIO to the rising of TM7IO to the dead time preset register 1 TM7DPR1 and the period from the falling of TM7IO to the rising of TM8IO to the dead time preset register 2 TM7DPR2 Dead time is inserted for the period of the set value 1 Only for the period from the IGBT output is enabled by the IGBT trigger to the first rising of TM7IO in the case of the IGBT falling standard the set value of the TM7DPRI 2 is inserted to the dead time 1 count clock should be longer than usually Dead Time IGBT Output Chapter 6 16 bit Timers Count Timing of Dead Time IGBT Output Timer 7 OI8IA L euin peeq fof oo oo ful ro Joo 22222 l ic __ osas u HddZIA L 1991 eojnos Figure 6 11 1 Count Timing of Dead Time IGBT Output Timer 7 VI 73 Dead Time IGBT Output Chapter 6 16 bit Timers VI 74 Output waveform of the IGBT with dead time at falling edge standard A TM7IO L TM8IO L until the IGBT trigger is input and become valid B After the trigger is input
496. ompare i i Register 1 i i I Register 2 i E i i IGBT Trigger Binary Y Y Y 0000 0001 X 0002 N X TM7IO output IGBT output 8 output IGBT output Figure 6 9 6 One Shot Pulse Output of High Precision IGBT Output When compare register 2 compare register 1 Timer 7 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively VI 61 Chapter 6 16 bit Timers 6 9 2 Setup Example B High precision IGBT Output Setup Example Timer 7 At the interrupt generation edge of the external interrupt 0 input signal TM71IO output pin outputs the waveform of 1 4 duty IGBT output waveform at 400 Hz using the timer 7 Select fosc 2 at fosc 20 MHz as the clock source Required period for one IGBT output waveform cycle depends on the set value of the compare register 1 period of IGBT output waveform depends on the set value of the compare register 2 An example setup procedure with a description of each step is shown below IGBT trigger output 400 Hz Figure 6 9 7 Output Waveform of TM71O Output Pin Setup Procedure Description 1 Stop the counter TM7MD 1 x 3F78 bp4 TM7EN 0 2 Set the output of special function pins P10MD x 3F1C bp4 P1OMD3 1 bp3 NBUZSEL 1 bp4 P1OMD2 1 bp3 BUZSEL 1 P1DIR x 3F31 bp3 P1DIR3 1 bp2 P1DIR2 1 3 S
497. on 0 Pull up 1 Pull down Port 9 pull up pull down selection 0 Pull up 1 Pull down Port 7 pull up pull down selection 0 Pull up 1 Pull down Port 1 pull up pull down selection 0 Pull up 1 Pull down IV 54 Port 7 Chapter 4 Ports Serial I O Pin Switching Control Register SCSEL 0x03F90 TMPSC11 0 TMPSC1 2 TMPSC11 Description Serial 1 used timer 2 output dividing switching selection X0 Timer 2 output 01 Timer 2 output 2 11 Timer 2 output 8 TMPSCO 2 TMPSCO 1 Serial 0 used timer 2 output dividing switching selection XO0 Timer 2 output 01 Timer 2 output 2 11 Timer 2 output 8 Serial 4 pin switching selection 0 P10 P11 1 P76 P77 Serial 1 pin switching selection 0 P15 to P17 1 PA4 to PA6 Serial 0 pin switching selection to PA2 1 P75 to P77 Port 7 IV 55 Chapter 4 Ports IV 56 LCD Output Control Register 1 LCCTR1 X 3FC2 R W LC1SL3 LC1SL2 LC1SL1 LC1SLO COMSL3 COMSL2 COMSL1 COMSLO 0 0 0 0 0 0 0 0 LC1SL3 Description SEG3 P74 selection 0 P74 1 SEG3 LC1SL2 SEG2 P75 selection 0 75 1 SEG2 LC1SL1 SEG1 P76 selection 0 P76 1 SEG1 LC1SLO SEGO P77 selection 0 77 1 SEGO COMSL3 selection 0 P33 1 COM3 COMSL2 COM 2 P32 selection 0 P32 1 C
498. on Figure 12 3 18 data to A are stored to bp7 to bp1 of RXBUFI in this order At LSB first data is stored to the lower bits of RXBUFI When the transfer bit count is 7 bits as shown on Figure 12 3 19 data to are stored to to bp6 of RXBUFI in this order wei HL 5 Figure 12 3 18 Reception Bit Count and First Transfer Bit starting with MSB Bo 6 25 4 3 2 C 0 RXBUF1 6 N Figure 12 3 19 Reception Bit Count and First Transfer Bit starting with LSB Operation The following items the same as clock synchronous serial B First Transfer Bit Setup Refer to XII 14 B Transmission Data Buffer Refer to XII 15 Reception Data Buffer Refer to XII15 Transmission Bit Count and First Transfer Bit Refer to XII 16 B Transmission Buffer Empty Flag Refer to XII 19 B Emergency Reset Refer to XII 20 Chapter 12 Serial interface 1 Operation XII 47 Chapter 12 Serial interface 1 Transmission Timing TXD1 pin gt Stop bit SC1TBSY Data settoTXBUF1 1 Interrupt SC1TIRQ Figure 12 3 20 Transmission Timing parity bit is enabled TXD1 pin Stop bit SC1TBSY setto TXBUF1 7 Interrupt SC1TIRQ Figure 12 3 21 Transmission Timing parity bit is disabled XII 48 Operation Chapter 12 Serial interface 1 Reception Timin
499. on of each step is shown below IGBT Trigger 305 18 2 lt gt Figure 6 10 4 Output Waveform of TM71O Output Pin and TM8IO Output Pin Setup Procedure Description 1 Stop the counter TM7MD1 x 3F78 bp4 TM7EN 0 2 Set the output of special function pins P1OMD x 3F1C bp4 P1OMD3 1 bp3 NBUZSEL 1 P1DIR x 3F31 bp4 P1DIR3 1 3 Set IGBT output TM7MD3 x 3F8E bp2 TM7IGBTEN 1 TM7MD2 x 3F79 bp4 PM7PWM 1 4 Set the standard IGBT output operation TM7MD2 x 3F79 bp5 TM7BCR 1 5 Select IGBT trigger generation interrupt source TM7MD3 x 3F8E bp1 0 T7IGBT1 0 01 1 Set the TM7EN flag of the timer 7 mode register 1 TM7MD1 to 0 to stop the timer 7 counting 2 Set the P1OMDS flag of the port 1 output mode register P1OMD to 71 to set the P13 pin to the special function pin Set the P1DIR3 flag of the port 1 direction control register P1DIR to 1 to set the output mode Add pull up pull down resistor if necessary Chapter 4 port 8 Set the T7IGBTEN flag of the timer 7 mode register 3 TM7MD3 to 1 the TM7PWM flag of the timer 7 mode register 2 TM7MD2 to 1 to select IGBT output 4 Set the TM7BCR flag of the TM7MD2 register to 0 to select the full count overflow as the clear factor of the binary counter b Set the external interrupt 0 IRQO input as IGBT trigger generation factor by the T7IG
500. on result Otherwise zero flag is cleared to 0 Carry Flag CF Carry flag CF is set to 1 when a carry from or a borrow to the MSB occurs Carry flag is cleared to 0 when no carry or borrow occurs Negative Flag NF Negative flag NF is set to 1 when MSB is 1 and reset to 0 when MSB is 0 Negative flag is used to handle a signed value Overflow Flag VF Overflow flag VF is set to 1 when the arithmetic operation results overflow as a signed value Otherwise overflow flag is cleared to 0 Overflow flag is used to handle a signed value Interrupt Mask Level IM1 and IMO Interrupt mask level IM1 and IMO controls the maskable interrupt acceptance in accordance with the interrupt factor interrupt priority for the interrupt control circuit in the CPU The two bit control flag defines levels 0 to 3 Level 0 is the highest mask level The interrupt request will be accepted only when the level set in the inter rupt level flag xxxLVn of the interrupt control register is higher than the interrupt mask level When the interrupt is accepted the level is reset to IM1 IMO and interrupts whose mask levels are the same or lower are rejected during the accepted interrupt processing Table 2 1 5 Interrupt Mask Level and Interrupt Acceptance Interrupt mask level Priority Acceptable interrupt level IM1 IMO Mask level 0 0 0 Highest Non maskable interrupt NMI only Mask leve
501. on the first transfer bit selection At MSB first use the upper bits of TXBUFO for storing When the transfer bit count is 6 bits as shown on Figure 11 3 2 if data A to stored to bp2 to bp7 of TXBUEFO the transfer is operated from F to A At LSB first use the lower bits of TXBUFO for storing When the transfer bit count is 6 bits as shown on Figure 11 3 3 if data A to F are stored to to 6 5 of TXBUFO the transfer is operated A to F TXBUFO F Figure 11 3 2 Transmission Bit Count and First Transfer Bit starting with MSB TXBUFO F E D C B Figure 11 3 3 Transmission Bit Count and First Transfer Bit starting with LSB Reception Bit Count and First Transfer Bit At reception when the transfer bit count is 1 bit to 7 bits the data storing method to the reception data buffer RXBUFO is different depending on the first transfer bit At MSB first data is stored to the lower bits of RXBUFO When the transfer bit count is 6 bits as shown on figure Figure 11 3 5 if data A to F are stored to bpO to bp5 of RXBUFO the transfer is operated from F to A At LSB first data is stored to the upper bits of RXBUFO When the transfer bit count is 6 bits as shown on Figure 11 3 4 if data A to F are stored to bp2 to bp7 of RXBUFO the transfer is operated from A to F RXBUFO B C D E F Figure 11 3 4 Reception Bit Cou
502. onnect the timer 7 and the timer 8 to the cascade b Select fs as the clock source by the TM7CK1 to 0 of the TM7MD 1 register Also select 1 2 of fs as the count clock source by the TM7PS1 to 0 flag 6 Set the interrupt generation cycle to the timer 7 preset register 1 TM7PR1 and the timer 8 preset register TM8PR1 100000 cycles 1 At the same time the same values as the preset registers are loaded to the timer 7 compare register 1 TM7OC1 and the timer 8 compare register TM8OC1 and the binary counters TM7BC TM8BC are initialized to x 0000 7 Set the TM7IE flag of the timer 7 interrupt control register TM7ICR to 0 to disable the interrupt 8 Set the interrupt level by the TM8LS1 to 0 flag of the timer 8 interrupt control register TM8ICR If any interrupt request flag is already set clear it Chapter 3 3 1 4 Interrupt Flag Setup 16 bit Timer Cascade Connection VI 81 Chapter 6 16 bit Timers VI 82 Setup Procedure Description 9 Enable the upper timer interrupt TMBICR bp1 TM8IE 1 10 Start the lower timer operation TM7MD 1 3 78 bp4 TM7EN 1 9 Set the flag of the TM8ICR register to 1 to enable the interrupt 10 Set the TM7EN flag of the TM7MD1 register to 1 to operate the timer 7 TM7BCL TM7BCH TM8BCL TM8BCH counts up from X 00000000 as a 32 bit timer When TM7BCL TM7BCH TM8BCL TM8BCH reaches the set value
503. onnect these oscillation pins to crystal oscillators for low frequency clock operation If the clock is an external input connect it to XI and leave XO open When using the STOP mode the chip will not operate with an external clock If these pins are not used connect XI to Vgs and leave XO open NRST 12 12 Input P27 Reset pins Active low This pin resets the chip when power is turned on is allocated as P27 and contains an internal pull up resistor Type 35 kw Setting this pin L level initialize the internal state of the device Thereafter setting the input to H level releases the reset The hardware waits for the system clock to stabilize then processes the reset interrupt Also if 0 is written to P27 and the reset is initiated by software L level will be output The output has an N ch open drain configuration If a capacitor is to be inserted between NRST and Vas it is recommended that a discharge diode be placed between NRST and Vpp P10 13 13 P11 14 14 P12 27 24 P13 28 25 P14 29 26 P15 30 27 P16 31 28 P17 32 29 yo SDA4A SCL4A TM8IO BUZZER 7 NBUZZER CLKOUT TMOIO RMOUT SEG11 TMOOB SBO1A TXD1A SEG10 TMeIO SBI1A RXD1A SEG9 TM2OB SBI1A SEG8 port 0 8 bit COMS tri state I O port Each bit can be set individually as either an input or output by the P1DIR register A pull up pull down resistor for each bit can be selected individually by the P1PLU re
504. ontains a force reset function If the communication should be stopped by force set SC1SBOS and SC1SBIS of the SC1MD1 register to 0 Each flag should be set as this setup procedure in order Activation of communication should be operated after all control registers refer to Table 12 2 1 except TXBUF1 are set Transfer rate of transfer clock set by the SC1MD3 register should not exceed 5 0 MHz Operation Chapter 12 Serial interface 1 B Transmission Reception Setup Example Standby Mode Reception The setup example for clock synchronous serial communication with serial 1 is shown Table 12 3 14 shows the condition at standby mode reception Table 12 3 14 Setup Examples for Synchronous Serial Interface Transmission Reception Standby Mode Reception Setup item Set to Serial data input pin Select SBI1 3 channels Transfer bit count 8 bit Start condition None First transfer bit MSB Input edge Falling edge Clock Clock slave Operation mode Stop mode Clock source fs 2 Clock source dividing Not divided Used pin A port 1 SBT1 SBO pin style Push pull 5871 pin pull up resistor Not added SBO pin pull up resistor Not added serial 1 communication complete Enable interrupt An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Select the prescaler operation 1 Set the SC1PSCE fl
505. ontrol register P1DIR to 1 to set the output mode Chapter 4 Port Function 3 Set the TMOMOD flag of the TMOMD register to 0 to select the normal timer operation 4 Select the prescaler output to the clock source by the 2 to 0 flag of the TMOMD register b Select fs 2 to the prescaler output by the TMOPSC 1 to 0 flag and TMOBAS flag of the timer 0 prescaler selection register CKOMD 6 Set the timer 0 compare register to the 1 2 of the timer pulse output cycle The setting value should be 50 1249 0x31 for 100 kHz to be divided by 5 MHz At that time the timer 0 binary counter is initialized to 0 00 7 Set TMOEN flag of the TMOMD register to 1 to operate the timer 0 TMOBC counts up from 0x00 If TMOBC reaches the setting value of the TMOOC register then TMOBC is cleared to 0x00 TMOIO output signal is inverted and TMOBC restarts to count up from 0x00 If any data is written to compare register when the binary counter is stopped timer output is reset to 8 bit Timer Pulse Output Chapter 5 8 bit Timers If any data is written to compare register when the binary counter is stopped timer output is reset to L Compare register Compare register Timer pulse output Selection clock cycle x 2 1 8 bit Timer Pulse Output 33 Chapter 5 8 bit Timers 34 5 7 8 bit PWM Output The TMnIO pin outp
506. or SBOO pin with 2 lines is changed from to L Also it is recognized when 5 1 flag is set to 1 and a clock line SBTO pin is L data line SBIO pin with 3 lines or SBOO pin with 2 lines is changed from H to L Both the SCOSBOS flag and the SCOSBIS flag of the SCOMDI register should be set to 0 before the start condi tion setup is changed When transmission and reception are executed at the same time set the start condition to disable to prevent abnormal operation First Transfer Bit Setup The SCODIR flag of the SCOMDO register can set the transfer bit MSB first or LSB first can be selected B Transmission Data Buffer The transmission data buffer TXBUFO is the spare buffer which stores data to be loaded to internal shift register Set the data to be transferred to transmission data buffer TXBUFO and the data is automatically loaded to internal shift register The data loading takes more than 3 transfer clocks cycles Data setting to TXBUFO again during data loading may not be operated properly You can determine whether or not data loading is in progress by mon itoring transmission buffer empty flag SCOTEMP of the SCOSTR SCOTEMP flag is set to 1 when data is set to TXBUFO and cleared to 0 when data loading ends Data set to TXBUFO Clock Prescaler output SCOTEMP CIock SBTO pin Data road period Figure 11 3 1 Transmission Data Buffer Reception Date Buffer The re
507. or duplex UART communication Table 12 3 15 shows UART serial interface functions Table 12 3 15 URAT Serial Interface Functions Communication style UART duplex j Interrupt SC1TIRQ transmission SC1RIRQ reception Used pins TXD1 output input RXD1 input First transfer bit specification MSB LSB Parity bit selection bit control 0 parity 1 parity odd parity even parity Frame selection 7 bits 1 STOP 7 bits 2 STOP 8 bits 1 STOP 8 bits 2 STOP Continuous operation Maximum transfer rate 300 kbps standard 300 bps to 38 4 kbps with baud rate timer XII 42 Operation Chapter 12 Serial interface 1 Activation Factor for Communication At transmission when data is set to the transmission data buffer TXBUFI start condition is generated to start transfer At reception when a start condition is received communication is started At reception if the data length of L for start bit is longer than 0 5 bit that can be recognized as start condition B Transmission Data transfer is automatically started by setting data to the transmission data buffer TXBUF1 When the trans mission is completed the serial 1 transmission interrupt SCITIRQ is generated Reception Once the start condition is received reception is started after the transfer bit counter that counts transfer bit is cleared When the reception is completed the serial 1 reception interrupt SC
508. oss detector signal at the standby mode External Interrupts 59 Chapter 3 Interrupts 60 AC Zero Cross Detector Setup Example External interrupt 0 and 1 AC zero cross detector generates the external interrupt 1 by using P55 ACZI pin An example of the setup procedure with a description of each step is shown below If the input level signal which is input from 55 2 pin cross with the intermediate level the external interrupt is generated Setup Procedure Description 1 Select the AC zero cross detector signal NFCTR 0x03F2E bp7 P55IM 1 2 Set the interrupt level IRQ1ICR 0x03FE3 bp7 6 IRQ1LV1 0 10 3 Enable the interrupt IRQ1ICR 0x03FE3 bp1 IRQ1IE 1 1 Set the P211M flag of the noise filter control register NFCTR to 1 to select the AC zero cross detector signal as the external interrupt 1 generation factor 2 Set the interrupt level by the IRQ1LV1 to 0 flag of the IRQ1ICR register If the interrupt request flag has been already set clear the interrupt flag Chapter 3 3 1 4 Interrupt Flag Setup 3 Set the IRQ1IE flag of the IRQ1ICR register to 1 to enable the interrupt When the input level of the input signal from 55 2 pin crosses with the intermediate level the external interrupt 1 is generated External Interrupts Chapter 3 Interrupts 3 3 9 External Interrupt At The Standby Mode External Interrupt
509. output pin Serial unused pin Clock I O pin SBO1A SBO1B SBI1A pin SBI1B SBT1A SBT1B pin pin Clock master Clock slave SC1SCMD1 SC1MST Port pin P15 PA5 P16 PA4 P17 PA6 Port setup Select used pin A SCSEL SC1SL Serial data input SBO1 selection SC1MD1 SC11OM Function Serial data input 1 input Transfer clock I O Transfer clock I O SC1MD1 SC1SBOS SC1MD1 SC1SBIS SC1MD1 SC1SBIS Style Push pull Nch open Push pull Nch open Push pull Nch open drain drain drain P10DC P10DC5 P1ODC P1ODC7 PAODC PAODC6 PAODC PAODC5 Input mode P1DIR P1DIR5 P1DIR P1DIR7 PADIR PADIR6 PADIR P1DIR5 Pull up setup Added Not added Added Not added Added Not added P1PLUD P1PLUD5 P1PLUD P1PLUD7 PAPLU PAPLU6 PAPLU PAPLUS Operation XII 31 Chapter 12 Serial interface 1 XII 32 B Pins Setup with 2 channels at reception Table 12 3 11 shows the setup for synchronous serial interface pin with 2 channels SBOI SBT1 pin at reception SBII pin can be used as a port Table 12 3 11 Setup for Synchronous Serial Interface Pin with 2 channels at reception Setup item Data output pin Serial unused pin Clock pin SBO1A pin SBO1B SBI1 SBT1A pin SBT1B pin pin Clock master Clock slave SC1SCMD1 SC1MST Port pin P1
510. own below Setup Procedure Description 1 Set the baud rate timer 1 Set the baud rate timer by the TM1MD register the TM10OC register Set TM1EN flag to 1 to start timer 1 Chapter 5 5 8 Serial Transfer Clock Output Operation 2 Select the clock source 2 Set the bp2 to 0 of the SCOMD3 register to 110 to SCOMD3 0x03F94 select Timer 1 output as a clock source bp2 0 SCOPSC2 0 110 3 Select the pin 3 Set the SCOSL flag of the SCSEL register to 0 to select SCSEL 0x03F90 A port A as I O pin SCOSL 0 4 Control the pin style 4 Set the PAODCO flag of the PAODC register to 1 to PAODC 0x03F2D select Nch open drain Set the PAPLUO flag of the bp0 PAODCO 1 PAPLU register to 1 to enable the pull up resistor PAPLU 0x03F4A 1 XI 60 Operation Chapter 11 Serial interface 0 Setup Procedure Description 5 Control the pin direction PADIR 0x03F3A PADIRO 1 bp1 PADIR1 0 6 Set the SCOMDO register Select the start condition SCOMDO 0xOSF91 bp3 SCOSTE 1 Select the first bit to be transferred SCOMDO 0x03F91 bp4 SCODIR 0 7 Set the SCOMD2 register Control the output data SCOMD2 0x03F93 SCOBRKE 0 Select the added parity bit SCOMD2 0x03F93 SCONPE 0 bp5 4 SCOPM1 0 00 Specify the flame mode SCOMD2 0x03F93 bp7 6 SCOFM1 0 11 8 Set the SCOMD1 register Select the communication type
511. p 0 1 3VLcD Light Light OFF Light OFF Light Light OFF S selected voltage N non selected voltage driver voltage XVI 30 Display Chapter 16 LCD XVI 31 Display 1 3Vicp 1 3Vicb 1 3 1 3Vicb Vict jj I 1 1 1 1 T 1 Cr 1 i 1 I 1 IL o 1 1 1 1 1 1 1 1 1 I I 1 1 1 1 1 1 1 1 1 1 i 1 io 1 EM 1 L 1 1 1 l 1 1 1 1 1 1 ie 1 1 LL L 3 TIU Sy 1 1 1 4 1 1 1 55 E 1 1 f 1 1 1 1 E o 1 1 i ee eH dee 2 Ei a O l 1 l LL 1 E m 1 1 1 1 1 1 I l TW 1 1 1 1 1 i 1 1 l 1 X 5 see Je ee A ee ee ae s cd us lu PEE MESES l l 2 1 SEG3 data A electrode COM3 SEG3 B electrode COM1 SEG3 Figure 16 4 4 LCD Display 1 4 duty Chapter 16 LCD 16 4 8 Setup Example 1 4 duty B a
512. p Segment output control H Segment output data VLC1 3 n LCD clock vite 3 2 8 Y Y 8 VL Y C3 i 4 5 LLL Y y Figure 4 6 6 Block Diagram P75 Atsegment output port I O direction control is forcefully set to input mode pull up resistor is disabled and segment output is executed by the segment output control Port 7 IV 63 Chapter 4 Ports D 4 Rege P7ODC6 gt Nch open drain control D D 2 P7DWN R Pull up pull down resistor selection oP yo R P7PLUD6 R Pull up pull down resistor control hi WA Reset P7DIR6 R EJ p Y direction control D gt WEK X m k MA P7OUT Port output data Q oume M 4 s ux i s I P7IN Schmitt trigger input Port input data lt Key interruptinput Serial 0 UARTO IIC4 reception data input IIC4 transmission data output SC4AD1 IICSEL LCD output control SET EN Segment output control ue 28 Segment output data VL
513. p Mnemonic Operation Flag VE NF CF ZF Size Re peat Machine Code 6 7 8 Notes 11 TBZ TBZ i08 bp label iltmem8ll0TOP ioBJbp 0 PC 7 d7 labeljsH PC if mem8 IOTOP i08 bp 1 PC 7 3PC 6 7 0100 Obp io8 gt d 1 TBZ i08 bp label imemB IOTOP io8Jop 0 PC 8 d abe PC 1 8 6 7 0011 0100 1bp io8 gt dii H 2 TBZ abs16 bp label if memB abs16 bp 0 PC 9 d7 label HPC if mem8 abs16 bp 1 PC 9 PC 7 8 0011 1110 Obp abs 16 gt d 1 TBZ abs16 bp label If memB abst6 op 0 PC 10 d1 label PC if mem8 abs16 bp 1 PC 10 PC 10 7 8 0011 1110 1bp abs 16 gt dii 2 TBNZ abs8 bp label if mem8 abs8 bp 1 PC 7 d7 label H PC if mem8 abs8 bp 0 PC 7 PC 6 7 0011 0001 Obp lt abs lt d7 5 ITBNZ abs8 bp label amp 58 1 8 11 if mem8 abs8 bp 0 PC 85PC 6 7 0011 0001 16 lt dii 2 TBNZ 8 if memB io bp 1 PC 7 d7 label HPC if mem8 io bp 0 PC 72PC 6 7 0011 0101 Obp io8 gt d 5 TBNZ io8 bp label TBNZ abs16 bp label if mem8io bp 1 PC 8 d1 1 label H gt
514. pin and the external interrupt block This external interrupt interface can manage to do with any kind of external interrupts 3 3 1 Overview 27 Table 3 3 1 shows the list of functions which external interrupts 0 to 2 and 4 are used Table 3 3 1 External Interrupt Functions External Programmab Both edges Noise filter AC zero Key input interrupt le active interrupt built in cross interrupt input pin edge detection External inter P54 O rupt 0 External inter P55 O rupt 1 External inter P56 O rupt 2 External inter O rupt 3 Because the external interrupt event and the AC zero cross is acknowledged by the rising of system clock the pulse which is shorter than the system clock cycle is neglected System clock x 2 for the interrupt factor generation is needed at the maximum against the Y external interrupt event from the pin because all synchronous circuits are inserted External Interrupts 41 Chapter 3 Interrupts Block Diagram 3 3 2 B External Interrupt 0 Interface Block Diagram JojsueJ ejeqg 1senbaij oO HI 31008 81004 uonoejep Buisiy 3900 5 uono l p yore gt gt snouoiugou S POSTAN
515. plication as a system controller in a camera timer selector for VCR CD player or MD With two oscillation system max 10 MHz 32 kHz contained on the chip the system clock can be switched to high frequency input high speed mode or to low frequency input low speed mode The system clock is generated by dividing the oscillation clock The best operation clock for the system can be selected by switching its frequency by software High speed mode has the normal mode which is based on 2 cycle clock fosc 2 and the double speed mode which is based on the same cycle clock with fosc A machine cycle min instructions execution in the normal mode is 250 ns when fosc is 8 MHz and when fosc is 10 MHz a machine cycle is 200 ns A machine cycle in the double speed mode is 125 ns when fosc is 8 MHz and 100 ns when fosc is 10 MHz Two types of packages are available 48 pin TQFP and 44 pin QFP 1 1 2 Product Summary _ ____________ ___________________________________ This manual describes the following models of the MN101C78 series These products have identical functions However MN101C78A is described mainly Table 1 1 1 Product Summary Model ROM Size RAM Size Classification MN101C78A 1 32 KB 1 5 KB Mask ROM version MN101C789 2 24 KB 1 5 KB Mask ROM version MN101CF78A 1 32 1 5 KB Flash EEPROM version 1 Under development 2 Under consideration 1 2 Overview Chapter 1 Overview 1 2 Hardwa
516. ply to the MN101CF784A on the target board Therefore the clock frequency of the MN101CF78A differs depending on each user The guaranteed clock frequency for the MN101CF78A during serial programming is shown below Frequency Operating voltage 10 MHz internal 5MHz 2 7 V to 3 6V 5 7 MHz internal 5 7MHz 3 0 V to 3 6 V 4 6 MHz internal 4 6 MHz 2 7 V to 3 6 V XVII 8 Onboard Serial Programming Mode Chapter 17 17 4 Special Function Registers List Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OxO3F00 RESERV OSCSEL OSESEL OSEDBL STOP HALT OSC1 0SCO 11 24 1 0 11 28 0 0 0 0 0 0 0 0 5 Division rate setup Internal STOP HALT Oscillation control always to system mode mode 0 clock setup setup 0x03F01 MEMCTR IOW1 IOWO IVBM Reserve Reserve IRWE Reserve Reserve 20 1 1 0 0 1 0 1 1 IO setup Interrupt Set Set Interrupt Set always to 11 base always always request address to 0 to 1 software writes 0 03 02 WDCTR Reserve Reserve Reserve WDTS1 WDTSO WDEN IX 4 d d d 0 0 0 1 1 0 Set always to 0 Watchdog timer Watchdo detection period g timer control 0x03F03 DLYCTR BUZOE BUZS2 BUZS1 BUZSO DLYS1 DLYSO 11 33 5 0 0 0 0 0 0 Buzzer Buzzer output frequency s
517. port P13 is used as I O pin of the timer 7 as well The output mode can be selected by bp3 of the port 1 output mode register PLOMD by each bit The of the port 1 output mode register PLOMD is set to 1 to output the special function data and 0 to use as the general port P14 is used as I O pin of the timer 0 and as output pin of the remote control carrier as well The output mode can be selected by bp4 of the port 1 output mode register PIOMD by each bit The bp4 of the port 1 output mode register is set to 1 to output the special function data and 0 to use as the general port P15 is used as the output pin of the timer 0 as well The output mode can be selected by bp5 of the port 1 output mode register P1OMD by each bit The of the port 1 output mode register P1OMD is set to 1 to output the special function data and 0 to use as the general port Port 1 IV 5 Chapter 4 Ports 6 P16 is used as I O pin of the timer 2 as well The output mode can be selected by bp6 of the port 1 output mode register PLOMD by each bit The bp6 of the port 1 output mode register PLOMD is set to 1 to output the special function data and 0 to use as the general port P17 is used as the output pin of the timer 0 as well The output mode can be selected by bp7 of the port 1 output mode register P1OMD by each bit The bp7 of the port 1 output mode register PIOMD
518. pt requests REDG2 Interrupt valid edge flag at the standby mode 0 Falling edge low level 1 Rising edge high level IRQ2IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQ2IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated 22 Control Registers Chapter 3 Interrupts External Interrupt 4 Control Register IRQ1ICR 0x03FE3 The external interrupt 4 control register IRQ4ICR controls interrupt level of external interrupt 4 valid edge interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable inter rupt enable flag MIE of PSW is 0 Table 3 2 6 External Interrupt 4 Control Register IRQ4ICR 0x03FE6 7 6 1 0 IRQ4LV1 IRQ4LVO IRQ4IE IRQ4IR 0 0 0 0 IRQ4LV1 IRQ4LVO Description Interrupt level flag The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interrupt requests IRQ4IE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQ4IR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers 23 Chapter 3 Interrupts Timer 0 Interrupt Control Register TMOICR The timer 0 interrupt control register TMOICR controls interrupt level of timer 0 interrupt interrupt enable flag and interrupt request Interrupt control register should
519. pter 15 A D Converter XV 2 15 1 Overview This LSI contains an A D converter with 10 bits resolutions It contains a built in sample hold circuit The chan nels 0 to 6 ANO to ANO of analog input can be switched by software When A D converter is stopped the power consumption can be reduced by turning the built in ladder resistance OFF A D conversion is activated by a register setup 1511 Functions nsn Table 15 1 1 shows the A D converter functions Table 15 1 1 A D Converter Functions A D Input Pins 7 pins Pins to ANO Interrupt ADIRQ Resolution 10 bits Conversion Time Min 24 5 us TAp as 800 ns Input range Vgs to VREF Power Consumption Built in Ladder Resistance ON OFF D conversion start flag is enabled and the instant when the actual analog signal is sampled a The conversion time shown in the above table does not include between the instant when A actual time is the conversion time plus 1 Tap Overview 15 1 2 Block Diagram Ji asa oE A D Converter Block Diagram Chapter 15 A D Converter ANCTR1 0 ANCTRO ANCTR2 IRQ2 P56 ANCHSO z P ANCHS1 Y ANCHS2 External I ANCKO int
520. ption of each step is shown below Setup Procedure Description 1 Specify the interrupt valid edge IRQOICR 0x03FE2 bp5 REDGO 1 2 Select the sampling clock 0x03F2E bp2 1 NFOSCK1 0 201 3 Set the noise filter operation 0x03F2E bpO NFOEN 1 4 Set the interrupt level IRQOICR 0x03FE2 bp7 6 IRQOLV1 0 10 5 Enable the interrupt IRQOICR 0x03FE2 bp1 IRQOIE 21 Above 2 and 3 can be set at the same time 1 Set the REDGO flag of the external interrupt O control register IRQOICR to 1 to specify the interrupt valid edge to the rising edge 2 Select the sampling clock to fosc 2 by the NFOSCK1 to 0 flag of the noise filter control register NFCTR 3 Set the NFOEN flag of the NFCTR register to 1 to add the noise filter operation 4 Set the interrupt level by the IRQOLV1 to 0 flag of the IRQOICR register If the interrupt request flag has been already set clear the request flag Chapter 3 3 1 4 Interrupt Flag Setup b Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt The input signal from P54 pin outputs the interrupt factor at the edge that is followed to the programmable active edge after passing through the noise filter a The noise filter should be setup before the interrupt is enabled The external interrupt pins are recommended to be pull up in advance 58 External Interrupts Chapter
521. put edge to falling 9 Set the SC3CMD flag of the SC3CTR register to 0 to select synchronous serial interface 10 Set the SC3MST flag of the SC3MD1 register to 0 to select clock slave external clock 11 Set the SC3SBOS flags of the SC3MD 1 register to 0 SC3SBIS SC3SBTS flags to 1 to set the 5803 pin to general port the SBI3 pin to serial data input and the SBT3 to serial clock I O Set the SC3IOM flag to 0 to set serial data input from the SBIS pin 12 Set the interrupt level to level 2 by SC3LV1 0 flags of the serial 3 interrupt control register SC3ICR 13 Set the SCSIE flag of the SC3ICR register to 1 to enable the interrupt If the interrupt request flag SC3IR of the SC3ICR register is already set clear SC3IR before the interrupt is enabled Chapter 3 3 1 4 Interrupt Flag Setup 14 Set dummy data to the serial transmission data buffer 15 Set the STOP flag of the CPUM register to 1 for transition to STOP mode 16 Set the transfer clock to SBT3 pin and transfer data to 5813 pin Operation XIII 35 Chapter 13 Serial Interface 3 XIII 36 Setup Procedure Description 17 Return from STANDBY mode 17 Serial 3 interrupt SC3IRQ is generated at the same time of reception of the 8 bits data and then CPU returns from STOP mode to NORMAL mode after oscillation stabilization wait time Note Procedures 5 to
522. put register is read to be 1 5 is used as input pin for analog as well Each bit can be set individually as an input by the port A input mode register PAIMD When it is used as analog input pin set the port A input mode register to 1 Then the value of the port A input register is read to be 1 PA6 is used as input pin for analog as well Each bit can be set individually as an input by the port A input mode register PAIMD When it is used as analog input pin set the port input mode register to 1 Then the value of the port A input register is read to be 1 Serial 0 I O pin can be selected to either PAO to PA2 or P75 to P77 When the SCOSL flag of the serial selection register SCSEL is set to 0 to PA2 are selected to 1 P75 to P77 are selected For serial 1 I O pin either P15 to P17 or 4 to PA6 can be selected by setting the serial selection register SCSEL When the SCISL flag of the serial selection register SCSEL is set to 0 for P15 to P17 to 1 for 4 to PA6 Port A IV 78 Chapter 4 Ports IV 74 4 8 2 Registers un TT Im ImTa Y n Table 4 8 1 shows the registers that control the port A Table 4 8 1 Port A Output Control Register Registers Address Function Page PAOUT Ox03F1A Port A output register IV 74 PAIN 2 Port A input register PADIR Port A direction control register PAPLUD Ox03F4A Port A pu
523. quipment measuring instruments and household appliances Consult our sales staff in advance for information on the following applications Special applications such as for airplanes aerospace automobiles traffic control equipment combustion equipment life support systems and safety devices in which exceptional quality and reliability are required or if the failure or malfunction of the products may directly jeopardize life or harm the human body Any applications other than the standard applications intended The products and product specifications described in this book are subject to change without notice for modification and or improvement At the final stage of your design purchasing or use of the products therefore ask for the most up to date Product Standards in advance to make sure that the latest specifications satisfy your requirements When designing your equipment comply with the guaranteed values in particular those of maximum rating the range of operating power supply voltage and heat radiation characteristics Otherwise we will not be liable for any defect which may arise later in your equipment Even when the products are used within the guaranteed values take into the consideration of incidence of break down and failure mode possible to occur to semiconductor products Measures on the systems such as redundant design arresting the spread of fire or preventing glitch are recommended in order to prevent physical i
524. r Chapter 7 Time Base Timer Free running Timer Count Timing of Timer Operation Timer 6 Binary counter counts up with the selected clock source as a count clock Count clock TM6CLRS flag Compare register Binary counter Interrupt request flag Figure 7 3 2 Count Timing of Timer Operation Timer 6 1 When any data is written to the compare register as the TM6CLRS flag is 0 the binary counter is cleared to 0x00 2 Even if any data is written to the compare register as the TM6CLRS flag is 1 the binary counter is not changed 3 When the binary counter reaches the value of the compare register as the TM6CLRS flag is 1 an interrupt request flag is set at the next count clock 4 When an interrupt request flag is set the binary counter is cleared to 0x00 and restarts the counting 5 Even if the binary counter reaches the value of the compare register as the TM6CLRS flag is 0 no interrupt request flag is set 8 bit Free running Timer VII 11 Chapter 7 Time Base Timer Free running Timer When the binary counter reaches the value in the compare register the interrupt request flag is set and the binary counter is cleared at the next count clock So set the compare register as Compare register setting count till the interrupt request 1 q If the fx input is selected as a clock source and the value of 6 binary counter is read out at operation an i
525. r count clock source and the value of the timer n binary counter is read out during operation incorrect value at count up may be read out To prevent this use the event count by synchronous TMnIO input as the following page Hu When the event input input is used clear the binary count before the timer opera tion Also when 0x00 is set to the compare register use the event count by the synchronous TMnIO input as the following page Timer can be recovered from STOP mode only the TMnIO input When TMnIO input is used at STOP mode fs should be selected for the count clock and set the value to TMnOC then select TMnIO input lt When the event input TMnIO is selected as the count clock source and the compare regis ter is rewritten during the timer operation the operation of the corresponding cycle to the value cannot be guaranteed during the transition period For proper timer operation with an expected cycle stop the timer rewrite the compare register then start the timer operation 8 bit Event Count V 27 Chapter 5 8 bit Timers Count Timing of Synchronous TMnIO Input Timer 0 1 2 3 If the synchronous TMnIO input is selected the synchronous circuit output signal is inputted to the timer n count clock The synchronous circuit output signal is synchronization with the falling edge of the system clock derived the TMnIO input signal TMnIO Input N N N N N u gt
526. r matches the set slave address Data transmission reception are controlled with the WRS flag of the SCASTR register and slave trans mission is selected when the WRS flag is set to 0 slave reception is selected when the WRS flag is set to 1 In slave transmission setting the transmission data to SCATXB register opens the bus line and data transmission is started by the clock transmitted from master In slave reception setting the dummy data to SC4RXB register opens the bus line and data reception is started by the clock transmitted from master Start Re Start Condition Detection When data SDA pin changes from to L while clock SCL pin is H start condition is detected and the STRT flag of the SCASTR register is set to 1 The STRT flag is cleared to 0 after communication data is set when the interrupt routine right after the slave address reception sets the communication data If start condition is detected again during data transfer the RSTRT flag is set This flag is cleared to after communication data is set when the interrupt routine right after the slave address reception sets the communication data If address trans mitted from master does not match the slave address these flags are automatically cleared at the timing when address miscompare is detected B Busy Flag This serial interface contains 2 busy flags SLVBSY I2CBSY The SLVBSY flag is set to 1 when address transmitted from master matches the slave a
527. re Functions B Functions ROM capacity RAM capacity 32768x8 bit 1 1536x8 bit 1 1 Differs depending upon the model Refer to Chapter 1 1 1 2 Product Summary Package Machine cycle QFP44 10 mm square 0 8 mm pitch TQFP48 7 mm square 0 5 mm pitch High speed mode lt fs fosc 2 fosc 1 gt 0 125 ms 8 MHz 2 7 V to 3 6 V 0 25 ms 8 MHz 4 MHz 2 3 V to 3 6 V 2 0 50 ms 4 MHz 2 MHz 1 8 V to 3 6 V 2 Low speed mode lt fs fx 2 gt 62 5 ms 32 kHz 1 8 V to 3 6 V 2 2 The guaranteed operating range for Flash EEPROM version MN1010CF78A is 2 7 V to 3 6 V Internal clock gear Oscillating circuit Operation modes Operating voltage Operating temperature Interrupt External interrupts gt Operation speed of internal system clock is variable by changing the frequency 2 4 16 32 64 128 dividing Two oscillation circuits high speed low speed NORMAL mode SLOW mode HALT mode STOP mode The operation clock can be switched in each model 1 8 V to 3 6 V Flash version of TQFP48 MN101CF78A is 2 7 V to 3 6 V 40 C to 85 C 22 levels Edge selectable IRQO External interrupt AC zero cross detector With Without noise filter IRQ1 External interrupt AC zero cross detector With Without noise filter IRQ2 External interrupt Both edges selectable IRQ3 external interrupt IRQ3 Key scan interrupt only Hardware Functions 1 3 Chapter 1
528. re registers 1 2 at the timing that the timer 8 binary counter is cleared Timer 8 Preset Register 1 TM8PR1 Table 6 2 21 Timer 8 Preset Register 1 Lower 8 bits TM8PR1L 0x03F84 bp 7 6 5 4 3 2 1 0 Flag TM8PR1L TM8PR1L TM8PR1L TM8PR1L TM8PRiL TM8PR1L 8 TM8PRiL 7 6 5 4 3 2 1 0 At reset X X X Access RAN Table 6 2 22 Timer 8 Preset Register 1 Upper 8 bits TM8PR1H 0x03F85 7 6 5 4 3 2 1 0 TM8PR1 H7 TM8PR1 H6 TM8PR1 H5 TM8PR1 H4 TM8PR1 H3 TM8PR1 H2 TM8PR1H 1 TM8PR1 HO X X X X X X X X Timer 8 Preset Register 2 TM8PR2 Table 6 2 23 Timer 8 Preset Register 2 Lower 8 bits TM8PR2L 0x03F8C 7 6 5 4 3 2 1 0 TM8PR2L 7 TM8PR2L 6 TM8PR2L 5 TM8PR2L 4 TM8PR2L 3 TM8PR2L 2 TM8PR2L 1 TM8PR2L 0 X X X X X X X X 7 6 5 4 3 2 1 0 TM8PR2 H7 TM8PR2 H6 TM8PR2 H5 TM8PR2 H4 TM8PR2 H3 TM8PR2 H2 TM8PR2H 1 TM8PR2 HO X X X X X X X X Control Registers Chapter 6 16 bit Timers Binary counter is a 16 bit up counter If any data is written to a preset register when the counting is stopped the binary counter is cleared to 0x0000 During the timer counting
529. rea ROM space Chapter 2 CPU Basics 2 1 9 X Addressing Modes B s This LSI supports the nine addressing modes Each instruction uses a combination of the following addressing 1 Register direct 2 Immediate 3 Register indirect 4 Register relative indirect 5 Stack relative indirect 6 Absolute 7 RAM short 8 I O short 9 Handy These addressing modes are well suited for C language compilers All of the addressing modes can be used for data transfer instructions In modes that allow half byte addressing the relative value can be specified in half byte 4 bit increments so that instruction length can be shorter Handy addressing reuses the last memory address accessed and is only available with the MOV and MOVW instructions Combining handy addressing with abso lute addressing reduces code size For transfer data between memory 8 addressing modes register indirect regis ter relative indirect stack relative indirect absolute RAM short I O short handy can be used For operation instruction register direct and immediate can be used Refer to instruction s manual for the MNIOIC series This LSI is designed for 8 bit data access It is possible to transfer data in 16 bit increments with odd or all even addresses Overview 13 Chapter 2 CPU Basics Il 14 Effective address Addressing mode Dn DWn An SP PSW imm4 imm8 imm16 Register direct Immediate Register in
530. recision IGBT Output When the compare register 2 is X 0000 VI 58 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively Chapter 6 16 bit Timers When the TM7EN flag is set to 0 stop status and the T7IGBTDT of the TM7MD3 register is set to 0 both 7 and TMSIO output L Count Timing of High Precision IGBT Output When compare register 2 compare register 1 Timer 7 The following shows the count timing when the value of the compare register 1 is set to the compare register 2 C LFU TM7EN Flag Compare 3 I N Register i H H i Compare Register 2 i i i i i i i amy Counter ggg X ono X X N oon TM71O output IGBT output 8 output IGBT output Figure 6 9 3 Count Timing of High Precision IGBT Output When compare register 2 compare register 1 For high precision IGBT output set the TM7BCR flag of the TM7MD 2 register to 1 and select TM7OC1 compare match as the binary counter clear factor and IGBT output set H output factor Also set the T7PWMSL flag of the TM7MD2 register to 1 and select the TM7OC2 compare match as the IGBT output reset L output factor In the initial state of the IGBT output TM71O when the IGBT output is selected by the T7IGBTEN of the TM7MDS register it is L output After the trigger is input it changes to H at the second cycle
531. register is initiated the P20UT7 flag becomes 1 and reset is released enough low level time at sudden unconnected And reset can be generated even if NRST pin a When NRST pin is connected to low power voltage detection circuit that gives pulse for is held low for less than OSC 4 clock cycles take notice of noise 30 Reset Chapter 2 CPU Basics Sequence at Reset 1 When reset pin comes to high level from low level the internal 14 bit counter It can be used as watchdog timer too starts its operation by system clock The period from starting its count from its overflow is called oscillation stabilization wait time 2 During reset internal register and special function register are initiated 3 After oscillation stabilization wait time internal reset is released and program is started from the address writ ten at address 0x4000 at interrupt rector table VDD NRST OSC2 XO Internal RST Oscillation stabilization wait time Figure 2 6 2 Reset Released Sequence Reset 31 Chapter 2 CPU Basics II 32 2 6 2 Oscillation Stabilization Wait time Oscillation stabilization wait time is the period from the stop of oscillation circuit to the stabilization for oscilla tion Oscillation stabilization wait time is automatically inserted at releasing from reset and at recovering from STOP mode At recovering from STOP mode the oscillation stabili
532. register to 1 to select duplex UART Set the SC1CKM flag of the SC1MD1 register to 1 to select divided at source clock Set the SC1DIV flag to 0 to select divided by 8 as source clock The SC1MST flag should always be set to 1 to select clock master Set the SC1SBOS SC1SBIS of the SC1MD1 register to 1 to set the RXD1 pin to serial data output and the RXD1 pin to serial data input 9 Set the SC1RIE flag of the SC1RICR register to 1 and SCITIE flag of the SC1TICR register to 1 to enable the interrupt request If the interrupt request is already set clear it Operation Chapter 12 Serial interface 1 Setup Procedure Description 10 Start the serial transmission 10 When the transmission data is set to the serial The transmission TXBUF1 0x03F9F transmission data buffer TXBUF1 the transmission is The reception data input to RXD1 started When the transmission is finished the serial 1 transmission interrupt SC1TIRQ is generated Also after the received data is stored to the RXBUF1 the serial 1 reception interrupt SC1RIRQ is generated Note 6 7 8 can be set at the same time When the TXD1 RXD1 pin are connected for communication with 1 channel serial data is input output from the TXD1 pin Input output can be switched by the port direction control register P1DIR At reception set SC1SBIOS of the SC1MD1 register to 1 to select serial data input
533. rescaler Prescaler 0 outputs fosc 4 fosc 16 fosc 32 fosc 64 fosc 128 Prescaler outputs fs 2 fs 4 fs 8 Fosc or fs can be selected as the clock source for each timer by using the prescaler Overview 5 1 1 Functions Chapter 5 8 bit Timers Table 5 1 1 shows functions that can be used with each timer Table 5 1 1 Timer Functions Timer 0 Timer 1 Timer 2 Timer 3 8 bit 8 bit 8 bit 8 bit Interrupt source TMOIRQ TM1IRQ TM2IRQ TMSIRQ Timer operation O O Event count TMOIO input TM1IO input 21 input TMSIO input P14 P70 P16 P71 Timer pulse output TMOIO output TM11O output 21 output TMSIO output P14 P70 P16 P71 PWM output TMOIO output pin 21 output pin P14 P16 Additional pulse method PWM output Timer output to TMOOA output pin 2 output large current pin 5 52 Serial transfer Serial 0 Serial 0 2 Serial 2 clock output Pulse width External interrupt O External interrupt 2 measurement P54 IRQO P56 IRQ2 Cascade connection Clock source fosc fosc fosc fosc fosc 4 fosc 4 fosc 4 fosc 4 fosc 16 fosc 16 fosc 16 fosc 16 fosc 32 fosc 64 fosc 32 fosc 64 fosc 64 fosc 128 fosc 64 fosc 128 fs 2 fs 2 fs 2 fs 2 fs 4 fs 8 fs 4 fs 8 fx fx fx fx TMOIO input TM11O input 210 input TMSIO input fosc Machine clock High frequency oscillation fx Machine clock Low freque
534. rial Interface Pin Setup with 2 channels at transmission reception Setup item Data output pin Data input pin TXDO pin RXDO pin Port pin 75 1 76 Port pin setup Select pin A B PAPLU PAPLUO P7PLU P7PLUS SCSEL SCOSL Serial data input selection RXDO SCOMD1 SCOIOM Function Serial data output Serial data input SCOMD1 SCOSBOS SCOMD1 SCOSBIS Style Push pull N ch open drain PAODC PAODCO P7ODC P7ODC5 y o Output mode Input mode PADIR PADIRO P7DIR P7DIR5 PADIR PADIR1 P7DIR P7DIR6 Pull up setup Added not added Operation XI 59 Chapter 11 Serial interface 0 11 3 4 Setup Example aa B Transmission Reception Setup The setup example for UART transmission reception with serial 0 is shown Table 11 3 29 shows the condition at transmission reception Table 11 3 29 UART Interface Transmission Reception Setup Setup item SEt to TXDO RXDO pin Independent with 2 channels Frame mode specification 8 bits 2 stop bits First transfer bit MSB Clock source Timer 1 Clock source dividing Divided by 8 Pin A port A TXDO RXDO pin type N ch open drain Pull up resistor of TXDO pin Added Parity bit add check 0 added check Serial 0 transmission complete Enable interrupt Serial 0 reception complete interrupt Enable An example setup procedure with a description of each step is sh
535. rigger should be set more than 2 cycles of the clock which is set the TMnCKSMP of the TMnMD3 register a Capture trigger signals of the 16 bit timers 7 and 8 are generated by sampling the rising edge If the capture clock frequency is longer against the system clock the value of the capture Y register may be read out before capturing VI 50 16 bit Timer Capture Chapter 6 16 bit Timers Capture Count Timing as Both Edges of External Interrupt Signal is selected as Trigger Timer 7 Timer 8 Count clock fs E A TN TMnEN flag Compare register Binary oc 0001 011140112 45555 5556 55575558 ZoOU counter Externa s O 1 0 _ interrupr m input signal Capture trigger synchronous to fs Capture 0000 0111 0114 5555 5558 register Figure 6 8 1 Capture Count Timing as External Interrupt Signal is selected as Trigger Timer 7 Timer 8 T A capture trigger is generated at the both edges of the external interrupt m input signal In synchronized with this capture trigger the value of binary counter is loaded to the input capture register The value loaded to the capture register is depending on the value of the binary counter at the falling edge of the capture trigger When the speci fied edge is selected as the capture trigger source the capture trigger is generated only at that edge
536. roduct download_impress htm Onboard Serial Programming Mode XVII 5 Chapter 17 Appendix XVII 6 17 3 2 Circuit Requirements for the Target Board VDDffor level detection 10 KQ Microcontroller O Wrst Serial 2 7 V to 3 6 V Writer Target Board Figure 17 3 1 Circuit Requirements for the Target Board Pins 8 23 pin 2 7V to 3 6V power supply NRST 12 pin Reset SBTOB 40 pin Serial interface clock supply pin SBOOB 38 pin Serial interface data input pin GND 5 pin Ground P76 39 pin Busy signal output pin MMOD 11 pin MMOD pin Low at user mode High at on board programming Vpp2 should be 2 7 lt lt 3 6 When Vpp level 2 7V to 3 6V is too low serial writer generates error message Connect pull up resistors to NRST MMOD SBTOB and P76 pins on the target board The pull up resistor value should be 10 1 Design NRST and MMOD to be able to toggle by a switch between serial writer programming and normal opera tion Alternatively install a wired OR connection For a wired OR connection disable NRST and MMOD from the target board during serial writer programming NRST is output from the serial writer through an open drain To prevent the other user circuits on the target board from communicating the circuit of the target board should be designed for SBTOO SBOOB and P76 pins to communicate with the serial writer
537. rol of pin type 3 Set the PSODC2 P30DC3 flags of the P3ODC register PSODC 0x03F3B to 1 1 to select N ch open drain for the SBO3 SBT3 bp2 2 1 pin type Set the PSODC2 flags of the bp3 1 register to 1 1 to add pull up resistor 0x03F43 bp2 P3PLU2 1 bp3 P3PLU3 1 28 Operation Chapter 13 Serial Interface 3 Setup Procedure Description 4 Control of pin direction PSDIR 0 0 bp2 P3DIR2 1 bp1 P3DIR1 0 bp3 P3DIR3 1 5 Set the SC3MDO register Select the transfer bit count SC3MDO 0x03FA0 bp2 0 SC3LNG2 0 111 Select the start condition SC3MDO 0x03FA0 bp3 SC3STE 0 Select the first bit to be transferred SC3MDO 0x03FA0 bp4 SC3DIR 0 Select the transfer edge SC3MDO 0x03FA0 bp6 SC3CE1 1 6 Set the SC3CTR register SC3CTR 0x03FA6 bp2 SC3CMD 0 7 Set the SC3MD1 register Select the transfer clock SC3MD1 0x03FA1 bp2 SC3MST 1 Control of pin function SC3MD1 0x03FA1 bp4 SC3SBOS 1 bp5 SC3SBIS 1 bp6 SC3SBTS 1 bp7 SC3IOM 0 8 Set the interrupt level SC3ICR 0 0 bp7 6 SC3LV1 0 10 9 Enable the interrupt SC3ICR SCSIE 1 bp0 SCSIR 0 10 Start serial transmission Reception data Input to 5813 pin Transmission data TXBUF3 0x03FA5 4 Set the P3DIR2 P3DIR3 flags of the Port pin control direction re
538. rrupt generation sources and the flags that control the timer pulse output cycle Table 6 5 2 16 bit Timer Interrupt Generation Source and Timer Pulse Output Cycle Timer 7 Timer 8 TM7MD2 register Interrupt source Timer pulse output cycle TM7IRS1 flag TM7BCR flag 1 1 TM7OC1 compare match Set value of TM7OC1 x2 0 1 TM7OC1 compare match Set value of TM7OC1 x2 1 0 TM7OC1 compare match Full count of TM7BC 2 0 0 Full count over flow Full count of TM7BC 2 TM8MD 2 register Interrupt source Timer pulse output cycle TMB8IRS1 flag TM8BCR flag 1 1 TM8OC1 compare match Set value of TM8OC1 x2 0 1 TM8OC1 compare match Set value of TM8OC1 x2 1 0 TM8OC1 compare match Full count of TM8BC x 2 0 0 Full count over flow Full count of TM8BC 2 16 bit Timer Pulse Output VI 35 Chapter 6 16 bit Timers TMnlO input TMnEN flag Compare register 1 Binary 0000 0001 0002 ONES 0000 0001 counter Interrupt request flag TMnIO output oun Figure 6 5 1 Count Timing of Timer Pulse Output Timer 7 Timer 8 TMnIO output pin outputs 2 x cycle compared with the value of the compare register If the binary counter reaches the compare value or full count overflow is occurred the binary counter is cleared to 0x0000 and the TMnIO output timer output is inverted In the initial state after releasing reset the timer pulse output is reset and low output is fixed Therefore
539. rrupts Ill 49 Chapter 3 Interrupts Key Interrupt Control Register 1 KEYT3_1IMD The key interrupt control register 1 selects if key interrupt is accepted Also this register assigns KEY input to key interrupt in 2 bit unit Table 3 3 6 Key Interrupt Control Register 1 KEYT3_1IMD 0x03F3E bp 7 6 5 4 3 2 1 0 Flag KEYTSSE 1 1 KEYT3 1 1 L EN2 EN1 ENO At reset 0 0 0 0 0 Access R W KEYTSSEL Description Key interrupt control 0 Key interrupt disable 1 Key interrupt enable KEYT3_1EN3 KEYS interrupt selection 0 Disable 1 Enable KEYT3_1EN2 KEY2 interrupt selection 0 Disable 1 Enable KEYT3_1EN1 KEY 1 interrupt selection 0 Disable 1 Enable III 50 KEYT3_1ENO External Interrupts interrupt selection 0 Disable 1 Enable Chapter 3 Interrupts B Key Interrupt Control Register 2 KEYT3_2IMD The key interrupt control register 2 assigns KEY input to key interrupt in 1 bit unit Table 3 3 7 Key Interrupt Control Register 2 KEYT3_2IMD 0x03F3F 3 2 1 0 KEYT3 2 KEYT3 2 2 KEYT3 2 EN3 EN2 EN1 ENO 0 0 0 0 Description 2bNS3 7 interrupt selection 0 Disable 1 Enable 2bN2 KEY6 interrupt selection 0 Disable 1 Enable 2 1 KEY5 interrupt selection 0 Disable 1 Enable
540. rs remain operational in HALTO and only the high frequency oscillator stops operating in HALTI An interrupt returns the CPU to the previous CPU operating mode that is to NORMAL from or to SLOW from HALTI STOP Modes STOPO STOP1 The CPU and both of the oscillators stop operating An interrupt restarts the oscillators and after allowing time for them to stabilize returns the CPU to the previous CPU operating mode that is to NORMAL from STOPO or to SLOW from STOPI B SLOW Mode This mode executes the software using the low frequency clock Since the high frequency oscillator is turned off the device consumes less power while executing the software IDLE Mode This mode allows time for the high frequency oscillator to stabilize when the software is changing from SLOW to NORMAL mode To reduce power dissipation in STOP and HALT modes it is necessary to check the stability of both the output current from pins and port level of input pins For output pins the output level should match the external level or direction control should be changed to input mode For input pins the external level should be fixed This LSI has two system clock oscillation circuits OSC is for high frequency operation NORMAL mode and XI is for low frequency operation SLOW mode Transition between NORMAL and SLOW modes or to standby mode is controlled by the CPU mode control register CPUM Reset and interrupts are the return factors from
541. rt I O port Timer 2B Timer 2B Timer 0B Timer 0 Timer 7 NBUZZE Timer 8 BUZZER output output output remote output output output selection selection selection selection control selection selection selection output selection 0x03F1D P7ODC P770DC P76ODC P75ODC 54 0 0 0 77 P76 P75 open open open drain drain drain control control control XVII 10 Special Function Registers List Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Ox03F1E EDGDT EDGSEL 49 1 2 m 0 IRQ2 both edges interrupt opera tion setup OxO3F1F CLKOUT SCHMIT PDOWN CLKSEL OUTEN IV 13 T 0 0 0 0 Switch Clock Clock Clock port output type output input function selection enable level 0x03F21 P1IN7 P1IN6 P1IN5 1 P1IN2 P1IN1 P11NO 8 x x x x x x 1 1 Port 1 input data 0x03F23 P3IN P3IN7 P3IN6 P3IN5 P3IN4 P3IN3 P3IN2 P3IN1 P3IN0 IV 27 1 x x x x x x x Port 3 input data OxO3F25 P5IN 6 5 4 2 P5INO 42 x x x x x x x Port 5 input data OxO3F27 P7IN P7IN7 P7IN6 P7IN5 P7IN4 P7IN3 P7IN2 P7IN1 P7INO 52 x x x x x x x x Port 7 input data 0x03F29 P9IN P9IN0 IV 68 Port 9 input data
542. ruction decoder Instruction Interrupt queue controller Program address 1 1 Operand address Interrupt bus Y 1 Bus controller 1 1 1 ROM bus 4 RAM bus expansion bus Y Y Y Internal ROM External interface Internal peripheral functions Internal RAM expansion Y i Figure 2 1 1 CPU Block Diagram Table 2 1 2 Block Diagram and Function Clock generator Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals to CPU blocks Program counter Generates addresses for the instructions to be inserted into the instruction queue Normally incremented by sequencer indication but may be set to branch destination address or ALU operation result when branch instructions or interrupts occur Instruction queue Stores up to 2 bytes of pre fetched instructions Instruction decoder Decodes the instruction queue sequentially generates the control signals needed for instruction execution and executes the instruction by controlling the blocks within the chip Instruction execution controller Controls CPU block operations in response to the result decoded by the instruction decoder and interrupt requests ALU Executes arithmetic operations logic op
543. rupt request flag SCOTIR of the SCOTICR register is already set clear SCOTIR before the interrupt is enabled 15 Set the dummy data to the serial transmission data buffer TXBUFO Operation XI 41 Chapter 11 Serial interface 0 Setup Procedure Description 16 Transfer to STOP mode 16 Set the STOP flag of the CPUM register to 1 to CPUM 0x03F00 transfer to the stop mode bp3 STOP 1 17 Start the serial communication 17 Input the transfer clock to the SBTO pin and transfer Transmission clock input SBTO pin data to the SBIO pin Received data input SBIO pin 18 Recover from the standby mode 18 The serial 0 UART transmission interrupt SCOTIRQ is generated at the same time of the 8 bits data reception then CPU is recovered from the stop mode to the normal mode after the oscillation stabilization wait Note Procedures 1 2 6 to 9 10 to 12 13 to 14 can be set at the same time Each flag should be set as this setup procedure in order Activation of communication should Y be operated after all control registers refer to Table 11 2 1 except TXBUFO are set XI 42 Operation 11 33 UART Serial Interface Chapter 11 Serial interface 0 Serial 0 can be used for duplex UART communication Table 11 3 15 shows UART serial interface functions Table 11 3 15 URAT Serial Interface Functions Communication style UART duplex j Interrupt SCOTIRQ tra
544. rupt request generated Control Registers Ill 37 Chapter 3 Interrupts Serial 4 Interrupt Control Register SCAICR The serial 4 interrupt control register SCAICR controls interrupt level of serial 4 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 21 Serial 4 Interrupt Control Register SC4ICR 0x03FF5 7 6 SCALV1 SCALVO 0 0 Description SC4LV1 Interrupt level flag SC4LVO This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to interrupt requests Interrupt enable flag 0 Disable interrupt 1 Enable interrupt Interrupt request flag 0 No interrupt request 1 Interrupt request generated 38 Control Registers Chapter 3 Interrupts Timer 8 Interrupt Control Register TM8ICR The timer 8 interrupt control register TM8ICR controls interrupt level of timer 8 interrupt interrupt enable flag and interrupt request Interrupt control register should be operated when the maskable interrupt enable flag MIE of PSW is 0 Table 3 2 22 Timer 8 Interrupt Control Register TM8ICR 0x03FF6 7 6 TM8LV1 TM8LVO 0 0 TM8LV1 TM8LVO Description Interrupt level flag This 2 bit flag sets the interrupt level by assigning an interrupt level of 0 to 3 to
545. ry Select no wait cycle for high performance system construction 20 Bus Interface 2 4 Standby Function 2 4 1 Overview This LSI has two sets of system clock oscillator high speed oscillation low speed oscillation for two CPU oper ating modes NORMAL and SLOW each with two standby modes HALT and STOP Power consumption can be decreased with using those modes CPU operation mode Chapter 2 CPU Basics STANDBY mode Wait period for oscillation stabilization is inserted OSC XI Low frequency oscillation clock 32 kHz Interrupt NORMAL mode 3 Program 5 NORMAL Reset OSC Oscillation XI Oscillation P EOSC Oscillation3 XI Oscillation 3 Program 4 Program 3 STOP mode IDLE OSC Oscillation i Program 1 HALT mode Program 2 Interrupt STOPT 1 OSC Halt SLOW XI Oscillation OSC Halt Program 5 XI Oscillation Interrupt SLOW mode E OSC Halt XI Oscillation 3 Program 4 Figure 2 4 1 Transition Between Operation Modes igh frequency oscillation clock Standby Function Il 21 Chapter 2 CPU Basics 22 HALT Modes HALT1 The CPU stops operating But both of the oscillato
546. s 8 bits Set the SC1STE flag of the SC1MDO register to 0 to disable the start condition Set the SC1DIR flag of the SC1MDO register to 0 to set MSB as a transfer first bit Set the SC1CE1 flag of the SC1MDO register to 1 to set the reception data input edge falling and the transmission data output edge rising 8 Set the SC1CMD flag of the SC1MD1 register to 0 to select the synchronous serial Set the SC1MST flag of the SC1MD1 register to 0 to select the clock slave external clock Set the SC1CKM flag to 0 to select not divided for the clock source Set the SC1SBOS SC1SBIS SC1SBTS flag of the SC1MD1 register to 1 to set the SBO1 pin to the serial data output the SBI1 pin to the serial input SBT1 pin to the transfer clock input output Set the SC1IOM flag to set the serial data input from the SBI1 pin 9 Set the interrupt level by the SC1TLV1 to 0 flag of the serial 1 transmission interrupt control register SC1TICR 10 Set the SC1TIE flag of the SC1TICR register to 1 to enable the interrupt If any interrupt request flag SC1TIR of the SC1TICR register is already set clear SC1TIR before the interrupt is enabled 11 Set the transmission data to the serial dummy data buffer TXBUF1 After the dummy data is set when clock input is done after more than 3 5 transfer clock reception is started When reception is finished the serial 1 UART transmission interrupt SC1TIRQ is generated
547. s are NOP executed Insert three NOP instructions right after the instruction of the transition to HALT STOP mode a Set of XSEL register before changing to the low speed oscillation mode Standby Function 27 Chapter 2 CPU Basics 2 5 Clock Switching This LSI can select the best operation clock for system by switching clock cycle division factor by program Divi sion factor is determined by both flags of the CPU mode control register CPUM and the Oscillator frequency control register OSCMD At the highest frequency CPU can be operated in the same clock cycle to the external clock hence providing wider operating frequency range B CPU Mode Control Register CPUM Table 2 5 1 CPU Mode Control Register CPUM 0x03F00 7 6 5 4 RESERV OSCSEL1 OSCSELO OSCDBL ED 0 Description RESERVED Set always to 0 Clock Frequency 00 1 OSCSEL1 OSCSELO Internal System Clock OSCDBL 0 Standard Input the oscillation clock cycle divided by 2 1 2 Input the oscillation clock cycle See Figure 2 4 2 for setup of bp3 0 flags of the CPU mode control register CPUM 28 Clock Switching High speed oscillation Low speed oscillation 0 fosc fx Chapter 2 CPU Basics 3 OSC1 gt 001 Dividing counter 2 dividing p 000 4 dividing 011 8 dividing 010 16 dividing
548. s to be selected to clear the binary counter the TMnOCI compare match and the full count overflow After the binary counter is cleared the counting up is restarted from 0x0000 Table 6 3 1 16 bit Timer Interrupt Source and Binary Counter Clear Source Timer 7 Timer 8 TM7MD 2 register Interrupt source Binary counter clear source TM7IRS1 flag TM7BCR flag 1 1 TM7OC1 compare match TM7OC1 compare match 0 1 TM7OC1 compare match TM7OC1 compare match 1 0 TM7OC1 compare match Full count overflow 0 0 Full count overflow Full count overflow TM8MD 2 register Interrupt source Binary counter clear source TMB8IRS1 flag TM8BCR flag 1 1 TM8OC1 compare match TM8OC1 compare match 0 1 TM8OC1 compare match TM8OC1 compare match 1 0 TM8OC1 compare match Full count overflow 0 0 Full count overflow Full count overflow Timer n can generate another set of an independent interrupt timer n compare register 2 match interrupt by the set value of the timer n compare register 2 TMnOC2 At the time of the interrupt the binary counter is cleared as the above setup The compare register is double buffer type So when the value of the preset registers is changed during the count ing the changed value is stored to the compare register when the binary counter is cleared This function can change the compare register value constantly without disturbing the cycle during timer operation Reload func tion Operatio
549. s16 Dm MOVW abs16 Am MOVW abs16 DWm 8 Dm d12 MOVW An DWm MOV Dn abs16 MOVW An abs16 MOVW DWn abs16 CBNE 8 Dm d12 CBEQ 8 abs8 d7 d11 8 abs8 d7 d11 MOVW d16 SP Am MOVW d16 SP DWm MOVW d8 SP Am MOVW d8 SP DWm MOVW An Am ADDW 8 DIVU MOVW 016 5 MOVW DWn d16 SP Instruction Map MOVW An d8 SP MOVW DWn d8 SP MOVW ADDW 1692 MULU Extension code b 001 1 2nd nibble 3rd nibble 0 1 2 Chapter 17 8 9 A B F TBZ abs8 bp d1 1 TBNZ abs8 bp d7 TBNZ abs8 bp d11 CMP Dn Dm ADD Dn Dm TBZ io8 bp d7 TBZ io8 bp d11 TBNZ io8 bp d7 TBNZ io8 bp d11 OR Dn Dm AND Dn Dm BSET io8 bp BCLR io8 bp JMP abs18 label JSR abs18 label Dn Dm 8 Dm ADDC Dn Dm BSET abs16 bp BCLR abs16 bp BTST abs16 bp emp 8 8016 mov 8 abs16 8 abs16 d7 11 CBNE 8 0516 07 11 TBZ abs16 bp d7 TBZ abs16 bp d11 TBNZ abs16 bp d7 TBNZ abs16 bp d11 Ver2 1 2001 03 26 Instruction Map Appendix XVII 35 Record of Changes The following shows the changes in the publication of MN101C78A F78A LSI User s Manual Edition 1 2 to 1 3 Page Line Definition Former Edition 1 2 New Edition 1 3 Cover Add MN101C78A LSI User s M
550. scaler operation output A port A as I O pin enable the pull up resistor 1 Set the SCOPSCE flag of the SCOMDS register to 1 to 2 Set the SCOPSC2 to 0 flag of the SCOMD3 register to 100 to select the fs 2 as the clock source 3 Set the SCOFDC1 to 0 flag of the SCOMDS register to 00 to select 1 High fix of the SBOO last data 4 Set the SC1SL flag of the SCSEL register to 0 to select 5 Set the PAODC7 PAODCS flag of the PAODC register to 1 1 to select Nch open drain to SBTO pin Set the PAPLU2 PAPLUB flag of the PAPLU register to 1 1 to Operation XI 37 Chapter 11 Serial interface 0 Setup Procedure Description 6 Control the pin direction PADIR 0x03F3A bp2 PADIR2 1 bp1 PADIR1 0 PADIRO 1 7 Set the SCOMDO register Select the transfer bit count SCOMDO 0x03F91 bp2 0 SCOLNG2 0 111 Select the start condition SCOMDO 0x03F91 bp3 SCOSTE 0 Select the first bit to be transferred SCOMDO 0x03F91 bp4 SCODIR 0 Select the transfer edge SCOMDO 0x03F91 bp7 SCOCE1 1 8 Set the SCOMD1 register Select the communication style SCOMD1 0x03F92 SCOCMD 0 Select the transfer clock SCOMD1 0x03F92 bp2 SCOMST 0 bp3 SCOCKM 0 Select the transfer clock SCOMD1 0x03F92 bp4 SCOSBOS 1 bp5 SCOSBIS 1 bp6 SCOSBTS 1 bp7 SCOIOM 0 9 Set the interrupt level SCOTICR OxO3FFO bp7 6 SCOLV1 0 10 10 Enable the interrupt
551. selected count operation continues while the trigger pin is When 0 the fall ing edge is selected count operation continues while the trigger pin is L To control the startup by the commands TM7EN count operation should be selected In that case timer count operation or IGBT output are controlled by the TM7EN flag of the TM7MDI register When 1 count opera tion is selected count continues counting until 0 count stop is set Make sure to set the TM7IGBTO 1 of the TM7MD3 register before operating the TM7EN flag of the TM7MDI register In that case setup of T7IGBTTR is neglected The binary counter is cleared as the counting stops The value is loaded from the preset register to the compare register in synchronization with the counter clock 16 bit High Precision IGBT Output Timer 7 The IGBT waveform of any cycle duty is generated by setting the cycle of IGBT to the compare register 1 TM7OC1 and setting the duty of the period to the compare register 2 7 2 The 16 bit timer that can be used by high precision IGBT output is the timer 7 One shot Pulse Output Setup One shot pulse output can be done by setting the TTONESHOT flag of the TM7MDA register to 1 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively VI 57 Chapter 6 16 bit Timers Count Timing of High Precision IGBT Output At Normal Timer 7 dud WU TM7EN
552. sfer clock I O SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Style Push pull Nch open Push pull N ch open Push pull N ch open drain drain drain PAODC PAODC2 P7ODC P7ODC7 P7ODC P7ODC5 Input mode PADIR PADIRO PADIR PADIR2 P7DIR P7DIR7 P7DIR P7DIR5 Pull up setup Added Not added Added Not added Added Not added PAPLU PAPLU2 P7PLU P7PLU7 Operation 29 Chapter 11 Serial interface 0 XI 30 Pins Setup with 3 channels at reception Table 11 3 8 shows the setup for synchronous serial interface pin with 3 channels SBOO pin SBIO SBTO pin at reception Table 11 3 8 Setup for Synchronous Serial Interface Pin with 3 channels at reception Setup item Data output pin Data input pin Clock pin pin SBIOA pin SBTOA pin SBTOB pin SBOOB pin SBIOB pin Clock master Clock slave SCOSCMD1 SCOMST Port pin 75 PA1 P76 PA2 P77 Port pin setup Select pin A B SCSEL SCOSL Serial data input SBIO selection SCOMD1 SCOIOM Function Port Serial input Transfer clock I O Transfer clock I O SCOMD1 SCOSBOS SCOMD1 SCOSBIS SCOMD1 SCOSBTS Style Push pull N ch open Push pull N ch open drain drain PAODC PAODC2 P70DC P70DC7 y o Input mode Output mode Input mode PADIR PADIR1 PADIR PADIR2 P7DIR P7DIR7 P7DIR P7DIR6
553. sfers with memory The four data registers may be paired to form the 16 bit data registers DWO D0 D1 and DW1 D2 D3 At reset the value of Dn is undefined 15 87 0 Data register Figure 2 1 6 Data Registers Overview 9 Chapter 2 CPU Basics 2 1 7 Processor Status Word sr H Processor status word PSW is 8 bit register that stores flags for operation results interrupt mask level and maskable interrupt enable PSW is automatically pushed onto the stack when an interrupt occurs and is automati cally popped when return from the interrupt service routine Processor Status Word PSW Table 2 1 4 Processor Status Word PSW bp Flag At reset Description Reserved Set always to 0 Maskable interrupt enable MIE 0 All maskable interrupts are disabled 1 xxxLVn xxxlE for each interrupt is enabled IM1 Interrupt mask level IMO Controls maskable interrupt acceptance Overflow flag VF 0 Overflow did not occur 1 Overflow occurred Negative flag 0 MSB of operation results is O 1 MSB of operation results is 1 Carry flag 0 A carry or a borrow from MSB did not occur 1 A carry or a borrow from MSB occurred Zero flag 0 Operation result is not O 1 Operation result is O Il 10 Overview Chapter 2 CPU Basics B Zero ZF Zero flag ZF is set to 1 when all bits are 0 in the operati
554. start condition SC1MD0 0x03F99 bp3 SC1STE 1 Select the first bit to be transferred SC1MDO 0x03F99 bp4 SC1DIR 0 7 Set the SC1MD2 register Control the output data SC1MD2 0x03F9B SC1BRKE 0 Select the added parity bit SC1MD2 0x03F9B SC1NPE 0 bp5 4 SC1PM1 0 00 Specify the flame mode SC1MD2 0x03F9B bp7 6 SC1FM1 0 11 8 Set the SC1MD1 register Select the communication type SC1MD1 0x03F9A SC1CMD 1 Select the clock frequency SC1MD1 0x03F9A SC1CKM 1 bp2 SC1MST 1 bp1 SC1DIV 0 Control the pin function SC1MD1 0x03F9A bp4 SC1SBOS 1 bp5 SC1SBIS 1 bp7 SC1IOM 0 9 Enable the interrupt SC1RICR 0x03FF1 bp1 SC1RIE 1 SC1TICR 0x03FF2 bp1 SC1TIE 1 b Set the P1DIR5 flag of the Port 1 pin direction control register P1DIR to 1 and the P1DIR6 flag to 0 to set P15 to the output mode P16 to the input mode 6 Set the SC1STE flag of the SC1MDO register to 1 to enable start condition Set the SC1DIR flag of the SC1MDO register to O to select MSB as first transfer bit 7 Set the SC1BRKE flag of the SC1MD2 register to O to select the serial data transmission Set the SC1PM1 to 0 flag of the SC1MD2 register to 00 to select 0 parity and set the SC1NPE flag to 0 to enable add parity bit Set the SC1FM1 to 0 flag of the SC1MD2 register to 11 to select 8 bits 2 stop bits at the flame mode 8 Set the SC1CMD flag of the SC1MD1
555. sters Chapter 6 16 bit Timers Timer 7 Mode Register 4 TM7MD4 Table 6 2 32 Timer 7 Mode Register 4 TM7MD4 0x03F6E 4 3 1 0 T7ONES T7NODE T7ICT2 T7CAPCL HOT D R 0 0 0 Description T7ONESHO One shot pulse selection 0 Continuous pulse 1 One shot pulse T7NODED Dead time selection 0 With dead time 1 Without dead time T7ICT2 Capture trigger selection 0 0 interrupt 1 Timer 1 interrupt T7CAPCLR BC clearance at capture 0 Clear 1 Unclear capturing at timer stop a T7CAPCLR flag is effective when timer is operating The binary counter is uncleared when Control Registers VI 19 Chapter 6 16 bit Timers This is a readable writable register that controls timer 8 Timer 8 Mode Register 1 TM8MD1 Table 6 2 33 Timer 8 Mode Register 1 TM8MD1 0x03F88 VI 20 7 6 3 2 1 0 Reserved 1 T8ICEDG TM8PS1 TM8PSO TM8CK1 TM8CKO 0 Reserved Description Set always 0 T8ICEDG1 Capture trigger edge selection 0 Falling edge 1 Rising edge TM8CL Timer output reset signal 0 Operate timer output 1 Disable timer output Reset TM8EN Timer 8 count control 0 Halt the count 1 Operate the count 3 2 TM8PS1 TM8PSO Count clock selection 00 1 1 of clock 01 1 2 of clock 10 1 4 of clock 11 1 16 of clock 1 0 TM8CK1 TM8CKO
556. t Clock 5 pin Input pin 5 1 5801 pin Transfer bit counter SCIRBSY Data set to TXBUF1 Interrupt SC1TIRQ Figure 12 3 16 Reception Timing at Standby Mode Reception at rising edge start condition is disabled Operation XII 27 Chapter 12 Serial interface 1 XII 28 B Pins Setup with channels at transmission Table 12 3 7 shows the setup for synchronous serial interface pin with channels 5 pin SBII pin SBTI pin at transmission Table 12 3 7 Setup for Synchronous Serial Interface Pin with 3 channels at transmission Setup item Data output pin Data input pin Clock pin pin SBO1B SBI1A pin SBI1B pin SBT1 pin SBT1B pin Clock master Clock slave SC1SCMD1 SC1MST Port pin P15 P16 P17 PA6 Port pin setup Select used pin A B SCSEL SC1SL Serial data input SBI1 selection SC1MD1 SC1IOM Function Serial data output 1 input Transfer clock I O Transfer clock I O SC1MD1 SC1SBOS SC1MD1 SC1SBIS SC1MD1 SC1SBTS Style Push pull Nch open Push pull Nch open Push pull Nch open drain drain drain P10DC P10DC5 P10DC P10DC7 PAODC PAODC6 PAODC PAODC5 Output mode Output mode Input mode P1DIR P1DIR5 P1DIR P1DIR7 PADIR PADIR6 PADIR PADIR5 Pull up setup Added Not added Added Not added Added Not added P1PLUD P1PLUD5 P1PLUD P1PLUD
557. t png PAIMD2 R Input mode control K Schmitt trigger input v Port input data PAINZ Analog input Serial 0 clock input Serial 0 clock output SCOMD1 SCOSBTS Figure 4 8 3 Block Diagram PA2 Reget R PADWN Pull up pull down resistor selection 1 WEK R Reset Pull up pull down resistor control pP PAPLUDS Wek R Reset direction control t bd PADIRS gt L K R 41849 ha Port output data D 1 WEK R Y Par ar d Input mode control ng 7 7 WEK YR PAIN Schmitt trigger input Port input data lt 3 J R Analog input Figure 4 8 4 Block Diagram Port A IV 79 Chapter 4 Ports t PADWN WEK R N 7 Reset Pull up pull down resistor control pees Pull up pull down resistor selection PADIRA direction control gt ecd Ve DH fen E Y Port output data p qrAOuTs 11 WEK 1 R Reset Input mode control PAIMD4 WEK R Schmitt trigger input Port input data lt 1 Z R Analog input Serial 1 UART1 reception data input Figure 4 8 5 Block Diagram PA4 Reset
558. t 110 7 bit 111 8 bit Chapter 13 Serial Interface 3 Serial interface Mode Register 1 SC3MD1 0x03FA1 bp 7 6 5 4 2 Flag SC3IOM SC3SBTS SC3SBIS SC3SBOS SC3MST At reset 0 0 0 0 0 Access SC3IOM Serial data input selection 0 Data input from SBI3 1 Data input from SBO3 SDA3 Description SC3SBTS SBT3 pin 0 Port function 1 Transfer clock input output SC3SBIS Serial input control 0 1 input 1 Serial data input SC3SBOS 0 Port 1 Serial data output SBOS SDA3 pin function SC3MST 0 Slave 1 Master Clock master slave selection Control Registers XIII 7 Chapter 13 Serial Interface 3 7 6 Serial interface Mode Register SC3MD3 0x03FA2 3 2 1 0 SC3FDC1 SCSFDCO SC3PSCE SC3PSC2 SC3PSC1 SC3PSCO 0 0 0 0 0 0 Description SBOS output selection after transfer of last data 00 Fixed to 1 High output 01 Hold last data 10 Fixed to O Low output 11 Reserved SC3FDC1 SC3FDCO Prescaler count control 0 Disable the count 1 Enable the count SC3PSCE Clock selection 000 fosc 2 001 fosc 4 010 fosc 8 011 fosc 32 100 fs 2 101 fs 4 110 timer 2 output 111 timer 3 output SC3PSC2 SC3PSC1 SC3PSCO XIII 8 Control Regist
559. t 2 Bit 1 Bit 0 0 03 4 IRQ2ICR IRQ2LV1 IRQ2LVO REDG1 IRQ2IE IRQ2IR 11 22 0 0 0 0 0 Interrupt level specifi Interrupt Interrupt Interrupt cation flag valid enable request edge flag flag specifi cation flag Ox03FE6 IRQ4ICR IRQ4LV1 IRQ4LVO IRQ4IE IRQ4IR 23 0 0 0 2 0 0 Interrupt level specifi Interrupt Interrupt Interrupt cation flag valid enable request edge flag flag specifi cation flag OxOSFE7 TMOICR TMOLV1 TMOLVO TMOIE TMOIR 24 0 0 2 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag 0 03 8 TM1ICR TM1LV1 TM1LVO 1 TM1IR 25 0 0 5 E 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag 0 03 9 TM2ICR TM2LV1 TM2LVO 21 TM2IR 26 0 0 E 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag 0x03FE TM3LV1 11 27 0 0 2 x 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag 0 0 TM6ICR TM6LV1 TM6LVO TM6IE TM6IR 28 0 0 2 z 0 0 Interrupt level flag Interrupt Interrupt enable request flag flag Special Function Registers List XVII 25 Chapter 17 Appendix Bit Symbol Address Register Page Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0x03FE TBICR TBLV1 TBL
560. t OVF 1 Match of BC and OC1 TM7PWM Timer output waveform selection 0 Output timer 1 Output PWM TM7IRS1 Timer 7 interrupt factor selection 0 Counter clear 1 Match of BC and OC1 T7ICEN Input capture operation enable flag 0 Disable capture operation 1 Enable capture operation T7ICT1 T7ICTO Capture trigger selection 00 External interrupt 0 input signal 01 External interrupt 1 input signal 10 External interrupt 2 input signal 11 Disable Control Registers VI 17 Chapter 6 16 bit Timers Timer 7 Mode Register 3 TM7MD3 Table 6 2 31 Timer 7 Mode Register 3 TM7MD3 0x03F8E 7 6 5 4 3 2 1 0 TM7CKS Reserved TM7CKE T7IGBTT T7IGBTD T7IGBTE T7IGBT1 T7IGBTO MP DG R T N 0 0 0 0 0 Description TM7CKSMP Capture sampling selection 0 Count clock 1 fs Reserved Set always 0 TM7CKEDG TM7IO count edge selection 0 Rising edge 1 Both edges T7IGBTTR IGBT trigger level selection 0 H 1 L T7IGBTDT IGBT dead timer insert timing 0 Falling edge standard 1 Rising edge standard T7IGBTEN IGBT operation enable 0 Disable 1 Enable T7IGBT1 IGBT timer startup factor selection T7IGBTO 01 External interrupt 0 input signal 10 Externa interrupt 1 input signal 11 External interrupt 2 input signal 00 Timer 7 count operation When IGBT is not selected set as T7IGBTEN 0 T7IGBT1 0200 VI 18 Control Regi
561. t bit at transmission and the minimum data input period of the last bit at reception At slave the internal clock should be set up to keep the data hold time at trans mission Table 12 3 4 Last Bit Data Length of Transfer Data The last bit data holding period at transmission The last data input period at reception At master 1 bit data length 1 bit data length Minimum At slave 1 bit data length of external clock x 1 2 4 internal clock cycle x 1 2 When start condition is disabled at SCISTE flag 0 the SBO1 output after the data output holding period of the final bit can be set by the setting value of the SCIFDCI to 0 flag of the SC1MD3 register as shown on Table 12 3 5 After releasing the reset despite the setting value of the SCIFDCI to 0 flag output before the serial transfer is H When start condition is enabled at SCISTE flag 1 despite the setting value of the SCIFDCI to 0 H is output Table 12 3 5 5801 Output after the Data Output Holding Period of the Last Bit without start condition SBO1 output after the data SC1FDC1 flag SC1FDCO flag output holding period of the last bit 0 0 Fixed to 1 High output 1 0 Last data holding 0 1 Fixed to 0 Low output 1 1 Reserved Operation Other Control Flag Setup Chapter 12 Serial interface 1 Table 12 3 6 shows flags that do not required to be set or monitored as the flags are not used at clock sy
562. t data Ig snq 19 o V Yo gt c amp c Port output control WEK VR Schmitt trigger input Port input data lt Z R Serial 1 reception data input Serial 1 UART1 transmission data output SC1MD1 SC1SBOS Timer 0 output LCD output control Segment output control A MW Segment output data Vict LCD clock Q ER Y Vic2 d 3 5 Vica Y i a Figure 4 2 6 Block Diagram 15 At segment output port I O direction control is forcefully set to input mode pull up resistor is disabled and seg ment output is executed by the segment output control 1 19 Chapter 4 Ports Edge event External interrupt 0 IRQO holding function Nch open drain control 4 Reget P1OD
563. t dene teinte XI 34 11 3 3 UART Serial Interface e e e e he E ERR Ree te beo tepido XI 43 11 34 Setup Example ette tee Regem e e ote eB A teen XI 60 Chapter 12 Serabinterfage ua gua dde ate e dot uu el t E 1 VDA OVERVIEW XII 2 12 1 T Functions eee XII 2 12 12 Block anc etre ER 4 12 2 Gontrol sonne XII 5 12 221 RESISTORS posee a dr Oe ERE REA RE REPE XII 5 12 2 2 Data Bu ffer Registers sata eee tee tee eire wid eet ee ade XII 6 12 2 3 Mode esee eee e e eite XII 7 12 3 Operation sescenti n e e tene esed i ee eremita eet idees 13 12 3 1 Clock Synchronous Serial Interface essere XII 13 12 32 Setup Example eee tet eec oe ie ede pee deepest uet XII 33 12 3 3 UART Serial Interface u c ettet orte pei ecrire pines XII 42 12 3 4 Setup Example neg a ei a hiba phase XII 59 Chapter 3 cain seh Sica 1 13 1 OVERVIEW XIII 2 13 1 T Functions itte etre t OU RR DERE OO IRE XIII 2 131 2 Block Diagram xiu tno e dei a d teet c teste ate iei XIII 3 13 2 Control Registers uote Ode aque He hie UE EU e ERE oats 4 1321 Registers RUNDE UM XIII 4 13 2 2 Data Buffer Register nete etie stie etie tte recep Dee XIII 5 13
564. t fs 2 5 MHz operation as a clock source A setup procedure example with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 TMOEN 0 2 Disable the interrupt TMOICR 0x03FE7 bp1 TMOIE 0 3 Select the normal timer operation TMOMD 0x03F54 TMOPWM 0 bp5 TMOMOD 0 4 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 5 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 0 TMOBAS 1 6 Set the cycle of the interrupt generation 0x03F52 0 9 7 Set the interrupt level TMOICR 0x03FE7 bp7 6 TMOLV1 0 10 8 Enable the interrupt TMOICR 0x03FE7 bp1 1 9 Start the timer operation TMOMD 0x03F54 TMOEN 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to 0 to stop the counting of the timer O 2 Set the TMOIE flag of the TMOICR register to 0 to disable the interrupt 3 Set the TMOPWM flag and the TMOMOD flag of the TMOMD register to 0 to select the normal timer operation 4 Select the prescaler output to the clock source by the 2 to 0 flag of the TMOMD register b Select fs 2 to the prescaler output by the TMOPSC 1 to 0 flag and TMOBAS flag of the timer 0 prescaler selection register CKOMD 6 Set the value of the interrupt generation cycle to the timer 0 compare register TMOOC The
565. t mode by the port 1 input mode register PIIMD The control flag of the port 1 input mode register PIIMD is set to 1 to output the special function data and 0 to use as the general port For P10 P11 P15 and P17 each bit can be selected individually as Nch open drain output by the port 1 Nch open drain control register The control flag of the port 1 Nch open drain control register PIODC is set to 1 for Nch open drain output and 0 for push pull output Special Function Pin Setup P10 is used as the transmission reception data I O pin of as well When the SELI2C flag of the serial inter face 4 addressing register 1 SC4AD1 is 1 P10 is the serial transmission reception data I O pin Push pull out put or Nch open drain output can be selected by setting the Port 1 Nch open drain control register PIODC P11 is used as the clock input pin of as well When the SCLI2C flag of the serial interface 4 addressing reg ister 1 SC4AD1 is 1 P11 is the serial clock input pin Push pull output or Nch open drain output can be selected by setting the Port 1 Nch open drain control register P12 is used as I O pin of the timer 8 as well The output mode can be selected by of the port 1 output mode register by each bit The bp of the port 1 output mode register PLOMD is set to 1 to output the special function data and 0 to use as the general
566. t pin outputs low level Standby mode can be recovered by the key interrupt Key input pin should be pull up in advance B Key Input Interrupt Setup Example External interrupt 4 After P70 to P73 of port 4 are set to key input pins and key is input low level the external interrupt 4 IRQ4 is generated An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Set the key input to input P7DIR 0x03F34 bp3 0 P7DIR3 0 20000 2 Set the pull up resistor P7PLU 0x03F44 bp3 0 P7PLU3 0 21111 3 Select the key input interrupt KEYT3_1IMD 0x03F3E bp7 KEYT3_1SEL 1 4 Select the key input pin KEYT3_1IMD 0x03F3E bp1 0 KEYT3 1EN2 1 11 5 Set the interrupt level IRQ4ICR OxO3FE6 bp7 6 IRQ4LV1 0 10 6 Enable the interrupt IRQ4ICR OxOSFE6 bp1 IRQ4IE 21 1 Set the P7DIR3 to 0 flag of the port 7 direction control register P7DIR to 0000 to set P70 to P73 pins 10 input pins 2 Set the P7PLUS to 0 flag of the port 7 pull up resistor control register P7PLU to 1111 to add the pull up resistors to P70 to P73 pins 3 Set the KEYT3SEL flag of the key interrupt control register KEYT3_1IMD to 1 to enable the key interrupt 4 Set the KEYT3_1EN1 to 0 of the key interrupt control register KEYT3_1IMD to 1111 to set P70 to P73 pins to key input pins 5 Set the interrupt level by the IRQ4LV1 to 0 flag of the IRQ4ICR r
567. t request flag IRQNPG When the setting of the IRQNPG flag is confirmed by the non maskable interrupt process program the softreset is recommended by outputting 0 to the reset pin P27 a When the undefined instruction is going to be executed this LSI generates the non maskable Control Registers 19 Chapter 3 Interrupts III 20 External Interrupt 0 Control Register IRQOICR The external interrupt 0 control register IRQOICR controls interrupt level of the external interrupt 0 valid edge interrupt enable and interrupt request Interrupt control register should be operated when the maskable interrupt enable MIE of PSW 15 0 Table 3 2 3 External Interrupt 0 Control Register IRQO0ICR 0x03FE2 7 6 1 0 IRQOLV1 IRQOLVO IRQOIE IRQOIR 0 0 0 0 Description IRQOLV 1 Interrupt level flag IRQOLVO The CPU has interrupt levels from 0 to 3 This flag sets the interrupt level for interrupt requests REDGO Interrupt valid edge flag at the standby mode 0 Falling edge low level 1 Rising edge high level IRQOIE Interrupt enable flag 0 Disable interrupt 1 Enable interrupt IRQOIR Interrupt request flag 0 No interrupt request 1 Interrupt request generated Control Registers Chapter 3 Interrupts External Interrupt 1 Control Register IRQ1ICR The external interrupt control register controls interrupt level of
568. t the same time SCITIRQ is gener ated SCIREMP is cleared to 0 after RXBUF1 is read out To communicate properly the external clock should be input after 3 5 transfer clock interval past from the data set to TXBUFI When the start condition is set to enable in the clock synchronous communication trans mission and reception should not be executed at the same time to prevent abnormal opera tion If the start condition is input to restart during communication the transmission data is not valid Set the transmission data to TXBUF1 again to operate the transmission again RXBUF1 is rewritten every time communication is completed At continuous communication data of RXBUF1 should be read out before the next reception is completed Operation XII 15 Chapter 12 Serial interface 1 Transfer Bit Count and First Transfer Bit At transmission when the transfer bit count is 1 bit to 7bits the data storing method to the transmission data buffer TXBUFI is different depending on the first transfer bit selection At MSB first use the upper bits of TXBUPFI for storing When the transfer bit count is 6 bits as shown on Figure 12 3 2 if data to are stored to bp2 to bp7 of TXBUF1 the transmission is operated from F to At LSB first use the lower bits of TXBUPFI for storing When the transfer bit count is 6 bits as shown on Figure 12 3 3 if data to are stored to to bp5 of TXBUFI the tra
569. t to 0x0000 Count clock TMnEN flag Compare register 1 Compare register 2 Binary 0000 Ip 0000 counter H TMnIO output PWM output Figure 6 7 2 Count Timing of High Precision PWM Output When the compare register 2 is 0x0000 0000 When the TMnEN flag is stopped at 0 the PWM output shows H 16 bit High Precision PWM Output Cycle Duty can be changed consecutively VI 45 Chapter 6 16 bit Timers VI 46 Count Timing of High Precision PWM Output At the compare register 2 the compere register 1 1 Count clock TMnEN flag Compare register 1 Compare register 2 Binary 0000 M 00000001 counter TMnIO output PWM output Figure 6 7 3 Count Timing of High Precision PWM Output At the compare register 2 the compare register 1 1 To output the high precision PWM output set the TMnBCR flag of the TMnMD2 register to 1 to select the TM7OC1 compare match as the clear source for the binary counter and the set H output source of the PWM output Also set the TnPWMLS flag to 1 to select the TMnOC2 compare match as the reset L output source of the PWM output N 1 In the initial state of the PWM output it is changed to H output from L output at the timing that the PWM operation is selected by the TMnPWM flag of the TMnMD register
570. te resistor VLC2 VLC3 potentials by using the internal resistor B Supplying voltage with the external voltage driving resistor Supply the voltage as shown in Table 16 3 2 Table 16 3 2 LCD Power Supply Static 1 2 1 3 Vict Vicp Vss Vss Vicp Vss Vice 1 2Vicp Vss 2 3Vicp Vss Vica Vss 1 3 Vss Vy ep LCD panel driver voltage Maximum voltage to the LCD panel a Use the LCD panel driver voltage Vi cp at Vi cp 3 6 V 14 Operation Chapter 16 LCD Figure 16 3 1 shows example of the LCD power supply connection a Static MN101C78 C V be D slot eee Vss b 1 3duty 1 3bias 1 4 1 3bias MN101C78 Vic2 Re i Vics Vss R Figure 16 3 1 LCD Power Supply Connection When using External Voltage Divider Resistors Operation XVI 15 Chapter 16 LCD 1 In Figure 16 3 1 current always flows through the voltage dividing resistors The following connection is used to cut the current flowing through these dividing resistors at MN101C78 VDD input pee Vict R IE Vic2 Vics R C Vss C
571. ter tec tte rede e 1 32 1 5 5 A D Converter Characteristics 20224240 000000 1 33 1 6 Package Dimension sane ved eene 1 34 1 7 Cautions Tor Circuit Setup c deta eed EORR ER 1 35 LT d General Usage tede ees I 35 1 72 nused pins eee ertet ie OR I 36 173 Supply p Oder E Er Ro unie I 38 1 743 Power Supply eren deep Red DS I 39 Ghapter II 1 2 OVerview sicot aetate eo eee em een mp dep Ress II 2 2 1 Block 1 4 2 1 2 CPU Control Registers e Per op ede II 6 2 1 3 Instruction Execution Controller sese eren eere 7 2 1 Pipeline PLOCESS i aa E eec II 8 2 1 5 Registers for Address eeepc drei eR eee ene II 8 2 1 6 Registers Tor Data 5 UOS RR Ue Eel iem t d oec Hesse 9 2 1 7 Processor Status Word ono ene rui remet reed II 10 2 1 8 Address Space oto oe II 12 2 1 9 Addressing M06068 nitet te II 13 2 10 MachimneClock ote dapi e de ne II 15 2 2 Memory Space eee AE ideni endet II 16 Contents 2 gt 2 21 Memory Mode e npo eO RE Ee e II 16 2 2 2 Sin
572. ter TM1ICR 0x03FE8 Timer 1 interrupt control register P1OMD OxO3F1C Port 1 output mode register P1DIR 0x03F31 Port 1 direction control register P7OMD OxO3F3C Port 7 output mode register P7DIR 0x03F37 Port 7 direction control register Control Registers V 7 Chapter 5 8 bit Timers V 8 Register Timer 2 TM2BC 0x03F58 Function Timer 2 binary counter TM20C OxOSF5A Timer 2 compare register TM2MD OxOSF5C Timer 2 mode register CK2MD OxOSF5E Timer 2 prescaler selection register TM2ICR OxOSFE9 Timer 2 interrupt control register P1OMD OxOSF1C Port 1 output mode register P1DIR OxOSF31 Port 1 direction control register P5OMD OxOSF2C Port 5 output mode register P5DIR 0x03F35 Port 5 direction control register TM3BC 0x03F59 Timer 3 binary counter OxOSF5B Timer 3 compare register TM3MD 0x03F5D Timer 3 mode register CK3MD Ox03F5F Timer 3 prescaler selection register Timer 3 interrupt control register P1OMD OxOSF1C Port 1 output mode register P1DIR OxOSF31 Port 1 direction control register P7OMD Port 7 output mode register P7DIR R W Readable Writable R Readable only Control Registers OxOSF37 Port 7 direction control register Chapter 5 8 bit Timers
573. ternal interrupt 2 IRQ2 IRQ2ICR 4 5 0x04014 Reserved 5 OxO3FE5 6 0x04018 External interrupt 4 IRQ4 IRQ4ICR 7 0x0401C Timer 0 interrupt TMOIRQ IRQOICR OxOSFE7 8 0x04020 Timer 1 interrupt TM1IRQ IRQ1ICR OxO3FE8 9 0x04024 Timer 2 interrupt TM2IRQ TM2ICR Ox03FE9 10 0x04028 Timer 3 interrupt TM3IRQ TMSICR 11 0x0402C Timer 6 interrupt TM6IRQ TM6ICR 0x03FEB 12 0x04030 Time base interrupt TBIRQ TBICR OxO3FEC 13 0x04034 Timer 7 interrupt TM7IRQ TM7ICR OxO3FED 14 0x04038 Timer 7 compere 2 match inter T7OC2IR T7OC2ICR OxOSFEE rupt Q 15 0x0403C Serial 0 UART reception inter SCORIR SCORICR Ox03FEF rupt Q 16 0x04040 Serial 0 UART transmission SCOTIR SCOTICR OxOSFFO interrupt Q 17 0x04044 Serial 1 UART reception inter SC1RIR SC1RICR Ox03FF1 rupt Q 18 0x04048 Serial 1 UART transmission SC1TIR SC1TICR Ox03FF2 interrupt Q 19 0x0404C Serial 3 interrupt SC3IRQ SC3ICR Ox03FF3 20 0x04050 A D conversion interrupt ADIRQ ADICR Ox03FF4 21 0x04054 Serial 4 interrupt SC4IRQ SC4ICR OxO3FF5 22 0x04058 Timer 8 interrupt TM8IRQ TM8ICR 0x03FF6 23 0x0405C Timer 8 compare 2 match inter TM8OC2 TM8OC2IC OxOS3FF7 rupt IRQ R 11 6 Overview Chapter 3 Interrupts Interrupt Level and Priority This LSI allocated vector numbers and interrupt control registers except reset interrupt to each interrupt The interrupt level except reset interrupt non maskable interrupt can be set by software per each
574. the clock input At the clock input 1 or more transfer clock should be needed after the start condition output 6 At the clock input 3 5 or more transfer clock should be needed after setting transmission data dummy data The system configuration is needed to notify the master of the data load completion 7 At the clock input 0 5 or more transfer clock should be needed after the start condition input When Operation receiving data continuously the system configuration is needed to notify the master of the readout completion Without the notification the data before readout may be overwritten Chapter 13 Serial Interface 3 B Transfer Bit Count Setup The transfer bit count can be selected from 1 bit to 8 bits Set the SC3LNG 2 to 0 flag of the SC3MDO register at reset 111 The SC3LNG 2 to 0 flag holds the previous value until other value is set during communication At slave set data to SC3TRB or input start condition before input a The SBT3 pin is masked inside serial interface to prevent operating errors by noise except clock to the pin Wait more than 3 5 transfer clocks before input the external clock after the data set to TXBUF3 Otherwise normal operation is not guaranteed Start Condition Setup Enable or disable of start condition can be selected with the SC3STE flag of the SC3MDO register Start condition is detected when the SC3CEI flag of the SC3MDO register is set to
575. the clock is an external input connect it to XI and leave XO open At the STOP mode the chip will not operate with an external clock At reset the input mode is selected and pull up resistors are enabled output 16 16 VO ANO SBOOA TXDOA port A 7 bit COMS tri state I O port PA1 17 17 AN1 SBIOA RXDOA Each bit can be set individually as either an PA2 18 18 AN2 SBTOA input or output by the P7DIR register 19 19 At reset the input mode is selected and pull 4 1 20 SBI1B RXD1B up resistors are disabled high impedance 5 1 21 AN5 SBO1A TXD1B output PA6 1 22 AN6 SBT1B SBOOA 16 16 VO PAO ANO TXDOA Serial interface Transmission data output pins for serial SBOOB 38 35 P75 KEY5 RXDOB SEG2 transmission data interface 0 1 3 SBO1A 30 27 P15 TXD1A TMOOB SEG10 output pins The output configuration either COMS push SBO1B 1 21 PAS AN5 TXD1B pull or Nch open drain can be selected at the SBO3 44 41 P33 1 P3ODC P7ODC PAODC registers Pull up and pull down registers can be selected by the P1PLUD P3PLU P7PLUD PAPLU registers Select the output mode at the PADIR registers and serial data output mode by serial mode register 1 SCOMD1 SC1MD1 SC3MD1 These can be used as normal I O pins when the serial interface is not used Pin Description 1 15 Chapter 1 Overview 16 TQFP 48 Pin No QFP44 Pin No
576. the first communica tion after reset release From the second communication the SC3STE flag of the SC3MDO register can select if start condition is enabled or not If start condition is detected during data communication in which the start condition is enabled the SC3STC flag of the SC3CTR register is set to 1 and the communication end interrupt SC3IRQ is generated to end the trans mission This means that the communication is not executed properly and needs to be re executed Clear the SC3STC flag by program When data line SDA3 pin is changed from to L while clock line the SCL3 pin is H start condition is generated Operation XIII 37 Chapter 13 Serial Interface 3 XIII 38 Generation of Stop Condition Stop condition is generated as the SDA3 line is changed from L to while the SCL3 line is Stop condi tion can be generated by setting the IIC3STPC flag of the SC3CTR register to 0 by program When the stop condition is generated IIC3STPC flag is cleared automatically Start condition Stop condition SDA Serial data i SCL i gu o o TE Serial clock i Figure 13 3 17 Start Condition and Stop Condition Input Edge Output Edge Setup In IIC communication data is always received at the falling edge of the clock Even if the SC3CEI flag is set to 0 the received data is stored in the falling edge of the clock Data I O Pin Setup The SDA3 pin used as SBO3 pin
577. the set value of the TM7OC2 register Once they match it outputs L After that TM7BC continues to count up Once TM7BC value matches the TM7OC register value to be cleared the IGBT output waveform outputs and TM7BC counts up from X 0000 again 7 pin outputs dead time worth of IGBT output waveform TMSIO pin out puts dead time worth of inverted IGBT output waveform To output the IGBT output waveform from the large current pin TM7IO set the special function pin to output mode as follows refer to setup example 2 Set each of P5SOMDI flag and PSOMD3 flag of the port 5 output mode register PSOMD to 1 to select P51 pin and P53 pin as the special function pins Set PSDIR1 and P5DIR3 flag of the port 5 direction control register to 1 to set output mode Dead Time IGBT Output Chapter 6 16 bit Timers 6 12 16 bit Timer Cascade Connection 6 12 1 X Operation Cascading timers 7 and 8 forms a 32 bit timer 16 bit Timer Cascade Connection Operation Timer 7 Timer 8 Timer 7 and timer 8 are combined to be a 32 bit timer Cascading timer is operated at clock source of timer 7 which are lower 16 bits Table 6 12 1 Timer Function at Cascade Connection Timer 7 Timer 8 32 bit Interrupt source TM8IRQ1 TM8IRQ2 Timer operation Timer pulse output 8 output PWM output Synchronous output Clock source fosc fosc 2 fosc 4 fosc
578. time base timer clear register TBCLR Both timers are operated by the enable signal of the TM6BEN 7 2 1 Control Registers Table 7 2 1 shows the registers that control timer 6 time base timer Table 7 2 1 Control Registers Register Address Function TM6BC OxOSF60 Timer 6 binary counter TM6OC 0x03F61 Timer 6 compare register TM6MD 0x03F62 Timer 6 mode register 0x03F64 Timer 6 enable register TM6ICR OxOSFEB R W Timer 6 interrupt control register 11 28 Time base timer TM6MD 0 03 62 R W Timer 6 mode register VII 8 TBCLR 0x03F63 W Time base timer clear control register VII 6 TBICR OxO3FEC R W Time base interrupt control register 11 29 Control Registers VII 5 Chapter 7 Time Base Timer Free running Timer 7 2 2 Programmable Timer Registers u nHO U O ae Timer 6 is a 8 bit programmable counter Programmable counter consists of compare register TM6OC and binary counter TM6BC Binary counter is a 8 bit up counter When the TM6CLRS flag of the timer 6 mode register TM6MD is 0 and the interrupt cycle data is written to the compare register 6 the timer 6 binary counter TM6BC is cleared to 0x00 Timer 6 Binary Counter TM6BC 0x03F60 7 6 5 4 3 2 1 0 TM6BC7 TM6BC6 TM6BC5 TM6BC4 2 TM6BC1 TM6BCO 0 0 0 0 0 0 0 0 R R R R R R R R Timer 6 Compare Register TM6O0C 0x03F61
579. tion IGBT output duty is changeable O TM71O output TM7O output x output TM8O output High precision IGBT output duty TM71O output TM7O output x cycle are changeable output TM8O output Capture function Pulse width measurement O 32 bit cascade connection O Overview Chapter 6 16 bit Timers Clock source fosc fosc 2 fosc 4 fosc 16 fs fs 2 fs 4 fs 16 TM7IO input TM7IO input 2 TM7IO input 4 TM7IO input 16 synchronous input synchronous input 2 synchronous input 4 synchronous input 16 fosc fosc 2 fosc 4 fosc 16 fs fs 2 fs 4 fs 16 input input 2 TMBIO input 4 input 16 synchronous 8 input synchronous 8 input 2 synchronous 8 input 4 synchronous 8 input 16 fosc Machine clock High frequency oscillation fs System clock Chapter 2 2 5 Clock Switching Overview VI 3 Chapter 6 16 bit Timers Block Diagram 6 1 2 Timer 7 Block Diagram Z 18151661 195 29 eum peep 4198 195 49 peep
580. tion can constantly generates interrupts 8 bit Timer Operation Timer 0 1 2 and 3 The generation cycle of timer interrupts is set by the clock source selection and the setting value of the compare register TMnOC in advance If the binary counter TMnBC reaches the setting value of the compare register an interrupt is generated at the next count clock then binary counter is cleared and counting is restarted from 0x00 Table shows clock source that can be selected by timer Clock source per Count Timer 0 Timer 1 Timer 2 Timer 3 8 bit 8 bit 8 bit 8 bit fosc 100 ns fosc 4 400 ns fosc 16 1 6 us O O fosc 32 3 2 us O fosc 64 6 4 us O O fosc 128 12 8 us 15 2 400 ns 15 4 800 5 fs 8 1 6 us fx 30 5 us fosc 10 MHz fx 32 768 kHz fs fosc 2 5 MHz When fs 2 fs 4 fs 8 are used as clock source they are counted at the rising of the count Y clock and when others are used they are counted at the falling of the count clock 8 bit Timer V 21 Chapter 5 8 bit Timers 22 Count Timing of Timer Operation Timer 0 1 2 and 3 Binary counter counts up with selected clock source as a count clock The basic operation of the whole function of 8 bit timer is as follows Count clock TMnEN flag Compare register i 0 mo yy fepe isis count
581. tion only E ACK bit bit level Clock sources fosc 2 fosc 2 fosc 4 fosc 4 fosc 8 fosc 8 fosc 32 fosc 32 fs 2 fs 2 fs 4 fs 4 timer 2 output timer 3 output Maximum transfer rate 5 0 MHz NORMAL mode 100 kHz High speed mode 400 kHz fs system clock fosc machine clock for high speed oscillation In communication transfer clock is obtained by dividing the clock source by 8 Overview Chapter 13 Serial Interface 3 13 1 2 Block Diagram Serial Interface Block Diagram 4 0064 08 1 28 1054605 5188898 2054605 6186606 Z 2 39 489 ASGEOII ASdEOS 6086606 915591 139595 andino 915891 3959 31 89 LNOENL osdgos OdLSEOIl E 15 095 Otel J E ALSEOS 8 3 9989 ZONTEOS 8 SMOVEOII LONTIEOS 950 OMOVEOII ol 99N169S awosos YLOEOS 39912 N OUIEOS Nr n 24 2105 2185 qQIWOS8OS 39295 5185205 Od LSESII x MOV 5186605 n EEd EYAS O9S Dx N ims oie dojs x ponies uonipuoo n n W X eea evas eoas 5085205 3115805 9 159 uoroejep Jeyng
582. to be measured 3 Select the prescaler output to the clock source by the TMOCK to 0 flag of the TMOMD register 4 Select fs 2 to the prescaler output by the TMOPSC1 to 0 flag and the TMOBAS flag of the timer 0 prescaler selection register CKOMD 5 Set the timer 0 compare register TMOOC to the bigger value than the cycle of fs 2 L period of measured pulse width At that time the timer 0 binary counter is initialized to 0x00 6 Set the interrupt level by the IRQOLV1 to 0 flag of the external interrupt 0 control register IRQOICR If the interrupt request flag is already set clear all interrupt request flags Chapter 3 3 1 4 Interrupt Flag Setup 7 Set the REDGO flag of the IRQOICR register to 1 to specify the interrupt valid edge to the rising edge 8 Set the IRQOIE flag of the IRQOICR register to 1 to enable the interrupt 9 Set the TMOEN flag of the TMOMD register to 1 to enable the timer 0 operation Simple Pulse Width Measurement Chapter 5 8 bit Timers TMOBC starts to count up with negative edge of the external interrupt 0 IRQO input as a trigger Timer 0 continues to count up during L period of IRQO input then stop the counting with positive edge of IRQO input as a trigger At the same time reading the value of TMOBC by interrupt handling can detects L period be wrong at the count stop To prevent this use the clock source that is syn
583. to select the brake transmission all bits from start bits to stop bits transfer 0 B Reception Error At reception there are 3 types of error overrun error parity error and framing error Reception error can be deter mined by the SCOORE SCOPEK SCOFEF flag of the SCOSTR register Even one of those errors is detected the SCOERE flag of the SCOSTR register is set to 1 Among reception error flags the SCOPEK flag and the SCOFEF flag are renewed when the reception complete interrupt SCORIRQ is generated The SCOORE flag is cleared at the same time of next communication complete interrupt SCORIRQ generation after the data of the RXBUFO is read out The decision of the received error flag should be operated before the next communication is finished Those error flag has no effect on communication operation Table 11 3 19 shows the list of reception error source Table 11 3 19 Reception Error Source of UART Serial Interface Flag Error SCOORE Overrun error Next data is received before reading the reception buffer SCOPEK Parity error at fixed to 0 when parity bit is 1 at fixed to 1 When parity bit is 0 Odd parity The total of 1 of parity bit and character bit is even Even parity The total of 1 of parity bit and character bit is odd SCOFEF Framing error Stop bit is not detected B Judgement of Break Status Reception Reception at break status can be judge If all received data from start bit and s
584. to setup example 2 Set each of 1 flag of the port 5 output mode register PSOMD to 1 to select P51 pin as the special function pins Set PSDIR1 flag of the port 5 direction control register to 1 to set output mode VI 64 16 bit High Precision IGBT Output Cycle Duty can be changed consecutively Chapter 6 16 bit Timers 6 10 16 bit Standard IGBT Output Only duty can be changed consecutively Startup trigger can be selected by the external interrupt 0 1 and 2 or starting of the timer 7 count operation When counting starts the operation is the same as the high precision PWM output 6 10 1 X Operation IGBT Trigger Selection IGBT trigger can be selected from IRQO IRQI1 IRQ2 and the start of the timer 7 count operation Setup should be done at the T7IGBTO and T7IGBTI flag of the TM7MD3 register When the startup is controlled from exter nal of the microcontroller one of IRQO to IRQ2 should be selected This trigger detects the input level before activation Either H L level can be selected with the T7IGBTTR flag of the TM7MD3 register When 1 the rising edge is selected count operation continues while the trigger pin is When 0 the falling edge is selected count operation continues while the trigger pin is To control the startup by the commands TM7EN count operation should be selected In that case timer count operation or IGBT output are controlled b
585. too is used to input output data Set the SC3IOM flag of the SC3MDI register to 1 to input serial data from the SBO3 pin As the 5813 pin is not used at that time it can be used as a general port But always set the SC3SBIS flag of the above register to 1 to set input serial data To detect start condition set the SC3SBIS flag of the SC3MD1 register to input serial data regardless of transmission reception Operation Chapter 13 Serial Interface 3 Reception of Confirming Bit after Data Transmission The IIC3ACKS flag of the SC3CTR register selects if ACK bit is enabled or not If ACK bit is enabled ACK bit is received from the slave station after data 1 to 8 bits is transferred At reception of ACK bit the SDA3 line is automatically released To receive ACK bit 1 clock is output to store ACK bit to the of the SC3CTR register The transmission reception shift register SC3TRB is not operated by the ACK bit reception clock When the received ACK bit level is L the reception is normal at slave and the next data can be received If the level is the reception maybe completed at slave so set the IIC3STPC flag of the SC3CTR register to 0 to end com munication Data transmission period Bus release period 1 2 m 1 bit reception clock uU Figure 13 3 18 Bit Reception Timing after Transmission of 8 Bit Data B Tr
586. top bit is 0 the SCOBRKF flag of the SCOMD2 register is set and determines the break status The SCOBRKF flag is set when the reception com plete interrupt SCORIRQ is generated XI 46 Operation Chapter 11 Serial interface 0 Continuous Communication This serial interface has continuous communication function When data is set to the transmission data buffer TXBUFO during communication the transmission buffer empty flag SCOTEMP is automatically set to communi cate continuously This does not generate any blank in communication Set data to TXBUF between previous data setup and generation of the communication complete interrupt SCOTIRQ B Clock Setup Transfer clock is not necessary for UART communication itself but necessary for setup of data transmission reception timing in the serial interface Select the timer to be used as a baud rate timer by the SCOMD3 register Reception Bit Count and First Transfer Bit At reception when the transfer bit count is 7 bits the data storing method to the received data buffer RXBUFO is different depending on the first transfer bit selection At MSB first data is stored to the upper bits of RXBUFO When the transfer bit count is 7 bits as shown on Figure 11 3 18 data to A are stored to bp7 to of RXBUFO in this order At LSB first data are stored to the lower bits of RXBUFO When the transfer bit count is 7 bits as shown on Figure 11 3 19 data to are stored to
587. tput edge rising 8 Set the SCOCMD flag of the SCOMD1 register to 0 to select the synchronous serial Set the SCOMST flag of the SCOMD1 register to 1 to select the clock master internal clock Set the SCOCKM flag to 0 to select not divided for the clock source Set the SCOSBOS SCOSBIS SCOSBTS flag of the SCOMD register to 1 to set the SBOO pin to the serial data output the SBIO pin to the serial input SBTO pin to the transfer clock input output Set the SCOIOM flag 0 to set the serial data input from the 5810 pin 9 Set the interrupt level by the SCOTLV1 to 0 flag of the serial 0 UART transmission interrupt control register SCOTICR Operation XI 35 Chapter 11 Serial interface 0 XI 36 Setup Procedure Description 10 Enable the interrupt SCOTICR OxOSFFO bp1 SCOTIE 1 SCOTIR 0 11 Start the serial transmission Transmission data 0 03 97 Received data input SBIO pin 10 Set the SCOTIE flag of the SCOTICR register to 1 to enable the interrupt If any interrupt request flag SCOTIR of the SCOTICR register is already set clear SCOTIR before the interrupt is enabled 11 Set the transmission data to the serial transmission data buffer TXBUFO The transmission or reception is started by the internal clock generation When the transmission is finished the serial O UART transmission interrupt SCOTIRQ is generated Chapter 3 3 1 4 S
588. ts high precision PWM output which is determined by the match timing of the timer binary counter and the compare register 1 and match timing of the binary counter and the compare register 2 6 7 1 Operation B 16 bit High Precision PWM Output Operation Timer 7 Timer 8 The PWM waveform of any cycle duty is generated by setting the cycle of PWM to the compare register 1 TMnOC1 and setting the duty of the H period to the compare register 2 TMnOC2 Count Timing of High Precision PWM Output at Normal Timer 7 Timer 8 TMnEN flag Compare register 1 Compare register 2 u Oe counter TMnIO output PWM output lt p C gt PWM basic component Setup time for compare register 1 M Setup time for compare register Figure 6 7 1 Count Timing of High Precision PWM Output at Normal PWM source waveform A shows until the binary counter reaches the compare register from 0x0000 B shows after the TMnOC2 compare match the binary counter then counts up until the binary counter reaches the compare register is cleared 16 bit High Precision PWM Output Cycle Duty can be changed consecutively Chapter 6 16 bit Timers C shows again when the binary counter is cleared Count Timing of High Precision PWM Output When the compare register 2 is 0x0000 Timer 7 Timer 8 Here is the count timing as the compare register 2 is se
589. tual analog signal is sampled The actual time is the conversion time plus 1 T Ap Calculus Conversion Time Ts 13 2 5 fs a The conversion time shown above does not include between the instant when A D conver A D conversion time may be extended up to 0 5 system clock when fx 2 is selected as the D conversion clock Built in Ladder Register Control The ANLADE flag of the ANCTRO register is set to 1 to send a current to the ladder resistance for A D conver sion When A D converter is stopped the ANLADE flag of the ANCTRO register is set to 0 to save the power consumption A D Conversion Start Factor Selection A D conversion start factor is set by the ANSTSEL flag of the ANCTR2 register By setting the ANSTSELI flag of the ANCTR2 register A D conversion starts with the external interrupt 2 factor Also A D conversion starts when ANST flag of the ANCTR2 register is set to 1 When the external interrupt 2 is selected as the A D conversion start factor specify the valid edge by the REDGO flag of the external interrupt 2 control register IRQ2ICR or EDGSEL2 flag of the both edges interrupt control register EDGDT Specify the valid interrupt edge before selecting the interrupt factor by the A D conversion start factor When the external interrupt 2 is selected as the A D conversion start factor specify the valid edge by the REDGO flag of the external interrupt 2 control regist
590. ue Set value Calculate d value Set value Calculate d value Set value Calculate d value 2 00 fosc 1 31250 fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 4 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 4 19 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 8 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 8 38 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 10 00 fosc fosc 4 fosc 16 fosc 32 fosc 64 fs 2 fs 4 Operation Chapter 12 Serial interface 1 B Pin Setup with 1 2 channels at transmission Table 12 3 25 shows the pins setup at UART serial interface transmission The pins setup is common to the TXDI pin RXDI pin regardless of whether the pins are independent connected Table 12 3 25 UART Serial Interface Pin Setup with 1 2 channels at transmission Setup item Data output pin Data input pin TXD1 pin RXD1 pin Port pin P15 PA5 P16 PA4 Port pin setup Select used pin A B SCSEL SC1SL Serial data input selection RXD1 SC1MD1 SC1IOM Function Serial data output 1 output SC1MD1 SC1SBOS SC1MD1 SC1SBIS Style Push pull Nch open drain P1ODC P1ODC5 PAODC PAODC5 y o O
591. up When TM6BC matches TM6OC the timer 6 interrupt request flag is set at the next count clock and TM6BC is cleared to 0x00 to restart counting 8 bit Free running Timer VII Chapter 7 Time Base Timer Free running Timer If the TM6CLRS flag of the TM6MD register is set to 0 TM6BC can be initialized at every rewriting of TM6OC register but in that state the timer 6 interrupt is disabled If the timer 6 interrupt should be used set the TM6CLRS flag to 1 after rewriting the TM6OC register On the timer 6 clock source selection if the time base timer output or the time base timer synchronous output is selected the clock setup of time base timer is necessary VII 14 8 bit Free running Timer 7 4 Time Base Timer 7 4 1 Operation Time Base Timer Time Base Timer Interrupt is constantly generated by a selected clock source and a interrupt generation cycle Table 7 4 1 shows the interrupt cycle is combination with the clock source Table 7 4 1 Selection of Time Base Timer Interrupt Generation Cycle Selected clock source Interrupt generation cycle fosc fosc X 1 27 12 8 us fosc X 1 28 25 6 us fosc X 1 29 51 2 us fosc x 1 210 102 4 us fosc x 1 213 819 2 us fosc X 1 215 3 27 ms fx fx x 1 27 3 9 ms fx x 1 28 7 8 ms fx x 1 29 15 6 ms fx x 1 210 31 2 ms fx x 1 213 250 ms fx x 1 215 1s fosc 10 MHz fx 32 768 kHz Time Base Tim
592. up factor of the serial communication Dummy data TXBUFO 0x03F97 b Set the PADIR2 PADIR1 flag of the Port A pin direction control register PADIR to 0 0 and the PADIRO flag to 1 to set PA2 PA1 to disable the start condition 6 Set the SCOLNG2 0 flag of the serial 0 mode register SCOMDO to 111 to set the transfer bit count as 8 bits 7 Set the SCOSTE flag of the serial 0 mode register SCOMDO to 1 to disable the start condition 8 Set the SCODIR flag of the SCOMDO register to 0 to set MSB as a transfer first bit 9 Set the SCOCE1 flag of the SCOMDO register to 1 to set the reception data input edge as falling 10 Set the SCOCMD flag of the SCOMD1 register to 0 to select the synchronous serial 11 Set the SCOMST flag of the SCOMD1 register to 0 to select the clock slave external slave Set the SCOCKM flag to 0 to select not divided for the clock source 12 Set the SCOSBOS flag of the SCOMD1 register to 0 the SCOSBTS flag of the SCOSBIS register to 1 to set the SBIO pin to the serial data input as the SBOO pin general port the SBTO pin to the transfer clock input output Set the SCOIOM flag 0 to set the serial data input from the SBIO pin 13 Set the interrupt level by the SCOLV1 to 0 flag of the serial 0 UART transmission interrupt control register SCOTICR level 2 14 Set the SCOTIE flag of the SCOTICR register to 1 to enable the interrupt If any inter
593. ut mode 3 Select communication pin 8 Set the SCASL flag of the SCSEL register to 0 to select SCSEL X 3F90 P10 and P11 for communication pins bp3 SC4SL 0 4 Select communication mode address mode 4 Set the I2CGEM flag to 0 to select normal SC4AD1 x 3FA8 communication mode and set I2CADM flag to 0 to bp3 I2CGEM 0 select 7 bits address mode bp2 I2CADM 0 5 Activate serial interface 4 5 Set the SELI2C flag of the SC4AD1 register to 1 to SC4AD1 x 3FA8 activate the serial interface bp7 SELI2C 1 6 Set the slave address 6 Set the slave address to the upper 7 bits of the SC4AD1 SCAADO x 3FA7 register I2CAD7 1 bp7 0 I2CAD7 1 0110011 7 Start communication 7 Master on the bus starts communication Operation 11 Chapter 14 Serial Interface 4 XIV 12 Setup Procedure Description 8 Confirm data transmission reception SCASTR x 3FAB bp7 WRS 0 9 Set transmission data SCATXB x 3FAA bp7 0 SI2CTXB7 0 x 55 8 When the address transmitted from the master matches the slave address set in the SC4AD1 register serial interface 4 interrupt SC4IRQ is generated In the interrupt routine when the WRS flag of the SC4MDO register is 0 this communication is recognized as slave transmission 9 Set the transmission data to the SCATXB register Operation Chapter 15 A D Converter Cha
594. ut pin of LED2 as well Each bit can be selected as output mode by bp6 of the port 5 output mode register PSOMD The port 5 output mode register is set to 1 for output pin of large current Nch Tr and 0 to use as output pin of general current The timer 0 output or the general port output can be set to large current with the combination of bp2 of the port 5 output mode register PSOMD P53 is used as output pin of LED3 as well Each bit can be selected as output mode by bp7 of the port 5 output mode register PSOMD The port 5 output mode register PSOMD is set to 1 for output pin of large current Nch Tr and 0 to use as output pin of general current The timer 0 output or the general port output can be set to large current with the combination of of the port 5 output mode register P5OMD Port 5 Chapter 4 Ports 4 5 2 Registers Table 4 5 1 shows the registers that control the port 5 Table 4 5 1 Port 5 Control Register P5OUT 0x03F15 Port 5 output register 41 P5IN 0 03 25 Port 5 input register 42 P5DIR 0x03F35 R W Port 5 direction control register 42 P5PLU 0x03F45 R W Port 5 pull up resistor control register IV 43 P5OMD OxO3F2C R W Port 5 output mode register IV 44 R W Readable Writable Port 5 output register PSOUT 0x03F 15 m p p F p p T pe ree meus ros eo our Po At reset Access R W R
595. utput mode P1DIR P1DIR5S PADIR PADIR5 Pull up setup Added not added P1PLUD P1PLUD5 PAPLU PAPLUS Operation XII 55 Chapter 12 Serial interface 1 B Pin Setup with 2 channels at reception Table 12 3 26 shows the pins setup at UART serial interface reception with 2 channels TXD1 pin RXD1pin Table 12 3 26 UART Serial Interface Pin Setup with 2 channels at reception Setup item Data output pin Data input pin TXD1 pin RXD1 pin Port pin P15 PA5 P16 PA4 Port pin setup Select used pin A B SCSEL SC1SL Serial data input selection RXD1 SC1MD1 SC1IOM Function Port Serial data input SC1MD1 SC1SBOS SC1MD1 SC1SBIS Style Input mode P1DIR P1DIR6 PADIR PADIR7 Pull up setup XII 56 Operation B Pin Setup with 1 channel at reception Chapter 12 Serial interface 1 Table 12 3 27 shows the pin setup at UART serial interface reception with 1 channel pin RXD1 pin in not used so can be used as a port Table 12 3 27 UART Serial Interface Pin Setup with 1 channel at reception Setup item Data output pin Data input pin TXD1 pin RXD1 Port pin P15 PA5 P16 PA4 Port pin setup Select used pin A B SCSEL SC1SL Serial data input selection TXD1 SC1MD1 SC1IOM Function Port Serial data input SC1MD1 SC1SBOS SC1MD1 S
596. uts the PWM waveform which is determined by the match timing for the compare register and the overflow timing of the binary counter 5 7 1 Operation Operation of 8 bit PWM Output Timer 0 and 2 The PWM waveform with an arbitrary duty cycle is generated by setting the duty cycle of PWM period to the compare register The cycle is the period from the full count to the overflow of the 8 bit timer Table 5 7 1 shows PWM output pins Table 5 7 1 Output Pins of PWM Output Timer 0 Timer 2 PWM output pin TMOIO output pin P14 TM2IO output pin P16 8 bit PWM Output Chapter 5 8 bit Timers Count Timing of PWM Output at Normal Timer 0 and 2 Count clock AE UE wae TMnEN flag Compare a i register GE ce counter TMnIO output A B PWM output Time the compare regiser PWM basic components overflow time of binary counter Interrupt request flag Figure 5 7 1 Count Timing of PWM Output at Normal source waveform when TMnPOP flag is set to 0 A is while counting up from 0x00 to the value stored in the compare register B is L after the match to the value in the compare register then the binary counter continues counting up till the overflow 8 bit PWM Output V 35 Chapter 5 8 bit Timers Count Timing of PWM Output when the compare register is 0x00
597. when block 1 2 and 3 are programmed separately 3 pro gramming count is added Therefore program several blocks together to reduce the pro gramming count Boot area stores the loader program for onboard serial programming Boot area can be pro grammed by the PROM writer only Flash EEPROM XVII 3 Chapter 17 Appendix 17 2 PROM Writer Mode 17 2 1 Overview In PROM writer mode the CPU is halted for the internal flash EEPROM to be programmed The microcntroller 15 inserted into a dedicated adaptor socket which connects to a PROM writer When the microcontroller connects to the adaptor socket it automatically enters PROM writer mode The programming adaptor differs depending on the writer and the package type Table 17 2 1 Programming Adaptor List Programming Writer Product Number By Ando Electric Co Ltd TEFO009 CF78A48 48 pin By Panax Matching information of the dedicated writer is posted on our semiconductor website which is listed on the last page of this manual B Fixing a Device on the Adapter Socket and the Position of No 1 Pin Set the No 1 pin of the device to this position 1 Pin Figure 17 2 1 Fixing a Device on the Adapter Socket and the Position of No 1 Pin XVII 4 PROM Writer Mode Chapter 17 Appendix 17 3 Onboard Serial Programming Mode 17 3 1 Overview The onboard serial programming mode is primarily used to program the flash EE
598. x00 TMnIO output timer output is inverted 8 bit Timer Pulse Output TMnIO output The TMnIO pin outputs signals of 2 x cycle of the setup value in the compare register If the binary counter V 31 Chapter 5 8 bit Timers 32 5 6 2 Setup Example Timer Pulse Output Setup Example Timer 0 1 2 and 3 TMOIO pin outputs 50 kHz pulse by using timer 0 For this select fs 2 for clock source and set a 1 2 cycle 100 kHz for the timer 0 compare register at fs 10 MHz An example setup procedure with a description of each step is shown below Setup Procedure Description 1 Stop the counter TMOMD 0x03F54 bp3 TMOEN 0 2 Set the special function pin to the output mode P1OMD 0x03F1C P1OMDO 1 P1DIR 0x03F31 P1DIRO 1 3 Select the normal timer operation TMOMD 0x03F54 bp4 TMOPWM 0 bp5 TMOMOD 0 4 Select the count clock source TMOMD 0x03F54 bp2 0 2 0 01 5 Select and enable the prescaler output CKOMD 0x03F56 bp2 1 TMOPSC1 0 X0 TMOBAS 1 6 Set the timer pulse output cycle 0x03F52 20x31 7 Start the timer operation TMOMD 0x03F54 bp3 TMOEN 1 1 Set the TMOEN flag of the timer 0 mode register TMOMD to O to stop timer 0 counting 2 Set the P10MDO flag of the port 1 output mode register P10MD to 0 to set P10 pin to the special function pin Set the TMOMOD flag of the port 1 direction c
599. x03F54 bp3 TMOEN 1 10 Set the TMOIE flag of the TMOICR register to 1 to enable the interrupt 11 Set the TMOEN flag of the TMOMD register to 1 to operate the timer 0 Every time TMOBC detects the falling edge of TMOIO input TMOBC counts up from 0x00 When TMOBC reaches the setting value of TMOOC register the timer 0 interrupt request flag is set at the next count clock then the value of TMOBC becomes 0x00 and counting up is restarted 30 8 bit Event Count 5 6 8 bit Timer Pulse Output Chapter 5 8 bit Timers 5 6 1 Operation The TMnIO pin can output a pulse signal at any frequency Operation of Timer Pulse Output Timer 0 1 2 and 3 The timers can output signals of 2 x cycle of the setup value in the compare register TMnOC Output pins are as follows Table 5 6 1 Timer Pulse Output Pin Timer 0 Timer 1 Timer 2 Timer 3 Pulse output TMOIO 2 output output output output P14 P70 P16 P71 Count Timing of Timer Pulse Output Timer 0 1 2 and 3 Count TMnEN im uL MM NO 17 742 3 flag E in Lar m 7 S n Qu ci x E Compare ME ME EE NT LO HIE 7 i lt register t coni n 2000 ON 2000 counter Interrupt request flag Figure 5 6 1 Count Timing of Timer Pulse Output Timer 0 1 2 and 3 reaches the compare register and the binary counter is cleared to 0
600. y bit of the used data on transmission reception should have the same polarity B Transfer Bit Count Setup The transfer bit count is automatically set after the frame mode is specified by the SCOFM1 to 0 flag of the SCOMD2 register If the SCOCMD flag of the SCOMDI register is set to 1 and UART communication is selected the setup by the synchronous serial transfer bit count selection flag SCOLNG2 to 0 is no longer valid Data Input Pin Setup 2 channels type data output pin TXDO pin data input pin RXDO pin 1 channel type data I O pin TXDO pin can be selected as a communication mode The RXDO pin can be used only for serial data input The TXDO pin can be used for serial data input or output Whether the serial data is input from RXDO or TXDO it can be selected by the SCOIOM flag of the SCOMDI register When data input from TXDO pin is selected to set the 1 channel communication transmission reception can be switched by the TXDO pin direction control For TXDOA pin it can be done by the PADIR2 flag of the PADIR register For TXDOB by the P7DIRS flag of the P7DIR register Atthe same time the RXDO pin can be used as a general port Reception Buffer Empty Flag When SCORIRQ is generated data is stored automatically to RXBUFO from the internal shift register When data is stored to RXBUFO from the shift register the reception buffer empty flag SCOREMP of the SCOSTR register is setto 1 That indicates that the receiv
601. y the TM7EN flag of the TM7MDI register When 1 count opera tion is selected count continues counting until 0 count stop is set Make sure to set the TM7IGBTO 1 of the TM7MD3 register before operating TM7EN flag of the TM7MDI register 16 bit Standard IGBT Output Timer 7 The IGBT waveform of any duty is generated by setting the duty of period to the compare register 1 TM7OC1 and detecting the trigger that is generated by the external interrupt after the external interrupt interface block has passed The cycle is the full count overflow time of the 16 bit timer The following shows IGBT output pins types of the selectable IGBT trigger and the setting of the interrupt flags Table 6 10 1 IGBT Output Pin Timer 7 IGBT output pin TM71O output P13 TM7O output P51 16 bit Standard IGBT Output Only duty can be changed consecutively 65 Chapter 6 16 bit Timers Table 6 10 2 IGBT Trigger Timer 7 mode register 3 T7IGBTTR IRQO falling edge 01 IRQO 1 IRQO rising edge 01 IRQO 0 IRQ1 falling edge 10 IRQ1 1 IRQ1 rising edge 10 IRQ1 0 IRQ2 falling edge 11 IRQ2 1 IRQ2 rising edge 11 IRQ2 0 TM7EN count operation 00 VI 66 16 bit Standard IGBT Output Only duty can be changed consecutively Chapter 6 16 bit Timers Count Timing of Standard IGBT Output At Normal Count Clock TM7EN Flag
602. ycle of noise remove function And this register also sets the AC zero cross detection function to IRQI Table 3 3 4 Noise Filter Control Register NFCTR 0x03F2E 6 5 2 1 NF1SCK1 NF1SCKO NFOSCK1 NFOSCKO 0 0 0 0 P55IM Description ACZ input enable flag 0 Disable ACZ input 1 Enable ACZ input 6 5 NF1SCK1 NF1SCKO IRQ1 noise sampling period 00 fosc 01 fosc 27 10 fosc 28 11 fosc 29 NF1ENM IRQ1 noise filter setup 0 Noise filter OFF 1 Noise filter ON P54IM ACZO input enable flag 0 ACZO interrupt disable 1 ACZO interrupt enable 2 1 NFOSCK1 NFOSCKO IRQO noise sampling period 00 fosc 01 fosc 2 10 fosc 28 11 fosc 29 NFOENM Ill 48 External Interrupts IRQO noise filter setup 0 Noise filter OFF 1 Noise filter ON Chapter 3 Interrupts Both Edges Interrupt Control Register EDGDT The both edges interrupt control register EDGDT selects interrupt edges of IRQ2 Interrupts are generated at both edges or at single edge The external interrupt control register IRQ2ICR specifies whether interrupts are generated Table 3 3 5 Both Edges Interrupt Control Register EDGDT 0x03F1E 2 EDGSEL1 0 Description EDGSEL1 IRQ2 both edges interrupt selection 0 Programmable active edge interrupt selection 1 Both edges interrupt selection External Inte
603. zation wait time control register DLYCTR is set to select the oscillation stabilization wait time At releasing from reset oscillation stabilization wait time is fixed The timer that counts oscillation stabilization wait time is also used as a watchdog timer That is used as a run away detective timer at anytime except at releasing from reset and at recovering from STOP mode Watchdog timer is initiated at reset and at STOP mode and starts counting from the initialize value 0x0000 when system clock fs is as clock source Block Diagram of Oscillation Stabilization Wait Time watchdog timer NRST STOP writeWDCTR HALT fs internal reset WDEN R 1 2 to 1 214 R 1 27 to 1 220 DLYCTR m m internal reset release 15 214 15 210 5 26 YY YY fs 22 MUX fs 220 18 fs 2 gt gt WDIRQ 15 216 Figure 2 6 3 Block Diagram of Oscillation Stabilization Wait Time watchdog timer Reset Chapter 2 CPU Basics Oscillation Stabilization Wait Time Control Register DLYCTR Table 2 6 1 Oscillation Stabilization Wait Time Control Register DLYCTR 0x03F03 Description Output selection 0 Port data output 1 Buzzer output Buzzer output frequency selection 000 fosc 2 4 001 fosc 21 010 fosc

MN101C78A/F78A LSI User`s Manual - Digi-Key

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