Home

SN32F100 Spec.

1. BK LI Channel length Channel length DS Ne Left za Right SD msb lsb 0 0 O msb lsb 0 0 0 msb Data length BCLK Left WS Channel length Channel length gu Left Right Justified SD msb lsb 0 0 0 msb lsb 0 0 0 msb Data length nn nil Right WS E Channel length d Channel length Justified SD 0 0 0 msb lsb 0 0 0 msb lsb 0 0 0 ms Data length SONiX TECHNOLOGY CO LTD Page 137 Version 1 4 NI N y SN32F100 Series N N A AN 32 Bit Cortex M0 Micro Controller Channel Length Data Length
2. BCLK DS po SD msb Isb msb Isb msb BCLK Left WS Justified SD msb lsb msb lsb msb BCLK Right WS Justified SD msb lsb msb lsb msb SONiX TECHNOLOGY CO LTD Page 138 Version 1 4 SONA 13 5 2 12S FIFO OPERAION 13 5 2 1 MONO 8bit N 3 N 2 N 1 N N 7 N 6 N 5 N 4 16bit N 1 N N 3 N 2 24 bit N N 1 32 bit N N 1 13 5 2 2 STEREO 8bit RIGHT 1 LEFT 1 RIGHT LEFT RIGHT 3 LEFT 3 RIGHT 2 LEFT 2 16bit RIGHT LEFT RIGHT 1 LEFT 1 24 bit LEFT RIGHT 32 bit LEFT RIGHT SONiX TECHNOLOGY CO LTD Page 139 SN32F100 Series 32 Bit Cortex MO Micro Controller Version 1 4 N Aa y 2FI j S Q N B N 32 Bit kuer andes 13 6 12S REGISTERS Base Address 0x4001 A000 13 6 1 12S Control register I28 CTRL Address Offset 0x00 Note START bit shall be set at last 12SEN 128 enable bit 0 Disable 1 Enable 12S I2SMOD 128 mode select bit 0 12S mode for external I2S interface If I2SEN 1 and I2SMOD 0 HW will switch GPIO to DIN DOUT MCLK BCLK and WS 1 Codec mode for internal I2S interface connected to ADC and DAC If I2SEN 1 and I28MOD 1 HW will switch channel length 32bits BCLK MCLK 4 Standard I2S format 12S master and I2S mono mode
3. SSA Note Connect the Crystal Ceramic and C as near as possible to the XIN XOUT VSS pins of MCU e Structure 1MHz 25MHz EHS external crystal ceramic resonator e Main Purpose System high clock source RTC clock source and PLL clock source e Warm up Time 2048 Feus XIN XOUT Shared Pin Selection Oscillator Mode XTALIN pin XTALOUT pin IHRC GPIO GPIO EHS X TAL Crystal Ceramic Crystal Ceramic SONG TECHNOLOGY CO LTD Page 46 Version 1 4 N NS NY SN32F100 Series N D A A 32 Bit Cortex M0 Micro Controller The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time The loading capacitance values must be adjusted according to the selected oscillator The EHS crystal is switched on and off using the EHSEN bit in Analog Block Control register SYSO ANBCTRL 3 2 3 3 Audio External High speed AUEHS Clock Note Connect the Crystal Ceramic and C as near as possible to the AUXTALIN AUXTALOUT VSS pins of MCU Structure 1MHz 25MHz AUEHS external crystal ceramic resonator e Main Purpose Audio high clock source e Warm up Time 2048 Fayeus AUXTALIN AUXTALOUT Shared Pin Selection Oscillator Mode AUXTALIN pin AUXTALOUT pin ze GPIO GPIO AUEHS X TAL Crystal Ceramic Crystal Ceramic The resonator and the load cap
4. 16bitx2 4 1 1 8 32 LQFP48 32 bit x 2 SN32F108F 64KB 8KB ake 50MHz 2 1 2 16bitx2 6 1 1 17 46 LQFP64 32 bit x 2 SN32F109F 64KB 8KB 4KB 50MHz 2 2 2 1 16bitx2 6 1 1 24 62 LQFP80 32 bit x 2 SONiX TECHNOLOGY CO LTD Page 14 Version 1 4 SN32F100 Series 32 Bit Cortex M0 Micro Controller NONA 1 2SYSTEM BLOCK DIAGRAM SWDIO TEST DEBUG SWCLK INTERFACE FLASH ROM SRAM MER pia ES REGULATOR VDD 1 8V 3 6V ARM CORTEX MO AHB LITE BUS VCORE XTALIN FLASH ROM AUXTALIN BOOT LOADER LXTALIN 4KB XTALOUT Per CLOCK GENERATION Clocks LXTALOUT CLKOUT AHB TO APB POWER CONTROL BRIDGE Controls SYSTEM FUNCTIONS RESET nds Comparator GPIO ports i PIOO 0 15 en GPIO PIO1 0 13 UTXDO PIO2 0 15 PIO3 0 15 VOUTP URXD1 o M VOUTN ios UART 1 3 16 bit Sigma delta DAC VMDNCOM m AVDD AVSS amp AVDD_DRV seko AVSS DRV V PI pit Sigma MIC PIMIC N MISOO SPIO 16 bit Sigma delta ADC MIC BIAS MOSIO VMID AVDD AVSS SCH V gem ER CT32B0 PWM 1 0 Mod CT32B0 CAPO SCLO SDAO 1200 CT32B1 PWM 1 0 CT32B1 CAPO Pr CT16B0 PWMIO CT16BO CAPO I28BCLK I2SWS i 12SDIN 128 Mn 1 Gei l CT16B1 PWMIO BEROUT CT16B1 CAPO I28MCLK SONiX TECHNOLOGY CO LTD Page 15 Version 1 4 Ns y SON IX NEE 1 3 CLOCK GENERATION BLOCK DIAGRAM AHB clock for AHB t
5. CT32Bn PWMx CT32Bn CAPO MRxSTO CEN CRST gt ee y Mt Keen A RESET _MRXRST MM PWMxEN 99 PWMxIOEN Y gt EMCx gt CAPO CAPOEN gt CAPOFE m CAPOI CAPORE CAPO Interrupt SONiX TECHNOLOGY CO LTD Page 82 Version 1 4 NI A WV S d A N 32 Bit 2 _ 7 5TIMER OPERATION The following figure shows a timer configured to reset the count and generate an interrupt on match The CT32Bn PRE register is set to 2 and the CT32Bn MRx register is set to 6 At the end of the timer cycle where the match occurs the timer count is reset This gives a full length cycle to the match value The interrupt indicating that a match occurred is generated in the next clock after the timer reached the match value PCLK LN JA PA LO CT32Bn PC 2 0 1 2 0 1 2 0 CT32Bn TC 4 5 6 0 TC Reset ia Interrupt N The following figure shows a timer configured to stop and generate an interrupt on match The CT32Bn PRE register is set to 2 and the CT32Bn MRx register is set to 6 In the next clock after the timer reaches the match value the CEN bit in CT32Bn TMRCTRL register is cleared and the interrupt indicating that a match occurred is generated PCLK CT32Bn PC 2 0 1 2 0 CT32Bn TC 4 5 6 CEN bit 1 0 Interrupt SONG TECHNOLOGY CO L
6. When Counter Mode is chosen as a mode of operation the CAP input selected by the CIS bits is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by CTM bits in this register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the CAP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently the duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 x PCLK Note If Counter mode is selected in the CNTCTRL register Capture Control CAPCTRL register must be programmed as 0x0 Reserved Een Pit CIS 1 0 Count Input Select In counter mode when CTM 1 0 are not 00 these bits select which CAPO pin is sampled for clocking 00 CT16Bn CAPO Other Reserved i CTM 1 0 Counter Timer Mode This field selects which rising PCLK edges can clear PC and increment Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Counter Mode TC is incremented on rising edges o
7. I28 DIV CLK O CLK O PAEO CLKO_EN 13 4 2 125 BLOCK DIAGRAM I2SMCLK I28 CTRL lt gt I2SWS 8 x 32 bit FIFO 28 CLOCK CONTROL I2SBCLK 4 12S_FIFO lt SERIAL ENCODER g I2SDIN EET 2SDOUT 128 STATUS I2S RIS gt 12S Interrupt I25 IE SONiX TECHNOLOGY CO LTD Page 134 Version 1 4 N No WY SN32F100 Series S Q d E N 32 Bit Cortex M0 Micro Controller 13 4 3 16 Bit Sigma Delta ADC BLOCK DIAGRAM IREFGEN CKGEN SONiX TECHNOLOGY CO LTD Page 135 Version 1 4 S y SONIX RE 13 4 4 16 Bit Sigma Delta DAC BLOCK DIAGRAM 3 3V 3 3V 3 3V 0 1uF 0 1uF 0 1uF A 10uF 10uF 10uF VSD DAC VD DAC VSA DAG VA DAC VSA DAC IO VA DAC IO DX EN EN EN EN DX E gt VOP 3 3V 220pF HeadPhone VA DRV Driver Ka X 10uH 0 1uF VSA DRV R DX DR 220pF VOUTN 10uF IREFGEN VREFGEN oS gt VON DX DX COM VMID 4 7JE O luF4 fuF 0 1uF SONiX TECHNOLOGY CO LTD Page 136 Version 1 4 SON roer 32 Bit Cortex M0 Micro Controller 13 5 FUNCTIONAL DESCRIPTION 13 5 1 12S OPERATION gt Standard 12S gt Right justified Data Format gt MSB Left justified Data Format Channel Length gt Data Length
8. Reset timer on match with optional interrupt generation gt One CT16B0 or CT16B1 PWM output corresponding to match register with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match gt For each timer one match register MRO can be configured as PWM allowing to use one match output as single edge controlled PWM output 6 3 PIN DESCRIPTION iption on P y CT16Bn CAPO Capture channel input 0 Depends on GPIOn CFG CT16Bn PWMx Output channel x of Match PWM output rece EE EEN SONG TECHNOLOGY CO LTD Page 72 Version 1 4 SONIX 6 4 BLOCK DIAGRAM SN32F100 Series 32 Bit Cortex MO Micro Controller MRxSTOR DS CEN CRST HIR gt i l STOP gt MRX D MRE PCLK MRx Interrupt pp TC gt RESET MRxRST DS gt PWMxEN gt PWMxIOEN Y gt CT16Bn_PWMx EMCx 2 CAPO APOEN k A CT16Bn CAPO CAPOFE gt CAPOT CAPORE gt CAPO Interrupt SONG TECHNOLOGY CO LTD Page 73 Version 1 4 NI WV O d A N 32 Bit 2 Fono 6 5 TIMER OPERATION The following figure shows a timer configured to reset the count and generate an interrupt on match The CT16Bn PRE register is set to 2 and the CT16Bn_MRx register is set to 6 At the end of the timer cycle where the match occurs the time
9. The selection is controlled by the CLKOUTSEL bits in SYS1 AHBCLKEN register SONG TECHNOLOGY CO LTD Page 49 Version 1 4 I i SONIX vr rlend 3 3 SYSTEM CONTROL REGISTERS 0 Base Address 0x4006 0000 3 3 1 Analog Block Control register SYSO ANBCTRL Address Offset 0x00 Reset value 0x0000 0001 Note EHSEN ELSEN IHRCEN bit can NOT be cleared if the EHS X tal ELS X tal IHRC is selected as system clock or is selected to become the system clock lame Reserved X Bit Description AUEHSFREQ Frequency range of AUEHS X TAL 0 lt 12MHz 1 gt 12MHz AUEHSEN Audio external high speed clock enable 0 Disable AUEHS X TAL 1 Enable AUEHS X TAL EIE N Frequency range driving ability of EHS X TAL 0 lt 12MHz 1 gt 12MHz INE External high speed clock enable 0 Disable EHS X TAL 1 Enable EHS X TAL ELSEN External low speed oscillator enable 0 Disable External 32 768 KHz oscillator 1 Enable External 32 768 KHz oscillator pe oem Internal high speed clock enable 0 Disable internal 12 MHz RC oscillator 1 Enable internal 12 MHz RC oscillator 3 3 2 PLL control register SYSO PLLCTRL Address Offset 0x04 Note PLLEN bit can NOT be cleared if the PLL is selected as system clock or is selected to become the system clock Name Reserved PLLEN PLL enable 0 Disable 1 Enable 1 Reserved SONG TECHNOLOGY CO LTD Page 50 Version 1 4
10. 0 No effect 1 Reset CT16B1 CT16BO reset 0 No effect 1 Reset CT16BO GPIO port 3 reset 0 No effect 1 Reset GPIO port 3 GPIO port 2 reset 0 No effect 1 Reset GPIO port 2 GPIO port 1 reset 0 No effect 1 Reset GPIO port 1 GPIO port 0 reset 0 No effect 1 Reset GPIO port 0 SONG TECHNOLOGY CO LTD Page 60 SN32F100 Series 32 Bit Cortex MO Micro Controller Version 1 4 I NI y SN32F100 Series O N a AN 32 Bit Cortex M0 Micro Controller d SYSTEM OPERATION MODE 4 1 OVERVIEW The chip builds in four operating mode for difference clock rate and power saving reason These modes control oscillators op code operation and analog peripheral devices operation Normal mode Sleep mode Deep sleep mode Deep Power down mode VVVV 4 2 NORMAL MODE In Normal mode the ARM Cortex MO core memories and peripherals are clocked by the system clock The SYS1 AHBCLKEN register controls which peripherals are running Selected peripherals have individual peripheral clocks with their own clock dividers in addition to the system clock The peripheral clocks can be disabled respectively The power to various analog blocks IHRC EHS X TAL ELS X TAL PLL Flash LVD Codec Comparator can be controlled at any time individually through the enable bit of all blocks 4 3LOW POWER MODES There are three special modes of processor power reduction Sleep mode Deep sleep mode and Deep power down mode The PMU CTR
11. 0 to 15 0 No effect on Pn x 1 Clear Pn x 5 3 12 GPIO Port n Open Drain Control register GPlOn ODCTRL nz0 1 2 3 Address offset 0x2C Several I Os have built in open drain function and must be set as output mode when enable open drain function Open drain external circuit is as following SONG TECHNOLOGY CO LTD Page 70 Version 1 4 I No AM SN32F100 Series S Q d A N 32 Bit Cortex M0 Micro Controller MCU1 MCU2 VG oO Pull upResistor ull up Y Open drain pin Open drain pin The external pull up resistor is necessary The digital output function of VO only supports sink current capability so the open drain output high is driven by pull up resistor and output low is sunken by MCU s pin Gu See Pn150C NM P3 s open drain control bit Pn140C P3 14 open drain control bit 0 Disable 1 Enable HW set P3 14 as output mode automatically n 0 2 Reserved Pn130C n 3 P3 13 open drain control bit 0 Disable 1 Enable HW set P3 13 as output mode automatically n 0 2 Reserved Pn120C n 3 P3 12 open drain control bit 0 Disable 1 Enable HW set P3 12 as output mode automatically n 0 2 Reserved AC Pn3OC PO s open drain control bit 0 Disable 1 Enable HW set P0 3 as output mode automatically n 1 3 Reserved Pn20C an PO 2 open drain control bit 0 Disable 1 Enable HW set PO 2 as output mode automatically n 1 3 Reserved Pn1OC n 0 PO 1 open drain control bit 0 Disable 1 Enable H
12. 7 Vdd 2 5V 1 Word 32 bits 60 MISC 2 1 90 2 30 ar Reset T 25C Vdd 1 8V 3 6V MEE ed Fire 7400 85C Vdd 1 8V 3 6V These parameters are for design reference not tested 1 IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull up resistors disabled and VDD 3 3V 2 LVD and all peripherals are disabled 3 IHRC and ILRC are enabled external X tal are disabled and PLL is disabled 4 IHRC is disabled external high X tal is enabled and PLL is enabled 5 ILRC is enabled IHRC and external X tal are disabled and PLL is disabled 6 All oscillators and analog blocks are turned off 7 DPDWAKEUP pin is pulled HIGH internally 313 5 5 3 7 Pageerasetime Tee Vdd 2 5V 1 Page 1024 bytes 0 1 Word Programming time 0 us C R EN PG PE PG VD T L Low Voltage Detector SONiX TECHNOLOGY CO LTD Page 170 Version 1 4 N y 7 SONAX NEE 18 3 CHARACTERISTIC GRAPHS The Graphs in this section are for design guidance not tested or guaranteed In some graphs the data presented are outside specified operating range This is for information only and devices are guaranteed to operate properly only within the specified range IHRC ILRC 13 00 See 12 80 18605 ed ER 12 60 ED SS ol o LLL 18 00 gt d 1240
13. Comparator Negative Signal Vn Comparator Output Signal CMPOUT Comparator Output Signal After De bounce i Trigger to De bounce X P De bounce End De bounce End Trigger to De bounce De bounce Time De bounce Time 4 SONiX TECHNOLOGY CO LTD Page 153 Version 1 4 I N y SN32F100 Series O N A X 32 Bit Cortex M0 Micro Controller The comparator positive input terminal includes internal reference voltage source The internal reference voltage source supports three levels which are 1 4 Vdd CMPS 1 0 00 1 2 Vdd CMPS 1 0 01 and 3 4 Vdd CMPSI1 0 10 11 The comparator negative input terminal supports maximum 24 channel controlled by CMCH 4 0 00000 P2 0 00001 P2 1 00010 P2 2 00011 P2 3 00100 P2 4 00101 P2 5 00110 P2 6 00111 P27 01000 P2 8 01001 P2 9 01010 P2 10 01011 2 P2 11 01100 P2 12 01101 P2 13 01110 P2 14 01111 P2 15 10000 P3 0 10001 P3 1 10010 P3 2 10011 P3 3 10100 P3 4 10101 P3 5 10110 P3 6 10111 P3 7 These channels selected is only when the comparator enables CMPEN 1 the 24 channel analog switch works or not workable If one pin is selected to be comparator negative input pin the pin is Switched to input mode and connected to comparator negative input terminal When the system selects to other pin or comparator disables the original channel will returns to last GPIO mode automatically The comparator output status can output to CMO pin
14. gt Counter or timer operation gt Two 32 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt gt The timer value may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge gt Four 32 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation Reset timer on match with optional interrupt generation gt Up to two CT32B0 or CT32B1 PWM outputs corresponding to match registers with the following capabilities Set LOW on match Set HIGH on match Toggle on match Do nothing on match gt For each timer up to two match registers MRO MR1 can be configured as PWM allowing to use up to two match outputs as single edge controlled PWM outputs 7 3PIN DESCRIPTION F i De iption D Con ration CT32Bn CAPO Capture channel input 0 Depends on GPlOn CFG pO CT32Bn PWMx O Output channel x of Match PWM output SONG TECHNOLOGY CO LTD Page 81 Version 1 4 SONIA 7 4BLOCK DIAGRAM SN32F100 Series 32 Bit Cortex M0 Micro Controller gt MRx Interrupt
15. 0x4003 2000 4 7 1 Backup registers 0 to 15 PMU_BKPO 15 Address Offset 0x0 0x04 0x08 OxOC 0x10 0x14 0x18 Ox1C 0x20 0x24 0x28 Ox2C 0x30 0x34 0x38 Ox3C The backup registers retain data through the Deep power down mode when power is still applied to the VDD pin but the chip has entered Deep power down mode Note Backup registers will be reset only when all power has been completely removed from the chip mir DIL lame 31 8 Reserved BACKUPDATA 7 0 BACKUPDATA Data retained during Deep power down mode 4 7 2 Power control register PMU CTRL Address Offset 0x40 The power control register selects whether one of the ARM Cortex MO controlled power down modes Sleep mode or Deep sleep mode or the Deep power down mode is entered and provides the flags for Sleep or Deep sleep modes and Deep power down modes respectively X Note The PMU CTRL register retains data through the Deep power down mode when power is still applied to the VDD pin and will be reset only when all power has been completely removed from the chip Bit Name Reserved SLEEPEN Sleep mode enable 0 Disable 1 Enable WEI instruction will make MCU enter Sleep mode BE nd Deep sleep mode enable 0 Disable 1 Enable WEI instruction will make MCU enter Deep sleep mode KB Deep power down mode enable 0 Disable 1 Enable WEI instruction will make MCU enter Deep power down mode
16. 1 Clear RXOVFIF bit 10 6 8 SSP n Data register SSPn DATA n 0 1 Address Offset 0x1C 3116 Reserved bn DATA 15 0 Write R W SW can write data to be sent in a future frame to this register when TX FULL 2 0 in SSPn STAT register TX FIFO is not full If the TX FIFO was previously empty and the SSP controller is not busy on the bus transmission of the data will begin immediately Otherwise the data written to this register will be sent as soon as all previous data has been sent and received Read SW can read data from this register when RX_EMPTY 0 in SSPn STAT registe Rx FIFO is not empty When SW reads this register the SSP controller returns data from the least recent frame in the RX FIFO If the data length is less than 16 bit the data is right justified in this field with higher order bits filled with Os SONiX TECHNOLOGY CO LTD Page 108 Version 1 4 I NI y SN32F100 Series S N A X 32 Bit Cortex M0 Micro Controller 11 nc 11 1 OVERVIEW The I2C bus is bidirectional for inter IC control using only two wires Serial Clock Line SCL and Serial Data line SDA Each device is recognized by a unique address and can operate as either a receiver only device e g an LCD driver or a transmitter with the capability to both receive and send information such as memory Transmitters and or receivers can operate in either master or slave mode depending on whether the chip has to initiate a data transfer or is only addre
17. 11 8 10 I2C n Monitor Mode Control register I2Cn MMCTRL n 0 1 Address Offset 0x30 This register controls the Monitor mode which allows the I2C module to monitor traffic on the DC bus without actually participating in traffic or interfering with the 12C bus In Monitor mode SDA output will be forced high to prevent the I2C module from outputting data of any kind including ACK onto the 12C data bus Depending on the state of the SCLOEN bit the SCL output may be also forced high to prevent the module from having control over the I2C clock line Note The SCLOEN and MATCH ALL bits have no effect if MMEN bit is 0 i e if the module is NOT in monitor mode 83 8 Reserved bn MATCH ALL Match address selection R W 0 Interrupt will only be generated when the address matches one of the values in I2Cn SLVADDRO 3 register 1 If I2C is in monitor mode an interrupt will be generated on ANY address received This will enable the part to monitor all traffic on the bus SCL output enable bit SELOEN 0 SCL output will be forced high Ban 1 12C module may act as a slave peripheral just like in normal operation the I2C holds the clock line low until it has had time to respond to an I2C interrupt MMEN Monitor mode enable bit R W 0 Disable 1 Enable SONiX TECHNOLOGY CO LTD Page 117 Version 1 4 NONA ene ados 12 UNIVERSAL ASYNCHRONOUS SERIAL RECEIVER AND TRANSMITTER UART 121 OVERVIEW
18. 7 ADGEN ADCpower onenable activeHigh RAW 0 L5 Reseved OA S R f o 5 MERTEN MiCBOOSTpoweronenabe aciveHigh RW 0 4 PGAEN PGApoweronenable aciveHign RW 0 90 Reserved pp R 0 13 7 21 ADC Setting 22 register ADC SET22 Address Offset Ox6C0 Bi Name Description Attribute Reset 314 Reserved 0 0 0 0 RR 38 IREFLEN IREFcircuitenable active High RW 0 2 VREFEN VhRtFeiruitenabe aciveHigh DW 0 1 MICBEN Microphone bias enable active High RW 0 0 CK EN CKGENenable aciveHigh RW 0 13 7 22 ADC Setting 23 register ADC SET23 Address Offset Ox6DO Reserved SEL_MICB TEEN Bias Output select 0 0 8 VA 1 Ee 3 Reserved SEL MIC P1 Let SUE SEC en EER and P1 8 MIC_N function selection 0 General purpose IO 1 A A Differential input when ADC is enabled Reserved SEL_MIX_MIC TEER input path to mixer enable 0 Disable 1 Enable SONiX TECHNOLOGY CO LTD Page 148 Version 1 4 NONA sad 13 7 23 ADC Setting 24 register ADC SET24 Address Offset Ox6E0 Bit ame Descriptior OOOO 6 5 BOOST AGC Boost setting value when AGC is on R 40 PGA AGC PGA setting value when AGC is on R 13 8 CODEC DAC REGISTERS Base Address 0x4006 5000 Note Codec DAC Registers are available only when codec mode is selected by I2SMO
19. Address Offset 0x34 After reset the UART will be in full duplex mode meaning that both TX and RX work independently After setting the HDEN bit the UART will be in half duplex mode In this mode the UART ensures that the receiver is locked when idle or will enter a locked state after having received a complete ongoing character reception Line conflicts must be handled in SW The behavior of the UART is unpredictable when data is presented for reception while data is being transmitted For this reason the value of the HDEN register should not be modified while sending or receiving data or data may be lost or corrupted SONiX TECHNOLOGY CO LTD Page 130 Version 1 4 N No wy SN32F100 Series Sv NS A N 32 Bit Cortex M0 Micro Controller 81 1 Reserved HDEN Half duplex mode enable bit 0 Disable 1 Enable SONiX TECHNOLOGY CO LTD Page 131 Version 1 4 I NI y SN32F100 Series N N A X 32 Bit Cortex M0 Micro Controller 13 auno 12S CODEC 13 1 OVERVIEW 13 1 1 125 Description The I2S bus specification defines a 5 wire serial bus having one data in one data out one MCLK clock one BCLK clock and one word select signal The basic I2S connection has one master which is always the master and one slave 13 1 2 Codec Description The SN32F100 mono Codec offers fundamental features suitable for system applications which contains 16 Bit Sigma delta ADC and DAC for audio in and audio out respectively The ADC supports
20. Furthermore the interrupts corresponding to each input must be enabled in the NVIC 4 5STATE MACHINE OF PMU gt Reset Wake up condition Pulling the DPDWAKEUP pin LOW Enter mode condition Reset condition 1 SLEEPEN I Enter mode condition O 2 WFI instruction 1 Pull High WAKEUP pin One of reset trigger sources Y 1 Pull High WAKEUP pin actives 2 DPDEN zl le 3 WFI instruction k Sleep Run gt Deep power down A mode gt mode mode Wake up condition A Interrupt Wake up condition GPIO Wakeup Enter mode condition RTC interrupt 1 DSLEEPEN 1 2 WEI instruction Reset condition One of reset trigger sources actives Y Deep sleep mode SONG TECHNOLOGY CO LTD Page 63 Version 1 4 N o WW SONIX e irie 4 6 OPERATION MODE COMPARSION TABLE ILRC ON OFF PLL OF i OF Cortex MO core oF i i OF F Peripherals By Enable bit of each By Enable bit of each Disable HCLK peripherals peripherals D RTC By RTCEN By RTCEN By RTCEN Wakeup Source N A All interrupts GPIO interrupt DPDWAKEUP pin RESET pin RTC interrupt LV kkk RTCENB RTC_CLKS _ILRC d ELS 0 sa EN x o LRO O x 1 ELS EE o SONG TECHNOLOGY CO LTD Page 64 Version 1 4 W EN O A SN32F100 Seri Q N E AN 32 Bit Cortex M0 4 7PMU REGISTERS Base Address
21. SAT POD AGC Control RAN OXOA The detection period for ADC saturation condition Fs Sampling rate 0000 1 Fs x 2 0 0001 1 Fs x 2 1 1110 1 Fs x 2 14 1111 1 Fs x 2 15 13 7 14 ADC Setting 14 register ADC SET14 Address Offset 0x610 en een E UN AGC OFF AGC Control AGC function 0 Enable 1 Disable BOOST_SET_VAL AGC Control R W 0x03 Boost setting value at normal mode when AGC is on 00 0dB 01 12dB 10 20dB 11 30dB PGA_SET_VAL AGC Control R W 0x10 PGA setting value at normal mode when AGC is on 1 5dB step 00000 Mute 00001 12dB 01001 0dB 11110 31 5dB 11111 33dB 13 7 15 ADC Setting 15 register ADC SET15 Address Offset 0x620 REES ACTIVE A Geng a ae Audio Interface Control 0 Disable 1 Enable Word length of DA interface 00 16 bits 01 18 bits 10 20 bits 11 24 bits 13 7 16 ADC Setting 16 register ADC SET16 Address Offset 0x630 A 0 O R D O i BOOST Boost setting value when AGC is off 00 0dB 01 12dB 10 20dB 11 30dB SONiX TECHNOLOGY CO LTD Page 146 Version 1 4 NONA Ga reden PGA setting value when AGC is off 00000 Mute 00001 12dB 11110 31 5dB 11111 33dB 13 7 17 ADC Setting 18 register ADC SET18 Address Offset 0x650 Eara O R 0 VOL_CTRL Digital Volume attenuation control At the normal mode when AGC is on or R W off 0000 0dB 0001 3dB 0010 6dB 0011 9dB 0100 12dB 0101 15dB 0110 18dB
22. SN32F100 Starter Kit SN LINK USB cable to provide communications between the SN Link and PC IDE Tools KEIL RVMDK N USB Cable to PC gt p SN32F100 Starter Kit SN LINK IDE Tools 17 1 SN LINK SN LINK is a high speed emulator for SONiX 32 bit series MCU It debugs and programs based on SWD protocol In addition to debugger functions the SN LINK also may be used as a programmer to load firmware from PC to MCU for engineering production even mass production SONiX TECHNOLOGY CO LTD Page 164 Version 1 4 NS y SONIX u 17 2 SN32F100 STARTER KIT SN32F 100 Starter kit is an easy development platform It includes SN32F 109 real chip and I O connectors to input signal or drive extra device of user s application It is a simple platform to develop application as target board not ready The starter kit can be replaced by target board because of SN32F100 series MCU integrates SWD debugger circuitry 17 2 1 SN32F100 Start Kit V1 0 DCH Lut SOSA SN32F100 STARTKIT_V1 0 BD_011613 HIR E TD pH 2 E ds I ONE TONS 4 M mn L SONiX TECHNOLOGY CO LTD Page 165 Version 1 4 NONA JP46 Mini USB connector for power supply S1 USB power on off S2 MCU power source is VDD or Writer JP53 VDD power source is 3 3V from board or external power Do not short if External power source is used U4 SN32F109F real chip D9 Power LED RESET button External reset trigger so
23. Step5 PD IREF 1 Step6 PD CLK 1 13 10 3Sigma delta DAC Enable Sequence Step1 DAC Digital Enable DAC EN IN 1 Step2 MCLK Output Enable MCLKOEN 1 and I2S Enable Step3 DAC Analog Enable Sigma delta DAC Power Up Sequence SONiX TECHNOLOGY CO LTD Page 151 Version 1 4 NONA SN32F100 Series 32 Bit Cortex M0 Micro Controller 1 4 24 CHANNEL COMPARATOR 14 4 OVERVIEW The analog comparator compares negative input voltage and then output the result to comparator output terminal The comparator has multi input selection for different applications The comparator negative input terminal is up to 24 channel controlled by CMCH 4 0 The comparator positive input terminal has three selections controlled by CMPSI1 0 bits The comparator output terminal connects to external pin CMO and connects to internal path There is a programmable direction function to decide comparator trigger edge for indicator function The comparator has flag indicator interrupt function and sleep mode weak up function for different application 24 channel negative input selection Comparator output function Comparator unit with programmable output de bounce Programmable trigger direction Interrupt function Sleep mode wake up function CMPEN P2 0 El CMO r21 ET P2 2 CM2 P23 CM3 P2 4 CM4 P2 5 CMS geg Evan d 10 11 M r27 mp ye vaa poly N pas cms uva PA Internal Voltage Bias Source P2 9 CM9 CMPS 1 0 CMD
24. The UART offers a flexible means of full duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format The serial interface is applied to low speed data transfer and communicate with low speed peripheral devices The UART offers a very wide range of baud rates using a fractional baud rate generator 12 2 FEATURES Full duplex 2 wire asynchronous data transfer Single wire half duplex communication 16 byte receive and transmit FIFOs Register locations conform to 16550 industry standard Receiver FIFO trigger points at 1 4 8 and 14 bytes Built in baud rate generator Software or hardware flow control VVVVVVV 12 3 PIN DESCRIPTION UTXDn O Serial Transmit data REESEN URXDn a Serial Receive data Depends on GPIOn_CFG SONiX TECHNOLOGY CO LTD Page 118 Version 1 4 N Es 3 N SN32F100 Series 32 Bit Cortex M0 Micro Controller 12 4 BLOCK DIAGRAM TX gt UARTn TH TSR gt UTXD A UART Baud Rate Generator SCR DLL DLM INTERRUPT RX UARTn IE gt UARTn RB RSR 1 URXD UARTn Il gt UARTn FC UARTn LS UARTn_LC SONiX TECHNOLOGY CO LTD Page 119 Version 1 4 NI M j S d N 32 Bit 2 _ 12 5 BAUD RATE CALCULATION The UART baud rate is calculated as UARTn_PCLK UA
25. Threshold for inactivating AGC High byte Once ADC output is lower than the threshold the check period setting is MUTE CAL POD in ADC_SET11 AGC will update internal digital gain until the PGA and Boost setting are equal to the setting in ADC_SET19 Then the internal digital gain is adjusted to default value Finally the AGC is entering mute mode until the ADC output is over search threshold in ADC SET7 8 ADC_SET8 13 7 10 ADC Setting 10 register ADC_SET10 Address Offset 0x5D0 Reserved ee THL BEG Control Threshold for inactivating AGC Low byte 13 7 11 ADC Setting 11 register ADC SET11 Address Offset 0x5E0 reseed STS A OT CAL POD AGC Control R W The calculating period for inactivating AGC Fs Audio sampling rate 0000 256 Fs x 2 0 0001 256 Fs x 2 1 1110 256 Fs x 2 14 1111 256 Fs x 2 15 AGC will check whether entering mute mode or not according to mute threshold per MUTE CAL POD seconds 13 7 12 ADC Setting 12 register ADC SET12 Address Offset Ox5FO ETEN RE EEE SETS PEE SAT TH AGC Control R W Threshold for ADC saturation condition The saturation condition is for sigma delta ADC if there are more than SAT_TH bit streams are saturating then the internal gain will be adjusted rapidly to avoid the ADC output saturation SONiX TECHNOLOGY CO LTD Page 145 Version 1 4 NONA EE 13 7 13 ADC Setting 13 register ADC SET13 Address Offset 0x600 ETE ES SV SE
26. gt Auto Gain Control AGC gt Common mode output interface lt gt Mute on off vvv SONiX TECHNOLOGY CO LTD Page 132 Version 1 4 SONA Ais Note The Codec circuit requires a 2 7V 3 6V operating voltage supply 13 3 PIN DESCRIPTION 13 3 1 125 Pin Description Pin I GPIO l2SBCLK ToT 128 Bit clock Master mme Km 12S Bit clock Slave Depends on GPIOn_CFG 2SWS O 12SWord Select Master REESEN 1 128 Word Select Slave I2SDIN 12S Received Serial data DependsonGPlOn CFG 12SDOUT O I2S Transmitted Serial data Zoe LO les Master clock output DEE 128 Master clock input from GPIO 13 3 2 Codec Pin Description AVDD_ADC Power supply input pins for Sigma delta ADC AVSS ADC WMID ADC P Sigmardelta ADO VMID output 1 MIC BAS P Sigma deta ADC Microphone Bias Voltage output 7 m AVSS DAC vors AVSS DRV _Sigma delta DAC Common mode output 1 be vom WO Sigma detaDAC output VOUIN vo Sigmadeta DAC output 1 13 3 3 Audio Clock Pin Description AUXTALOUT External high speed X tal output pin for audio Depends on GPlOn CFG AUXTALIN External high speed X tal input pin for audio Depends on GPlOn CFG SONiX TECHNOLOGY CO LTD Page 133 Version 1 4 BONER ear crt te cnt 32 Bit Cortex M0 Micro Controller 13 4 BLOCK DIAGRAM 13 4 1 125 CLCOK CONTROL MCLK SEL DS MCLK MCLKDIV BCLKDIV HCLK PS PCLK
27. 0111 21dB 1000 24dB 1001 27dB 1010 30dB 1011 36dB 1100 42dB 1101 48dB 1110 54dB 1111 78dB MUTE_CTRL Digital Volume attenuation control At the mute mode when AGC is on R W 0000 0dB 0001 3dB 0010 6dB 0011 9dB 0100 12dB 0101 15dB 0110 18dB 0111 21dB 1000 24dB 1001 27dB 1010 30dB 1011 36dB 1100 42dB 1101 48dB 1110 54dB 1111 78dB 13 7 18 ADC Setting 19 register ADC_SET19 Address Offset 0x660 SF EE SG 555 BOOST _ MUTE AGC Control M VAL Boost setting value at mute mode when AGC is enabled 00 0dB 01 12dB 10 20dB 11 30dB PGA_MUTE_VAL AGC Control 0x10 PGA setting value at mute mode when AGC is enabled 00000 Mute 00001 12dB SONiX TECHNOLOGY CO LTD Page 147 Version 1 4 NONA va 01001 0dB 11110 31 5dB 11111 33dB 13 7 19 ADC Setting 20 register ADC SET20 Address Offset 0x670 Reserved ELEME MUTE POD The updating period for Digital Volume attenuation at the normal mute mode when AGC is on Bit 7 4 for normal mode Bit 3 0 for mute mode Fs Sampling rate 0000 1 Fs x 2 0 0001 1 Fs x 24 1 1110 1 Fs x 2 14 1111 1 Fs x 2 15 The volume update when mode transition This is mainly for avoiding large variation of analog gain setting during the transition of normal mode and mute mode 13 7 20 ADC Setting 21 register ADC SET21 Address Offset 0x6BO Descriptic E 58 Resend EP T RT 4
28. 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 5 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 4 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 3 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 2 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 1 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode y y y I o o I I I I I y o o I SONiX TECHNOLOGY CO LTD Page 68 Version 1 4 Y NS 9 NX SN32F100 Series N N A A 32 Bit Cortex MO Micro Controller 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Note HW will switch P1 7 and P1 8 to Microphone differential input if SEL_MIC 1 in ADC SET23 register Setting SEL_MIC 0 before P1 7 and P1 8 as GPIO function Note P0 14 is the input pin only please don t set it to the output function in GPIOO MODE
29. 10 The interrupt assertion threshold voltage is 2 70V 11 The interrupt assertion threshold voltage is 3 00V 3 2 Reserved LVDRSTLVL 1 0 LVD reset level 00 The reset assertion threshold voltage is 2 00V 01 The reset assertion threshold voltage is 2 40V 10 The reset assertion threshold voltage is 2 70V 11 Reserved SONiX TECHNOLOGY CO LTD Page 54 Version 1 4 N No TRY SN32F100 Series Sv A X 32 Bit Cortex M0 Micro Controller 3 3 8 External RESET Pin Control register SYSO_EXRSTCTRL Address Offset 0x1C ER RESETDIS External RESET pin disable bit 0 Enable external RESET pin P0 15 acts as RESET pin 1 Disable PO 15 acts as GPIO pin 3 3 9 SWD Pin Control register SYS0 SWDCTRL Address Offset 0x20 811 Reseved BD E SWDDIS SWD pin disable bit 0 Enable SWD pin P0 13 acts as SWDIO pin P0 12 acts as SWCLK pin 1 Disable PO 13 and PO 12 act as GPIO pins 3 3 10 Anti EFT Ability Control register SYSO ANTIEFT Address Offset 0x30 This register decides the HW anti EFT ability ona Reseved OA AEFT 2 0 Bd m EFT ability RW 010 Low 011 Medium 100 Strong SONG TECHNOLOGY CO LTD Page 55 Version 1 4 N y j SONIX aai doliis 3 4SYSTEM CONTROL REGISTERS 1 Base Address 0x4005 E000 3 4 1 AHB Clock Enable register SYS1_AHBCLKEN Address Offset 0x00 The SYS_AHBCLKEN register enables the AHB clock to individual system and peripheral blocks Note gt 1 W
30. 29 25 Reserved CHLENGTHI4 0 Bit number of single channel CHLENGTH 4 0 1 0 6 Reserved 7 8 bits 8 9 bits 31 32bits Max If I2SEN 1 and I2SMOD 1 HW will switch channel length 32bits 19 Reserved RXFIFOTH 2 0 RX FIFO Threshold level 0 RX FIFO threshold level 0 1 RX FIFO threshold level 1 n RX FIFO threshold level n 15 Reserved TX FIFO Threshold level TREO 0 TX FIFO threshold level 0 1 TX FIFO threshold level 1 n TX FIFO threshold level n DL 1 0 Data Length 00 8 bits 01 16 bits 10 24 bits 11 32 bits CLRRXFIFO Clear 12S RX FIFO 0 No effect 1 Reset RX FIFO RXFIFOLV bit becomes 0 RXFIFOEMPTY bit becomes 1 Data in RX FIFO will be cleared This bit returns O automatically CLRTXFIFO Clear 12S TX FIFO 0 No effect 1 Reset TX FIFO TXFIFOLV bit becomes 0 TXFIFOEMPTY bit becomes 1 Data in TX FIFO will be cleared This bit returns 0 automaticall Receiver enable bit 0 Disable 1 Enable LI ww ee ET 0 Disable SONIX TECHNOLOGY CO LTD Page 140 Version 1 4 N No AM SN32F100 Series Sv NS A N 32 Bit Cortex M0 Micro Controller ON PP FORMATI1 0 128 operation format R W 11 0 00 Standard 12S format 01 Left justified format 10 Right MSB justified format 11 Reserved If I2SEN 1 and I2SMOD 1 HW will switch Standard 12S format Master Slave selection bit R W 0 Act as Master using internally generated BCLK and WS signals 1 Act as Slave usi
31. 6 3 SSP n Clock Divider register SSPn CLKDIV n 0 1 Address Offset 0x08 85 8 Reseved pn 7 0 DIV 7 0 SSPn clock divider 0 SCK SSPn PCLK 2 1 SCK SSPn PCLK 4 2 SCK SSPn_PCLK 6 X SCK SSPn_PCLK 2X 2 10 6 4 SSP n Status register SSPn STAT n 0 1 Address Offset 0x0C Reserved RX FIFO threshold flag 0 Data in RX FIFO s RXFIFOTH 1 Data in RX FIFO RXFIFOTH TX FIFO threshold flag 0 Data in TX FIFO TXFIFOTH 1 Data in TX FIFO lt TXFIFOTH 0 SSP controller is idle 1 SSP controller is transferring RX FIFO empty flag 0 RX FIFO is NOT empty 1 RX FIFO is empty TX FIFO full flag gt 0 TX FIFO is NOT full 1 TX FIFO is full TX EMPTY TX FIFO empty flag 0 TX FIFO is NOT empty In Master mode the transmitter will begin to transmit automatically 1 TX FIFO is empty SONiX TECHNOLOGY CO LTD Page 106 Version 1 4 RX FULL RX FIFO full flag gt 0 RX FIFO is NOT full 1 RX FIFO is full NONA ai ee 10 6 5 SSP n Interrupt Enable register SSPn IE n 0 1 Address Offset 0x10 This register controls whether each of the four possible interrupt conditions in the SSP controller is enabled DI no 8 4 Reserved Bd op TX FIFO threshold interrupt enable 0 Disable 1 Enable EN dE RX FIFO threshold interrupt enable 0 Disable 1 Enable RX time out interrupt enable 0 Disable 1 Enable RX Overflow interrupt enable 0 Disable 1 Enable 10 6 6
32. 8 bit counter The clock is fed to the timer via a pre scaler The timer decrements when clocked The minimum value from which the counter decrements is 0x01 Hence the minimum Watchdog interval is Twpr pcik x 128 x 1 and the maximum Watchdog interval is Twpr peik x 128 x 256 The Watchdog should be used in the following manner 1 Select the clock source for the watchdog timer with WDTCLKSEL register 2 Set the prescale value for the watchdog clock with WDTPRE bits in APB Clock Prescale register 0 SYS1 APBCPO register 3 Get the Watchdog timer constant reload value in WDT TC register 4 Enable the Watchdog and setup the Watchdog timer operating mode in WDT CFG register 5 The Watchdog should be fed again by writing 0x55AA to WDT FEED register before the Watchdog counter underflows to prevent reset or interrupt When the watchdog is started by setting the WDTEN in WDT CFG register the time constant value is loaded in the watchdog counter and the counter starts counting down When the Watchdog is in the reset mode and the counter underflows the CPU will be reset loading the stack pointer and program counter from the vector table as in the case of external reset Whenever the value 0x55AA is written in WDT FEED register the WDT TC value is reloaded in the watchdog counter and the watchdog reset or interrupt is prevented The watchdog timer block uses two clocks HCLK and WDT PCLK HCLK is used for the AHB accesses to the watchdog re
33. CO LTD Page 175 Version 1 4 SONE SN32F 100 Series 32 Bit Cortex MO Micro Controller 21 MARKING DEFINITION 21 1 INTRODUCTION There are many different types in GONG 32 bit MCU production line This note lists the marking definitions of all 32 bit MCU for order or obtaining information 21 2 MARKING INDETIFICATION SYSTEM SN32X PartNo X X X Ly Material Temperature Range Shipping Package Device ROM Type Title SONiX TECHNOLOGY CO LTD Page 176 B PB Free Package G Green Package 40 C 85 C W Wafer H Dice K SK DIP P P DIP S SOP X SSOP F LQFP J QFN oil Device Part No F Flash memory SONIX 32 bit MCU Production Version 1 4 NONA 21 3 MARKING EXAMPLE SN32F100 Series 32 Bit Cortex M0 Micro Controller Name ROM Type Device Package Temperature Material SN32F109FG Flash memory 109 LQFP 40 C 85 C Green Package SN32F109W Flash memory 109 Wafer 40 C 85 C SN32F109H Flash memory 109 Dice 40 C 85 C SN32F108FG Flash memory 109 LQFP 40 C 85 C Green Package SN32F107FG Flash memory 109 LQFP 40 C 85 C Green Package 21 4 DATECODE SYSTEM XX X X XXXXX SONiX TECHNOLOGY CO LTD Day SONiX Internal Use Month 1 January Year 2 February 9 September A October B November C December 03 2003 04 2004 05 2005 06 2006 Page 177 Version 1 4 NONA SN32F100 Series 32 Bit
34. CT16Bn PWMCTRL nz0 1 Address Offset 0x34 The PWM Control register is used to configure the match outputs as PWM outputs Each match output can be in dependently set to perform either as PWM output or as match output whose function is controlled by CT16Bn EM register For each timer a maximum of three single edge controlled PWM outputs can be selected on the CT16Bn_PWMCTRL 2 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared ES La M A PWMOIOEN CT16Bn PWMO GPIO selection bit 0 CT16Bn PWMO pin act as GPIO 1 CT16Bn PWMO pin act as match output and output signal depends on SONG TECHNOLOGY CO LTD Page 79 Version 1 4 N N o VM SN32F100 Series Sv NS A X 32 Bit Cortex MO Micro Controller e PWMOEN bit EA 193 Reserved PWMOEN PWMO enable 0 CT16Bn PWMO is controlled by EMO 1 PWM mode is enabled for CT16Bn PWMO 6 7 12 CT16Bn Timer Raw Interrupt Status register CT16Bn RIS nz0 1 Address Offset 0x38 This register indicates the raw status for Timer PWM interrupts A Timer PWM interrupt is sent to the interrupt controller if the corresponding bit in the CT16Bn IE register is set CAPOIF Interrupt
35. Cortex M0 Micro Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part SONiX TECHNOLOGY CO LTD Main Office Address 10F 1 NO 36 Taiyuan Street Chupei City Hsinchu Taiwan R O C Tel 886 3 5600 888 Fax 886 3 5600 889 Taipei Office Address 15F 2 NO 171 Song Ted Road Taipei Taiwan R O C Tel 886 2 2759
36. LTD Page 25 Version 1 4 SONIX SN32F100 Series 32 Bit Cortex MO Micro Controller Bi direction I O Pin Shared with Specific Analog Input Function e g XIN ADC Rev GPIOPn MODE x E GPIOn_CFG de GPIOPn MODE X E GPIOn CFG EN Output Latch Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn MODE register gt I O Input Bus 4 VO Output Bus gt Analog IP Input Terminal Bi direction UO Pin Shared with Specific Analog Output Function e g XOUT Reu GPIOPn MODE x t GPIOn CFG Pin GPIOPn_MODE gt pe GPIOn_CFG Output gt I O Input Bus Latch Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn MODE register SONG TECHNOLOGY CO LTD Page 26 VO Output Bus Analog IP Output Terminal Version 1 4 NORS V SN32F100 Series N Y N A N 32 Bit Cortex MO Micro Controller CENTRAL PROCESSOR UNIT CPU 2 1 MEMORY MAP OxFFFF FFFF OxE010 0000 Reserved Reserved Pad i OxE000 F
37. PLL frequency is determined by the following parameters Feu Frequency from the PLLCLKSEL multiplexer Fyco Frequency of the Voltage Controlled Oscillator VCO 156 to 320 MHz Feikour Frequency of PLL output P System PLL post divider ratio controlled by PSEL bits in PLL control register SYSO PLLCTRL F System PLL front divider ratio controlled by FSEL bits in PLL control register SYSO PLLCTRL M System PLL feedback divider ratio controlled by MSEL bits in PLL control register SYSO PLLCTRL VVVVVV To select the appropriate values for M P and F it is recommended to follow these constraints 10MHz lt FCLKIN lt 25MHz 150MHz lt Fyco lt 330MHz 2 M lt 31 F 1 or2 P 6 8 10 12 or 14 duty 50 2 5 Feikour 20MHz 30MHz 40MHz 50MHz 24MHz 36MHz 48MHz 32MHz 22MHz 24MHz 50MHz with jitter 500 ps DOP orm SONG TECHNOLOGY CO LTD Page 45 Version 1 4 NORS V SN32F100 Series S NS E N 32 Bit Cortex M0 Micro Controller 3 2 3 EXTERNAL CLOCK SOURCE 3 2 3 1 External High speed EHS Clock External high clock includes Crystal Ceramic modules The start up time of is longer The oscillator start up time decides reset time length 4MHz Crystal 4MHz Ceramic 3 2 3 CRYSTAL CERAMIC Crystal Ceramic devices are driven by XIN XOUT pins For high normal low frequency the driving currents are different XIN CRYSTAL xou M C U HH 20pF T 20pF VDD
38. Program Erase operations can be performed over the whole product voltage range 15 3 FEATURES gt Read interface 32 bit gt Flash Program Erase operation gt Code Option includes Code Security CS Write operations to the main memory block and the code options are managed by an embedded Flash Memory Controller FMC The high voltage needed for Program Erase operations is internally generated The main Flash memory can be read write protected against different levels of Code Security CS During a write operation to the Flash memory any attempt to read the Flash memory will stall the bus The read operation will proceed correctly once the write operation has completed This means that code or data fetches cannot be made while a write erase operation is ongoing For write and erase operations on the Flash memory the IHRC will be turn ON by FMC The Flash memory can be programmed and erased using ICP and ISP SONiX TECHNOLOGY CO LTD Page 157 Version 1 4 I NI y SN32F100 Series S N A X 32 Bit Cortex M0 Micro Controller 15 4 ORGANIZATION Block Name Base Address T Size Byte Page 0 0x00000000 0x000003FF 1024 Page 1 0x00000400 0x000007FF 1024 User ROM i Page 63 0x0000FC00 0x0000FFFF 1024 Page 0 Ox1FFF0000 0x1FFFO3FF 1024 Boot Loader Page 1 0x1FFF0400 0x1FFFO7FF 1024 Page 2 0x1FFF0800 0x1FFFOBFF 1024 Page 3 0x1FFFOCOO Ox1FFFO
39. RECOMMEND FREQUENCY SET TING sesse bikes esse e HERR s Ge ko bee Dae gees 51 3 3 3 Clock Source Status register SY SO CAS an 42 3 3 4 System Clock Configuration register SYSO CLKCHGl een 32 3 5 5 AHB Clock Prescale register SYSD AHBGP san 52 3 3 6 System Reset Status register SYSO_RSTST anna a 53 3 3 7 LVD Control register SYS0 LYDCTRE a 53 3 3 8 External RESET Pin Control register SYSO_EXRSTCTRL esse esse se es se se ee se ee ee se ee ee se ee 55 3 3 9 SWD Pin Control register SYSO_SWDCTRL uns 55 3 3 10 Anti EFT Ability Control register SYSO ANTIEFT esse esse esse es eee ss se se ee se ee see se ge ee ge 55 34 SYSTEM CONTROLREGISTER S To 56 3 4 1 AHB Clock Enable register SY54 AHBCLKEN ans ea 56 3 4 2 APB Clock Prescale register 0 SYS1 APBCPO een 57 SONiX TECHNOLOGY CO LTD Page 4 Version 1 4 IN y SN32F100 Series O Q A N 32 Bit Cortex M0 Micro Controller 3 4 3 APB Clock Prescale register 1 SYSI APBCP anne a 56 3 4 4 Peripheral Reset register MN vaere 59 4 SYSTEM OPERATION MODE ovisscsscsosescscssosscossisecosssnsssosssssscssensencanesneesodessoesepssssecssusvenscoandnosceasoseccasess 61 4 1 OVERVIEW ie e A ters 61 4 2 NORMALEMODE yas OE EE E EEEa E E 61 43 LOW POWER MODE Sn 61 4 3 1 SLEEP MODE ss 61 4 3 2 DEEP SLEEP MODE eege Eege 62 4 3 3 DEEP POWER DOWN DED E 62 4 3 3 1 Entering Deep power down made anne a 63 4 3 3 2 Exiting Deep power down mode sesse se ee ee
40. SONG TECHNOLOGY CO LTD Page 65 Version 1 4 N NI y SN32F100 Series S N A N 32 Bit Cortex M0 Micro Controller D GENERAL PURPOSE I O PORT GPIO 5 1 OVERVIEW sr ports can be configured input output by SW Each individual port pin can serve as external interrupt input pin Interrupts can be configured on single falling or rising edges and on both edges The VO configuration registers control the electrical characteristics of the pads Internal pull up pull down resistor Most of the I O pins are mixed with analog pins and special function pins V V WV WM 5 2GPIO MODE The MODE bits in the GPlOn CFG n 0 1 2 3 register allow the selection of on chip pull up or pull down resistors for each pin or select the repeater mode The repeater mode enables the pull up resistor if the pin is logic HIGH and enables the pull down resistor if the pin is logic LOW This causes the pin to retain its last known state if it is configured as an input and is not driven externally The state retention is not applicable to the Deep power down mode Note HW will switch P1 7 and P1 8 to Microphone differential input if SEL_MIC 1 in ADC_SET23 register Setting SEL_MIC 0 before P1 7 and P1 8 as GPIO function Note P0 14 is the input pin only please don t set it to the output function in GPIOO MODE register SONG TECHNOLOGY CO LTD Page 66 Version 1 4 N g SONIX vr pried 5 3GPIO REGISTERS Base Address 0x4004 4000 GPI
41. System Stop IPower On Delay Time The LVD low voltage detector is built in SONiX 32 bit MCU to be brown out reset protection When the VDD drops and is below LVD detect voltage the LVD asserts an interrupt signal to the NVIC This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt if not SW can monitor the signal by reading a dedicated status register An additional threshold level can be selected to cause a forced reset of the chip The LVD detect level is different by each MCU The LVD voltage level is a point of voltage and not easy to cover all dead band range Using LVD to improve brown out reset is dependent on application requirement and environment If the power variation is very deep violent and trigger the LVD the LVD can be the protection If the power variation can touch the LVD detect level and make system work error the LVD can t be the protection and need to other reset methods More detail LVD information is in the electrical characteristic section Watchdog reset The watchdog timer is a protection to make sure the system executes well Normally the watchdog timer would be clear at one point of program Don t clear the watchdog timer in several addresses The system executes normally and the watchdog won t reset system When the system is under dead band and the execution error the watchdog timer can t be clear by program The watchdog is continuously cou
42. controlled by CMPOEN bit When CMPOEN O the comparator output pin is GPIO mode If CMPOEN 1 CMO pin outputs comparator output status and isolates GPIO mode The comparator output terminal connects to internal path The CMPOUT flag is the CMPOUT shows the comparator result immediately but the CMPIRQ only indicates the event of the comparator result The comparator output terminal through de bounce circuit generates the comparator trigger edge controlled by CMPG The even condition is controlled by register and includes rising edge CMPOUT changes from low to high falling edge CMPOUT changes from high to low controlled by CMPG bit The CMPIRQ 1 condition makes the comparator interrupt service executed when CMPGIE comparator interrupt control bit set Internal Reference CMPS 1 0 00 1 4 Vdd Voltage CMPS 1 0 01 1 2 Vdd CMPS 1 0 10 11 3 4 Vdd Comparator Comparator CMPN P2 0 P2 15 Internal Logic P3 0 P3 7 selected by CMCH 4 0 CMPEN 1 14 8 COMPARATOR APPLICATION NOTICE The comparator is to compares the positive voltage and negative voltage to output result The positive used internal reference and negative sources are analog signal In hardware application circuit the comparator input pins must be connected a 0 1uF capacitance to reduce power noise and make the input signal more stable The application circuit is as following Channel 0 of Comparator Negative Input Channel 23 of Comparat
43. dead band V1 doesn t touch the below area and not effect the system operation But the V2 and V3 is under the below area and may induce the system error occurrence Let system under dead band includes some conditions DC application The power source of DC application is usually using battery When low battery condition and MCU drive any loading the power drops and keeps in dead band Under the situation the power won t drop deeper and not touch the system reset voltage That makes the system under dead band AC application SONG TECHNOLOGY CO LTD Page 38 Version 1 4 N N NY SN32F100 Series D D A A 32 Bit Cortex M0 Micro Controller In AC power application the DC power is regulated from AC power source This kind of power usually couples with AC noise that makes the DC power dirty Or the external loading is very heavy e g driving motor The loading operating induces noise and overlaps with the DC power VDD drops by the noise and the system works under unstable power situation The power on duration and power down duration are longer in AC application The system power on sequence protects the power on successful but the power down situation is like DC low battery condition When turn off the AC power the VDD drops slowly and through the dead band for a while 3 1 3 2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION To improve the brown out reset needs to know the system minimum operating voltage which is depend on the system executing r
44. dit 161 15 10 2 Flash Control register FLASH C TRE ais 161 15 10 3 Flash Data register FLASH DIT idad 161 15 10 4 Flash Address register FLASH ADDR E 162 SONG TECHNOLOGY CO LTD Page 11 Version 1 4 IN N y SN32F100 Series O N A N 32 Bit Cortex M0 Micro Controller 16 SERIAL WIRE DEBUG SWD use nennen 163 161 OVERVIEW ee een ed 163 162 FEATURES sure 163 165 PINDESGCRIP KEE 163 184 DEBUG NOTE sr 163 164 1 LIMITATIONS rr iaa 163 10622 DEBUG RECOVERY ES RD Ai 163 16 4 3 INTERNAL PULL UP DOWN RESITIORS on SWD DIN 163 17 DEVELOPMENT TOOL euer 164 INED ADD ns aaa E A 164 17 2 SNS2EIIOSTARTER KIT nes ee 165 HA NTN Kit VIO ua ee er 165 17 2 2 sSN32F100 Start Kit VIVIS gassen 167 18 ELECTRICAL CHARACTERISTIC 6 issssecsesenasccanasausiiccotneslacasesavsoonsessetascasssceicostasagedeasessusserenseds 169 18 1 ABSOLUTEMAXIMUM RATING ersinnen ui 169 162 ELECTRICAL CHARACTERISTIC un nee 169 18 3 ER RE 171 19 FLASH ROM PROGRAMMING PIN esse sasie sesse n onde eg see ee se on bede sege sk ee ee wed see ee be oe Ke we ede kes od 172 0 PACKAGE INFORMATION E 173 D MN 173 20 27 EQEP 64 PIN eee 174 20 3 LQFP 80 PIN RE RE EE EE N 175 21 MARKING DEFINITION etm ni 176 21 1 INTRODUCTION Pec 176 21 2 MARKING INDETIFICATION SYSTEM cutis io di 176 213 MARKING EXAMPLE t 177 21 1 DATECODE SYSTEM unsere 177 SONG TECHNOLOGY CO LTD Page 12 Version 1 4 NONA SN32F100 Series 32 Bit Cortex M0 Micro Controller
45. ee ee ee ee Re ee Re GR Re ee ee 63 Bd WAKEUP NR Ts 63 4 5 STATE MACHINE OF PIVU EE 63 4 6 OPERATION MODE COMPARSION TABLE esse es ss sees ss se ss se se es ss ge es se se ee ss ge es sg se es se ee es se Ge ee se ee 64 4 7 PMU do EKS DE iN 65 4 7 1 Backup registers D to 15 TEE ie 65 4 7 2 Power control register PMU CTRL is ves de At 65 3 GENERAL PURPOSE VO PORT GPIO a ua 66 5 1 OVERVIEW ee GR ee ee Ge ee A A A NAS 66 32 VON 66 5 3 GPIO REGISTER Su ile 67 5 3 1 GPIO Port n Data register GPIOn DATA n 0 1 2 3 ee ee es se ee Se ee eene enne 67 5 3 2 GPIO Port n Mode register GPIOn MODE nz0 1 2 3 ee ee esse se ee es se se ee ee se ee ee ee ee ee ee ee ee 67 5 3 3 GPIO Port n Configuration register GPIOn_CFG n 0 1 2 3 sess 67 5 3 4 GPIO Port n Interrupt Sense register GPIOn IS n0 1 2 3 sss 69 5 3 3 GPIO Port n Interrupt Both edge Sense register GPIOn IBS n 0 1 2 3 sss 69 5 3 6 GPIO Port n Interrupt Event register GPIOn IEV n0 1 2 3 sess 69 5 3 7 GPIO Port n Interrupt Enable register GPIOn IE n 0 1 2 3 csse 69 5 3 6 GPIO Port n Raw Interrupt Status register GPIOn RIS n 0 1 2 3 ees ees ss ees se se ee ee se 70 5 3 9 GPIO Port n Interrupt Clear register GPIOn IC N 0 1 2 3 esses 70 5 3 10 GPIO Port n Bits Set Operation register GPIOn BSET n 0 1 2 3 sse 70 5 3 1
46. gt 0 Interrupt disabled 1 Interrupt enabled 2 3 2 3 IRQO 31 Interrupt Set Pending Register NVIC ISPR Address 0xE000 E200 Refer to Cortex MO Spec The ISPR forces interrupts into the pending state and shows the interrupts that are pending Note Writing 1 to the ISPR bit corresponding to gt aninterrupt that is pending has no effect adisabled interrupt sets the state of that interrupt to pending SETPENDI31 0 Interrupt set pending bits Write 0 No effect 1 Change interrupt state to pending Read gt 0 Interrupt is not pending 1 Interrupt is pending 2 3 2 4 IRQ0 31 Interrupt Clear Pending Register NVIC ICPR Address 0xE000 E280 Refer to Cortex MO Spec The ICPR removes the pending state from interrupts and shows the interrupts that are pending Note Writing 1 to an ICPR bit does not affect the active state of the corresponding interrupt SONG TECHNOLOGY CO LTD Page 32 Version 1 4 NONA EE o CLRPEND 31 0 Interrupt clear pending bits Write gt 0 No effect 1 Removes pending state of an interrupt Read 0 Interrupt is not pending 1 Interrupt is pending 2 3 2 5 IRQO 31 Interrupt Priority Register NVIC IPRn n 0 7 Address 0xE000 E400 0x4 n Refer to Cortex MO Spec The interrupt priority registers provide an 8 bit priority field for each interrupt and each register holds four priority fields This means the number of registers is implementation defined and corresponds to th
47. interrupts will be generated after each data byte is received for a slave write transfer or after each byte that the module thinks it has transmitted for a slave read transfer In this second case the data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master Following all of these interrupts the processor may read the data register to see what was actually transmitted on the bus 11 7 2 LOSS of ARBITRATION In monitor mode the I2C module will not be able to respond to a request for information by the bus master or issue an ACK Some other slave on the bus will respond instead This will most probably result in a lost arbitration state as far as our module is concerned Software should be aware of the fact that the module is in monitor mode and should not respond to any loss of arbitration state that is detected In addition hardware may be designed into the module to block some all loss of arbitration states from occurring if those state would either prevent a desired interrupt from occurring or cause an unwanted interrupt to occur Whether any such hardware will be added is still to be determined SONiX TECHNOLOGY CO LTD Page 113 Version 1 4 N av j S A d N N 32 Bit a den 11 8 12C REGISTERS Base Address 0x4001 8000 I2CO 0x4005 A000 I2C1 11 8 1 12C n Control register I2Cn CTRL nz0 1 Address Offset 0x00 The I2Cn CTRL registers control setting of bits t
48. n DL 3 0 Data length DL 3 0 1 0000 0001 Reversed 0010 data length 3 1110 data length 15 1111 data length 16 Interface format 0 SPI 1 SSI Master Slave selection bit 0 Act as Master 1 Act as Slave Slave data output disable bit ONLY used in slave mode 0 Enable slave data output 1 Disable slave data output MISO 0 Loop back mode enable 0 Disable 1 Data input from data output SONiX TECHNOLOGY CO LTD Page 105 Version 1 4 7 6 FRESETI1 0 SSP FSM and FIFO Reset bit 00 No effect 01 Reserved 10 Reserved 11 Reset finite state machine and FIFO BUF BUSY 0 data in shift BUF is cleared TX EMPTY 1 TX FULL 0 RX EMPTY 1 RX FULL 0 and data in FIFO is cleared This bit will be cleared by HW automatically NONA mue er SSPEN SSP enable bit 1 Enable 10 6 2 SSP n Control register 1 SSPn_CTRL1 n 0 1 Address Offset 0x04 35 3 Reseved pn AN CPHA Clock phase for edge sampling R 0 Data changes at clock falling edge latches at clock rising edge when CPOL 0 Data changes at clock rising edge latches at clock falling edge when CPOL 1 1 Data changes at clock rising edge latches at clock falling edge when CPOL 0 Data changes at clock falling edge latches at clock rising edge when CPOL 1 ERN Clock polarity selection bit 0 SCK idles at Low level 1 SCK idles at High level pe MSB LSB selection bit 0 MSB transmit first 1 LSB transmit first 10
49. received a NACK Received a NACK ACK done status p Not received an ACK Received an ACK ax done status 0 No RX with ACK NACK transfer 1 8 bit RX with ACK NACK transfer is done 11 8 3 12C n TX Data register I2Cn TXDATA nz0 1 Address Offset 0x08 TOP DN Stop done status S 0 No STOP bit 1 MASTER mode gt a STOP condition was issued SLAVE mode gt a STOP condition was received SONiX TECHNOLOGY CO LTD Page 115 Version 1 4 SONA ML Ai This register contains the data to be transmitted In Master TX mode CPU writes this register will trigger a TX function In Slave TX mode CPU has to write this register before next TX procedure 318 Reseved R 0 11 8 4 12C n RX Data register I2Cn RXDATA n 0 1 Address Offset 0x0C 958 Reserved Rn DATA 7 0 Contains the data received Read this register when RX DN 1 R 0x00 11 8 5 12C n Slave Address 0 register I2Cn SLVADDRO n 0 1 Address Offset 0x10 Only used in slave mode In master mode this register has no effect If this register contains 0x00 the I2C will not acknowledge any address on the bus Register ADRO to ADR3 will be cleared to this disabled state on reset oe Slave address mode m 0 7 bit address mode 1 10 bit address mode d General call address enable bit 0 Disable 1 Enable general call address 0x0 ADDRI9 0 The 12C slave address 9 0 ADD 9 0 is valid when ADD MODE 1 ADDI7 1 is valid when ADD MOD
50. register 5 3 4 GPIO Port n Interrupt Sense register GPlOn IS nz0 1 2 3 Address offset OxXOC IS 15 0 Selects interrupt on pin x as level or edge sensitive x 0 to 15 0 Interrupt on Pn x is configured as edge sensitive 1 Interrupt on Pn x is configured as event sensitive 5 3 5 GPIO Port n Interrupt Both edge Sense register GPlOn IBS nz0 1 2 3 Address offset 0x10 31 16 Reserved Due Selects interrupt on Pn x to be triggered on both edges x 0 to 15 0 Interrupt on Pn x is controlled through register GPlOn IEV 1 Both edges on Pn x trigger an interrupt 5 3 6 GPIO Port n Interrupt Event register GPlOn IEV nz0 1 2 3 Address offset 0x14 Reserved 81 16 Reserved O IEV 15 0 Selects interrupt on pin x to be triggered rising or falling edges x 0 to 15 0 Depending on setting in register GPlOn IS Rising edges or HIGH level on Pn x trigger an interrupt 1 Depending on setting in register GPlOn IS Falling edges or LOW level on Pn x trigger an interrupt 5 3 7 GPIO Port n Interrupt Enable register GPlOn IE nz0 1 2 3 Address offset 0x18 Bits set to HIGH in the GPIOn IE register allow the corresponding pins to trigger their individual interrupts Clearing a bit disables interrupt triggering on that pin IEI5 Selects interrupt on pin x to be enabled x 0 to 15 15 0 0 Disable Interrupt on Pn x 1 Enable Interrupt on Pn x SONiX TECHNOLOGY CO LT
51. set to perform either as PWM output or as match output whose function is controlled by CT32Bn EM register For each timer a maximum of three single edge controlled PWM outputs can be selected on the CT32Bn PWMCTRL 93 0 outputs One additional match register determines the PWM cycle length When a match occurs in any of the other match registers the PWM output is set to HIGH The timer is reset by the match register that is configured to set the PWM cycle length When the timer is reset to zero all currently HIGH match outputs configured as PWM outputs are cleared Bi Name Description Attribute Resel 31 22 Reserved Pn o PWM1IOEN CT32Bn_PWM1 GPIO selection bit R W 0 CT32Bn_PWM1 pin act as GPIO 1 CT32Bn PWM pin act as match output and output signal depends on PWMIEN bit PWMOIOEN CT32Bn PWMO GPIO selection bit RW 0 CT32Bn PWMO pin act as GPIO 1 CT32Bn PWMO pin act as match output and output signal depends on PWMOEN bit 192 Reserved P D SONG TECHNOLOGY CO LTD Page 88 Version 1 4 NONA sai PWMIEN PWM1 enable 0 CT32Bn_PWM1 is controlled by EM1 1 PWM mode is enabled for CT32Bn_PWM1 PWMOEN PWMO enable 0 CT32Bn PWMO is controlled by EMO 1 PWM mode is enabled for CT32Bn PWMO 7 7 12 CT32Bn Timer Raw Interrupt Status register CT32Bn RIS nz0 1 Address Offset 0x38 This register indicates the raw status for Timer PWM interrupts A Timer PWM interrupt is sent to the interrupt controller if the co
52. the Deep sleep mode is that can power down clock generating blocks such as oscillators and PLL thereby gaining far greater dynamic power savings over Sleep mode In addition the Flash can be powered down in Deep sleep mode resulting in savings in static leakage power however at the expense of longer wake up times for the Flash memory 4 3 3 DEEP POWER DOWN DPD MODE In Deep power down mode power Turn off the on chip voltage regulator and clocks are shut off to the entire chip with the exception of the DPDWAKEUP pin DPDWAKEUP pin must be pulled HIGH externally to enter Deep power down mode and pulled LOW to exit Deep power down mode The processor state and registers peripheral registers and internal SRAM values are not retained However the chip can retain data in four BACKUP registers Wakes up the chip from Deep power down mode by pulling the DPDWAKEUP pin LOW Turn on the on chip voltage regulator When the core voltage reaches the power on reset POR trip point a system reset will be triggered and the chip re boots The RESET pin has no functionality in Deep power down mode SONG TECHNOLOGY CO LTD Page 62 Version 1 4 N N y SN32F100 Series S N A N 32 Bit Cortex M0 Micro Controller 4 3 3 1 Entering Deep power down mode Follow these steps to enter Deep power down mode from Normal mode 1 Pull the DPDWAKEUP pin externally HIGH Please confirm pull up time to ensure that the DPDWAKEUP pin already in the pull up sta
53. to be loaded with the contents of TC 2 Enable a sequence of 1 then 0 on CT16Bn CAPO signal will reset the TC 3 Reserved CAPORE Capture Reset on CT16Bn CAPO signal rising edge 0 Disable 1 Enable a sequence of 0 then 1 on CT16Bn CAPO signal will cause CAPO to be loaded with the contents of TC 2 Enable a sequence of 0 then 1 on CT16Bn CAPO signal will reset the TC 3 Reserved 6 7 9 CT16Bn Capture 0 register CT16Bn CAPO nz0 1 Address Offset 0x2C Each Capture register is associated with a device pin and may be loaded with the counter timer value when a specified event occurs on that pin The settings in the Capture Control register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges Mime 2 CAPO 15 0 6 7 10 CT16Bn External Match register CT16Bn_EM n 0 1 Address Offset 0x30 The External Match register provides both control and status of CT16Bn PWM 1 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules Reserved EMCO 1 0 Determines the functionality of CT16Bn PWMO 00 Do Nothing 01 CT16Bn PWMO pin is LOW 10 CT16Bn PWMO pin is HIGH 11 EE CT16Bn PWMO the TC and MRO are equal this bit will act according to EMCO bits a and also drive the state of CT16Bn PWMO output 6 7 11 CT16Bn PWM Control register
54. to one to enable the timer reset when the timer value matches the value of the corresponding match register SONG TECHNOLOGY CO LTD Page 84 Version 1 4 IN ow 2F1 j SO NS a X 32 Bit alee teen 7 7 CT32Bn REGISTERS Base Address 0x4000 4000 CT32B0 0x4000 6000 CT32B1 7 7 1 CT32Bn Timer Control register CT32Bn_TMRCTRL nz0 1 Address Offset 0x00 Note CEN bit shall be set at last 31 2 Reseved 3 DR o CRST Counter Reset R W 0 Disable counter reset 1 Timer Counter is synchronously reset on the next positive edge of PCLK This is cleared by HW when the counter reset operation finishes BENE Counter Enable R W 0 Disable Counter 1 Enable Timer Counter for counting 7 7 2 CT32Bn Timer Counter register CT32Bn TC nz0 1 Address Offset 0x04 Unless it is reset before reaching its upper limit the TC will count up through the value OxFFFFFFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed 31 0 TC 81 0 Timer Counter ER 7 7 3 CT32Bn Prescale register CT32Bn PRE nz0 1 Address Offset 0x08 31 0 PR 81 0 Prescalemaxvalue RW o 7 7 4 CT32Bn Prescale Counter register CT32Bn PC nz0 1 Address Offset 0x0C The 32 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows c
55. up trigger edge is bi direction The comparator s wake up function only supports sleep mode not deep sleep mode and deep power down mode If the trigger edge condition comparator output status exchanging is found the system will be wake up from sleep mode If the trigger edge direction is interrupt trigger condition the CMPIRQ is set as 1 Of course the interrupt routine is executed if the interrupt function enabled When the wake up trigger edge direction is equal to interrupt trigger condition the system will execute interrupt operation after sleep mode wake up immediately The critical condition is comparator positive voltage equal to comparator negative voltage and the voltage range is decided comparator offset parameter of input common mode In the voltage range the comparator output signal is unstable and keeps oscillating until the differential voltage exits the range In the condition the comparator flag CMPIRQ latches the first exchanging and issue the status but the status is a transient not a stable condition So the comparator builds in a filter to de bounce the transient condition The comparator output signal is through a de bounce circuit to filler comparator transient status The de bounce time is controlled by CMDB 1 0 bits that means the comparator minimum response time is zero 1 CMP PCLK 2 CMP PCLK or 3 CMP PCLK The de bounce time depends on the signal slew rate and selected by program Comparator Positive Signal Vp
56. value in the Counter timer when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges Note HW will switch VO Configuration directly when CAPOEN 1 FILET ENE 6 5 CAPOEN Capture 0 function enable bit R W 0 Disable 1 Enable Capture 0 function for external Capture pin 2 3 Reserved Interrupt on CT32Bn_CAPO signal event a CAPO load due to a CT32Bn CAPO signal event will generate an interrupt 0 Disable 1 Enable 3 2 CAPOFE Capture Reset on CT32Bn CAPO signal falling edge 0 Disable 1 Enable a sequence of 1 then 0 on CT32Bn CAPO signal will cause CAPO to be loaded with the contents of TC 2 Enable a sequence of 1 then 0 on CT32Bn CAPO signal will reset the TC 3 Reserved 1 0 CAPORE Capture Reset on CT32Bn CAPO signal rising edge 0 Disable 1 Enable a sequence of 0 then 1 on CT32Bn CAPO signal will cause CAPO to be loaded with the contents of TC 2 Enable a sequence of 0 then 1 on CT32Bn CAPO signal will reset the TC 3 Reserved SONG TECHNOLOGY CO LTD Page 87 Version 1 4 N No VAY SN32F100 Series O Q N A x 32 Bit Cortex MO Micro Controller 7 7 9 CT32Bn Capture 0 register CT32Bn CAPO nz0 1 Address Offset 0x2C Each Capture register is associated with a device pin and may be loaded with the counter timer value when a s
57. when the UARTn RB FIFO is empty 0 UARTn RB FIFO is empty 1 UARTn RB FIFO contains valid data 12 7 10 UART n Scratch Pad register UARTn SP n 0 1 Address Offset Ox1C This register has no effect on the UART operation This register can be written and or read at user s discretion There is no provision in the interrupt interface that would indicate to the host that a read or write of this register has occurred A PAD 7 0 A readable writable byte 12 7 11 UART n Auto baud Control register UARTn ABCTRL n 0 1 Address Offset 0x20 This register controls the process of measuring the incoming clock data rate for the baud rate generation and can be read and written at user s discretion Besides it also controls the clock pre scaler for the baud rate generation The reset value of the register keeps the fractional capabilities of UART disabled making sure that UART is fully SW and HW compatible with UARTs not equipped with this feature Name Reserved Bit D on ABTOIFC Auto baud time out interrupt flag clear bit 0 No effect 1 Clear ABTOIF bit This bit is automatically cleared by HW ABEOIFC End of auto baud interrupt flag clear bit 0 No effect 1 Clear ABEOIF bit This bit is automatically cleared by HW Reserved MED S o AUTORESTART Restart mode 0 No restart 1 Restart in case of timeout counter restarts at next UART RX falling edge ee Auto baud mode select bit 0 Mode 0 1 Mode 1 START Th
58. 0 Disable 1 Enable Enable reset TC when MR2 matches TC 0 Disable 1 Enable a Enable generating an interrupt when MR2 matches the value in the TC 0 Disable 1 Enable MR1STOP Stop MR1 TC will stop and CEN bit will be cleared if MR1 matches TC 0 Disable 1 Enable MRIRST Enable reset TC when MR1 matches TC SONiX TECHNOLOGY CO LTD Page 86 Version 1 4 m N o AV SN32F100 Series O Q NS A X 32 Bit Cortex MO Micro Controller 0 Disable 1 Enable PI Enable generating an interrupt when MR1 matches the value in the TC R W 0 Disable 1 Enable AA Stop MRO TC will stop and CEN bit will be cleared if MRO matches TC 0 Disable 1 Enable u MRORST Enable reset TC when MRO matches TC 0 Disable 1 Enable MA MROIE Enable generating an interrupt when MRO matches the value in the TC 0 Disable 1 Enable 7 7 7 CT32Bn Match register 0 3 CT32Bn MR0 3 n 0 1 Address Offset 0x18 0x1C 0x20 0x24 The Match register values are continuously compared to the Timer Counter TC value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the CT32Bn MCTRL register BESKREV EE PATTI DENT 7 7 8 CT32Bn Capture Control register CT32Bn_CAPCTRL nz0 1 Address Offset 0x28 The Capture Control register is used to control whether the Capture register is loaded with the
59. 000 Pd Debug Control OxE000 EDOO NVIC OxE000 E000 OxE010 0000 VT OxE000 0000 Private Peripheral Bus 0x4008 0000 OxE000 0000 Geen 0x4006 8000 N Comparator i F Reserved for External Device Sigma delta DAC 0x4006 6000 0x4006 5000 Sigma delta ADC 0x4006 4000 iu 0x4006 2000 X Ox A000 0000 SYSO 0x4006 0000 SYS1 0x4005 E000 SN Reserved Reserved for External o DCI 024005 C000 0x4005 A000 SSPI 0x4005 8000 UARTI 0x6000 0000 0x4005 6000 Reserved 0x4004 C000 GPIO3 Reserved for Peripheral Bos GPIO2 034004 A000 0x4004 8000 E 0x4004 6000 4 GPIOO 0x4008 0000 0x4004 4000 eaea Reserved 0x4003 4000 0x4000 0000 PMU 0x4003 2000 Reserved 0x2000 2000 Reserved 0x2000 0000 SE Reserved Ox1FFF 2800 2KB Information Block 0x4001 E000 Ox1FFF 2000 SSPO Reserved 0x4001 C000 Ox1FFF 1000 DS 4 KB Boot ROM 0x4001 A000 Ox1FFF 0000 I2C0 0x4001 8000 UARTO sl 0x4001 6000 Reserved Tu Reserved 0x4001 4000 RTC 0x4001 2000 0x0001 0000 WDT 0x4001 0000 Reserved 64 KB on chip FLASH 0x4000 8000 CT32B1 0x4000 6000 0x0000 0000 CT32B0 0x4000 4000 CT16B1 0x4000 2000 CT16BO 0x4000 0000 2 2 SYSTEM TICK TIMER The SysTick timer is an integral part of the Cortex MO The SysTick timer is intended to generate a fixed 10 ms interrupt for use by an operating system or other system management software SONG TECHNOLOGY CO LTD Page 27 Version 1 4 N Q NY SN32F100 Series D D E A 32 Bit Cortex M0 Micro Controller Since the Sys
60. 00000000 Sg SONiX TECHNOLOGY CO LTD NA Y2 External low speed 32 768KHz X tal Y3 External high speed X tal for Audio JP18 SN LINK connector JP15 Writer connector JP20 Short to force MCU stay in Boot loader JP21 I2S connector JP3 JP4 I2C0 I2C1 connector JP7 JP12 SPIO SPI1 connector JP8 JP9 UARTO UART1 connector R1 SCLO pull up resistor R3 SDAO pull up resistor R2 SCL1 pull up resistor R4 SDA1 pull up resistor R5 UTXDO pull up resistor R6 URXDO pull up resistor R41 UTXD1 pull up resistor R42 URXD1 pull up resistor JP47 Codec ADC power connector JP48 Codec DAC power connector JP49 Codec Driver power connector JP34 Headset connector JP29 Microphone connector JP42 MIC N connector JP43 MIC P connector JP54 MIC BIAS from chip supply or external bias R30 MIC BIAS from external bias adjust Page 168 SN32F100 Series 32 Bit Cortex MO Micro Controller Version 1 4 N N y SN32F100 Series O N A N 32 Bit Cortex M0 Micro Controller 1 8 ELECTRICAL CHARACTERISTIC 18 1 ABSOLUTE MAXIMUM RATING Supply voltage Vdd RE EE A beats 0 3V 3 6V Inputin voltage VIA Ee Vss 0 2V Vdd 0 2V Operating ambient temperature Topr SN32F107 5N32F108 SN32F109 ME 40 C 85 C Storage ambient temperature SO vide genes Peta anani EER etn rtm eR E ee BEP EE ERG AREA AA ad A epa ra 40 C 125 C 18 2 ELECTRICAL CHARACTERISTIC Stand
61. 1 3 PIN DESCRIPTION it ee 110 DP WAVE CHARACTERISTICS Se ns pU DEN ROI REIR ac 110 115 BEM3SSTERMODES sick een 111 11 5 1 MASTER TRANSMITTER MODE ia 111 1152 MASTER RECEIVER MODE aa 111 11 33 ARBITRATION m 111 Ii NENNE 112 11 6 1 SLAVE TRANSMITTER MODE suis 112 EE RE ATTEN 112 TLF CRINES QUUD c Re Ge Oe Ge en Ge ee Ge ee ae ee ee eed 113 SE WERTEN 113 11 72 LOSSGPARBIDPRATION EE 113 11 89 PEREGISTERS E 114 11 8 1 UTNE PER CTR POSU id Lak RU a N Go 114 11 8 2 2C n Status register ELCH STAT S de ee SR eN an 115 11 8 3 2Cn TX Data register 120 TXDATA n 0 1 aa 115 1184 I2CnRX Data register I2Cn RXDATA n 0 1 116 11 85 I2Cn Slave Address 0 register I2Cn SLVADDRO rof 116 11 8 6 I2C n Slave Address 1 3 register 2Cn SLVADDRI 3 n 0 1 esee 116 11 87 I2CnSCL High Time register I2Cn SCLHT n 0 1 116 11 8 8 BEnrSCL Low Tine register UR SCLLT aD ea 117 11 8 9 I2Cn Timeout Control register I2Cn TOCTRL n 0 1 una 117 11 8 10 I2C n Monitor Mode Control register I2Cn_MMCTRL N O 1 117 12 UNIVERSAL ASYNCHRONOUS SERIAL RECEIVER AND TRANSMITTER UART 118 121 OVERVIEW ai dide cal a o EE 118 122 FEATURES ME 118 12 3 PIN DESCRIPTION EE 118 SONiX TECHNOLOGY CO LTD Page 8 Version 1 4 N N y SN32F100 Series O Q A N 32 Bit Cortex M0 Micro Controller 124 BLOCK DIAGRAM EE 119 12 5 BAUD RATECALCULATION ee 120 12 6 AUIS
62. 1 GPIO Port n Bits Clear Operation register GPIOn BCLR n 0 1 2 3 ee ss se ee ee se 70 5 3 12 GPIO Port n Open Drain Control register GPIOn ODCTRL n 0 1 2 3 sss 70 6 16 BIT TIMER WITH CAPTURE FUNCTION ssssesenessesesenensasssesesenenensnsesenensnsssesssenenensesesenensnsnsesenen 72 6 1 OVERVIEW M 72 62 FEATURE 72 6 3 RRE e AT NA E 72 GA BLOCKDIAGRAM EE 73 SONiX TECHNOLOGY CO LTD Page 5 Version 1 4 IN N y SN32F100 Series O NS A N 32 Bit Cortex M0 Micro Controller 6 5 TIMER OPERATION ci aia 74 6 6 E O seems EE ae ress rene 75 6 7 CTIOBN REGISTERS T 76 6 7 1 CTI6Bn Timer Control register CTI6Bn TMRCTRL n 0 1 ees ees se ees se ee se ee ee ee 76 6 7 2 CTI6Bn Timer Counter register CT16Bn TC n 0 1 ee se ee ee ee ER Re ee Ee ee ee 76 6 7 3 CTIOBn Prescale register CT16Bn_PRE d E ia 76 6 7 4 CT16Bn Prescale Counter register CTIGBA PC nV Tan aa 76 6 7 5 CTI6Bn Count Control register CT16Bn_CNTCTRL n 0 1 sees 77 6 7 6 CTI6Bn Match Control register CT 16Bn MCTRL n 0 1 ees see es se ee se se ee ee Ee ee ee 77 6 7 7 CTI6Bn Match register 0 3 CT16Bn_MRO 3 n 0 I ee se ee es Ee ee ER Re ee Ee ee ee 78 6 7 6 CT16Bn Capture Control register CT16Bn_CAPCTRL n 0 1 ees esse ese ee ee ee 78 6 7 9 CTIOBn Capture 0 register CTI6BA CAPO n D 1 an 79 6 7 10 C
63. 1 PRODUCT OVERVIEW 1 1 FEATURES SONG TECHNOLOGY CO LTD Memory configuration 64KB on chip Flash programming memory 8KB SRAM 4KB Boot ROM Operation Frequency up to 50MHz Interrupt sources ARM Cortex MO built in Nested Vectored Interrupt Controller NVIC VO pin configuration Up to 62 General Purpose l O GPIO pins with Configurable pull up pull down resistors GPIO pins can be used as edge and level sensitive interrupt sources Comparator input pin CMO CM23 Comparator output pin CMO Programmable WatchDog Timer WDT Programmable watchdog frequency with watchdog Clock source and divider System tick timer 24 bit timer The system tick timer clock is fixed to the frequency of the system clock The SysTick timer is intended to generate a fixed 10 ms interrupt Real Time Clock RTC LVD with separate thresholds Reset 1 65V for Vcore 1 8V 2 0 2 4 2 7V for VDD Interrupt 2 0 2 4 2 7 3 0V for VDD Fcpu Instruction cycle Fepu Fuoik Fsvscik 1 F syscik 2 F sysc k 4 Working voltage 1 8V 3 6V Operating modes Normal Sleep Deep sleep and Deep power down Serial Wire Debug SWD In System Programming ISP supported Page 13 Timer Two 16 bit and two 32 bit general purpose timers with a total of four capture inputs GPWMs DAC 16 bit Sigma delta DAC for Audio Can drive the L R Channel Earphone SNR 90dB THD N 750B ADC 16 bit Sigma delta ADC for Audio AGC
64. 11111 Reserved 14 4 2 Comparator Interrupt Enable register CMP IE Address Offset 0x10 This register controls whether the interrupt condition in the Comparator controller is enabled Bit Name 31 1 Reserved CMPGIE Comparator edge trigger interrupt enable Comparator interrupt trigger direction refer to CMPG 0 Disable 1 Enable SONiX TECHNOLOGY CO LTD Page 155 Version 1 4 Na No TRY SN32F100 Series SO a X 32 Bit Cortex M0 Micro Controller 14 4 3 Comparator Interrupt Status register CMP RIS Address Offset 0x14 This register contains the status for interrupt condition regardless of whether or not the interrupt is enabled in CMP IE register This register indicates the status for Comparator control raw interrupts A Comparator interrupt is sent to the interrupt controller if the corresponding bit in the CMP_IE register is set EET ER CMPGIF o sage reinas a a aaaaaeeeeeeA edge trigger interrupt flag 0 Comparator edge trigger doesn t occur 1 Comparator edge trigger occurs 14 4 4 Comparator Interrupt Clear register CMP IC Address Offset 0x18 C Reed E E E 5 CMPGIC 0 No effet 1 Clear CMPGIF bit SONiX TECHNOLOGY CO LTD Page 156 Version 1 4 I NI y SN32F100 Series S N A X 32 Bit Cortex M0 Micro Controller 1 5 FLASH 15 1 OVERVIEW The SN32F100 series MCU integrated device feature in system programmable ISP FLASH memory for convenient upgradeable code storage T
65. 1980 Fax 886 2 2759 8180 Hong Kong Office Unit No 705 Level 7 Tower 1 Grand Central Plaza 138 Shatin Rural Committee Road Shatin New Territories Hong Kong Tel 852 2723 8086 Fax 852 2723 9179 Technical Support by Email Sn8fae sonix com tw Page 178 Version 1 4
66. 2 CT16Bn Timer Counter register CT16Bn TC nz0 1 Address Offset 0x04 Unless it is reset before reaching its upper limit the TC will count up to the value 0x0000FFFF and then wrap back to the value 0x00000000 This event does not cause an interrupt but a Match register can be used to detect an overflow if needed 81 16 Reseved P 0 j 150 Ten TimerCounter DW 0 6 7 3 CT16Bn Prescale register CT16Bn PRE nz0 1 Address Offset 0x08 8116 Reseved bn 15 0 PR SO jPrsaemavau DW 0 6 7 4 CT16Bn Prescale Counter register CT16Bn PC nz0 1 Address Offset 0x0C The 16 bit Prescale Counter controls division of PCLK by some constant value before it is applied to the Timer Counter This allows control of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc 3116 Reseved PRP o 15 0 PC IS 0 PrescaleCounter CR SONG TECHNOLOGY CO LTD Page 76 Version 1 4 NONA one Ais 6 7 5 CT16Bn Count Control register CT16Bn_CNTCTRL nz0 1 Address Offset 0x10 This register is used to select between Timer and Counter mode and in Counter mode to select the pin and edges for counting
67. 32F100 Series D N A A 32 Bit Cortex M0 Micro Controller determined by the enable bit of all blocks The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Wake up the chip from Sleep mode by an interrupt occurs The RESET pin has keep functionality in Sleep mode The Sleep mode is entered by using the following steps 1 Write 1 to SLEEPEN bit in PMU CTRL register 2 Execute ARM Cortex MO WFI instruction 4 3 2 DEEP SLEEP MODE In Deep sleep mode the system clock to the ARM Cortex MO core is stopped and execution of instructions is suspended The clock to the peripheral functions are stopped because the power state of oscillators are powered down the clock source are stopped except RTC low speed clock source ELS X TAL ILRC if used X Note User SHALL decide to power down RTC low speed clock source ELS X TAL ILRC oscillator or not if RTC is enabled The processor state and registers peripheral registers and internal SRAM values are maintained and the logic levels of the pins remain static Wake up the chip from Deep sleep mode by anyone of GPIO port pins PO P3 interrupt trigger or RTC interrupt The RESET pin has keep functionality in Deep sleep mode The Deep sleep mode is entered by using the following steps 1 Write 1 to DSLEEPEN bit in PMU CTRL register 2 Execute ARM WFI instruction The advantage of
68. 40 C 1700 40 C E 1220 1600 EE j 5 no mr E 1500 20 3 11 80 O 2 14 00 L ee O 1160 m 25T i 13 00 ase u 12 00 11 40 70 a 11 20 c 11 00 70 i 85 11 00 19 00 85 C 190 2 30 2 30 230 1 60 240 2 60 3 10 3 60 VDD V VDD V VDD v s Regulator 1 8V Output VDD v s Max Eau 60 50 40 zm se 2 n 2 30 DE gt 20 10 0 VZ he a 28 128 Cer 29 qo 38 38 180 200 220 240 260 280 300 320 340 360 VDD V VDD V SONiX TECHNOLOGY CO LTD Page 171 Version 1 4 N N V SN32F100 Series O NS A N 32 Bit Cortex M0 Micro Controller 1 d FLASH ROM PROGRAMMING PIN Programming Information of SN32F100 Series Chip Name SN32F109F SN32F108F SN32F107F MP PRO Writer Flash IC JP3 Pin s Toce 27 48 28 Tu SEU PGM un sr ALSB PDB SONiX TECHNOLOGY CO LTD Page 172 Version 1 4 32 Bit Cortex M0 Micro Controller SONIN id 20 PACKAGE INFORMATION 20 1 LOFP 48 PIN 9 00 BSC 7 00 BSC 9 00 BSC 7 00 BSC 0 5BSC SONiX TECHNOLOGY CO LTD Page 173 Version 1 4 NONA oue ie 20 2 LQFP 64 PIN b 013 o 8 023 c 00 020 D 90085 gt D 700 BSC gt e 040BSC E 90086 gt E 700 BSC L 045 080 075 u T100REF e el ss 7 SONiX TECHNOLOGY CO LTD Page 174 Version 1 4 Ns y SONAX NEE 20 3 LQFP 80 PIN SONiX TECHNOLOGY
69. 6 CM6 45 P2 5 CM5 44 P2 4 CM4 PO 1 UTXDO 43 P2 3 CM3 P0 2 SCLO 42 P2 2 CM2 PO 3 SDAO 41 P2 1 CM1 P0 4 SCKO PGDCLK SNSZFIUBF P0 5 SELO PGDIN P0 6 MISOO OTPCLK P0 7 MOSIO VR DOUT 40 P2 0 CMO 39 P1 13 XTALOUT 38 P1 12 XTALIN 37 P1 1 AUXTALIN 36 P1 0 AUXTALOUT 35 P1 11 LXTALOUT P0 14 DPDWAKEUP 34 P1 10 LXTALIN P0 15 RESET 33 VSS EF _ GE Zo SE ES O O ES SEE bk Ta72249589999992 gt adaz2na58SHMna0aQ8 o 3 28 528 8838389 gt za zz TE oc gw D A SONG TECHNOLOGY CO LTD Page 18 Version 1 4 No NEA V SN32F100 Series O as N A N 32 Bit Cortex MO Micro Controller SN32F107F LQFP 48 pins oo oe S ses 99 SS e ages VE vas m mom edo a ao HEA M 9 m ob EER I ED oO OO zo o aA e e o oo 2 d Soa SZ ZS oO Ok s BEG ESE SE EE EE Amr SO m oO 0 x 0 o Oo dod o o o oi o o oi oi o Ee n n gt gt 36 P2 1 CM1 35 P2 0 CMO 34 P1 13 XTALOUT 33 P1 12 XTALIN 32 P1 1 AUXTALIN 31 P1 0 AUXTALOUT 30 P1 11 LXTALOUT P0 4 SCKO PGDCLK P0 5 SELO PGDIN P0 6 MISOO OTPCLK P0 7 MOSIO VR DOUT 29 P1 10 LXTALIN P0 12 SWCLK 28 VSS P0 13 SWDIO 10 27 VDD P0 14 DPDWAKEUP 11 26 AVSS DAC P0 15 RESET 12 25 VCOM DAC SN32F107F o o Jo Om S ON a EN EN ES a AVSS ADC MIC BIAS AVDD ADC P1 8 MIC N P1 7 MIC P AVDD DRV AVDD DAC O a a gt gt SONG TECHNOLOGY CO LTD Page 19 Version 1 4 en WN V SN32F100 Series O Y N A
70. AP selected input the frequency of the CAP input can not exceed one half of the PCLK clock Consequently the duration of the HIGH LOW levels on the same CAP input in this case can not be shorter than 1 2 x PCLK Note If Counter mode is selected in the CNTCTRL register Capture Control CAPCTRL register must be programmed as 0x0 Mtribute Des on Re Reserved Pn CIS 1 0 Count Input Select In counter mode when CTM 1 0 are not 00 these bits select which CAP pin is sampled for clocking 00 CT32Bn CAPO Other Reserved Bit CTM 1 0 Counter Timer Mode This field selects which rising PCLK edges can clear PC and increment Timer Counter TC 00 Timer Mode every rising PCLK edge 01 Counter Mode TC is incremented on rising edges on the CAP input selected by CIS bits 10 Counter Mode TC is incremented on falling edges on the CAP input selected by CIS bits 11 Counter Mode TC is incremented on both edges on the CAP input selected by CIS bits 7 7 6 CT32Bn Match Control register CT32Bn MCTRL nz0 1 Address Offset 0x14 Name Reserved Bit a iS Stop MR3 TC will stop and CEN bit will be cleared if MR3 matches TC 0 Disable 1 Enable LIB dE Enable reset TC when MR3 matches TC 0 Disable 1 Enable A Enable generating an interrupt when MR3 matches the value in the TC 0 Disable 1 Enable B ee Stop MR2 TC will stop and CEN bit will be cleared if MR2 matches TC
71. ARACTERISTICS l mE l ERE SDA PN l l l l d i l l l g I l P I eee I Data i Data EE START Change Change STOP Signal Allowed Allowed Signal SONiX TECHNOLOGY CO LTD Page 110 Version 1 4 I NI y SN32F100 Series N N A X 32 Bit Cortex M0 Micro Controller 11 5 12C MASTER MODES 11 5 1 MASTER TRANSMITTER MODE Write 1 to STA bit r START condition begins From Slave a r STA 0 F ACK_STAT 1 Transmit Address R W 0 Transmission Data SDA Y T Write address and TXDATA ko Start transmit SCL held Low l SCL food ot SI V tV J2V 3A AV JV Je 7V Je 9 2 6 3 J4V 5V J6 U7 J8V J9V PI Write to TXDATA SCL N be sr tn Falling edge of ninth clock Repeat Start End of transmission 11 5 2 MASTER RECEIVER MODE Write 1 to ACK bit Write 1 to ACK bit Start Acknowledge sequence Start Acknowledge sequence Write 1 to STA bit r START condition begins From Slave AGEram Master E i l i Write 1 to STO bit I i STA 0 l i I Transmit Address to Slave R W 1 Receiving Data from Slave Receiving Data from Slave v SDA Ya H polls Td 0 D7 De Ds Dal Dal Dal D1 D ACK_ De De D5 D4 D3 D2 D1 D 0 jac K y lt q A Write address and TXDATA o ACK_ is not sent Start transmit SCL P Master terminal transfer 11 5 3 ARBITRATION In the master transmitter mode the a
72. B 1 0 P2 11 CMI P2 12 CM12 P2 13 C CM13 354 u CM14 OR Odo BOME utd P2 15 be CMIS P3 0 CM16 P3 1 CMI7 P3 2 E CM18 P33 P CMI9 P3 4 m CM20 P3 5 35 CM21 P3 6 CM22 P37 ES CM23 CMCH 4 0 SONiX TECHNOLOGY CO LTD Page 152 Programmable internal reference voltage connected to comparator s positive terminal CMPOEN GPIO X 7 i CMO pin A CMPG CMPIEN CMPIRQ EN EN Comparator Interrupt CMPOUT flag Version 1 4 NI M i S d A N 32 Bit 2 _ 14 2 COMPARATOR OPERATION The comparator operation is to compare the voltage between comparator positive input and negative input terminals When the positive input voltage is greater than the negative input voltage the comparator output is high status When the positive input voltage is smaller than the negative input voltage the comparator output is low status Comparator Positive Signal Vp N lt Comparator Negative Signal Vn Vp Vn Vp gt Vn Vp gt Vn Comparator Output Signal Vp Vn Vp Vn The comparator builds in interrupt function The interrupt function trigger edge is selected by CMPG The trigger edge supports rising edge CMPG 0 falling edge CMPG 1 If the trigger edge condition is found the CMPIRQ is set as 1 If the comparator interrupt function enables the system will execute interrupt routine The CMPIRQ must be cleared by program The comparator builds in sleep mode wake up function The comparator sleep mode wake
73. BAUDFLOW usted 121 101 NTN Nr 121 1262 AUTO BAUD MODES ia 122 127 UARTREGISTERS opone D Qus E pU Ee 124 12 7 1 UART n Receiver Buffer register UARTn RB N 0 Il 124 12 7 2 UART n Transmitter Holding register UARTn TH N 0 Il 124 12 7 5 UART n Divisor Latch LSB registers UARTn DLL n 0 In 124 12 7 4 UART n Divisor Latch MSB register UARTn DLM n 0 1 sse 124 12 7 5 UART n Interrupt Enable register UARTn IE n 0 Il 125 12 7 6 UART n Interrupt Identification register UARTn II N 0 1 essere 125 12 7 7 UART n FIFO Control register UARTn_FIFOCTRL n 0 1 eese 127 12 7 8 UART n Line Control register UARTn LC n 0 1 ees ees se es se ee eese eee 127 127 9 UART n Line Status register UARTn LS n O D anna aan 127 12 7 10 UART n Scratch Pad register UARTA_SP n 0 I 129 12 7 11 UART n Auto baud Control register UARTn ABCTRL n 0 In 129 12 7 12 UART n Fractional Divider register UARTn_FD n 0 In 129 12 7 13 UART n Control register UARTn_CTRL n 0 dese sie He se N SEAN Gee SKA Ke ke ge Ee Ke 130 12 7 14 UART n Half duplex Enable register UARTn HDEN n 0 II 130 13 AUDIO BS CODEC E 132 BL OVERVIEW c E 132 PANT EE e 132 12 1 2 NNN 132 13 2 FEATURES cr OE DE OR OE OO 152 VEE EE E 132 1322 Codee Features T a i 132 13 3 PIN DESCRIPTION ET 133 1331 DS PIES CANO da en ee ee 133 1992 COREL ANDE IN AA EE N IR DI
74. CAPO n 0 1 aaa ana 66 7 7 10 CT32Bn External Match register CT32Bn EM n 0 1 ee ee se ee ee ee se se ee ee ee ee Re ee ee ee ee ee 88 7 711 CT32Bn PWM Control register CT32Bn PWMCTRL nz0 I sess 66 7 7 12 CT32Bn Timer Raw Interrupt Status register CT32Bn RIS N 0 L ee esses 89 7 7 13 CT32Bn Timer Interrupt Clear register CT32Bn_IC nz0 lI ssec 89 8 WATCHDOG TIMER WD Dicc 90 SONiX TECHNOLOGY CO LTD Page 6 Version 1 4 IN N y SN32F100 Series O Q A N 32 Bit Cortex M0 Micro Controller 8 1 OVERVIEW ui M 90 a BEOCKDIAGRAM ET 91 8 37 MR ANE EN euere 92 8 3 1 Watchdog Configuration register WIT CEG una 92 8 3 2 Watchdog Clock Source register WDT CLKSOURCE eese enne enne 92 8 3 3 Watchdog Toner Constant register WOT TG E 92 6 3 4 Watchdog Feed register WOT FEED E 93 REALTIME CLOCK RIO sen 94 9 1 OVER EE OO NER A 94 92 CEEA EURES eree INS o ee ene nes ea oe gat eos ened ee IEERENEOR 94 93 FUNCTIONAL DESCRIPTION eiii 94 9 3 1 INTRODULTION use 94 9 3 2 RESET RTCG REGISTERS aria ai 94 9 3 3 KIT PIAGASSERTIN Sasse 94 9 3 4 RIC OPERATION iio 95 4 BLOCK DAGANE 96 9 5 RTCRECTISTE c e 97 9 5 1 RTC Control register RTC_CTRL E 97 9 5 2 RTC Clock Source Select register RIC CLS nn aaa 97 9 5 3 RTC Interrupt Enable ve 97 9 5 4 RTC Raw Interrupt A E E 97 9 5 5 RTC Interrupt Clear register RIC IE na a ee Ge AE 98 9 5 6 RTC Sec
75. CO LTD Page 43 Version 1 4 N N y SN32F100 Seri S d A X 32 Bit Cortex M0 Seen 3 2 SYSTEM CLOCK ifferent clock sources can be used to drive the system clock SYSCLK 12 MHz internal high speed RC IHRC 16 KHz internal low speed RC ILRC PLL clock High speed external EHS crystal clock Low speed external ELS 32 768 KHz crystal oO VVVVV One clock sources can be used to drive the audio 125 Codec clock 2SMCLK gt Audio High speed external AUEHS crystal clock for audio Each clock source can be switched on or off independently when it is not used to optimize power consumption The micro controller is a dual clock system There are high speed clock and low speed clock The high speed clock is generated from the external oscillator amp on chip PLL circuit The low speed clock is generated from on chip low speed RC oscillator circuit ILRC 16 KHz 3 2 1 INTERNAL RC CLOCK SOURCE 3 2 1 1 Internal High speed RC Oscillator IHRC The internal high speed oscillator is 12MHz RC type The accuracy is 2 under commercial condition The IHRC can be switched on and off using the IHRCEN bit in Analog Block Control register SYSO_ANBCTRL 3 2 1 2 Internal Low speed RC Oscillator ILRC The system low clock source is the internal low speed oscillator built in the micro controller The low speed oscillator uses RC type oscillator circuit The frequency is affected by the voltage and temperature of the system In common conditi
76. D 2 7 3 3 3 6 V 9 ADC i j i MIC BI Microphone Bias Voltage M h B x 59 2 64 9 V Ba SEL_MICB 0 se ser m v SONiX TECHNOLOGY CO LTD Page 169 Version 1 4 VO High level output source current N N NY SN32F100 Series N N A A 32 Bit Cortex MO Micro Controller Microphone Bias Voltage 59 2 97 9 V N SEL MICB 1 ss 297 em vo Middle reference voltage VMID A AVDD ADC 3 3V VDD 1 8V i 59 1 9 V ADC Analog Reference Levels DC AVSS ADC VSS 0V 596 65 5 CL 10uF ional to Noise Rati SNR Signal to oise Ratio l 94 1KHz input 120dBr A weighted Analog Input to ADC Output EAD A THD N Total Harmonic Distortion 1KHz input 6dBr AVDD DAC Analog P 3 6 S ee ower SC se AVDD Headphone Driver P i 3 6 SEM num NN se 5 B Middle reference voltage 2 7 V 2 7 V VMID D AVDD DAC AVDD DRV 3 3V VDD 1 8V C AVSS_DAC AVSS_DRV VSS 0V CL 4 7uF DAC Analog Reference Levels Common mode voltage VCOM AVDD DAC AVDD DRV 3 3V VDD 1 8V AVSS_DAC AVSS_DRV VSS 0V CL 4 7uF DA Signal to Noise Ratio SN AVDD_DAC AVDD_DRV 3 3V VDD 1 8V AVSS_DAC AVSS_DRV VSS 0V Headphone Driver Analog 1KHz input RL 16Q 120dBr A weighted Output Total Harmonic Distortion Tun AVDD DAG AVDD DRV 3 3V VDD 1 8V AVSS_DAC AVSS_DRV VSS 0V 1KHz input RL 160 Po 20mW 6dBr FLASH Supply Voltage Lu ts ved 20K 100K Ti y gt lt Q Oo lt o o ed Fe sy 30
77. D 1 13 8 1 DAC Setting 1 register DAC SET1 Address Offset 0x000 308 Seene TR 10 6 PDOLK OKGENPOwerdown ace High mw 8 mde O d EE 48 Reserved 2 Pb VREF VREF Oro or RM 1 VMIDSEL Normal mode Fast Start up select RAN 0 Normal mode 1 Fast Ee mode 0 Reserved 13 8 2 DAC Setting 2 register DAC SET2 Address Offset 0x010 a Rasen EE RMP 1 0 Attenuation ramp rate R W T2 LRCK clock RMP 00 1T RMP 01 2T RMP 10 AT RMP 11 8T If VOL 7 0 in DAC SETS is changed then after RMP seconds the DAC output will start updating the volume ere Rs 3 RAN 1 Tf wr iN Mute ON OFF 1 Mute on G SCH per 1 Enable 0 Disable 0 SOFT RSTN Software reset digital circuit low reset one MCLK pulse trigger RW 1 13 8 3 DAC Setting 3 register DAC SET3 Address Offset 0x020 SONiX TECHNOLOGY CO LTD Page 149 Version 1 4 N N o TRY SN32F100 Series Sv a N 32 Bit Cortex M0 Micro Controller 9 8 Reseved e O R 0 7 0 VOL 7 0 Digital volume attenuation 0 5dB step DAN 0x00 0dB 0x01 0 5dB 0x02 1dB Ox7E 63dB Ox7F 63 5dB 13 8 4 DAC Setting 4 register DAC SETA Address Offset 0x030 9 8 Reserved 1 1 1 OR 0 6 3 Reserved 0 0 0 O R 0 j DEMS 1 0 Select the DAC de emphasis response curve 0 Reserved R W 1 De emphasis for 48 kHz 2 De emphasis for 44 1 kHz 3 De emphasis for 32 k
78. D Page 69 Version 1 4 NS No AM SN32F100 Series Sv Q A RK 32 Bit Cortex MO Micro Controller 5 3 8 GPIO Port n Raw Interrupt Status register GPlOn RIS nz0 1 2 3 Address offset Ox1C This register indicates the status for GPIO control raw interrupts A GPIO interrupt is sent to the interrupt controller if the corresponding bit in GPlOn IE register is set 3116 Reserved bn IF 15 0 GPIO raw interrupt flag x 0 to 15 0 No interrupt on Pn x 1 Interrupt requirements met on Pn x 5 3 9 GPIO Port n Interrupt Clear register GPlOn IC nz0 1 2 3 Address offset 0x20 Bit Nar 31 16 Reserved IC 15 0 Selects interrupt flag on pin x to be cleared x 0 to 15 0 No effect 1 Clear interrupt flag on Pn x 5 3 10 GPIO Port n Bits Set Operation register GPlOn BSET nz0 1 2 3 Address offset 0x24 In order for SW to set GPIO bits without affecting any other pins in a single write operation the GPIO bit is set if the corresponding bit in the GPlOn BSET register is set Bi Name Description Attribute R 31 16 Reseved RR W BSET 15 0 Bit Set enable x 0 to 15 0 No effect on Pn x 1 Set Pn x to 1 5 3 11 GPIO Port n Bits Clear Operation register GPlOn BCLR nz0 1 2 3 Address offset 0x28 In order for SW to clear GPIO bits without affecting any other pins in a single write operation the GPIO bit is cleared if the corresponding bit in this register is set BCLRI15 0 Bit clear enable x
79. DAO SDA1 pins as 20mA high sinking current if I2CMODE 1 gt 3 ACK and NACK bits can t both be 1 when receiving data gt 4 User has to write 1 to ACK or NACK bit in Master mode to continue next RX process Description 319 Reserved bn I2CEN 12C Interface enable bit 0 Disable The STO bit is forced to 0 1 Enable 12EN shall not be used to temporarily release the I2C bus since the bus status is lost when I2CEN resets The ACK flag should be used instead START bit 0 No START condition or Repeated START condition will be generated 1 Cause the 12C interface to enter master mode and transmit a START or a Repeated START condition Automatically cleared by HW STOP flag 0 Stop condition idle 1 Cause the 12C interface to transmit a STOP condition in master mode or recover from an error condition in slave mode Automatically cleared by HW Assert ACK Low level to SDA flag 0 Master mode No function Slave mode Return a NACK after receiving address or data 1 An ACK will be returned during the acknowledge clock pulse on SCLn when The address in the Slave Address register has been received The General Call address has been received while the General Call bit GC in the ADR register is set SONiX TECHNOLOGY CO LTD Page 114 Version 1 4 Ne y j SONIX dees gt A data byte has been received while the 12C is in the master receiver mode gt A data byte has been rece
80. E 0 11 8 6 12C n Slave Address 1 3 register I2Cn SLVADDR1 3 nz0 1 Address Offset 0x14 0x18 Ox1C 31 10 Reserved The 12C slave address EIEN ADD 9 0 is valid when ADD MODE 1 ADDI7 1 is valid when ADD MODE 0 11 8 7 12C n SCL High Time register I2Cn SCLHT nz0 1 Address Offset 0x20 Note I2C Bit Frequency I2Cn PCLK I2Cn SCLHT I2Cn SCLLT Nam 318 Reserved 7 0 SCLHI7 0 Count for SCL High Period time T9 SOHO TE Ae POLK cycle SONiX TECHNOLOGY CO LTD Page 116 Version 1 4 N No VAY SN32F100 Series O Q N A X 32 Bit Cortex MO Micro Controller 11 8 8 12C n SCL Low Time register I2Cn SCLLT n 0 1 Address Offset 0x24 Reserved SCLL 7 0 Count for SCL Low Period time SCL Low Period Time SCLL 1 12C0_PCLK cycle 11 8 9 12C n Timeout Control register I2Cn TOCTRL n 0 1 Address Offset 0x2C Timeout happens when Master Slave SCL remained LOW for TO 32 12C0_PCLK cycle When I2C timeout occurs the I2C transfer will return to IDLE state and issue a TO interrupt to inform user That means SCL SDA will be released by HW after timeout User can issue a STOP after timeout interrupt occurred in Master mode Time out status will be cleared automatically by writing I2Cn CTRL or I2Cn TXDATA register 81 16 Reseved bn TO 15 0 Count for checking Timeout R W 0x0 0 Disable Timeout checking N Timeout period time N I2Cn PCLK cycle
81. ER di 27 22 SYSTEM TIER TIMER condi n 27 22 1 OPERATION OE S 28 2 2 2 SYSTICK USAGE HINTS AND TIPS ses 28 2 2 3 SYSTICK REGISTER naked kes 29 2 23 1 System Tick Timer Control and Status register SYSTICK CTRL ess 29 2 2 8 2 System Tick Timer Reload value register SYSTICK LOAD eee 20 2 2 3 3 System Tick Timer Current Value register SYSTICK VAL ee 29 2 2 3 4 System Tick Timer Calibration Value register SYST CALIB eene 30 2 5 NESTED VECTORED INTERRUPT CONTROLLER NVIC eene 31 2 3 1 INTERRUPT AND EXCEPTION VECTORES ea eer eed een EAS 31 2 9 4 NI REGISTER NN EE Ho 31 2 3 2 1 TRQO 31 Interrupt Set Enable Register NVIC ISER eee 32 2 3 2 2 TRQO 31 Interrupt Clear Enable Register NVIC ICER eee 32 2 3 2 3 IRQO 31 Interrupt Set Pending Register NVIC IS 32 2 3 2 4 IRQO 31 Interrupt Clear Pending Register NVIC ICPR eee 32 2 3 2 5 IRQO 31 Interrupt Priority Register NVIC IPRn n20 7 eee 33 2 4 APPLICATION INTERRUPT AND RESET CONTROL AIRC eere 33 23 CODBOPTON TABLE c tee EE OE ER EE N SEEE 35 20 CORE REGER OVERVIEW enable 36 3 SYSTEM CONTRO E ass idee dese eee od as 37 ME OE EA EE EE ET OE OE MM d IE EE EE N EE N 37 3 1 1 POWER ON RESET E 37 3 1 2 WATC
82. Error in RX FIFO flag RXFE 1 when a character with a RX error such as framing error parity error or break interrupt is loaded into the UARTn RB register This bit is cleared when the UARTn LS register is read and there are no subsequent errors in the UART FIFO 0 UARTn RB register contains no UART RX errors or FIFOEN 0 1 UARTn RB register contains at least one UART RX error Transmitter Empty flag TEMT 1 when both THR and TSR are empty TEMT is cleared when either the TSR or the THR contain valid data 0 THR and or TSR contains valid data 1 THR and TSR are empty Transmitter Holding Register Empty flag THRE indicates that the UART is ready to accept a new character for transmission In addition this bit causes the UART to issue THRE interrupt to if THREIE 1 THRE 1 when a character is transferred from the THR into the TSR The bit is reset to logic O concurrently with the loading of the Transmitter Holding Register by the CPU 0 THR contains valid data 1 THR TX FIFO is empty Break Interrupt flag When RXD1 is held in the spacing state all zeros for one full character transmission start data parity stop a break interrupt occurs Once the break condition has been detected the receiver goes idle until RXD1 goes to marking state all ones A UARTn LS register read clears Bl bit The time of break detection is dependent on FIFOEN bit in UARTn FIFOCTRL register 0 Break interrupt status is inactive 1 Break int
83. FFF 1024 15 5 READ The embedded Flash module can be addressed directly as a common memory space Any data read operation accesses the content of the Flash module through dedicated read senses and provides the requested data The read interface consists of a read controller on one side to access the Flash memory and an AHB interface on the other side to interface with the CPU The main task of the read interface is to generate the control signals to read from the Flash memory as required by the CPU 15 6 PROGRAM ERASE The Flash memory erase operation can be performed at page level To ensure that there is no over programming the Flash programming and erase controller blocks are clocked by IHRC 15 7 EMBEDDED BOOT LOADER The embedded boot loader is used to reprogram the Flash memory using the UARTO serial interface This program is located in the Boot ROM and is programmed by SONiX during production SONiX TECHNOLOGY CO LTD Page 158 Version 1 4 lI g SONIX ie ad 15 8 FLASH MEMORY CONTROLLER FMC The FMC handles the program and erase operations of the Flash memory 15 8 1 CODE SECURITY CS Code Security is a mechanism that allows the user to enable different levels of security in the system so that access to the on chip Flash and use of the ISP can be restricted Important Any Code Security change becomes effective only after the device has gone through a power cycle ams 0 0x5A5A Writer can Erase Program U
84. FLASH gt FLASH block EN N AHB clock for USART1 XTALIN External High speed Crystal 7 E USATI j USART1_PCLK USART1 USART1 oscillator USARTICLKEN lock Prescaler Ot clock source register block XTALOUT Mesas 24816 EN AHB clock for USARTO 4 e USARTO USARTO PCLK u USARTO USARTO AUXTALIN External High Clock Prescaler gt speed Crystal AucLKou Audio Glock USARTOCLKEN pene clock source register block oscillator AUXTALOUTe Ais e AHB clock for I2C1 TECT lose riesci 1201 1201 12C1CLKEN PET clock source register block MCLKSEL AHB clock for ADC Taco 12C0_PCLK 12C0 12C0 EE 125 Clock Prescaler clock source register block jag poi ook Prescaler 11 2 48 16 11 2 4 8 16 F AHB clock for 125 N AHB clock for SSPO 125 128 i SSPO SSPO PCLK SSPO SSPO A register block clock source Glock Prescaler clock source register block HB clock for DAC AHB clock for SSP1 DAC DAC SSP1 SSP1 POLK SSP1 SSP1 register block clock source Clock Prescaler dock source register block 11 2 4 8 16 AHB clock for HB clock for ADC Comparator ADC ADC CODE CMP PCLK Comparator Comparator gt s register block clock source FAT CMPCLKEN lege clock source register block SONG TECHNOLOGY CO LTD Page 16
85. HDOG RESET WDT RESET EE 38 3 1 3 BROWN OUT RESET cia ei Eeer 38 SONiX TECHNOLOGY CO LTD Page 3 Version 1 4 IN y SN32F100 Series O Q H N 32 Bit Cortex M0 Micro Controller 4 13 1 BROWN OUT DESCRIPTION scr iia 38 3 1 3 2 THE SYSTEM OPERATING VOLTAGE DECSRIPTION eene 39 3133 BROWN QUT RESET IMPROVEMENT u 39 3 1 4 EXTERNACRESE ET 40 3 141 SIMPLY RC RESET CIRCUDLLE aaa ke ee 41 3 142 DIODE amp RC RESET CIRCUIT sn 41 S145 ZENER DIODE RESET CIRCUIT een 42 3 1 4 4 VOLTAGE BIAS RESET CIRCUIT WE 42 3145 EXTERNAL RESET IC aid 43 3 1 5 SOFTWARE RESET lt A n pn A Ee 43 32 SYSTEM CEOCK que EES 44 3 2 1 INTERNAL RC CLOCK SOURCE 00 AAA 44 3 2 1 1 Internal High speed RC Oscillator HRC 44 24 1 2 Internal Low speed RC Oscillator ILRC ne 44 32 2 ss EE EN ET EE IE AE UT NG EE 45 3221 PLL Freguency selection EE N AE AE EE EE EE 45 3 2 3 EXTERNAL CLOCK SOURCE nun aa NS K RENE RARE ee 46 3230 External High speed EHS CODE u a alistan 46 252 CRYSLASL CERAMIE EE 46 3 2 3 3 Audio External High speed AUEHS Clock 47 3 2 3 4 External Low speed ELS ClOcK anni ka 47 SU E NRS 47 1230 Bypass Mod C 48 3 2 4 SYSTEM CLOCK SYSCLE J SELECTION neun een ana 49 3 2 5 CLOUCK OUT CAPABITITY EEN 49 3 3 SYSTEM CONTROL REGISTERS ee Rara tad eld m hdi aan 50 3 3 1 Analog Block Control register SYSO ANBCTRL eese eee esee ee eene Ee SE Ge GR tanen 50 3 3 2 PLL control TEE E ER EE 50 3321
86. Hz E ONEN Initialize DAC RAM aw o set 1 until Ini RAM Ready 1 then clear this bit 13 8 5 DAC Status register DAC STATUS Address Offset 0x040 Attribute mese a E N EE EE EE EE O0 Ini RAM Ready Status for checking whether the ram initialization is ready or not R ee 13 9 Sigma delta ADC Control Flow 13 9 1 Sigma delta ADC Power up Sequence Step1 IREF EN 1 Step2 VREF EN 1 Step3 MICBOOST EN 1 Step4 PGA EN 1 Step5 ADC EN 1 Step6 CK EN 1 Step7 MICB EN 1 13 9 2 Sigma delta ADC Power down Sequence Step1 ADC EN 0 Step2 PGA EN 0 Step3 MICBOOST EN 0 Step4 MICB EN 0 Stepb VREF EN 0 Step6 IREF EN 0 SONiX TECHNOLOGY CO LTD Page 150 Version 1 4 N N y SN32F100 Series O d A N 32 Bit Cortex M0 Micro Controller Step7 CK EN 0 13 9 3 Sigma delta ADC Enable Sequence Step1 ADC Analog Enable Sigma delta ADC Power Up Sequence Step2 ADC Digital Enable ACTIVE 1 Step3 Delay 21us for ADC setup time Step4 MCLK Output Enable MCLKOEN 1 and 12S Enable 13 10 Sigma delta DAC Control Flow 13 10 1 Sigma delta DAC Power up Sequence Step1 PD IREF 20 Step2 VMIDSEL 1 Step3 PD_VREF 0 Step4 VMIDSEL 0 Stepb PD DAC 20 Step6 PD CLK 0 Step7 After PD CLK delay 6 3us Step8 After DG data ready delay 125ms Step9 PD DRV 0 13 10 2 Sigma delta DAC Power down Sequence Step1 PD DRV 1 Step2 PD DAC 1 Step3 VMIDSEL 0 Step4 PD VREF 1
87. IE ALARM Interrupt OVFIE DE OVERFLOW Interrupt gt Version 1 4 EN y j SONIX eld 9 5RTC REGISTERS Base Address 0x4001 2000 9 5 1 RTC Control register RTC CTRL Address offset 0x00 Note RTCEN bit shall be set at last RTCEN RTC enable bit R W 0 Disable 1 Enable Reset SEC CNT and ALM CNT 9 5 2 RTC Clock Source Select register RTC CLKS Address offset 0x04 Note SW shall disable RTC RTCEN 0 when changing the value of this register 3 RTC clock source selection er ELIA HW will reset SEC CNT and ALM CNT when changing the value 00 ILRC 01 ELS X TAL 10 Reserved 11 EHS X TAL clock 128 9 5 3 RTC Interrupt Enable register RTC IE Address offset 0x08 8 3 Reserved OVFIE Overflow interrupt enable 0 Disable 1 Enable ALMIE Alarm interrupt enable 0 Disable 1 Enable SECIE Second interrupt enable 0 Disable 1 Enable 9 5 4 RTC Raw Interrupt Status register RTC RIS Address offset 0x0C SU3 Reseved PRP o j OVFIF Overflow interrupt flag This bit is set by HW when ALM ONT overflows ALM CNT counts from OxFFFFFFFF to 0x0 An interrupt is generated if OVFIE 1 0 Overflow not detected 1 32 bit programmable counter overflow occurred SONG TECHNOLOGY CO LTD Page 97 Version 1 4 SONA pene e Alarm interrupt flag This bit is set by HW when ALM_CNT ALM_CNTV An interrupt is generated if ALRIE 1 0 Alarm no
88. If this happens the SysTick counter stops Ensure SW uses word accesses to access the SysTick registers SONG TECHNOLOGY CO LTD Page 28 Version 1 4 Y N 9 NX SN32F100 Series Is N A A 32 Bit Cortex M0 Micro Controller The SysTick counter reload and current value are not initialized by HW This means the correct initialization sequence for the SysTick counter is 1 Program the reload value in SYSTICK LOAD register 2 Clear the current value by writing any value to SYSTICK VAL register 3 Program the Control and Status SYSTICK CTRL register 2 2 3 SYSTICK REGISTERS 2 2 3 1 System Tick Timer Control and Status register SYSTICK CTRL Address OxE000 E010 Refer to Cortex MO Spec 3137 Reserved PD 0 EX COUNTFLAG This flag is set when the System Tick counter counts down to 0 and is cleared by reading this register 453 Reserved 0 CLKSOURCE Selects the SysTick timer clock source 0 reference clock 1 system clock Fixed TICKINT System Tick interrupt enable 0 Disable the System Tick interrupt 1 Enable the System Tick interrupt the interrupt is generated when the System Tick counter counts down to 0 pepe System Tick counter enable 0 Disable 1 Enable 2 2 3 2 System Tick Timer Reload value register SYSTICK LOAD Address OxE000 E014 Refer to Cortex MO Spec The RELOAD register is set to the value that will be loaded into the SysTick timer whenever it counts down to zero This register is set by softw
89. L register controls which mode is going to entered The CPU clock rate may also be controlled as needed by changing clock sources re configuring PLL values and or altering the system clock divider value This allows a trade off of power versus processing speed based on application requirements Run time power control allows disable the clocks to individual on chip peripherals allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application Selected peripherals have their own clock divider for power control Note 1 The debug mode is not supported in Deep sleep and Deep Power down mode 2 The pins which are not pin out shall be set correctly to decrease power consumption in low power modes Strongly recommended to set these pins as input pull up 4 3 1 SLEEP MODE In Sleep mode the system clock to the ARM Cortex MO core is stopped and execution of instructions is suspended Peripheral functions if selected to be clocked in SYS1 AHBCLKEN register continue operation during Sleep mode and may generate interrupts to cause the processor to resume execution Sleep mode eliminates dynamic power used by the processor itself memory systems and related controllers and internal buses The power state of the analog blocks HRC EHS X TAL ELS X TAL PLL Flash LVD Codec Comparator is SONG TECHNOLOGY CO LTD Page 61 Version 1 4 N NS NY SN
90. N N y SN32F100 Series O NS A N 32 Bit Cortex M0 Micro Controller SN32F100 Series USER S MANUAL SN32F107 SN32F108 SN32F109 SONiX 32 Bit Cortex MO Micro Controller SONIX reserves the right to make change without further notice to any products herein to improve reliability function or design SONIX does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others SONIX products are not designed intended or authorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SONIX product could create a situation where personal injury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries affiliates and distributors harmless against all claims cost damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SONIX was negligent regarding the design or manufacture of the part SONiX TECHNOLOGY CO LTD Page 1 Version 1 4 N N y SN32F100 Series O NS A N 32 Bit Cortex M0 Micro Contro
91. O 0 0x4004 6000 GPIO 1 0x4004 8000 GPIO 2 0x4004 A000 GPIO 3 5 3 1 GPIO Port n Data register GPIOn_DATA n 0 1 2 3 Address offset 0x00 EE 3116 Reserved 150 DATA 15 0 Input data read or output data write for Pn 0 to Pn 15 5 3 2 GPIO Port n Mode register GPlOn MODE nz0 1 2 3 Address offset 0x04 Note HW will switch VO Mode directly when Specific function Peripheral is enabled not through GPIOn MODE register Reserved MODE 15 0 a pin x as input or output x 0 to 15 n O and x 14 is input 0 Pn x is configured as input 1 Pn x is configured as output Note HW will switch P1 7 and P1 8 to Microphone differential input if SEL_MIC 1 in ADC SET23 register Setting SEL_MIC 0 before P1 7 and P1 8 as GPIO function Note P0 14 is the input pin only please don t set it to the output function in GPIOO MODE register 5 3 3 GPIO Port n Configuration register GPlOn CFG nz0 1 2 3 Address offset 0x08 Reset value OXAAAAAAAA Note HW will switch VO Mode directly when Specific function Peripheral is enabled not through GPIOn MODE register BI Nam CFG15 1 0 DIE of Pn 15 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode CFG14H 0 Configuration of Pn 14 1 0 00 Pull up resistor enabled 01 Pull down resistor enable
92. Offset 0x04 Note Must reset the corresponding peripheral with SYS1 PRST register after changing the prescale value e 20005 2008 AUEHSPRE 2 0 Audio external high clock source prescale value 000 AUEHS 1 001 AUEHS 2 010 AUEHS 4 011 AUEHS 8 100 AUEHS 16 Other Reserved 27 Reserved RR SSP1PRE 2 0 SSP1 clock source prescale value R W 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 28 Reseved CORA SSPO clock source prescale value SSPOPRE 2 0 000 HCLK 1 RAN 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 19 Had EE 9 CMPPRE 2 0 Comparator clock source prescale value R W 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 1 AO SONG TECHNOLOGY CO LTD Page 57 Version 1 4 N NS 9 NX SN32F100 Series N N A A 32 Bit Cortex MO Micro Controller CT32B1 clock source prescale value CT32B1PRE 2 0 O00 HLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 11 Reseved CT32BOPRE 2 0 CT32B0 clock source prescale value 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 7 Reseved RR CT16B1 clock source prescale value CT16B1PRE 2 0 000 HCLK 1 RAN 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved A ls agai SE aa va al va CT16BO clock source pre
93. Other Reserved O7 Reevwed BD UART1 clock source prescale value UART1PRE 2 0 000 HCLK 1 RAN 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 8 Reserved HD j UARTO clock source prescale value UARTOPRE 2 0 000 HCLK 1 RAN 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 3 4 4 Peripheral Reset register SYS1 PRST Address Offset 0x0C All bits are cleared by HW automatically after setting as 1 E CODECADRST BEE ADC reset 0 No effect 1 Reset Codec ADC 0 No effect 1 Reset Codec DAC IT ness EE 0 No effect 1 Reset WDT SONiX TECHNOLOGY CO LTD Page 59 Version 1 4 NONiX lal nil t m bd I2CORST ps I2C1RST 19 18 Reserved UARTIRST se UARTORST 15 14 Reserved E SSP1RST pe SSPORST W i CMPRST 10 Reserved Bf Kanal El enge Ml aed 5 Reserved E GPIOP3RST p GPIOP2RST M GPIOP1RST ad GPIOPORST RTC reset 0 No effect 1 Reset RTC 128 reset 0 No effect 1 Reset I25 12C0 reset 0 No effect 1 Reset 12C0 12C1 reset 0 No effect 1 Reset 12C1 UART1 reset 0 No effect 1 Reset UART1 UARTO reset 0 No effect 1 Reset UARTO SSP1 reset 0 No effect 1 Reset SSP1 SSPO reset 0 No effect 1 Reset SSPO Comparator reset 0 No effect 1 Reset Comparator CT32B1 reset 0 No effect 1 Reset CT32B1 CT32B0 reset 0 No effect 1 Reset CT32B0 CT16B1 reset
94. RTBAUDRATE E EE eee Oversampling x 256 x DLM DLL x 1 DIVADDVAL MULVAL Where UARTn PCLK is the peripheral clock UARTn DLM and UARTn DLL are the standard UART baud rate divider registers and DIVADDVAL and MULVAL are UART fractional baud rate generator specific parameters in UARTn FD register The value of MULVAL and DIVADDVAL should comply to the following conditions 1 1 S MULVAL s 15 2 0 lt DIVADDVAL s 14 3 DIVADDVAL MULVAL 4 Oversampling is 8 or 16 The value of the UARTn FD register should not be modified while transmitting receiving data or data may be lost or corrupted The oversampling method can be selected by programming the OVERB bit in UARTn FD register and can be either 16 or 8 times the baud rate clock e OVER8 1 Oversampling by 8 to achieve higher speed up to UARTn PCLK 8 In this case the maximum receiver tolerance to clock deviation is reduced 1 ee 1 hb 3 8 gt p 3 8 1 BIT TIME Sampled values e OVER8 0 Oversampling by 16 to increase the tolerance of the receiver to clock deviations In this case the maximum speed is limited to maximum UARTn PCLK 16 Sampled values LH EHE Sampling Clock h E 3 ta fs fe IL EER 6 16 7116 7116 JJ E Ed T BIT TIME ACA SONiX TECHNOLOGY CO LTD Page 120 Version 1 4 N N NY SN32F100 Series D D A 32 Bit Cortex M0 Micro Controller If the UARTn FD register value does not comply to these t
95. S NM MEIN MM NUS RUM sd 133 133 2 Audio Clock Pin DESC a eN ea Ge je 133 134 BEOCKEDIAGRA NE ai RR 134 1341 BS CLC OR CONTRO E AAA ARA AAA AA AA 134 13 42 ABS KLOCK DIAGRAM nee AA 134 13 4 3 16 Bit Sigma Delta ADC BLOCK DIAGRAM ee se ee enne Re ee ee Re ee inne 135 13 44 16 Bit Sigma Delta DAC BLOCK DIAGRAM ee se ee Re ER Re ER eene nennen nennen 136 185 FUNCTIONAL DES RTR 137 1131 Ao RTE EE 137 1532 PS FIFO OPERAION EE 139 SONiX TECHNOLOGY CO LTD Page 9 Version 1 4 SN32F100 Series 32 Bit Cortex MO Micro Controller 13 5 2 1 MONO e anes 139 1522 RE 139 13 0 BS REGISTERS EE e 140 130 PG Eg LES TREO REE 140 15562 IES Clockyesister 125 A ab aa 141 12 03 DS Status register 425 STATUS sus 141 13 6 4 PS Interrupt Enable register DS TENA veste a wb urb b tu ti 142 13 05 DS Raw Interrupt Malus register 125 esas bai eese suu eo ach Ra raa piu Pe sae AA ea UR SUR RA ES 142 13 6 6 128 Interrupt Clear register 125 id 143 13 6 7 I2S RX FIFO register I2S_RXFIFO eee 143 1368 I2S TX FIFO register 125 TXFIFO euere 143 147 CODEC RECHNEN 143 13 7 1 ADC Setting I register ADO da a 143 132 72 ADG Setting 2 register ADE SETS EE 144 13 7 3 ADC Setting 3 register ADC_SET3 nannte 144 13 74 APE Setting 4 register ADC_SET4 A een 144 137 35 ADC Seius 5 register ADC_SETS E 144 13 7 6 ADC Setting 6 register ADC SET Lae 144 13 7 7 ADC Sett
96. SONA wei PLLCLKSELH System PLL clock source R GERSELTI O 00 IHRC 12 MHz oscillator av 01 EHS X TAL 10 MHz 25 MHz Other Reserved 119 Reserved HD FSEL Front divider value The division value F is the programmed 2 R W 0 F 1 1 F 2 7 5 PSEL 2 0 Post divider value P PSEL 2 0 2 RAN 011b 000 010 Reserved 011 P 26 100 P 8 101 P2 10 110 P2 12 111 P 2 14 To select the appropriate values for M P and F it is recommended to follow these constraints 10MHz lt FCLKIN lt 25MHz 150MHz lt Fyco lt 330MHz 2 M lt 31 F 1 or2 P 6 8 10 12 or 14 duty 50 2 5 Fetkout 20MHz 30MHz 40MHz 50MHz 24MHz 36MHz 48MHz 32MHz 22MHz 24MHz 50MHz with jitter 500 ps 10MHz 12MHz 16MHz 20MHz 25MHz 30MHz 32MHz 36MHz 44MHz 48MHz SOMHZ V V V y LL y v rs AARON L v pr LX P v EE E UNES E EEN PES Ex IE y pop T T T T Tyv i 3 3 2 1 RECOMMEND FREQUENCY SETTING Fvco Fouen F M Foikour Fvco P Lo Jq xw J A o 1 Co BEE E A o 1 E EH o 1 AE ME El o 1 E d o 1 SONiX TECHNOLOGY CO LTD Page 51 Version 1 4 Ns N o A SN32F100 Series Sv N A x 32 Bit Cortex MO Micro Controller 3 3 3 Clock Source Status register SYSO CSST Address Offset 0x08 28 Reseved RR AUEHSRDY Audio external high speed clock ready flag 0 AUEHS oscillator not ready 1 AUEHS oscillator ready PLLRDY PLL clock
97. SSP n Raw Interrupt Status register SSPn RIS n 0 1 Address Offset 0x14 This register contains the status for each interrupt condition regardless of whether or not the interrupt is enabled in SSPn IE register This register indicates the status for SSP control raw interrupts An SSP interrupt is sent to the interrupt controller if the corresponding bit in the SSPn IE register is set TX FIFO threshold interrupt flag 0 No TX FIFO threshold interrupt 1 TX FIFO threshold triggered RX FIFO threshold interrupt flag 0 No RX FIFO threshold interrupt 1 RX FIFO threshold triggered RXTOIF RX time out interrupt flag RXTO occurs when the RX FIFO is not empty and has not been read for a time out period 32 SSPn_PCLK The time out period is the same for master and slave modes 0 RXTO doesn t occur 1 RXTO occurs RXOVFIF RX Overflow interrupt flag RXOVF occurs when the RX FIFO is full and another frame is completely received The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs 0 RXOVF doesn t occur 1 RXOVF occurs 10 6 7 SSP n Interrupt Clear register SSPn IC n 0 1 Address Offset 0x18 Bit lam AE TXFIFOTHI 0 No effet 3 TXHFOTHIC Oe FIFOTHIF bi RXFIFOTHI 0 No effet 2 RXFIFOTHIG G No et FFOTHF bit SONiX TECHNOLOGY CO LTD Page 107 Version 1 4 S Q Ns d X 32 Bit E E Cette RXTOIC 0 No effet 1 Clear RXTOIF bit RXOVFIC 0 No effet
98. SYSO EXRSTCTRL register Default value is 1 which means external reset function is enabled External reset pin is Schmitt Trigger structure and low level active The system is running when reset pin is high level voltage input The reset pin receives the low voltage and the system is reset The external reset operation actives in power on and normal running mode During system power up the external reset pin must be high level input or the system keeps in reset status External reset sequence is as following External reset only external reset pin enable System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released e System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock SONG TECHNOLOGY CO LTD Page 40 Version 1 4 N N NY SN32F100 Series D D A 32 Bit Cortex M0 Micro Controller e Program executing Power on sequence is finished and program executes from Boot loader if BLEN bit 1 or from 0x0 if BLEN bit 0 The external reset can reset the system during power on duration and good external reset circuit can protect the system to avoid working at unusual power condition e g brown out reset in AC power application 3 1 4 1 SIMPLY RC RESET CIRCUIT 100 ohm This is the basic reset circuit and only includes R1 a
99. Start bito V bitt bm bits bit4 bits bits X bit7 Parity Y Stop URXD Start bit LSB of A or a START bit in USARTn_ABCTRL Rate Counter 16 x Baud Rtae MUN 16 Cycles SONiX TECHNOLOGY CO LTD Page 123 Version 1 4 N y j SONIX vr pated 12 7 UART REGISTERS Base Address 0x4001 6000 UARTO 0x4005 6000 UART1 12 7 1 UART n Receiver Buffer register UARTn RB n 0 1 Address Offset 0x00 This register is the top byte of the UART RX FIFO and contains the oldest character received and can be read via the bus interface The LSB bit 0 contains the first received data bit If the character received is less than 8 bits the unused MSBs are padded with zeros The Divisor Latch Access Bit DLAB in the UARTn LC register must be zero in order to access this register Since PE FE and BI bits correspond to the byte on the top of the UART RX FIFO i e the one that will be read in the next read from this register the right approach for fetching the valid pair of received byte and its status bits is first to read the content of the UARTn LS register and then to read a byte from this register 3 8 Reseved PR o RB 7 0 Contains the oldest received byte in the UART RX FIFO 0 12 7 2 UART n Transmitter Holding register UARTn TH n 0 1 Address Offset 0x00 This register is the top byte of the UART TX FIFO The top byte is the newest character in the TX FIFO and can be written via the bus interf
100. TD Page 83 Version 1 4 32 Bit Cortex MO Micro Controller SON roer 7 6PWM 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value in CT32Bn MRO 3 registers is equal to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs the PWM output remains continuously LOW 3 f a match value larger than the PWM cycle length is written to the CT32Bn_MRO 3 registers and the PWM signal is HIGH already then the PWM signal will be cleared on the next start of the next PWM cycle 4 Ifa match register contains the same value as the timer reset value the PWM cycle length then the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 Ifa match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously ETC CT32Bn_MRO 100 PWM1 LL CT32Bn_MR1 25 PWM 9 CT32Bn_MRO 60 CT32Bn TC 0 25 60 100 TC resets Note When the match outputs are selected to perform as PWM outputs the timer reset MRnRST and timer stop MRnSTOP bits in CT32Bn MCTRL register must be set to zero except for the match register setting the PWM cycle length For this register set the MRnR bit
101. TI6Bn External Match register CT16Bn EM n 0 1 ees sesse es ees se ee ees ee ee ee ee ee 79 6 711 CTI6Bn PWM Control register CT16Bn_PWMCTRL n 0 1 essen 79 6 7 12 CTI6Bn Timer Raw Interrupt Status register CTI6Bn RIS n 0 1 ese ees se ee 80 6 7 13 CTI6Bn Timer Interrupt Clear register CT16Bn IC n 0 1 essere 80 7 32 BIT TIMER WITH CAPTURE FUNCTION sresesessssesenensnsssssesenensnsesenenensnsssssenenensssssenenensnsssevenenen 81 7 1 OVERVIEW EE 81 y id OE EE N EE AE RA AE E 81 253 PIN DESCRIPTION meee mene oiu cr tado A 81 T4 BLOCK DIAGRAM sissies wei dis 82 7 5 TIMER OPERATION Tr 83 7 6 PWM m 84 7 7 dd ke ME de Eed KE 85 7 7 1 CT32Bn Timer Control register CT32Bn TMRCTRL n 0 1 ese ees se es se ee ee ee ee 85 7 7 2 CT32Bn Timer Counter register CT32Bn_TC n 0 1 une 85 7 7 3 CT32Bn Prescale register CISZBA PRE 1 0 De a aa 85 7 7 4 CI32Bn Prescale Counter register CIT32Bn PC 1 0 dese seed ana 65 7 7 5 CT32Bn Count Control register CT32Bn_CNTCTRL n 0 1 se es Ee ee ee ee ee 85 7 7 6 CT32Bn Match Control register CT32Bn_MCTRL n 0 1 ees see es se ee se Ee ee ee ee ee 86 7 7 7 CT32Bn Match register 0 3 CT32Bn MRO 3 n 0 1 ee se ee Se Re ee ER ee ee ee ee 87 7 7 8 CT32Bn Capture Control register CT32Bn_CAPCTRL n 0 1 esee 87 7 7 9 CI32Bn Capture 0 register CTI2BA
102. Tick timer is a part of the Cortex MO it facilitates porting of software by providing a standard timer that is available on Cortex MO based devices Refer to the Cortex MO User Guide for details 2 2 1 OPERATION The SysTick timer is a 24 bit timer that counts down to zero and generates an interrupt The intent is to provide a fixed 10 ms time interval between interrupts The system tick timer is enabled through the SysTick control register The system tick timer clock is fixed to the frequency of the system clock The block diagram of the SysTick timer SYSTICK CALIB 4 SYSTICK LOAD Load data Private Peripheral SYSTICK VAL Bus System clock 24 bit down counter clock Ref clock ETE CLKSOURCE Fix to 1 SYSTICK CTRL COUNTFLAG TICKINT gt SysTick interrupt gt When SysTick timer is enabled the timer counts down from the current value SYST VAL to zero reloads to the value in the SysTick Reload Value Register SYST LOAD on the next clock edge then decrements on subsequent clocks When the counter transitions to zero the COUNTFLAG status bit is set to 1 The COUNTFLAG bit clears on reads X Note When the processor is halted for debugging the counter does not decrease 2 2 2 SYSTICK USAGE HINTS AND TIPS The interrupt controller clock updates the SysTick counter Some implementations stop this clock signal for low power mode
103. UTXD1 CT16B 1 CAPO P3 14 SCL1 CT32B0_ CAPO P3 15 SDA1 CT32B1 CAPO SONG TECHNOLOGY CO LTD Page 24 Version 1 4 S SS AN SN32F100 Series 32 Bit Cortex M0 Micro Controller 1 6 PIN CIRCUIT DIAGRAMS e Normal Bi direction VO Pin Reu GPIOPn MODE x I GPIOn_CFG Pin L VO Input Bus GPIOPn MODE x I GPIOn_CFG Output Latch Ro T O Output Bus Rep Bi direction I O Pin Shared with Specific Digital Input Function e g SPI 12C Rev Specific Input Function Control Bit GPIOPn MODE GPIOn CFG Specific Input Bus Pin u gt I O Input Bus GPIOPn MODE A x GPIOn_CFG Output Latch Output Bus Specific Output Function Control Bit Some specific functions switch I O direction directly not through GPIOn MODE register Bi direction UO Pin Shared with Specific Digital Output Function e g SPI I2C Rru GPIOPn MODE gt x GPIOn_CFG Pin gt I O Input Bus GPIOPn_MODE A x E GPIOn CFG Output Bus Output Latch Specific Output Bus Specific Output Function Control Bit Specific Input Function Control Bit Some specific functions switch I O direction directly not through GPIOn MODE register SONG TECHNOLOGY CO
104. Version 1 4 BR BN y SN32F100 Seri N d Q A N 32 Bit Cortex M0 LE 1 4 PIN ASSIGNMENT SN32F109F LQFP 80 pins P3 14 SCL1 CT32B0_CAPO P3 9 CT16BO PWMO P3 6 CM22 CT32B0 PWM1 P3 5 CM21 CT16B1 PWMO P3 7 CM23 CT32B1_PWM1 o a lt Oo o N e E o lt e Mm D e DO P3 4 CM20 NI N P3 10 CT32B0O_PWMO P3 11 CT32B1 PWMO P3 12 URXD1 CT16BO CAPO P3 13 UTXD1 CT16B1 CAPO 60 P2 11 CM11 59 P2 10 CM10 58 P2 9 CM9 57 P2 8 CM8 56 P2 7 CM7 55 P2 6 CM6 54 P2 5 CM5 53 P2 4 CM4 52 P2 3 CM3 51 P2 2 CM2 50 P2 1 CM1 49 P2 0 CMO 48 P1 13 XTALOUT 47 P1 12 XTALIN 46 P1 1 AUXTALIN 45 P1 0 AUXTALOUT P0 12 SWCLK 44 P1 11 LXTALOUT P0 13 SWDIO 43 P1 10 LXTALIN P0 14 DPDWAKEUP 42 VSS P0 15 RESET 41 VDD P0 4 SCKO PGDCLK P0 5 SELO PGDIN P0 6 MISOO OTPCLK PO Z MOSIO VR DOUT P0 8 SCK1 PO 9 SEL1 P0 10 MISO1 P0 11 MOSI1 SN32F109F wo VMID DAG gt tc a Ka e gt lt P1 6 l2SWS SONG TECHNOLOGY CO LTD Page 17 Version 1 4 BR BN y SN32F100 Series N Q A N 32 Bit Cortex MO Micro Controller SN32F108F LQFP 64 pins P3 14 SCL1 CT32BO CAPO P3 9 CT16BO PWMO P3 6 CM22 CT32B0_PWM1 P3 5 CM21 CT16B1_PWMO P3 7 CM23 CT32B1_PWM1 o DO lt O m N e E o lt lt a Rei i be OL o o P3 10 CT32B0_PWMO P3 11 CT32B1 PWMO P3 12 URXD1 CT16BO CAPO P3 13 UTXD1 CT16B1 CAPO 48 P2 8 CM8 47 P2 7 CM7 46 P2
105. W set PO 1 as output mode automatically n 1 3 Reserved Pn0OC o PO O open drain control bit 0 Disable 1 Enable HW set P0 0 as output mode automatically n 1 3 Reserved SONiX TECHNOLOGY CO LTD Page 71 Version 1 4 N M 2FI j SONIX sa A 6 16 BIT TIMER WITH GAPTURE FUNCTION 6 1 OVERVIEW Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt In PWM mode one match register can be used to provide a single edge controlled PWM output on the match output pins 6 2 FEATURES gt Two 16 bit counter timers gt Counter or timer operation gt Two 16 bit capture channels that can take a snapshot of the timer value when an input signal transitions A capture event may also optionally generate an interrupt gt The timer value may be configured to be cleared on a designated capture event This feature permits easy pulse width measurement by clearing the timer on the leading edge of an input pulse and capturing the timer value on the trailing edge gt Four 16 bit match registers that allow Continuous operation with optional interrupt generation on match Stop timer on match with optional interrupt generation
106. X TA ILRC gt Reset sources of the RTC Core Prescale value Alarm Counter and Divider Cold boot DPDWAKEUP gt Three dedicated enabled interrupt lines Alarm interrupt generating a software programmable alarm interrupt Seconds interrupt generating a periodic interrupt signal with a programmable period length up to 1 second Overflow interrupt to detect when the internal programmable counter rolls over to zero 9 3 FUNCTIONAL DESCRIPTION 9 3 1 INTRODUCTION RTC core includes a 20 bit preload value RTC SECCNTV Every TR_CLK period the RTC generates an interrupt Second Interrupt if it is enabled in RTC IE register The second block is a 32 bit programmable counter that can be initialized to the current system time The system time is incremented at the TR_CLK rate and compared with a programmable date stored in the RTC_ALR register in order to generate an alarm interrupt if enabled in RTC IE register 9 3 2 RESET RTC REGISTERS The RTC_SECCNTV RTC_ALMCNTV RTC_SECCNT and RTC_ALMCNT registers are reset by cold boot or DPDWAKEUP reset 9 3 3 RTC FLAG ASSERTION The RTC Second interrupt flag SECIF is asserted on each RTC Core clock cycle before the update of the RTC Counter The RTC Overflow interrupt flag OVFIF is asserted on the last RTC Core clock cycle before the counter reaches 0x0 The RTC Alarm interrupt flag ALMIF are asserted on the last RTC Core clock cycle before the counter rea
107. a set of differential MIC input and the microphone input path includes a programmable gain amplifier PGA and MIC boost to adjust the analog volume Also there is a digital volume attenuation control after ADC which can adjust the volume of digital output by bit shift Besides Audio Gain Controller AGC is programmable to monitor the input and further adjust the volume properly The DAC includes a power supply input for DAC driver a power supply input pins for DAC a DAC VMID output and a DAC Common mode output The Codec circuit requires a 2 7 3 6 V operating voltage supply 13 2 FEATURES 13 2 1 12S Features I2S can operate as either master or slave Capable of handling 8 16 24 32 bit data length Mono and stereo audio data supported 12S and MSB justified data format supported 8 word 32 bit FIFO data buffers are provided Generate interrupt requests when buffer levels cross a programmable boundary Controls include reset stop and mute options separately for I2S input and 12S output VVVVVVV 13 2 2 Codec Features Mono Codec Audio sample rates 8K 16K 32K and 48KHz ADC lt gt SNR 94dB 120dBr A W lt gt DR 94dB 60dBr A W lt gt THD N 80dB 0dBr gt DAC lt gt SNR 90dB 120dBr A W lt gt DR 900B 60dBr A W lt gt THD N 75dB 0dBr gt Differential microphone interface lt gt Programmable gain amplifier PGA 12dB 33dB lt gt MIG boost gain 0 12 20 300B lt
108. ace The LSB represents the first bit to transmit The Divisor Latch Access Bit DLAB in UARTn LC register must be zero in order to access this register Nam Description ESA 7 0 TH 7 0 The byte will be sent when it is the oldest byte in TX FIFO and the transmitter is available 12 7 3 UART n Divisor Latch LSB registers UARTn DLL n 0 1 Address Offset 0x00 The UART Divisor Latch is part of the UART Baud Rate Generator and holds the value used optionally with the Fractional Divider to divide the UARTn PCLK clock in order to produce the baud rate clock which must be the multiple of the desired baud rate that is specified by the Oversampling Register typically 16X The UARTn DLL and UARTn DLM registers together form a 16 bit divisor and DLAB bit in UARTn LC register must be one in order to access these registers DLL contains the lower 8 bits of the divisor and DLM contains the higher 8 bits A zero value is treated like 0x0001 T ETA Bit tion determines the baud rate of the UART 12 7 4 UART n Divisor Latch MSB register UARTn DLM n 0 1 Address Offset 0x04 318 Reserved Bi BEERS 7 0 DLM 7 0 The UART Divisor Latch MSB Register along with the DLL register determines the baud rate of the UART SONiX TECHNOLOGY CO LTD Page 124 Version 1 4 NONA gie ade 12 7 5 UART n Interrupt Enable register UARTn IE n 0 1 Address Offset 0x04 The DLAB bit in UARTn LC register must be zero in order to ac
109. acitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time The loading capacitance values must be adjusted according to the selected oscillator The AUEHS crystal is switched on and off using the AUEHSEN bit in Analog Block Control register SYSO ANBCTRL 3 2 3 4 External Low speed ELS Clock The low speed oscillator can use 32768 crystal oscillator circuit 3 2 3 5 CRYSTAL Crystal devices are driven by LXIN LXOUT pins The 32768 crystal and 10pF capacitor must be as near as possible to MCU The ELS crystal is switched on and off using the ELSEN bit in Analog Block Control register SYSO_ANBCTRL SONG TECHNOLOGY CO LTD Page 47 Version 1 4 NONA N edlen LXIN 32768Hz XOUT MCU o Al Lo 10pF 10pF VDD SSA Note Connect the Crystal Ceramic and C as near as possible to the LXIN LXOUT VSS pins of MCU The capacitor between LXIN LXOUT and VSS must be 10pF 3 2 3 6 Bypass Mode In Bypass mode the external clock signal square sinus or triangle with 50 duty cycle must be provided to drive the XTALIN LXTALIN pin while the XTALOUT LXTALOUT pin should be the inverse of the input clock signal External clock source EHS X tal can have a frequency of up to 25 MHz Select this mode by setting EHSEN bit in Analog Block Control register SYSO ANBCTRL Bypass ELS X TAL must have a frequen
110. age Power on reset sequence is as following Power up System detects the power voltage up and waits for power stable External reset only external reset pin enable System checks external reset pin status If external reset pin is not high level the system keeps reset status and waits external reset pin released System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successfully and supply to system clock Program executing Power on sequence is finished and program executes from Boot loader if BLEN bit 21 or from 0x0 if BLEN bit 0 VN vvv SONiX TECHNOLOGY CO LTD Page 37 Version 1 4 I NI y SN32F100 Series S S X 32 Bit Cortex M0 Micro Controller 3 1 2 WATCHDOG RESET WDT RESET Watchdog reset is a system protection In normal condition system works well and clears watchdog timer by program Under error condition system is in unknown situation and watchdog can t be clear by program before watchdog timer overflow Watchdog timer overflow occurs and the system is reset After watchdog reset the system restarts and returns normal mode Watchdog reset sequence is as following e Watchdog timer status System checks watchdog timer overflow status If watchdog timer overflow occurs the System is reset System initialization All system registers is set as initial conditions and system is ready Oscillator warm up Oscillator operation is successf
111. amplitude of ADC High byte 13 7 4 ADC Setting 4 register ADC SETA Address Offset 0x570 3 8 Reserved 7 0 HB L AGC Control High bound setting for output amplitude of ADC Low byte 13 7 5 ADC Setting 5 register ADC SET5 Address Offset 0x580 AAA ENS ES NOR_POD AGC Control R W The period of gain update at normal mode when AGC is enabled Fs Audio sampling rate 0000 1 Fs x 2 0 0001 1 Fs x 21 1110 1 Fs x 2 14 1111 1 Fs x 2 15 13 7 6 ADC Setting 6 register ADC SET6 Address Offset 0x590 EIERE M AA ES EE MUTE POD AGC Control R W The period of gain update at mute mode when AGC is enabled Fs Audio sampling rate 0000 1 Fs x 2 0 0001 1 Fs x 2 1 1110 1 Fs x 2 14 1111 1 Fs x 2 15 13 7 7 ADC Setting 7 register ADC SET7 Address Offset 0x5A0 31 8 Reserved PR 0 SONiX TECHNOLOGY CO LTD Page 144 Version 1 4 O Q NN 9 NX SN32F100 Series N N A A 32 Bit Cortex M0 Micro Controller 7 0 SEARCH_TH_H AGC Control 0x03 Threshold for activating AGC High byte Once ADC output is larger than the threshold AGC will update internal digital gain until the output amplitude is between high bound and low bound 13 7 8 ADC Setting 8 register ADC SET8 Address Offset 0x5BO Gus eee SEARCH TH L BEE Control Threshold for activating AGC Low byte 13 7 9 ADC Setting 9 register ADC SET9 Address Offset 0x5CO ne e MUTE TH H AGC Control RAN
112. ard Operating Conditions Typical temperature Ta 25 C Operating Temperature 40C Ta lt 85 C for Industrial Class The below data covers process corner range SS TT FF PARAMETER DESCRIPTION un De max UNIT Voltage Supply voltage for core and external rail 18 33 36 v VDDriserate rise rate Veon VDD rise rate to ensure internal power on reset oo Toms Power Consumption System clock 12MHz 7 mA Iddi Normal mode System clock 50MHz System clock 12MHz Supply Current 1 2 3 6 Idd2 Sleep Mode 1 2 8 6 System clock 16KHz 116 Vdd 3 3V GE See en iioi es perse Me ste Vdd 3 3V 1 RD und ee mew d ear Port Pins RESET pin High level input voltage Vu Cf vd vdd v Low level input voltage Vw Css ovaal v imutvotage fm 0 vdd v Outputvoltage ve Ct vdd v VO port pull up resistor__ Rey Vin Vss Vdd 33V 1 40 60 80 KO __VO port pulldown resistor_ Reo Vinsaav 40 60 80 Kol TE E pes Pull up resistor disable Vin Vdd 2 ua ort input leakage curren e GE id 9 I2C bus pins P0 2 P0 3 P3 14 and P3 15 Vin Vad D sw 2 o ow D por and RESET pins Juwevescos s 10 ma High drive output pin Vop Vdd 0 5V 12 20 mA P0 0 P0 3 P3 12 P3 15 bil UO Low level output sink current Standard port and RESET pins Vor Vss 0 5V 5 10 ma Codec ADC Analog Power AVD
113. are as part of timer initialization The SYST CALIB register may be read and used as the value for RELOAD if the CPU or external clock is running at the frequency intended for use with the SYST CALIB value The following example illustrates selecting the SysTick timer reload value to obtain a 10 ms time interval with the system clock set to 50 MHz The SysTick clock system clock 50 MHz RELOAD system tick clock frequency x 10 ms 1 50 MHz x 10 ms 0x0007A11F ret 230 RELOAD be to load into the SYST CVR when the counter is enabled and i i mr it reaches 0 2 2 3 3 System Tick Timer Current Value register SYSTICK VAL Address 0xE000 E018 Refer to Cortex MO Spec Bii Name Description Attribute Resel 31 24 Reserved RR SONG TECHNOLOGY CO LTD Page 29 Version 1 4 NONA NS reden CURRENT Reading this register returns the current value of the System Tick counter R W 0x7E7F35 Writing any value clears the System Tick counter and the COUNTFLAG bit in SYST_CSR 2 2 3 4 System Tick Timer Calibration Value register SYST_CALIB Address 0xE000 E01C Refer to Cortex MO Spec NOREF Indicates the reference clock to MO is provided or not 1 1 No reference clock provided SKEW Indicates whether the TENMS value is exact an inexact TENMS value can affect the suitability of SysTick as a software real time clock 0 TENMS value is exact 1 TENMS value is inexact or not given 29 24 Reseved 280 TENMS R
114. ate and power level Different system executing rates have different system minimum operating voltage The electrical characteristic section shows the system voltage to executing rate relationship System Mini Operating Voltage Vdd V P g Normal Operating Area System Reset Voltage System Rate Fcpu Normally the system operation voltage area is higher than the system reset voltage to VDD and the reset voltage is decided by LVD detect level The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating voltage above the system reset voltage 3 1 3 3 BROWN OUT RESET IMPROVEMENT How to improve the brown reset condition There are some methods to improve brown out reset as following LVD reset Watchdog reset Reduce the system executing rate External reset circuit Zener diode reset circuit Voltage bias reset circuit External reset IC Note The Zener diode reset circuit Voltage bias reset circuit and External reset IC can completely improve the brown out reset DC low battery and AC slow power down conditions SONG TECHNOLOGY CO LTD Page 39 Version 1 4 I SN y SN32F100 Series S N A X 32 Bit Cortex M0 Micro Controller LVD reset VDD Power yss Power is below LVD Detect Voltage and System Reset System Normal Run System Status
115. ccessfully and interrupt is enabled FIFOEN Equivalent to FIFOEN bit in UARTn FIFOCTRL register R 1 Reseved INTID 2 0 Interrupt identification which identifies an interrupt corresponding to the UARTn RX FIFO 0x3 1 Receive Line Status RLS SONiX TECHNOLOGY CO LTD Page 125 Version 1 4 SONA RE 0x2 2a Receive Data Available RDA 0x6 2b Character Time out Indicator CTI 0x1 3a THRE Interrupt 0x7 3b TEMT Interrupt Other Reserved INTSTATUS Interrupt status The pending interrupt can be determined by evaluating UARTn_11 3 1 0 At least one interrupt is pending 1 No interrupt is pending Bits UARTn_II 9 8 are set by the auto baud function and signal a time out or end of auto baud condition The auto baud interrupt conditions are cleared by setting the corresponding Clear bits in the Auto baud Control Register Given the status of UARTn_II 3 0 an interrupt handler routine can determine the cause of the interrupt and how to clear the active interrupt The UARTn I register must be read in order to clear the interrupt prior to exiting the Interrupt service routine Tn II Priority 0110 Highest Overrun error OE Parity error PE Read UARTn_LS register 9 Framing error FE or Break interrupt Bl Read UARTn_RB register RDA 0100 RX data in FIFO reached trigger level FCRO 1 or UART FIFO drops below trigger level THRE 0010 TEMT 1110 THRE if source of interrupt or Writ
116. cess this register Bi Name 31 10 Reserved ABTOIE Enables the auto baud time out interrupt enable bit 0 Disable 1 Enable ABEOIE End of auto baud interrupt enable bit 0 Disable 1 Enable TEMTIE TEMT interrupt enable bit The status of this interrupt can be read from TEMT bit in UARTn LS register 0 Disable 1 Enable 8 Reserved HD tom Receive Line Status RLS interrupt enable bit It The status of this interrupt can be read from UARTn LS 4 1 0 Disable 1 Enable THRE interrupt enable bit TAREE The status of this interrupt can be read from THRE bit in UARTn LS RAN register 0 Disable 1 Enable RDAIE RDA interrupt enable bit Enables the Receive Data Available interrupt It also controls the Character Receive Time out interrupt 0 Disable 1 Enable 12 7 6 UART n Interrupt Identification register UARTn II nz0 1 Address Offset 0x08 This register provides a status code that denotes the priority and source of a pending interrupt The interrupts are frozen during a UARTn II register access If an interrupt occurs during a UARTn II register access the interrupt is recorded for the next UARTn II register access Bi Name Descriptior Attribute Reset 3110 Reseved Pn ABTOIF Auto baud time out interrupt flag 0 Auto baud has not timed out 1 Auto baud has timed out and interrupt is enabled ABEOIF End of auto baud interrupt flag 0 Auto baud has not finished 1 Auto baud has finished su
117. ches the RTC Alarm counter reload value stored in the Alarm register SONG TECHNOLOGY CO LTD Page 94 Version 1 4 SONI IX SN32F100 Series 32 Bit Cortex M0 Micro Controller 9 3 4 RTC OPERATION The following figure shows the RTC waveform when it is configured with RTC_SECCNTV 3 RTC_ALMCNTV 0x1000 RTC_PCLK V V 0x3 I 1 Ox1 A 0x2 0x3 Y 0x0 ACA Vnus AJ RTC SECCNT y oxo Y 0x1 oe Y 0x3 d 0x0 pos Y 0x2 Y og 0x0 RTC SECIF o cleared by SW V RTC ALMCNT X 0x1000 0x1001 0x0 0x1 RTC_ALMIF 2 RTC PCLK RTC_SECCNT 0x0 TN 0x1 0x2 jos 0x0 RTC_ALMCNT 0x1 0x2 Y 0x3 0x0 0x1 V 0x2 oa d 0x0 y 0x1 y 0x2 2 1 A J A OxFFFFFFFD y OXFFFFFFFE OxFFFFFFFF 0x0 RTC_OVFIF Cleared by SW SONG TECHNOLOGY CO LTD Page 95 Version 1 4 S y SONAX 9 4 BLOCK DIAGRAM EHS_XTAL 128 ELS_XTAL ILRC SRC_SEL CLKSEL RTCEN SN32F100 Series 32 Bit Cortex MO Micro Controller SECIE BEBE SECOND Interrupt RTC SECCNTV RTC SECCNT SECIF SECOND RTC ALMCNTV ALMIF RTC ALMCNT OVFIF SONG TECHNOLOGY CO LTD Page 96 ALM
118. contains the reset source except DPDWAKEUP reset since the LPFLAG bit in PMU CTRL register had presented this case Reserved 0 PORRSTF POR reset flag Set by HW when a POR reset occurs 0 Read No POR reset occurred Write Clear this bit 1 POR reset occurred EXTRSTF External reset flag Set by HW when a reset from the RESET pin occurs 0 Read No reset from RESET pin occurred Write Clear this bit 1 Reset from RESET pin occurred LVDRSTF LVD reset flag Set by HW when a LVD reset occurs 0 Read No LVD reset occurred Write Clear this bit 1 LVD reset occurred WDTRSTF WDT reset flag Set by HW when a WDT reset occurs 0 Read No watchdog reset occurred Write Clear this bit 1 Watchdog reset occurred SWRSTF Software reset flag Set by HW when a software reset occurs 0 Read No software reset occurred Write Clear this bit 1 Software reset occurred 3 3 7 LVD Control register SYSO LVDCTRL Address Offset 0x18 The LVD control register selects four separate threshold values for generating a LVD interrupt to the NVIC or LVD reset Reserved O S O LVDEN LVD enable 0 Disable 1 Enable LVDRSTEN LVD Reset enable 0 Disable 1 Enable SONG TECHNOLOGY CO LTD Page 53 Version 1 4 I No WAY SN32F100 Series S Y NS N N 32 Bit Cortex M0 Micro Controller 186 Reserved PD LVDINTLVL 1 0 LVD interrupt level 00 The interrupt assertion threshold voltage is 2 00V 01 The interrupt assertion threshold voltage is 2 40V
119. cy of 32 768 KHz You select this mode by setting ELSEN bit in Analog Block Control register SYSO ANBCTRL XTALIN XTALOUT LXTAHN LXTALOUT The 1 to 25 MHz EHS X TAL has the advantage of producing a very accurate rate External X TAL on the main clock EHS ELS X TAL ELS X TAL must have a frequency of 32 768 KHz Load capacitors SONG TECHNOLOGY CO LTD Page 48 Version 1 4 N N y SN32F100 Series S N A X 32 Bit Cortex M0 Micro Controller 3 2 4 SYSTEM CLOCK SYSCLK SELECTION After a system reset the IHRC is selected as system clock When a clock source is used directly or through the PLL as system clock it is not possible to stop it A switch from one clock source to another occurs only if the target clock source is ready clock stable after startup delay or PLL locked If a clock source which is not yet ready is selected the switch will occur when the clock source is ready Ready bits in SYSO CSST register indicate which clock s is are ready and SYSCLKST bits in SYSO CLKCFG register indicate which clock is currently used as system clock 3 2 5 CLOCK OUT CAPABITITY The MCU clock output CLKOUT capability allows the clock to be output onto the external CLKOUT pin The configuration registers of the corresponding GPIO port must be programmed in alternate function mode One of 6 clock signals can be selected as clock output HCLK IHRC ILRC PLL clock output ELS X TAL EHS X TAL AUEHS X TAL Nooo n
120. d SONG TECHNOLOGY CO LTD Page 67 Version 1 4 SONA AE EEE 27 26 CFG13 1 0 CFG1 1 0 Geng SN32F100 Series 32 Bit Cortex MO Micro Controller 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 13 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 12 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 11 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 10 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 9 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 8 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 7 00 Pull up resistor enabled 01 Pull down resistor enabled 10 Inactive no pull down pull up resistor enabled 11 Repeater mode Configuration of Pn 6 00 Pull up resistor enabled 01 Pull down resistor enabled
121. e can be reset by SW by setting the SYSRESREQ bit in the AIRC register in Cortex MO spec Note To write to this register user must write 0x05FA to the VECTKEY field at the same time otherwise the processor ignores the write Bit lame VECTKEY Register key Read as unknown Write 0x05FA to VECTKEY otherwise the write is ignored ENDIANESS Data endianness implemented 0 Little endian 1 Big endian System reset request This bit read as 0 0 No effect 1 Requests a system level reset Reserved for debug use This bit read as 0 When writing to the register you must write 0 to this bit otherwise behavior is Unpredictable SONG TECHNOLOGY CO LTD Page 33 Version 1 4 AAA I No AM SN32F100 Series Sv NS A N 32 Bit Cortex M0 Micro Controller 0 Reserved Rn SONG TECHNOLOGY CO LTD Page 34 Version 1 4 N o WW SONIX me 2 5CODE OPTION TABLE Address Ox1FFF 2000 Code Security 15 0 Code Security R W OxFFFF OxFFFF CSO 0x5A5A CS1 OxA5A5 CS2 0x55AA CS3 en med nn SONG TECHNOLOGY CO LTD Page 35 Version 1 4 SONA oe 2 6 CORE REGISTER OVERVIEW noun E R General purpose registers High registers d Ro R2 Stack Pointer SP R13 Link Register LR R14 Program Counter PC R15 PSR Program Status Register a Interrupt mask register gt Special registers CONTROL Control Register RO R12 General purpose registers for data operation
122. e TC MROIE 0 Disable 1 Enable 6 7 7 CT16Bn Match register 0 3 CT16Bn MRO 3 nz0 1 Address Offset 0x18 0x1C 0x20 0x24 The Match register values are continuously compared to the Timer Counter TC value When the two values are equal actions can be triggered automatically The action possibilities are to generate an interrupt reset the Timer Counter or stop the timer Actions are controlled by the settings in the CT16Bn MCTRL register 6 7 8 CT16Bn Capture Control register CT16Bn_CAPCTRL nz0 1 Address Offset 0x28 The Capture Control register is used to control whether the Capture register is loaded with the value in the Counter timer when the capture event occurs and whether an interrupt is generated by the capture event Setting both the rising and falling bits at the same time is a valid configuration resulting in a capture event for both edges Note HW will switch VO Configuration directly when CAPOEN 1 E Name TT CAPOEN Capture 0 function enable bit R W 0 Disable 1 Enable Capture 0 function for external Capture pin 2 3 Reserved Hk Interrupt on CT16Bn CAPO signal event a CAPO load due to a mm CT16Bn CAPO signal event will generate an interrupt 0 Disable 1 Enable m NN Capture Reset on CT16Bn CAPO signal falling edge pue 0 Disable 1 Enable a sequence of 1 then 0 on CT16Bn CAPO signal will cause SONG TECHNOLOGY CO LTD Page 78 Version 1 4 NONA aai Trail CAPO
123. e THR register TEMT if source of interrupt or Write THR register Minimum of one character in the RX FIFO and no character input or removed during a time period Read UARTn_RB register 1100 gu depending on how many characters are in FIFO and what the trigger level is set at 3 5 to 4 5 character times SONiX TECHNOLOGY CO LTD Page 126 Version 1 4 N N o WY SN32F100 Series Ss Q N A X 32 Bit Cortex MO Micro Controller 12 7 7 UART n FIFO Control register UARTn FIFOCTRL n 0 1 Address Offset 0x08 This register controls the operation of the UART RX and TX FIFOs oe Se Reserved RXTL 1 0 RX Trigger Level These two bits determine how many receiver UART FIFO characters must be written before an interrupt is activated 00 Trigger level O 1 character 01 Trigger level 1 4 characters 10 Trigger level 2 8 characters 11 Trigger level 3 14 characters EN O ER NC TXFIFORST TX FIFO Reset bit 0 No impact on either of UART FIFOs 1 Writing a logic 1 to reset the pointer logic in UART TX FIFO HW shall clear this bit automatically RXFIFORST RX FIFO Reset bit 0 No impact on either of UART FIFOs 1 Writing a logic 1 to reset the pointer logic in UART RX FIFO HW shall clear this bit automatically FIFOEN FIFO enable 0 No effect 1 Enable for both UART Rx and TX FIFOs and UARTn FIFOCTRL 7 1 access This bit must be set for proper UART operation 12 7 8 UART n Line Control register UARTn LC nz0 1 Addres
124. e generation pre scaler divisor value If this field is O fractional baud rate generator will not impact the UART baud rate 12 7 13UART n Control register UARTn CTRL n 0 1 Address Offset 0x30 In addition to HW flow control this register enables implementation of SW flow control When TXEN 1 the UART transmitter will keep sending data as long as they are available As soon as TXEN bit becomes 0 UART transmission will stop It is strongly suggested to let the UART HW implemented auto flow control features take care of limit the scope of TXEN to SW flow control Note It is advised that TXEN and RXEN are set in the same instruction if needed in order to minimize the setup and the hold time of the receiver E EE ER TXEN When this bit is 1 data written to the UARTn TH register is output on the TXD pin as soon as any preceding data has been sent If this bit is cleared to 0 while a character is being sent the transmission of that character is completed but no further characters are sent until this bit is set again In other words a 0 in this bit blocks the transfer of characters from the UARTn TH register or TX FIFO into the transmit shift register RXEN 0 Disable RX related function 1 EE RX 51 Reserved UARTEN A enable 0 Disable All UART shared pins act as GPIO 1 Enable HW switches GPIO to UART pin automatically 12 7 14UART n Half duplex Enable register UARTn HDEN n 0 1
125. e number of implemented interrupts Name PRI 4 n 3 Each priority field holds a priority value 0 192 The lower the value the x greater the priority of the corresponding interrupt The processor implements only bits 31 30 of each field bits 29 24 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register PRI 4 n 2 Each priority field holds a priority value 0 192 The lower the value the greater the priority of the corresponding interrupt The processor implements only bits 23 22 of each field bits 21 16 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register PRI 4 n 1 Each priority field holds a priority value 0 192 The lower the value the greater the priority of the corresponding interrupt The processor implements only bits 15 14 of each field bits 13 8 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register 7 0 PRI 4 n Each priority field holds a priority value 0 192 The lower the value the greater the priority of the corresponding interrupt The processor implements only bits 7 6 of each field bits 5 0 read as zero and ignore writes This means writing 255 to a priority register saves value 192 to the register 2 4 APPLICATION INTERRUPT AND RESET CONTROL AIRC Address 0xE000 EDOC Refer to Cortex MO Spec The entire MCU including the cor
126. elia ADC Enable Sequence 151 13 10 SIGMA DELTA DAC CONTROL FLOW EE 151 13 10 1 Sigma delta DAC Power up Segue 8 ssepe Ria d a RH d 151 13 10 2 Sipma delta DAC Power down Sequence iei desti usa basse a 151 13 10 3 Sigma delta DAC Enable Sequence see se ee SE ee EA ente eee etes enne seen ne seen Ge 151 14 24 CHANNEL COMPARATOR essa a eege ed Ee GEE Geb P ek el DNA Gede N 152 141 OVERVIEW anne E A O TAARE a 152 14 2 COMPARA TOR OPERATION ia 153 14 3 COMPARATOR APPLICATION NOTICE use 154 144 COMPARATOR CONTROL REOGISTERS nn conc ee ee ee 154 441 Comparator Control register CMPM ata 154 14 4 2 Comparator Interrupt Enable register CMP TE BE 155 14 4 3 Comparator Interrupt Status register CMP RIS eee ss se se esse Se ee sana ansa ke Se Ge ek ke Ee ee 156 1444 Comparator interrupt Clear register UMP 1C vic na 156 15 BEE AAS at Ga 157 D DENN 157 15 2 EMBEDDED FLASH MEMORY 157 15 3 FEATURES rS 157 154 ORGANIZATION EN 158 133 NN 158 15 5 PROGRANVERAS Es a ee hen 158 15 7 EMBEDDED BOOT LOADER lt A AR 158 15 8 FLASEHMEMORYEONTROLLER FM One a 159 DAL CODE ETTE 159 15 82 PROGRAM FLASH MEMORY eeneg 160 15 8 3 ERASE H 160 15 8 3 1 PAGE ERA Everest set ao so Ga eed Es 160 15 8 32 EE 160 159 READ PROTECTION E 160 15 10 ME REGISTERS ee 161 15 10 1 Flash Status register FLASH STATUS niat gea eva Lx ak RU bed veran
127. eload value for 10ms timing subject to system clock skew errors If the R W OxATIFF value reads as zero the calibration value is not known SONG TECHNOLOGY CO LTD Page 30 Version 1 4 NG y j SONIX oe pated 2 3 NESTED VECTORED INTERRUPT CONTROLLER NVIC All interrupts including the core exceptions are managed by the NVIC NVIC has the following Features The NVIC supports 32 vectored interrupts 4 programmable interrupt priority levels with hardware priority level masking Low latency exception and interrupt handling Efficient processing of late arriving interrupts Implementation of System Control Registers Software interrupt generation VVVVVV 2 3 1 INTERRUPT AND EXCEPTION VECTORS 2 3 2 NVIC REGISTERS SONG TECHNOLOGY CO LTD Page 31 Version 1 4 Y NS 9 NX SN32F100 Series N N A A 32 Bit Cortex MO Micro Controller 2 3 2 1 IRQO 31 Interrupt Set Enable Register NVIC ISER Address 0xE000 E100 Refer to Cortex MO Spec The ISER enables interrupts and shows the interrupts that are enabled SETENA 31 0 Interrupt set enable bits Write gt 0 No effect 1 Enable interrupt Read gt 0 Interrupt disabled 1 Interrupt enabled 2 3 2 2 IRQO 31 Interrupt Clear Enable Register NVIC_ICER Address 0xE000 E180 Refer to Cortex MO Spec The ICER disables interrupts and shows the interrupts that are enabled CLRENA 31 0 Interrupt clear enable bits Write gt 0 No effect 1 Disable interrupt Read
128. errupt status is active Framing Error flag When the stop bit of a received character is a logic 0 a framing error occurs A UARTn LS register read clears FE bit The time of the framing error detection is dependent on FIFOEN bit in UARTn FIFOCTRL register Upon detection of a framing error the RX will attempt to re synchronize to the data and assume that the bad stop bit is actually an early start bit However it cannot be assumed that the next received byte will be correct even if there is no Framing Error 0 Framing error status is inactive 1 Framing error status is active Parity Error flag When the parity bit of a received character is in the wrong state a parity error occurs A UARTn LS register read clears PE bit Time of parity error detection is dependent on FIFOEN bit in UARTn FIFOCTRL register 0 Parity error status is inactive 1 Parity error status is active Overrun Error flag The overrun error condition is set as soon as it occurs A UARTn LS register read clears OE bit OE 1 when UART RSR has a new character assembled and the UARTn RB FIFO is full In this case the UARTn RB FIFO will not be overwritten and the character in the UARTn RS register will be lost 0 Overrun error status is inactive 1 Overrun error status is active Receiver Data Ready flag RDR 1 when the UARTn RB FIFO holds an unread character and is SONiX TECHNOLOGY CO LTD Page 128 Version 1 4 os NONA wa cleared
129. flag for capture channel 0 0 No interrupt on CAPO 1 Interrupt requirements met on CAPO Interrupt flag for match channel 3 0 No interrupt on match channel 3 1 Interrupt requirements met on match channel 3 Interrupt flag for match channel 2 0 No interrupt on match channel 2 1 Interrupt requirements met on match channel 2 Interrupt flag for match channel 1 0 No interrupt on match channel 1 1 Interrupt requirements met on match channel 1 Interrupt flag for match channel 0 0 No interrupt on match channel 0 1 Interrupt requirements met on match channel 0 6 7 13 CT16Bn Timer Interrupt Clear register CT16Bn IC nz0 1 Address Offset 0x3C Reserved 0 1 Clear CAPOIF bit 1 Clear MR3IF bit 1 Clear MR2IF bit 1 Clear MR1IF bit 1 Clear MROIF bit SONG TECHNOLOGY CO LTD Page 80 Version 1 4 N M 2FI j SONIX ke D 32 BIT TIMER WITH CAPTURE FUNCTION 7 1 OVERVIEW Each Counter timer is designed to count cycles of the peripheral clock PCLK or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers Each counter timer also includes one capture input to trap the timer value when an input signal transitions optionally generating an interrupt In PWM mode up to two match registers can be used to provide a single edge controlled PWM output on the match output pins 7 2FEATURES gt Two 32 bit counter timers
130. function Differential Microphone input Build in Microphone Bias Voltage support SNR 94dB THD N 800B 24 channel Comparator Interface Two I2G controllers supporting DC bus specification with multiple address recognition and monitor mode Two UART controllers with fractional baud rate generation Two SPI controllers with SSP features and multi protocol capabilities 12S Function with mono and stereo audio data supported MSB justified data format supported and can operate as either master or slave System clocks External high clock Crystal type 10MHz 25MHz External Audio high clock Crystal type 16 384MHz External low clock Crystal type 32 768 KHz Internal high clock RC type 12 MHz Internal low clock RC type 16 KHz PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal May be run from the external high clock or the internal high RC oscillator Clock output function which can reflect the internal high low RC oscillator HCLK PLL output and external high low clock Package Chip form support LQFP 80 pin LQFP 64 pin LQFP 48 pin Version 1 4 NONA SN32F100 Series 32 Bit Cortex M0 Micro Controller Features Selection Table Chip rom RAM Boot OFF 9 uart spi c 128 TIMER pwm EE wine Desc enge Max ADC DAC Wakeup SN32F107F 64KB 8KB ake 50MHz 1 1 2
131. gisters and is derived from the system clock The WDT PCLK is used for the watchdog timer counting Several clocks can be used as a clock source for WDT PCLK clock IHRC ILRC ELS X tal and HCLK The clock to the watchdog register block can be disabled in AHB Clock Enable register SYS1 AHBCLKEN register for power savings Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source SONG TECHNOLOGY CO LTD Page 90 Version 1 4 SONIX 8 2 BLOCK DIAGRAM WDT_PCLK gt 128 WDT_TC SN32F100 Series 32 Bit Cortex M0 Micro Controller Feed Watchdog WDT_FEED Feed OK v A Reload Counter 8 bit Down Counter underflow Enable Counter M WDT Ch WDINT WDTIE WDTEN gt WDT Reset SONiX TECHNOLOGY CO LTD Page 91 WDT Interrupt Version 1 4 Y N 9 NX SN32F100 Series DS N A A 32 Bit Cortex MO Micro Controller 8 3 WDT REGISTERS Base Address 0x4001 0000 8 3 1 Watchdog Configuration register WDT CFG Address Offset 0x00 The WDT CFG register controls the operation of the Watchdog through the combination of WDTEN and WDTIE bits This register indicates the raw status for Watchdog Timer interrupts A WDT interrupt is sent to the interrupt controller if both the WDINT bit and the WDTIE bit are set WDKEY Watchdog register key Read as 0 When writing to the
132. grammed 31 0 DATA 31 0 Datatobeprogrammed RW 0 SONiX TECHNOLOGY CO LTD Page 161 Version 1 4 Ns No TRY SN32F100 Series SO a N 32 Bit Cortex M0 Micro Controller 15 10 4Flash Address register FLASH_ADDR Address offset 0x10 The Flash address to be erased or programmed should be updated by SW and the PG bit or PER bit shall be set before filling in the Flash address FAR 31 0 Flash Address Choose the Flash address to erase when Page Erase is selected or to program when Page Program is selected Note Write access to this register is blocked when the BUSY bit in the FLASH_STATUS register is set SONiX TECHNOLOGY CO LTD Page 162 Version 1 4 N cn BNO V SN32F100 Series O Ww Q A N 32 Bit Cortex M0 Micro Controller 1 SERIAL WIRE DEBUG SWD 16 1 OVERVIEW SWD functions are integrated into the ARM Cortex MO The ARM Cortex MO is configured to support up to four breakpoints and two watch points 16 2 FEATURES Supports ARM Serial Wire Debug SWD mode Direct debug access to all memories registers and peripherals No target resources are required for the debugging session Up to four breakpoints Up to two data watch points that can also be used as triggers VVVVV 16 3 PIN DESCRIPTION SWCLK _ Serial Wire Clock pin in SWD mode N SWDIO VO Serial Wire Data Input Output pin in SWD mode N 16 4 DEBUG NOTE 16 4 1 LIMITATIONS Debug mode changes the way in which reduced power
133. hat controls operation of the I2C interface When STA 1 and the I2C interface is not already in master mode it enters master mode checks the bus and generates a START condition if the bus is free If the bus is not free it waits for a STOP condition which will free the bus and generates a START condition after a delay of a half clock period of the internal clock generator If the 12C interface is already in master mode and data has been transmitted or received it transmits a Repeated START condition STA may be set at any time including when the 12C interface is in an addressed slave mode When STO 1 in master mode a STOP condition is transmitted on the I2C bus When the bus detects the STOP condition STO is cleared automatically In slave mode setting STO bit can recover from an error condition In this case no STOP condition is transmitted to the bus The HW behaves as if a STOP condition has been received and it switches to not addressed slave receiver mode If STA and STO are both set then a STOP condition is transmitted on the 12C bus if it the interface is in master mode and transmits a START condition thereafter If the 12C interface is in slave mode an internal STOP condition is generated but is not transmitted on the bus Note 1 I2CEN shall be set at last gt 2 HW will assign SCLO SCL1 and SDAO SDA1 pins as output pins with open drain function instead of GPIO automatically and HW will assign SCLO SCL1 and S
134. he FLASH memory may be programmed via the SONIX 32 bit MCU programming interface or by application code for maximum flexibility The SN32F100 series MCU provides security options at the disposal of the designer to prevent unauthorized access to information stored in FLASH memory gt The MCU is stalled during Flash program and erase operations although peripherals Timers WDT VO PWM etc remain active gt Watchdog timer should be cleared if enabled before the Flash write or erase operation The erase operation sets all the bits in the Flash page to logic 1 gt HW will hold system clock and automatically move out data from RAM and do programming after programming finished HW will release system clock and let MCU execute the next instruction 15 2 EMBEDDED FLASH MEMORY The Flash memory is organized as 32 bit wide memory cells that can be used for storing both code and data constants and is located at a specific base address in the memory map of chip The high performance Flash memory module in chip has the following key features gt Memory organization the Flash memory is organized as a User ROM Boot ROM User ROM Up to 16K x 32 bits divided into 64 pages of 1024 Bytes Boot ROM Up to 1K x 32 bits divided into 4 pages of 1024 Bytes The Flash interface implements instruction access and data access based on the AHB protocol It implements the logic necessary to carry out Flash memory operations Program Erase
135. hen the clock is disabled the peripheral register values may not be readable by SW and the value returned is always 0x0 2 HW will replace GPIO with CLKOUT function directly if CLKOUTSEL is Not 0 KE NE NR CLKOUTSEL 2 0 Clock output source 000 Disable 001 HCLK 010 PLL clock output 011 ILRC clock 100 IHRC clock 101 ELS clock 110 EHS clock 111 AUEHS clock 27 25 boli a Enables clock for WDT 0 Disable 1 Enable eed EE clock for RTC 0 Disable 1 Enable eye Enables clock for I2S 0 Disable 1 Enable ARES Enables clock for DCH 0 Disable 1 Enable TE clock for I2C1 Disable r Enable 19 18 Reserved Bu a clock for UART1 Disable dE Enable Md ad Enables clock for UARTO 0 Disable 1 Enable _15 14 Reseved Enables clock for SSP1 0 Disable 1 Enable ld hand EI us clock for SSPO 0 Disable 1 Enable Ma Enables clock for Comparator 0 Disable 1 Enable SONG TECHNOLOGY CO LTD Page 56 Version 1 4 N No TRY SN32F100 Series S Q S N 32 Bit Cortex M0 Micro Controller 18 Reseved Di Enables clock for CT32B1 0 Disable 1 Enable Bi Enables clock for CT32B0 0 Disable 1 Enable EET Ee for CT16B1 Disable 1 Enable CT16BOCLKEN Enables clock for CT16B0 0 Disable 1 Enable 5 Reserved GPIOCLKEN Enables clock for GPIO 0 Disable 1 Enable 2 0 Reserved 3 4 2 APB Clock Prescale register 0 SYS1 APBCPO Address
136. highest rate 2 A falling edge on URXD pin triggers the beginning of the start bit The rate measuring counter will start counting UARTn PCLK cycles 3 During the receipt of the start bit 16 pulses are generated on the RSR baud input with the frequency of the UART input clock guaranteeing the start bit is stored in the RSR 4 During the receipt of the start bit and the character LSB for MODE 0 in UARTn ABCTRL register the rate counter will continue incrementing with the pre scaled UART input clock UARTn PCLK 5 If MODE 0 the rate counter will stop on next falling edge of the UART RX pin If MODE 1 the rate counter will stop on the next rising edge of the URXD pin 6 The rate counter is loaded into UARTn DLM UARTn DLL and the baud rate will be switched to normal operation After setting the DLM DLL the end of auto baud interrupt ABEOINT in UARTn II register will be set if enabled The RSR will now continue receiving the remaining bits of the character gt AUTO BAUD RATE MODE 0 Waveform A 0x41 or a 0x61 lt gt Start bito V bit bm bit3 pia bits bits X bit7 Parity Y Stop URXD Start bit LSB of A or a START bit in USARTn_ABCTRL Rate Counter 16 x Baud Rtae LI 16 Cycles 16 Cycles gt AUTO BAUD RATE MODE 1 Waveform SONiX TECHNOLOGY CO LTD Page 122 Version 1 4 N y SN32F100 Series S N E X 32 Bit Cortex MO Micro Controller A 0x41 or a 0x61
137. icro Controller 9 5 9 RTC Alarm Count register RTC_ALMCNT Address offset 0x20 ALMCNTI31 0 RTC alarm counter i 810 ALMCNT 31 0 The current value of the RTC alarm counter 2 SONG TECHNOLOGY CO LTD Page 99 Version 1 4 NI y SN32F100 Series S N A X 32 Bit Cortex M0 Micro Controller 1 0 SPI SSP 10 1 OVERVIEW The SSP is a Synchronous Serial Port controller capable of operation on a SPI and 4 wire SSI bus It can interact with multiple masters and slaves on the bus Only a single master and a single slave can communicate on the bus during a given data transfer Data transfers are in principle full duplex with frames of 4 to 16 bits of data flowing from the master to the slave and from the slave to the master In practice it is often the case that only one of these data flows carries meaningful data 10 2 FEATURES Compatible with Motorola SPI and 4 wire TI SSI bus Synchronous Serial Communication Supports master or slave operation 8 frame FIFO for both transmitter and receiver 4 bit to 16 bit frame Maximum SPI speed of 25 Mbps master or 6 Mbps slave in SSP mode Data transfer format is from MSB or LSB controlled by register The start phase of data sampling location selection is 1 phase or 2 phase controlled register VVVVVVVV SONiX TECHNOLOGY CO LTD Page 100 Version 1 4 NONA ie 10 3 PIN DESCRIPTION SELn MISOn MOSIn SCKn O SSP Serial clock Master 10 SSP Serial c
138. ing 7 register ADC_SET7 E 144 13 7 8 ADC Setting O register AIG SETS aiii A AS 145 15 79 ADC Setting 9 register ADC_SET9 a 145 13 7 10 ADC Setting TU register ADE STI I nn es 145 13 7 11 ADC Setting 11 register ADC BEET A ii A Aa 145 13 7 12 ADC Setting 12 EE ET ais 145 13 7 13 ADC Setting 13 register ADOBE a 146 13 7 14 ADC Setting 14 register ADE ET AOS 146 13 7 15 ADC Setting 15 register ADC BETT Dai ER AR ek ao as OR GN N be EN EA Ge RED RS 146 13 7 16 ADC Setting 16 register APIE Eege edd 146 13 7 17 ADC Setting 18 register ADC SETS a taa 147 13 7 18 ADC Setting 19 register ADC SET ead don DIU Un eU RU os 147 13 7 19 ADC Setting 20 register ADC_SET20 ii A a A eg 148 13 7 20 ADC Senne 21 vesisier ADE SEITZ is 148 13 7 21 ADC Setting 22 register ADU SETZ2 ia 148 13 7 22 ADC Setting 23 register TADO ee 148 13 7 23 ADC Setting 24 register ADC_SET24 E 149 13 8 CODEC DAE REGISTER Sana 149 1501 DAL Setting I register DAC SETT daa 149 1502 DAC Setting 2 register DAC SET2 Es 149 12 02 DAC Setting 3 register DAG SET AD A a ti 149 13 8 4 DAC Setting 4 register DAC_SET4 EE 150 SONG TECHNOLOGY CO LTD Page 10 Version 1 4 NONA SN32F100 Series 32 Bit Cortex M0 Micro Controller 13 8 5 DAC Status register DAC STATUS ca 150 13 9 SIGMA DELTA ADC CONTROL FLOW stand en ae 150 13 94 Sigma delta ADC Power up Sequence eier ee eek se eie iia 150 13 92 Sigia delta ADC Power down Sequence u 150 13 9 3 Sipma d
139. ipped and a warning is issued by the PGERR bit in FLASH STATUS register The end of the program operation is indicated by the EOP bit in the FLASH STATUS register The main Flash memory programming sequence in standard mode is as follows Set the PG bit in the FLASH CTRL register Perform the data write at the desired address Wait for the BUSY bit to be reset Read the programmed value and verify ooo 15 8 3 ERASE The Flash memory can be erased page by page or completely Mass Erase 15 8 3 1 PAGE ERASE A page of the Flash memory can be erased using the Page Erase feature of the FMC To erase a page the procedure below should be followed Set the PER bit in the FLASH_CTRL register Program the FLASH ADDR register to select a page to erase Set the STRT bit in the FLASH CTRL register Wait for the BUSY bit to be reset Read the erased page and verify 906099 15 8 3 2 MASS ERASE When the Flash memory read protection is changed from protected to unprotected a Mass Erase of the User ROM is performed by HW before reprogramming the read protection option 15 9 READ PROTECTION The read protection is activated by setting the Code Security bytes in Code option When the Flash memory read protection is changed from protected to unprotected a Mass Erase of the User ROM is performed by HW before reprogramming the read protection option SONiX TECHNOLOGY CO LTD Page 160 Version 1 4 NG No WAY SN32F100 Series QI N A x 32 Bit C
140. is bit is automatically cleared after auto baud completion 0 Auto baud stop auto baud is not running 1 Auto baud start auto baud is running Auto baud run bit This bit is automatically cleared by HW after auto baud completion 12 7 12UART n Fractional Divider register UARTn_FD n 0 1 Address Offset 0x28 This register controls the clock prescaler for the baud rate generation and can be read and written at the user s discretion This prescaler takes the APB clock and generates an output clock according to the specified fractional requirements In most applications the UART samples received data 16 times in each nominal bit time and sends bits that are 16 input clocks wide OVERS bit allows software to control the ratio between the input clock and bit clock This is required for smart card mode and provides an alternative to fractional division for other modes Note If the fractional divider is active DIVADDVAL gt 0 and UARTn_DLM 0 the value of the UARTn DLL register must 2 3 SONiX TECHNOLOGY CO LTD Page 129 Version 1 4 NONA ve ei Bit Name 31 9 Reserved OVER8 Oversampling value 0 Oversampling by 16 1 Oversampling by 8 7 4 MULVAL 3 0 Baud rate pre scaler multiplier value MULVAL 3 0 1 0000 Baud rate pre scaler multiplier value is 1 for HW 0001 Baud rate pre scaler multiplier value is 2 for HW 1111 Baud rate pre scaler multiplier value is 16 for HW 0 DIVADDVALISO Baud rat
141. ith a stable current through R1 and R2 For power consumption issue application e g DC power system the current must be considered to whole system power consumption Note Under unstable power condition as brown out reset Zener diode reset circuit and Voltage bias reset circuit can protects system no any error occurrence as power dropping When power drops below the reset detect voltage the system reset would be triggered and then system executes reset sequence That makes sure the system work well under unstable power situation 3 1 4 5 EXTERNAL RESET IC Bypass Capacitor 0 1uF The external reset circuit also uses external reset IC to enhance MCU reset performance This is a high cost and good effect solution By different application and system requirement to select suitable reset IC The reset circuit can improve all power variation 3 1 5 SOFTWARE RESET The entire MCU including the core can be reset by software by setting the SYSRESREQ bit in the AIRC Application Interrupt and Reset Control register in Cortex MO spec The software initiated system reset sequence is as follows 1 A software reset is initiated by setting the SYSRESREQ bit 2 Aninternal reset is asserted 3 The internal reset is deasserted and the MCU loads from memory the initial stack pointer the initial program counter and the first instruction designated by the program counter and then begins execution SONG TECHNOLOGY
142. ived while the 12C is in the addressed slave receiver mode HW will clear after issuing ACK automatically Assert NACK HIGH level to SDA flag 0 No function 1 An NACK will be returned during the acknowledge clock pulse on SCLn when A data byte has been received while the I2C is in the master receiver mode HW will clear after issuing NACK automatically 0 Reseved 11 8 2 12C n Status register I2Cn STAT nz0 1 Address Offset 0x04 Check this register when I2C interrupt occurs and all status will be cleared automatically by writing l2Cn CTRL or I2Cn TXDATA register While I2CIF 1 the low period of the serial clock on the SCL line is stretched and the serial transfer is suspended When SCL is HIGH it is unaffected by the state of I2CIF I2CIF I2C Interrupt flag 0 I2C status doesn t change 1 Read 2C status changes Write Clear this flag 14 10 Reserved TIMEOUT Time out status 0 No Timeout 1 Timeout LOST ARB Lost arbitration 0 Not lost arbitration 1 Lost arbitration 7 SLV TX HIT 0 No matched slave address SLV TXHT 1 Slave address hit and is called for TX in slave mode SLV RX HIT 0 No matched slave address cw 1 Slave address hit and is called for RX in slave mode ME Mal status MN 12C is in Slave state 1 12C is in Master state START_DN Start done status 0 No START bit 1 MASTER mode gt a START bit was issued SLAVE mode gt a START bit was received NACK done status p Not
143. l of the PNP transistor outputs high voltage and MCU operates normally When VDD is below Vz 0 7V the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by Zener specification Select the right Zener voltage to conform the application 3 1 4 4 VOLTAGE BIAS RESET CIRCUIT The voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely The operating voltage is not accurate as Zener diode reset circuit Use R1 R2 bias voltage to be the active level When VDD voltage level is above or equal to 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs high SONG TECHNOLOGY CO LTD Page 42 Version 1 4 N S xX SN32F100 Series N N A A 32 Bit Cortex M0 Micro Controller voltage and MCU operates normally When VDD is below 0 7V x R1 R2 R1 the C terminal of the PNP transistor outputs low voltage and MCU is in reset mode Decide the reset detect voltage by R1 R2 resistances Select the right R1 R2 value to conform the application In the circuit diagram condition the MCU s reset pin level varies with VDD voltage variation and the differential voltage is 0 7V If the VDD drops and the voltage lower than reset pin detect level the system would be reset If want to make the reset active earlier set the R2 R1 and the cap between VDD and C terminal voltage is larger than 0 7V The external reset circuit is w
144. ller AMENDENT HISTORY Version Date Description 1 0 First version released 1 1 2013 03 29 1 Update Codec Spec Update DAC Setting 3 Register Update Sigma delta DAC Power Up Sequence 1 2 2013 04 02 Update Codec Spec Update ADC Setting 23 Register Update DAC Setting 1 Register and DAC Setting 2 Register 1 3 2013 06 04 Add SN32F100 Start Kit V1 1 description Add Comparator Output Debounce Time Update supply current Add Operation Mode Comparison Table Update System Block Diagram Update System Tick Timer description Update LQFP 64 Pin Package Information Update Comparator description Modify ADC s SEL MIC definition Update I2S s Status register default value Update ADC s SEL MIC register default value Update Code Security diagram Update Code Option Table Update High level and Low level input voltage Spec Update PO 14 DPDWAKEUP pin description 1 4 2013 07 16 DB 0 MED SUO OT PR RM S NN 0 o SONiX TECHNOLOGY CO LTD Page 2 Version 1 4 N N y SN32F100 Series O N A N 32 Bit Cortex MO Micro Controller Table of Content AMENPENT EISTORT nenne ia 2 Y PRODUCT OVERVIEW asia ae 13 EE alis EN EE AE EE OE EE OE LE EE N Or 13 1 2 SYSTEM BLOCK DIAGRAM aii tae sense iese se see ga bose Ince rai 15 L3 CLOCK GENERA TION BLOCK DIAGRAM cup ea 16 14 PINASSIGNMENT E 17 13 PINDESCRIPTIONS aaa EE EE OE EE EE 20 16 PINCIRCUIT DIAGRAMS une 25 4 CENTRAL PROCESSOR UNIT CPU ann 27 21 MEMORY MAP EE ER
145. lock Slave DependsonGPIOnCFG 0 SPI Slave Select SSI Frame Sync Maste 0 1 SSP Slave Select Slave DependsonGPION CFG 1 Master In Slave Out Master DependsonGPIOn CFG Master In Slave Out Slave N O Master Out Slave In Master 1 1 Master Out Slave In Slave DependsonGPIOnCFG SONiX TECHNOLOGY CO LTD Page 101 Version 1 4 I y s S d N N 32 Bit a den 10 4 INTERFACE DESCRIPTION 10 4 1 SPI The SPI interface is a 4 wire interface where the SSEL signal behaves as a slave select The main feature of the SPI format is that the inactive state and phase of the SCK signal are programmable through the CPOL and CPHA bits in SSPn CTRL1 register When the CPOL clock polarity control bit is LOW it produces a steady state low value on the SCK pin If the CPOL clock polarity control bit is HIGH a steady state high value is placed on the CLK pin when data is not being transferred The CPHA clock phase bit controls the phase of the clock on which data is sampled When CPHA 1 the SCK first edge is for data transition and receive and transmit data is at SCK 2 edge When CPHA 0 the 1 bit is fixed already and the SCK first edge is to receive and transmit data The SIO data transfer timing as following figure MLSB CPOL CPHA Diagrams Low tm Les A A A A OR Am A ss em Les A A A A OR Am A ss SONiX TECHNOLOGY CO LTD Page 102 Version 1 4 N No WY SN32F100 Series Sv E N 32 Bit Corte
146. modes work internal to the ARM Cortex MO CPU and this ripples through the entire system These differences mean that power measurements should not be made while debugging the results will be higher than during normal operation in an application During a debugging session the SysTick Timer is automatically stopped whenever the CPU is stopped Other peripherals are not affected 16 4 2 DEBUG RECOVERY User code may disable SWD function in order to use P0 12 and P0 13 as GPIO and may not debug by SWD function to debug or download FW any more SONiX provide Boot loader to check the status of P0 2 BOOT pin during boot procedure if BLEN 1 If PO 2 is Low during Boot procedure MCU will execute code in Boot loader instead of User code so SWD function is not disabled Exit Boot loader user code can still configure PO 2 as other functions such as GPIO 16 4 3 INTERNAL PULL UP DOWN RESITIORS on SWD PINS To avoid any uncontrolled IO levels the device embeds internal pull up and pull down resistor on the SWD input pins gt NJTRST Internal pull up gt SWDIO JTMS Internal pull up gt SWCLK JTCK Internal pull down Once a SWD function is disabled by SW the GPIO controller takes control again SONiX TECHNOLOGY CO LTD Page 163 Version 1 4 N Aa y j NONA zu E 1 D DEVELOPMENT TOOL SONIX provides an Embedded ICE emulator system to offer SN32F100 series MCU firmware development SN32F100 Embedded ICE Emulator System includes
147. n UARTn II register will get set if the interrupt is enabled ABTOIE bit in UARTn IE register is set and the auto baud has completed successfully The auto baud interrupts have to be cleared by setting the corresponding ABTOINTCLR and ABEOIE bits in UARTn IE register SONIX TECHNOLOGY CO LTD Page 121 Version 1 4 I NI y SN32F100 Series N N A X 32 Bit Cortex M0 Micro Controller The fractional baud rate generator must be disabled DIVADDVAL 0 during auto baud Also when auto baud is used any write to UARTn DLM and UARTn DLL registers should be done before UARTn ABCCTRL register write The minimum and the maximum baud rates supported by UART are a function of UARTn PCLK and the number of data bits stop bits and parity bits ratemin 2x PCLK lt UART PCLK lt EEGENEN 16x 215 baudrate 16 x 2 databits paritybits stopbits 12 6 2 AUTO BAUD MODES When the SW is expecting an AT command it configures the UART with the expected character format and sets the ACR Start bit The initial values in the divisor latches DLM and DLM don t care Because of the A or a ASCII coding A 2 0x41 a 0x61 the UART Rx pin sensed start bit and the LSB of the expected character are delimited by two falling edges When the ACR Start bit is set the auto baud protocol will execute the following phases 1 On START bit setting the baud rate measurement counter is reset and the RSR is reset The RSR baud rate is Switched to the
148. n the CAPO input selected by CIS bits 10 Counter Mode TC is incremented on falling edges on the CAPO input selected by CIS bits 11 Counter Mode TC is incremented on both edges on the CAPO input selected by CIS bits 6 7 6 CT16Bn Match Control register CT16Bn_MCTRL nz0 1 Address Offset 0x14 Name D iption Attribute Bit n Reserved Stop MR3 TC will stop and CEN bit will be cleared if MR3 matches TC MR3STOP 0 Disable P R W 1 Enable Enable reset TC when MR3 matches TC MR3RST 0 Disable R W 1 Enable Enable generating an interrupt when MR3 matches the value in the TC MR3IE 0 Disable R W 1 Enable Stop MR2 TC will stop and CEN bit will be cleared if MR2 matches TC MR2STOP 9 Disable P R W 1 Enable SONG TECHNOLOGY CO LTD Page 77 Version 1 4 N NN 9 NX SN32F100 Series DS N A A 32 Bit Cortex MO Micro Controller Enable reset TC when MR2 matches TC 1 Enable Enable generating an interrupt when MR2 matches the value in the TC 1 Enable Stop MR1 TC will stop and CEN bit will be cleared if MR1 matches TC MR1STOP 0 Disable 1 Enable Enable reset TC when MR1 matches TC MRIRST 0 Disable 1 Enable Enable generating an interrupt when MR1 matches the value in the TC MRIIE 0 Disable 1 Enable Stop MRO TC will stop and CEN bit will be cleared if MRO matches TC 1 Enable Enable reset TC when MRO matches TC me EE 1 Enable Enable generating an interrupt when MRO matches the value in th
149. nd C1 The RC circuit operation makes a slow rising signal into reset pin as power up The reset signal is slower than VDD power up timing and system occurs a power on signal from the timing difference Note The reset circuit is no any protection against unusual power or brown out reset 3 1 4 2 DIODE amp RC RESET CIRCUIT R1 47K ohm R2 100 ohm This is the better reset circuit The R1 and C1 circuit operation is like the simply reset circuit to make a power on signal The reset circuit has a simply protection against unusual power The diode offers a power positive path to conduct higher power to VDD It is can make reset pin voltage level to synchronize with VDD voltage The structure can SONG TECHNOLOGY CO LTD Page 41 Version 1 4 32 Bit Cortex MO Micro Controller SONAR ea rs te cnt improve slight brown out reset condition Note The R2 100 ohm resistor of Simply reset circuit and Diode amp RC reset circuit is necessary to limit any current flowing into reset pin from external capacitor C in the event of reset pin breakdown due to Electrostatic Discharge ESD or Electrical Over stress EOS 3 1 4 3 ZENER DIODE RESET CIRCUIT R1 33K ohm The Zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely Use Zener voltage to be the active level When VDD voltage level is above Vz 0 7V the C termina
150. ng externally BCLK and WS signals If I2SEN 1 and I2SMOD 1 HW will switch Master mode Mono Stereo selection bit a 0 Stereo If I2SEN 1 and l2SMOD 1 HW will switch Mono mode Mute enable bit b 0 Disable Mute 1 Enable I2SSDA Output 0 Start Transmit Receive bit Le 0 Stop Transmit Receive 1 Start Transmit Receive 13 6 2 12S Clock register 28 CLK Address Offset 0x04 mue maa LL LR LAS soup BRIN 1 BCLK MCLK 4 2 BCLK MCLK 6 3 BCLK MCLK 8 BCLK MCLK 2 n 2 If I2SEN 1 and I2SMOD 1 HW will switch BCLK MCLK 4 MCLK source selection bit MELRSEL 0 MCLK source of master is from DG PCLK 1 MCLK source of master is from External high speed X tal for audio AUXTALOUT AUXTALIN and Audio Clock Prescaler out AUEHSPRE 2 0 MCLKOEN dE output enable bit 0 Disable 1 Enable MCLKDIV 2 0 MCLK divider 0 MCLK MCLK source 1 MCLK MCLK source 2 2 MCLK MCLK source 4 n MCLK MCLK source 2 n n gt 0 13 6 3 12S Status register I28 STATUS Address Offset 0x08 Bit Name 31 21 Reserved 20 17 RXFIFOLVI3 RX FIFO used level EM 0000 0 8 RX FIFO is used Empty SONiX TECHNOLOGY CO LTD Page 141 Version 1 4 N NS 9 NX SN32F100 Series N N A A 32 Bit Cortex MO Micro Controller 0001 1 8 RX FIFO is used 0010 2 8 RX FIFO is used 1000 8 8 RX FIFO is used Full Other Reserved 16 Reseved BD TXFIFOLV 3 0 TX FIFO used level 0000 0 8 TX FIFO is used Em
151. nting until overflow occurrence The overflow signal of watchdog timer triggers the system to reset and return to normal mode after reset sequence This method also can improve brown out reset condition and make sure the system to return normal mode If the system reset by watchdog and the power is still in dead band the system reset sequence won t be successful and the system stays in reset status until the power return to normal range Reduce the system executing rate If the system rate is fast and the dead band exists to reduce the system executing rate can improve the dead band The lower system rate is with lower minimum operating voltage Select the power voltage that s no dead band issue and find out the mapping system rate Adjust the system rate to the value and the system exits the dead band issue This way needs to modify whole program timing to fit the application requirement External reset circuit The external reset methods also can improve brown out reset and is the complete solution There are three external reset circuits to improve brown out reset including Zener diode reset circuit Voltage bias reset circuit and External reset IC These three reset structures use external reset signal and control to make sure the MCU be reset under power dropping and under dead band The external reset information is described in the next section 3 1 4 EXTERNAL RESET External reset function is controlled by External RESET pin control
152. o APB bridge to AHB matrix to Cortex MO FCLK HCLK and System Timer to SYS and to PMU EN AUCLKout PLLCLKout WDTOLKEN y AHB clock for WDT D WDT WDT PCLK CLKOUT Clock Prescaler WOT MET CLKOUT Prescaler MS EE clock source register block 1124 512 2 4 8 16 WDTCLKSEL EN 4 AHB clock for CT32B1 CLKOUTSEL ina EE eremi ron gt cree CTs2B CT32BICLKEN oek Presealer clock source register block ND AHB clock for CT32B0 gt j eg ec CT32B0 PCLK CT3280 CT32B0 Clock Prescaler y CT32BOGLKEN rim clock source register block I a AHB clock for CT16B1 gt d E CT16B1_PCLK CT16B1 CT16B1 Clock Prescaler A gt AHB CTI6B1CLKEN alone clock source register block Prescaler e FExtemal Low nad pig L AHB clock for CT16B0 LXTALIN Speed Crystal Ri LXTALOUT oscillator 5 ind i CT16B0_PCLK CT16B0 CT16B0 32 768KHz CT16BOCLKEN DEn docksoure register block SYSCLKSEL 24 0 AHB clock for RTC RTCCLKEN ATC_PCLK AiG mm PLLCLKSEL clock source register block SN AHB clock for GPIO GPIO block GPIOCLKEN AHB clock for SRAM gt SRAM block AHB clock for
153. on the frequency of the RC oscillator is about 16 KHz Note The ILRC can ONLY be switched on and off by HW SONG TECHNOLOGY CO LTD Page 44 Version 1 4 I NI y SN32F100 Series S S A X 32 Bit Cortex M0 Micro Controller 3 2 2 PLL SN32F100 series MCU uses the PLL to create the clocks for the core and peripherals The input frequency range is 10MHz to 25MHz The input clock is divided down and fed to the Phase Frequency Detector PFD This block compares the phase and frequency of its inputs and generates a control signal when phase and or frequency do not match The loop filter filters these control signals and drives the voltage controlled oscillator VCO which generates the main clock and optionally two additional phases The VCO frequency range is 156MHz to 320MHz These clocks are divided by P by the programmable post divider to create the output clock s The VCO output clock is then divided by M by the programmable feedback divider to generate the feedback clock The output signal of the phase frequency detector is also monitored by the lock detector to signal when the PLL has locked on to the input clock The PLL settling time is 100 us IV Eve Felkin E F9 gt vco DIV PFD m LPF m VCO gt m gt Fclkout DIV 3 2 2 1 PLL Frequency selection The PLL frequency equations Fvco Fon F M Feikour Fvco P The
154. ond Counter Reload Value register RTC SECCNTV essere 98 9 5 7 RIC Second Count register RIC SELCNT sau 98 9 5 8 RTC Alarm Counter Reload Value register RTC ALACNTMI se ee ee se ee ee se 98 9 5 9 RTC Alarm Count register RIC ALMENT ae 99 10 Ph ed EE EE E N 100 VL DENN sv 100 10 2 FEATURES Ad 100 US ge fod Un oe e KE E 101 104 INTERFACE DESCRIPTION EE 102 ET MN 102 EET EEE i 103 I043 COMMUNICATION ELO ses ee oe oe bee ees Gede oe ie se Deo dee Ge ee ewe ee in eed ee de ke id 103 10 4 3 1 SINGLE FRAME E 103 10 432 MN EEN 104 10 5 AUTOSSBIE CAUTO CS euet Ee DE DE Ri NGT 104 10 8 SSP REGISTERS sn DE ie oe ars Ge meee Ee ee oo eee eee 105 SONIX TECHNOLOGY CO LTD Page 7 Version 1 4 IN N y SN32F100 Series O Q A N 32 Bit Cortex M0 Micro Controller 106 1 SSP n Control register 0 SSPn CTRLO A 0 1 105 1062 SSP Control resister 1 S8Pn CTRLI n 0 Miss 106 10 6 3 SSP n Clock Divider register SSPn_CLKDIV n 0 1 se se ER SE ke GE de Ee nnda 106 1064 SSP n Status register SS Pn STAT NEO na 106 10 6 5 SSP n Interrupt Enable register SSPn IE n O Il 107 10 6 6 SSP n Raw Interrupt Status register SSPn RIS n 0 1 see es ek eec Se EG AE Ed Ai 107 10 6 7 SSP n Interrupt Clear register SSPn_IC Mel Dana 107 1068 SSP n Data register SSPn_DATA n 0 Dia a 108 1 EE RE EE AE 109 ILE OVERVIEW ME EE EN EE ER N EE EE AD EE EE EE NE 109 112 MR EA 109 1
155. ontrol of the relationship between the resolution of the timer and the maximum time before the timer overflows The Prescale Counter is incremented on every PCLK When it reaches the value stored in the Prescale Register the Timer Counter is incremented and the Prescale Counter is reset on the next PCLK This causes the TC to increment on every PCLK when PR 0 every 2 PCLKs when PR 1 etc 31 0 PC 31 0 Prescale Counter RW O0 7 7 5 CT32Bn Count Control register CT32Bn CNTCTRL n 0 1 Address Offset 0x10 This register is used to select between Timer and Counter mode and in Counter mode to select the pin and edges for SONG TECHNOLOGY CO LTD Page 85 Version 1 4 TEN WN o W SN32F100 Series S Q d A N 32 Bit Cortex M0 Micro Controller counting m When Counter Mode is chosen as a mode of operation the CAP input selected by CIS bits is sampled on every rising edge of the PCLK clock After comparing two consecutive samples of this CAP input one of the following four events is recognized rising edge falling edge either of edges or no changes in the level of the selected CAP input Only if the identified event occurs and the event corresponds to the one selected by CTM bits in this register will the Timer Counter register be incremented Effective processing of the externally supplied clock to the counter has some limitations Since two successive rising edges of the PCLK clock are used to identify only one edge on the C
156. or Negative Input 14 4 COMPARATOR CONTROL REGISTERS Base Address 0x4006 6000 14 4 1 Comparator Control register CMPM Address Offset 0x00 Description Attribute 81 CMPEN Comparator control bit O RW 0 j SONiX TECHNOLOGY CO LTD Page 154 Version 1 4 N No wy SN32F100 Series m Q NS A N 32 Bit Cortex M0 Micro Controller MEN Disable P2 15 0 P3 7 0 are GPIO mode Enable Comparator negative input pins are controlled by CMCH 4 0 ML L aer ms CMPOUT a AE OES GE asi Par output flag bit The comparator output status is 1 as comparator disabled 0 Comparator internal reference voltage is less than CMPN voltage 1 RA MAE EMIT internal reference voltage is larger than CMPN voltage 13 12 Reserved CMDB 1 0 HOUR SEERDE TREE output debounce time select bit 00 1 CMP PCLK 01 2 CMP PCLK 10 3 CMP PCLK 11 No de bounce CMPOEN Comparator output pin control bit M Disable CMO pin is GPIO mode Enable comparator output pin P3 8 pin exchanges to comparator eh pin CMO pin and GPIO function is isolated CMPG Comparator interrupt trigger direction control bit 0 Rising edge trigger CMPP CMPN or comparator internal reference voltage 1 Falling edge trigger CMPP CMPN or comparator internal reference voltage po Reserved KEE CMPS 1 0 Comparator positive input voltage control bit If TCHEN 1 CMPS 1 0 bits are useless and the in
157. ortex MO Micro Controller 15 10 FMC REGISTERS Base Address 0x4006 2000 15 10 1 Flash Status register FLASH_STATUS Address offset 0x04 Reset value 0x0000 0000 EE RN RN RR RN End of operation flag 0 Flash operation programming erase is not completed 1 Set by HW when a Flash operation programming erase is completed and is cleared on the beginning of a Flash operation 43 Reserved Programming error flag PERS 0 Read No error Write Clear this flag 1 Set by HW when the address to be programmed contains a value different from OXFFFFFFFF before programming 1 Reserved Busy flag 0 Flash operation is not busy 1 Flash operation is in progress This is set on the beginning of a Flash operation clear EOP bit at the same time and reset when the operation finishes or when an error occurs by HW 15 10 2Flash Control register FLASH CTRL Address offset 0x08 817 Reseved PD Start Erase operation SR 1 Triggers an ERASE operation when set This bit is set only by SW and T resets when the BUSY bit resets PER bit shall also be 1 when XA this bit 5 2 Reserved A aa This bit is set only by SW and reset when the BUSY bit resets Flash Programming chosen ORW o This bit is set only by SW and reset when the BUSY bit resets 15 10 3Flash Data register FLASH_DATA Address offset 0x0C For Page Program operations this should be updated by SW to indicate the data to be pro
158. pecified event occurs on that pin The settings in the Capture Control register determine whether the capture function is enabled and whether a capture event happens on the rising edge of the associated pin the falling edge or on both edges H lame Deecrintion LIL INGIIIG Los LE LE N Attribute Reset 31 0 CAPO 31 0 Timer counter capture value R o 7 7 10 CT32Bn External Match register CT32Bn EM nz0 1 Address Offset 0x30 The External Match register provides both control and status of the external match pins CT32Bn PWMCTRLI3 0 If the match outputs are configured as PWM output the function of the external match registers is determined by the PWM rules 7 6 EMC1 1 0 Determines the functionality of CT32Bn_PWM1 00 Do Nothing 01 CT32Bn PWM1 pin is LOW 10 CT32Bn_PWM1 pin is HIGH 11 Toggle CT32Bn_PWM1 EMCO 1 0 Determines the functionality of CT32Bn PWMO 00 Do Nothing 01 CT32Bn_PWMO pin is LOW 10 CT32Bn PWMO pin is HIGH 11 Toggle CT32Bn PWMO 1e Reserved When the TC and MR1 are equal this bit will act according to EMC1 bits and also drive the state of CT32Bn_PWM1 output When the TC and MRO are equal this bit will act according to EMCO bits and also drive the state of CT32Bn PWMO output 7 7 11 CT32Bn PWM Control register CT32Bn PWMCTRL nz0 1 Address Offset 0x34 The PWM Control register is used to configure the match outputs as PWM outputs Each match output can be independently
159. pty 0001 1 8 TX FIFO is used 0010 2 8 TX FIFO is used 1000 8 8 TX FIFO is used Full Other Reserved 0 RX FIFO is not empty 1 RX FIFO is empty Data read from RX FIFO will be zero 0 TX FIFO is not empty 1 TX FIFO is empty TXFIFOFULL TX FIFO full flag 0 TX FIFO is not full 1 TX FIFO is full Write operation to TX FIFO will be ignored RX FIFO threshold flag 0 RXFIFOLV x RXFIFOTH 1 RXFIFOLV RXFIFOTH TX FIFO threshold flag 0 TXFIFOLV TXFIFOTH 1 TXFIFOLV TXFIFOTH 52 Reseved o MANE a 0 Current channel is Left channel 1 Current channel is Right channel Ti ni gt EM 0 No 128 interrupt 1 12S interrupt occurs 13 6 4 I2S Interrupt Enable register I2S IE Address Offset 0x0C Bit Name Reserved RX FIFO threshold interrupt enable bit 0 Disable 1 Enable MG TX FIFO threshold interrupt enable bit 0 Disable 1 Enable RXFIFOFULL RX FIFO full flag 0 RX FIFO is not full 1 RX FIFO is full RXFIFOUDFIEN RX FIFO underflow interrupt enable bit 0 Disable 1 Enable TXFIFOOVFIEN TX FIFO overflow interrupt enable bit 0 Disable 1 Enable Reseved 0000 000000000 13 6 5 125 Raw Interrupt Status register I2S RIS Address Offset 0x10 SONiX TECHNOLOGY CO LTD Page 142 Version 1 4 Na No TRY SN32F100 Series Sv NS N N 32 Bit Cortex M0 Micro Controller 31 8 Reserved 0 No RX FIFO threshold interrupt 1 RX FIFO threshold triggered 0 No TX FIFO thre
160. r count is reset The interrupt indicating that a match occurred is generated after the timer reached the match value PCLK oJ x PA PA E CT16Bn PC 2 0 1 2 0 1 2 0 CT16Bn TC 4 5 6 0 TC Reset Interrupt N The following figure shows a timer configured to stop and generate an interrupt on match The CT16Bn PRE register is set to 2 and the CT16Bn MRx register is set to 6 After the timer reaches the match value the CEN bit in CT16Bn TMRCTRL register is cleared and the interrupt indicating that a match occurred is generated PCLK CT16Bn PC 2 0 1 2 0 CT16Bn TC 4 5 6 CEN bit 1 0 Interrupt SONG TECHNOLOGY CO LTD Page 74 Version 1 4 32 Bit Cortex MO Micro Controller BONER er 6 6 PWM 1 All single edge controlled PWM outputs go LOW at the beginning of each PWM cycle timer is set to zero unless their match value in CT16Bn_MRO 3 registers is equal to zero 2 Each PWM output will go HIGH when its match value is reached If no match occurs the PWM output remains continuously LOW 3 f a match value larger than the PWM cycle length is written to the CT16Bn_MRO 3 registers and the PWM signal is HIGH already then the PWM signal will be cleared on the next start of the next PWM cycle 4 Ifa match register contains the same value as the timer reset value the PWM cycle length then
161. rbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the 12C bus If another device on the bus overrules a logic 1 and pulls the SDA line low arbitration is lost and the I2C block immediately changes from master transmitter to slave receiver The 12C block will continue to output clock pulses on SCL until transmission of the current serial byte is complete Arbitration may also be lost in the master receiver mode Loss of arbitration in this mode can only occur while the DC block is returning a not acknowledge to the bus Arbitration is lost when another device on the bus pulls this signal low Since this can occur only at the end of a serial byte the 12C block generates no further clock pulses SONiX TECHNOLOGY CO LTD Page 111 Version 1 4 I SN y SN32F100 Series S N a X 32 Bit Cortex M0 Micro Controller 11 6 12C SLAVE MODES 11 6 1 SLAVE TRANSMITTER MODE D R SDA E Receiving Address R W 1 Transmission Data ACK_ E Terminate by Master SONiX TECHNOLOGY CO LTD Page 112 Version 1 4 I NI y SN32F100 Series S N A X 32 Bit Cortex M0 Micro Controller 11 7 MONITOR MODE 11 7 1 INTERRUPT All interrupts will occur as normal when the module is in monitor mode This means that the first interrupt will occur when an address match is detected any address received if the MATCH ALL bit is set otherwise an address matching one of the four address registers Subsequent to an address match detection
162. ready flag 0 PLL unlocked 1 PLL locked 5 Reserved EHSRDY External high speed clock ready flag 0 EHS oscillator not ready 1 EHS oscillator ready 3 Reserved ELSRDY External low speed clock ready flag 0 EHS oscillator not ready 1 EHS oscillator ready 1 Reserved 0 IHRC not ready 1 IHRC ready 3 3 4 System Clock Configuration register SYSO_CLKCFG Address Offset 0x0C 317 Reseved ORO System clock switch status iir Set and cleared by HW to indicate which clock source is used as system clock 000 IHRC is used as system clock 001 ILRC is used as system clock 010 EHS X TAL is used as system clock 011 ELS X TAL is used as system clock 100 PLL is used as system clock Other Reserved 3 Reserved HD System clock switch STEE Set and cleared by SW BI 000 IHRC 001 ILRC 010 EHS X TAL 011 ELS X TAL 100 PLL output Other Reserved 3 3 5 AHB Clock Prescale register SYSO_AHBCP Address Offset 0x10 304 Reseved PD S SONG TECHNOLOGY CO LTD Page 52 Version 1 4 N N 9 NX SN32F100 Series Is N A A 32 Bit Cortex M0 Micro Controller AHBPRE 3 0 AHB clock source prescale value 0000 SYSCLK 1 0001 SYSCLK 2 0010 SYSCLK 4 0011 SYSCLK 8 0100 SYSCLK 16 0101 SYSCLK 32 0110 SYSCLK 64 0111 SYSCLK 128 1000 SYSCLK 256 1001 SYSCLK 512 Other Reserved 3 3 6 System Reset Status register SYSO_RSTST Address Offset 0x14 This register
163. register you must write Ox5AFA to WDKEY otherwise behaviour of writing to the register is ignored Reserved 0 Disable 1 Enable When enable the watchdog the WDT TC value is loaded in the watchdog counter WDTINT Watchdog interrupt flag Read 0 Watchdog does not cause an interrupt 1 Watchdog timeout and causes an interrupt Only when WDTIE 1 Write 0 Clear this flag SW shall feed Watchdog before clearing 8 3 2 Watchdog Clock Source register DT CLKSOURCE Address Offset 0x04 Watchdog register key Read as 0 When writing to the register you must write Ox5AFA to WDKEY otherwise behaviour of writing to the register is ignored Reserved CLKSEL 1 0 Selected Watchdog clock source 00 IHRC oscillator 01 HCLK 10 ILRC oscillator 11 ELS X TAL Watchdog interrupt enable 0 Watchdog timeout will cause a chip reset Watchdog reset mode Watchdog counter underflow will reset the MCU and will clear the WDINT flag 1 Watchdog timeout will cause an interrupt Watchdog i Watchdog enable M 8 3 3 Watchdog Timer Constant register WDT TC Address Offset 0x08 The WDT TC register determines the time out value Every time a feed sequence occurs the WDT TOC content is reloaded in to the Watchdog timer It s an 8 bit counter Thus the time out interval is Twor pcik x 128 x 1 Twpr PCLK x 128 x 256 Watchdog overflow time 0 02us x 1 x 128 x 1 0 0625ms x 32 x 128 x 256 2 56us 65536ms Watchdog regi
164. rresponding bit in the CT16Bn IE register is set Bil Name Reserved Interrupt flag for capture channel 0 Bie O No internt on CAPO 1 Interrupt requirements met on CAPO El Interrupt flag for match channel 3 0 No interrupt on match channel 3 1 Interrupt requirements met on match channel 3 a Interrupt flag for match channel 2 0 No interrupt on match channel 2 1 Interrupt requirements met on match channel 2 a re Interrupt flag for match channel 1 0 No interrupt on match channel 1 1 Interrupt requirements met on match channel 1 AMEN Interrupt flag for match channel 0 0 No interrupt on match channel 0 1 Interrupt requirements met on match channel 0 7 7 13 CT32Bn Timer Interrupt Clear register CT32Bn IC n 0 1 Address Offset OX3C Reserved 0 No effect 1 Clear CAPOIF bit 0 No effect 1 Clear MR3IF bit 0 No effect 1 Clear MR2IF bit 0 No effect 1 Clear MR1IF bit 0 No effect 1 Clear MROIF bit SONG TECHNOLOGY CO LTD Page 89 Version 1 4 I NI y SN32F100 Series N N A X 32 Bit Cortex M0 Micro Controller H WATCHDOG TIMER WDT 8 1 OVERVIEW The purpose of the Watchdog is to reset the MCU within a reasonable amount of time if it enters an erroneous state When enabled the Watchdog will generate a system reset or interrupt if the user program fails to feed or reload the Watchdog within a predetermined amount of time The Watchdog consists of a divide by 128 fixed pre scaler and a
165. s The Stack Pointer SP In Thread mode the CONTROL register indicates the stack pointer to use SP R13 Main Stack Pointer MSP or Process Stack Pointer PSP On reset the processor loads the MSP with the value from address 0x00000000 LR R14 The Link Register LR It stores the return information for subroutines function calls and exceptions PC R15 The Program Counter PC It contains the current program address On reset the processor loads the PC with the value of the reset vector at address 0x00000004 The Program Status Register PSR combines Application Program Status Register APSR Interrupt Program Status Register IPSR Execution Program Status Register EPSR These registers are mutually exclusive bit fields in the 32 bit PSR 31 3029 28 27 252423 i PRIMASK The PRIMASK register prevents activation of all exceptions with configurable priority CONTROL The CONTROL register controls the stack used when the processor is in Thread mode SONG TECHNOLOGY CO LTD Page 36 Version 1 4 I NI y SN32F100 Series S N a X 32 Bit Cortex M0 Micro Controller 3 SYSTEM CONTROL 3 1 RESET A system reset is generated when one of the following events occurs A low level on the RST pin external reset Power on reset POR reset LVD reset Watchdog Timer reset WDT reset Software reset SW reset DPDWAKEUP reset when exiting Deep power down mode by DPDWAKEUP pin D OU P a The reset so
166. s Offset 0x0C This register determines the format of the data character that is to be transmitted or received Bit Name Description Attribute Reset E St EC 0 Disable access to Divisor Latches 1 Enable access to Divisor Latches Br Control bit Bon Kd 8 Disable break transmission 1 Enable break transmission Output pin UART TXD is forced to logic 0 PS 1 0 Parity Select bits R W 00 Odd parity Number of 1s in the transmitted character and the attached parity bit will be odd 01 Even Parity Number of 1s in the transmitted character and the attached parity bit will be even 10 Forced 1 stick parity 11 Forced O stick parity E Enable bit Mil ME Disable parity generation and checking 1 Enable parity generation and checking po Stop Bit Select bit EER 0 1 stop bit 1 2 stop bits 1 5 if WLS bits 00 Word Length Select bits Mu 0 00 5 bit character length FUW 01 6 bit character length 10 7 bit character length 11 8 bit character length 12 7 9 UART n Line Status register UARTn LS nz0 1 Address Offset 0x14 SONiX TECHNOLOGY CO LTD Page 127 Version 1 4 N M 1 j SONIX M A Note 1 The break interrupt Bl is associated with the character at the top of the UARTn RB FIFO 2 The framing error FE is associated with the character at the top of the UARTn RB FIFO 3 The parity error PE is associated with the character at the top of the UARTn RB FIFO
167. scale value CT16BOPRE 2 0 DOG MELIA 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 3 4 3 APB Clock Prescale register 1 SYS1 APBCP1 Address Offset 0x08 Note Must reset the corresponding peripheral with SYS1 PRST register after changing the prescale value CLKOUTPRE 3 0 Clock out source prescale value 0000 Clock out source 1 0001 Clock out source 2 0010 Clock out source 4 0011 Clock out source 8 0100 Clock out source 16 0101 Clock out source 32 0110 Clock out source 64 0111 Clock out source 128 1000 Clock out source 256 1001 Clock out source 512 Other Reserved q I2C1PRE 2 0 12C1 clock source prescale value 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved 23 Reserved SONG TECHNOLOGY CO LTD Page 58 Version 1 4 SONA ma reden WDTPRE 2 0 Hy GE SE prescale value R W 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 101 HCLK 32 Other Reserved 1938 Reseved HD SysTick clock source prescale value 17 16 SYSTICKPRE 1 0 00 HCLK 1 RAN 01 HCLK 2 10 HCLK 4 11 HCLK 8 s nono SS Ge Ga aa I2SPRE 2 0 a prescale value 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16 Other Reserved i Reseved I2COPRE 2 0 12C0 clock source prescale value 000 HCLK 1 001 HCLK 2 010 HCLK 4 011 HCLK 8 100 HCLK 16
168. ser ROM Writer can Read Erase Program User ROM SWD can Read Erase Program User ROM FW can Read Erase Program User ROM EEPROM emulation P SWD can NOT Read Erase Program User ROM X FW can Read Erase Program User ROM EEPROM emulation Writer can NOT Read Erase Program User ROM SWD can NOT Read Erase Program User ROM O X X FW can Read Erase Program User ROM EEPROM emulation Writer can NOT Read Erase Program User ROM x SWD can NOT Read Erase Program User ROM FW can NOT Read Erase Program User ROM EEPROM emulation Note User may try to change security level from CS3 to CS0 from CS2 to CSO or from CS1 to CS0 HW shall 1 Mass erase the User ROM first User shall NOT execute this operation in debug mode since the SWD communication may fail during the mass erase procedure 2 Update security level CSI om ar Cm CS3 includes New option byte programming includes Option byte erase Mass Erase SONiX TECHNOLOGY CO LTD Page 159 Version 1 4 I NI y SN32F100 Series N N A X 32 Bit Cortex M0 Micro Controller 15 8 2 PROGRAM FLASH MEMORY The Flash memory can be programmed 32 bits at a time CPU can program the main Flash memory by performing standard word write operations The PG bit in the FLASH CTRL register must be set FMC preliminarily reads the value at the addressed main Flash memory location and checks that it has been erased If not the program operation is sk
169. shold interrupt 1 TX FIFO threshold triggered 0 No RX FIFO underflow 1 RX FIFO underflow RX FIFO is empty and still being read BI Lnd TX FIFO overflow interrupt flag pes 0 No TX FIFO overflow 1 TX FIFO overflow TX FIFO is full and still being written 0 Reseved DD 13 6 6 12S Interrupt Clear register I2S IC Address Offset 0x14 18 ese RA _ RXFIFOTHIC 0 No effect 1 Clear RXFIFOTHIF bit La TXFIFOTHIC 9 No effect 1 Clear TXFIFOTHIF bit RXFIFOUDIC 0 No effect 1 Clear RXFIFOOUDIF bit ER TXFIFOOVIC 0 No effect 1 ee bit 3 0 Reseved 13 6 7 125 RX FIFO register I2S RXFIFO Address Offset 0x18 Caro RXHFOBIO zemren 0 13 6 8 12S TX FIFO register I28 TXFIFO Address Offset 0x1C 310 TXFIFO S1 0 exsetTxFFO un 13 7 CODEC ADC REGISTERS Base Address 0x4006 4000 Note Codec ADC Registers are available only when codec mode is selected by I2SMOD 1 13 7 1 ADC Setting 1 register ADC SET1 Address Offset 0x540 818 Reserved RO SONiX TECHNOLOGY CO LTD Page 143 Version 1 4 NONA dees 7 0 LB H AGC Control Low bound setting for output amplitude of ADC High byte 13 7 2 ADC Setting 2 register ADC SET2 Address Offset 0x550 o Rea EE Low bound setting for output amplitude of ADC Low byte 13 7 3 ADC Setting 3 register ADC SET3 Address Offset 0x560 a Reset HB H nn eee Control High bound setting for output
170. ssed The 12C is a multi master bus and can be controlled by more than one bus master connected to it It is also SMBus 2 0 compatible Depending on the state of the direction bit R W two types of data transfers are possible on the 12C bus gt Data transfer from a master transmitter to a slave receiver The first byte transmitted by the master is the slave address Next follows a number of data bytes The slave returns an acknowledge bit after each received byte gt Data transfer from a slave transmitter to a master receiver The first byte the slave address is transmitted by the master The slave then returns an acknowledge bit Next follows the data bytes transmitted by the slave to the master The master returns an acknowledge bit after all received bytes other than the last byte At the end of the last received byte a not acknowledge is returned The master device generates all of the serial clock pulses and the START and STOP conditions A transfer is ended with a STOP condition or with a Repeated START condition Since a Repeated START condition is also the beginning of the next serial transfer the I2C bus will not be released The 12C interface is byte oriented and has four operating modes Master transmitter mode Master receiver mode Slave transmitter mode Slave receiver mode VVVV 11 2 FEATURES The I2C interface complies with the entire 12C specification supporting the ability to turn power off to the ARM Cortex MO wi
171. ster key Read as 0 When writing to the register you must write Ox5AFA to WDKEY otherwise behaviour of writing to the register is ignored SONiX TECHNOLOGY CO LTD Page 92 Version 1 4 N No wy SN32F100 Series Sv N 32 Bit Cortex M0 Micro Controller 15 9 Reserved 7 0 TC 7 0 Watchdog timer constant reload value TC 7 0 1 0000 0000 Timer constant 1 0000 0001 Timer constant 2 1111 1110 Timer constant 255 1111 1111 Timer constant 256 8 3 4 Watchdog Feed register WDT FEED Address Offset 0x0C WDKEY Watchdog register key l Read as 0 When writing to the register you must write Ox5AFA to WDKEY otherwise behaviour of writing to the register is ignored FV 15 0 Feed value Read as 0x0 0x55AA The watchdog is fed and the WDT TOC value is reloaded in the watchdog counter SONG TECHNOLOGY CO LTD Page 93 Version 1 4 I NI y SN32F100 Series N N a X 32 Bit Cortex M0 Micro Controller d REAL TIME CLOCK RTC 9 1 OVERVIEW The RTC is an independent timer The RTC provides a set of continuously running counters which can be used to provide a clock calendar function with suitable software The counter values can be written to set the current time date of the system 9 2FEATURES Programmable prescale value division factor up to 2 gt 32 bit programmable counter for long term measurement gt The RTC clock source could be any of the following EHS XTAL clock divided by 128 ELS
172. t and Auto SEL data flow is controlled by hardware If Auto SEL function is enabled the SPI s hardware controls the SEL output of the SPI If Auto SEL function is disabled by setting the the SELDIS bit the SELCTRL bit controls the SEL output of the SPI If Auto SEL function is enabled hardware controls the SEL output and the actual value of SEL will be copied in the SELCTRL Control bit of the SPI As long as Auto SEL is enabled the value of the SELCTRL Control bit is read only for software SONiX TECHNOLOGY CO LTD Page 104 Version 1 4 Ns y 2FI j SONIX BEN Seien 10 6 SSP REGISTERS Base Address 0x4001 C000 SSPO 0x4005 8000 SSP1 10 6 1 SSP n Control register 0 SSPn CTRLO n 0 1 Address Offset 0x00 Note gt 1 Must reset SSP FSM with FRESET 1 0 after changing any configuration of SSP when SSPEN 1 gt 2 HW will switch VO configurations refer to FORMAT bit directly when SSPEN 1 Bit Nam Reserved SELCTRL Source for SEL pin For SPI mode only 0 SEL pin is low level 1 SEL pin is high level ME iN Auto SEL disable bit For SPI mode only 0 Enable Auto SEL flow control 1 Disable Auto SEL flow control XFIFOTH 2 RX FIFO Threshold level 19 08 9THIEAI 0 RX FIFO threshold level 0 1 RX FIFO threshold level 1 n RX FIFO threshold level n TXFIFOTH 2 0 TX FIFO Threshold level 0 TX FIFO threshold level 0 1 TX FIFO threshold level 1 n TX FIFO threshold level 2
173. t detected 1 Alarm detected Second interrupt flag This bit is set by HW when SEC_CNT SEC_CNTV An interrupt is generated if SECIE 1 0 Second flag condition not met 1 Second flag condition met 9 5 5 RTC Interrupt Clear register RTC_IC Address offset 0x10 Reseved bn 9m Bif N 1 Clear OVFIF bit um ie A E 1 Clear ALMIF bit 0 No effect Sc teem lw In 9 5 6 RTC Second Counter Reload Value register RTC SECCNTV Address offset 0x14 Reset value 0x8000 Bi Name Descriptic Attribute Reset 3120 Reseved RTC second counter reload value SEH Update this register will reset RTC SECCNT and RTC ALMCNT HM Ge registers The zero value is not recommended and will be replaced with default value 0x8000 by HW 9 5 7 RTC Second Count register RTC SECCNT Address offset 0x18 The RTC core has one 32 bit programmable counter and this register keeps the current counting value of this counter SECCNTI31 0 RTC second counter 810 SECONT StO The current value of the RTC counter 9 5 8 RTC Alarm Counter Reload Value register RTC ALMCNTV Address offset 0x1C Reset value OXFFFFFFFF ALMCNTV 31 0 RTC alarm counter reload value R W OxFFFFFFFF Update this register will reset ALMCNT The zero value is not recommended and will be replaced with default value OXFFFFFFFF by HW SONG TECHNOLOGY CO LTD Page 98 Version 1 4 N No VAY SN32F100 Series SO N A X 32 Bit Cortex MO M
174. te Optional Save data to be retained during Deep power down to the DATA bits in Backup registers Write 1 to DPDEN bit in PMU CTRL register to enable Deep power down mode Time spent between step 1 and step 5 shall longer than 20 us Execute ARM Cortex MO WFI instruction ARON After step 5 the PMU turns off the on chip voltage regulator and waits for a wake up signal from the DPDWAKEUP pin 4 3 3 2 Exiting Deep power down mode Follow these steps to wake up the chip from Deep power down mode 1 DPDWAKEUP pin transition from HIGH to LOW The PMU will turn on the on chip voltage regulator When the core voltage reaches the power on reset POR Trigger point a system reset will be triggered and the chip reboots All registers except the PMU BKPO to PMU BKP 15 and PMU_CTRL will be reset 2 Once the chip has rebooted read DPDEN bit in PMU CTRL register to verify that the reset was caused by a wake up event from Deep power down and was not a cold reset Clear the DPDEN bit in PMU CTRL register Optional Read the stored data in the backup registers Setup the PMU for the next Deep power down cycle Qv A co 4 4WAKEUP INTERRUPT System will exit Deep sleep mode when GPIO indicates a GPIO interrupt to the ARM core The all GPIO port pins are served as wakeup pins The user must program the registers for each pin to set the appropriate edge polarity for the corresponding wakeup event Only edge sensitive is supported to wakeup MCU
175. ternal reference switches automatically 00 Internal 1 4 Vdd and enable internal reference voltage generator 01 Internal 1 2 Vdd and enable internal reference voltage generator 10 11 Internal 3 4 Vdd and enable internal reference voltage generator CMCH 4 0 Comparator negative input pin control bit CMPEN must be 1 00000 Comparator negative input pin is P2 0 00001 Comparator negative input pin is P2 1 00010 Comparator negative input pin is P2 2 00011 Comparator negative input pin is P2 3 00100 Comparator negative input pin is P2 4 00101 Comparator negative input pin is P2 5 00110 Comparator negative input pin is P2 6 00111 Comparator negative input pin is P2 7 01000 Comparator negative input pin is P2 8 01001 Comparator negative input pin is P2 9 01010 Comparator negative input pin is P2 10 01011 Comparator negative input pin is P2 11 01100 Comparator negative input pin is P2 12 01101 Comparator negative input pin is P2 13 01110 Comparator negative input pin is P2 14 01111 Comparator negative input pin is P2 15 10000 Comparator negative input pin is P3 0 10001 Comparator negative input pin is P3 1 10010 Comparator negative input pin is P3 2 10011 Comparator negative input pin is P3 3 10100 Comparator negative input pin is P3 4 10101 Comparator negative input pin is P3 5 10110 Comparator negative input pin is P3 6 10111 Comparator negative input pin is P3 7 11000
176. the PWM output will be reset to LOW on the next clock tick Therefore the PWM output will always consist of a one clock tick wide positive pulse with a period determined by the PWM cycle length 5 If a match register is set to zero then the PWM output will go to HIGH the first time the timer goes back to zero and will stay HIGH continuously iius CT16Bn_MRO 100 PWMO LL CT16Bn_MRO 25 EES CT16Bn MR0 60 CT16Bn TC 0 25 60 100 TC resets Note When the match outputs are selected to perform as PWM outputs the timer reset MRnRST and timer stop MRnSTOP bits in CT16Bn_MCTRL register must be set to zero except for the match register setting the PWM cycle length For this register set the MRnR bit to one to enable the timer reset when the timer value matches the value of the corresponding match register SONG TECHNOLOGY CO LTD Page 75 Version 1 4 IN ow 2F1 j SO A N 32 Bit on den 6 7CT16Bn REGISTERS Base Address 0x4000 0000 CT16B0 0x4000 2000 CT16B1 6 7 1 CT16Bn Timer Control register CT16Bn TMRCTRL nz0 1 Address Offset 0x00 Note CEN bit shall be set at last 312 Reseved O A CRST Counter Reset R W 0 Disable counter reset 1 Timer Counter is synchronously reset on the next positive edge of PCLK This is cleared by HW when the counter reset operation finishes IEEE Counter Enable R W 0 Disable Counter 1 Enable Timer Counter for counting 6 7
177. thout interfering with other devices on the same I2C bus gt Standard I2C compliant bus interfaces may be configured as Master or Slave gt DC Master features m Clock generation W Start and Stop generation gt 12C Slave features m Programmable I2C Address detection m Optional recognition of up to four distinct slave addresses m Stop bit detection gt Supports different communication speeds m Standard Speed up to 100KHz m Fast Speed up to 400 KHz Arbitration is handled between simultaneously transmitting masters without corruption of serial data on the bus v Programmable clock allows adjustment of 12C transfer rates Data transfer is bidirectional between masters and slaves Serial clock synchronization allows devices with different bit rates to communicate via one serial bus VV ON V Serial clock synchronization is used as a handshake mechanism to suspend and resume serial transfer SONiX TECHNOLOGY CO LTD Page 109 Version 1 4 Y SS 9 NX SN32FI00 Series px N E A 32 Bit Cortex M0 Micro Controller gt Monitor mode allows observing all I2C bus traffic regardless of slave address gt 2C bus can be used for test and diagnostic purposes Generation and detection of 7 bit 10 bit addressing and General Call 11 3 PIN DESCRIPTION Type Description SCLn VO 12C Serial clock Output with Open drain Input depends on GPIOn CFG SDAn 12C Serial data Output with Open drain Input depends on GPlOn CFG 11 4 WAVE CH
178. ully and supply to system clock Program executing Power on sequence is finished and program executes from 0x0 Watchdog timer application note is as following Before clearing watchdog timer check I O status and check RAM contents can improve system error Don t clear watchdog timer in interrupt vector and interrupt service routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Note Please refer to the WATCHDOG TIMER about watchdog timer detail information 3 1 3 BROWN OUT RESET 3 1 3 1 BROWN OUT DESCRIPTION The brown out reset is a power dropping condition The power drops from normal voltage to low voltage by external factors e g EFT interference or external loading changed The brown out reset would make the system not work well or executing program error VDD System Work Well Area Brown Out Reset Diagram The power dropping might through the voltage range that s the system dead band The dead band means the power range can t offer the system minimum operation power requirement The above diagram is a typical brown out reset diagram There is a serious noise under the VDD and VDD voltage drops very deep There is a dotted line to separate the system working area The above area is the system work well area The below area is the system work error area called
179. urce WAKEUP button Trigger source to wake up from deep power down mode Y1 External high speed X tal Y2 External low speed 32 768KHz X tal Y3 External high speed X tal for Audio JP18 JP15 Writer connector JP20 Short to force MCU stay in Boot loader JP21 JP3 JP4 I2C0 I2C1 connector JP7 JP12 SPIO SPI1 connector JP8 JP9 UARTO UART1 connector R1 SCLO pull up resistor R3 SDAO pull up resistor R2 SCL1 pull up resistor R4 SDA1 pull up resistor R5 UTXDO or UTXD1 pull up resistor R6 URXDO or URXD1 pull up resistor JP47 JP48 JP49 JP34 JP29 JP42 JP43 R30 MIC BIAS from external bias adjust SN LINK connector 12S connector Codec ADC power connector Codec DAC power connector Codec Driver power connector Headset connector Microphone connector MIC N connector MIC P connector SONiX TECHNOLOGY CO LTD Page 166 SN32F100 Series 32 Bit Cortex MO Micro Controller Version 1 4 NONA Na 17 2 2 SN32F100 Start Kit V1 1 V1 2 insbirrya KINE JP46 Mini USB connector for power supply S1 USB power on off JP53 VDD power source is 3 3V from board Writer or external power Open if External power source is used U4 SN32F109F real chip D9 Power LED RESET button External reset trigger source WAKEUP button Trigger source to wake up from deep power down mode Y1 External high speed X tal SONiX TECHNOLOGY CO LTD Page 167 Version 1 4 d 000000000000000000
180. urce can be identified by checking the reset flags in System Reset Status register SYSO_RSTST These sources act on the RST pin and it is always kept low during the delay phase The RESET service routine vector is fixed at address 0x00000004 in the memory map For more details refer to Interrupt and Exception Vectors Finishing any reset sequence needs some time The system provides complete procedures to make the power on reset successful For different oscillator types the reset time is different That causes the VDD rise rate and start up time of different oscillator is not fixed RC type oscillator s start up time is very short but the crystal type is longer Under client terminal application users have to take care of the power on reset time for the master terminal requirement The reset timing diagram is as following VDD LVD Detect Level Power ss SUE VDD External Reset ss External Reset External Reset High Detect Low Detect Watchdog Overflow Vi Watchdog Normal Run i Watchdog Reset Watchdog Stop E System Normal Run i f i System Status system Stop PowerOn External Watchdog Delay Time Reset Delay Reset Delay Time Time 3 1 1 POWER ON RESET POR The power on reset depends on LVD operation for most power up situations The power supplying to system is a rising curve and needs some time to achieve the normal volt
181. ve data stream and set the divisor latch registers UARTn DLM and UARTn DLL accordingly Auto baud function is started by setting the START bit in UARTn ABCTRL register and can be stopped by clearing the START bit The START bit will clear once auto baud has finished and reading the bit will return the status of auto baud pending finished When auto baud function is started FIFO will be cleared not available to write the TX FIFO and the transmitter will stop transmitting until auto baud function finishes or be stopped Two auto baud measuring modes are available which can be selected by the MODE bit in UARTn ABCTRL register In Mode 0 the baud rate is measured on two subsequent falling edges of the UART RX pin the falling edge of the start bit and the falling edge of the least significant bit In Mode 1 the baud rate is measured between the falling edge and the subsequent rising edge of the UART RX pin the length of the start bit The AUTORESTART bit in UARTn ABCTRL register can be used to automatically restart baud rate measurement if a timeout occurs the rate measurement counter overflows If this bit is set the rate measurement will restart at the next falling edge of the URXD pin The auto baud function can generate two interrupts e The ABTOINT interrupt in UARTn II register will get set if the interrupt is enabled ABTOIE bit in UARTn IE register is set and the auto baud rate measurement counter overflows The ABEOINT interrupt i
182. wo requests then the fractional divider output is undefined If DIVADDVAL is zero then the fractional divider is disabled and the clock will not be divided UART can operate with or without using the Fractional Divider The desired baud rate can be achieved using several different Fractional Divider settings The following algorithm illustrates one way of finding a set of DLM DLL MULVAL and DIVADDVAL values Such set of parameters yields a baud rate with a relative error of less than 1 196 from the desired one The following example illustrates selecting the DIVADDVAL MULVAL DLM and DLL to generate BR 115200 when UARTn PCLK 12 MHz and Oversampling 16 UARTn PCLK UARTBAUDRATE Oversampling x 256 x DLM DLL x 1 DIVADDVAL MULVAL 12000000 115200 16 x 256 x DLM DLL x 1 DIVADDVAL MULVAL 256 x DLM DLL x 1 DIVADDVAL MULVAL 6 51 Since the value of MULVAL and DIVADDVAL should comply to the following conditions 1 1 S MULVAL s 15 2 0 lt DIVADDVAL s 14 3 DIVADDVAL MULVAL Thus the suggested UART settings would be DLM 0 DLL 4 DIVADDVAL 5 and MULVAL 8 The baud rate generated is 115384 and has a relative error of 0 1696 from the originally specified 115200 12 6 AUTO BAUD FLOW 12 6 1 AUTO BAUD The UART auto baud function can be used to measure the incoming baud rate based on the AT protocol Hayes commana If enabled the auto baud feature will measure the bit time of the recei
183. x 32 Bit Cortex M0 Micro Controller 1 5 PIN DESCRIPTIONS VDD VSS AVDD DAC AVSS DAC AVDD_ADC AVSS ADC AVDD DRV AVSS DRV VCOM DAC VMID DAC VMID ADC MIC BIAS P0 0 URXDO PO 1 UTXDO Power supply input pins for digital circuit Power supply input pins for Sigma delta DAC Power supply input pins for Sigma delta ADC Power supply input pins for Sigma delta DAC Driver SONG TECHNOLOGY CO LTD Page 20 Version 1 4 P0 3 SDAO P0 4 SCK0 PGDCLK PO 5 SELO PGDIN P0 6 MISO0 OTPCLK PO Z MOSIO VR DOU T PO 2 SCLO P0 2 General purpose digital input output pin N N o WAY SN32F100 Seri d E N 32 Bit ini Sinn e VR DOUT Recognition code verify data checksum ID output in programming mode PO uu SONG TECHNOLOGY CO LTD Page 21 Version 1 4 P1 0 AUXTALOUT O Q N 9 NX SN32F100 Series N Na 32 Bit Cortex M0 Micro Controller SONG TECHNOLOGY CO LTD Page 22 Version 1 4 EN EES SONIN SN32F100 Series N Na 32 Bit Cortex M0 Micro Controller PWMO PWM1 SONG TECHNOLOGY CO LTD Page 23 Version 1 4 O Q N 9 NX SN32F100 Series N NB B A 32 Bit Cortex M0 Micro Controller P3 12 URXD1 CT16B VO P3 12 General purpose digital input output pin 0 CAPO P3 7 CM23 CT32B1 PWM1 P3 8 CMO P3 9 CT16BO PWMO P3 10 CT32B0 PWM 0 P3 11 CT32B1 PWM 0 SDA1 DC data input output High current sink only during DC Fast mode Plus CT32B1 CAPO Capture input O for CT32B1 P3 13
184. x M0 Micro Controller 10 4 2 SSI For device configured as a master in this mode SCK and CS are forced LOW and the transmit data line DATA is in 3 state mode whenever the SSP is idle Once the bottom entry of the transmit FIFO contains data CS is pulsed HIGH for one SCK period The value to be transmitted is also transferred from the transmit FIFO to the serial shift register of the shifted out on the DATA pin Likewise the MSB of the received data is shifted onto the DATA pin by the off chip serial slave device Both the SSP and the off chip serial slave device then clock each data bit into their serial shifter on the falling edge of each SCK The received data is transferred from the serial shifter to the receive FIFO on the first rising edge of SCK after the LSB has been latched 10 4 3 COMMUNICATION FLOW 10 4 3 1 SINGLE FRAME SPI A TI E 34 CS 1 DATA MSB LSB SONiX TECHNOLOGY CO LTD Page 103 Version 1 4 N No wy SN32F100 Series Sv NS N AN 32 Bit Cortex M0 Micro Controller 10 4 3 2 MULTIFRAME e CPOL 0 CPHA 1 CPOL 1 CPHA 0 SH CPOL 1 CPHA 1 CPOL 0 CPHA 0 FO FO FO FO Fl Fl Fl Fl para mi BEE FI m TI CS FO FO FO FO Fl Fl Fl Fl TE jme Te 10 5 Auto SEL Auto CS The Auto SEL function is enabled by defaul

SN32F100 Spec.

Contents

Download Pdf Manuals

Related Search

Related Contents