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Automotive 8-bit MCU, with up to 8 Kbyte Flash, data EEPROM, 10

1. Address Block Register label Register name oo 0x00 5300 TIM5_CR1 TIM5 control register 1 0x00 0x00 5301 TIM5_CR2 TIM5 control register 2 0x00 0x00 5302 TIM5 SMCR TIM5 slave mode control register 0x00 0x00 5303 TIM5 IER TIMS interrupt enable register 0x00 0x00 5304 TIM5 SR1 TIMS status register 1 0x00 0x00 5305 TIM5 SR2 TIMS status register 2 0x00 0x00 5306 TIM5 EGR TIM5 event generation register 0x00 0x00 5307 TIM5 CCMR1 TIM5 capture compare mode register 1 0x00 0x00 5308 TIM5 CCMR2 TIM5 capture compare mode register 2 0x00 0x00 5309 TIM5 CCMR3 TIM5 capture compare mode register 3 0x00 0x00 530A TIM5 CCER1 TIM5 capture compare enable register 1 0x00 0x00 530B TIM5 TIM5 CCER2 TIM5 capture compare enable register 2 0x00 00 530C0x TIM5 CNTRH TIM5 counter high 0x00 0x00 530D TIM5_CNTRL TIM5 counter low 0x00 0x00 530E TIM5 PSCR TIM5 prescaler register 0x00 0x00 530F TIM5 ARRH TIM5 auto reload register high OxFF 0x00 5310 TIM5 ARRL TIM5 auto reload register low OxFF 0x00 5311 TIM5 CCR1H TIM5 capture compare register 1 high 0x00 0x00 5312 TIM5 CCR1L TIM5 capture compare register 1 low 0x00 0x00 5313 TIM5 CCR2H TIM5 capture compare reg 2 high 0x00 0x00 5314 TIM5 CCR2L TIM5 capture compare register 2 low 0x00 0x00 5315 TIM5_CCR3H TIM5 capture compare register 3 high 0x00 0x00 5316 TIM5 CCR3L TIM5 capture compare register 3 low 0x00 pros EE
2. Vpp STM8A me Vr VAN Rain AIN p 0 6 V Ow YAN conversion EE ud UA Vt Can Z 06 v On 1 pA LL Cape MSv38372V1 1 Legend Ran external resistance CAN capacitors Csamp internal sample and hold capacitor d 88 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics 9 3 11 g EMC characteristics Susceptibility tests are performed on a sample basis during product characterization Functional EMS electromagnetic susceptibility While executing a simple application toggling 2 LEDs through I O ports the product is stressed by two electromagnetic events until a failure occurs indicated by the LEDs e FESD Functional electrostatic discharge positive and negative is applied on all pins of the device until a functional disturbance occurs This test conforms with the IEC 61000 4 2 standard e FTB A burst of fast transient voltage positive and negative is applied to Vpp and Vss through a 100 pF capacitor until a functional disturbance occurs This test conforms with the IEC 61000 4 4 standard A device reset allows normal operations to be resumed The test results are given in the table below based on the EMS levels and classes defined in application note AN1709 Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment
3. STM8AF6213 23 23A 26 Electrical characteristics Table 55 ADC accuracy with RAIN lt 10 KO Vpp 5V Symbol Parameter Conditions Typ Max Unit fapc 2 MHz 1 6 3 5 Ex Total unadjusted error fApc 4 MHz 2 2 4 fapc 6 MHz 2 4 4 5 fapc 2 MHz 1 1 2 5 IE Offset error fApc 4 MHz 1 5 3 fapc 6 MHz 1 8 3 fApc 2 MHz 1 5 3 Es Gain error fApc 4 MHz 2 1 3 LSB fapc 6 MHz 2 2 4 fApc 2 MHz 0 7 1 5 Epl Differential linearity error fapc 4 MHz 0 7 1 5 fapc 6 MHz 0 7 1 5 fapc 2 MHz 0 6 1 5 JE Integral linearity error fapc 4 MHz 0 8 2 fApc 6 MHz 0 8 2 Ly Max value is based on characterization not tested in production 2 ADC accuracy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for lj piv and ZliNyPin in the VO port pin characteristics section does not affect the ADC accuracy Table 56 ADC accuracy with RAIN 10 kO Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit fApc 2 MHz 1 6 3 5 Er Total unadjusted error TADC 4 MHz 1 9 4 fApc 2 MH
4. 1 Thermal resistances are based on JEDEC JESD51 2 with 4 layer PCB in a natural convection environment Reference document JESD51 2 integrated circuits thermal test method environment conditions natural convection still air Available from www jedec org Selecting the product temperature range When ordering the microcontroller the temperature range is specified in the order code see Section 11 Ordering information The following example shows how to calculate the temperature range needed for a given application g DoclD025118 Rev 5 STM8AF6213 23 23A 26 Package information Assuming the following application conditions Maximum ambient temperature Tamax 75 C measured according to JESD51 2 IpDmax 8 MA Vpp 5 V Maximum 20 I Os used at the same time in output at low level with loL 8 MA Vo 0 4 V Pintmax 8 MA x 5 V 400 mW Piomax 20 x 8 mA x 0 4 V 64 mW This gives PINTmax 400 mW and Pjomax 64 mW Ppmax 400 mW 64 mW Thus Ppmax 464 mW Using the values obtained in Table 63 Thermal characteristics on page 98 T max is calculated as follows For LQFP32 60 C W TJmax 75 C 60 C W x464 mW 75 C 27 8 C 102 8 C This is within the range of the suffix C version parts 40 lt Ty lt 125 C Parts must be ordered at least with the temperature range suffix C DoclD025118 Rev 5 99 106 g Ordering information STM8AF621 3 23 23A 26 11 Order
5. 24 106 DocID025118 Rev 5 Ly STM8AF6213 23 23A 26 Pinout and pin description Table 6 STM8AF6213 STM8AF6223 TSSOP20 pin description continued Input Output a B lg Main Default Alternate O o 2 k function D Pin name Type e s c ko function alternate 2 S515195 198 afterreset function after remap F 8 35 5 g 2 0 amp option bit amp 9 9 k SPI master 10 PAS TIMS_CHS Wo x x x lus oal x x Portas Timer 5 stave select SPI NSS channel 3 AFR1 Timer 1 11 Esc cep io NG Kl Sa To Port B5 I2C data break input ies AFR4 ADC PB4 12C SCL 3 external 12 ADC ETR vo X X o1 T Port B4 I2C clock Selia AFR4 Top level interrupt PC3 ae AFR3 13 TIM1 CHSTLIL VO x X X HS O3 X X PotC3 nameg Timer 4 TIM1_CH1N inverted channel 1 AFR7 Timer 1 oe PC4 TIM1 CH4 channel 4 AFR2 Time 14 CLK CCO AIN2 L UO X x Xx Hs 03 x X PortC4 configurabl r 1 inverted TIM1 CH2N e clock autour channel 2 P AFR7 Timer 5 15 en vo X X x Hs 03 x X PortC5 SPlcock channel 1 AFRO PC6 SPI MOSI PI master Timer 1 16 TIM1 GH1 vo X xX X HS OS X X PotC6 slave in channel 1 AFRO PC7 SPI MISO SPI master meri 17 TM GH2 vo X xX X HS OS X x Portc7 aan channel E 2 AFRO 18 PD1 SWIM vo Xx xiHsS O4 X X Potpi SWM data interface Ly DoclD025118 Rev 5 25
6. 43 Interrupt vector mapping ass ks sk RR ke ee ek ea ee 45 Option bytes is bag SESSE DoE RERURE RARUS SS SERE ED DE DEK 47 8 1 Option byte description xa kaa eee 48 8 2 STM8AF6213 23 23A 26 alternate function remapping bits 49 Electrical characteristics cece RR RR RR RR RR RA RR AR ee 53 9 1 Parameter conditions 22 dx erm dai eu be ac ados a i dra de dedos 53 9 1 1 Minimum and maximum values eee 53 9 1 2 Typical values EE N NG PNG BA eee ed ped dE 53 9 1 3 Typical GUNES cus ei RTE ETTR KTR in Neha Sen Ta ad 53 9 1 4 Loading capacitor R R R cect 53 9 1 5 Pin input voltage xK R R SEE ENRE ee RR m 54 9 2 Absolute maximum ratings 0000 eee eee 54 9 3 Operating conditions sk KARA DADAAN HA deep apad tra 56 9 3 1 VCAP external capacitor 000002 EE EE ee eee 58 9 3 2 Supply current characteristics llle 58 9 3 3 External clock sources and timing characteristics 67 9 3 4 Internal clock sources and timing characteristics 69 9 3 5 Memory characteristics 000 eee 70 9 3 6 VO port pin characteristics EE SS eee ee 72 9 3 7 Reset pin characteristics EE EE EE ee eee eee 79 9 3 8 SPI serial peripheral interface cee eee eee 81 9 3 9 I2C interface characteristics 0 ccc eee ee sees 84 9 3 10 10 bit ADC characteristics l llle 86 DoclD025118 Rev 5 3 106 Contents STM8AF6213
7. d 66 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics 9 3 3 External clock sources and timing characteristics HSE user external clock Subject to general operating conditions for Vpp and Ta Table 39 HSE user external clock characteristics Symbol Parameter Conditions Min Typ Max Unit User external clock source THSE ex frequency d 7 i MHz OSCIN input pin high level Vasant ae papin 07xVpp Vpop 0 3V V OSCIN input pin low level Vusg voltage dod Vss 03xVpp OSCIN input leakage ILEAK HSE current P g Vss lt VIN lt Vpp 1 1 UA 1 Data based on characterization results not tested in production Figure 17 HSE external clock source External clock source JUUL MS36489V1 d DoclD025118 Rev 5 67 106 Electrical characteristics STM8AF6213 23 23A 26 HSE crystal ceramic resonator oscillator The HSE clock can be supplied with a 1 to 16 MHz crystal ceramic resonator oscillator All the information given in this paragraph is based on characterization results with specified typical external components In the application the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time Refer to the crystal resonator manufacturer for more details frequency package accuracy Table 40 HSE oscillator c
8. Table 59 ESD absolute maximum ratings Maximum Symbol Ratings Conditions Class value Unit V Electrostatic discharge voltage TA 25 C conforming to 3A 4000 ESD HBM Human body model JESD22 A114 V Electrostatic discharge voltage Taz 25 C conforming to 3 500 V ESD CDM Charge device model JESD22 C101 V Electrostatic discharge voltage Taz 25 C conforming to B 200 ESD MM Machine model JESD22 A115 1 Data based on characterization results not tested in production d DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics d Static latch up Two complementary static tests are required on six parts to assess the latch up performance e A Supply overvoltage applied to each power supply pin e A current injection applied to each input output and configurable lO pin are performed on each sample This test conforms to the EIA JESD 78 IC latch up standard For more details refer to the application note AN1181 Table 60 Electrical sensitivities Symbol Parameter Conditions Class Ta 25 C Ta 85 C LU Static latch up class A Ta 125 C Ta 150 C 1 Class description A Class is an STMicroelectronics internal specification All its limits are higher than the JEDEC specifications that means when a device belongs to class A it exceeds the JEDEC standard B class strictly covers all the JEDEC criteria international
9. i in 1 page steps Low density Flash program memory up to 8Kbyte Flash program memory area Write access possible for IAP MS38344V1 Read out protection ROP The read out protection blocks reading and writing the Flash program memory and data EEPROM memory in ICP mode and debug mode Once the read out protection is activated any attempt to toggle its status triggers a global erase of the program and data memory Even if no protection can be considered as totally unbreakable the feature provides a very high level of protection for a general purpose microcontroller DoclD025118 Rev 5 15 106 Product overview STM8AF6213 23 23A 26 4 5 4 5 1 16 106 Clock controller The clock controller distributes the system clock fyASTER coming from different oscillators to the core and the peripherals It also manages clock gating for low power modes and ensures clock robustness Features e Clock prescaler to get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler e Safe clock switching Clock sources can be changed safely on the fly in Run mode through a configuration register The clock signal is not switched until the new clock source is ready The design guarantees glitch free switching e Clock management To reduce power consumption the clock controller can stop the clock to the core indi
10. k y life augmented STM8AF6213 STM8AF6223 STM8AF6223A STM8AF6226 Automotive 8 bit MCU with up to 8 Kbyte Flash data EEPROM 10 bit ADC timers LIN SPI FC 3 to 5 5 V Features June 2015 Core Max fepy 16 MHz Advanced STM8A core with Harvard architecture and 3 stage pipeline Extended instruction set Memories Program memory 4 to 8 Kbyte Flash program data retention 20 years at 55 C after 1 kcycle Data memory 640 byte true data EEPROM endurance 300 kcycle RAM 1 Kbyte Clock management Low power crystal resonator oscillator with external clock input Internal user trimmable 16 MHz RC and low power 128 kHz RC oscillators Clock security system with clock monitor Reset and supply management Wait auto wakeup Halt low power modes with user definable clock gating Low consumption power on and power down reset Interrupt management Nested interrupt controller with 32 interrupts Up to 28 external interrupts on 7 vectors Timers Advanced control timer 16 bit 4 CAPCOM channels 3 complementary outputs dead time insertion and flexible synchronization 16 bit general purpose timer with 3 CAPCOM channels each IC OC PWM 8 bit AR basic timer with 8 bit prescaler Auto wakeup timer Window and independent watchdog timers Datasheet production data e LQFP32 7x7 mm TSSOP20 6 4x4 4 mm VOs Up to
11. C_SCL T PB4 AINS HS AIN2 IAIN1 AINO HS S Z s TIM1_CH2N TIM1 CHIN TIM1_ETR TIM1 CH3N TIM1_BKIN I2C_SDA T ADC ETR PC7 HS SPI MISO TIM1 CH2 PC6 HS SPI MOSI TIM1 CH1 PC5 HS SPI SCK TIM5 CH1 PCA HS TIM1 CH4 CLK CCO AIN2 TIM1 CH2N PC3 HS TIM1 CH3 TLI TIM1_CH1N PC2 HS TIM1 CH2 TIM1 CH3N PC1 HS TIM1 CH1 LINUART CK TIM1 CH2N PE5 SPI NSS TIM1 CH1N MS38347V1 2 T true open drain P buffer and protection diode to Vpp not implemented 3 alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Table 8 STM8AF6226 LQFP32 pin description Input Output B Ble Main Default ee a Pin name Type 2 5 EIl function alternate o g2 7 s 8 2 after reset function after remap a o 35 E c amp On option bit 2 9 0 d T 1 NRST VO X Reset 2 PAJ OSCND vo X X X O1 x x Portat Resonator crystal in 3 PA2OSCOUT vo X X X loul x x Poraz Resonator lt crystal out d DoclD025118 Rev 5 29 106 Pinout and pin description STM8AF6213 23 23A 26 Table 8 STM8AF6226 LQFP32 pin description continued Input Output S Ble Main Default ARUM am la Pin name Type 2 5 E fic function alternate o S158191 2 A
12. l 30 33 ee 64 byte terase Erase time for 1 block 64 byte 3 0 33 70 106 DoclD025118 Rev 5 ky STM8AF6213 23 23A 26 Electrical characteristics Table 45 Flash program memory Symbol Parameter Condition Min Max Unit Twe Temperature for writing and erasing 40 150 C Flash program memory endurance ADES Nwe erase write cycles TA RAD 1900 cycles TA 25 C 40 tRET Data retention time years Ta 55 C 20 1 The physical granularity of the memory is 4 byte so cycling is performed on 4 byte even when a write erase operation addresses a single byte Table 46 Data memory Symbol Parameter Condition Min Max Unit Twe Temperature for writing and erasing 40 150 C Data memory endurance TA725 C 300 k 3 Nwe 5 cycles erase write cycles Ta 40 C to 125 C 100 KO E r Ta 25 C 406 tRET ata retention time years TA 55 C 2000 1 The physical granularity of the memory is 4 byte so cycling is performed on 4 byte even when a write erase operation addresses a single byte 2 More information on the relationship between data retention time and number of write erase cycles is available in a separate technical document 3 Retention time for 256B of data memory after up to 1000 cycles at 125 C d DoclD025118 Rev 5 71 106 Electrical characteristics STM8AF6213 23 23A 26 9 3 6 VO port pin characteristi
13. lt Vss For true open drain pads there is no positive injection current and the corresponding Vin maximum must always be respected DoclD025118 Rev 5 IiNJ PIN must never be exceeded This is implicitly insured if Vin maximum is respected If Vy maximum d STM8AF6213 23 23A 26 Electrical characteristics d Table 23 Current characteristics Symbol Ratings Max Unit lvpp Total current into Vpp power lines source 100 lyss Total current out of Vss ground lines sink 80 Output current sunk by any I O and control pin 20 lio Output current source by any I Os and control pin 20 NIN 4 Injected current on RST pin 4 Injected current on OSCIN pin 4 Injected current on any other pin 4 FinyTON e Total injected current sum of all I O and control pins 20 Data based on characterization results not tested in production 2 All power Vpp Vppio VppA and ground Vss Vssio Vssa pins must always be connected to the external supply 3 lingcpiny must never be exceeded This is implicitly insured if Vjy maximum is respected If Vin maximum cannot be respected the injection current must be limited externally to the liy py value A positive injection is induced by Vig Vpp while a negative injection is induced by VjysVss For true open drain pads there is no positive injection current and the corresponding VIN maximum must always be respected 4 ADC accu
14. 0 3 V Vol NnRsT NRST output low level voltage 2 0 5 Reunrst NRST pull up resistor 30 55 80 kQ tep Rst NRST input filtered pulse 75 NRST Input not filtered pulse ns INFP NRST duration 9 s 500 7 topiNRsT NRST output pulse 9 20 US 1 Data based on characterization results not tested in production 2 The Rpy pull up equivalent resistor is based on a resistive transistor 3 Data guaranteed by design not tested in production Figure 32 Typical NRST Vj and Vj vs Vpp 4 temperatures wy Mi d DoclD025118 Rev 5 79 106 Electrical characteristics STM8AF6213 23 23A 26 80 106 Figure 33 Typical NRST pull up resistance vs Vpp 4 temperatures NRESET pull up estre kn 25 3 3 5 4 45 5 5 5 6 Veg MI Figure 34 Typical NRST pull up current vs Vpp 4 temperatures NRESET Pull Up currant 3 Val The reset network shown in Figure 35 protects the device against parasitic resets The user must ensure that the level on the NRST pin can go below Vi sr max see Table 51 NRST pin characteristics otherwise the reset is not taken into account internally For power consumption sensitive applications the external reset capacitor value can be reduced to limit the charge discharge current If NRST signal is used to reset external circuitry attention must be taken to the charge discharge time of the external capacitor to ful
15. 0x00 A000 0x02 7FFF MS38348V1 d 34 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Memory and register map Table 9 Memory model for the devices covered in this datasheet Flash program Flash program 3 RAM end Stack roll over memory end RAM size memory size address address address 8K 0x00 9FFF 1K 0x00 03FF 0x00 0200 4K 0x00 BEEE 6 2 Register map 6 2 1 VO port hardware register map Table 10 VO port hardware register map Address Block Register label Register name Wak oxo05000 T PAODR PortAdataoutputlatchregister 0x00 0x00 5001 PA IDR Port A input pin value register Oxxx 0x00 5002 Port A PA DDR Port A data direction register 0x00 0x00 5003 PA CR1 Port A control register 1 0x00 0x00 5004 PA CR2 Port A control register 2 0x00 0x00 5005 PB ODR Port B data output latch register 0x00 0x00 5006 PB_IDR Port B input pin value register OO 0x00 5007 Port B PB_DDR Port B data direction register 0x00 0x00 5008 PB CR1 Port B control register 1 0x00 0x00 5009 PB CR2 Port B control register 2 0x00 0x00 500A PC ODR Port C data output latch register 0x00 0x00 500B PB IDR Port C input pin value register oxxx 0x00 500C Port C PC DDR Port C data direction register 0x00 0x00 500D PC CR1 Port C control register 1 0x00 0x00 500E PC CR2 Port C control register 2 0x00 0x00 500F PD ODR Po
16. 2 for 20 pin packages Added the note below Table STM8AF6226T alternate function remapping bits 1 0 for 32 pin packages Updated Table I2C characteristics to modify tyspa and add tsp Updated Section C assembly toolchains 03 Apr 2014 Replaced STM8AF6226T by STM8AF6226 part number Added STM8AF6223A part number to cover STM8AF6223PxAx order codes Removed LINUART alternate function for PA3 in Table STM8AF6223PxAx TSSOP20 pin description Removed note 3 for lapan in Table Total current consumption in active halt mode at VDD 5 V Updated the remapping option on PA3 for AFR 1 0 11 in Table STM8AF6223 alternate function remapping bits 1 0 for 20 pin packages Updated notes related to trer minimum value in Table Data memory Updated Table ESD absolute maximum ratings Added notes related to protrusions and gate burrs for D and E1 dimensions in Table 20 pin 4 40 mm body 0 65 mm pitch mechanical data 104 106 DoclD025118 Rev 5 d STM8AF6213 23 23A 26 Revision history Table 64 Document revision history continued Date Revision Changes Extended the applicability to STM8AF6213 devices Updated the program memory feature the power management and the clock management features on the cover page TUE 20de Added the table in Section Memory map Updated the Figure fopymax versus Vpp in Section Operating conditions Updated Section Ordering information
17. HS SPI MOSI TIM1 CH1 OSCOUT PA2 PC5 HS SPI SCK TIM5 CH1 VSS PC4 HS TIM1 CH4 CLK CCO AIN2 TIM1_CH2N VCAP PBO HS TIM1 CH1N AINO VDD PB1 HS TIM1 CH2N AIN1 TIM5 BKIN I2C SDA T pes 10 PB4 TyI2C SCL ADC ETR MS38346V1 HS high sink capability T true open drain P buffer and protection diode to Vpp not implemented alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function Table 6 STM8AF6213 STM8AF6223 TSSOP20 pin description Input Output DO 8 Main Default l O D Dx function o Pin name Type 2 E C XO function alternate 2 1515 012 2 afterreset function after remap F 6 SIE el 8100 option bit 2 1 09 mo c PD4 TIM5 CH1 Vao LINUART 1 BEEP VO X xX X HS O03 X X Port D4 1 BEEP clock LINUART_CK AFR2 output Analog input 5 PD5 AIN5 2 LINUART TX VO X xX X HS O03 X X Port D5 LINUART data transmit Analog PD6 AIN6 input 6 3 LINUART_RX VO X xX X HS 03 X X Port D6 LINUART data receive 4 NRST VO X Reset 5 PA OSCIND vo x X X for x X Porta1 Resonator S crystal in 6 PA20SCOUT vo X X X O1 X X Porta2 Resonator crystal out 7 VSS S Digital ground 8 VCAP S 1 8 V regulator capacitor 9 VDD S Digital power supply
18. Internal reference voltage on channel AIN7 e Analog watchdog interrupt e External trigger input e Trigger from TIM1 TRGO e Endof conversion EOC interrupt Additional AIN12 analog input is not selectable in ADC scan mode or with analog watchdog Values converted from AIN12 are stored only into the ADC_DRH ADC_DRL registers Internal bandgap reference voltage Channel AIN7 is internally connected to the internal bandgap reference voltage The internal bandgap reference is constant and can be used for example to monitor Vpp It is independent of variations in Vpp and ambient temperature Ta Communication interfaces The following communication interfaces are implemented e LINUART Full feature UART synchronous mode SPI master mode Smartcard mode IrDA mode single wire mode LIN2 2 capability e SPI full and half duplex 8 Mbit s e IC up to 400 Kbit s Some peripheral names differ between the datasheet and STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 see Table 4 Table 4 Communication peripheral naming correspondence Peripheral name in reference manual Peripheral name in datasheet RM0016 LINUART UART4 d DoclD025118 Rev 5 STM8AF6213 23 23A 26 Product overview 4 14 1 d LINUART Main features 1 Mbit s full duplex SCI SPI emulation High precision baud rate generator Smartcard emulation IrDA SIR encoder decoder LIN mode Single wire hal
19. L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 k 0 3 5 7 0 3 5 7 ccc 0 100 0 0039 1 Values in inches are converted from mm and rounded to 4 decimal digits DoclD025118 Rev 5 93 106 Package information STM8AF6213 23 23A 26 94 106 Figure 43 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint 0 80 EE UR NN F DDDDnnnp i 4 7 L 0 30 L LC N 7 30 16 0 50 9 70 EI a 7 30 L 1 gt NNN ppp lt lt 9 70 y 5V FP V2 1 Dimensions are expressed in millimeters Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 44 LQFP32 marking example package top view XXXXXX XXXXXX Product identification Date cod Standard ST logo ate coce Revision code Pin 1 identifier MS37789V1 DoclD025118 Rev 5 d STM8AF6213 23 23A 26 Package information 10 2 TSSOP20 package information Figure 45 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package outline SEATING PLANE C GAGE PLANE PIN 1 IDENTIFICATION 1 Drawing is not to scale YA ME V3 Table 62 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data m
20. Package information Device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location Figure 47 TSSOP20 marking example package top view Standard ST logo Product identification XXXXXXXXX Pin 1 identifier Date code Revision code TCE MS38373V1 g DoclD025118 Rev 5 97 106 Package information STM8AF6213 23 23A 26 10 3 10 3 1 10 3 2 98 106 Thermal characteristics The maximum chip junction temperature T max must never exceed the values given in Table 26 General operating conditions T max in degrees Celsius may be calculated using the following equation TJmax Tamax PDmax X Oja Where Tamax is the maximum ambient temperature in C y is the package junction to ambient thermal resistance in C W Ppmax is the sum of Pintmax and PyOmax PDmax Pintmax Piromax Pintmax is the product of lnn and Vpp expressed in Watts This is the maximum chip internal power Pyomax represents the maximum power dissipation on output pins Where Promax Vor lon X Vbp Vou log taking into account the actual Vo lo and Vou lou of the I Os at low and high level in the application Table 63 Thermal characteristics Symbol Parameter Value Unit Thermal resistance junction ambient S TSSOP20 4 x 4 mm ng Lud aaa EE JA Thermal resistance junction ambient 60 C W LQFP 32 7 x7 mm
21. Reserved area 43 byte 0x00 5340 TIM6_CR1 TIM6 control register 1 0x00 0x00 5341 TIM6_CR2 TIM6 control register 2 0x00 0x00 5342 TIM6_SMCR TIM6 slave mode control register 0x00 0x00 5343 TIM6_IER TIMG interrupt enable register 0x00 0x00 5344 TIM6 TIM6_SR TIM6 status register 0x00 0x00 5345 TIM6_EGR TIM6 event generation register 0x00 0x00 5346 TIM6_CNTR TIM6 counter 0x00 0x00 5347 TIM6_PSCR TIM6 prescaler register 0x00 0x00 5348 TIM6_ARR TIM6 auto reload register OxFF DoclD025118 Rev 5 41 106 Memory and register map STM8AF6213 23 23A 26 42 106 Table 11 General hardware register map continued 1 Depends on the previous reset source 2 Write only register DoclD025118 Rev 5 Address Block Register label Register name 2 ye a Reserved area 153 byte Hasan ADC1 ADC DBxR ADC data buffer registers 0x00 ps zi Reserved area 12 byte 0x00 5400 ADC CSR ADC control status register 0x00 0x00 5401 ADC CR1 ADC configuration register 1 0x00 0x00 5402 ADC CR2 ADC configuration register 2 0x00 0x00 5403 ADC CR3 ADC configuration register 3 0x00 0x00 5404 ADC DRH ADC data register high OxXX 0x00 5405 ADC DRL ADC data register low OxXX 0x00 5406 ADC TDRH ADC Schmitt trigger disable register high 0x00 0x00 5407 ADC TDRL ADC Schmitt trigger disable register low 0x00 0x00 5408 DEM ADC HTRH ADC high thre
22. d STM8 development tools Development tools for the STM8 microcontrollers include the full featured STice emulation System supported by a complete software tool package including C compiler assembler and integrated development environment with high level language debugger In addition the STMB is to be supported by a complete range of tools including starter kits evaluation boards and a low cost in circuit debugger programmer Emulation and in circuit debugging tools The STice emulation system offers a complete range of emulation and in circuit debugging features on a platform that is designed for versatility and cost effectiveness In addition the STMB8 application development is supported by a low cost in circuit debugger programmer The STice is the fourth generation of full featured emulators from STMicroelectronics It offers new advanced debugging capabilities including coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application In addition STice offers in circuit debugging and programming of STM8A microcontrollers via the STM8 single wire interface module SWIM which allows non intrusive debugging of an application while it runs on the target microcontroller For improved cost effectiveness STice is based on a modular design that allows you to order exactly what you need to meet your development requirements and to adapt your emulation system to support existing and f
23. eee ees 26 Table 8 STM8AF6226 LQFP32 pin description EE EE SE ee ee ee ee ee ee 29 Table 9 Memory model for the devices covered in this datasheet EE EE Ee 35 Table 10 I O port hardware register map EE EE EE ee EE n 35 Table 11 General hardware register map EE EE ee ee ee ek eee 36 Table 12 CPU SWIM debug module interrupt controller registers nananana EE EE Ee Ee ee 43 Table 13 Interrupt mapping 00 0 EE EE ee ee ee ee ee ee ee ee ee ee es 45 Table 14 Option bytes we x n e RRR RRR simre ee ee ee ee ee ee ee e hs 47 Table 15 Option byte description RR Ih 48 Table 16 STM8AF6226 alternate function remapping bits 7 2 for 32 pin packages 49 Table 17 STM8AF6213 and STM8AF6223 alternate function remapping bits 7 2 for 20 pin packages ns 50 Table 18 STM8AF6223A alternate function remapping bits 7 2 for 20 pin packages 50 Table 19 STM8AF6226 alternate function remapping bits 1 0 for 32 pin packages 51 Table 20 STM8AF6213 STM8AF6223 alternate function remapping bits 1 0 for 20 pin packageS n 51 Table 21 STM8AF6223A alternate function remapping bits 1 0 for 20 pin packages 52 Table 22 Voltage characteristics EE EE EG EE ee EG ee ee ee ee ee ee ee ee ee 54 Table 23 Current characteristics EE EE EE EG ee ee ee ee ee ee ee ee ee ee ee 55 Table 24 Thermal characteri
24. erase cycles and a high system integration level with internal clock oscillators watchdog and brown out reset Full documentation is offered as well as a wide choice of development tools Table 1 STM8AF6213 23 23A 26 features Device STM8AF6226 STM8AF6223 STM8AF6223A STM8AF6213 Pin count 32 20 Max number of GPIOs ed cd 16 including 12 high sink I Os Ext interrupt pins 28 16 Timer CAPCOM channels 6 7 6 7 Timer mah EE 3 4 2 4 A D converter channels 7 5 7 5 ud R em 8K 4k Data EEPROM byte 6400 RAM byte 1K Peripheral set Multipurpose timer TIM1 SPI 126 LINUART window WDG independent WDG ADC PWM timer TIM5 8 bit timer TIM6 1 No read while write RWW capability d 10 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Block diagram 3 Block diagram Figure 1 STM8AF6213 23 23A 26 block diagram Reset block M XTAL1 16MHz KS Clock controller Reset Reset gt M RC int 16 MHz Detector POR BOR RCint 128 kHz MTM Clock to peripherals and core lt Window WDG STM8 core dans KE Independent WDG Single wire debug interface EN Debug SWIM lt gt lt Up to 8 Kbyte program Flash 640 byte lt gt data EEPROM tee 1 Kbyte RAM Address and data bus X 400 Kbit s LA 12C dar Up to 8 Mbit s n SPI 4 j 16 bit a
25. express or implied to any intellectual property right is granted by ST herein Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product ST and the ST logo are trademarks of ST All other product or service names are the property of their respective owners Information in this document supersedes and replaces information previously supplied in any prior versions of this document 2015 STMicroelectronics All rights reserved d 106 106 DoclD025118 Rev 5 Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery amp Lifecycle Information STMicroelectronics STM8AF6226TASSSX STM8AF6226TASSSY STM8AF6226TCSSSX STM8AF6226TCSSSY STM8AF6223PDU STM8AF6213PCX STM8AF6223PCAX
26. features pinout electrical characteristics mechanical data and ordering information e For complete information on the STM8A microcontroller memory registers and peripherals please refer to STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 e For information on programming erasing and protection of the internal Flash memory please refer to the STM8 Flash programming manual PM0051 e For information on the debug and SWIM single wire interface module refer to the STM8 SWIM communication protocol and debug module user manual UM0470 e For information on the STM6 core please refer to the STM8 CPU programming manual PM0044 DoclD025118 Rev 5 9 106 Description STM8AF6213 23 23A 26 2 Description The STM8AF6213 STM8AF6223 STM8AF6223A and STM8AF6226 automotive 8 bit microcontrollers offer 4 to 8 Kbyte of Flash program memory plus integrated true data EEPROM The STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 refers to devices in this family as low density They provide the following benefits performance robustness and reduced system cost Device performance and robustness are ensured by advanced core and peripherals made in a state of the art technology a 16 MHz clock frequency robust I Os independent watchdogs with separate clock source and a clock security system The system cost is reduced thanks to an integrated true data EEPROM for up to 300 kwrite
27. for sound generation The signal is in the range of 1 2 or 4 kHz The beeper output port is only available through the alternate function remap option bit AFRT TIM1 16 bit advanced control timer This is a high end timer designed for a wide range of control applications With its complementary outputs dead time control and center aligned PWM capability the field of applications is extended to motor control lighting and half bridge driver e 16 bit up down and up down auto reload counter with 16 bit fractional prescaler e Fourindependent capture compare channels CAPCOM configurable as input capture output compare PWM generation edge and center aligned mode and single pulse mode output e Synchronization module to control the timer with external signals or to synchronise with TIM5 or TIM6 e Break input to force the timer outputs into a defined state e Three complementary outputs with adjustable dead time s Encoder mode s Interrupt sources 3 x input capture output compare 1 x overflow update 1 x break g DoclD025118 Rev 5 STM8AF6213 23 23A 26 Product overview 4 11 4 12 TIM5 16 bit general purpose timer 16 bit autoreload AR up counter 15 bit prescaler adjustable to fixed power of 2 ratios 1 32768 3 individually configurable capture compare channels PWM mode Interrupt sources 3 x input capture output compare 1 x overflow update Synchronization module to control the timer with external
28. g 2 2 j A amp afterreset function after remap kar 8S 5 E c 2 O Je option bit dol MHE lt Analog input 3 AFR2 27 PD2 AIN3 VO X X X HS 03 X X Port D2 Timer 52 TIM5 CH3 channel 3 AFR1 Analog input PD3 AIN4 4 Ha i 28 TIM5 CH2 VO X X X HS O3 XIX Port D3 2IADC ADC ETR external trigger PD4 Timer 5 TIM5_CH1 channel LINUART a BEEP Ko X o ATHS LOS ANA Fom D3 1 BEEP clock AFR2 LINUART CK output Analog input PD5 AIN5 30 LINUART TX VO X X X HS O3 X X Port D5 5 LINUART data transmit Analog input PD6 AIN6 31 LINUART RX VO X X X HS 03 X X Port D6 6 LINUART data receive Timer 1 32 FEET vo X X X IHS O3 X X PortD7 Top level channel 4 TIM1 CH4 interrupt AFRE 1 VO pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Section Absolute maximum ratings 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain VO P buffer weak pull up and protection diode to VDD are not implemented 4 The PD1 pin is in input pul
29. loading conditions STM8A PIN 50 pF MSv37796V1 DoclD025118 Rev 5 53 106 Electrical characteristics STM8AF6213 23 23A 26 9 1 5 9 2 54 106 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 8 Figure 8 Pin input voltage STM8A PIN MSv37797V1 Absolute maximum ratings Stresses above those listed as absolute maximum ratings may cause permanent damage to the device This is a stress rating only and functional operation of the device under these conditions is not implied Exposure to maximum rating conditions for extended periods may affect device reliability Table 22 Voltage characteristics Symbol Ratings Min Max Unit Vppx Vss Supply voltage including VppA and Vppio 0 3 6 5 V Input voltage on true open drain pins 2 Vss 0 3 6 5 IN Input voltage on any other pin Vss 0 3 Vpp 0 3 N Vppx Vppl Variations between different power pins 50 IVssx V ssl Variations between all the different ground pins 50 ini see Absolute maximum ratings VESD Electrostatic discharge voltage electrical sensitivity on page 90 All power Vpp and ground Vss pins must always be connected to the external power supply cannot be respected the injection current must be limited externally to the lapin value A positive injection is induced by Vin gt Vpp while a negative injection is induced by VIN
30. management feature is no more available If this remapping option is selected and the SPI is enabled the SSM bit must be configured in the SPI_CR2 register to select software NSS management 52 106 DoclD025118 Rev 5 Ly STM8AF6213 23 23A 26 Electrical characteristics 9 9 1 d Electrical characteristics Parameter conditions Unless otherwise specified all voltages are referred to Vss Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature supply voltage and frequencies by tests in production on 100 of the devices with an ambient temperature at T4 40 C Ta 25 C and TA Tamax given by the selected temperature range Data based on characterization results design simulation and or technology characteristics are indicated in the table footnotes and are not tested in production Typical values Unless otherwise specified typical data are based on T4 25 C Vpp 5 0 V They are given only as design guidelines and are not tested Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range Typical curves Unless otherwise specified all typical curves are given only as design guidelines and are not tested Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 7 Figure 7 Pin
31. racl p lt tsu STO 1 I sTopi t 9 tsu STA STO 1 L ai17490V2 Measurement points are made at CMOS levels 0 3 x Vpp and 0 7 x Vpp DoclD025118 Rev 5 85 106 Electrical characteristics STM8AF6213 23 23A 26 9 3 10 10 bit ADC characteristics Subject to general operating conditions for Vpp fuaster and Ta unless otherwise specified Table 54 ADC characteristics Symbol Parameter Conditions Min Typ Max Unit Vpp 3 to 5 5 V 1 4 fapc ADC clock frequency EE MHz Vpp 4 5 to 5 5 V 1 6 V Conversion voltage l V l V V AN ange SS DD V Internal bandgap Van 231055V Q 422 2 V BGREF reference voltage DD i 1 19 i 1 25 Internal sample and hold Canc capacitor l 3 pF fADC 4MHz 0 75 tg Minimum sampling time fADC 6MHz 0 5 US tstap Wakeup time from standby 7 Minimum total conversion Tug d d c me us tcony time including sampling fapc 6 MHz 2 33 time 10 bit resolution 14 abc 1 During the sample time the input capacitance Can 3 pF max can be charged discharged by the external source The internal resistance of the analog source must allow the capacitance to reach its final voltage level within ts After the end of the sample time ts changes of the analog input voltage have no effect on the conversion result Values for the sample clock ts depend on programming 2 Tested in production d 86 106 DoclD025118 Rev 5
32. signals or to synchronize with TIM1 or TIM6 TIM6 8 bit basic timer 8 bit autoreload adjustable prescaler ratio to any power of 2 from 1 to 128 Clock source CPU clock Interrupt source 1 x overflow update Synchronization module to control the timer with external signals or to synchronize with TIM1 or TIM5 Table 3 TIM timer features Timer TIM1 Counter Counting CAPCOM Complemen size bits mode channels _ tary outputs Timer synchroniz ation chaining Prescaler Ext trigger Any integer 16 from 1 to Up down 4 3 Yes 65536 TIM5 Any power 16 of 2 from 1 Up 3 0 No Yes to 32768 TIM6 Any power 8 of 2 from 1 Up 0 0 No to 128 d DoclD025118 Rev 5 19 106 Product overview STM8AF6213 23 23A 26 4 13 Note 4 14 20 106 Analog to digital converter ADC1 The STM8AF6213 STM8AF6223 STM8AF6223A and STM8AF6226 products contain a 10 bit successive approximation A D converter ADC1 with up to 7 external and 1 internal multiplexed input channels and the following main features s Input voltage range O to Vpp e Input voltage range 0 to Vppa e Conversion time 14 clock cycles e Single and continuous and buffered continuous conversion modes e Buffer size n x 10 bits where n number of input channels e Scan mode for single and continuous conversion of a sequence of channels e Analog watchdog capability with programmable upper and lower thresholds e
33. the CLK_ICKR register Ly DoclD025118 Rev 5 61 106 Electrical characteristics STM8AF6213 23 23A 26 3 Configured by the AHALT bit in the FLASH CR1 register Total current consumption in halt mode Table 34 Total current consumption in halt mode at Vpp 5 V B Max at Maxat Max at Symbol Parameter Conditions Typ 85 C 125 C 150 C Unit Flash in operating mode 63 75 105 i Supply current in halt HSI clock after wakeup is DD H S mode Flash in power down mode 6 0 20 0 55 1 ao HSI clock after wakeup 1 Tested in production Table 35 Total current consumption in halt mode at Vpp 3 3 V HP Max at Max at Symbol Parameter Conditions Typ 85c 1 425 C 1 Unit Flash in operating mode 60 75 100 Supply current in halt HSI clock after wakeup ui DD H mode Flash in power down mode 45 47 30 HSI clock after wakeup 1 Data based on characterization results not tested in production Low power mode wakeup times Table 36 Wakeup times Symbol Parameter Conditions Typ Max Unit Wakeup time 0 to 16 MHz See 3 twuwrl from wait mode to run mode fcpu fmasTER7 16 MHz 0 56 6 6 MVR voltage 10 20 4 a 6 Wakeup time regulator on Flash in HSI after 3 6 3 twu AH active halt mode operating wakeup US to run model MVR voltage model p 48 regulator off 50 8 E Wakeup time Flash in operating mode
34. to select software NSS management Table 20 STM8AF6213 STM8AF6223 alternate function remapping bits 1 0 for 20 pin packages AFR1 option bit value AFRO option bit value VO port Alternate function mapping AFR1 and AFRO remapping options inactive 0 0 S Default alternate functions PC5 TIM5_CH1 0 1 PC6 TIM1_CH1 PC7 TIM1_CH2 i a PA3 SPI NSS PD2 TIM5_CH3 DoclD025118 Rev 5 51 106 Option bytes STM8AF6213 23 23A 26 Table 20 STM8AF6213 STM8AF6223 alternate function remapping bits 1 0 for 20 pin packages continued AFR1 option bit value AFRO option bit value 1O port Treaty PD2 TIM5_CH3 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 1 1 PC2 Not available PC1 Not available PE5 Not available PA3 SPI NSS PF4 Not available 1 Refer to the pin descriptions Table 21 STM8AF6223A alternate function remapping bits 1 0 for 20 pin packages AFR1 option bit value AFRO option bit value VO port m 0 0 AFR1 and AFRO remapping options inactive Default alternate functions PC5 TIM5 CH1 0 1 PC6 TIM1 CH1 PC7 TIM1_CH2 PA3 Not available i PD2 TIM5_CH3 PD2 TIM5_CH3 PC5 TIM5 CH1 PC6 TIM1 CH1 PC7 TIM1_CH2 12 12 PC2 Not available PC1 Not available PE5 Not available PA3 Not available PF4 Not available 1 Refer to the pin descriptions 2 If both AFR1 and AFRO option bits are set the SPI hardware NSS
35. via the SWIM protocol Additional tools include a low cost in circuit programmer as well as ST socket boards which provide dedicated programming platforms with sockets for programming the STM8 For production environments programmers will include a complete range of gang and automated programming solutions from third party tool developers already supplying programmers for the STM8 family DoclD025118 Rev 5 103 106 d Revision history STM8AF6213 23 23A 26 13 Revision history Table 64 Document revision history Date 11 Oct 2013 Revision 1 Changes Initial release 16 Dec 2013 Changed the document status to Production data Updated Figure STM8AF6223PxAx TSSOP20 pinout to add SPI_NSS to PD4 TLI to PD2 and change remap function on PB5 from TIM5 BKiln to TIM1 BKIN Updated Table STM8AF6223PxAx TSSOP20 pin description to add SPI NSS to PD4 and TLI to PD2 Updated Table STM8AF6223 TSSOP20 pin description and Table LQFP32 pin description Updated AFR2 definition in Table STM8AF6223PxAx alternate function remapping bits 7 2 for 20 pin packages Removed the remapping option on PA3 for AFR 1 0 510 in Table STM8AF6223PXAx alternate function remapping bits 1 0 for 20 pin packages Added note and removed remapping option on PA3 for AFR 1 0 11 in Table STM8AF6223 alternate function remapping bits 1 0 for 20 pin packages Updated AFR2 definition in STM8AF6223 alternate function remapping bits 7
36. 106 Pinout and pin description STM8AF6213 23 23A 26 Table 6 STM8AF6213 STM8AF6223 TSSOP20 pin description continued Input Output a Ble Main Default Alternate o s o 2x function o Pin name Type amp 3 c c o function alternate 2 S 515 9 1 A a cafterreset functio after remap 5 35 E c 2 O e option bit amp 9 9 mo c Analog input 3 PD2 AIN3 AFR2 19 TIM5 CH3 VO X XI X HS 03 X X Port D2 Timer 52 channel 3 AFR1 Analog input 4 PD3 AIN4 Timer 52 20 TIM5 CH2 VO X XI XIHS O X X Port D3 channel ADC_ETR 2 ADC external trigger 1 VO pins used simultaneously for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Section Absolute maximum ratings 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to VDD are not implemented 4 The PD1 pin is in input pull up during the reset phase and after internal reset release Table 7 STM8AF6223A
37. 2 OxFF 0x00 7F72 ITC_SPR3 Interrupt software priority register 3 OxFF 0x00 7F73 ITC_SPR4 Interrupt software priority register 4 OxFF 0x00 7F74 iis ITC SPR5 Interrupt software priority register 5 OxFF 0x00 7F75 ITC_SPR6 Interrupt software priority register 6 OxFF 0x00 7F76 ITC_SPR7 Interrupt software priority register 7 OxFF 0x00 7F77 ITC_SPR8 Interrupt software priority register 8 OxFF pe SE Reserved area 2 byte 0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00 pees Reserved area 15 byte Ky DoclD025118 Rev 5 43 106 Memory and register map STM8AF6213 23 23A 26 Table 12 CPU SWIM debug module interrupt controller registers continued Address Block Register label Register name en oxoo7F90 DM BKIRE DMbreakpoint 1 register extended byte OxFF 0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte OxFF 0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte OxFF 0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte OxFF 0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte OxFF 0x00 7F95 DM DM_BK2RL DM breakpoint 2 register low byte OxFF 0x00 7F96 DM CR1 DM debug module control register 1 0x00 0x00 7F97 DM CR2 DM debug module control register 2 0x00 0x00 7F98 DM CSR1 DM debug module control status register 1 0x10 0x00 7F99 DM CSR2 DM debug module control status register 2 0x00 0x00 7F9A DM ENFCTR DM enable function register OxFF pe Pues Res
38. 23 23A 26 9 3 11 EMC characteristics cece eee 89 10 Package information xs sps 2 pur K 92 10 1 LQFP32 package information 0 00 c eee eee 92 10 2 TSSOP20 package information 0 000 cee eee 95 10 3 Thermal characteristics SEE SS SE ES ee eee 98 10 3 1 Reference document ccc eee eee 98 10 3 2 Selecting the product temperature range ie EE EE se ee 98 11 Ordering information 20026260000 EER hr RE eee ees 100 12 STM8 development tools 00 cee ee eee eee eee 101 12 1 Emulation and in circuit debugging tools ii EE ee 101 12 1 1 STice key features ee 101 12 2 Softwaretools eee eee 102 1221 STM toolset ool e EI Be ee e p PRA AA 102 12 2 2 C and assembly toolchains lille 102 12 3 Programming tools ees 103 13 Revision history n RII 104 4 106 DoclD025118 Rev 5 Ly STM8AF6213 23 23A 26 List of tables List of tables Table 1 STM8AF6213 23 23A 26 features EE EE GE Ee Ge ee ee ee ee ee ese 10 Table 2 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers 16 Table 3 TIM timer features RRR ce eee eee 19 Table 4 Communication peripheral naming correspondence eae 20 Table 5 Legend abbreviations for pinout tables 020 eee 23 Table 6 STM8AF6213 STM8AF6223 TSSOP20 pin description 0000 a 24 Table 7 STM8AF6223A TSSOP20 pin description 0c
39. 28 l Os on a 32 pin package including 21 high sink outputs Highly robust I O design immune against current injection Communication interfaces LINUART LIN 2 2 compliant master slave modes with automatic resynchronization SPI interface up to 8 Mbit s or fuAsTER 2 C interface up to 400 Kbit s Analog to digital converter ADC 10 bit 1 LSB ADC with up to 7 muxed channels 1 internal channel scan mode and analog watchdog Internal reference voltage measurement Operating temperature up to 150 C Qualification conforms to AEC Q100 rev G DoclD025118 Rev 5 1 106 This is information on a product in full production www st com Contents STM8AF6213 23 23A 26 Contents 1 Introduction uai xx ESAE bees NAKA kee Ree EE eke OE OE 9 2 Description cessere e te PR EE eee PAL bia RN E 10 3 Block diagram ee PETI T 11 4 Product overview Ts e KR 13 4 1 Central processing unit CPU 0c eee ee 13 4 1 1 Architecture and registers EE EE Ee ee 13 4 1 2 Addressing 0c cece eee eee eee 13 4 1 3 Instruction set oori aau paden rase y em Cab dale a WE es Ae NG 13 4 2 Single wire interface module SWIM and debug module DM 14 4 2 1 SWIME S ses ET GANA ER dM eee UI uae EU 14 4 2 2 Debug module 2 022200 TA Ery LANANG m be ee ee es 14 4 3 Interrupt controller EE EE EE EE EE EE Ee ee ke ke ke ke ee 14 4 4 Flash program and data EEPROM memory a 14 4 4 1 Write protec
40. 52 twum from halt mode to di run mode 2 Flash in power down mode 54 1 Data guaranteed by design not tested in production 2 Measured from interrupt event to interrupt vector fetch 3 twuwen 2 X l fuAsrER 67 x Tfopu 4 Configured by the REGAH bit in the CLK ICKR register 5 Configured by the AHALT bit in the FLASH CR1 register 6 Plus 1 LSI clock depending on synchronization 62 106 DoclD025118 Rev 5 Ly STM8AF6213 23 23A 26 Electrical characteristics Total current consumption and timing in forced reset state Table 37 Total current consumption and timing in forced reset state Symbol Parameter Conditions Typ Max Unit Vpp 5 V 400 Ipp R Supply current in reset state UA Vpp 3 3 V 300 eee pin release to vector l 150 us 1 Data guaranteed by design not tested in production 2 Characterized with all I Os tied to Vgg Current consumption for on chip peripherals Subject to general operating conditions for Vpp and Ta HSI internal RC fcpy fyasTER 16 MHz Vpp 5V Table 38 Peripheral current consumption Symbol Parameter Typ Unit Ippctim1 TIM1 supply current 210 IDD TIM5 TIM5 supply current 130 IDD TiMe TIM6 supply current 50 IDD UART1 LINUART supply current 120 UA Ipp sP SPI supply current 45 Ippu2c 2C supply current 65 lpp apc1 ADC1 supply current 1000 1 Data based on a differen
41. 7 ms Power on reset 1 Vine threshold 2 6 af 2 85 Brown out reset 1 Vig ibid 2 5 2 65 2 8 Brown out reset VHYS BOR hysteresis l E 700 mV Guaranteed by design not tested in production 2 Reset is always generated after a trgyp delay The application must ensure that Vpp is still above the minimum operating voltage Vpp min when the trepp delay has elapsed 3 There is inrush current into Vpp present after device power on to charge CExT capacitor This inrush energy depends from Cey7 capacitor value For example a Cex7 of 1UF requires Q 1 pF x 1 8V 1 8 UC q DoclD025118 Rev 5 57 106 Electrical characteristics STM8AF6213 23 23A 26 9 3 1 VCAP external capacitor Stabilization for the main regulator is achieved connecting an external capacitor CExr to the Vcap pin Cgxr is specified in Table 26 Care should be taken to limit the series inductance to less than 15 nH Figure 10 External capacitor CExT C ESL ln zz raro ESR RLeak MSv36488V1 1 Legend ESR is the equivalent series resistance and ESL is the equivalent inductance 9 3 2 Supply current characteristics The current consumption is measured as described in Section 4 3 Interrupt controller Total current consumption in run mode The MCU is placed under the following conditions e All I O pins in input mode with a static value at Vpp or Vss no load e All periphe
42. Added the footnote about the inrush current below Table 27 Operating conditions at power up power down Figure 44 LQFP32 marking example package top view Figure 47 TSSOP20 marking example package top view Updated LIN standard version the register label for LINUART block in Table 11 26 Jun 2015 5 General hardware register map the power dissipation in Table 26 General operating conditions Table 41 HSI oscillator characteristics for HSI oscillator accuracy the standard for EMI in Electromagnetic interference EMI Figure 48 STM8AF6213 23 23A 26 ordering information scheme 1 2 to add HSI accuracy Moved Section 10 3 Thermal characteristics to Section 10 Package information Ly DoclD025118 Rev 5 105 106 STM8AF6213 23 23A 26 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ST reserve the right to make changes corrections enhancements modifications and improvements to ST products and or to this document at any time without notice Purchasers should obtain the latest relevant information on ST products before placing orders ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement Purchasers are solely responsible for the choice selection and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products No license
43. B4 I2C clock trigger AFR4 Timer 1 PB1 inverted 12 TIM1 CH2N VO X X X HS O03 X X Port B1 channel AIN1 2 Analog input 1 Timer 1 PBO inverted 13 TIM1 CH1N AINO y o X X X HS 03 X X Port BO channel 1 Analog input 0 Timer 1 Analog PC4 TIM1_CH4 channel 4 input 2 14 CLK CCO AIN2 VO X X X HS 03 X X Port C4 configurabl AFR2 Time TIM1 CH2 e clock r 1 channel output 2 AFR7 Timer 5 15 MS CHI VO X X X HS O3 X X Port C5 SPI clock channel 1 En AFRO Ly DoclD025118 Rev 5 27 106 Pinout and pin description STM8AF6213 23 23A 26 Table 7 STM8AF6223A TSSOP20 pin description continued Input Output a Ble Main Default Alternate O o gx function N Pin name Type c 5 c clib function alternate 2 2 2 gt 4 8 19 C afterreset function atter remap j 6 3 5 gg 0 option bit ORE mo PC6 SPI MOSI PI master mer 16 TIM1 CH1 VO X X X HS O3 X X Port C6 o tslav in channel 1 AFRO PC7 SPI MISO SPI master ler 17 TIM4 CH2 VO X X X HS O3 X X Port C7 ini clave out channel 2 AFRO 18 pp SWM vo X X x us os x x Ponp SWIM data interface Analog input 3 PD2 AIN3 AFR2 9 nimus ca YO X X X HS os x x PortD2 S Pan channel 3 AFR1 Analog input 4 PD3 AIN4 Timer 52 20 TIM5 CH2 VO X X X HS O3 X X Port D3 channel ADC ETR 2 ADC external trigger 1 VO pins used simultaneo
44. CKDIVR Clock divider register 0x18 0x00 50C7 und CLK PCKENR1 Peripheral clock gating register 1 OxFF 0x00 50C8 CLK CSSR Clock security system register 0x00 0x00 50C9 CLK CCOR Configurable clock control register 0x00 0x00 50CA CLK PCKENR2 Peripheral clock gating register 2 OxFF 0x00 50CB Reserved area 1 byte 0x00 50CC CLK HSITRIMR HSI clock calibration trimming register 0x00 0x00 50CD ins CLK SWIMCCR SWIM clock control register esas COQUE Reserved area 3 byte 0x00 50D1 mine WWDG_CR WWDOG control register Ox7F 0x00 50D2 WWDG WR WWDR window register Ox7F pang paaa Reserved area 13 byte 0x00 50E0 IWDG KR IWDG key register 0xxxO 0x00 50E1 IWDG IWDG PR IWDG prescaler register 0x00 0x00 50E2 IWDG RLR IWDG reload register OxFF es ipud Reserved area 13 byte 0x00 50F0 AWU CSR1 AWU control status register 1 0x00 0x00 50F1 AWU AWU APR AWU idi ec arn buffer Ox3F 0x00 50F2 AWU TBR AWU timebase selection register 0x00 0x00 50F3 BEEP BEEP CSR BEEP control status register Ox1F paang ee Reserved area 12 byte DoclD025118 Rev 5 37 106 Memory and register map STM8AF6213 23 23A 26 Table 11 General hardware register map continued Address Block Register label Register name _ 0x00 5200 SPI_CR1 SPI control register 1 0x00 0x00 5201 SPI_CR2 SPI control register 2 0x00 0x00 5202 SPI ICR SPI in
45. Max twscLL SCL clock low time 4 7 5 1 3 5 tw SCLH SCL clock high time 4 0 i 0 6 tsu sDa SDA setup time 250 100 th SDA SDA data hold time 0 3 3450 o 900 SDA SDA and SCL rise time 1000 300 NS t sc SDA SDA and SCL fall time 300 z 300 tscL thista START condition hold time 4 0 0 6 tsu STA Repeated START condition setup time 4 7 0 6 tsusto STOP condition setup time 4 0 0 6 US t STOP to START condition time 47 13 w STO STA bus free S R a 7 Pulse width of spikes suppressed by 5 tsp the input filter d 50 0 39 is Cp Capacitive load for each bus line 400 400 pF 1 fmaster must be at least 8 MHz to achieve max fast I C speed 400 kHz time undefined region of the falling edge of SCL Data based on standard IC protocol requirement not tested in production 5 The minimum width of the spikes filtered by the analog filter is above tsp max DoclD025118 Rev 5 The maximum hold time of the start condition has only to be met if the interface does not stretch the low The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the d STM8AF6213 23 23A 26 Electrical characteristics d Figure 39 Typical application with I2C bus and timing diagram 1 START l I I WSDA gt e me SDA pile isu SDA P7 h STA r NSC gt e th SDA SCL LLE VEE 1 tw SCLH 7 H SCL HHH LE
46. O Je option bit dol d T Timer 1 PE5 SPI NSS SPI master inverted L TIM1 CH1N um KN e S ER Pon ES slave select channel 1 AFR1 0 PC1 Timer 1 Timer 1 TIM1 CH1 channel 1 inverted 18 LINUART_CK No Ec Be MEES ode X Para LINUART channel 2 TIM1 CH2N clock AFR1 0 PBA Timer1 e 19 TIM1_CH2 VO X X X HS OS X X Port C2 TIM1 CH3N channel 2 channel 3 AFR1 0 Top level R Timer 1 DER Eu 20 TIM1 CH3 TLI VO X X X HS OS X X Port C3 l channel 3 1 inverted TIM1 CH1N channel 1 AFR7 Analog input PC4 Timer 1 2 TIM1_CH4 channel 4 AFR2 Timer 2 CLK CCO AIN uM X 2s 28 EE Pot CA configurable 1 inverted 2 TIM1 CH2N clock output channel 2 AFR7 Timer 5 22 Tie Gate VO X X X HS 03 X X Port C5 SPI clock channel 1 AFRO PC6 Pimast r Timer 1 23 SPI_MOSI VO XIXI X HS O3 X X Port C6 Steve n channel 1 TIM1 CH1 AFRO PC7 SPI master Timer 1 24 SPI_MISO VO X X X HS OS X X Port C7 inf Slave cut channel TIM1_CH2 2 AFRO PDO Timer 1 Configurable 25 TIM1 BKIN VO X X X HS 03 X X Port DO break BUE clock output CLK CCO P AFR5 26 Pbti SWM vo X X X HS O4 X X ponr p SWIM data interface Ly DoclD025118 Rev 5 31 106 Pinout and pin description STM8AF6213 23 23A 26 Table 8 STM8AF6226 LQFP32 pin description continued Input Output S Ble Main Default ARUM am la Pin name Type 2 s f fv function alternate
47. OPT5 HSECNT 7 0 HSE crystal oscillator stabilization time 0x00 2048 HSE cycles OXB4 128 HSE cycles OxD2 8 HSE cycles OxE1 0 5 HSE cycles STM8AF6213 23 23A 26 alternate function remapping bits Table 16 STM8AF6226 alternate function remapping bits 7 2 for 32 pin packages Option byte number OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive default alternate function 2 1 Port C3 alternate function TIM1_CH1N port C4 alternate function TIM1 CH2N AFR6 Alternate function remapping option 6 0 AFR6 remapping option inactive default alternate function 2 1 Port D7 alternate function TIM1 CHA AFR5 Alternate function remapping option 5 0 AFR5 remapping option inactive default alternate function 2 1 Port DO alternate function CLK CCO AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive default alternate function 2 1 Port B4 alternate function ADC ETR port B5 alternate function TIM1 BKIN AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive default alternate function 2 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive default alternate function 2 1 Port C4 alternate function AIN2 port D2 alternate function AIN3 port D4 alternate function LINUART CK 1 Do not use more than one remapping o
48. R4 AFR3 AFR2 AFR1 AFRO 0x00 function 0x00 remapping Jaha AFR NOPT2 NAFR7 NAFR6 NAFR5 NAFR4 NAFR3 NAFR2 NAFR1 NAFRO OxFF 0x00 HSI LSI IWDG WWDG WWDG 4805 E OPiS Reserved TRIM _EN _HW HW HALT 0x00 0x00 option NHSI NLSI NIWDG NWWDG NWWG 4806 NOPT3 Reserved TRIM EN HW Hw HALT OFF 0x00 EXT CKAWU PRS PRS 4807 OPT4 Reserved CLK SEL C4 CO 0x00 Clock option 0x00 NEXT NCKAWU NPRS NPRS 4808 NOPT4 Reserved CLK SEL C4 CO OxFF pons OPT5 HSECNT 7 0 0x00 HSE clock startup pu NOPT5 NHSECNT 7 0 OxFF Ky DoclD025118 Rev 5 47 106 Option bytes STM8AF6213 23 23A 26 8 1 Option byte description Table 15 Option byte description Option byte no OPTO Description ROP 7 0 Memory readout protection ROP OxAA Enable readout protection write access via SWIM protocol Note Refer to STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 section on Flash EEPROM memory readout protection for details OPT1 OPT2 for more details UBC 7 0 User boot code area 0x00 No UBC no write protection 0x01 Page 0 defined as UBC memory write protected 0x02 Page 0 to 1 defined as UBC memory write protected Pages 0 and 1 contain the interrupt vectors Ox7F Pages 0 to 126 defined as UBC memory write protected Other values Page 0 to 127 defined as UBC memory write protected Note Refer to STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 se
49. TER taisoy PO Data output disable time Slave mode 25 2 dis Slave mode 7 tso Data output valid time after enable edge 65 2 T Master mode t MO Data output valid time after enable edge 36 DoclD025118 Rev 5 81 106 Electrical characteristics STM8AF6213 23 23A 26 Table 52 SPI characteristics continued Symbol Parameter Conditions Min Max Unit 2 Slave mode t80 after enable edge al Data output hold time ns t 2 Master mode 11 h MO after enable edge 1 Parameters are given by selecting 10 MHz I O output frequency Values based on design simulation and or characterization results and not tested in production Min time is for the minimum time to drive the output and the max time is for the maximum time to validate the data 4 Min time is for the minimum time to invalidate the output and the max time is for the maximum time to put the data in Hi Z Figure 36 SPI timing diagram slave mode and CPHA 0 NSS input ISU NSS lg Ra tec 935 In NS8 1 U 1 1 Vi E E 1 1 j N fees id X NN 1 tw SCKH n i i 1 35 CPHA 0 tw SCKL n i a CPOL 1 N Ao m U 1 1 i 1 l n NGO TH th S0 a p pig Mo tais S0 epi 1 MISO MSB OUT BITS out iso OUT OUTPUT tsu S bree l MOSI 1 SN GUT E MSR IN BIT IN Y ean Y 1 ra ths ai14134c 1 Measurement points are made at CMOS lev
50. TSSOP20 pin description Input Output A 8 Main Default Alternate O D 2x function o Pin name Type 3 c s function alternate 2 S 1515 919 BG lftrreset function after remap F 5 3 E c 2 0O D option bit del wo PD4 TIM5_CH1 ous LINUART 1 BEEP SPI NSS VO X X X HS O3 X X Port D4 1 BEEP clock LINUART CK AFR2 output Analog input 5 PD5 AIN5 2 LINUART TX VO X X X HS O3 X X Port D5 LINUART data transmit 26 106 DoclD025118 Rev 5 g STM8AF6213 23 23A 26 Pinout and pin description Table 7 STM8AF6223A TSSOP20 pin description continued Input Output o amp c Main Default Alternate O o gx function N Pin name Type c 5 c clib function alternate 2 2 2 gt 4 8 19 C afterreset function atter remap j 6 3 5 gg 0 option bit o0 wo lt Analog PD6 AING input 6 3 LINUART RX VO X X X HS O3 X X Port D6 LINUART data receive 4 NRST VO X Reset 5 PA OSCIND vo XI X X fort x x Portar Resonator crystal in 6 PAgOSCOUT vo X X X o x x Poraz Resonator crystal out 7 VSS S Digital ground 8 VCAP S 1 8 V regulator capacitor 9 VDD S Digital power supply Timer 1 MEER VO X X X at ELK Port A5 I2C data break input AFR4 ADC PB4 I2C_SCL l l Gl external 11 ADC_ETR VO X X O1 T Port
51. afterreset function after remap kar SE OO option bit dol d T 4 VSS Digital ground 5 VCAP 1 8 V regulator capacitor 6 VDD Digital power supply SPI master PA3 slave select TIM5_CH3 Timer 52 AFR1 7 SPI_NSS ko X X LUN NA Por ag channel 3 LINUART LINUART TX data transmit AFR1 0 PEA LINUART 8 VO X Xl 01 X X Port F4 data receive LINUART RX AFR1 0 9 PB7 VO X X X 10 X X Port B7 10 PB6 VO X X X O1 X X Port B6 Timer 1 11 TM EN O Es ee GA TE ET Port B5 I2C data break input AFR4 ADC PB4 I2C SCL l 7 GT external 12 ADC ETR VO X X O1 T Port B4 I2C clock trigger AFR4 T E 13 AINS TIM1 ET VO X X X HS OS X X Port B3 R external trigger Analog input PB2 AIN2 2 Timer 1 14 TIM4 CH3N VO X X X HS OS X X Port B2 inverted channel 3 Analog input PB1 AIN1 1 Timer 1 15 TIM1_CH2N VO X X X HS OS X X Port B1 inverted channel 2 Analog input PBO AINO 0 Timer 1 16 TIM1 CHIN VO X X X HS OS X X Port BO inverted channel 1 30 106 DoclD025118 Rev 5 Ly STM8AF6213 23 23A 26 Pinout and pin description Table 8 STM8AF6226 LQFP32 pin description continued Input Output S Ble Main Default ARUM ees la Pin name Type 2 5 E fic function alternate g 2 2 j A amp afterreset function after remap kar 8S 5 E c 2
52. and simplified MCU software It should be noted that good EMC performance is highly dependent on the user application and the software in particular Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application Prequalification trials Most of the common failures unexpected reset and program counter corruption can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second To complete these trials ESD stress can be applied directly on the device over the range of specification values When unexpected behavior is detected the software can be hardened to prevent unrecoverable errors occurring see the application note reference AN1015 Table 57 EMS data Symbol Parameter Conditions Level class souk Vpp 3 3 V Tas 25 C Voltage limits to be applied on any VO pin 1 VFESD to induce a functional disturbance fmasTER 16 MHz HSI clock 2 B Conforms to IEC 61000 4 2 Fast transient voltage burst limits to be Vpp 3 3 V Taz 25 C Verte applied through 100 pF on Vpp and Vss__ faster 16 MHz HSI clock AA pins to induce a functional disturbance Conforms to IEC 61000 4 4 1 Data obtained with HSI clock configuration after applying hardware recommendations described in AN2860 EMC guidelines for STM8S microcontrollers DoclD025118 Rev 5 89 106 Electrical chara
53. capacitor VcAp ESR of external capacitor 0 3 Q at 1 MHz ESL of external capacitor 15 nH Power dissipation at TSSOP20 45 Pp 3 TA 85 hs for suffix A version mW TA 125 C for suffix C version LOFP32 i 83 Ta 150 C for suffix D version Ambient temperature for suffix A 40 85 version T Ambient temperature for suffix C Maximum power 40 125 version dissipation Ambient temperature for suffix D 40 150 C version Suffix A 40 90 Ty Junction temperature range Suffix C 40 130 Suffix D 40 155 1 Care should be taken when selecting the capacitor due to its tolerance as well as the parameter dependency on temperature DC bias and frequency in addition to other factors The parameter maximum value must be respected for the full application range This frequency of 1 MHz as a condition for VcAp parameters is given by design of internal regulator See Section 10 3 Thermal characteristics DoclD025118 Rev 5 d STM8AF6213 23 23A 26 Electrical characteristics Figure 9 fcpumax Versus Vpp fcpu MHz Functionality 24 not guaranteed in l this area m 12 F nctiojalty guaranteed Ta 40 to 150 C 8 0 i i i 3 0 4 0 5 0 5 5 Supply voltage V MSv37798V1 Table 27 Operating conditions at power up power down Symbol Parameter Conditions Min Typ Max Unit Vpp rise time rate 20 oo typp us V Vpp fall time rate l 2 1 co TEMP Reset release delay Vpp rising 1
54. clD025118 Rev 5 69 106 Electrical characteristics STM8AF6213 23 23A 26 Low speed internal RC oscillator LSI Subject to general operating conditions for Vpp and Ta Table 42 LSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fig Frequency 110 128 150 kHz tsusi LSI oscillator wakeup time 7 US Ibps LSI oscillator power consumption 5 UA 1 Tested in production 9 3 5 Memory characteristics RAM and hardware registers Table 43 RAM and hardware registers Symbol Parameter Conditions Min Unit Vrm Data retention model Halt mode or reset Vit max V 1 Minimum supply voltage without losing the data stored in RAM in halt mode or under reset or in hardware registers only in halt mode Guaranteed by design not tested in production 2 Refer to the operating conditions for the value of Vir may Flash program memory data EEPROM memory General conditions T4 40 to 150 C Table 44 Flash program memory data EEPROM memory Symbol Parameter Conditions Min Typ Max Unit Operating voltage 30 55 y all modes execution write erase fopy is 0 to 16 MHz i y DD Operating voltage with 0 ws 26 55 code execution j 7 j Standard programming time including erase for byte word block 6 0 6 6 bos 1 byte 4 byte 64 byte Fast programming time for 1 block
55. cs EE EE EE EE EE eee 70 Table 43 RAM and hardware registers ie ee EE Ee Ge ee Ge ee en 70 Table 44 Flash program memory data EEPROM memory iis se is eee eee 70 Table 45 Flash program memory iliis hs 71 Table 46 Datamemory ss EE R EE is kinpa eee eee 71 Ly DoclD025118 Rev 5 5 106 List of tables STM8AF6213 23 23A 26 Table 47 Table 48 Table 49 Table 50 Table 51 Table 52 Table 53 Table 54 Table 55 Table 56 Table 57 Table 58 Table 59 Table 60 Table 61 Table 62 Table 63 Table 64 6 106 I O static characteristics llli 72 Output driving current standard ports llis 74 Output driving current true open drain ports eee 74 Output driving current high sink ports ee EE ee ee ee ek ee ee 75 NRST pin characteristics EE EE ccc ete ee ee 79 SPI characteristics A A ai aa s aad a T eee 81 PO characteristics 84 ADC characteristics ie EE EE EE Ee Ee EE ee ee ee ee ee ee ee ee ee ee 86 ADC accuracy with RAIN lt 10 KO Vpp 75V 87 ADC accuracy with RAIN lt 10 KO Vpp 7 3 3 VV Ee eee 87 EMS data nod uua ER Ru EE ia S LR E d Ph AD EE ddan EE 89 ar oe E TE EE N OE N 90 ESD absolute maximum ratings llle 90 Electrical sensitivities llli eh 91 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data 00 0 ees 93 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 m
56. cs General characteristics Subject to general operating conditions for Vpp and T unless otherwise specified All unused pins must be kept at a fixed voltage using the output mode of the I O for example or an external pull up or pull down resistor Table 47 I O static characteristics Symbol Parameter Conditions Min Typ Max Unit ViL Input low level voltage 0 3 V 0 3 x Vpp V Vin Input high level voltage 0 7 x Vpp Vpp 0 3 V Vhys Hysteresis 700 mV Rpu Pull up resistor Vpp 5 V Vin Vss 35 55 80 kQ Fast I Os l 35 2 Load 50 pF Standard and high sink I Os l 1252 a Rise and fall time Load 50 pF fe RF 10 90 Fast I Os m Load 20 pF 20 Standard and high sink I Os 592 Load 20 pF Digital input pad leakage likg Bier put p 9 Vss lt VIN lt Vpp 1 3 UA Vss lt Vins VDD 42509 Analog input pad leakage 40 C lt TA lt 125 C ZA Ikg ana Current Vas Vas Vs l l mU 40 C lt TA lt 150 C Leakage current in ee likgtini pied roz Injection current 4 mA 10 UA 1 Hysteresis voltage between Schmitt trigger switching levels Based on characterization results not tested in production 2 Data based on characterization results not tested in production 3 Guaranteed by design d 72 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics d Figure 19 Typical Vj and Vj vs Vpp 4 temperat
57. cteristics STM8AF6213 23 23A 26 90 106 Electromagnetic interference EMl Based on a simple application running on the product toggling 2 LEDs through the I O ports the product is monitored in terms of emission This emission test is in line with the norm IEC 61967 2 which specifies the board and the loading of each pin Table 58 EMI data Conditions 1 Symbol Parameter Monitored Max fuse fcpu Unit General conditions frequency band 16 MHz 16 MHz 8 MHz 16 MHz VERE V 0 1 MHz to 30 MHz 5 5 Peak level Ta 25 C 30 MHz to 130 MHz 4 5 dBuV SEM LQFP32 package EMI level IEC 61967 2 2 5 2 5 level 1 Data based on characterization results not tested in production Absolute maximum ratings electrical sensitivity Based on three different tests ESD DLU and LU using specific measurement methods the product is stressed to determine its performance in terms of electrical sensitivity For more details refer to the application note AN1181 Electrostatic discharge ESD Electrostatic discharges one positive then one negative pulses separated by 1 second are applied to the pins of each sample according to each pin combination The sample size depends on the number of supply pins in the device 3 parts n 1 supply pin One model can be simulated Human body model This test conforms to the JESD22 A114A A115A standard For more details refer to the application note AN1181
58. ction on Flash EEPROM write protection AFR 7 0 Refer to the following sections for the alternate function remapping descriptions of bits 7 2 and 1 0 respectively OPT3 HSITRIM high speed internal clock trimming register size 0 3 bit trimming supported in CLK_HSITRIMR register 1 4 bit trimming supported in CLK_HSITRIMR register LSI_EN low speed internal clock enable 0 LSI clock is not available as CPU clock source 1 LSI clock is available as CPU clock source IWDG_HW Independent watchdog 0 IWDG independent watchdog activated by software 1 IWDG independent watchdog activated by hardware WWDG HW Window watchdog activation 0 WWDG window watchdog activated by software 1 WWDG window watchdog activated by hardware WWDG HALT Window watchdog reset on Halt 0 No reset generated on Halt if WWDG active 1 Reset generated on Halt if WWDG active 48 106 d DoclD025118 Rev 5 STM8AF6213 23 23A 26 Option bytes 8 2 d Table 15 Option byte description continued Option byte no OPT4 Description EXTCLK External clock selection 0 External crystal connected to OSCIN OSCOUT 1 External clock signal on OSCIN CKAWUSEL Auto wakeup unit clock 0 LSI clock source selected for AWU 1 HSE clock with prescaler selected as clock source for AWU PRSC 1 0 AWU clock prescaler Ox 16 MHz to 128 kHz prescaler 10 8 MHz to 128 kHz prescaler 11 4 MHz to 128 kHz prescaler
59. dvanced control 4 CAPCOM die lt timer TIM1 o gt channels 2 Maid 3 complementary SPI emul outputs E em general purpose de Up to timers TIM5 3 CAPCOM Up to 7 channels gt ADC1 de channels 8 bit basic timer TIM6 1 2 4 kHz beep da Beeper lt es lt gt AWU timer MS38343V1 ky DoclD025118 Rev 5 11 106 Block diagram STM8AF6213 23 23A 26 1 12 106 Legend ADC Analog to digital converter beCAN Controller area network BOR Brownout reset ISC Inter integrated circuit multimaster interface IWDG Independent window watchdog LINUART Local interconnect network universal asynchronous receiver transmitter POR Power on reset SPI Serial peripheral interface SWIM Single wire interface module USART Universal synchronous asynchronous receiver transmitter Window WDG Window watchdog g DoclD025118 Rev 5 STM8AF6213 23 23A 26 Product overview 4 4 1 d Product overview The following section intends to give an overview of the basic features of the products covered by this datasheet For more detailed information on each feature please refer to STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 Central processing unit CPU The 8 bit STM8 core is designed for code efficiency and performance It contains 6 internal registers which are directly add
60. ee 64 Typ Ipp Ruw YS fcpu HSE user external clock Vpp HIV 64 Typ IDD RUN vs VDD HSEI RC osc fepy S1GMHE eiu ERRARE Ue at eae ae RE 65 Typ Ipp wri VS Vpp HSE user external clock fcpy 16 MHz eee 65 Typ Ipp wri VS fcpy HSE user external clock Vpp 25 V ee ee eee 66 Typ IDD WEI vs VDD HSI RC osc fopy N MEE ie AA 66 HSE external clock Source arar arg R ce hh eee 67 HSE oscillator circuit diagram 0 eae 68 Typical Vj and Vjy vs Vpp 4 temperatures 000 000 0000 73 Typical pull up resistance Rpy vs Vpp 4 temperatures 0 00000 eee 73 Typical pull up current lp vs Vpp 4 temperatures a 74 Typ Voi Vpp 5 V standard ports 0 000 002 cee eee eee 75 Typ Vol Vpp 3 3 V standard ports elles 75 Typ V oL Vpp 5 V true open drain ports 0 0 02 Se ee ee 76 Typ V oL Vpp 3 3 V true open drain ports 00 00 0 0000 76 Typ Voi Vpp 5 V high sink ports nanana ee 76 Typ VoL Vpp 3 3 V high sink ports 0 6 ee 71 Typ Vpp Vou Vpp 5 V standard ports unaa TT Typ Vpp Vou Vpp 3 3 V standard portal 0 00 0 0000 000008 TT Typ Vpp Vou Vpp 5 V high sink ports 00 0000 Se dee 78 Typ Vpp Vou Vpp 3 3 V high sink ports 00000000000 78 Typical NRST Vi and Vip vs Vpp 4 temperatures llus 79 Typical NRST pull up resistance vs Vpp 4 temperatures llis sees 80 Typical NRST pu
61. els 0 3 Vpp and 0 7 Vpp d 82 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics Figure 37 SPI timing diagram slave mode and CPHA 1 NSS input l SU NSS 4 gt r tScK 9 th Nss 4 Na qu 2 CPHA 1 i 1 f s CPOL 0 S i i i x 9 CPHA 1 twsckt i I 1 n i T SO br th SO a a CE ily tasso aaa ta SO PE 1 Y a MISO OUTPUT MSOUT OUT BIT6 OUT iso OUT tsu s1 lt gt a th sl M MOSI INPUT MBN O BIT 4 IN LSN O ai14135b 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp Figure 38 SPI timing diagram master model High NSS input LSOK 3 CPHa 0 5 CPOL 0 i 1 l oe E T i u x CPHA 0 t i G CPOL 1 ama Y P y i 1 I IN li bs Vi 1 1 IN a CPHA 1 Y i A 5 CPOL 0 mt O ii i 1 m x CPHA 1 1 n l i 1 i magka PA pita TM SCK tsu mi 1 tw SCKL TT Tr E TEN SCK MISO sin TO INPUT MSBIN IN BITS IN LBN S IN I a thy EE TEE OUTPUT Mar OUT ai14136c 1 Measurement points are at CMOS levels 0 3 Vpp and 0 7 Vpp Ly DoclD025118 Rev 5 83 106 Electrical characteristics STM8AF6213 23 23A 26 9 3 9 84 106 IC interface characteristics Table 53 I C characteristics Standard mode I2C Fast mode I2C Symbol Parameter Unit Min Max Min
62. erforming a reset Window watchdog timer The window watchdog is used to detect the occurrence of a software fault usually generated by external interferences or by unexpected logical conditions which cause the application program to abandon its normal sequence The window function can be used to trim the watchdog behavior to match the application timing perfectly The application software must refresh the counter before time out and during a limited time window A reset is generated in two situations 1 Timeout at 16 MHz CPU clock the time out period can be adjusted between 75 us up to 64 ms 2 Refresh out of window the downcounter is refreshed before its value is lower than the one stored in the window register DoclD025118 Rev 5 17 106 Product overview STM8AF6213 23 23A 26 4 8 4 9 4 10 18 106 Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures It is clocked by the 128 kHz LSI internal RC clock source and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 us to 1 s Auto wakeup counter e Used for auto wakeup from active halt mode e Clock source Internal 128 kHz internal low frequency RC oscillator or external clock e LSI clock can be internally connected to TIM1 input capture channel 1 for calibration Beeper The beeper function outputs a signal on the BEEP pin
63. erved area 5 byte 1 Accessible by debug module only d 44 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Interrupt vector mapping 7 Interrupt vector mapping Table 13 Interrupt mapping Priority e Description edid ONSE e mode Reset Reset Yes Yes 0x00 8000 TRAP Software interrupt 0x00 8004 0 TLI External top level interrupt 0x00 8008 1 AWU Auto wakeup from Halt Yes 0x00 800C 2 oe Clock controller 0x00 8010 3 EXTIO Port A external interrupts Yes Yes 0x00 8014 4 EXTI1 Port B external interrupts Yes Yes 0x00 8018 5 EXTI2 Port C external interrupts Yes Yes 0x00 801C 6 EXTI3 Port D external interrupts Yes Yes 0x00 8020 7 EXTIA Port E external interrupts Yes Yes 0x00 8024 8 EXTI5 Port F 0x00 8028 9 Reserved 0x00 802C 10 ISPI End of transfer Yes Yes 0x00 8030 it jm Mee s MELLE 12 TIM1 TIM1 capture compare 0x00 8038 ta eis uc O O 0x00 8035 14 TIM5 TIM5 capture compare 0x00 8040 15 Reserved 0x00 8044 16 Reserved 0x00 8048 17 LINUART Tx complete 0x00 804C 18 LINUART iu Ed DEE 0x00 8050 19 C I C interrupts Yes Yes 0x00 8054 20 Reserved 0x00 8058 21 Reserved 0x00 805C ADC1 end of 22 ADC1 conversion analog 0x00 8060 watchdog interrupt Ky DoclD025118 Rev 5 45 106 Interrupt vector mapping STM8AF6213 23 23A 26 Table 13 Interrupt map
64. f duplex mode LIN mode Master mode LIN break and delimiter generation LIN break and delimiter detection with separate flag and interrupt source for read back checking Slave mode Autonomous header handling one single interrupt per valid header Mute mode to filter responses Identifier parity error checking LIN automatic resynchronization allowing operation with internal RC oscillator HSI clock source Break detection at any time even during a byte reception Header errors detection Delimiter too short Synch field error Deviation error if automatic resynchronization is enabled Framing error in synch field or identifier field Header time out DoclD025118 Rev 5 21 106 Product overview STM8AF6213 23 23A 26 4 14 2 4 14 3 22 106 Asynchronous communication UART mode s Full duplex communication NRZ standard format mark space e Programmable transmit and receive baud rates up to 1 Mbit s fcpy 16 and capable of following any standard baud rate regardless of the input frequency e Separate enable bits for transmitter and receiver e Tworeceiver wakeup modes A Address bit MSB dle line interrupt e Transmission error detection with interrupt generation e Parity control Synchronous communication e Full duplex synchronous transfers e SPI master operation e 8 bit data communication e Maximum speed 1 Mbit s at 16 MHz fepy 16 Serial peripheral inte
65. fill the external devices reset timing conditions Minimum recommended capacity is 100 nF d DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics 9 3 8 d Figure 35 Recommended reset pin protection Vpp Rpu External reset circuit NRST Filter Internal reset STM8A optional gt 0 1 uF I JE MSv38371V1 SPI serial peripheral interface Unless otherwise specified the parameters given in Table 52 are derived from tests performed under ambient temperature fyAsTER frequency and Vpp supply voltage conditions tMASTER 1 fMASTER Refer to I O port characteristics for more details on the input output alternate function characteristics NSS SCK MOSI MISO Table 52 SPI characteristics Symbol Parameter Conditions Min Max Unit Master mode 0 8 fsck SPI clock frequency MHz Ttcisck Slave mode 0 6 fsck sPI clock rise and fall time CaPacitive load c 25 t SCK C s 30 pF tsunss NSS setup time Slave mode 4 tMASTER trnss NSS hold time Slave mode 70 2 IMGCKH SCK high and low time Master mode tsck 2 15 tsekl2 15 w SCKL t 2 Master mode 5 SuMD o Data input setup time t su S1 Slave mode 5 ns 2 Master mode 7 NUS Data input hold time thsi Slave mode 10 tatso 9 Data output access time Slave mode 3 tMAS
66. haracteristics Symbol Parameter Conditions Min Typ Max Unit f External high speed oscillator l 4 l 16 MHz HSE l frequency Rr Feedback resistor 220 kQ CO ey load l E l 20 pF pacitance C 20 pF 6 startup si 3 HSE oscillator power fosc 16 MHz 1 6 stabilized m DD HSE HSE consumption C 10 pF l 6 startup fosc 16 MHz 1 2 stabilized Om Oscillator transconductance 5 5 mA V 4 Vpp is z tsu HSE Startup time stabilized 1 ms 1 Cis approximately equivalent to 2 x crystal Cj gap The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value Refer to the crystal manufacturer for more details Data based on characterization results not tested in production tsu HSE is the startup time measured from the moment it is enabled by software until a stabilized 16 MHz oscillation is reached The value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer Figure 18 HSE oscillator circuit diagram Rm fuse to core i Lm Co i Rp Cu om mr 6 OSCIN Resonator Current control Resonator C OSCOUT L2 STM8 MSv37799V1 68 106 DocID025118 Rev 5 Ly STM8AF6213 23 23A 26 Electrical characteristics HSE oscillato
67. illimeters inches Symbol Min Typ Max Min Typ Max A 1 200 0 0472 A1 0 050 0 150 0 0020 0 0059 A2 0 800 1 000 1 050 0 0315 0 0394 0 0413 b 0 190 0 300 0 0075 0 0118 c 0 090 0 200 0 0035 0 0079 po 6 400 6 500 6 600 0 2520 0 2559 0 2598 E 6 200 6 400 6 600 0 2441 0 2520 0 2598 E19 4 300 4 400 4 500 0 1693 0 1732 0 1772 e 0 650 0 0256 L 0 450 0 600 0 750 0 0177 0 0236 0 0295 L1 1 000 0 0394 Ky DoclD025118 Rev 5 95 106 Package information STM8AF6213 23 23A 26 Table 62 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package mechanical data continued millimeters inches Symbol Min Typ Max Min Typ Max k 0 8 0 8 aaa 0 100 0 0039 1 Values in inches are converted from mm and rounded to four decimal digits 2 Dimension D does not include mold flash protrusions or gate burrs Mold flash protrusions or gate burrs shall not exceed 0 15mm per side 3 Dimension E1 does not include interlead flash or protrusions Interlead flash or protrusions shall not exceed 0 25mm per side Figure 46 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package footprint 0 25 BR ai 1 d 1 35 r 0 25 7 10 4 40 romana 0 40 0 65 YA_FP_V1 1 Dimensions are expressed in millimeters d 96 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26
68. ing information Figure 48 STM8AF6213 23 23A 26 ordering information scheme Example STM8A F 62 2 3 l P C A U Product class 8 bit automotive microcontroller Program memory type F Flash EEPROM Device family 62 LIN only Program memory size 1 4 Kbyte 2 8 Kbyte Pin count 3 20 pins 6 32 pins HSI accuracy Blank 5 17 396 Package type T LQFP P TSSOP Temperature range A 40 to 85 C C 40 to 125 C D 40 to 150 C Number of ADC analog inputs Blank 5 analog inputs A 7 analog inputs Packing Y Tray U Tube X Tape and reel compliant with EIA 481 C 1 Fora list of available options e g memory size package and orderable part numbers or for further information on any aspect of this device please go to www st com or contact the nearest ST Sales Office 2 Parts marked as ES E or accompanied by an Engineering Sample notification letter are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge In no event ST will be liable for any customer usage of these engineering samples in production ST Quality has to be contacted prior to any decision to use these Engineering Samples to run qualification activity 100 106 DocID025118 Rev 5 Ly STM8AF6213 23 23A 26 STM8 development tools 12 12 1 12 1 1
69. l up during the reset phase and after internal reset release 32 106 DoclD025118 Rev 5 d STM8AF6213 23 23A 26 Pinout and pin description 5 3 g Alternate function remapping As shown in the rightmost column of Table 6 Table 7 and Table 8 some alternate functions can be remapped at different I O ports by programming one of eight AFR alternate function remap option bits Refer to Section 8 Option bytes on page 47 When the remapping option is active the default alternate function is no longer available To use an alternate function the corresponding peripheral must be enabled in the peripheral registers Alternate function remapping does not effect GPIO capabilities of the VO ports see the GPIO section of STM8S series and STM8AF series 8 bit microcontrollers reference manual RM0016 DoclD025118 Rev 5 33 106 Memory and register map STM8AF6213 23 23A 26 6 Memory and register map 6 1 Memory map Figure 6 Memory map 0x00 0000 RAM 1 Kbyte 0x00 03FF 513 byte stack 0x00 0800 0x00 3FFF 0x00 4000 orae 640 byte data EEPROM 0x00 4280 aor Reseved 0x00 4800 WERE 0x00 480A plion bytes 0x00 480B 0x00 4864 0x00 4865 0x00 4870 Pique eA R 0x00 4FFF 0x00 5000 GPIO and peripheral registers 0x00 57FF l EF 0x00 7EFF a 700 CPU SWIM debug ITC registers 0x00 7FFF 0x00 8000 0x00 807F 0x00 8080 32 interrupt vectors Flash program memory 0x00 9FFF 8 Kbyte
70. ll up current vs Vpp 4 temperatures 0 0 00 80 Recommended reset pin protection EE EE EE EE EE ee ee ee ee ee ee 81 SPI timing diagram slave mode and CPHA lt 82 SPI timing diagram slave mode and CPHA 2 1 ii SE ee eee 83 SPI timing diagram master modell EE EO EA AA MEE act 83 Typical application with I2C bus and timing diagram EE EE SE EE EE ese ee 85 ADC accuracy characteristics EE EE Ee EE ee ee ee ee ee ee ee ee ee ee 88 Typical application with ADC 88 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline 92 LQFP32 32 pin 7 x 7 mm low profile quad flat package recommended footprint es 94 LQFP32 marking example package top view 000 eee eee eee 94 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch package outline lisse s I ta iR pA RR RARO RARO de nid 95 TSSOP20 20 lead thin shrink small outline 6 5 x 4 4 mm 0 65 mm pitch DoclD025118 Rev 5 7 106 List of figures STM8AF6213 23 23A 26 package footprint osea oaa taya i R 9 EE EE EE R R E RR TER es 96 Figure 47 TSSOP20 marking example package top view 0c eee ee eee 97 Figure 48 STM8AF6213 23 23A 26 ordering information schemelD ee ee 100 8 106 DoclD025118 Rev 5 ky STM8AF6213 23 23A 26 Introduction 1 g Introduction The datasheet contains the description of STM8AF6213 STM8AF6223 STM8AF6223A and STM8AF6226
71. low level with 4 lio 10 mA Vpp 3 3 V l 1 00 pins sunk lio 20 mA Vop 5 V 1 50 Output high level with B 8 pins sourced ig MA gd ce ies l V 5 1 9 Output high level with lio 10 MA Vpp 3 3 V 2419 E 4 pins sourced lio 20 mA Vop 5 V 3 300 Unit 1 Data based on characterization results not tested in production Figure 22 Typ Vo Vpp 5 V standard ports DoclD025118 Rev 5 75 106 Electrical characteristics STM8AF6213 23 23A 26 Figure 24 Typ Vo Vpp 5 V true open drain ports d 76 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics Figure 27 Typ Vo Vpp 3 3 V high sink ports d DoclD025118 Rev 5 77 106 Electrical characteristics STM8AF6213 23 23A 26 Figure 30 Typ Vpp Vou Vpp 5 V high sink ports d 78 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics 9 3 7 Reset pin characteristics Subject to general operating conditions for Vpp and Ta unless otherwise specified Table 51 NRST pin characteristics Symbol Parameter Conditions Min Typ Max Unit VitNRsT NRST input low level voltage 0 3 0 3 x Vpp ViuNRsT NRST input high level voltage la gt 2 mA 07xVpp Vpp
72. m 0 65 mm pitch package mechanical data n 95 Thermal characteristics EE EE ee ee ee ee ee ee ee ee ee ee ee 98 Document revision history ie e EE eee eae 104 d DoclD025118 Rev 5 STM8AF6213 23 23A 26 List of figures List of figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 Figure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Figure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Ly STM8AF6213 23 23A 26 block diagram liiis 11 Flash memory organization rn 15 STM8AF6213 STM8AF6223 TSSOP20 pinout llle 23 STM8AF6223A TSSOP20 pinout eh 24 STM8AF6226 LQFP32 piNOUt x Re e R RR RRR R RR RRR e eh 29 Memory map x redra erret ens oe CIR ie ap ER AR e Pn Mee ae Wes SEEKER 34 Pin loading conditions R R TR R R R TN RN RI uh 53 PIN input voltage s Z aE rx pene gerat eter t exero qe tere Ga ERR Dal RO e NG 54 T pumax versus VERS n DAAR pete PAIN uote duet i ser ade De du Leite ids 57 External capacitor CEXT lt e 58 Typ Ipp Ruw VS Vpp HSE user external clock fepy 16 MHz 2 eee
73. mentary control register 2 OxFF 0x00 505D Flash FLASH_FPR Flash protection register 0x00 0x00 505E FLASH NFPR Flash complementary protection register OxFF 0x00 505F FLASH IAPSR Flash in application programming status 0x40 register 0x00 5060 to 0x00 5061 Reserved area 2 byte 0x00 5062 Flash FLASH PUKR Flash Program memory unprotection 0x00 register 0x00 5063 Reserved area 1 byte 0x00 5064 Flash FLASH_DUKR Data EEPROM unprotection register 0x00 0x00 5065 to 0x00 509F Reserved area 59 byte 0x00 50A0 EXTI_CR1 External interrupt control register 1 0x00 ITC 0x00 50A1 EXTI CR2 External interrupt control register 2 0x00 0x00 50A2 to 0x00 50B2 Reserved area 17 byte DoclD025118 Rev 5 Ly STM8AF6213 23 23A 26 Memory and register map g Table 11 General hardware register map continued Address Block Register label Register name ea 0x00 50B3 RST RST_SR Reset status register 0xxx pen maps Reserved area 12 byte 0x00 50CO CLK ICKR Internal clock control register 0x01 0x00 50C1 zd CLK ECKR External clock control register 0x00 0x00 50C2 Reserved area 1 byte 0x00 50C3 CLK CMSR Clock master status register OxE1 0x00 50C4 CLK SWR Clock master switch register OxE1 0x00 50C5 CLK SWCR Clock switch control register OxXX 0x00 50C6 CLK
74. ode executed fcpu fMaster 128 HSI RC osc 16 MHz 8 0 46 0 58 from Flash 15 625 kHz a fopu fMASTER 128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Tested in production 2 Default clock configuration measured with all peripherals off Table 29 Total current consumption with code execution in run mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 8 fcpu fmastER 716 MHz HSE user ext clock 16 MHz 2 2 3 HSI RC osc 16 MHz 1 5 2 Supply current in run mode n HSE user ext clock 16 MHz 0 81 code executed CPU IMASTER Z from RAM HSI RC osc 16 MHz 0 7 0 87 fopu fMaster 128 HSI RC osc 16 MHz 8 0 46 0 58 15 625 kHz i fopy faster 7128 kHz LSI RC osc 128 kHz 0 41 0 55 IDD RUN mA HSE crystal osc 16 MHz 4 fopu fuasrER 16 MHz HSE user ext clock 16 MHz 3 9 4 7 HSI RC osc 16 MHz 3 7 4 5 Supply current in run mode fcpy fyasTER 2 MHz HSI RC osc 16 MHZz 8 0 84 1 05 code executed from Flash fopu fuasTER 128 125 kHz HSI RC osc 16 MHz 0 72 0 9 fopu fmaster 128 HSI RC osc 16 MHz 8 0 46 0 58 15 625 kHz i fcpu fMASTER 7128 kHz LSI RC osc 128 kHz 0 42 0 57 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off d DoclD025118 Rev 5 59 106 Electrical characteristics STM8AF6213 23 23A 26 To
75. open drain OD open drain PP push pull Bold X pin state after internal reset release Reset state Unless otherwise specified the pin state is the same during the reset phase and after the internal reset release TSSOP20 pinouts and pin descriptions Figure 3 STM8AF6213 STM8AF6223 TSSOP20 pinout H PD3 HS AIN4 TIM5 CH2 ADC ETR H PD2 HSVAINS TIM5 CH3 H PD1 HS SWIM H PC7 HS SPI MISO TIM1 CH2 H PC6 HS SPI MOSI TIM1 CH1 H PC5 HS SPI SCK TIM5 CH1 LINUART CK TIM5 CH1 BEEP HS PD4 H O AINS LINUART TX HS PD5 AING LINUART RX HS PD6 NRST OSCIN PA1 OSCOUT PA2 VSS PC4 HS TIM1_CH4 CLK_CCO AIN2 TIM1_CH2N VCAP H PC3 HS TIM1 CH3 TLIJ TIM1_CH1N VDD PB4 T I2C SCL ADC ETR SPI NSS TIM5 CH3 HS PA3 D 10 PB5 T I2C SDA TIM1 BKIN MS38345V1 HS high sink capability T true open drain P buffer and protection diode to Vpp not implemented alternate function remapping option if the same alternate function is shown twice it indicates an exclusive choice not a duplication of the function DoclD025118 Rev 5 23 106 Pinout and pin description STM8AF6213 23 23A 26 Figure 4 STM8AF6223A TSSOP20 pinout LINUART CK TIM5 CH1 BEEP HS PD4 1 O AINS LINUART TX HS PD5 AING LINUART RX HS PD6 PD3 HS AIN4 TIM5 CH2 ADC ETR PD2 HS AIN3 TIM5 CH3 PD1 HS SWIM NRST PC7 HS SPI_MISO TIM1_CH2 OSCIN PA1 PC6
76. ory access security system MASS is always enabled and protects the main Flash program memory data EEPROM and option byte To perform in application programming IAP this write protection can be removed by writing a MASS key sequence in a control register This allows the application to write to data EEPROM modify the contents of main program memory or the device option byte A second level of write protection can be enabled to further protect a specific area of memory known as UBC user boot code Refer to the figure below DocID025118 Rev 5 Ly STM8AF6213 23 23A 26 Product overview 4 4 2 d The size of the UBC is programmable through the UBC option byte in increments of 1 page 64 byte block by programming the UBC option byte in ICP mode This divides the program memory into two areas e Main program memory up to 8 Kbyte minus UBC e User specific boot code UBC configurable up to 8 Kbyte The UBC area remains write protected during in application programming This means that the MASS keys do not unlock the UBC area It protects the memory used to store the boot program specific code libraries reset and interrupt vectors the reset routine and usually the IAP and communication routines Figure 2 Flash memory organization Data Data memory area 640 byte EEPROM memory Option bytes Programmable area UBC area from 64 byte 1 page Remains write protected during IAP to up to 8 Kbyte
77. ping continued Priorit Source Dascriptiah Wakeup from esser i Interrupt vector y block P halt mode address mode TIM6 29 MG update overflow trigger O O 9x90 8964 24 Flash EOP WR PG DIS 0x00 8068 1 Except PA1 g 46 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Option bytes 8 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device Except for the ROP read out protection byte each option byte has to be stored twice in a regular form OPTx and a complemented one NOPTx for redundancy Option bytes can be modified in ICP mode via SWIM by accessing the EEPROM address shown in Table 14 Option bytes below Option bytes can also be modified on the fly by the application in IAP mode except the ROP and UBC options that can only be modified in ICP mode via SWIM Refer to the STM8 Flash programming manual PM0051 and STM8 SWIM communication protocol and debug module user manual UM0470 for information on SWIM programming procedures Table 14 Option bytes s Option bits Factory Option Option Addr salas c din default Xeno x 6 5 4 3 2 1 0 setting Read out E protection OPTO ROP 7 0 0x00 ROP vor OPT1 UBC 7 0 0x00 User boot code UBC po NOPT1 NUBC 7 0 OxFF p Alternate OPT2 AFR7 AFR6 AFR5 AF
78. ption in the same port 2 Referto the pin description DoclD025118 Rev 5 49 106 Option bytes STM8AF6213 23 23A 26 50 106 Table 17 STM8AF6213 and STM8AF6223 alternate function remapping bits 7 2 for 20 pin packages Option byte number OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive default alternate function 2 1 Port C3 alternate function TIM1_CH1N port C4 alternate function TIM1 CH2N AFR6 Alternate function remapping option 6 Reserved AFR5 Alternate function remapping option 5 Reserved AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive default alternate function 2 1 Port B4 alternate function ADC_ETR port B5 alternate function TIM1 BKIN AFR3 Alternate function remapping option 3 0 AFR3 remapping option inactive default alternate function 2 1 Port C3 alternate function TLI AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive default alternate function 2 1 Port D4 alternate function LINUART CK 1 Do not use more than one remapping option in the same port 2 Referto the pin description Table 18 STM8AF6223A alternate function remapping bits 7 2 for 20 pin packages Option byte number OPT2 Description AFR7 Alternate function remapping option 7 0 AFR7 remapping option inactive default alternate function 2 1 Port C4 al
79. r critical du formula The crystal characteristics have to be checked with the following formula Im Imcrit where 9ncrit can be calculated with the crystal parameters as follows Imorit 2 x Ix HSE xR 2Co C Rm Notional resistance see crystal specification Lm Notional inductance see crystal specification Cm Notional capacitance see crystal specification Co Shunt capacitance see crystal specification C 4 Cj C Grounded external capacitance 9 3 4 Internal clock sources and timing characteristics Subject to general operating conditions for Vpp and Ta High speed internal RC oscillator HSI Table 41 HSI oscillator characteristics Symbol Parameter Conditions Min Typ Max Unit fus Frequency 16 MHz i icati 40 7 1 HSI oscillator user Trimmed by the application 1 1 trimming accurac for any Von and TA 1 1 9 y conditions 0 5 E 0 5 ACCus 3 0V lt Vpp x 5 5 V 5 5 HSI oscillator accuracy 740 Cs Tas 150 C factory calibrated 3 0V Vpp 5 5 V 32 l 32 40 C lt Ta lt 125 C HSI oscillator wakeup 3 tsu HSI time 2 US HSI oscillator power 4 IDD HSI consumption 7 7 Qa pa 1 Depending on option byte setting OPT3 and NOPT3 2 These values are guaranteed for STM8AF62xxIxx order codes only 3 Guaranteed by characterization not tested in production 4 Data based on characterization results not tested in production Ly Do
80. racy vs negative injection current Injecting negative current on any of the analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input It is recommended to add a Schottky diode pin to ground to standard analog pins which may potentially inject negative current Any positive injection current within the limits specified for lj piv and 2 IINJ PIN in the I O port pin characteristics section does not affect the ADC accuracy 5 When several inputs are submitted to a current injection the maximum IINJ PIN is the absolute sum of the positive and negative injected currents instantaneous values These results are based on characterization with X IINJ PIN maximum current injection on four I O port pins of the device Table 24 Thermal characteristics Symbol Ratings Value Unit TsrG Storage temperature range 65 to 150 C Ty Maximum junction temperature 150 Table 25 Operating lifetime OLF Symbol Ratings Value Unit OLF Conforming to AEC Q100 40 to 150 C DoclD025118 Rev 5 55 106 Electrical characteristics STM8AF6213 23 23A 26 9 3 56 106 Operating conditions Table 26 General operating conditions Symbol Parameter Conditions Min Max Unit fepu Internal CPU clock frequency x 0 16 MHz VpD Standard operating voltage S 3 0 5 5 V Cext capacitance of external l 470 3300 nF
81. rals are disabled clock stopped by peripheral clock gating registers except if explicitly mentioned Subject to general operating conditions for Vpp and Ta Unless otherwise specified data are based on characterization results and not tested in production Table 28 Total current consumption with code execution in run mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 2 3 fcpu fuasrER 16 MHz HSE user ext clock 16 MHz 2 2 35 Supply current HSI RC osc 16 MHz 17 20 IDD RUN NEU feu hinad ge 125 kHz HSE user ext clock 16 MHz 0 86 ma from RAM HSI RC osc 16 MHz 0 7 0 87 feru aeres 129 HSI RC osc 16 MHz 8 0 46 0 58 fopy fMASTER 28 kHz LSI RC osc 128 kHz 0 41 0 55 d 58 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics Table 28 Total current consumption with code execution in run mode at Vpp 5 V continued Symbol Parameter Conditions Typ Max Unit Supply current HSE crystal osc 16 MHz 4 5 in run mode E codeexecuted fopu fmaster 16 MHz HSE user ext clock 16 MHz 4 3 4 75 from Flash HSI RC osc 16 MHz 3 7 450 fesu fmaster 2 MHz HSI RC osc 16 MHz 8 0 84 20 IDD RUN mA Supply current fou fmasteR 128 125 kHz HSI RC osc 16 MHz 0 72 0 9 in run mode c
82. re interface module together with an integrated debug module permit non intrusive real time in circuit debugging and fast memory programming SWIM Single wire interface module for direct access to the debug mode and memory programming The interface can be activated in all device operation modes The maximum data transmission speed is 145 byte ms Debug module The non intrusive debugging module features a performance close to a full featured emulator Besides memory and peripheral operation CPU operation can also be monitored in real time by means of shadow registers s R W to RAM and peripheral registers in real time e R W access to all resources by stalling the CPU e Breakpoints on all program memory instructions software breakpoints e Two advanced breakpoints 23 predefined breakpoint configurations Interrupt controller e Nested interrupts with three software priority levels e 32 interrupt vectors with hardware priority e Upto 28 external interrupts on 7 vectors including TLI e Trap and reset interrupts Flash program and data EEPROM memory e Up to 8 Kbyte of Flash program single voltage Flash memory e 640 byte true data EEPROM e User option byte area Write protection WP Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction There are two levels of write protection The first level is known as MASS mem
83. rent consumption in active halt mode Table 32 Total current consumption in active halt mode at Vpp 5 V Conditions Max Max Symbol Parameter Main Typ at at Maxat Unit voltage Flash D on 150 C 2 Clock source 85 C 125 C regulator mode MVR HSE crystal 1030 Operating 0S 16 MHz mode LSI RC osc 128 kHz 200 260 300 On HSE crystal 970 Supply current in Power down 08c 16 MHz A DD H active halt mode mode LSI RE osc H 128 kHz 150 200 230 Operating LSI RC osc mede 128 kHz 66 85 140 200 ci P d LSI RC ower down osc mode 128 kHz n 20 40 O 1 Configured by the REGAH bit in the CLK ICKR register 2 Configured by the AHALT bit in the FLASH CR1 register Table 33 Total current consumption in active halt mode at Vpp 3 3 V Conditions Main Max at Max at Symbol Parameter voltage Flash Typ 85 c 1 125 C Unit regulato 3 Clock source c mode MVR 2 HSE crystal 550 Operating 0Sc 16 MHz mode LSI RC osc 128 kHz 200 260 290 On HSE crystal 970 Supply current in Power osc 16 MHz X DD AH active halt mode down mode SI RC osc H 128 kHz 150 200 230 Operating LSI RC osc mode 128 kHz PO ga 19s P LSI RC ower osc down mode 128 kHz 10 LS 3 1 Data based on characterization results not tested in production 2 Configured by the REGAH bit in
84. ressable in each execution context 20 addressing modes including indexed indirect and relative addressing and 80 instructions Architecture and registers e Harvard architecture e 3 stage pipeline e 32 bit wide program memory bus single cycle fetching for most instructions e XandY 16 bit index registers enabling indexed addressing modes with or without offset and read modify write type data manipulations e 8 bit accumulator e 24 bit program counter 16 Mbyte linear memory space e 16 bit stack pointer access to a 64 Kbyte level stack e 8 bit condition code register 7 condition flags for the result of the last instruction Addressing e 20addressing modes e Indexed indirect addressing mode for look up tables located anywhere in the address space e Stack pointer relative addressing mode for local variables and parameter passing Instruction set e 80 instructions with 2 byte average instruction size e Standard data movement and logic arithmetic functions e 8 bit by 8 bit multiplication e 16 bit by 8 bit and 16 bit by 16 bit division e Bit manipulation e Data transfer between stack and accumulator push pop with direct stack access e Data transfer using the X and Y registers or direct memory to memory transfers DoclD025118 Rev 5 13 106 Product overview STM8AF6213 23 23A 26 4 2 4 2 1 4 2 2 4 3 4 4 4 4 1 14 106 Single wire interface module SWIM and debug module DM The single wi
85. rface SPI e Maximum speed 8 Mbit s fuasrER 2 both for master and slave e Full duplex synchronous transfers e Simplex synchronous transfers on two lines with a possible bidirectional data line s Master or slave operation selectable by hardware or software e CRC calculation e 1 byte Tx and Rx buffer e Slave master selection input pin Inter integrated circuit I2C interface s lC master features Clock generation Start and stop generation e 2C slave features Programmable IZC address detection Stop bit detection e Generation and detection of 7 bit 10 bit addressing and general call e Supports different communication speeds Standard speed up to 100 kHz A Fast speed up to 400 kHz d DoclD025118 Rev 5 STM8AF6213 23 23A 26 Pinout and pin description 5 5 1 d Pinout and pin description The following table presents the meaning of the abbreviations in use in the pin description tables in this section Table 5 Legend abbreviations for pinout tables Type l input O output S power supply Level Input CM CMOS standard for all I Os Output HS High sink Output speed O1 Slow up to 2 MHz O2 Fast up to 10 MHz 03 Fast slow programmability with slow as default state after reset OA Fast slow programmability with fast as default state after reset Port and control Input float floating wpu weak pull up configuration Output T true
86. rt D data output latch register 0x00 0x00 5010 PD IDR Port D input pin value register OO 0x00 5011 Port D PD DDR Port D data direction register 0x00 0x00 5012 PD CR1 Port D control register 1 0x02 0x00 5013 PD CR2 Port D control register 2 0x00 Ky DoclD025118 Rev 5 35 106 Memory and register map STM8AF6213 23 23A 26 Table 10 VO port hardware register map continued Address Block Register label Register name Heel status 0x00 5014 PE ODR Port E data output latch register 0x00 0x00 5015 PE_IDR Port E input pin value register oxxx 0x00 5016 Port E PE DDR Port E data direction register 0x00 0x00 5017 PE CR1 Port E control register 1 0x00 0x00 5018 PE CR2 Port E control register 2 0x00 0x00 5019 PF ODR Port F data output latch register 0x00 0x00 501A PF IDR Port F input pin value register Oxxx 0x00 501B Port F PF DDR Port F data direction register 0x00 0x00 501C PF CR1 Port F control register 1 0x00 0x00 501D PF CR2 Port F control register 2 0x00 1 Depends on the external circuitry Table 11 General hardware register map Address Block Register label Register name neset status 0x00 501E to 0x00 5069 Reserved area 60 byte 0x00 505A FLASH_CR1 Flash control register 1 0x00 0x00 505B FLASH_CR2 Flash control register 2 0x00 0x00 505C FLASH_NCR2 Flash comple
87. shold register high OxFF 0x00 5409 ADC HTRL ADC high threshold register low 0x03 0x00 540A ADC LTRH ADC low threshold register high 0x00 0x00 540B ADC LTRL ADC low threshold register low 0x00 0x00 540C ADC AWSRH ADC watchdog status register high 0x00 0x00 540D ADC_AWSRL ADC watchdog status register low 0x00 0x00 540E ADC _AWCRH ADC watchdog control register high 0x00 0x00 540F ADC AWCRL ADC watchdog control register low 0x00 papa Reserved area 1008 byte g STM8AF6213 23 23A 26 Memory and register map 6 2 2 CPU SWIM debug module interrupt controller registers Table 12 CPU SWIM debug module interrupt controller registers Address Block Register label Register name daa 0x00 7F00 A Accumulator 0x00 0x00 7F01 PCE Program counter extended 0x00 0x00 7F02 PCH Program counter high 0x00 0x00 7F03 PCL Program counter low 0x00 0x00 7F04 XH X index register high 0x00 0x00 7F05 CPU XL X index register low 0x00 0x00 7F06 YH Y index register high 0x00 0x00 7F07 YL Y index register low 0x00 0x00 7F08 SPH Stack pointer high 0x03 0x00 7F09 SPL Stack pointer low OxFF 0x00 7F0A CCR Condition code register 0x28 ped is Reserved area 85 byte 0x00 7F60 CPU CFG GCR Global configuration register 0x00 0x00 7F70 ITC SPR1 Interrupt software priority register 1 OxFF 0x00 7F71 ITC_SPR2 Interrupt software priority register
88. standard DoclD025118 Rev 5 91 106 Package information STM8AF6213 23 23A 26 10 10 1 92 106 Package information In order to meet environmental requirements ST offers these devices in different grades of ECOPACK packages depending on their level of environmental compliance ECOPACK specifications grade definitions and product status are available at www st com ECOPACK is an ST trademark LQFP32 package information Figure 42 LQFP32 32 pin 7 x 7 mm low profile quad flat package outline SEATING PLANE E LUIT AG 0 25 mm GAUGE PLANE RES 5V ME V2 1 Drawing is not to scale a DoclD025118 Rev 5 STM8AF6213 23 23A 26 Package information g Table 61 LQFP32 32 pin 7 x 7 mm low profile quad flat package mechanical data millimeters inches Symbol Min Typ Max Min Typ Max A 1 600 0 0630 A1 0 050 0 150 0 0020 0 0059 A2 1 350 1 400 1 450 0 0531 0 0551 0 0571 b 0 300 0 370 0 450 0 0118 0 0146 0 0177 0 090 0 200 0 0035 0 0079 D 8 800 9 000 9 200 0 3465 0 3543 0 3622 D1 6 800 7 000 7 200 0 2677 0 2756 0 2835 D3 5 600 0 2205 E 8 800 9 000 9 200 0 3465 0 3543 0 3622 E1 6 800 7 000 7 200 0 2677 0 2756 0 2835 E3 5 600 0 2205 e 0 800 0 0315
89. ster 1 Ox00 0x00 5233 UART4_BRR2 LINUART baud rate register 2 0x00 0x00 5234 UART4_CR1 LINUART control register 1 0x00 0x00 5235 NART UART4_CR2 LINUART control register 2 0x00 0x00 5236 UART4_CR3 LINUART control register 3 0x00 0x00 5237 UART4_CR4 LINUART control register 4 0x00 0x00 5238 Reserved 0x00 5239 UART4_CR6 LINUART control register 6 0x00 0x00 523A UART4_GTR LINUART guard time register 0x00 0x00 523B UART4_PSCR LINUART prescaler 0x00 pus pun Reserved area 20 byte Ky DoclD025118 Rev 5 39 106 Memory and register map STM8AF6213 23 23A 26 40 106 Table 11 General hardware register map continued Address Block Register label Register name aae 0x00 5250 TIM1_CR1 TIM1 control register 1 0x00 0x00 5251 TIM1_CR2 TIM1 control register 2 0x00 0x00 5252 TIM1_SMCR TIM1 slave mode control register 0x00 0x00 5253 TIM1 ETR TIM1 external trigger register 0x00 0x00 5254 TIM1 IER TIM1 Interrupt enable register 0x00 0x00 5255 TIM1 SR1 TIM1 status register 1 0x00 0x00 5256 TIM1 SR2 TIM1 status register 2 0x00 0x00 5257 TIM1 EGR TIM1 event generation register 0x00 0x00 5258 TIM1 CCMR1 TIM1 capture compare mode register 1 0x00 0x00 5259 TIM1 CCMR2 TIM1 capture compare mode register 2 0x00 0x00 525A TIM1 CCMR3 TIM1 capture compare mode register 3 0x00 0
90. stics EE EE EE EE ee ee ee tees 55 Table 25 Operating lifetime OLF ei EE EG ee RR I en 55 Table 26 General operating conditions EE EE EE Ee ee Ee ee ee eh 56 Table 27 Operating conditions at power up power down EE EE EE EE EE cece eee eee 57 Table 28 Total current consumption with code execution in run mode at Vpp 2 5 V 58 Table 29 Total current consumption with code execution in run mode at Vpp 3 3V 59 Table 30 Total current consumption in wait mode at Vpp 2 5 VY SS Se eee 60 Table 31 Total current consumption in wait mode at Vpp 2 3 3 V SE Se SS ed se ee 60 Table 32 Total current consumption in active halt mode at Vpp 2 BV AA 61 Table 33 Total current consumption in active halt mode at Vpp 2 3 3V EE Ee ee 61 Table 34 Total current consumption in halt mode at Vpp SE SV SEE ES EE eee 62 Table 35 Total current consumption in halt mode at Vpp 2 3 3 V EE ES eds ee 62 Table 36 WakeuptimeS EE SS SS rrr 62 Table 37 Total current consumption and timing in forced reset state 63 Table 38 Peripheral current consumption ies EE EE EE eee eee eee eee 63 Table 39 HSE user external clock characteristics EE EE se ee EE ee eee eee 67 Table 40 HSE oscillator characteristics iis EE 000 cece ee ee ee ee ee ee ee 68 Table 41 HSI oscillator characteristics EE EE EE EE Se se eee 69 Table 42 LSI oscillator characteristi
91. tal current consumption in wait mode Unless otherwise specified data based are on characterization results and not tested in production Table 30 Total current consumption in wait mode at Vpp 5 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 6 fCPU TMASTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 50 Supply current IDDWFI in wait mode fcPu fiuasrER 128 125 kHz HSI RC osc 16 MHz 0 7 0 88 MA fopy IMASTER Los HSI RC osc 16 MHz 8 2 0 45 0 57 fopu fuasrER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Tested in production 2 Default clock configuration measured with all peripherals off Table 31 Total current consumption in wait mode at Vpp 3 3 V Symbol Parameter Conditions Typ Max Unit HSE crystal osc 16 MHz 1 1 fcpu TMASTER 16 MHz HSE user ext clock 16 MHz 1 1 1 3 HSI RC osc 16 MHz 0 89 1 1 Supply current IDDWFI in wait mode fcpu fuasrER 128 125 kHz HSI RC osc 16 MHz 0 7 0 88 MA fepu MASTER denm HSI RC osc 16 MHz 8 2 0 45 0 57 fopu fuasrER 128 kHz LSI RC osc 128 kHz 0 4 0 54 1 Data based on characterization results not tested in production 2 Default clock configuration measured with all peripherals off d 60 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics Total cur
92. ternate function TIM1_CH2N AFR6 Alternate function remapping option 6 Reserved AFR5 Alternate function remapping option 5 Reserved AFR4 Alternate function remapping option 4 0 AFR4 remapping option inactive default alternate function 2 1 Port B4 alternate function ADC_ETR port B5 alternate function TIM1 BKIN AFR3 Alternate function remapping option 3 Reserved AFR2 Alternate function remapping option 2 0 AFR2 remapping option inactive default alternate function 2 1 Port D4 alternate function LINUART CK 1 Do not use more than one remapping option in the same port 2 Refer to the pin description d DoclD025118 Rev 5 STM8AF6213 23 23A 26 Option bytes d Table 19 STM8AF6226 alternate function remapping bits 1 0 for 32 pin packages AFR1 option bit value AFRO option bit value VO port ee 0 0 AFR1 and AFRO remapping options inactive Default alternate functions PC5 TIM5_CH1 0 1 PC6 TIM1_CH1 PC7 TIM1_CH2 PA3 SPI NSS j PD2 TIM5_CH3 PD2 TIM5_CH3 PC5 TIM5_CH1 PC6 TIM1_CH1 PC7 TIM1_CH2 19 12 PC2 TIM1_CH3N PC1 TIM1_CH2N PE5 TIM1 CHIN PA3 LINUART TX PF4 LINUART RX Refer to the pin descriptions If both AFR1 and AFRO option bits are set the SPI hardware NSS management feature is no more available If this remapping option is selected and the SPI is enabled the SSM bit must be configured in the SPI_CR2 register
93. terrupt control register 0x00 0x00 5203 SPI SR SPI status register 0x02 0x00 5204 9 SPI DR SPI data register 0x00 0x00 5205 SPI CRCPR SPI CRC polynomial register 0x07 0x00 5206 SPI RXCRCR SPI Rx CRC register OxFF 0x00 5207 SPI TXCRCR SPI Tx CRC register OxFF por Lr Reserved area 8 byte 0x00 5210 I2C_CR1 I2C control register 1 0x00 0x00 5211 I2C CR2 I2C control register 2 0x00 0x00 5212 I2C FREQR I2C frequency register 0x00 0x00 5213 I2C OARL I2C own address register low 0x00 0x00 5214 I2C_OARH I2C own address register high 0x00 0x00 5215 Reserved area 1 byte 0x00 5216 I2C DR I2C data register 0x00 0x00 5217 I2C I2C SR1 I2C status register 1 0x00 0x00 5218 I2C SR2 I2C status register 2 0x00 0x00 5219 I2C SR3 I2C status register 3 0x00 0x00 521A I2C ITR I2C interrupt control register 0x00 0x00 521B I2C CCRL I2C clock control register low 0x00 0x00 521C I2C_CCRH I2C clock control register high 0x00 0x00 521D I2C_TRISER I2C TRISE register 0x02 0x00 521E I2C PECR I2C packet error checking register 0x00 p GHE Reserved area 17 byte 38 106 DoclD025118 Rev 5 g STM8AF6213 23 23A 26 Memory and register map Table 11 General hardware register map continued Address Block Register label Register name _ 0x00 5230 UART4_SR LINUART status register 0xCO 0x00 5231 UART4 DR LINUART data register OxXX 0x00 5232 UART4 BRR1 LINUART baud rate regi
94. tial lnn measurement between reset configuration and timer counter running at 16 MHz No IC OC programmed no I O pads toggling Not tested in production 2 Data based on a differential lnn measurement between the on chip peripheral when kept under reset and not clocked and the on chip peripheral when clocked and not kept under reset No I O pads toggling Not tested in production 3 Data based on a differential lnn measurement between reset configuration and continuous A D conversions Not tested in production d DoclD025118 Rev 5 63 106 Electrical characteristics STM8AF6213 23 23A 26 Current consumption curves The following figures show typical current consumption measured with code executing in RAM Figure 11 Typ Ipp Run VS Vpp HSE user external clock fcpy 16 MHz 205 IDO run HSE ma uw a iiid KA t IDD run HSE ma Fou MHz d 64 106 DoclD025118 Rev 5 STM8AF6213 23 23A 26 Electrical characteristics Figure 13 Typ IDD RUN VS Vpp HSEI RC OSC fcpu 16 MHz IDD run HSI ma DD WFIHSE mA d DoclD025118 Rev 5 65 106 Electrical characteristics STM8AF6213 23 23A 26 Figure 15 Typ Ipp wri VS fcpu HSE user external clock Vpp 5 V DD WEI HSE ma Fcru MHz Figure 16 Typ Ipp wr vs Vpp HSI RC OSC fcPu 16 MHz IDD WFI HS ma Feeu MHz
95. tion WP RII 14 4 4 2 Read out protection ROP 0 0 cee eee 15 4 5 Clock controller 00 cece een 16 4 5 1 Features eise eta E A a MER H a C deb nare a a ek ee BAN 16 4 6 Power management uem a Ke RR RR hos KERE REED eaves nea 17 4 7 Watchdog timers siasa Race rb og redo rii de AUS de upon raid deam 17 4 8 Auto wakeup counter 00 ccna 18 4 9 Beeper R s 18 4 10 TIM1 16 bit advanced control timer llle 18 4 11 TIM5 16 bit general purpose timer llis 19 4 12 TIM6 8 bitbasictimer Ee ee ee ee ee 19 4 13 Analog to digital converter ADC1 EE EE eee 20 4 14 Communication interfaces ee es 20 4 14 4 LINUART EE EE EE res 21 4 14 2 Serial peripheral interface SPI 0 00 22 4 14 3 Inter integrated circuit Fo interface ii EE EE EER eee 22 2 106 DoclD025118 Rev 5 Ky STM8AF6213 23 23A 26 Contents g Pinout and pin description e e e e cee ee 23 5 1 TSSOP20 pinouts and pin descriptions Se se 23 5 2 LQFP32 pinout and pin description l l 29 5 3 Alternate function remapping 00 ER eee eee 33 Memory and register map 2 22 0c ER eee eee eee 34 6 1 Memory map ss e e s s e e e R aban eee en DEE eevee DAE E X ARR GR ER A 34 6 2 lez den trace CPP 35 6 2 1 VO port hardware register map 000 eee 35 6 2 2 CPU SWIM debug module interrupt controller registers
96. tronics featuring e Seamless integration of C and ASM toolsets e Full featured debugger e Project management e Syntax highlighting editor e Integrated programming interface e Support of advanced emulation features for STice such as code profiling and coverage ST visual programmer STVP Easy to use unlimited graphical interface allowing read write and verify of your STM8 microcontroller Flash program memory data EEPROM and option bytes STVP also offers project mode for saving programming configurations and automating programming sequences C and assembly toolchains Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment making it possible to configure and control the building of the application directly from an easy to use graphical interface Available toolchains include Cosmic C compiler for STM8 All compilers are available in free version with a limited code size depending on the compiler For more information refer to www cosmic software com www raisonance com and www iar com STM8 assembler linker Free assembly toolchain included in the STM8 toolset which allows the users to assemble and link your application source code g DoclD025118 Rev 5 STM8AF6213 23 23A 26 STM8 development tools 12 3 Programming tools During the development cycle STice provides in circuit programming of the STM8 Flash microcontroller on the user application board
97. ures VIL VIH V 25 3 3 5 4 45 5 55 6 v M Figure 20 Typical pull up resistance Rpy vs Vpp 4 temperatures Pul up resistance k DoclD025118 Rev 5 73 106 Electrical characteristics STM8AF6213 23 23A 26 74 106 Figure 21 Typical pull up current lj vs Vpp 4 temperatures Pul up current pa Table 48 Output driving current standard ports Symbol Parameter Conditions Min Max Unit Output low level with 8 lo 10 mA 20 pins sunk Vpp25V VoL Output low level with 4 lig 4 mA 4000 pins sunk Vpp 3 3 V V Output high level with 8 lo 10 mA 28 7 pins sourced Vpp 25V i OH Output high level with 4 llo 4 mA 240 l pins sourced Vpp 3 3 V i 1 Data based on characterization results not tested in production Table 49 Output driving current true open drain ports Symbol Parameter Conditions Max Unit los 10 mA Vpp 25V 1 0 Vo Output low level with 2 pins sunk ljg 10 MA Vpp 3 3 V 1 5 0 V lo 20 mA Vpp 2 5 V 2 0 1 Data based on characterization results not tested in production DoclD025118 Rev 5 d STM8AF6213 23 23A 26 Electrical characteristics d Table 50 Output driving current high sink ports Symbol Parameter Conditions Min Max Output low level with 8 _ _ pins sunk llo 10 mA Vpp 5V 0 8 V 1 e Output
98. usly for high current source sink must be uniformly spaced around the package In addition the total driven current must respect the absolute maximum ratings see Section Absolute maximum ratings 2 When the MCU is in Halt Active halt mode PA1 is automatically configured in input weak pull up and cannot be used for waking up the device In this mode the output state of PA1 is not driven It is recommended to use PA1 only in input mode if Halt Active halt is used in the application 3 In the open drain output column T defines a true open drain I O P buffer weak pull up and protection diode to VDD are not implemented 4 The PD1 pin is in input pull up during the reset phase and after internal reset release 28 106 DoclD025118 Rev 5 d STM8AF6213 23 23A 26 Pinout and pin description 5 2 LQFP32 pinout and pin description Figure 5 STM8AF6226 LQFP32 pinout HS high sink capability OSCOUT PA2 LINUART_TX SPI_NSS TIM5 CH3 HS PA3 LINUART RX PF4 NRST OSCIN PA1 VSS VCAP VDD H oe OQ EG M LINUART_CK AIN4 TIM5_CH2 ADC_ETR CLK CCO AINS LINUART TX BEEP TIM5 CH1 AING LINUART RX TIM1_BKIN TLI TIM1 CH4 FRR RRR PD7 PD6 PD5 PD4 PD3 PD2 O PDO 323130292827 2625 e 2 EN o a EN N s w FS a a o PB3 PB1 PBOF
99. uture ST microcontrollers STice key features e Occurrence and time profiling and code coverage analysis new features e Advanced breakpoints with up to 4 levels of conditions e Data breakpoints e Program and data trace recording up to 128 KB records e Read write on the fly of memory during emulation e In circuit debugging programming via SWIM protocol e 8 bit probe analyzer s 1 input and 2 output triggers e Power supply follower managing application voltages between 1 62 to 5 5 V e Modularity that allows you to specify the components you need to meet your development requirements and adapt to future requirements e Supported by free software tools that include integrated development environment IDE programming software interface and assembler for STM8 DoclD025118 Rev 5 101 106 STM8 development tools STM8AF6213 23 23A 26 12 2 12 2 1 12 2 2 102 106 Software tools STM8 development tools are supported by a complete free software package from STMicroelectronics that includes ST visual develop STVD IDE and the ST visual programmer STVP software interface STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8 STMB8 toolset The STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www st com This package includes ST visual develop Full featured integrated development environment from STMicroelec
100. vidual peripherals or memory e Master clock sources four different clock sources can be used to drive the master clock 1 16 MHz high speed external crystal HSE Up to 16 MHz high speed user external clock HSE user ext 16 MHz high speed internal RC oscillator HSI 128 kHz low speed internal RC LSI e Startup clock after reset the microcontroller restarts by default with an internal 2 MHz clock HSI 8 The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts e Clock security system CSS this feature can be enabled by software If an HSE clock failure occurs the internal RC 16 MHz 8 is automatically selected by the CSS and an interrupt can optionally be generated e Configurable main clock output CCO This outputs an external clock for use by the application Table 2 Peripheral clock gating bit assignments in CLK_PCKENR1 2 registers Bit Periphera Bit Peripheral Bit Peripheral Bit Peripheral I clock clock clock clock PCKEN17 TIM1 PCKEN13 LINUART PCKEN27 Reserved PCKEN23 ADC PCKEN16 TIM5 PCKEN12 Reserved PCKEN26 Reserved PCKEN22 AWU PCKEN15 Reserved PCKEN11 SPI PCKEN25 Reserved PCKEN21 Reserved PCKEN14 TIM6 PCKEN10 2c PCKEN24 Reserved PCKEN20 Reserved DoclD025118 Rev 5 g STM8AF6213 23 23A 26 Product overview 4 6 4 7 a Power management For efficient po
101. wer management the application can be put in one of four different low power modes Users can configure each mode to obtain the best compromise between lowest power consumption fastest start up time and available wakeup sources e Wait mode in this mode the CPU is stopped but peripherals are kept running The wakeup is performed by an internal or external interrupt or reset e Active halt mode with regulator on in this mode the CPU and peripheral clocks are stopped An internal wakeup is generated at programmable intervals by the auto wake up unit AWU The main voltage regulator is kept powered on so current consumption is higher than in Active halt mode with regulator off but the wakeup time is faster Wakeup is triggered by the internal AWU interrupt external interrupt or reset e Active halt mode with regulator off this mode is the same as Active halt with regulator on except that the main voltage regulator is powered off so the wake up time is slower e Halt mode in this mode the microcontroller uses the least power The CPU and peripheral clocks are stopped the main voltage regulator is powered off Wakeup is triggered by external event or reset Watchdog timers The watchdog system is based on two independent timers providing maximum security to the applications Activation of the watchdog timers is controlled by option bytes or by software Once activated the watchdogs cannot be disabled by the user program without p
102. x00 525B TIM1 CCMR4 TIM1 capture compare mode register 4 0x00 0x00 525C TIM1 CCER1 TIM1 capture compare enable register 1 0x00 0x00 525D TIM1 CCER2 TIM1 capture compare enable register 2 0x00 0x00 525E TIM1 CNTRH TIM1 counter high 0x00 0x00 525F TIM1_CNTRL TIM1 counter low 0x00 0x00 5260 bug TIM1_PSCRH TIM1 prescaler register high 0x00 0x00 5261 TIM1_PSCRL TIM1 prescaler register low 0x00 0x00 5262 TIM1_ARRH TIM1 auto reload register high OxFF 0x00 5263 TIM1_ARRL TIM1 auto reload register low OxFF 0x00 5264 TIM1_RCR TIM1 repetition counter register 0x00 0x00 5265 TIM1_CCR1H TIM1 capture compare register 1 high 0x00 0x00 5266 TIM1 CCR1L TIM1 capture compare register 1 low 0x00 0x00 5267 TIM1 CCR2H TIM1 capture compare register 2 high 0x00 0x00 5268 TIM1 CCR2L TIM1 capture compare register 2 low 0x00 0x00 5269 TIM1 CCR3H TIM1 capture compare register 3 high 0x00 0x00 526A TIM1_CCR3L TIM1 capture compare register 3 low 0x00 0x00 526B TIM1 CCR4H TIM1 capture compare register 4 high 0x00 0x00 526C TIM1_CCR4L TIM1 capture compare register 4 low 0x00 0x00 526D TIM1_BKR TIM1 break register 0x00 0x00 526E TIM1_DTR TIM1 dead time register 0x00 0x00 526F TIM1_OISR TIM1 output idle state register 0x00 paa E Reserved area 147 byte DoclD025118 Rev 5 g STM8AF6213 23 23A 26 Memory and register map g Table 11 General hardware register map continued
103. z 1 2 5 Eol Offset error fapc 4 MHz 1 5 2 5 fApc 2 MHz 13 3 Ec Gain error LSB fADC 4MHz 2 3 fApc 2 MHz 0 7 1 Epl Differential linearity error fapc 4 MHz 0 7 1 5 fApc 2 MHz 0 6 1 5 EL Integral linearity error fapc 4 MHz 0 8 2 1 Max value is based on characterization not tested in production DoclD025118 Rev 5 87 106 Electrical characteristics STM8AF6213 23 23A 26 Figure 40 ADC accuracy characteristics A EG 1023 pec KAL BR PEER RE EES LANG n 7 I 10224 uten _Vppa ssa IDEAL 1024 1021 m i m Wu 7 7 Zu E x K 7 1 aa 1 i T 44 i ag Mora sl Z sd 1 E 7 E l 4 d us L E 8 jx 2 i i i Ta Ep 24 pm lt gt i iJ a 1LSBIDEAL t UH Ol 4123 4 5 6 7 1021102210231024 Vssa VDDA Example of an actual transfer curve The ideal transfer curve End point correlation line Er Total unadjusted error Maximum deviation between the actual and the ideal transfer curves Eo Offset error Deviation between the first actual transition and the first ideal one Eg Gain error Deviation between the last ideal transition and the last actual one Ep Differential linearity error Maximum deviation between actual steps and the ideal one E Integral linearity error Maximum deviation between any actual transition and the end point correlation line Figure 41 Typical application with ADC

Automotive 8-bit MCU, with up to 8 Kbyte Flash, data EEPROM, 10

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