NB6L11MMNGEVB Evaluation Board User`s Manual
Contents
1. at Package Pins T NLEE Ei EE Bottom View g NS EN B Figure 6 Power Supply Configuration for Device NB6L11M www BDTt com ON NB6L11MMNGEVB NB6L11MMNGEVB TEST Power Supply Voc Ver DUTGND Differential an Test Measuring Signal Equipment Generator DUTGND Vee Channel 1 Channel 2 SMAGND Trigger Trigger Veel GND 0 V DUTGND Power Supply 1 Connect appropriate power supplies to Voc VEg DUTGND SMAGND and ExPad see Table 2 2 Connect a signal generator to the input SMA connectors Setup input signal according to the device data sheet 3 Connect a test measurement device to the device s output SMA connectors NOTE The test measurement device must contain 50 Q termination Figure 7 Basic Lab Setup typical Table 2 POWER SUPPLY LEVELS Power Supply Table 3 NB6xxxM CML OUTPUTS SPLIT POWER Dual Power Supplies SUPPLY CONFIGURATION Device Pin Power Supply Convertor Spilt Power Supply Voc Vee 0V SMAGND Vmr OV 8 Voc DUTGND DUTGND 2 5 V or 3 3 V SEND DUTGND 2 5 V Offset Split Power Supply Configuration Figure 8 Split or Dual Power Supply Connections www BD Tt tom ON NB6L11MMNGEVB Table 4 BILL OF MATERIALS SMA Connector Rosenberger SMA Connector Side 32K243 40ME3 http www rosenberger de Launch Gold Plated http www rosenbergerna com Surface Mount Keystone SMT Miniature Test 5015 4 http www keyelco c2. NB6L11MMNGEVB NB6L11MMNGEVB Evaluation Board User s Manual Introduction ON Semiconductor has developed the QFNI6EVB evaluation board for its high performance devices packaged in the 16 Pin QFN This evaluation board was designed to provide a flexible and convenient platform to quickly evaluate characterize and verify the operation of various ON Semiconductor products Many QFN16EVBs are dedicated with a device already installed and can be ordered from www onsemi com at the specific device web page This manual specifically describes the application of the OFN16EVB with the use of the NB6L11MMNG device This evaluation board user s manual contains e Information on 16 lead QFN Evaluation Board Assembly Instructions Appropriate Lab Setup e Bill of Materials This user s manual provides detailed information on board contents layout and its use It should be used in Pe E CN e sv vs 3e E a B 8B E B kur n ve Nr NEP uanun Top View ON Semiconductor http onsemi com EVAL BOARD USER S MANUAL conjunction with an appropriate ON Semiconductor device datasheet located at www onsemi com The datasheet contains the technical device specifications Board Layout The QFN16 Evaluation Board provides a high bandwidth 50 controlled impedance environment and is implemented in four layers The first layer or primary trace layer is 0 008 thick Rogers RO4003 material and is des
3. Z FR 40020m S f 7 0 062 0 007 LAYER 3 GROUND VCC amp VEE PLANE P2 1 OZ FR4005in S 7 LAYER 4 BOTTOM SIDE 1 OZ Figure 4 Evaluation Board Layout 4 Layer www BDTt com ON NB6L11MMNGEVB Top View Evaluation Board Assembly Instructions The QFN 16 evaluation board is designed for characterizing devices in a 50 Q laboratory environment using high bandwidth equipment Each signal trace on the board has a via at the DUT pin which provides an option of placing a termination resistor on the board bottom depending on the input output configuration see Table 1 Example Configuration List Table 4 contains the Bill of Materials for this evaluation board The OFN16EVB was designed to accommodate a custom QFN 16 socket Therefore some external components are installed on the bottom side of the board Solder the Device on the Evaluation Board The soldering of a device to the evaluation board can be accomplished by hand soldering or solder reflow techniques using solder paste Make sure pin 1 of the device is located properly and all the pins are aligned to the footprint pads Solder the QFN 16 device to the evaluation board As mentioned earlier many OFN16EVBs are dedicated with a device already installed and can be ordered from onsemi com at the specific device web page Connecting Power and Ground On the top side of the evaluation board solder the four surface mount test point clips anvils to the pads
4. at www onsemi com site pdf Patent Marking pdf SCILLC reserves the right to make changes without further notice to any products herein SCILLC makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does SCILLC assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including Typicals must be validated for each customer application by customer s technical experts SCILLC does not convey any license under its patent rights nor the rights of others SCILLC products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application Buyer shall indemnify and hold SCILLC and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and rea
5. igned to have equal electrical length on all signal traces from the device under test DUT pins to the SMA connectors The second layer is the 1 0 oz copper ground plane and is primarily dedicated for the SMA connector ground plane FR4 dielectric material is placed between the second and third layers and between third and fourth layers The third layer is also 1 0 oz copper plane A portion of this layer is designated for the device Vcc and DUTGND power planes The fourth layer is the secondary trace layer TEMPE AZ 83282 USA tweet 502 438 1112 LOI 41 5833 P N MO0A82C21835 0 0 REVB 5 4 Bottom View Figure 1 Top and Bottom View of the 16 QFN Evaluation Board Semiconductor Compon 1 blication Order Number December 2012 WWW e CO m EVBUM2168 D NB6L11MMNGEVB Mn St LD ee EE A IL Ih A VEE DUTGND VCC SMA GND Y Y Pin 12 gt Pin 1 Q Pin 11 gt zZ Pin2 DUT GND d Pin 10 gt 4 Pins dp Pin 9 gt E Pin 4 A A lee N O W c c c CE oO a n A Figure 2 Enlarged Bottom View Figure 3 Enlarged Bottom View of the Evaluation Board SILKSCREEN TOP SIDE LAYER 1 TOP SIDE 1 OZ ROGERS40030 008in 4 LAYER 2 GROUND PLANE P1 1 OZ Z
6. labeled Vcc VEE DUTGND SMAGND and ExPad ExPad is connected to the exposed flag of the QFN package For proper operation the exposed flag is typically recommended to be tied to Vgg DUTGND the negative supply of the device The positive power supply connector is labeled Vcc Depending on the device the negative power supply nomenclature is labeled either GND or Ver To help avoid confusion with the use of this board the negative supply Figure 5 Evaluation Board Layout TEMPE AZ BER L5 4 F KT LADY 434 HS E FAK ATH B2 4510033 P N IMQOAB2C21B35 REV C e Bottom View connector is labeled Vgg DUTGND SMAGND is the ground for the SMA connectors and is not to be confused with the device ground VEr DUTGND SMAGND and DUTGND can be connected in single supply applications The power pin layout and typical connection of the evaluation board is shown in Figure 6 It is recommended to add bypass capacitors to reduce unwanted noise from the power supplies Connect 0 1uF capacitors from Vcc and Vpgg DUTGND to SMA GND Output Loading Termination ECL PECL LVPECL Outputs Most ECL outputs are open emitter and need to be DC loaded and AC terminated to Vcc 2 0 V via a 50 Q resistor If no internal resistors are provided on the device 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the ECL driver Solder the chip resistors to the bottom side of the board between the app
7. om Test Points Point Chip Capacitor AVC Corporation 0603 0 01 uF 10 06035C103KAT2A http www avxcorp com 0603 0 1 uF 10 0603C104KAT2A Eu Chip Resistor Panasonic 0402 50 Q 1 ERJ 2RKF49R9X na http www panasonic com Precision Thick Film Chip Resistor Evaluation Board ON Semiconductor QFN 16 Evaluation QFN16EVB 1 http www onsemi com Board Device Samples ON Semiconductor QFN 16 Package NB6L11MMNG http www onsemi com Device Components are available through most distributors i e www newark com www digikey com www BD ftf com ON NB6L11MMNGEVB 12 Quom SMA_GHI Second Layer SMA_GND Plane Figure 9 Gerber Files www BD Ttf com ON NB6L11MMNGEVB e JIE 13 Jit a 8 TP TR e LE j e WEG WEE e 9 e ie dB ein _ E Deer 07705 e T e see d3 NBs ox e e DUT_GND SMA_GHD TPS TP4 P d amp amp J e JE amp e T 7 6 6 0 Third Layer DUT GND Trace ON Semiconductor TEMPE AZ 85282 USA TES INT 1 602 438 1112 UU a FAX INT 1 802 431 9633 db P N Moon M g DEC Bottom Layer Figure 10 Gerber Files www BD ftf com ON NB6L11MMNGEVB ON Semiconductor and WwW are registered trademarks of Semiconductor Components Industries LLC SCILLC SCILLC owns the rights to a number of patents trademarks copyrights trade secrets and other intellectual property A listing of SCILLC s product patent coverage may be accessed
8. ropriate input device pads and the ground pads If internal resistors are provided the VT pins should be wired to SMAGND More information on termination is provided in AND8020 For standard ECL lab setup and test a split dual power supply is recommended enabling the 50 Q internal impedance in the oscilloscope or other measuring instrument to be used as an ECL output load termination By offsetting Vcc 20 V SMAGND Vcc 2 0 V SMAGND is the system ground 0V Vcc is 2 0 V and Vpgg DUTGND is 3 0 V 1 3 V or 0 5 V see Table 2 Power Supply Levels CML Outputs Likewise CML outputs need to be terminated to Vcc via a 50 2 resistor If no internal resistors are provided on the www BD ftf com ON NB6L11MMNGEVB device 0402 chip resistor pads are provided on the bottom side of the evaluation board to terminate the CML driver If internal resistors are provided the Vr pins should be wired to Vcc For CML lab setup and test operation with negative supply voltages is recommended to enable the 50 Q internal Impedance in the oscilloscope or other measuring instrument to be used as a CML output termination Vcc 0 V SMAGND 0 V and Vgg DUTGND 5 0 V 3 3 V 2 5 V or 1 8 V LVDS Outputs LVDS outputs are typically terminated with 100 2 across the Q O output pair The 100 2 can be added on the OFNI6EVB but it is not provided on the board since there are several user dependent LVDS output measuremen
9. sonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part SCILLC is an Equal Opportunity Affirmative Action Employer This literature is subject to all applicable copyright laws and is not for resale in any manner PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT N American Technical Support 800 282 9855 Toll Free ON Semiconductor Website www onsemi com Literature Distribution Center for ON Semiconductor USA Canada P O Box 5163 Denver Colorado 80217 USA Europe Middle East and Africa Technical Support Order Literature http www onsemi com orderlit Phone 303 675 2175 or 800 344 3860 Toll Free USA Canada Phone 421 33 790 2910 LL Fax 303 675 2176 or 800 344 3867 Toll Free USA Canada Japan Customer Focus Center For additional information please contact your local Email orderlit onsemi com Phone 81 3 5817 1050 Sales Representative www BDTIC com ON weten
10. t techniques For LVDS lab setup and test a single supply is typically used ie Vcc 2 3 3 V and DUTGND 0 V Installing the SMA Connectors Each configuration indicates the number of SMA connectors needed to populate an evaluation board for a given device Each input and output requires one SMA connector Install all the required SMA connectors onto the board and solder the center signal conductor pin to the board on J1 through J16 Please note that the alignment of the signal connector pin of the SMA connector to the metal trace on the board can influence lab results The launch and reflection of the signals are largely influenced by imperfect alignment and soldering of the SMA connector Validating the Assembled Board After assembling the evaluation board it is recommended to perform continuity checks on all soldered areas before commencing with the evaluation process Time Domain Reflectometry TDR is another highly recommended validation test www BDTt com ON NB6L11MMNGEVB NB6L11MMNGEVB ASSEMBLY Table 1 CONFIGURATION FOR DEVICE NB6L11M NOTE DUTGND Vee Exposed Pad and must be tied to DUTGND VEe CONFIGURATIONS Top View Polarity of 22 uF C4 C2 OR Semiconductor SMAGND m TEMPE AZ 85282 U S A e INT 1 BO2 438 1112 ud 2 FAX INT 602 431 9635 a gt CD P N 1M00AB2C21835 Install 0 1 uF Decoup vd REV C el ling Capacitors Here Td e i and
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