PROCMegaDelay User Guide
Contents
1.2. PROCMegaDelay IP User s Guide September 2008 GiDEL products and their generated products are not designed intended authorized or warranted to be suitable for use in life support applications devices or systems or other critical applications 1993 2008 by GiDEL Ltd All rights reserved GiDEL PROCSiar II PROCSpark IF PROC_DSP PSDB CL M PROCWizard PROCCamLink PROCMultiPort PROCMegaFIFO PROCMegaDelay and other product names are trademarks of GiDEL Ltd which may be registered in some jurisdictions This information is believed to be accurate and reliable but GiDEL Ltd assumes no responsibility for any errors that may appear in this document GiDEL reserves the right to make changes in the product specifications without prior notice Windows NT Windows XP Windows 2000 Stratix Il EP2S60 DDRII CameraLink and other brands and product names are trademarks or registered trademarks of their respective holders USA Worldwide 1600 Wyatt Drive Suite 1 2 Ha ilan Street P O Box 281 Santa Clara Or Akiva CA 95054 USA Israel 30600 Tel 1 408 969 0389 Tel 972 4610 2500 Fax 1 866 615 6810 Fax 972 4610 2501 sales _usa GiDEL com sales euOGIDEL com Web www GiDEL com info GiDEL com Contents 1 UT 2 2 Key Feat reS 3 3 Setting up PROCMegaDelay pp 4 4 PROCMegaDelay in HDL Ne 9 4 1 General Notes nennen nennen 9 4 2 Working
3. For more information please refer to the PROCMultiPort IP User Guide 6 4 GiDEL PROCMegaFIFOTM PROCMegaFIFO is GiDEL s IP that provides a simple and convenient way to transfer data to from GiDEL PROC boards With PROCMegaFIFO data may be transferred between the host PC and user s subdesigns or between subdesigns using the on board memory as a very large FIFO PROCMegaFIFO eliminates the need to take care of synchronization when transferring data between designs The software no longer needs to respond to the hardware in real time and hardware designs may now transfer data in bursts and withdraw it in a continuous stream PROCMegaFIFO uses special arbitration techniques when transferring data between the host PC and user s subdesigns These techniques prevent memory overflows underruns thus using the maximum available bandwidth for data transfers 14 Request and Acknowledge signals ensure correct data transfers On the software side the Proc class methods perform automatic initialization of the FIFO logic and enable easy data transfers using DMA For more information please refer to the PROCMegaFIFO IP User Guide 15 c Del 7 References 7 1 REFERENCES PROOCWizard Version 8 0 User Manual PROCMultiPort IP User Guide PROCMegaFIFO IP User Guide 8 1 User Guide History 8 Appendix Date Changes Feb 2006 Rev 01 User Guide Sept 2008 Addition of SODIMM Density and Type
4. the Property Page Property Page Define read ports settings Figure 6 Example of a Filled Property Page 9 Click Finish to return to the Configuration Mode Gadel 4 PROCMegaDelay in HDL 4 1 General Notes In the current version of PROCWizard there is no bandwidth check The user has to avoid memory throughput override To calculate the throughput multiply memory clock rate by memory width and reduce it by 75 For example suppose we have a 32bits wide memory running on 150MHz Throughput 0 75 32 150 10 3 6Gbps If the memory is of DDR type the final throughput is multiplied by 2 Throughput 3 6Gbps 2 7 2Gbps The sum of all active ports data rates should be less than the memory throughput 4 2 Working with PROCMegaDelay To reset and start PROCMegaDelay 1 In case of Non Constant Delay port apply the desired delay on the Delay bus of that port delay_MDelay_name_port_name 2 Assert the MDelay_name_reset pin high for at least 3 periods of the data clock MDelay_name_clk 3 Wait for MDelay_name_ready to go high usually 10 30 clock periods from the reset fall 4 3 Writing and Reading data After MDelay name ready signal goes high you may start writing to the source port of MegaDelay Assert MDelay name clk en signal high when the data is ready on the source port data bus Valid data will appear on the read port s buses data MDelay name port name after the specified number of clo
5. 16M 4 22 DATA WIDTH Port data bus width m in bits MEM WIDTH EO nda width in bits The number of read ports is the number of different delay lines in the design NUMBER OF READ POR The number of TS read ports Table 1 PROCMegaDelay Parameter Names 11 5 2 Signal Bus Names for PROCMegaDelay Signal Bus Name Direction Purpose Comments dedos Global reset signal is active INPUT Global reset signal low INPUT Memory clock All MegaDelay ports are Neon HERES ELIAS synchronized with this clock Reset pulse is active high INPUT MegaDelay reset Should be at least 3 clocks wide Resets the MegaDelay When high MegaDelay unit is OUTPUT Ready signal ready to accept and deploy data MegaDelay unit will accept Clock enable and deploy data upon each clock when this signal is high For ports with non fixed delay this bus sets the desired delay time Place the desired number of clocks to delay on this bus before resetting the MegaDelay Delay time in clocks INPUT Source data Data to delay OUTPUT Delayed data Table 2 MegaDelay Signal and Bus Names port_name is the name given to the MegaDelay port during the definition process in PROCWizard Mdelay name is the name given to the MegaDelay module during the definition process in PROCWizard 12 Gr Del 6 Accessories 6 1 GiDEL PROC Developer s Kit GiDEL PROC Developer s Kit is a set of building blocks designed f
6. cks E 5 PROCMegaDelay Gvel Parameters and Signals The tables below describe the parameters and signals used in the Memory Controller subdesigns These subdesigns are generated whenever a memory controller is used and are named using the following scheme IC X Bank Y Ctrl where X is the IC number and Y is the memory bank name These HDL files tdf are automatically generated by PROCWizard whenever the SDRAM controller is used The signals that are driven from the user logic are automatically added to the user subdesigns with the same name 1 All GiDEL IPs should be connected using automatic generation with PROCWizard 2 The parameters and the signals are defined automatically and there is no need to change them manually The best way to change them is to define a new design in PROCWizard and generate a new HDL code ee 3 There are a number of the signals and parameters which are not described here They are generated automatically to suit current design The user should not change them in any case 4 PROCMegaDelay IP does not interfere in the throughput control Be careful not to exceed memory throughput and use MDelay name ready signal 5 1 Parameters for PROCMegaDelay Parameter name Purpose Comments For example if we define a 16MB MegaDelay and the memory cell is 4 bytes wide ADDR_WIDTH Memory address then we have 4M address bus width in bits space and 22 bit address bus ADDR_WIDTH Log2
7. eded PROCMegaDelay IP key features include User friendly design with standard input and output Simple interface Optimized for easy control Large memory buffers managed using cyclic memory pointers Several outputs may be defined for each PROCMegaDelay module to output the same data delayed by different factors GIDE 3 Setting up PROCMegaDelay The input and all the outputs of PROCMegaDelay must be connected to the same subdesign You should have your target subdesign ready before you start setting up the MegaDelay The following should be defined IC s a Main clock and memory clock User designs and with appropriate clocks In the current version of PROCDeveloper s Kit it is not be possible to put a PROCMegaDelay in the same memory bank as PROCMultiPort and vice versa To learn how to define subdesigns please refer to PROCWizard Version 8 0 User Manual To set up PROCMegaDelay using the PROCWizard 1 Click Configure card in the PROCWizard toolbar Figure 1 below to enter the Configuration Mode njajal je lele Lila ag Figure 1 Configure Card The Configuration Mode is used to build designs in PROCWizard New items can be added to the design in this mode and existing items can be redesigned To learn more about the Configuration Mode please refer to PROCWizard Version 8 0 User Manual 2 Click the sign to the left of the Designs Card proc card type item to expand it 3 R
8. ight click on the name of the desired IC to access the IC component drop down menu and select GiDEL IP Core gt MegaDelay Delta gt lilo m re E Designs Card PROCSparkII 35 E Global values ED Clock Rate 100 000 Clocks Add Register Xi O Info Add Memory Add Register s Group user_entity Add Subdesign GIDEL IP Core gt MultiPort Remove Del Clock Menu BITS Cut Ctrl x Copy Ctrl C Sort Properties Shift P Figure 2 Accessing MegaDelay in IC Component Drop Down Menu The MegaDelay dialog box appears MegaDelay Name Port Count Memory Size 1 X 1MB Memory Bank Clock C Bank GE BankB C BakC Clock can be changed in clock component settings SUDIMM Density Type 2 GB E Figure 3 MegaDelay Dialog Box 4 n the MegaDelay dialog box define the following attributes The Name of the MegaDelay memory The output Port Count each output port may output the source data after a different delay The Memory Size to be allocated for the delay The Memory Bank in which the MegaDelay will reside If the selected Memory Bank is a SODIMM memory then a SODIMM group box with the fields Density and Type will appear in the MegaDelay dialog box See Figure 3 Click the Density arrow to select one of the possible memory densities Click the SODIMM Type arrow to select your SODIMM s memory type To determine y
9. ll the above instantiations with user s modules entities and the on board local bus and memories Device constraints including FPGA pin out pins power voltage VCCIO Quartus operation recommendations etc In addition the PROCWizard can generate documentation in html or doc format describing in detail the generated features PROCWizard also enables you to test and debug the design in a PC environment Using PROCWizard you can access PROC boards with a structural browser and macros scripts You may load save and compare memory files to check data transfers and access the registers memories defined in the design in real time For more information please refer to the PROCWizard User Manual 8 0 6 3 GiDEL PROCMultiPort PROCMultiPort completes the PROC board features and provides an advanced controller for the on board memories This controller has up to 16 ports each port features a simple access FIFO like or random All ports are connected to the same memory domain and can be accessed independently and simultaneously with individual clock domains and data widths PROCMultiPort segmented mode provides the ability to logically enlarge the FPGA memory size The innovative PROCMultiPort concept enables new design methodologies It can replace many large and complicated designs thus reducing development effort For example it can replace swappable double buffers or implement multiple logical memories in the same physical memory
10. or fast high productivity system development It is a complete system solution including boards software tools IPs and optional daughterboards The major software tools and IPs are detailed in the following paragraphs 6 2 GiDEL PROCWizard GiDEL PROCWizard is a convenient developer s environment that can automatically generate the Hardware Software interface for your application This interface includes Application driver C class The driver can be generated for Windows or Linux environment The driver is built in two layers O The lower layer the Proc class implements basic board functionality such as FPGA loading DMA interfaces Interrupt Service Routines board clocking system setups board information acquisition FPGA size speed grade etc The Proc class is supplied with the PROCWizard The higher layer is automatically generated by the PROCWizard This class inherits from the Proc class and implements all the application specific functionality It loads the Stratix Il device sets up the board clocking and initializes all the class members to allow simple access to the board application from the user space HDL code Verilog VHDL or AHDL PROCWizard can automatically generate the following features O O O Interface module entity that communicates with the software driver PROCMultiPort on board memory controller instantiations Basic PLLs to control external memories Top level design connecting a
11. our SODIMM s type refer to the GiDEL SODIMM Type Datasheet document In accordance to the SODIMM s Type the PROCWizard will automatically generate a customized design The Memory Clock rate is in MHz and is set via the clock menu 5 Click Next to continue the configuration of MegaDelay in the Property Page Property Page Define read ports settings Ho Name Permanent Entity Clock clk2 0 7 Clock 25 00 Port Width 8 lt Back Finish Cancel Figure 4 Property Page 6 In the Property Page select the required Target subdesign Entity Data Clock domain Data Width in bits 7 Double click in each row to access the Delay Settings for every port Delay Settings Delay Settings Name Name No_Delay fix port3 C Constant Delay Constant Delay Non Constant Delay C Non Constant Delay Delay clocks 24000 Figure 5 Delay Setting Choices The following settings are available Output port Name Delay type Constant Delay Non Constant Delay Delay in clocks for Constant Delay ports NOTE The minimum delay is 8 000 clocks The maximum delay is determined by the size of the memory in which the MegaDelay resides If Non Constant Delay was chosen for a particular port the Delay bus of that port will be connected to the target subdesign This way the user s logic may set a different delay each time the MegaDelay is reset 8 Continue defining delays as required in
12. thus enabling generation of very large delay lines PROCMegaDelay is typically used for 2D 3D video processing where very large quantities of data must be stored in memory and extracted later PROCMegaDelay makes it possible to compare between two not necessary subsequent video frames or to write video stream as it arrives and read it by frames for further processing PROCMegaDelay is simple to use Its straightforward interface is based on the familiar GiDEL PROCMultiPort interface Once the PROCMegaDelay has been set up GiDEL PROCWizard automatically connects the required signals to the designer s module The signals entering the user s module are ready for immediate use Gr Del 2 Key Features PROCMegaDelay was designed to provide an effective and simple means of creating delay lines PROCMegaDelay defines the on board memory or a part of it as pipeline storage Data is inserted on the one end of the pipeline and simultaneously withdrawn from the other end The length of the pipeline defines the delay time The main advantage of PROCMegaDelay is its ability to work with huge memory banks The delay memory bank may be on board DDR memory or memory modules connected to SODIMM sockets Due to the very large dimensions of these memory banks the data may be delayed by millions of clocks PROCMegaDelay uses cyclic memory pointers This way a virtual infinite memory space is created assuming that the memory bandwidth is not exce
13. with PROCMegaDelay 9 4 3 Writing and Reading data sse 9 5 PROCMegaDelay Parameters and Signals 10 5 1 Parameters for PROCMegaDelay see 11 5 2 Signal Bus Names for PROCMegaDelay sss 12 6 MENTOR 13 6 1 GIBEL PROG Developers Kit usa eee eee tree rer n eterne 13 6 2 GIDEL PROGCWIzArd M e deed 13 6 3 GIDEL PROGCMuUltiPOrt M css qro ener re 14 6 4 GIDEL PROCMegaFIFO TM ed 14 7 Relsrenices p M ie 16 7 1 REFERENGES ed rane eat eco oce e rl pase gn 16 8 PRI SINGIN Sucre nter nie RAR eee ere SRD EATER RR PETERE ERE 17 8 1 User Guide HISTOR IER M 17 ii Figures Figure 1 Configure 23 4 Figure 2 Accessing MegaDelay in IC Component Drop Down Menu 5 Figure 3 MegaDelay Properties Dialog pp 5 6 Figure 5 Delay Setting Choices pp 7 Figure 6 Example of a Filled Property Page eene 8 Table 1 MegaDelay Parameter Names Table 2 MegaDelay Signal and Bus Names RN Tables 1 Introduction PROCMegaDelay IP is GiDEL s Intellectual Property that provides a simple and convenient way to create large delay lines frame delays PROCMegaDelay eliminates the need to use standard delay lines which utilize internal FPGA memories Instead PROCMegaDelay uses the on board memory or SODIMM memory module
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