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STEL-2176

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1. 00 1001 1011 0011 0001 0010 0011 0111 0110 0 0 1000 1010 0010 0000 0000 0001 0101 0100 9 0 e e 0100 0101 0001 0000 0000 0010 1010 1000 e e o 0110 0111 0011 0010 0001 0011 1011 1001 ka 11 6 a0 2 2 2 2 5 8 5 3 S S 5 8 2 5 5 8 WCP 53712 10 29 97 Figure 8 64 Constellation Two bits the same for each modulation type are identified as ICC The remaining bits are identified as bg 1 where q 2 4 and 6 for 16 64 or 256 QAM IkOx are processed by the differential decoder before being fed to the frame sync block The remaining bits bo are fed directly to the frame sync Differential Decoder Two bits of each symbol are differentially decoded according to the equation User Manual Figure 9 256 OAM Constellation DAVIC 100000 100001 100101 100100 110100 110101 110001 110000 100010 100011 100111 100110 110110 100111 110011 110010 101010 101011 100111 101110 111110 111111 111011 111010 e e e 0 0 101000 101001 e e 8 E 8 gt 24 5 8 8 001000 001001 001101 e 8 8 2 8 8 E Ed 5 8 8 8 001010 001011 001111 8 8 9 9 9 9 5 8 000010 000011 00
2. 26 Group 2 Sub Group Read Write ananem anana nenen 26 Group 2 Sub Group D Read Only Registers 27 Group 2 Sub Group E Read Write Registers peo ee e 28 Group 2 Sub Group E Read Only 28 Group 2 Sub Group F Read Write Registers 5 29 Group 2 Sub Group F Read Only 30 Group 3 Sub Group Read Write Registers eterni eredi enne tnn 30 Group 3 Sub Group B Read Only Registers 31 Group 3 Sub Group Read ud ea eec tea ed 31 Group 3 Sub Group Read Only anane eee 31 Group 3 Sub Group Read Write Registers eet pae ae derbi ide 32 Group 3 Sub Group D Read Only Registers sssssssseeeeeeee 32 Group 3 Sub Group E Read Write 33 Group 3 Sub Group E Read Only ee 33 Group 3 Sub Group F Read Write Registers ior 34 Group 3 Sub Group G Read Write Registers seien ro cob d dese b 34 Group 3 Sub Group G Read Only Registers
3. Q b Q m 16QAM SL M A LLLA IL Q nuno a 16QAM ES Note bo is the first serial data bit to arrive at the Bit Mapper Differential Encoder The Differential Encoder encodes the bits I Ij 0 7 of each symbol received from the Bit Mapper to determine the output bit values i e Qj I and which are routed to the Symbol Mapper User Manual The differential encoder can be either enabled or bypassed under the control of either a register bit or a user supplied control signal TXDIFFEN The selection between user input pin control or register control is made in another register bit as shown in Table 39 45 STEL 2176 Transmitter Description Table 39 Differential Control Register 38 Level Value Bits 1 0 Encoding off continuously Encoding on continuously Encoding enabled by pu 116 X 0 high enable the Differential Encoder low disable the Differential Encoder For any modulation mode if differential encoding is disabled then Lovocro5o If differential encoding is enabled then the results are described below for each modulation type BPSK In BPSK mode the next output bit is found by XORing the input bit with the current output bit The result is a 180 degree phase change if the output is high and 0 degrees if the
4. O Dedicated to analog section of Dedicated to digital section of sure 1 Receive output frame sync flag User Manual Introduction uL From 193 VSSA Ground analog Dedicated to analog section of ADCS s Dedicated to digital section of 5 195 VDDA Power analog Dedicated to analog section of ADC Pe Power analog Dedicated to analog section of I C ADCINP 198 ADCINN Analog input Complementary ADC input 8 18 199 VSSA Ground analog Dedicated to analog section of ADC 9 Pe 200 VSSA Ground analog Dedicated to analog section of D Dedicated to digital section of ADC e __202 Power analog Dedicated to analog section of ADCS 8 2 Q VREFP From ADCS 204 Dedicated to digital section of Fe Deden diat 206 V55 Ground analog Dedicated to analog section of D 2007 10004 Power analog Dedicated to analog section of I C sure t Q Digital GND VSS Analog In N Analog In P Analog GND 55 01 5 5 Digital Supply VDD wn N N N N STEL 2176 53567 c 1 2 07 97 Figure 1 Reference A D Wiring T1 6TKK81 L 0 1 Note 1 DACOUTP 509 AVss 0 1 500 line
5. TXSCRMEN 49 SERIAL OUTPUT SERIAL INPUT yor gt 2 SSYNC WCP 53809 12 2 97 Figure 26 Scrambler Block Diagram Randomized Data The value in the INIT registers is loaded into the scrambler shift registers whenever the scrambler is at disabled The scrambler will scramble data one bit a Enable Clear Data Input time at each falling edge of TXBITCLK that occurs WCR panah while both the scrambler are active Figure 27 DAVIC Scrambler Table 35 Scrambler Parameters Characteristic Block 2 Register Setting Generator cx 1 Register 35 Register 34 Register 33 rd 7 di 0 Bit7 to Bit7 to BitO Cis to to Seed Any 24 bit binary value 5 41 X Register 31 Register 30 INIT Reg Bit7 8 BitO Bit7 0 Be 7 put 0 S24 517 516 Meck Reg where c is a binary value 0 1 Scrambler Frame synchronized sidestream 36 Bit 4 ee s RUNDE Scrambler Self synchronized Register 36 Bit 4 BET mee Table 36 Sample Scramble Register Values Characteristic Block 2 Register Setting Generator x 1 Register 35 Register 34 Register 33 Polynomial Bit 7 to Bit 0 Bit 7 to Bit 0 Bit 7 to Bit 0 Mask Reg 0000 0000 0110 0000 0000 0000 Seed 0000A9 Register 32 Register 31 Register 30 INIT Reg Bit 7 to Bit 0 Bit 7 to Bit 0 Bit 7 to Bit 0 0000 0000 0000 0000 1010 1001
6. n DAN Ka oes i 100 100 101 000 000 100 10 011 011 001 000 011 10 110 011 100 000 110 001 100 000 010 001 110 100 010 101 110 110 011 111 001 100 011 110 110 111 100 100 110 101 100 010 010 111 110 0 0 101 001 010 001 011 101 110 001 111 101 53709 10 29 97 Figure 15 64 QAM Mapping User Manual 17 STEL 2176 Receiver Description 1110 1111 1110 1111 1110 1111 1110 1111 0000 0011 0100 0111 1000 1011 1100 1111 1111 1101 1011 1001 0111 0101 0011 0001 1111 1111 1111 1111 1111 1111 1111 1111 1100 1101 1100 1101 1100 1101 1100 1101 0000 0011 0100 0111 1000 1011 1100 1111 1110 1100 1010 1000 0110 0100 0010 0000 1100 1100 1100 1100 1100 1100 1100 1100 1010 1011 1010 1011 1010 1011 1010 1011 0000 0011 0100 0111 1000 1011 1100 1111 1111 1101 1011 1001 0111 0101 0011 0001 1011 1011 1011 1011 1011 1011 1011 1011 1000 1001 1000 1001 1000 1001 1000 1001 0000 0011 0100 0111 1000 1011 1100 1111 1110 1100 1010 1000 0110 0100 0010 0000 1000 1000 1000 1000 1000 1000 1000 1000 0110 0111 0110 0111 0110 0111 0110 0
7. 1 TRANSMLIEPLDER S Anan a Ba Lana a ala a A A Ana Elo 1 INTRODUCTION Ga a a a GAE E AG 2 Ja an ga te seda 2 TRANSMITTER OVERVIEW i 2 MECHANICAL SPECIFICATIONN S 5 2 eterno taste sa EN D EN ENEG aa a EEE NE GE en po GE EE E a 3 208 PIN SOEP PACKAGE a a aja eo ates _ 3 ELECTRICAL SPECIFICATION O A a a a NG EN wens 8 RECEIVER E 568 696969 10 OVERVIEW e GO a a hcl 10 _ _ 2 lt 2 __ ___ ____ _ _ _ _____ _ 11 0 99 9 2 _ 3 000022 11 Mictocontroller ___33 3 3_ _ _ 3 ___ 11 Master Receive Clock sese seme sese e e eser se seen 12 QAM DermodulatorBlocks 5 2 22 ng 13
8. _ 1 O STEL 2176 4 User Manual Introduction Pin No 6__ 5________ __ 77 78 79 a vD Power SS 82 83 aa Dedicated to digital portion of DAC Power analog Dedicated to analog portion of DAC 88 DACOUTP Output of DAC Terminate 37 5 ohms to ground 8 DACOUTN Analog output Comp output of DAC Terminate 37 5 ohms to ground igure VSSA Power analog Dedicated to analog portion of DAC 92 93 94 95 97 re 2 100 101 _ 19 _ VLL 33 5 195 PSS Ground 39 vo sco eR ii 5 7 vp Poe 2 wes i c _ 2 55 5 55 M Ti VDD5 Input buffer bias Set to 3 3V or 5V dep on max input V voltage 11 Ground TXPLLEN Enable transmit clock PLL 91 Dedicated to digital portion of DAC User Manual 5 STEL 2176 Introduction Pin No 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184
9. s mse er SCRAMBLER Init Reg 7 0 E ee gt DATA DATA RSENBP RSENS SCRME SCRM DiffDC BP DiffDCS EL Transmit Parameter Descriptions Auxiliary Clock Rate Sets the divide by ratio of for generating an output clock for use with external Divider control circuits Bit Mapping Selects the Bit to 5ymbol mapping option when QPSK or 16QAM modulation is selected Used to arm the TXBITCLK synchronization circuit when TXCLKEN cannot be applied low between bursts Bit Sync Re arm BypassB Allows the Scrambler and Reed Solomon Encoder to be bypassed CLRFIR Controls the Gain of the FIR Filter DATAENBPB Continuously enables or disables the input multiplexer of the Bit Encoder Block DATAENSEL Selects software DATAENBPB or hardware input pin 109 control for enabling the input multiplexer of the Bit Encoder Block DiffDCBPB Allows the Differential Encoder to be bypassed DiffDCSEL Selects software DiffDCBPB or hardware input pin 116 control for enabling the Differential Encoder ENDAC Setting this bit to 0 will make the DAC output enable controlled by the signal see page 65 Setting it to 1 will make the DAC enabled all the time The default is 0 FIR bypass Controls routing of I Q data through or around the FIR filters FIR Filter Sixteen 10 bit FIR coefficients Each coefficient is applied to two t
10. 34 Transmit Features 40 Foster bte distr tuse M M M Rie Id 41 BIT Encoding Data Path 42 scrambler Parameters iste soak Hair etse ase 43 Sample Scramble Register 43 Reed Solomon Encoder 44 BitMapping Options piper inte ge gan dde 45 Differential Encoder 46 QPSK Differential Encoding and Phase Shite tectonics 46 Symbol Mapping 48 Symbol Mapping ies 48 FIR Filter Configuration Options 50 iv User Manual LIST TABLES TABLE PAGE 44 FIR Filter Coefficient Storage 5 aaa tete sine NE 50 45 Interpolation Filter Bypass 51 46 Interpolation Filter Signal Level 51 47 Signal Inversion 1 100 52 48 I 54 49 Addresses of the STEL 2176 Register GFOUDS ied ertet io 54
11. 16 QAM ID 64 QAM ID 256 QAM ShiftSel_W3 1 0 ShiftSel W2 2 0 ShiftSel W1 2 0 Factory Penns Value Factory ShiftSel_W5 2 0 ShiftSel_W4 2 0 Se 32 eer Value STEL 2176 26 User Manual Receiver Description Table 16 Group 2 Sub Group D Read Only Registers Mae 7 1 9 131 313 I 7 1 0 _ User Manual 27 STEL 2176 Receiver Description Bank 0 Group 2 Sub Group D Register Data Field Descriptions CenterTapAddr Defines which the taps address that will be set as the center tap There are 12 taps in the FFE that can be designated as the center tap 0 to 11 DDenable Allows the FFE to switch to decision directed DD mode otherwise the FFE will remain in its blind equalization mode aka CMA constant modulus algorithm mode Factory Defined Value The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values must be written to the data field Factory Use Only This data field is used by the factory and its function is not related to the STEL 2176 receive and transmit characteristics ShiftSel_W1 ShiftSel_W2 2 0 The setting specifies the step size of the FFE the nominal value is 2 2 0 ShiftSel W3 2 0 The setting specifies the step size of the FFE the nominal value is 2 2 0 2 0 The setting specifies the step size of the FFE the nominal value is 2 ShiftSel W4 Shif
12. 21761 00 0000 20 00000 STEL 2176 IC ul User Manual STel MAN 97709 STEL 2176 Digital Mod Demod ASIC 16 64 256 QAM Receiver with FEC QPSK 16 QAM Transmitter with FEC TRADEMARKS Stanford Telecom and STEL are registered trademarks of Stanford Telecommunications Incorporated STEL 2176 User Manual FOREWORD The Telecom Component Products Division of Stanford Telecommunications Inc is pleased to provide its customers with this copy of the STEL 2176 User Manual This User Manual contains product information for the STEL 2176 and is being provided to assist our customers in understanding the advantages to be gained by integrating both the receiver and transmitter functions as an integral portion of their cable modem chip Recipients of this User Manual should note that the content contained here in is subject to change The content of this User Manual will be updated to reflect the latest technical data without notice to the recipients of this document User Manual STEL 2176 for 5 2176 Supported Modes of Operation Downstream 16 OAM 64 256 K K STEL 2176 User Manual TABLE 5 PARAGRAPH PAGE KEY FEATURES ge eere osa ba esee teles 1
13. 50 load X 0 1 DACOUTN 4 Mini Circuits T 502 AVss Note 1 Normally some application dependent alias filtering and amplitude control appear at this point in the circuit WCP 53807 c 12 5 97 Figure 2 Example Output Load Schematic User Manual 7 STEL 2176 Introduction ELECTRICAL SPECIFICATIONS The STEL 2176 electrical characteristics are provided by Table 2 through Table 4 Stresses greater than those shown in Table 2 may cause permanent damage to the STEL 2176 Exposure to these conditions for extended periods may also affect the STEL 2176 reliability Tu DDmax Avppmax SV pmax AV Diss max Note Table 2 Absolute Maximum Ratings Symbol Storage Temperature Supply voltage on VDD Supply voltage on AVDD Supply voltage on 5VDD Analog supply return for AVDD Input voltage DC input current Power dissipation All voltages are referenced to Vss 5Vbp must be greater than or equal to Vs This rule can be violated for a maximum of 100 msec during power up All voltages with respect to and assume 40 to 125 0 3 to 4 6 0 3 to 4 6 0 3 to 7 0 10 of VDD 0 3 to 5VDD 0 3 30 1500 Table 3 Recommended Operating Conditions Supply Voltage Supply Voltage Supply Voltage DAC Load Capacitance DAC Load Resistance Recommended DAC Load DAC Output Voltage Op
14. 41 Symbol Mapper Block 5 ente 6 45 Nyquist BIR eo t entem tas redet tea toss 50 5 0 reete 50 lt __ _ 51 TOSBIE D A MR i o NGGONE 52 User Manual 1 STEL 2176 TABLE 5 PARAGRAPH PAGE CONTROL UNIT DESCRIPTION 52 2 corteo rte naa 52 Master Transmit Clock Generators aa Ga na Ga pee tet ag aa aa aga 52 Clock Generator oc ee eee eerte dte ue detect E 53 INGO soe oe e E E t foster teens Ets 53 TRANSMIT REGISTER 6 54 Programming the 2176 Transmit and Receive 1 54 Block 2 Upstream 109158618 Group hai anga anaa 54 TIMING 5 57 BURST TIMING EXAMPLES 65 RECOMMEN
15. ajan naja 53838 12 5 97 NOTE 1 STEL receivers differentially decode relative to the last preamble symbol To encode the first symbol against zero symbol reference instead bring TXDIFFEN high at the leading edge of the user data packet dotted line NOTE 2 If bit 6 of Block 2 Register 364 is 1 then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK dotted line This is required if the Reed Solomon encoder is used STEL 2176 67 User Manual Transmitter Description 5 5 BURST SIGNAL RELATIONSHIPS TXTCLK aaa 2 ZO ni TXDATAEN 1 1 TXTSDATA 9 Pi L a ai ca lt t GUARD PREAMBLE gt k uSER DATA kt GUARD TKDIFFEN TKRDSLEN NANI TXSCRMEN TXSYMPLS X X X ih TKDATAENO WCP 53821 12 5 97 SLAVE MODE OPSK FULL VIEW BURST TIMING SIGNAL RELATIONSHIPS XX 1 GUARD PREAMBLE gt 4 USER DATA gt GUARD TIME TXDIFFEN TXDATAENO WCP 53822 c 12 5 97 NOTE 1 STEL receivers differenti
16. Scrambler Frame synchronized sidestream Register 36 Bit 4 Type Set to zero User Manual 43 STEL 2176 Transmitter Description Reed Solomon Encoder The STEL 2176 uses a standard Reed Solomon RS Encoder for error correction encoding of the serial data stream The error correction encoding uses GF 256 and can be programmed for an error correction capability of 1 to 10 a block length of 3 to 255 and one of two primitive polynomials using the data fields listed in Table 37 When TXDATAENI is high and the RS Encoder is enabled the serial data stream both passes straight through the RS Encoder and also into encoding circuitry The encoding circuitry computes a checksum that is 2T bytes long for every K bytes of input data After the last bit of each block of K bytes of input data the RS Encoder inserts its checksum 2T bytes of data into the data path There is no adverse effect to letting TXTCLK or TXTSDATA continue to run during the checksum the data input will be ignored TXCKSUM will be asserted high to indicate that the checksum bytes are being inserted into the data stream and will be lowered at the end of the checksum data insertion The width of the TXCKSUM pulse is 2T bytes The STEL 2176 registers include two bits for determining the bit order for data into and checksum out of the RS Encoder circuitry Set these to match the Reed Solomon decoding circuitry along with the other parameters Table 37 Reed Sol
17. Format of the receiver output is MPEG 2 frames TRANSMITTER OVERVIEW The transmitter is highly integrated and flexible It receives serial data randomizes the data performs Forward Error Correction FEC and differential encoding maps the data to a constellation before modulation and outputs an analog RF signal It includes a 10 bit DAC and is capable of operating at data rates up to 20 Mbps in QPSK mode and 40 Mbps in 16QAM mode The transmitter uses a digital FIR filter to optimally shape the spectrum of the modulating data prior to modulation Signal level scaling is provided after the FIR filter to allow maximum arithmetic dynamic range The transmitter side offers QPSK and 16QAM modulation with frequencies from 5 to 65 MHz It can operate in continuous or burst mode And it can operate with very short gaps between bursts less than four symbols All digital interfaces support 3 3 volt and 5 volt logic User Manual Introduction MECHANICAL SPECIFICATIONS 208 PIN SQFP PACKAGE Dimensions are milimaers 30 60 0 20 28 00 0 20 PIN 1 IDENTIFIER ZONE 208 157 IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII GAGE PLANE SEATING PLANE _ 0 50 0 75 DETAIL A 0 090 0 200 mek 3 40 0 20 DETAIL DETAILA DETAILB 4 10 MAX j SN SEATING PLANE 0 50 zal TPG53310c 729 97 Table 1 STEL 2176 Pin Assignments Pin De
18. Table 34 BIT Encoding Data Path Options Register 56 Bits 65 Register 38 Bits 7 2 X X X X X X RS Encoder then Scrambler i XX XX XX Bypass RS Encoder XX XX XX Scrambler The scrambler can be used to randomize the serial data in order to avoid a strong spectral component that might otherwise arise from the occurrence of repeating patterns in the input data The Scrambler Figure 26 uses Pseudo Random PN generator to STEL 2176 42 1X 1X LX 11 10 0 generate PN code pattern 24 registers are presettable and any combination of the registers can be connected tapped to form any polynomial of up to 24 bits The scrambler may be either frame synchronized or self synchronized Table 35 shows the registers involved User Manual Transmitter Description enabled Internal delays on the TKSCRMEN control signal input allow for a rising edge to occur coincident with the rising edge of TXBITCLK that precedes the latching of the first data bit to be scrambled 24 0 1 2 3 22 23 24 _ _ 24 bit INIT Reg 24 bit Shift Reg The Mask Init and SSync fields can be programmed for different scrambler configurations For example the DAVIC Scrambler configuration shown in Figure 27 can be implemented by programming the Mask Init and SSync fields with the values indicated by Table 36 1 0 1 1 1
19. 12 5 97 TXNCOLD NCO LOADING AUTOMATIC ZERO SELECTED ZERO tDENHV 5 t DENLZ TKDATAENO IDOFCWV gt lt tDOFCWI WCP 53817 12 5 97 NOTE 1 The first rising edge of CLK after TXNCOLD goes high initiates the load process Table 57 NCO Loading AC Characteristics 3 3 10 Vss 0 V Ta 40 to 85 C Symbol NCO LD to Change Output 23 CLK cycles Delay TKFCWSEL to NCO LD Setup 3 CLK cycles TXFCWSEL to NCO LD Hold 10 CLK cycles TXDATAENO Low to Zero Frequency Out Delay 23 CLK cycles TENG TXDATAENO High to Valid Frequency Out 23 CLK cycles Delay TXDATAENO to TKFCWSEL Valid 3 CLK cycles TXDATAENO to TXFCWSEL Invalid 10 CLK cycles User Manual 63 STEL 2176 Transmitter Description DIGITAL OUTPUT TIMING CLK JU OU OU U U kd LT LT LT LT LI TXACLK ke tco 2 Note 1 lt tACKH ke PN TXSYMPLS tco gt ka WOP 53818 12 7 97 1 shown for equal to 2 where n is the 4 bit binary value Block 2 Register BITS 3 0 Table 58 Digital Output Timing
20. Enables or disables the pseudo random generator Selects one of two primitive polynomials for use with the Reed Solomon Encoder for encoding data Allows the Reed Solomon Encoder to be bypassed Selects software RSENBPB or hardware input 117 control for enabling the Reed Solomon Encoder A 24 bit word that is loaded into the PN generator to initialize its shift register A 24 bit word that is masks the output of the PN generator shift register Allows the Scrambler to be bypassed Selects software or hardware input pin 118 control for enabling the Scrambler Controls selection of the self sync or frame sync signal for routing back to the PN generator shift circuit Controls whether the input data is to be scrambled then encoded by the Scrambler and Reed Solomon Encoder or whether it is to be encoded then scrambled Selects one of five symbol mapping options when 160AM modulation is selected Sets the error correction capability of the error correction encoding Selects an externally generated clock for external control of data latching Determines whether the first input bit is the MSB or LSB of the byte applied to the RS Encoder 56 User Manual Transmitter Description TIMING DIAGRAMS CLOCK TIMING fq teek r m tCLKH tCLKL be 52787 12 5 97 Table 51 Clock Timin
21. 14 RECEIVE AND UNIVERSAL REGISTER 5 5 2 0 100 00 20 PROGRAMMING THE 2176 RECEIVE 5 0909099 20 REGISTER 20 Bank Universal Registers Group ini ues E a 20 Bank 0 QAM Demodulator Registers Universal Registers Group 2 2 0021 22 Bank 1 Registers Group cota Dan A 30 TIMING 2 E Se caw ea ce eed ones A Pad sede GN AE D bu 35 NO GAP PARALLEL Rm dues cate 35 6 6 _ _ lt _______ _ __ __ _ _ _ __ 35 GAPS PARAE E 5 La cach a 35 GAPS SERIATHMODE M a b Soe 35 TRANSMITTER esses ene eren ee ere e ERES e EYE NP ERE ER Pest aV A A 39 etre tutis ete nsa de ott 39 FUNCTIONAL BLOCK DIAGRAM 9 39 Tec 39 Bit SYNGBIOCK C 39 Bit ENCOGER Block ee Se er e odes snared Seed
22. 185 186 187 188 189 190 191 Pin Name RXPDATAOUT 4 VDD RXPDATAOUT 3 RXPDATAOUT 2 RXPDATAOUT 1 RXPDATAOUT O VSS RXOUTCLK VDD RXACQFLAG RXACQFAIL RXDECDFLG MESYNC RAMADDR IS5 RAMADDR 14 RAMADDR 13 MADDRII12 gt lt 1 on gt gt V gt WN MADDRIII RAMADDR IO 9 RAMADDRIS VDD MADDR 7 MADDRI6 MADDRI5 MADDRI4 eec gt gt ES R R R 23 gt EIS s MADDR 3 MADDR 2 WN 02 23 23 2p 7 6 5 RAMDATA 4 23129 gt gt 23 En ES a MDATA 3 MDATA 2 0 Na gt gt S es RAMWEB RAMCSB RAMOEB DD RXIENBLE RXOENBLE 55 VDD VSSA VDDA VCMA VDD o gt STEL 2176 Power Receive parallel output data Receive parallel output data Ground Io C 5 _ 5 Ground Ground Power __ __ O De Interleaver optional external SRAM address De Interleaver optional external SRAM address Ground le E an ng Power a _ 6 ees Ground 2222 2 22 O Bi directional
23. Frame Sync state machine goes into idle OP_ERR Setting the value to 1 enables flagging of data errors via the checksum in the Frame Sync byte SyncSymbol Used in Annex A only to input an arbitrary MPEG FRAME sync symbol normally 47 Bank 1 Group 3 Sub Group FrameSync Registers Table 27 Group 3 Sub Group E Read Write Registers Ades 7 5 4 3 2 1 os No Mineo a gt uoi mm INE 57 SyncSymbol 7 0 53 54 55 56 57 Table 28 Group 3 Sub Group E Read Only Registers gt L gt gt 1 IL 58 to 65 Factory Use Only Bank 1 Group 3 Sub Group D Register Data Field Descriptions Factory Use Only This data field is used by the factory and its function is not related to the STEL 2176 receive and transmit characteristics NoMissMode If NoMissMode is 1 then once Frame Sync is acquired the state machine will never go to the idle mode even if all data is bad ErrorTolEn If ErrorTolEn is 1 then all bits in the Frame Sync sequence must match the expected pattern This is for Annex B only ErrorTolerance Sets the number of bits that can be wrong in the Frame Sync sequence and have the sequence considered valid TRACK The number of frames the Frame Sync state machine must detect before telling the Viterbi that data should be realigned This is for Annex B only HIT The number
24. Interleaver as shown HAT j Input 5 13 Neu gt WCP 53704 10 28 97 Figure 12 De Interleaver I and J are programmable Block 1 Registers 474 and 48y total memory of J _ I 1 1 2 is required The STEL 2176 has 8K internal memory Up to 64K memory can be added externally without any additional logic as shown Reed Solomon Decoder This function decodes Reed Solomon blocks Each code block is 204 bytes long and contains 188 bytes of data STEL 2176 followed by 16 bytes of checksum The code blocks are assumed to be coded according to ITU T J 83 Annex A FEC shortened R S algorithm If the decoder fails to decode a code block the decoder sets the undecodable flag true for this block This flag propagates to the STEL 2176 output as RXDECDFLG In addition the number of errors in each decodable block accumulates Error_cnt 15 0 Block 1 Registers 72 and 73 This register can be reset by writing a 1 to CLR ERR bit 0 of Block 1 Register 74 De Handomizer The de randomizer is exactly the same as the randomizer described by the ITU T J 83 Annex A standard Output Clock Block The function of the output clock block is to evenly distribute the output receive data of the STEL 2176 and to eliminate gaps caused by the FEC subsystem The output of the Reed Solomon decoder is 188 bytes
25. MHz XO External RAM WCP 52861 5 07 97 Figure 3 STEL 2176 Receiver Block Diagram FUNCTIONAL BLOCKS ADC The ADC uses differential analog signal inputs ADCINP and ADCINN Differential coupling to the ADC is important to prevent common mode noise from the digital sections of the ASIC from coupling into the input The recommended input signal level is 0 75V The input is sampled by the ADC and the samples are converted into 10 bit digital values The sampling rate is typically 25 MHz for an input of 44 MHz 3 MHz with a symbol rate of about 5 MHz i e the MCNS standard or 29 MHz for an input of 36 MHz 4 MHz with a symbol rate of about 7 MHz i e the DAVIC and DVB standards The sampling rate is controlled the choice of crystal connected between RXOSCIN and RXOSCOUT or by the clock frequency applied to User Manual RXOSCIN The sample rate must be slightly more than 4 samples per symbol The sample clock generated by the crystal receive clock oscillator or applied to RXOSCIN must be a low phase noise signal For this reason dedicated power and ground connections for the receive oscillator and input buffer are adjacent to the RXOSCIN and RXOSCOUT pins Microcontroller Interface The microcontroller interface provides access to the internal programmable Universal Downstream Receive and Upstream Transmit registers see page 20 via a parallel or a SPI interface The interface used is selected the interface
26. TXDATAENI goes low on rising edge of TXTCLK on the cycle of TXTCLK after the last user data bit TXCLKEN must stay high until any time on or after the point where DATAENO goes low K DATAENO stays high until the 13th TXSYMPLS after TXDATAENI goes low L TXRDSLEN and TXSCRMEN go high on the first rising edge of TXTCLK in the User Data M TXRDSLEN goes low on the rising edge of TXTCLK last user data symbol N TXSCRMEN goes low on the rising edge of TXTCLK on the cycle of TXTCLK after the last user data bit 2 STEL 2176 66 User Manual MASTER MODE BPSK BURST TIMING SIGNAL RELATIONSHIPS TXCLKEN 1 I XX TXTCLK I TKTSDATA PI Pi PIT PI Tu Ut VI I CI GE Gt CI 4 GUARD TIME gt 4 t USER DATA 3 GUARD TIME TXDIFFEN I NOTE 1 TXRDSLEN N N N N N Y TXSCRMEN TXSYMPLS XX A J J TXDATAENO WCP 53837 c 12 5 97 SLAVE MODE BPSK BURST TIMING SIGNAL RELATIONSHIPS TXCLKEN TXTCLK TXDATAEN TXTSDATA P PI PI I CI CI CI CI lt 4 GUARD gt 4 gt t USER gt lt GUARD TIME gt TXDIFFEN TIME NOTE 1 TXRDSLEN NIS TXSCRMEN TXSYMPLS XX
27. Vss 0 V Ta 40 to 85 C ax Symbol Clock Period TXTSDATA to Clock Setup TXTSDATA to Clock Hold STEL 2176 Conditions 6 nsec 2 nsec 2 nsec 60 User Manual Transmitter Description WRITE TIMING WASU Address ADDR s oj tCSHD CSSU gt CS A twRHD IWRSU 8 n WRB tDSBL DSB Data DATAr 9j WCP 53814 c 12 5 97 Table 55 Write Timing AC Characteristics 3 3 1096 Vss 0 V Ta 40 to 85 C Symbol Write Address Setup Write Address Hold Address Valid Period tava we Chip Select CS Setup tcs Chip Select CS Hold tisu Write Setup WRB Write Hold WRB toss Data Strobe Pulse Width Data Hold Time Data Setup Time User Manual 61 STEL 2176 Transmitter Description READ TIMING 53815 C 12 2 97 Table 56 Read Timing AC Characteristics 3 3 1096 Vss 0 V Ta 40 to 85 C Symbol Address Valid Period 20 Address to Data Valid Delay 9 Address to Data Invalid Delay Data Valid After Chip Select Low Data Invalid After Chip Select High 1 STEL 2176 62 User Manual Transmitter Description NCO LOADING USER CONTROLLED OLD FREQ NEW FREQ tECWHD FCWSU gt TXFCWSEL4 9 DON T CAREX vaD XK DON T CARE tLDPIPE gt 1 53816
28. and depends on a control word from Frame Sync If Level2 is 0 level 1 interleaving is always 128 X 1 the control word does not matter ShadowMode There is 8 Kbytes of internal memory for the interleaver In normal operation the interleaver first fills up its internal memory then uses external memory If Shadow mode is 1 internal memory is bypassed addr 15 0 The address is used by the interleaver to access the SRAM For Annex A 256 QAM requires external SRAM TestMode The Interleaving type is set elsewhere by selecting QAM and Annex type Setting this register to 1 enables use of the I and J values stored in the I_test and J_test Read Write registers Bank 1 Group 3 Sub Group D MPEG FrameSync Registers Table 25 Group 3 Sub Group D Read Write Registers Address 7 5 4 3 2 155 SycSymbo ERR Table 26 Group 3 Sub Group D Read Only Registers Cadas 5 4 3 gt 3 Factory Use Only 2506 1 Factory Use Only Factory Use Only Factory Use Only STEL 2176 32 User Manual Receiver Description Bank 1 Group 3 Sub Group D Register Data Field Descriptions Factory Use Only This data field is used by the factory and its function is not related to the STEL 2176 receive and transmit characteristics HIT The number of Syncs that must be detected before data is output MISS The number of misses before the MPEG
29. complex modulators and multiplied by the sine and cosine carriers which are generated by the NCO The I channel signal is multiplied by the cosine output from the NCO and the Q channel signal is multiplied by the sine output The resulting modulated sine and cosine carriers are applied to an adder and either added or subtracted User Manual Transmitter Description together according to the register settings shown in Table 47 This provides control over the characteristics of the resulting RF signal by allowing either or both of the two products to be inverted prior to the addition Data Enable Output The TXDATAENO output is a modified replica of the TXDATAENI input TXDATAENO is asserted as a high 2 symbols after TKDATAENI goes high and it is asserted as a low 13 symbols after goes low In this way high on the TXDATAENO line indicates the active period of the DAC during transmission of the data burst However if the guard time between the current and next data burst is less than 13 symbols then the TXDATAENO line will be held high through the next burst Table 45 Interpolation Filter Bypass Control Number of Interpolation Filter Bypass Interpolation Stages Register 2B Bits 5 4 Selected iji 0 0M Table 46 Interpolation Filter Signal Level Control Gain Factor Filter Gain Control Relative Register 2A Bits 7 4 51 STEL 2176 Transmitter Description Table 47 Signal Inversion Con
30. e Internally generated PN code data is latched by the internal TXBITCLK Test mode See Table 33 for register settings to implement each mode TXBITCLK latches data on its falling edge TXTCLK latches data on its rising edge Whenever the TXCLKEN input is low the TXBITCLK output will stop There is also an auxiliary continuous clock TXACLK output which is discussed later in the clock generator section The TXACLK output is primarily for use in master mode where users may need a clock to run control circuits during the time between bursts When using slave mode the data that is latched by the rising edge of TXTCLK is re latched internally by the next falling edge of TXBITCLK which re synchronizes the data to the internal master clock Synchronizing TXBITCLK TXSYMPLS The synchronization circuit aligns the STEL 2176 TXBITCLK and its TXSYMPLS counter circuits to the beginning of the first user data symbol The circuit has two parts an arming circuit and a trigger circuit Once armed the first rising edge on the TXTCLK input will activate trigger the synchronization process The circuit can be armed in two ways taking TXCLKEN from low to high or toggling Block 2 Register 2 bit 0 from low to high to low again In a normal burst mode application the circuit is automatically re armed between bursts because User Manual goes low For applications that will not allow TXCLKEN to cycle
31. feedback equalizer coefficients Bank 0 Group 2 Sub Group F PLL Address Range Registers Table 19 Group 2 Sub Group F Read Write Registers am 7 5 5 1 6 Ti atii Defined Vale 28 SSCS Ti Ti D6 Ti _________________ E atii Defined Nahen F3 lateng behind Nala sa 1 3 HESWHSLWiek FESWESEWIDD E Factory Defined Factory Defined Value Ip E Factory Defined Value 7 PeeyDemdVawesS 27 Ti Ti Ti ma SSS 27 28 29 24 28 20 2E 25 30 31g 324 33 34 85 36 37 38 39 38 3C 3D 3E User Manual 29 STEL 2176 Description Table 20 Group 2 Sub Group Read Only Registers Address 7 6 5 4 3 2 1 60 to 684 Factory Use Only 7 0 DeltaPhase 15 8 Bank 0 Group 2 Sub Group F Register Data Field Descriptions DeltaPhase 15 0 Specifies the initial value for the PLL s phase increment Factory Defined Value The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values m
32. il 68 e Receiver Description Bank 0 Group 2 Sub Group B DDC Nyquist AGC and AFC Address Range Registers Table 11 Group 2 Sub Group B Read Write Registers Address 7 6 5 1 1 2 OF Factory Defined Value 34 UpdateEn Correct_ NAGA 104 DeltaTheta_in 5 0 CorrectEn Update_ DeltaTheta_in 13 6 H 124 GainSel Nyquist_AlphaSel AGC InvertOu AGC Invert tputB OutputA Factory Defined Value 00 14 AGC_ThresholdA AGC_ThresholdB Factory Defined Value 26 16 QAM 37 64 QAM or 3C 256 QAM Factory Defined Value 524 Signal BW 5MHz or 3B Signal BW 7MHz H AFC_Cntr_stop1 AFC_Cntr_stop2 1B WARNING SHOULD NOT BE PROGRAMMED BY THE USER Table 12 Group 2 Sub Group B Read Only Registers Address 7 6 5 4 3 2 I 3 46 Factory Use Only 474 Factory Use Only 48 DDC DeltaTheta 3 0 49 DDC_DeltaTheta 11 4 4 Use Only DDC_DeltaTheta 13 12 4B Factory Use Only 4C Factory Use Only 4 Factory Only Factory Use Only STEL 2176 24 User Manual Receiver Description Bank 0 Group 2 Sub Group B Register Data Field Descriptions AFC_Cntr_stop1 7 0 AFC_Cntr_stop2 7 0 GainSel 3 0 AGC_InvertOutputA AGC_InvertOutputB AGC PowerEstimate 9 0 AGC ThresholdA 7 0 ThresholdB 7 0 Correct addsub Update ad
33. low between bursts some system level precautions should be observed to maintain synchronization of user data to the STEL 2176 TXBITCLK Once triggered the sync circuit re starts the TXBITCLK and TXSYMPLS counters The TXBITCLK output starts high and TXSYMPLS resets to the start of a symbol There is a delay equal to about three cycles of the master clock from the rising edge of the TXTCLK input before this re start occurs During this brief delay period the TXBITCLK and TXSYMPLS counters are still free running and may or may not have transitions In master mode the rising edge of TXTCLK normally marks the transition of the first user data bit which will be latched in by the next falling edge of TXBITCLK In slave mode the first user data bit must already be valid at this first rising edge of TXTCLK Bit Encoder Block The Bit Encoder Block consists of a Scrambler a Reed Solomon Encoder and data path controls multiplexers as shown in Figure 25 Data Path Control Multiplexers The STEL 2176 provides a great deal of flexibility and control over the routing of data through or around the encoding functions With appropriate register selections data can be routed around bypass both encoders through either one and around the other through the scrambler then the RS Encoder or through the RS Encoder and then the scrambler Control over the bypassing can be set for software control or external user input signal contro
34. of data for every 204 input bytes Therefore there is a gap of 16 bytes where the checksum information is removed The STEL 2176 output can send the received data in bytes on an 8 bit wide buss or in bits on a single line as shown in Downstream Output Timing Diagrams Figure 19 through Figure 21 Selecting between bytewise versus bitwise can be done by setting Serial Mode bit 0 of Bank 1 Register 69 to 1 ANNEX B The ITU T J 83 Annex B FEC subsystem consists of the following blocks 1 Q from Adaptive zm rellis Equalizer Coded Frame De modulator Sync Reed Solomon Decoder De Randomizer To Output Clock MPEG 2 Framing De Interleaver WCP 53705 c 10 28 97 Figure 13 ITU T J 83 Annex B FEC Subsystem 16 User Manual Receiver Description Frame Sync Buffer 28 bits 64QAM 38 bits 256 QAM 1 2 Binary Differential Convolutional Y Decoder Decoder 4 5 punctured WCP 53706 10 28 97 Figure 14 Trellis Coded Demodulator The demapping block maps the Adaptive Channel bits for 16 64 or 256 QAM respectively The mapping Equalizer I and outputs for each symbol into 4 6 or8 tables are as follows Q T T 110 111 111 011 010 111 011 011I100 101 101 111 110 101 111 111 011 000 100 000 101 010 110 000 111 010 110 100 111 000 010 100 100 111 101 011 000 100 001 011 000 101 001 111 010 101 011 111 i
35. of the filter linear This also eliminates the inter symbol interference that results from group delay distortion In this way it is possible to change the carrier frequency over a wide frequency range without having to change filters thus providing the ability to operate a single system in many channels The STEL 2176 can operate with very short gaps between transmitted bursts to increase the efficiency of Time Division Multiple Access TDMA systems The STEL 2176 operates properly even when the interburst gap is less than four 4 symbols half the length of the FIR filter response In this case the The STEL 2176 utilizes advanced signal processing p uc which are covered by 5 Patent Number PRODUCT INFORMATION 20 Transmitter Description postcursor the previous burst overlaps and is superimposed on the precursor of the following burst Signal level scaling is provided after the FIR filter to allow the STEL 2176 s maximum arithmetic dynamic range to be utilized Signal levels can be changed over a wide range depending on how the device is programmed In addition the STEL 2176 is designed to operate from a 3 3 power supply and the chip can be interfaced with logic that operates at 5 Vdc FUNCTIONAL BLOCK DIAGRAM DESCRIPTIONS The STEL 2176 is comprised of the Data Path see page 39 and Control Unit see page 52 sections shown in Figure 24 The Data Path is comprised of a Bit Sync Block Bit Encod
36. output is low QPSK In QPSK mode the next output dibit is found by XORing the input dibit with the current output dibit Table 40 shows the results of the differential encoding performed for QPSK modulation and the resulting phase shift In the table I I and Q 16QAM In 16QAM mode the differential encoding algorithm is the same as in QPSK Only the two MSB s I and are encoded The output bits and are set equal to the inputs bits I and Table 40 OPSK Differential Encoding and Phase Shift Current Input Current Output Next Output Phase Shift 10 10 degrees qo 01 10 11 01 10 11 01 10 11 01 10 11 STEL 2176 w NT Ne 46 User Manual Symbol The Symbol Mapper receives I Q Ij of each symbol Based on the signal modulation and the symbol mapping selection the Symbol Mapper block maps the symbol to a constellation data point 1 0 The Symbol Mapping field bits 7 5 of Block 2 Register 2 will map the four input bits to a new value as indicated in Table 41 BPSK and QPSK For BPSK and QPSK the settings of the symbol to constellation mapping bits is ignored The constellations for BPSK Figure 29 and QPSK Figure 30 are shown below values are indicated by large bold font 00 and 11 and 1 Q values by the smaller font 00 an
37. reset 25 STEL 2176 Receiver Description Bank 0 Group 2 Sub Group C Timing Address Range Register Table 13 Group 2 Sub Group Read Write Registers Address 7 5 gt 4 9 Factory Defined Value 144 Ratio in 5 2 Factory Defined Value 34 Ratio_in 13 6 Ratio_in 21 14 Factory Defined Value 42 Table 14 Group 2 Sub Group C Read Only Registers gt I I HE Factory Use Only Coa 2 1 Pwrlvl PowerEstimate 6 0 Factory Use Only 5B Use Only Pwrlvl_powerEstimate 10 7 Bank 0 Group 2 Sub Group C Register Data Field Descriptions Factory Defined Value The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values must be written to the data field Factory Use Only This data field is used by the factory and its function is not related to the STEL 2176 receive and transmit characteristics Pwrlvl_powerEstimate 10 0 Ratio_in 21 2 Ratio_out 21 0 Bank 0 Group 2 Sub Group D FFE Address Range Registers Table 15 Group 2 Sub Group D Read Write Registers MO gt M Defined Value DDenable UpdateEn CenterTapAddr 16 QAM 264 34 256 QAM Factory Defined Value
38. the DAVIC 256 OAM demapper Factory Defined Value The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values must be written to the data field Bank 1 Group 3 Sub Group B De Randomizer Registers Table 22 Group 3 Sub Group B Read Only Registers L gt gt Not Used DataOut 6 0 Bank 1 Group 3 Sub Group B Register Data Field Descriptions DataOut Bank 1 Group Sub Group De Interleaver Registers Table 23 Group 3 Sub Group Read Write Registers amm 7 LI gt x C ShadowModc I test Table 24 Group 3 Sub Group Read Only Registers Ade 7 1 5 4 3 2 1 43 44 User Manual 31 STEL 2176 Receiver Description Bank 1 Group 3 Sub Group C Register Data Field Descriptions I test Read Write The I value used during test mode I test Read Only Read register that permits looking at I value when the interleaver is running during test J test Read Write The value used during test mode J test Read Only Read register that permits looking at J value when the interleaver is running during test Level2 There are two distinct operating modes of interleaving for Annex B If Level2 is 1 the depth of interleaving is variable
39. wm 30 00 7 3m ton 2000 _ IC mr pom STEL 2176 48 User Manual Transmitter Description 52990 4 26 97 Figure 32 Gray Coded Constellation Figure 34 DAVIC Coded Constellation 11 52989 4 26 97 52991 4 26 97 Figure 35 Right Coded Constellation User Manual 49 STEL 2176 Transmitter Description Nyquist FIR Filter The finite impulse response FIR filters are used to shape each transmitted symbol pulse by filtering the pulse to minimize the sidelobes of its spectrum The Symbol Mapper Block outputs the 1 1 data to a pair of I channel FIR filters and the Q Q data to a pair of Q channel FIR filters Figure 36 shows the filter block diagram for a channel pair I or Q The FIR filter can be bypassed altogether or in BPSK or QPSK modes individual channels can be turned on and off which changes the effective filter gain Table 43 shows the various FIR configuration options Table 43 FIR Filter Configuration Options Register 2E Register 2C Mode Gain Bits 4 1 Bit 1 160 1010 BPSK OPSK Each of the 32 tap linear phase FIR filters use 16 ten bit coefficients which are completely pro grammable for any symmetrical mirror image poly nomial The FIR filter coefficients are stored in addres
40. 0 0100 0101 0100 0101 0100 0101 0101 0001 0011 0101 0111 1001 1011 1101 1111 0111 0110 0111 0110 0111 0110 0111 2210 0100 0110 1000 1010 1100 ag T 1000 1001 1000 1001 1000 0101 0111 1001 1011 1101 190 aa 1011 1010 1011 1010 1011 1010 1011 0000 0010 0100 0110 1000 1010 1100 111 1100 1101 1100 1101 1100 1101 1100 1101 0001 0011 0101 0111 1001 1011 1101 1111 0001 1110 1111 1110 1111 1110 1111 1110 1111 1110 0000 0010 0100 0110 1000 1010 1100 1110 WCP 53710 C 10 29 97 Figure 16 256 QAM Mapping The de mapper generates q bits for each symbol where q 6 for 64 QAM and q 8 for 256 QAM Two bits and 2 are processed by the binary convolutional decoder and the differential decoder The remaining bits are passed directly to the output buffer Viterbi Decoder The binary convolutional decoder is a 1 2 Viterbi decoder 4 5 punctured For every 5 consecutive input b or b 2 bits the Viterbi decoder produces only 4 output bits With this type of punctured code there are 5 possibilities for synchronization The synchronization can occur automatically or under manual control using the programmable registers Setting VitFeedBackEn bit 4 of Bank 0 Register F4 to 1 selects the automatic mode while setting it to 0 selects the manual mode In th
41. 0111 000110 010110 010111 010011 010010 rotate 90 degrees 10 000000 000001 000101 000100 010100 01010 8 8 2 8 8 8 8 rotate 180 degrees 11 rotate 270 degrees 1 WCP 53839 12 5 97 Figure 10 256 QAM Constellation DVB IEEE 802 14 I Tk Qk Ox 1 ly Qi 1 1001 Demapper Differential Decoder WCP 53708 10 28 97 Figure 11 Demapper 15 STEL 2176 Receiver Description Frame Sync The frame sync receives symbols from the mapper Each symbol represents 4 6 or 8 bits for 16 QAM 64 QAM and 256 QAM respectively These bits are collected into bytes For 16 QAM every two symbols are converted into one byte For 64 QAM every 4 symbols to are converted into 3 bytes and for 256 QAM each symbol gives one byte Once bytes are formed the frame sync block looks for a sequence of fixed byte values separated by 203 bytes of data 47 203 bytes 8 203 bytes 47 203 bytes 47 203 gc Ma uA When the frame sync finds this pattern HIT Block 1 Register 55 times the frame sync block declares acquisition and starts feeding the bytes to the De Interleaver The frame sync stays in the acquisition state until it misses this pattern MISS Block 1 Register 56 times De Interleaver This block is a convolutional De
42. 111 0000 0011 0100 0111 1000 1011 1100 1111 1111 1101 1011 1001 0111 0101 0011 0001 0111 0111 0111 0111 0111 0111 0111 0111 0100 0101 0100 0101 0100 0101 0100 0101 0000 0011 0100 0111 1000 1011 1100 1111 1110 1100 1010 1000 0110 0100 0010 0000 0100 0100 0100 0100 0100 0100 0100 0100 0010 0011 0010 0011 0010 0011 0010 0011 0000 0011 0100 0111 1000 1011 1100 1111 1111 1101 1011 1001 0111 0101 0011 0001 0011 0011 0011 0011 0011 0011 0011 0011 0000 0001 0000 0001 0000 0001 0000 0001 0000 0011 0100 0111 1000 1011 1100 1111 1110 1100 1010 1000 0110 0100 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 1101 1010 1001 0110 0101 0010 0001 0000 0001 0000 0001 0000 0001 0000 0001 0001 0001 0001 0001 0001 0001 0001 0001 0001 0011 0101 0111 1001 1011 1101 1111 1110 1101 1010 1001 0110 0101 0010 0001 0010 0011 0010 0011 0010 0011 0010 0011 0010 0010 0010 0010 0010 0010 0010 0010 0000 0010 0100 0110 1000 1010 1100 1110 ae 1101 1010 1001 0110 0101 0101 0101 0101 0101 C 1010 1001 0110 0110 0110 0110 0 0001 010
43. 26 97 Figure 36 Nyquist FIR Filter 50 User Manual Data Enable Bypass 22 16 3 Stage Differentiator 3 Stage Sample Integrator Clock Gain Control 7 Master Clock WOP 52993 c 5 2 97 Figure 37 Interpolation Filter Block Diagram will overflow which will destroy the output spectral characteristics To compensate for this the interpolation filter has a gain function This gain is normally set empirically If the output spectrum is broad band noise or if it appears correct but has regular momentary hits of broad band spectral noise then the digital gain is too high The interpolation filter gain is the first place to adjust gain because it does not directly affect the shape of the signal spectrum and it has a very wide adjustment range Overall gain can affected in the FIR filter function the interpolation gain function and by the number of interpolation stages and therefore accumulators used Normally three interpolation stages are used but there is a bypass option for use when the interpolation is very high It should be used only as a last resort after all other gain reduction options have been exercised because of the severe impact to spurious performance The register bits that affect the interpolation filter functions are shown in Table 45 and Table 46 Modulator The interpolated I and Q data signals are input from the Interpolation Filter fed into two
44. 50 Transmit Block 2 Register Data 5 ee 55 51 Clock Timing ara Cen see 57 52 Pulse Width AC 58 53 Bit Clock Synchronization 59 54 Input Data and Clock AC Characteristics ie ed 60 55 Write Timing AC Chatacteristics 61 56 Read Timing AC Characteristiesu ans oes ote 62 57 NCO Loading AC Characteristics 63 58 Digital Output Timing AC Chiara cherishes iade 64 59 TXDATAENI to TXDATAENO Timing Characteristics 65 User Manual STEL 2176 5 10 bit A D on 16 64 256 QAM demodulation Selectable ITU T J 83 Annex A Annex B forward error correction FEC MCNS IEEE 802 14 preliminary DAVIC DVB compliant Parallel or serial output data with or without gaps Viterbi decoder for Annex B Selectable Reed Solomon decoder for Annex A and Annex B Programmable De Interleaver Programmable De Randomizer MPEG 2 Framing TRANSMITTER Patented U S Patent 5 412 352 Complete BPSK QPSK 16QAM modulator Complete upstream modulator solution serial data in RF signal out Programmab
45. AC Characteristics 3 3 10 Vss 0 V Ta 40 to 85 C Symbol Clock to TXBITCLK TXSYMPLS TXDATAENO 2 edge Auxiliary Clock TXACLK High 2 CLK cycles Auxiliary Clock TXACLK Low n 1 CLK cycles Symbol Pulse TXSYMPLS High 1 CLK cycles TXBITCLK Low to TXDATAENO edge 1 CLK cycles Notes 1 is the 4 bit binary value in Block 2 Register 2 bits 3 0 STEL 2176 64 User Manual Transmitter Description TXDATAENI TO TXDATAENO TIMING iDENSP gt 4 TXDATAENI tDIHDO gt 9 22 ISPDEN gt is cl pu tsPDEN gt gt 4 o A lt 4 Table 59 TXDATAENO Timing AC Characteristics 3 3 10 Vss 0 V Ta 40 to 85 Symbol 258 TXSYMPLS 13 TXSYMPLS 3 nsec 5 nsec TXDATAENI High to TXDATAENO High TXDATAENI Low to TXDATAENO Low TXSYMPLS trailing edge to TXDATAENI Setup TXDATAENI to TXSYMPLS trailing edge Setup tompo tsppen toensp Notes WCP 53819 c 12 5 97 1 Shown for Block 2 Register 36 bit 6 0 No Reed Solomon If bit 6 of Register 36 is a 1 then the edges of TXDATAENO will be delayed from those illustrated by 8 4 or 2 TXSYMPLS for BPSK QPSK or 16QAM respectively Key BURST TIMING EXAMPLES y gt WAVEFORM INPUTS The following seven timing diagrams are qualitative in nature and meant to illu
46. DED INTERFACE 5 70 STEL 2176 11 User Manual LIST OF FIGURES FIGURE PAGE 1 Reteterice 50 L 7 Example Output Load Schematics 7 3 STEL 2176 Receiver Block Diagram 10000 11 4 Master Receive Clock ee 12 5 QAM Demodulator Blocks 3 5 2 tiet d tne ee erede 13 6 LEWAT 9 83 AnnexA REC 14 7 16 Constellation sos oo ise Aide cea feste eases 15 8 641 OAM Constellation det o e ee ie a 15 9 256 QAM Constellation DAV IC a dee kae oen doe eee ede 15 10 256 QAM Constellation DVB IEEE 802 14 rie teet bor rts 15 11 Demapper 15 12 16 13 ITU T 4 83 Annex B FEC SUubSyVStetnsc soie te ben s Mesi cce ie ped 16 14 Trellis Coded tea dus 17 15 Mapping ME 17 16 256 Mapping 5 a Susie LI REE aaa e 18 17 Derandomiz t aa E EU GENTE A E ws 19 18 este e ed tee Peur 19 19 Downstream Output Timing Parallel Data Output 2 2 36 20 Downstream Output Timing
47. De Interleaver Interleaving is used in the FEC standards to improve performance when the channel contains bursty noise Since the transmitter Interleaver spreads the data over a large time when the receiver performs the matched operation to the Interleaver in order to bring the data back into the correct time sequence any burst errors appear to be spread out in time This helps makes these errors 10 User Manual correctable by the FEC STEL 2176 internal memory can support all MCNS Interleaver configurations For deeper interleaving a direct interface to external memory is provided The output of the receiver is typically arranged as MPEG 2 frames although the MPEG 2 framing can be 1st IF Output 44 MHz Receiver Description by passed for ATM applications The output can be 8 bit parallel with a byte clock or serial with a bit clock The data can be output in a smooth fashion without inter frame gaps or with the pauses in output data caused by the FEC system passed through to the output see Receiver Timing discussion Fo 44 36 MHz BW2 6 8 MHz N Programmable Nyquist 0 12 to 0 2 Micro Controller Interface Micro Controller SPI Parallel H s amp o 2 10 bits Sample Recovery Adaptive Channel Equalizer 20 taps De mapper Reed Solomon Viterbi Diff Decoder Clock Decoder 204 188 and 128 122 Frame Sync Deinterleaver Synthesizer 25
48. LS signal output is intended to allow the user to verify synchronization of the external serial data TXTSDATA with the STEL 2176 symbol timing TXSYMPLS is normally low and pulses high for a period of one CLK cycle at the point where the last bit of the current symbol is internally latched by the falling edge of the internal BIT Clock TXBITCLK signal Refer to the Timing Diagrams section The internal TXBITCLK period is a function of the MOD field bits 3 2 of Block 2 Register 2 which determines the signal modulation TXBITCLK has a 50 duty cycle for BPSK and QPSK modes It also has 50 duty cycle in 160AM mode when is even If N 1 is odd then TXBITCLK will be high for N 2 1 clocks and then low for 2 clocks Refer to the Bit Clock Synchronization Timing diagram in the Timing Diagrams section 3 lt lt 4095 The TXBITCLK frequency is determined by CLK K 1 for 16QAM BITCLK 2 for QPSK N 1 K 4 for SES 3 lt N x 4095 NCO A 24 bit Numerically Controlled Oscillator NCO is used to synthesize a digital carrier for output to the Modulator The NCO gives a frequency resolution of about 6 Hz at a clock frequency of 100 MHz The NCO also uses 12 bit sine and cosine lookup tables LUTs to synthesize a carrier with very high spectral purity typi cally better than 75 dBc at the digital outputs 53 STEL 2176 Transmitter Description The STEL 2176 provides register space for three dif
49. MHz For MCNS and DAVIC standards 44 MHz and 36 MHz are the two typical IF frequencies used For 44 MHz the corresponding bandwidth is 6 MHz for 36 MHz the corresponding bandwidth is 8 MHz Sampling of the input may be set for 25 MHz for the 6 MHz bandwidth or 29 MHz for the 8 MHz bandwidth The downstream receiver offers 16 64 256 QAM demodulation for Annex A associated with DAVIC or Annex B associated with MCNS It also offers a variety of choices for the data and clock outputs frames with or without gaps and parallel or serial data The incoming signal is sampled The timing recovery circuit determines the epoch of each symbol Automatic frequency and gain control circuitry correct the frequency and amplitude of the signal and a Digital Down Converter DDC brings the alias band associated with sampling down to zero A Nyquist filter eliminates inter symbol interference and an Adaptive Channel Equalizer ACE corrects for channel distortion while fine tuning the signal A demapper transforms the modulated signal back into symbols and a De STEL 2176 Interleaver puts the data bits back into the original order while Trellis and Reed Solomon decoders handle error correction For Annex A a Reed Solomon decoder decodes and corrects every 204 bytes in 188 bytes For Annex B there is a Viterbi decoder and a 128 122 code word length information 7 bit Reed Solomon decoder A de randomizer is used to unscramble the data stream
50. PREAMBLE _ jat USER DATA lt GUARD TIME gt TXDIFFEN NOTE 1 TXDATAENO WCP 53824 c 12 5 97 STEL 2176 69 User Manual Transmitter Description RECOMMENDED INTERFACE CIRCUITS SLAVE MODE INTERFACE TSDATA TKTSDATA TXDATAENO DATAEN TXDATAEN 530625176 DIFFEN TXDIFFEN FCWSEL TXFCWSEL o TCLK TXTCLK WCP 52995 c 5 2 97 TSDATA TXTSDATA BITCLK DATAENI TXDATAENI STEL 2176 DIFFEN TXDIFFEN TXTCLK TXCLKEN 52115A c 5 2 97 TXCLKEN may be turned off between bursts to conserve power as long as it is kept on until after TXDATAENO goes low Note that the TXBITCLK output goes inactive whenever TXCLKEN is low STEL 2176 70 User Manual Information in this document is provided connection with Intel products No license express or implied by estoppel or otherwise to any intellectual property rights is granted by this document Except as provided in Intel s Terms and Con ditions of Sale for such products Intel assumes no liability whatsoever and Intel disclaims any express or implied Intel may make changes to specifications and product de scriptions at any time without notice For Further Information Call or Write Intel INTEL CORPORATION Cable Network Operation warranty relating to sale and or use of Intel products in cluding liability or warranties relating t
51. Serial Output a eiectus eno ER ates v ln 36 21 Downstream Output Timing Parallel Data Output seem 37 22 Downstream Output Timing Parallel Data Output eerte eerte 38 23 De Interleaver External SRAM sss ee 38 24 STEL 2176 Transmitter Block 40 25 Bit Encoder Functional 42 26 Scrambler Block Diagram rop Hie rye qe vieta 43 27 D AVIG Scrambler 4 d ies eee Der ertet gaga 43 28 Mapping Block Functional Diagram ssssssee 45 29 I II 8 M L IX 47 30 QPSK 47 31 Natural Mapping 48 32 Gray Coded _ _ 49 33 Left Coded Constellations reeeo ag an 9 49 34 DAVIC Cod d Constellation isa span a aia a ang na aapa 49 35 Right Coded s 49 36 Nyguist PIR Filters oio eret eo pt ute E eset 50 37 Interpolation Filter B
52. able or disable access operations to the STEL 2176 When a high is asserted on CS all access operations are disabled and a low is asserted to enable the access operations The CS input only affects Block 2 Register access and has no effect on the data path The Data Strobe DSB input signal is used to write the data that is the data bus DATA into the Block 2 STEL 2176 clock and outputs a direct analog RF signal at a frequency of 5 to 65 MHz The DAC outputs DACOUTP and DACOUTN are complementary current sources designed to drive double terminated 50Q or 750 250 or 37 5Q total load to ground The nature of digitally sampled signals creates an image spur at a frequency equal to the Master Clock minus the output RF frequency This image spur should be filtered by a user supplied low pass filter For best overall spurious performance the gain of the STEL 2176 should be the highest possible before digital overflow occurs see Interpolation Filter discussion Register selected by ADDR Write Read WRB input signal is used to control the direction of the Block 2 Register access operation When WRB is high the data in the selected Block 2 Register is output onto the bus When WRB is low the rising edge of DSB is used to latch the data on the bus into the selected Block 2 Register Refer to the Write and Read Timing diagrams in the Timing Diagrams section Some of the Block 2 Reg
53. ally decode relative to the last preamble symbol To encode the first symbol against a zero symbol reference instead bring TXDIFFEN high at the leading edge of the user data packet dotted line NOTE 2 If bit 6 of Block 2 Register 36 is 1 then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK dotted line This is required if the Reed Solomon encoder is used STEL 2176 68 User Manual MASTER MODE 16QAM BURST TIMING SIGNAL RELATIONSHIPS TXCLKEN TKDATAENI TXTSDATA s PO Po Pool posuopaqus also ped BoTscpog 4 GUARD TIME gt lt PREAMBLE gt 4 5 DATA gt GUARD TIME gt TXDIFFEN NOTE 1 WCP 53823 c 12 5 97 NOTE 1 STEL receivers differentially decode relative to the last preamble symbol To encode the first symbol against a zero symbol reference instead bring TXDIFFEN high at the leading edge of the user data packet dotted line NOTE 2 If bit 6 of Block 2 Register 364 is 1 then the rising edge of DATAENO will be delayed by eight cycles of TXBITCLK dotted line This is required if the Reed Solomon encoder is used SLAVE MODE 16QAM BURST TIMING SIGNAL RELATIONSHIPS TXCLKEN TXDATAENI TXTSDATA Pu Fee Pool Ph 069960 e to fSg 4 GUARD TIME gt
54. aps of the FIR filter to Coefficients control its filter characteristics FZSINB Controls the sine component of the NCO output Setting the field to 0 rotates the User Manual constellation by 45 for on axis modulation of a BPSK signal 55 STEL 2176 Transmitter Description Interpolation Filt Bypass Interpolation Filter Gain Control Invert I Q Chan K LDLSBF LSB Sampling Rate Control MOD NCO PN Code Sel PN On Off PPolynomial RSENBPB RSENSEL SCRAMBLER Init Registers SCRAMBLER Mask Registers SCRMENBPB SCRMENSEL Self Sync S RS Symbol Mapping T TCLK Sel TRLSBF STEL 2176 Controls the number of filter stages the Interpolation Filter will use for filtering the signal Sets the gain of the Interpolation Filter Controls the signal inversion of the I and Q channels by using an adder to add or subtract the two channels Defines the length of the User Data Packet in bytes Determines whether the MSB or LSB of the checksum byte is to be output as the first bit of the serial output data A 12 bit word that controls the sampling rate of the 10 Bit DAC Register 29 contains the 8 LSBs and Register 39 contains the 4 MSBs Selects type of modulation BPSK QPSK or 160AM Three 24 bit frequency control words The word selected for setting the frequency of the NCO carrier is selected by the input pins TXFCWSEL 1 0 Selects one of two PN codes when pseudo random generator is enabled
55. ble flag true for this block This flag propagates to the STEL 2176 RXDECDFLG output In addition the number of errors in each decodable block accumulates in Error cnt 15 0 Bank 1 Registers 72 73 This register can be reset by writing a 1 to CLR ERR bit 0 of Bank 1 Register 74 MPEG Framing The 5 decoder s output is serialized and fed through the ITU T J 83 Annex B MPEG 2 syndrome converter The output of the syndrome generator is monitored for the pattern of 47 separated by 1496 bits When n n is a programmable number successive occurrences of this pattern are found MPEG 2 frame sync is declared MPEG 2 packets are framed by converting every 8 bits into one byte After declaring successful MPEG 2 frame sync the absence of a valid code word at the expected location is indicated as a packet error 2 framing be bypassed if so selected In this case the output of the 5 decoder will be reformed into bytes starting at the beginning of each frame Output Clock Block The output clock block functionally the same as the Annex A output clock block However the gaps between data bytes occur due to eliminating the R S checksum symbols the frame sync information and the bits that were added to support Viterbi decoding 19 STEL 2176 Description RECEIVE AND UNIVERSAL REGISTER DESCRIPTIONS PROGRAMMING THE 2176 RECEIVE FUNCTIONS The STEL 2176 has a combinatio
56. d 11 16QAM For 160AM modulation the Symbol Mapper maps each input symbol to one of the 16QAM constellations The specific constellation is programmed by the Symbol WCP 52999 c 10 29 97 Figure 29 BPSK Constellation User Manual Transmitter Description Mapping field bits 7 5 of Block 2 Register 2E to select the type of symbol mapping If the MSB of the Symbol Mapping field is set to 0 the mapping will be bypassed and 1010 I CI I C The resulting constellation Figure 31 is the natural constellation for the STEL 2176 If the MSB of the Symbol Mapping field is set to 1 bits 6 5 can select any of four possible types of symbol mapping Gray DAVIC Left or Right as indicated by Table 41 Table 42 summarizes the symbol mapping and the resulting constellations are shown in Figure 31 and Figure 32 In these figures are indicated by large bold font 00 01 10 and 11 and 1 Q by the smaller font 00 01 10 and 11 10 WCP 52986 c 10 29 97 Figure 30 QPSK Constellation 47 STEL 2176 Transmitter Description Table 41 Symbol Mapping Selections Mapping Register 2E Selection Bits 7 5 100 DAVIC 101 01 WCP 52987 c 10 29 97 Figure 31 Natural Mapping Constellation Table 42 Symbol Mapping Natural Mapping Bypass LI MM 8 _ wm _ o mw XI w
57. d into two groups of registers which yields a total of four register groups Table 49 shows the Bank Address that must be written to location in order to access the respective register group The registers comprising The Bank 0 and Bank 1 registers are described in the Receiver Section see page 20 The registers comprising Bank 2 are described below When the Bank 2 Group 4 registers are accessed the hexadecimal register addresses listed in Table 50 are sent to the Microcontroller Interface see page 11 for doing a read or write operation on a specific register Table 49 Addresses of the STEL 2176 Register Groups Group Bank Group Name Bank Address location FF Demodulator Registers Universal Registers Downstream FEC Registers _ Upstream or transmitter Registers Block 2 Upstream Registers Group 4 Description Each of the Block 2 registers see Table 50 is an 8 bit Read Write register and each register contains more data fields described below The data fields are STEL 2176 H 00 00 01 24 the transmit parameters which control the transmit characteristics of the STEL 2176 When a transmit parameter requires more than 8 bits it is stored in multiple data fields and stored used two or more registers 54 User Manual Transmitter Description Table 50 Transmit Block 2 Register Data Fields _ 2 ______ ENDAC _ PNsd_
58. ddress 7 6 5 4 3 2 Factory Defined Value Annex A 804 Annex Ca Nawa _ OutputDataatc 1 4 Table 31 Group 3 Sub Group G Read Only Registers Address 7 6 5 4 3 2 T _ AS Error_cnt 15 8 STEL 2176 34 User Manual Description Bank 1 Group 3 Sub Group G Register Data Field Descriptions Factory Defined Value The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values must be written to the data field CLR_ERR Error_cnt 15 0 Clears the Error_cnt register Error_cnt 7 0 is byte 0 of the number of errors found in a block and Error_cnt 15 8 is byte 1 of the number of errors found in a block OutputDataRate Register FE 3 0 When Register FE 3 0 is TIMING The basic input to the receiver is an analog input basic outputs consist of data serial or parallel an output clock and a frame sync These outputs are shown in the four timing diagrams that follow There are four output modes depending on whether there are gaps between frames and depending on whether the data output is parallel 8 bit or serial The addition of the Read Solomon checksum creates gaps in the transmission of the MPEG 2 frame But the STEL 2176 provides the option of spreading the gap over a frame so there appea
59. der TKDIFFEN WCP 53810 12 2 97 Figure 28 Mapping Block Functional Diagram Transmitter Description Bit Mapper The Bit Mapper receives serial data and maps the serial data bits to output symbol bits L I and There are four output bits per symbol even in BPSK and QPSK modes In BPSK all bits are set equal to each other In QPSK each input symbol bit drives a pair of output bits The four symbol bits are routed to the Differential Encoder in parallel For BPSK modulation each bit symbol by of the input serial data stream is mapped directly to 1 7 0 II ie lI Q Thus bit mapping has no affect on the respective value of the symbol s four bits as shown in Table 38 For QPSK modulation each pair of bits a dibit forms a symbol b The QPSK dibit is mapped so that I and shown in Table 38 For 16QAM every four bits a nibble forms a symbol byb b b The 16QAM nibble is mapped to L Q 1 and Q as shown in Table 38 Table 38 Bit Mapping Options 5 I 5 Bit To Symbol Mapping Register 2D Register 2C bits b b b bits 6 4 3 2 XX IX Bit Mapping Mod Mode QPSK 1 NA xo 0 QPSK NA NA 0 160 16QAM L 9 Q a 160 SENI
60. dsub CorrectEn DDC_DeltaTheta DeltaTheta_in 13 0 Factory Defined Value Factory Use Only Nyquist AlphaSel 1 0 UpdateEn WARNING SHOULD NOT BE PROGRAMMED BY THE USER User Manual Set the upper limit for the first frequency offset estimate Set the upper limit for the second frequency offset estimate Sets the gain of the AGC The effective gain is 1 229959 GainSel defaults to 2 and will normally range from 2 to 8 InvertOutputA is a checkbutton that inverts the polarity of the AGC s output bits default is off When InvertOutput is off then a low AGC output bit means that the current power estimate is greater than the corresponding Threshold InvertOutputB is a checkbutton that inverts the polarity of the AGC s output bits default is off When InvertOutput is off then a low AGC output bit means that the current power estimate is greater than the corresponding Threshold There two gain amplifiers ThresholdA sets the power threshold 0 to 2 8 1 of one amplifier For 256 OAM the value ranges from about 75 to 100 default is 96 depending on the desired A D clipping level There are two gain amplifiers ThresholdB sets the AGC s power threshold 0 to 248 1 of one amplifier For 256 OAM the value ranges from about 75 to 100 default is 96 depending on the desired A D clipping level Correct addsub should always be the opposite of Update addsub Update addsub controls which way the NCO rotates t
61. e TXBITCLK low period is the same except for 160AM when N is even in which case the low period is N 2 yielding the correct TXBITCLK period but not a perfect squarewave Table 53 Bit Clock Synchronization AC Characteristics Vpp 3 3 V 10 Vss 0 V Ta 40 to 85 Symbol Parameter Min Nom Max Units Conditions y Clock to TXBITCLK TXSYMPLS TXDATAENO 2 nsec TXACLK edge Clock Enable TXCLKEN to TXTCLK Setup 3 nsec User Manual 59 STEL 2176 Transmitter Description TRANSMIT INPUT DATA AND CLOCK TIMING SLAVE MODE NOTE 1 NOTE 2 DON T CARE 14 55 4 tuo gt MASTER MODE NOTE 1 TXAUXCLK TXTCLK DON T CARE TXBITCLK NOTE 3 tsu lup Note 1 Mode is determined by setting of BIT 7 in Block 2 Register 2 Bit 7 high is slave mode Bit 7 low is master mode Note 2 In slave mode even though TXBITCLK is shown as Don t Care it should be noted that internally the STEL 2176 will relatch the data on the next falling edge of TXBITCLK Thus avoid changing the control signal inputs PXDATAENI TXDIFFEN TXRDSLEN TXSCRMEN at the falling edges of TXBITCLK Note3 In the STEL 2176 data is latched on the rising edge of the CLK that follows the falling edge of TXBITCLK Thus the data validity window is one CLK period delayed CLK not shown Table 54 Input Data and Clock AC Characteristics Vpp 3 3 V 10
62. e manual mode the decoder starts at any point in the puncturing sequence To skip to the next state write 1 to VitFeedBack bit 7 of Bank 0 Register Differential Decoder The two bit streams coming out of the Viterbi decoder are fed into the differential decoder The differential STEL 2176 decoder uses the following formula to produce its output Xk 6XLU 1 9 CV V 1 X4 VI 1 Zk Xk Y 4 Yk Yi 1 Buffer The trellis coded demodulator buffer converts groups of 5 symbols into a bitstream 28 bits for 64 QAM or 38 bits for 256 OAM following Annex B convention Frame Sync This block receives data from the buffer The frame sync looks for Annex B frame sync patterns which are different for 64 QAM and 256 QAM Also the separation distance between successive patterns is different 60 R S code words for 64 QAM and 88 R S code words for 256 QAM When the frame sync finds this pattern HIT Bank 1 Register 55 4 times the frame sync block declares acquisition and starts further processing of the data 18 User Manual The frame sync stays in the acquisition state until it misses this pattern MISS Bank 1 Register 56 times When in the acquisition state the frame sync patterns are deleted except the 4 bits identifying the interleaving parameters These can be used by the De Interleaver to automatically select the De Interleaving parameters The remaini
63. e of sub sampling technique works by intentionally undersampling the carrier frequency so that aliased signal appears at a lower frequency The sampling rate is still high enough to capture all of the modulation bandwidth without distortion In the case of a 44 MHz IF and a 25 MHz clock the resulting digital signal is centered at 6 MHz In the case of a 36 MHz IF and 29 MHz clock the resulting digital signal is centered at 7 MHz For more information on sub sampling techniques please see Stanford Telecom Application Note A 117 The digital samples from the ADC are downconverted to baseband I and Q signals in the Digital Down Converter DDC block Since the RF tuner sections of a cable modem may have large frequency errors an Automatic Frequency Control AFC block is used in the STEL 2176 for coarse tuning of the DDC This allows rapid acquisition of the input signal even with frequency errors of 200 kHz Fine tuning of the DDC is done using a carrier Phase Lock Loop PLL STEL 2176 An Automatic Gain Control AGC function provides two output signals to adjust the RF and IF analog gain stages of circuitry external to the STEL 2176 so that the ADC input is in the optimal range The two outputs can be programmed to create a sequential AGC system which maximizes RF gain for improved receiver noise figure The two AGC outputs and the external gain adjust blocks work together to maximize ADC performance but when large adjacent channe
64. edBack register to force the Frame Sync circuit to search for the start of the symbol group 21 STEL 2176 Receiver Description Bank 0 QAM Demodulator Registers Universal 5 0 has two sets of registers a Read Write set which Registers Group 2 is used for control purposes and a Read only set for monitoring purposes The sub groups are The QAM Demodulator Registers Universal Registers are divided into 6 sub groups of registers Each sub Sub Group Name Read Write Read only Register Addresses Register Addresses Control address range 00 to OE 40 to 45 DDC Nyquist AGC and AFC address range to 1B 46 to 52 H H H H H o aen Eee Bank 0 Group 2 Sub Group Control Address Range Registers Table 8 Group 2 Sub Group A Read Write Registers Address 7 6 5 1 3 esetFnable ctEn nSel Factory Defined Value 64 Factory Defined Value 40 16 QAM 53 64 QAM 874 256 QAM Factory Defined Value 334 16 QAM 374 64 QAM 544 256 QAM Factory Defined Value 5F 16 OAM 76 64 QAM A4 256 QAM Table 9 Sub Group Read Only Registers 7 6 I 2 LI Acguisitionbock I m 404 Aly 42 43 44 45 STEL 2176 22 User Manual Receiver Description Bank 0 Group 2 Sub Group Re
65. er Block i e the Scrambler Reed Solomon Encoder and two Multiplexers shown in Figure 25 Symbol Mapper Block i e the Bit Mapper Differential Encoder and Symbol Mapper are shown in Figure 28 two channels one for I and one for Q a Combiner and a 10 bit DAC Each channel consists of a Nyquist Filter Interpolation Filter and Modulator The Control Unit is comprised of a Bus Interface Unit BIU Clock Generator and NCO Table 32 summarizes the main features of the circuits described by the remaining paragraphs of this section DATA PATH DESCRIPTION Bit SYNC Block The Bit Sync Block has two functions latching input data and synchronizing the STEL 2176 TXBITCLK and symbol counters to the user data GTEI 2176 Transmitter Description Table 32 Transmit Features 5 to 65 MHz maximum of approximately 40 of master clock From Master clock divided by 16 down to Master clock divided by 16384 in steps of 4 yielding a maximum symbol rate of 10 Msps with a 160 MHz clock Five selectable symbol to constellation mappings I and modulator signs Spectral Signs of I and plus the mapping to Sine and Cosine carriers is programmable Inversion Reed Solomon Encoder Selectable on off Two selectable generator polynomials Block length shortened any amount Error correction capability T 1 to 10 Scrambler Selectable on off Self synchronizing or frame synchronized sidestream Location before or after RS Encoder Prog
66. erating Temperature Ambient 43 3 10 5 0 10 3 3 10 lt 20 lt 37 5 lt 1 25 40 to 85 s volts volts volts volts mA mW Volts Volts Volts pF ohms ohms Volts C Note 3 If interface logic is to be driven by Vpp then connect the 5V pin to the V supply and set pin 32 to correct value Duty Cycle Derating is required from 70 to 85 C STEL 2176 User Manual Introduction Table 4 ADC Performance Specifications Sampling Frequency 50 Resolution 10 Input Differential Signal Range 0 75 0 75 Analog Input Bandwidth 60 Signal to Distortion Ratio 10 MHz 54 signal over 25 MHz BW Input Common Mode 1 4 1 5 1 6 Table 5 DC Characteristics 3 3 V 31096 Yi 0 V T 40 to 85 C Symbol Supply Current Quiescent Static no clock Supply Current Operational Vy Supply Current Operational 5 Supply Current Operational Clock High Level Input Voltage 5 CLK Logic 1 Clock Low Level Input Voltage CLK Logic 0 High Level Input Voltage Other inputs Logic 1 Low Level Input Voltage Other inputs Logic 0 High Level Input Current VIN 5 Low Level Input Current VIN Vss High Level Output Voltage Io 2 0 mA Low Level Output Voltage 3 2 0 mA Output Short Circuit Current VOUT VDD VDD max Input Capacitance All inputs Output Capacitance All outputs Output Full Scale DAC Current Single outp
67. f Bank 0 Register F7 and M is the value stored in RxFsynM bits 6 0 of Bank 0 Register The recommended values for DAVIC DVB and IEEE 802 14 are Oscillator Frequency 29 MHz M 2 and N 8 The recommended values for MCNS are Oscillator Frequency 25 MHz M 2 and N 8 OSCILLATOR RXOSCIN A ig 1 RXOSCOUT RKMULTEN RXBYPCLK RXBYPASSFSYN FREQUENCY MULTIPLIER RXMULTCLK To ADC MCLK PLL WCP 53852 c 12 7 97 Figure 4 Master Receive Clock Generator STEL 2176 12 User Manual QAM Demodulator Blocks The following diagram shows the major QAM circuit blocks OutB Timing 1 sample 50 Recovery Symbol Adaptive to FEC SRRC qualize Filter AFC 4 WCP 53702 10 28 97 Figure 5 Demodulator Blocks Digital Down Converter DDC The digital samples from the ADC mixed down to baseband I and Q signals in the Digital Down Converter DDC block The input analog signal is sub sampled at the rate set by the receive crystal oscillator or a clock applied directly to the RXOSCIN input The resultant sub sampled input signal s spectrum is aliased to a lower frequency In typical cases with a 44 MHz 3 MHz input and 25 MHz sample rate the digital signal appears to the input of the DDC asa 6 MHz 3 signal For a 36 MHz 4 MHz input and a 29 MHz sample rate the d
68. ferent carrier freguencies The carrier freguency that will drive the modulator is selected by the TXFCWSEL control pin input signals A high on the TXNCOLD input pin causes the registers selected by TXFCWSEL to drive the NCO at the frequency determined by the register value The NCO s frequency is programmable using the NCO field Block 2 Registers 08 00 The nine 8 bit registers at addresses 00y through 08y are used to store the three 24 bit frequency control words FCW A FCW B and FCW as shown in Table 48 The output carrier frequency of the NCO fcarr will be tuus fax CARR where fc is the frequency of the CLK input signal The FZSINB field bit 7 Block 2 Register controls the sine component output of the NCO This can be used in BPSK to rotate the constellation 45 degrees to axis modulation For normal operation it should be set to one Table 48 FCW Selection TXFCWSEL FCW Selected FCW Value Bits 0 FCW A Register 02 Bits 7 0 Register Oly Bits7 0 Register 00 Bits 7 0 FCWB Register 05y Bits7 0 Register 044 Bits7 0 Register 03 Bits 7 0 Register 08 Bits 7 0 Register 07 Bits 7 0 Register 06y Bits 7 0 TRANSMIT REGISTER DESCRIPTIONS Programming the 2176 Transmit and Receive Functions The STEL 2176 has a total of xxx registers and they are arranged as three banks of registers As indicated in Table 49 Bank 0 is sub divide
69. g Characteristics 3 3 10 Vss 0 V Ta 40 to 85 C Symbol Clock Frequency LC Clock Period Clock High Period Clock Low Period Clock Rising Time Clock Falling Time User Manual 57 STEL 2176 Transmitter Description TRANSMIT PULSE WIDTH ICEL TXCLKEN RSTL TXRSTB N TXNCOLD INLDH WCP 53811 12 5 97 Table 52 Pulse Width AC Characteristics 3 3 V 1046 Vss 0 V Ta 40 to 85 Symbol Clock Enable TXCLKEN Low 4 nsec Reset TXRSTB Low 5 nsec NCO Load TXNCOLD High 1 CLK cycles STEL 2176 58 User Manual Transmitter Description BIT CLOCK SYNCHRONIZATION neck TT LI II ET Le gt La CESU I C0 gt I 5O600000 tr 2 N 1 BPSK 1 5 See 1 N 411 160 See Note 2 2 2 160 2 WCP 53826 c 12 5 97 Note 1 TXBITCLK will be forced high on the second rising edge of CLK following the rising edge of TXTCLK Note 2 period of time that TXBITCLK is high is measured in cycles of CLK e g N 1 in QPSK N is a 12 bit binary number formed by taking bits 3 0 of Block 2 Register 39 as the MSB s and taking bits 7 0 of Block 2 Register 29 as the LSB s Th
70. gister Data Field Descriptions AcquireCnt AcquisitionFail AcquisitionLock Decimate_GainSel ErrPwr Factory Defined Value JitPwr Pwrlvl correctEn QAM Enable QAM SoftResetEnable State SymbolCnt 9 0 SymbolKCnt User Manual The value indicates the number of times the STEL 2176 has attempted to acquire the signal The value is set to 1 when an acquisition failure is declared due to excessive error power the STEL 2176 is also returned to the idle mode The value is set to 1 when acquisition lock is detected If GainSel is low the default the Nyquist filter output 10 bits plus 1 fractional bit is multiplied by a factor of 1 25 2 dB power if GainSel is high the scale factor is 1 5 43 5 dB power Provides an indication of the SNR The conversion between ErrPwr and the SNR can be determined from Table 10 intermediate values can be found by interpolation The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values must be written to the data field Enables the power level adjuster to correct for deviations in the signal power due to adjacent channel interference The value is set to 1 to enable soft reset of the QAM Table 10 SNR to ErrPwr Conversion ErrPwr 64 QAM 256 QAM 16 OAM 20 26 33 41 51 64 78 95 29 STEL 2176 _ p pH ERE pu ul
71. hereby selecting either the positive or negative passband sidelobe This allows spectrum inversion The hardware default value is 1 which selects the positive sidelobe spectrum inversion off CorrectEn should be set to 1 When set to 0 the DDC ignores the AFC s frequency correction DeltaTheta_in 13 0 sets the initial phase increment of the NCO thereby specifying the carrier frequency L DeltaTheta_in should be initialized depending on the carrier and the sampling frequencies DeltaTheta_in round f f 219 where f is the sample clock frequency Note that f will be 25 to 30 MHz and f will be 6 MHz or 7 MHz E g for f 6 and f 25 DeltaTheta in 6 25 2 3932 fc DeltaTheta_in 2 f The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values must be written to the data field This data field is used by the factory and its function is not related to the STEL 2176 receive and transmit characteristics Selects the excess BW of the Nyquist matched filter 00 gt 12 01 gt 15 10 gt 18 11 gt not valid Should be set to 1 When set to 0 the DDC s NCO is frozen This data field is used by the factory and the programmed value will affect the STEL 2176 receive and transmit characteristics The factory programmed value should not be changed by the user If inadvertently changed the receiver must be
72. igital signal appears to the input of the DDC as 7 MHz 4 MHz signal Other input frequencies and sample rates are also possible The digital signal is down converted to baseband I and Q by mixing with cos 27 and sin 27 fet where f is the center frequency of the digital signal The Digital Down Converter contains a numerically controlled oscillator NCO with cosine and sine outputs a pair of mixers and an image filter The frequency fe is a combination of a starting value that is set using DeltaTheta_in 13 0 bits 7 2 of Bank 0 Register 10 and Bank 0 Register and frequency error terms computed by the Automatic Frequency Control block The value for DeltaTheta_in 13 0 is given by DeltaTheta in 13 0 f ADC sample rate 214 For f 6 MHz and ADC sample rate 25 MHz DeltaTheta_in 13 0 OF5C For f 7 MHz and ADC sample rate 29 MHz DeltaTheta in 13 0 0F73 User Manual Receiver Description The complex NCO drives a pair of multipliers which serve as mixers The products of the ADC samples and the sine and cosine outputs of the NCO produce the desired baseband I and signals plus undesired higher frequency image terms These higher frequency terms are removed by an image filter Automatic Frequency control AFC The STEL 2176 can accommodate up to 200 kHz uncertainty in the carrier frequency The carrier frequency recovery is divided into two steps The first step is a coarse f
73. iming signals bit symbol and sampling rate signals The auxiliary clock TXACLK output is primarily for use in master mode where users may need a clock to run control circuits during the guard time between bursts when TXCLKEN is low and TXBITCLK has stopped The output clock rate is set by the frequency of the external master clock and the value of the Auxiliary Clock Rate Control field bits 3 0 of Block 2 Register The clock rate is set to TAS ZENEI If N is set to 1 or 0 the output will remain set high thereby disabling this function If the TXACLK signal is not required it is recommended that it be set in this mode to conserve power consumption The TXACLK output is a pulse that will be high for 2 cycles of CLK and low for N 1 CLK cycles Unlike other functions the TXACLK output is not affected by TXCLKEN The data path timing is based on the ratio of the master clock frequency to the symbol data rate The ratio must be a value of four times an integer number N 1 The value of N must be in the range of 3 to 4095 This value is represented by a 12 bit binary number that is programmed by LSB and MSB Sampling Rate Control fields Block 2 Register 29 LSB and bits 3 0 of Block 2 Register 39 MSB which sets the TXSYMPLS frequency based on the frequency of the external master clock to User Manual f Symbol Rate Rad The symbol pulse TXSYMP
74. ister data fields are used for factory test and must be set to specific values for normal operation These values are noted in Table 50 Master Transmit Clock Generator The STEL 2176 uses a master clock CLK to control the transmit timing functions CLK can be generated in either of three ways as shown in Figure 38 A transmit bypass clock can be applied to the TXBYPCLK input and selected to drive CLK An external clock can be applied to the TXOSCIN input or a crystal can be connected across the TXOSCIN and TXOSCOUT inputs The oscillator circuit outputs a 20 50 MHz signal to a frequency multiplier PLL which upconverts the signal to a 100 150 MHz clock When the bypass clock is not used the multiplexer is set to select the output of the frequency multiplier to drive the CLK signal The frequency multiplier output can also be routed to the TXPLLCLK output for test purposes 52 User Manual ENCLKOUT ILLATOR TXOSCIN 050906019 A 20 50 MHz L_ TXOSCOUT TXPLLEN TXBYPCLK TXBYPASSFSYN FREQUENCY MULTIPLIER Transmitter Description TXPLLCLK CLK 100 165 MHz WCP 53854 c 12 8 97 Figure 38 Master Clock Generation Clock Generator The timing of the STEL 2176 is controlled by the Clock Generator which uses an master clock CLK and programmable dividers to generate all of the internal and output clocks There are primarily two clock systems the auxiliary clock and the data path t
75. l Generally if an encoding function will be left either on or off continuously then software control is appropriate If the function must be turned on and off dynamically typically in order to send the preamble in the clear i e unencoded then external user input control is required If the Reed Solomon encoder will not be used at all then a separate Al STEL 2176 Transmitter Description bypass option can be activated to remove 8 bit delay register from the data path that is required if the possibility of turning on the encoder exists Each of the external user input control pins if enabled turns on the encoding function when high and bypasses the function when low The TXDATAENI input signal determines whether or not data will advance shift through the encoding blocks The presence of a high on the TXDATAENI input when the TXBITCLK output goes low allows the circuits to advance data through them The TXDATAENI signal is delayed internally to allow the rising edge of TXDATAENI to coincide with the first rising edge of TXTCLK TXSCRMEN 5 5 ENCODED DATA y 50 8 9 SERIAL DATA Es TXDATAEN 2 2 CHKSUM SIGNAL Reed Solomon i Encoder Figure 25 Encoder Functional Diagram TKRDSLEN WCP 53808 12 5 97 See Table 34 for a summary of register settings required to achieve the various data path possibilities
76. le I and Q for each symbol to the equalizer These samples are taken at the epoch of each symbol Adaptive Channel Equalizer The output of the Timing Recovery block is fed to the Adaptive Equalizer at a rate of one complex sample symbol The Adaptive Equalizer will 1 Compensate for channel distortion including a Multipath b AM hum hum d Phase noise 2 Fine tune to the carrier frequency and phase offset 3 Set the acquisition flag true after the equalizer successfully locks on to the signal 4 Write to ErrPwr Block 0 Register 44 the estimated output SNR STEL 2176 The adaptive equalizer control registers are Block 1 Registers 21 to 241 FEC Decoder Blocks The purpose of the FEC subsystem is to improve the bit error rate performance of the data link The arrangement of the FEC blocks in the receiver is in reverse order from the transmitter The STEL 2176 FEC subsystem can decode signals which are generated in conformance with either the ITU T J 83 Annex A or Annex B FEC standards There are two different though similar set of blocks used for ITU T J 83 Annex A Figure 6 and Annex B Figure 13 The STEL 2176 supports the MPEG 2 standard MPEG 2 uses 188 byte packets with a sync byte and three header bytes containing service identification scrambling and control information The 184 bytes of data follows the sync and header bytes Normally this header information flows through t
77. le over a wide range of data rates Numerically Controlled Oscillator NCO modulator provides fine frequency resolution Carrier frequencies programmable from 5 to 65 MHz Uses inexpensive crystal in 25 MHz range Operates in continuous and burst modes STEL 2176 Introduction Programmable control registers for maximum flexibility FIFO for optional removal of inter frame gaps Automatic frequency control 200 kHz Highly integrated receiver functions Up to 50 MHz IF input Uses inexpensive Crystal in the 25 MHz range Adaptive Channel Equalizer ACE to compensate for channel distortion Selectable Nyquist filter Fast acquisition Differential Encoder Programmable Scrambler and Programmable Reed Solomon FEC Encoder Programmable 64 tap FIR filter for signal shaping before modulation 10 bit DAC on chip Compatible with DAVIC IEEE 802 14 preliminary Intelsat IESS 308 MCNS Standards Supports low data rates for voice applications and high data rates for wideband applications User Manual INTRODUCTION The STEL 2176 is a complete subscriber side cable modem chip that integrates both receiver and transmitter functions It is offered in CMOS 35 micron geometry operating at 3 3 Volts with integrated DAC and ADC Its programmable register set offers a flexible solution to meet current and evolving standards RECEIVER OVERVIEW A 10 bit A D converts the analog input signal The analog input signal may be up to 50
78. lock Ie 51 38 Master Clock Generation _ 53 User Manual 111 5ICL 2176 TABLE 1 WN PPP 02 02 02 02 2 2 C0 F2 2 l2 F2 l2 F2 FPR PRP RP RR RB ONO ON amp gt C DT amp C STEL 2176 LIST OF TABLES PAGE STEL 2176 Pin Assignments 0 cccccccccscsnceceeeencessensaaeceseeeenenessaaeeseeeeesennnesaasesseeeens 3 Absolute Maximum 8 Recommended Operating Conditions 8 ADC Performance Specifications een eene 9 DC Characteristics MM 9 nte Resister Setoa Mr le fy 20 Only Registers davies duos 65 20 Group 2 Sub Group Read Write 22 Sub Group Read Only Registers 22 SNR Gonversion su od tee ted n E AES UE na ng anas 23 Group 2 Sub Group B Read Write 24 Group 2 Sub Group Read Only Registers e 24 Group 2 Sub Group Read Write 26 Group 2 Sub Group Read Only
79. ls are present the power of the desired signal may change A second digital AGC tracks and adjusts the level of the desired signal after the adjacent channel energy is removed by filtering Following the DDC a square root raised cosine Nyquist filter eliminates adjacent channel signals and performs matched filtering to eliminate intersymbol interference The filter excess bandwidth or alpha is programmable from 0 12 to 0 20 The Timing Recovery block finds the exact location in the center of each symbol using a special low jitter discriminator These values are fed to the Adaptive Channel Equalizer An Adaptive Channel Equalizer ACE compensates for any multipath distortion on the input signal introduced in the channel The equalizer uses one sample per symbol T spaced taps The output of the equalizer is baseband I and Q signals with carrier frequency and phase errors symbol timing errors gain errors and multipath effects removed The Demapper takes the baseband I and Q signals representing the QAM symbols and translates each symbol back into a series of binary values based on one of the selectable constellation maps Following the Demapper is the Forward Error Correction FEC system This programmable system supports both the ITU T J 83 Annex A see page 14 and Annex B see page 16 standards In general both FEC systems employ Reed Solomon Decoders Frame Sync circuits that determine the FEC code block boundaries and a
80. min 15 nsec H5 nsec pi a I lt gt 1 1 I 53888 12 6 97 Figure 23 STEL 2176 38 User Manual TRANSMITTER INTRODUCTION The STEL 2176 contains a highly integrated maximally flexible burst transmitter targeted to the cable modem market It receives serial data randomizes the data performs FEC and differential encoding maps the data to a constellation before modulation and outputs an analog RF signal The STEL 2176 is the latest in a series of modulator chips that comprise the STEL 1103 through STEL 1109 modulators Several key components e g a 64 bit FIR and a clock multiplier have been incorporated in the STEL 2176 and the enhancements have resulted in significant improvements to the chip s performance The STEL 2176 is capable of operating at data rates of up to 10 Mbps in BPSK mode 20 Mbps in QPSK mode and 40 Mbps in 16QAM mode It operates at clock frequencies of up to 165 MHz which allows its internal 10 bit Digital to Analog Converter DAC to generate RF carrier frequencies of 5 to 65 MHz The STEL 2176 also uses digital FIR filtering to optimally shape the spectrum of the modulating data prior to modulation This optimizes the spectrum of the modulated signal and minimizes the analog filtering required after the modulator The filters are designed to have a symmetrical mirror image polynomial transfer function thereby making the phase response
81. n of universal receive and transmit registers The registers are arranged as three banks of registers Bank 0 Bank 1 and Bank 2 The Bank 0 registers are divided into Group 1 and Group 2 registers The Bank 1 and 2 registers form separate groups Groups 3 and 4 respectively The Bank 0 and 1 registers Groups 1 2 and 3 are described by the following paragraphs The Bank 2 registers Group 4 are described in the Transmitter section see page 54 The Bank Group address shown below must be written to register location to access the respective 1 Universal Registers Group 1 bank of registers Register location can be accessed from each register bank group The registers can be accessed using the Microcontroller Interface s parallel or serial interface see page 11 REGISTER DESCRIPTIONS Bank O Universal Registers Group 1 The Universal Registers Bank 0 Group 1 consist of three sets of registers Read Write see Table 6 Read only and Write only see Table 7 The Read only register set Bank 0 Register F2 is for factory use only and not described by this User Manual Bank Group Address location 05 f 2 Demodulator Registers Universal Registers Group 2 1 Downstream Registers 4 Upstream or transmitter Registers Table 6 Read Write Register Set BypassMPE Gframe write only Te 5 3 1 0 N
82. ng data that is all bits between frame syncs are formed in 7 table bits symbols and passed to the de randomizer Derandomizer The Derandomizer uses a linear feedback shift register as shown below It works in GF 128 The delay elements are initialized at the beginning of each frame to 7Fy 7 and 7 Data In 7 7 Data 53707 10 29 97 Figure 17 Derandomizer De Interleaver This block is a convolutional De Interleaver as shown 1 2 3 4 2 II 1 y J HH A J LH 2 J Fls J L4 j J Input aT HHH gt VVC 53704 C 10 28 97 Figure 18 De Interleaver I and J Bank 1 Registers 47 and 484 programmable however in Level II the I and J values are determined by the 4 bit pattern of the frame sync User Manual Receiver Description A total memory of J _ 1 1 _ 1 2 is required The STEL 2176 has 8K internal memory Up to 64K memory can be added externally without any additional logic as shown Reed Solomon Decoder This function decodes Reed Solomon blocks Each code block is 128 7 bits symbols long and contains 122 7 bits symbols of data followed by 6 7 bits symbols of checksum The code blocks are assumed to be coded according to ITU T J 83 Annex B FEC 5 algorithm If the decoder fails to decode a code block the decoder sets the undecoda
83. nimum pipeline delay position This is achieved by setting bit 6 of Block 2 Register to zero Reed Solomon cannot be used in this mode If bit 6 is set high allowing Reed Solomon an additional pipeline delay of 8 bits is inserted into the data path This will shift both edges of DATAENO to the right by 8 cycles of TXTCLK 3 Ifthe preamble is not encoded the same as the user data the TXDIFFEN control can be toggled in mid transmission as shown Otherwise the TXDIFFEN control can be held high or low depending on encoding desired A First data bit transition on falling edge of TXTCLK first of 14 preamble symbols The data will be valid on the next rising edge of TXTCLK TXCLKEN rises on the same falling edge of TXTCLK that the data starts on TXCLKEN is allowed to rise any time earlier than shown TXDATAENI rises on the first rising edge of TXTCLK middle of the first preamble bit DATAENO rises on the falling edge of TXTCLK at the end of the second symbol TXDIFFEN rises on the rising edge of TXTCLK one symbol before the first user data symbol User data bits change on the falling edge of TXTCLK and must be valid during the next rising edge of TXTCLK NEBRIA Aa Q End of user data Note that the data is allowed to go away immediately after it is latched in by the rising of TXTCLK which occurs in the middle of the last user data bit H TXDIFFEN goes low on rising edge of TXTCLK last user data symbol
84. o fitness for a particu lar purpose merchantability or infringement of any patent copyright or other intellectual property right Intel products are not intended for use in medical life saving or life sus taining applications 350 E Plumeria Drive San Jose CA 95134 Customer Service Telephone 408 545 9700 Technical Support Telephone 408 545 9799 FAX 408 545 9888 Copyright O Intel Corporation December 15 1999 All rights reserved WCP 970317
85. o the Receiver frequency synthesizer Setting the value to 1 loads the value of TxFsynM into the Transmitter frequency synthesizer Setting the value to 1 loads the value of TxFsynN into the Transmitter frequency synthesizer Setting the value to 1 starts the QAM acquisition The programmed value determines the number of acquisition tries the QAM makes before it declares an acquisition failure The acquisition process will be restarted QAMEnable must be set to 1 to enable the QAM circuitry before programming QAM Start Used to select 16 64 or 256 OAM 00 t 16 QAM 01 t 64 QAM 10 t 256 QAM Setting the value to 1 resets the FIFO of the output clock in case of overflow Setting value to 1 bypasses the frequency synthesizer in the Master Receive Clock Generator Value controls the Receiver Frequency Synthesizer output Value controls the Receiver Frequency Synthesizer output Setting value to 1 bypasses the frequency synthesizer in the Master Transmit Clock Generator Value controls the Transmitter Frequency Synthesizer output Value controls the Transmitter Frequency Synthesizer output When use of Viterbi Decoder feedback is enabled setting the value to 1 forces the Frame Sync circuit to begin shifting by one symbol and testing for the start of the symbol group Once the search is externally initiated the value should be returned to Setting the value to 1 enables the use of Viterbi Decoder feedback for using the VitFe
86. o the receiver output but with ITU T J 83 Annex B there is an option of bypassing the MPEG 2 outer layer of processing Annex A FEC The ITU T 83 Annex A FEC subsystem consists of the following blocks 1 Q from Adaptive Equalizer Demappear pus De Interleaver Reed Solomon De Randomizer To Output Clock Decoder WCP 53703 c 10 28 97 Figure 6 ITU T J 83 Annex A FEC Subsystem Demapper This block maps the Adaptive Channel Equalizer I and Q outputs for each symbol into 4 6 or 8 bits for 16 64 or 256 OAM respectively The mapping tables are as follows 14 User Manual Receiver Description Q 000100 001100 011100 010100 110100 111100 101100 100100 e 000101 001101 011101 010101 110101 111101 101101 100101 6 000111 001111 1111 010111 110111 111111 101111 100111 0 0 000110 001110 011110 010110 110110 111110 101110 100110 000010 001010 011010 010010 110010 111010 101010 100010 000011 001011 011011 010011 110011 111011 101011 100011 oO 000001 001001 011001 010001 110001 111001 101001 100001 rotate 90 degrees e 000000 001000 011000 010000 110000 111000 101000 100000 10 rotate 180 degrees rotate 270 degrees 11 1 WCP 53713 10 29 97 1100 1110 0110 0100 1000 1001 1101 1100
87. of Syncs that must be detected before data is output MISS The number of misses before the Frame Sync state machine goes into idle SyncSymbol Used in Annex A only to input an arbitrary FRAME sync symbol normally 47 User Manual 33 STEL 2176 Receiver Description Bank 1 Group 3 Sub Group F OutputCIk Registers Table 29 Group 3 Sub Group F Read Write Registers Address 7 6 5 4 p 3 2 1 0o Nominal_value 7 0 67 Nominal Value 15 8 2 Nominal Value 19 16 Not Used ByPass LSB First Serial Mode Mode 0 Bank 1 Group 3 Sub Group F Register Data Field Descriptions ByPass Mode Setting to 0 enables output clock block to eliminate gaps between MPEG frames LSB First set Nominal Value 19 0 The 20 bit value is programmed according to the Annex and QAM type as shown below It controls how fast the output clock is operating by setting the ratio of the high speed clock to the output clock Annex A Annex B STEL Use Only 16 64 256 Scale Controls the amount of jitter in the output clock If Scale is set to low acquisition of the input data will be slower i e locking onto it will take longer but the clock will be smoother Serial Mode If Serial Mode is 1 the data is serial Bank 1 Group 3 Sub Group G Reed Solomon Decoder Registers Table 30 Group 3 Sub Group G Read Write Registers A
88. omon Encoder Parameters 4 1 bit field for selecting Primitive Polynomial 0 p x x X 2 1 L1 1 bits 3 0 4 bit field for setting Error Correction Capability Programmable over the range of 1 to 10 bits 7 0 8 bit field for setting User Data Packet Length K in bytes Programmable over the range of 1 to 255 2T Net length N K 2T LDLSBF Determines whether the first bit of the serial input is to be the MSB bit 4 0 or LSB bit 4 1 of the byte applied to the RS Encoder Code generator polynomial 1 is used when PP 1 G x TRLSBF 39 bit 5 Determines whether the MSB bit 5 0 or LSB bit 5 1 of the RS Encoder checksum byte is to be the first bit of the serial output data Notes GF 256 Code generator polynomial 2 is used when PP 0 G x D 028 1 0 STEL 2176 44 User Manual Symbol Block The Symbol Mapper Block Figure 28 maps the serial data bits output the Bit Encoder Block to symbols differentially encodes the symbols and in 16QAM maps the symbols to one of five constellations The Symbol Mapper Block functions are modulation dependent The modulation mode also defines the number of bits per symbol The Symbol Mapper Block outputs 2 bits for each symbol to each of the two Nyquist FIR Filters 1 o ENCODED ae pete ele DATA E CI1 01 Differential Enco
89. ot Used FECTestMode Bypass QAM VitFeedBackEn Factory Use Only Program to 0j Factory Defined Value 0 RxBypassFsyn TxBypassFsyn Factory Defined Value 2 RxFsynM RxFsynN TxFsynM TxFsynN Not Used Factory Use Only QAMAcquisitionMaxTries GAMEnable FEC Type Table 7 Write Only Registers Address 7 6 5 4 2 0 Factory Defined Value 0 VitFeedBack Factory Defined Value 0 LoadRxM LoadRxN LoadTxM LoadTxN QAM Start STEL 2176 20 User Manual Description Bank 0 Group 1 Register Data Field Descriptions BypassMPEGframe Factory Use Only FEC Type FECTestMode LoadRxM LoadRxN LoadTxM LoadTxN QAM Start QAMAcquisitionMaxTries QAMEnable Reset_OutputFIFO RxBypassFsyn RxFsynM RxFsynN TxBypassFsyn TxFsynM TxFsynN VitFeedBack VitFeedBackEn User Manual This data field is a write only register Setting it to 1 will bypass MPEG framing This data field is used by the factory and must be programmed to the value indicated above Used to select the type of FEC encoding 00 t Annex 01 t Annex B 10 t STel use only For test purposes the QAM can be bypassed by setting the value to 1 Data is then fed directly to the FEC Setting the value to 1 loads the value of RxFsynM into the Receiver frequency synthesizer Setting the value to 1 loads the value of RxFsynN int
90. ource s 5V output to pin 31 and its return to pin 32 and The polarity of OUTA and OUTB may be controlled with InvertOutputA bit 0 of Bank 0 Register 1211 and AGC InvertOutputB bit 1 of Bank 0 Register 12H For variable gain stages where a higher control voltage at the input to the filter produces higher gain set the AGC InvertOutput bit to 0 For variable gain stages 13 STEL 2176 Receiver Description where a higher control voltage at the input to the filter produces lower gain set the AGC_InvertOutput bit to 1 The two outputs can be programmed to create a sequential AGC system which maximizes RF gain for improved receiver noise figure This is accomplished by setting AGC_ThresholdA Bank 0 Register 144 and AGC ThresholdB Bank 0 Register 154 to slightly different values The threshold which is set to a lower value will cause its associated output to command increase gain first This output is typically connected to the RF variable gain stages so that the best receiver noise figure is achieved Timing Recovery and Nyquist Filter The sampled signal gt 4 times the symbol rate in I and format is fed to this block to Eliminate inter symbol interference ISI by filtering it with a square route raised cosine filter SRRC of a selectable excess bandwidth a for 12 lt lt 20 Recover the exact symbol rate within 100 ppm of the nominal value Resample and transmit one composite samp
91. put Clock ____ TPG 53300 c 7 28 97 Figure 20 STEL 2176 36 User Manual Receiver Description DOWNSTREAM OUTPUT TIMING PARALLEL DATA OUTPUT Case 1 Gaps between MPEG 2 Frames 1 88 Bytes and 204 Clocks I LI Frame Sync x Data 7 0 Cc Output Clock After 188 clocks bytes starting from the Frame The output clock will stay low till next Frame Sync TPG 53299 c 7 28 97 Figure 21 DOWNSTREAM OUTPUT TIMING SERIAL DATA OUTPUT Case 1 No Gaps between MPEG 2 Frames Frame Sync gt M58 LSB first X Output Clock e ra ES 8 n sec After 8 204 clocks 8 204 bITS starting from the Frame Sync The output clock will stay low till next Frame Sync TPG 53297 c 728 97 User Manual 37 STEL 2176 Receiver Description Figure 22 DE INTERLEAVER EXTERNAL SRAM TIMING Internal clock 5 SRAM ADDRESS E SRAMOEb _ 1 15 15 15 I lt Dad pad pp 1 SRAMWEb_ N mon E i 15 0 115 nsec
92. rammable generator polynomial Programmable length up to 2 1 Programmable initial seed Differential Encoder Selectable on off IXDIFREN DATA PATH TXTSDATA S I DACOUTP 10 Bit DACOUTN 9 9 Modulator i SQ 1 TXDATAENO TXRDSLEN LI 1 r TXCKSUM 8E A n OG GN VDDA I 2 4 522 Ooo Soo y VDD5 SAMPLS ud MB MASTER CLOCK CLK TXRSTB 1 1 TXBITCLK 1 LL TXSYMPLS I TXACLK 1 TXCLK TXNCOLD 1 TKFCWSEL Numerically Controlled DATA7 9 Oscillator ADDRs 1 I 858 Tuum DSB 1 Unit WRB I Group 2 erm Registers 1 1 WCP 53806 12 7 97 Figure 24 STEL 2176 Transmitter Block Diagram STEL 2176 40 User Manual Transmitter Description Table 33 Data Latching Options Latched By Register 2C Bit 7 Register 2D Bits 1 0 TXISDATA TXBITCLK pz LL 11 PN Code 10 3 TXBITCLK i 23 18 TXBITCLK Latching Input Data Latching of input data is accomplished in one of three modes e Externally supplied TXTSDATA is latched by the internal TXBITCLK Master mode Externally supplied TXTSDATA is latched by externally provided TXTCLK Slave mode
93. requency estimation during initial signal acquisition This estimation is performed by the AFC section The estimated carrier frequency offset is calculated by the AFC and fed to the DDC NCO AGC The AGC takes the output from the Image Filter in the DDC and estimates the power of the signal The AGC discriminator compares the estimate to one or two different thresholds that can be set via the registers values ThresholdA Bank 0 Register 144 and ThresholdB Bank 0 Register 154 Thresholds should be set to optimize ADC performance The range of the AGC s power thresholds is 0 to 128 25 For 256 QAM the value ranges from about 75 to 100 default is 96 depending on the desired A D clipping level The trade off for selecting the value weighs occasional ADC clipping with a large input versus loss of signal fidelity with a small input The power of the input signal depends upon adjacent channel interference AM hum burst noise etc The AGC generates two 1 bit outputs OUTA and OUTB that indicate whether that the input analog signal is too high or too low The OUTA and OUTB signals should be smoothed using low pass filters These filters can each be a series resistor of ___ ohms and a shunt capacitor of ___ _ F OUTA and OUTB can be set to have a logic high voltage of either 3 3V or 5V For 3 3V operation connect the power source s 3 3V output to pins 31 and 32 and its return to For 5V operation connect the power s
94. rs to be no gap For gap or no gap mode data may be parallel or serial The four modes are as follows NO GAP PARALLEL MODE Here Frame Sync indicates the first byte of an MPEG 2 frame and Output Clock is approximately 50 of the byte period There 188 bytes in a frame User Manual The value to be written to the OutputDataRate data field is dependent on the value of OutputDataRate 4 0 should be set to Not Valid Not Valid with one byte per symbol NO GAP SERIAL MODE This is similar to the above Here the frame length is 8X 188 bits and the Output Clock is for a bit period rather than a byte period GAPS PARALLEL MODE In this mode there are two differences The Output Clock is now approximately 8 nanoseconds The Output Clock goes for 188 bytes then the data and clock stop until Frame Sync is asserted again GAPS SERIAL MODE This mode is the same as above but here the bytes are serialized There are 8 X 188 clocks and 8 X 188 bits per Frame Sync STEL 2176 Description DOWNSTREAM OUTPUT TIMING SERIAL DATA OUTPUT Case 1 No Gaps between MPEG 2 Frames Frame Sync Data 7 0 KO gt Output Cock A N A 2 2 Period TPG 53298 c 7 28 97 Figure 19 DOWNSTREAM OUTPUT TIMING SERIAL OUTPUT Case 1 No Gaps between MPEG 2 Frames Frame Sync Data LSB first X X Out
95. scription Ground J SS 2 3 i 5 VSSA Ground Dedicated to receive clock multiplier Analog 10 11 12 13 14 15 16 17 3 STEL 2176 Introduction 22 JRVD a _ POWERS utl o 23 24 25 26 27 8 yss Ground 29 30 31 32 3 around ee internal connection leave open 5 239 vss Ground Control Status register parallel address bus Control Status register parallel address bus Control Status register parallel address bus Control Status register parallel address bus Control Status register parallel address bus Control Status register parallel address bus Control Status register parallel address bus Control Status register parallel address bus Serial parallel inter sel 00 parallel 01 SPI serial 5 VDD Power VX5 Gowd _L s VDD _ 3 Ss SS Enables output pins 11 amp 102 60 DATA Bi directional Control Status register parallel data in out Control Status register parallel data in out Control Status register parallel data in out Control Status register parallel data in out Control Status register parallel data in out 66 2 Bi directional Control Status register parallel data in out Control Status register parallel data in out 68 DATA O Bi directional Control Status register parallel data in out 0 Goud S O ypp
96. select lines INTSEL 1 0 11 STEL 2176 Receiver Description The parallel interface consists of an 8 bit address bus ADDR 7 0 an 8 bit bi directional data bus DATA 7 0 and the control signals chip select CS read write WRB and data strobe DSB The SPI interface consists of a serial input SI serial output SO and a serial clock SCK Master Receive Clock Generator The STEL 2176 uses a master clock MCLK to control the receive timing functions MCLK can be generated in either of three ways as shown in Figure 4 A receive bypass clock can be applied to the RXBYPCLK input and selected to drive CLK The RXMULTEN should be held high to select the RXBYPCLK input An external clock can be applied to the RXOSCIN input or a crystal can be connected across the RXOSCIN and RXOSCOUT inputs The oscillator circuit outputs a 20 50 MHz signal to a frequency multiplier PLL which upconverts the signal to a 100 150 MHz clock When the bypass clock is not used RXMULTEN is driven high to ENCLKOUT select the output of the frequency multiplier to drive the MCLK signal The frequency multiplier output frequency is controlled by the formula MCLK OscillatorOutput where Oscillator signal RXOSCIN and RXOSCOUT is four times the signal symbol rate value of M and N should be selected so MCLK is four times the value of the Oscillator signal e Nis the value stored in RxFsynN bits 6 0 o
97. ses 09 28 using two addresses for each 10 bit coefficient as shown in Table 50 The coefficients are stored as Two s Complement numbers in the range 512 to 511 200 to 1FF The filter is always constrained to have symmetrical coefficients resulting in a linear phase response This allows each coefficient to be stored once for two taps as shown in Table 44 Interpolating Filter The Interpolating Filter shown in Figure 37 is a configurable three stage interpolating filter The filter increases the STEL 2176 s sampling rate to permit the wide range of RF carrier frequencies possible by interpolating between the FIR filter steps at the master clock frequency This smoothes the digital representation of the signal which removes spurious signals from the spectrum STEL 2176 The interpolation filter contains accumulators As the interpolation ratio grows larger the number of accumulations per period of time increases If the interpolation ratio becomes too large the accumulator Table 44 FIR Filter Coefficient Storage MSB LSB Bits 9 8 Bits 7 0 Filter Taps Taps 16 and 47 Taps 17 and 46 Taps 18 and 45 Taps 19 and 44 Taps 30 and 33 Taps 31 and 32 Taps 0 and 63 Taps 1 and 62 Taps 13 and 50 Taps 14 and 49 Taps 15 and 48 Note For MSB storage only bits 1 0 are used Q4 U X 0 V C CLRFIR 2 BYPASS WCP 52992 c 4
98. strate the functional Must be relationships between the control inputs and signal Say outputs in various modes of burst operation Use the May 5 Change key at right to interpret the timing marks Only the first PANG an A diagram 15 complete and realistic burst The remaining diagrams are too short in duration to show TXDATAENO TXCLKEN going low from L to H Don t Care Permitted Does Not OUTPUTS Will be Steady Will be Changing from H to L Will be Changing from L to H Changing State Unknown Center Line is High Impedance Off State User Manual 65 VVC 53036 5 6 97 STEL 2176 Introduction SLAVE MODE QPSK BURST TIMING FULL BURST _ NAME mra TXTSDATA 4 a J gt TKDATAENI 1 TKDATAENOO D gt TXDIFFEN E gt H TKRDSLEN L M TXSCRMEN L gt N 4 Preamble lt user Data gt Guard Time TKsYMPLS I I I II I I II I I II I II II I I I I VVCL 53820 C 12 5 97 NOTES 1 All input signals shown derived from TXTCLK Each edge is delayed from a TXTCLK edge by typically 6 to 18 nsec DATAENO does not depend on TXTCLK but its edges are synchronized to TXTCLK TXTCLK itself can be turned off after TXDATAENI goes low 2 DATAENO shown at its mi
99. tSel W5 The setting specifies the step size of the FFE the nominal value is 2 ShiftSel W5 2 0 sets the step size when the PLL is acquiring UpdateEn Enables update of the feedforward equalizer FFE WIO 15 0 to WI11 15 0 Current in phase feedforward equalizer coefficients WQO0 15 0 to WO11 15 0 Current quadratic feedforward equalizer coefficients Bank 0 Group 2 Sub Group E FBE Address Range Registers Table 17 Group 2 Sub Group E Read Write Registers Ades gt 6 5 38 2 0 Factory Defined Value 74 Update_En Factory Defined Value ShiftSel_W_DD 1 0 m Factory Defined Value 7F Table 18 Group 2 Sub Group E Read Only Registers Address 7 6 5 3 2 a 98 WIO 7 0 Wins STEL 2176 28 User Manual 7a Receiver Description WOAI 11 4 WOBSI 11 4 Bank 0 Group 2 Sub Group E Register Data Field Descriptions Factory Defined Value The specified value must be written to the data field In a few cases several values are provided for selecting a specific mode and one of the specified values must be written to the data field ShiftSel_W_DD Sets the step size for the FBE when the system initially switches the equalizers to DD mode Update_En Enables update of the feedback equalizer FBE WIO0 11 0 to WI5 11 0 Current in phase feedback equalizer coefficients WQO0 11 0 to WO5 11 0 Current quadratic
100. trol Invert I Q Channel Output of Adder Block Register 2B Bits 1 0 Sum I cos ot sin ot 00 Sum I cos ot sin ot 01 Sum LI cos wt sin ot 10 Sum I cos ot sin wt 11 10 Bit DAC The 10 bit Digitatto Analog Converter DAC receives the modulated digital data and the Master clock The DAC samples the digital data at the rate of the Master CONTROL UNIT DESCRIPTION Bus Interface Unit The Bus Interface Unit BIU is part of the Microcontroller Interface see page 11 If contains the Block 2 Registers 90 programmable 8 bit registers The Reset TXRSTB input signal is the master reset for the STEL 2176 Asserting a low on TXRSTB will reset the contents of all Block 2 Registers to 00 as well as clearing the data path registers Asserting a high on TXRSTB enables normal operation After power is applied and prior to configuring the STEL 2176 a low should be asserted on TXRSTB Since TXRSTB is asynchronous the TXCLKEN input should be held low whenever TXRSTB is low The parallel address bus is used to select one of the 90 Block 2 Registers by placing its address on the ADDR bus lines The data bus DATA 9 is an 8 bit bi directional data bus for writing data into or reading data from the selected Block 2 Register The access operation is performed using the control signals DSB CS and WRB The Chip Select CS input signal is used to en
101. ust be written to the data field Factory Use Only This data field is used by the factory and its function is not related to the STEL 2176 receive and transmit characteristics FBE_ShiftSel_W_Lock 1 0 Sets the step size of the FBE when the system has locked steady state operation FFE_ShiftSel_W_DD 2 0 Sets the step size of the FFE when the system initially switches the equalizers to DD mode FFE ShiftSel W Lock 2 0 Sets the step size of the FFE when the system has locked steady state operation UpdateEn UpdateEn should be high if UpdateEn is low the PLL is disabled Bank 1 FEC Registers Group 3 group have a Read Write set of registers which are used for control purposes a Read only set which are used for monitoring purposes or a combination of both types of sub groups Addresses Register Added A e Demodulator Registers Universal Registers are divided into 7 sub groups of registers Each sub D MPEGFameSys Bank 1 Group 3 Sub Group A Viterbi and De Mapper Registers Table 21 Bad 3 gt Write a DVB amp IEEE Value 34 802 14 map STEL 2176 30 User Manual Description Bank 1 Group 3 Sub Group Register Data Field Descriptions DVB amp IEEE 802 14 map Set the value to 1 to select 256 QAM DVB amp IEEE 802 14 demapper 0 selects
102. ut DAC Compliance Voltage Based 50 ohms load Differential 2 resistance to ground DAC Output Resistance DAC Output Capacitance NOTES 1 Current source to ground output User Manual 9 STEL 2176 Receiver Description RECEIVER OVERVIEW The STEL 2176 is a complete subscriber side cable modem ASIC which integrates both the downstream receiver and upstream transmitter functions The receiver includes a high performance 10 bit Analog to Digital Converter ADC with a direct Intermediate Frequency IF interface The receiver also includes a QAM demodulator and both ITU T J 83 Annex A and Annex B Forward Error Correction FEC The upstream transmitter includes a BPSK QPSK 16QAM modulator with highly flexible FEC and scrambling and a 10 bit low spurious digital to analog converter DAC for direct synthesis of an upstream 5 to 65 MHz signal Both the receiver and transmitter are highly flexible and programmable the STEL 2176 Digital Mod Demod ASIC offers a solution to meet current and evolving standards The input to the STEL 2176 receiver is an analog IF signal of up to 50 MHz Typically the IF signal has 44 MHz center frequency with a 6 MHz bandwidth for NTSC based systems or a 36 MHz center frequency with an 8 MHz bandwidth for PAL based systems In typical applications the input signal is sampled by the ADC at approximately 25 MHz for the 44 MHz IF or at approximately 29 MHz for the 36 MHz IF This typ

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