COSI-NoC User Manual (Version 1.2)
Contents
1. a parameter that balances the importance of minimizing power vs mini mizing area if P is the power consumption and A the area occupied by the network the cost function used in this case is AP 1 A A where A is defined by the powervsarea attribute The cost function is not always defined in this way but depends on the optimization strategy chosen by th user All this parameters have defaults values and other parameters can be specified for a complete list of synthesis parameters see Section 2 5 The last part of the project definition is used to ask COSI NOC to generate some outputs for a complete list of output options see Section 2 6 13 lt xml version 1 0 gt lt Project name cmp2x2 1nput output results gt lt Constraints file constraints xml gt lt Library name Mylib file mylib xml gt lt Parameters switchingfactor 0 5 maxindegree 3 maxoutdegree 3 allowptp 0 powervsarea 1 gt lt Output gt lt Svg name cmp2x2 svg gt lt SystemC name cmp2x2 cpp mk cmp2x2 mk gt lt Report name cmp2x2 rep gt lt Dot name cmp2x2 dot gt lt Output gt lt Project gt We are asking COSI NOC to generate an SVG graphical representation of the network that is going to be saved as home myname project results cmp2x2 svg We are also asking to generate other outputs like a textual report home myname project results cmp2x2 rep and a SYSTEMC simulator2. home myname project results cmp2x2 cpp In order to run a synthesis you first need to make sure that the COSIROOT environment variable is set If it is not use the following command gt export COSIROOT current COSI NOC also you might want to add the directory where the COSI NOC executable is located to your PATH environment variable gt export PATH PATH current COSI NOC bin In order to run the synthesis use the following command home myname project gt CosiNoc x project xml 14 After the synthesis is completed the results can be found in the directory home myname project results To know how to use and interpret the re sults please refer to Section 3 With the project file that we have just set up the synthesis ends with the following message The problem is not feasible please increase the number of input ports of a destination Destination PO input bandwidth 5 6e 11 maximum input bandwidth 2 048e 11 Let s revisit the synthesis parameters that we specified Among these we didn t include two parameters that define the maximum outdegree of a source and the maximum indegree of a destination We only specified these values for the routers The default values for the source maximum output degree and for the destination maximum input degree is 1 Since our target clock frequency is 1 6GHz the capacity of a point to point connection is 1 6 Gflitps that for a flit with width equal to 128 corresponds to 204 8
3. tory of the SYSTEMC library This information is used by the SYSTEMC code generator of COSI NOC that writes also a Makefile to compile an executable simulation of the synthesized NoC The root and exec attributes of the PARQUET element define the installation directory of the PARQUET floor planner and the executable file to run re spectively When PARQUET is compiled as a set of dynamically linked library plus an executable file the directory defined by the root attribute is also used to set the LD_LIBRARY_PATH environment variable before runningPARQUET 1 3 Getting Started In this section we explain how to use COSI NOC to synthesize an NoC and analyze the synthesis result We use a very simple example of a 2 x 2 Chip Multi Processor CMP We start from the specification of the communication constraints of our chip as shown in Figure 1 1 all the necessary files for this example can be found in the directory COSIROOT tests cmp2x2placed We assume that all the cores are already placed on the chip so that even if you don t have PARQUET installed you can still follow this example Each core is 5x5 mm and needs to communicate with all the other cores with an aggregate bandwidth equal to 192 Gbps First decide the path of two directories the input directory that contains the specification of the communication constraints and the library of communication components and the output directory where the synthesis results will be saved For insta
4. c __ 100 0 gt ea s P3 P2 No objects selected Click Shift click or drag around objects to bes eet 68 3 Figure 1 2 Visualization of the NoC using INKSCAPE Dynamic power 0 42825 W Static power 0 02736 W Total power 0 45561 W Network dynamic power 5 09583 Network power 5 13107 Among the many file that you can in this directory you can visualize Svg file containing the graphical representation of the synthesized network using INKSCAPE Figure 1 2 shows the graphical representation of the synthesis result using INKSCAPE Each source to destination path is saved as a different layer in order to be able to visualize the choices taken by the algorithm Routers depicted as green rectangles and links depicted as black arrows are drawn to scale Notice that the representation of links is only logical in the sense that the real layout will route wires only along the x and y coordinates i e Manhattan routing The logical structure of the network is saved in cmp2x2 dot Figure 1 3 shows the graphical representation of the logical structure of the network using DOTTY Each core is represented simply by a square Routers are represented by records Each record represents one entry of the routing table The first row of the record corresponds to the source to destination flows that cross the router while the second row correspond to the next hop the packets should be forwarded to Finally it i
5. gt lt Constraint name POPi source P0 dest P1i bw 192000000000 T 10 gt lt Constraint name POP2 source P0 dest P2 bw 192000000000 T 10 gt lt Constraint name POP3 source P0 dest P3 bw 192000000000 T 10 gt lt Constraint name P1P2 source P1 dest P2 bw 192000000000 T 10 gt lt Constraint name P1P3 source P1 dest P3 bw 192000000000 T 10 gt lt Constraint name P1P0 source P1 dest PO bw 192000000000 T 10 gt lt Constraint name P2P3 source P2 dest P3 bw 192000000000 T 10 gt lt Constraint name P2P0 source P2 dest PO bw 192000000000 T 10 gt lt Constraint name P2P1i source P2 dest P1 bw 192000000000 T 10 gt lt Constraint name P3P0 source P3 dest PO bw 192000000000 T 10 gt lt Constraint name P3Pi source P3 dest P1 bw 192000000000 T 10 gt lt Constraint name P3P2 source P3 dest P2 bw 192000000000 T 10 gt lt Mutual exclusions to be added here gt lt Constraints gt Each constraint is identified by a name a source core a destination core a min imum bandwidth and a maximum latency requirements The last optional set of elements are mutual exclusions among constraints We know that each processor can only send packets to one other processor at the time This implies that for instance constraints POP1 and POP2 are mutually exclusive see Sec tion 2 3 for an explanati
6. aa Yaron ow Bee eb oe oe Se Se eee SS sua 2 The Input Format 2 1 Configuration of COSI NOC 224 4 xi Pe 1 6 3v 4 bt Sex x 2 2 Description of a COSI NOC Project 2 3 Specification of the Communication Constraints 2 4 Specification of the Library Components 2 5 Specification of the Synthesis Parameters 2 6 Specification of the Required Output 3 The Output Format ab SENSES VG O Ut DUG cana Ate ee a Be SG Seed su PE amp a2 Phe Doro pute amp 444 2 Bad KOA M2 22A4 22a oo he SYSTEM CGC OUlpur sa s Win Bee eM RS eee a ee Chapter 1 Introduction COSI NOC is an open source software for the automatic synthesis of networks on chip NoC COSI NOC is part of the Communication Synthesis Infrastruc ture COSI under development at the University of California at Berkeley The goal of the COSI project is to develop a formal framework and a methodology to address the problem of synthesizing embedded networks A Network on Chip NoC is an embedded network that provides the communication service to a heterogeneous or homogeneous Multi Processor System on Chip MPSoC The user of COSI NOC specifies the communication synthesis problem by providing a description of 1 the end to end communication requirements and 2 the performance cost trade off of routers and links An end to end communication requirement also called point to point com munication constraint
7. bw 192000000000 bw 192000000000 T 101 T 101 T 101 T 101 T 101 T 101 T 101 T 101 T 101 T 101 T 101 T 101 gt gt gt gt gt gt gt gt gt gt gt gt lt Exclusion set POP1 POP2 POP3 gt lt Exclusion set P1P2 P1P3 P1PO gt lt Exclusion set P2P3 P2PO P2P1 gt lt Exclusion set P3PO P3P1 P3P2 gt lt Constraints gt The library of communication components that include wires and routers are all defined in the library file The library file contains three kinds of in formation the parameters of the silicon technology the characterization of the copper wires and the characterization of the on chip routers as a function of the number of inputs and outputs lt xml version 1 0 gt lt Library name Mylib gt lt Technology fclk 1 6e9 vdd 1 2 wmin 200e 9 1off 0 15 isc 65e 6 r0 10 0e3 cp 2 5e 15 c0O 1 5e 15 nlayers 7 gt lt Wires and Routers to be added here gt lt Library gt Each library is identified by a unique name The first element that we have defined specifies many parameters of the silicon technology The details about these parameters can be found in Section 2 4 The parameters here refer to a 100 nm technology The other elements that can be added to the library specification are the wires and the routers For instance we add the characte
8. defines the minimum required bandwidth and the max imum allowed latency between a source IP core and a destination IP core The performance and cost of a point to point link are computed analytically The user can specify the parameters of the model that include the physical characteristics of the silicon technology For routers we use ORION to estimate the power consumption and the area occupation To synthesize an optimal network COSI NOC 1 2 uses an algorithm based on an iterative application of a modified version of Dijkstra shortest path al gorithm Alg00 The adoption of the simple shortest path algorithm has been advocated by many researchers in this field like in MMAT06 HGRO5 The main difference with other approaches is the definition of a graph from which the shortest path is drawn In particular such graph called the NoC platform captures the set of all possible NOC implementations that satisfy the design specification constraints COSI NOC takes into account the chip floor plan the limited area available for the communication infrastructure the maximum distance that wires can span on a chip the constraints on the input and output degree for routers and network interfaces the constraints imposed by the flow control algorithm like deadlock avoidance and the maximum throughput of wires and routers 1 1 Content of the COST NoC v1 2 Distribu tion This distribution of COSI NOC contains the following directory e bi
9. structure of a COSI NOC project lt TMP root tmp gt lt SYSTEMC root usr share systemc 2 1 vi gt lt PARQUET root home apinto Projects cosi tools PARQUET_050330 exec Parquet exe gt lt Configuration gt The TMP element is a temporary directory where COSI NOC saves all temporary files used to communicated with external tools ike PARQUET The SYSTEMC element defines the installation directory of SYSTEMC This element is used in the generation of the makefile to compile the SYSTEMC simulator that can be generated as one of the results of the NoC synthesis The PARQUET element defines the installation directory of the PARQUET floor planner and the name of the executable file to run A configuration file is already provided with the current distribution of COSI NoC The user needs only to change the pointers to the SYSTEMC and PARQUET distributions 2 2 Description of a COSI NOC Project A project is an xml description of a communication synthesis task We use the simple example shown in Figure 1 1 to explain all the different parts that compose the synthesis task specification This example represents a Chip Multi Processor CMP composed of four cores Each of them is a processor of specific area 25 mm in our example 19 Communication requirements among the processors are captured by a point to point graph Each arc corresponds to an end to end communication constraint that must be satisfied The constraint
10. COSI NoC User Manual Version 1 2 Alessandro Pinto University of California at Berkeley 545P Cory Hall Berkeley CA 94720 apInto eecs berkeley edu September 23 2007 Copyright c 2007 The Regents of the University of California All rights reserved Permission is hereby granted without written agreement and without license or royalty fees to use copy modify and distribute this software and its documentation for any purpose provided that the above copyright notice and the following two paragraphs appear in all copies of this software and that appropriate acknowledgments are made to the research of the COSI group IN NO EVENT SHALL THE UNIVERSITY OF CALIFORNIA BE LIABLE TO ANY PARTY FOR DIRECT INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION EVEN IF THE UNIVERSITY OF CALIFORNIA HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE THE UNIVERSITY OF CALIFORNIA SPECIFICALLY DISCLAIMS ANY WARRANTIES INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE THE SOFTWARE PROVIDED HEREUNDER IS ON AN AS IS BASIS AND THE UNIVERSITY OF CALIFORNIA HAS NO OBLIGATION TO PROVIDE MAINTENANCE SUPPORT UPDATES ENHANCEMENTS OR MODIFICATIONS Contents 1 Introduction 1 1 Content of the v1 2 Distribution KE Iocan s docx ae esi A ee ee a do th n l seer eee a ere alk L3 Getihe Started ic
11. Gbps This means that each link can only carry one constraint For a source one output connection only is sufficient because the constraints out of a source are mutually exclusive On the other hand each destination receives three non exclusive inputs that cannot share the same link thus requiring three distinct input ports In order to account for this modify the parameters as follows lt Parameters switchingfactor 0 5 maxindegree 3 maxoutdegree 3 destindegree 3 allowptp 0 powervsarea 1 gt and run the synthesis again The number of points considered during synthesis is about 1000 This synthesis takes about 100 second to complete on an Intel Core Due Q 2GHz Step into directory home myname project results File cmp2x2 rep contains a textual description of the synthesis result It contains many interesting properties of the network like the number average number of hops for all point to point connections the power consumption and the area occupation For instance the power report for this example looks as follows Power report Wires Dynamic power 4 66758 W Static power 0 00787755 W Total power 4 67546 W Routers 15 k cmp2x2 svg Inkscape File Edit View Layer Object Path Text Effects Whiteboard Help 3 ti HEH 9 BSH QQQ DHE Sk PTAS ESTE P3 P0 P2 P3 P2 P1 P2 P0 P1 P3 P1 P2 P1 P0 P0 P3 P0 P2 P0 P1 Allowed IP Cores e Opacity
12. ame P1P2 source Pi dest P2 bw 192000000000 T 10 gt lt Constraint name P1P3 source P1 dest P3 bw 192000000000 T 10 gt lt Constraint name P1iP0 source Pi dest PO bw 192000000000 T 10 gt lt Constraint name P2P3 source P2 dest P3 bw 192000000000 T 10 gt lt Constraint name P2PQ source P2 dest PO bw 192000000000 T 10 gt lt Constraint name P2P1 source P2 dest P1 bw 192000000000 T 10 gt lt Constraint name P3P0 source P3 dest PO bw 192000000000 T 10 gt lt Constraint name P3Pi source P3 dest P1 bw 192000000000 T 10 gt lt Constraint name P3P2 source P3 dest P2 bw 192000000000 T 10 gt lt Exclusion set POP1 POP2 POP3 gt lt Exclusion set P1P2 PIP3 PIPO gt lt Exclusion set P2P3 P2PO P2P1 gt lt Exclusion set P3PO P3P1 P3P2 gt lt Constraints gt Figure 2 4 XML description of the communication constraints 23 that are the coordinates of the bottom left and top right corner of the IP respectively If the value of this attribute is Area then the position of the IP core is not fixed and must be determined before synthesis using a floor planner we use PARQUET AM03 to floor plan a chip If this is the case an area attribute must be specified Positions must be expressed in wm and areas in pm Remark 2 3 1 Technical remark on the IP fixed placement When the type for an IP core is specif
13. ans on VLSI 11 6 1120 1135 December 2003 Graphu1z Graph Visualization Software http www graphviz org Andreas Hansson Kees Goossens and Andrei R amp 462 dulescu A unified approach to constrained mapping and routing on network on chip architectures In CODES ISSS 05 Proceedings of the 3rd IEEE ACM IFIP international conference on Hardware software codesign and system synthesis pages 75 80 2005 Inkscape http www inkscape org Man Lung Mui K Banerjee and A Mehrotra A global intercon nect optimization scheme for nanometer scale vlsi with implications for latency bandwidth and power dissipation EEE Transactions on Electron Devices 2004 S Murali P Meloni F Angiolini D Atienza 5 Carta L Benini G De Micheli and L Raffo Design of Application Specific Net works on Chips with Floorplan Information In International Con ference on Computer Aided Design ICCAD 2006 to appear Otter Tool for Topology Display http www caida org tools visualization otter Scalable Vector Graphics SVG http www w3 org Graphics SVG SYSTEMC oul Language Reference Manual http www systemc org web sitedocs Irm_2_1 html TinyXml http www grinninglizard com tinyxml 34 IWan02 H Wang Orion A power performance simulator for interconnec tion networks 2002 XML Extensible Markup Language XML http www w3 org XML 39
14. constraints xml and the description of the library components from home myname project mylib xml The constraint file contains the specification of all the cores and all the end to end communication requirements among the cores Create the file home myname project constraints xml and start with the following elements lt xml version 1 0 gt lt Constraints gt lt Core name PO type Placed xbl 0 ybl 0 xtr 5000 ytr 5000 gt lt Core name P1 type Placed xb1 5000 yb1l 0 xtr 10000 ytr 5000 gt lt Core name P2 type Placed xbl 0 ybl 5000 xtr 5000 ytr 10000 gt lt Core name P3 type Placed xb1 5000 yb1 5000 xtr 10000 ytr 10000 gt lt PtP constraints to be added here gt lt Constraints gt We have just defined the IP cores Each core has a name and a type In this case all the cores are already placed on the chip and they are characterized by the bottom left and top right corner coordinates in um units Communication constraints are included as follows lt xml version 1 0 gt lt Constraints gt lt Core name PO type Placed xbl II O II ybl II O II xtr 5000 ytr 5000 gt lt Core name P1 type Placed xbl 5000 ybl 0 xtr 10000 ytr 5000 gt lt Core name P2 type Placed xbl 0 ybl 5000 xtr 5000 ytr 10000 gt lt Core name P3 type Placed xbl 5000 ybl 5000 xtr 10000 ytr 10000
15. d libcosi a that contains the objects files of COSI NoC and libtinyxml a that contains the objects files of the XML parser that we use TinyXML tin One executable is generated current COSI NoC bin CosiNoc x that is the main executable file This release contains already a compiled version of PARQUET AMO3I We are not allowed to distribute the source code This executable has been compiled under Fedora 6 with g 4 1 1 If you want to run COSI NOC ona different platform you can obtain the source code of PARQUET from http vlsicad eecs umich edu BK parquet Remark 1 2 1 On floor planning If the placement of each IP core is known the user can pass this information directly to COSI NOC Section 2 2 explains how to provide a placement of the IP cores as an additional input to the synthesis problem Section 2 3 explains how to include the placement information in the specification of the communication constraints In these two cases there is no need to floor plan the chip before synthesizing the NoC COSI NOC needs PARQUET only if the chip floor plan is not known or only partially known It is convenient to add the path where the COSI NOC executable is to your PATH environment variable If you use the bash shell run the following command to add the path export PATH PATH current COSI NoC bin Before running COSI NOC there is one more configuration step to com plete The file cosiconfig xm1 that is in current COSI NoC is a co
16. e Library and the Parameters These three elements are necessary for the synthesis the con straints define the problem in terms of the IP cores and the communication requirements among them the library defines the available on chip communica tion components and the rules to install and connect them the parameters fix some constants and options that are needed by the synthesis algorithm The output element is optional There are many possible outputs that a user can ask COSI NOC to generate Some of them are graphical or logical representation of the NOC and can be effectively used to have an idea of the NOC complexity and of the decisions that the algorithm has made The Sys TEMC Sys output is very useful to simulate the NOC under synthetic or real traffic conditions Notice that if no output option is specified then no output is generated by COSI NOC This chapter describes the COSI NOC input format more specifically how a project is specified how constraints are defined how the library is described and how the user specifies the output to be generated 2 1 Configuration of COST NoC The configuration file must be placed in the root directory of the distribution This file is written in XML format and must be called cosiconfig xml An example of the content of the configuration files is the following lt xml version 1 0 gt lt Configuration gt lt COSI version NOC 1 2 gt 18 Project Output Figure 2 1 Xml
17. e The specification of the desired outputs marked with the tag Output COSI NOC can generate many different outputs for analysis visualiza tion and simulation purposes refer to Section 3 2 3 Specification of the Communication Constraints The specification of the communication synthesis problem comprises two parts the communication agents and their interaction In the case of NOC synthesis the communication agents are intellectual property IP cores on the chip Their physical sizes are treated as constraints to the communication synthesis engine In fact once the floor plan has been decided each IP core becomes a piece of logic on the chip that cannot be touched This means that additional circuitry for the communication infrastructure can only be installed in those parts of the chip that are not already occupied by any IP core End to end communication constraints are captured by a set of arcs Each arc connects a source IP core to a destination IP core In the specification file Currently this number is interpreted as the maximum number of hops For a different delay model e g a cycle accurate delay model of routers its meaning can change 20 lt xml version 1 0 gt lt Project name cmp2x2 1nput output results gt lt Constraints file constraints xml useplacement Soc_placed pl gt lt Library name 100nm4ch128 file library100nm xml gt lt Parameters sparearea 0 25 step 0 01
18. e name of the IP core and a unique integer identifier Figure 2 4 shows the XML description of the communication constraints for the 2 x 2 CMP The root element is marked with the tag Constraints It contains three type of elements Core Constraint and Exclusion A Core element specifies an IP core with the following attributes e name is a string that uniquely identifies the IP core e type refers to the type of the specification It can be Area or Placed If the value of this attribute is Placed then the core has a fixed position on the chip and a fixed horizontal and vertical dimension In this case four additional attributes must be specified xbl ybl xtr and ytr 22 lt xml version 1 0 gt lt Constraints gt h i a This test case contains four processors PO P1 P2 and P3 Fach processor is 25mm 2 Fach processor needs to communicate with all other processors at 192Gb s Constraints having the same source are mutually exclusive gt lt Core type Area area 25000000 name P0 gt lt Core type Area area 25000000 name P1 gt lt Core type Area area 25000000 name P2 gt lt Core type Area area 25000000 name P3 gt lt Constraint name POPi source PO0 dest P1 bw 192000000000 T 10 gt lt Constraint name POP2 source PO0 dest P2 bw 192000000000 T 10 gt lt Constraint name POP3 source PO dest P3 bw 192000000000 T 10 gt lt Constraint n
19. e only handle one type of link and one type of router The extension to many types does not change the approach that we follow for communication synthesis The same algorithms can be reused while the size of the design space exploration increases Remark 2 4 1 On the router s maximum bandwidth Figure 2 5 shows a library where the maximum bandwidth supported by a router is equal to the clock frequency Usually the number of clock cycles necessary to transfer a flit from the input queues to the output is N gt 1 In this case the effective maximum bandwidth of a router is less than the clock cycle In particular after the arbitration of the input queues has resulted in the input to output assignment each flit is transferred in N cycles therefore a packet is transferred at fek N flits per second 2 5 Specification of the Synthesis Parameters The algorithm that is used by COSI NOC to synthesis a network is very flexible and the result depends on the various parameters that must be set in the project file There are two sets of parameters that can be specified One set contributes to the definition of the set of admissible implementations and consists of additional resource constraints This set of parameters includes e sparearea default 0 25 defines the amount of area around the IP core that is considered available to install routers Given an IP core with area A a portion of area equal to sparearea A is evenly distributed arou
20. ea C AP 1 A A The weighting constant is specified by this attribute hopconstraints default 0 If the value of this switch is 1 the algorithm tries to meet the input delay constraints otherwise such constraints are disregarded areaconstraint default 0 If the value of this switch is 1 the synthesis algorithm tries to implement a network that occupies and area as close as possible to the value specified by the attribute area density default unspecified This parameter specifies the number of points per millimeter square to be considered as installation points for routers 2 6 Specification of the Required Output COSI NOC can generate a set of outputs to analyze the synthesis result The synthesis result is guaranteed to satisfy all communication constraints and to be long to the set of admissible implementations Yet if you are interested in check ing whether the implementation satisfies your expectations COSI NOC is able to generate a graphical representation of the implemented network in SvG for mat Svg a logical representation in DoT format Dot a SYSTEMC simu lation Sys an input file for the OTTER network visualization tool Ott and a textual report In order to request the generation of a specific output you can include an Output element in the XML project as follows lt Dutput gt lt 5vg name cmp2x2 svg gt lt SystemC name cmp2x2 cpp mk cmp2x2 mk gt lt Report name cm
21. es of a link The attributes that can be set are the type of the wire only copper is supported by now and all the important physical properties for that type In the case of copper wires the following data must be specified the metal layer the resistance per unit length r and the capacitance per unit length c e Routers that describes the energy dissipation and area of a router as a function of the number of inputs and number of outputs These two quan tities are given as two matrices where the value of the entry i j defines that quantity for a router with inputs and 7 outputs The two attributes maxin and maxout are bounds on the maximum number of inputs and outputs of the model The real bounds are set as attributes of the pa rameters of the project The attribute maxbw is the maximum bandwidth that a router can handle It represents the maximum throughput for each input output port Notice that this library is very different from the one used in the cmp2x2 example To avoid a router to get congested we limit the maximum bandwidth per input port to a flit rate that is much smaller than the clock frequency This is a more realistic case since a the imple mentation of a router with flit traversal latency of one clock cycle is stall hard 27 The same file can contain the specification of many libraries and each library can contain the specification of many types of wires and many types of routers In this first release though w
22. esis as in Figure 3 1 32 For each source and destination we introduce a network interface We con nect each source and destination core to its network interface and then we con nect the network interfaces to the rest of the network Point to point links from source to destinations become point to point links between network interfaces In this way each core has at most one input and one output port Notice that if the allowptp parameter is set to zero no point to point links are synthesized The SYSTEMC library that is provided in the distribution implements a wormhole switching technique and a weighted fair queuing technique COSI NOC generates the routing tables and the weights for each router The weight vector for a router R is a vector wr that has an element for each input queue The total bandwidth bwpr is distributed among the input queues such that bw bwr writ X weit The generation of a makefile requires the correct definitions of the SYSTEMC element in the COSI NOC configuration file and of the COSIROOT environment variable This variables are needed to point at the correct include and library directories In this distribution we target the Linux and Mac Os X platforms only 33 Bibliography AIg00 AM03 Dot HGRO5 Ink MBM04 MMAT06 Introduction to Algorithms MIT Press 2000 Saurabh N Adya and Igor L Markov Fixed outline floorplanning Enabling hierarchical design IEEE Tr
23. eviously derived using ORION Wan02 The energy consumption are expressed in Joule consid ering a switching factor equal to one The area is expressed in u Entry i 7 of these matrices characterize a router with 2 inputs and 7 outputs Remark 1 3 1 On network interfaces In this example we are assuming that network interfaces have the same cost of the routers We are aware of the fact that interfaces might have a different cost and we will add more accurate interface models in future releases Before running the synthesis we need to complete the project description by adding input parameters constraints and specifying the desired outputs 12 lt xml version 1 0 gt lt Project name cmp2x2 1nput output results gt lt Constraints file constraints xml gt lt Library name Mylib file mylib xml gt lt Parameters switchingfactor 0 5 maxindegree 3 maxoutdegree 3 allowptp 0 density 50 powervsarea 1 gt lt Other things to be added later gt lt Project gt The parameters that we have just added define the switching factor used to compute the power consumption the maximum input degree and output degree of each router a switch that does not allow point to point one hop connections between a source and a destination the density of points that are considered as potential installation points for routers expresses in number of points per mm7
24. flitwidth 128 switchingfactor 0 5 maxindegree 3 maxoutdegree 3 destindegree 3 sourceoutdegree 1 allowptp 1 allowtwohops 1 powervsarea 1 0 hopconstraints 0 areaconstraint 0 area 1 density 10 gt lt Dutput gt lt 5vg name cmp2x2 svg gt lt SystemC name cmp2x2 cpp mk cmp2x2 mk gt lt Report name cmp2x2 rep gt lt TabAppend name cmp txt gt lt Dot name cmp2x2 dot gt lt Otter name cmp2x2 odf gt lt Output gt lt Project gt Figure 2 2 Example of COSI NoCproject file 21 Figure 2 3 Bipartite graph representation of the communication constraints sources and destinations are denoted by string identifiers At the specification level each identifier denotes an IP core therefore it is possible to assign the same identifier to a source and a destination When the specification is parsed a bipartite graph is generated where sources and destinations are distinct Each node represents a directional interface input or output but not bidirectional Figure 2 3 shows the bipartite graph representation Each node is an interface sources are denoted by double circles of an IP core that can have multiple inputs or multiple outputs but neither bidirectional nor mixed type ports By setting the synthesis parameters properly the user can force the final imple mentation to have one port per core or many see Section 2 5 Each node in the bipartite graph has a name the sam
25. ied Placed the IP core is placed in a specific position on the chip and the vertical and horizontal dimensions are also fixed As every IP core in a specification is passed to the floor planner we need to make sure that a specific position gets assigned to the lower left corner of each placed IP and that the dimensions are also preserved The way in which we achieve this is to tell the floor planner that each placed IP is a hard rectilinear block defined by four vertices the four corners of the IP In order to place the IP in the desired position we insert a pad for each placed IP in such position and assign a very high weight to the net connecting the pad and the IP When the prefix of a core name is CosiComm the core is considered a spare block used only for the communication infrastructure During floor planning these cores are treated as any other core they can be placed or not In many practical cases the communication designer is assigned a fixed position for a few cores typically the off chip memory interface and the CPUs and a fixed position for a few areas that can be used for communication Our input format supports all such cases An end to end communication requirement is specified by a Constraint element which has the following attributes e name is a string identifier Each constraint should have a unique identifies that can be referenced later to define exclusion sets e source is the identifier of the IP core that is
26. n chip wires and routers are characterized in different ways For wires we use an analytical model MBM04 assuming that they will be opti mally buffered in the final implementation For routers we use ORION Wan02 to derive an estimation of the area and energy per flit of each router We run ORION for different configurations of a router in terms of number of inputs and outputs and we collect the results into a matrix We are interested in two met rics energy per flit and area The energy per flit is further decomposed into two components dynamic energy and static energy dissipation Figure 2 5 shows the typical description of a library of communication com ponents that consists of the following elements e Library that contains the library description The only attribute is the library name The same XML file may contain many library descriptions that are distinguished by unique names 25 lt xml version 1 0 gt lt Library name 100nm1ch128 gt lt Technology fclk 1 5e9 vdd 1 2 ioff 0 15 wmin 200e 9 isc 65e 6 rO 10 0e3 cp 2 5e 15 c0 1 5e 15 nlayers 7 gt lt Wire type copper layer 6 r 103 9e3 c 154 0e 12 pitch 460e 9 gt lt Router maxin 10 maxout 10 maxbw 300e6 energy 1 81013e 11 1 21089e 12 2 06545e 11 1 96132e 12 3 26714e 11 2 098e 12 4 70244e 11 3 27506e 12 area 168 25600 32768 51200 gt lt Library gt Figure 2 5 Exam
27. n contains the main executable called CosiNoc x e doc contains this document e systemc contains a library of SYSTEMC components to simulate a Network on Chip The components provided with this library are a model for sources and destinations a model for routers a model for point to point links implemented as bundle of wires a simulation monitor e techlib contains performance and cost parameters of the on chip com munication components at 100 70 and 50 nm e tests contains three examples cmp2x2placed used as a reference example in this manual an advanced set top box ADSTB and a tVOPD example 1 2 Installation The installation of COSI NOC is a straightforward process We denote the current directory where the COSI NOC tgz tar ball resides with current Expand the tar ball using the command current gt tar zxvf COSI NoC tgz Directory current now contains a new directory COSI NoC that contains the source code of the distribution Change directory to current COSI NoC Before compiling COSTI NoC you must define the environment variable COSIROOT to point to current COSI NoC If you are using the bash shell you can use the following command to set up the environment variable export COSIROOT current COSI NoC In order to compile the static libraries that are used by COSI NOC and the executable file CosiNoc x simply execute the following command current COSI NoC gt make Two libraries are generate
28. nce let these two directories be denoted by home myname project and home myname project results The project file that we show in a moment will be saved in home myname project this is also the directory structure used for all the tests accompanying this release Create a project file called project xml The content of a project file is divided in sections the definition of properties related to the project the definition of the constraints the definition of the synthesis parameters and the definition of the type of results that you need An XML project file starts as follows lt xml version 1 0 gt lt Project name cmp2x2 1nput output results gt lt Other things to be added later gt lt Project gt The Project element defines a project called cmp2x2 The input and output attributes define the directories where the input files and output files are saved respectively The communication constraints and the library of communication compo nents are going to be described in two separate files The name of such files are defined by two elements in the project file lt xml version 1 0 gt lt Project name cmp2x2 1nput output results gt lt Constraints file constraints xml gt lt Library name Mylib file mylib xml gt lt Other things to be added later gt lt Project gt COSI NOC parses the communication constraints from home myname project
29. nd the core and considered open space i e available to implement the com munication infrastructure additional area can be reserved by defining CosiComm IP core see Section 2 3 e step default 0 1 defines the minimum distance in terms of critical se quential length from the port of core and the closest interface router e flitwidth default 128 is the flit width This value directly impacts the capacity of each link as the clock frequency is fixed e switchingfactor default 0 5 is the percentage of bits that switch be tween two consecutive flits e maxindegree default 2 is the maximum input degree for routers e maxoutdegree default 2 is the maximum output degree for routers e sourceoutdegree default 1 is the maximum number of outputs of a source network interface 28 destindegree default 1 is the maximum number of inputs of a destina tion network interface allowptp default 0 is a switch to allow direct point to point connection between a source and a destination If this switch is equal to 1 then such connections are allowed if it is equal to 0 that point to point connections are not allowed allowtwohops default 0 is a switch to allow the connection between a source and a destination through a single interface If the value of this switch is 1 each source and destination par is separated by a minimum of three hops powervsarea default 0 5 The cost of a network is the convex sum of power and ar
30. ner Routers are represented by green squares and latches by orange squares The distinction between routers and latches is the following if for all inputs all and only the flows entering the router go to the same output then the router does not have to arbitrate among input queues or decide which output to send the input to In this case this piece of logic is reduced to be just a latch Note that it is not possible to get rid of the latch because it was introduced by the synthesizer in order to break the wire that is longer than the critical sequential length Each link is represented by an arrow Links are directional Sizes are actual physical sizes When the SvG file is generated the visible area is defined in wm and all dimensions are scaled appropriately in order to have a real idea of the area that is occupied by each block and the one taken by the wires SVG files can be opened with standard SvGenhanced browser or with tools like INKSCAPE Ink If INKSCAPE is adopted as a viewer then two extra features are gained The SvG file contains the definition of many layers One layer is dedicated to the IP cores and it is the only one that is visible The other layers l Figure 3 1 Transformation from the implementation graph to the Sys TEMCnetlist contain the source to destination paths There is one layer for each path and they can be visualized and superimposed using the layers menu of INKSCAPE Moreover the
31. nfiguration file that is read by COSI NOC every time at the beginning of its execution The configuration file has the following structure lt xml version 1 0 gt lt Configuration gt lt COSI version NOC 1 2 gt lt TMP root tmp gt lt SYSTEMC root usr share systemc 2 1 vi gt lt PARQUET root home apinto Projects cosi tools PARQUET_050330 exec Parquet gt lt Configuration gt The COSI element defines the version of COSI NOC that you are using and you should not change it unless you make modifications to the infrastructure and you want to distinguish you release from the original one The root attribute of the TMP element defines the directory that shall be used for temporary files Some independent modules of the COSI NOC soft ware release exchange information through temporary files For instance the communication constraints are parsed by the input module that writes the files needed by the PARQUET floor planner in the temporary directory The floor plan module runs PARQUET that writes the chip placement file in the tem porary directory The placement parser module reads the placement from the temporary directory and initializes a data structure with the position of each IP core Core PO Core P2 i B 192 Gbps T 10 Cycles 0 0 Figure 1 1 Example of a Chip Multi Processor CMP composed of four pro CeSSOrs The root attribute of the SYSTEMC element defines the installation direc
32. on of the meaning of mutual exclusions The complete set of constraints is defined by the following xml file lt xml version 1 0 gt lt Constraints gt lt Core name PO type Placed xbl O ybl O xtr 5000 ytr 5000 gt lt Core name P1 type Placed xb1 5000 ybl 0 xtr 10000 ytr 5000 gt lt Core name P2 type Placed xb1 0 yb1l 5000 xtr 5000 ytr 10000 gt lt Core name P3 type Placed xbl 5000 ybl 5000 xtr 10000 ytr 10000 gt lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint lt Constraint name POP1 source P0Q name POP2 source P0Q name POP3 source P0Q name P1P2 source P1i name P1P3 source P1i name P1P0 source P1i name P2P3 source P2 name P2P0 source P2 name P2P1 source P2 name P3P0 source P3 name P3P1 source P3 name P3P2 source P3 dest P1 dest P2 dest P3 dest P2 dest P3 dest POQ dest P3 dest POQ dest P1 dest PO dest P1 dest P2 10 bw 192000000000 bw 192000000000 bw 192000000000 bw 192000000000 bw 192000000000 bw 192000000000 bw 192000000000 bw 192000000000 bw 192000000000 bw 192000000000
33. p2x2 rep gt 29 lt TabAppend name cmp txt gt lt Dot name cmp2x2 dot gt lt Otter name cmp2x2 odf gt lt Output gt The Output element can contain one element for each required output The recognized elements are Svg to request the generation of an SvG file that depicts the network The only attributes that can be specified is the name of the Svc file The file name is relative to the outputdir parameter of the project see Section 2 2 Dot to request the generation of a DoT file that represents the logical structure of the network The only attribute that can be specified is the name of the DoT file The file name is relative to the outputdir parameter of the project see Section 2 2 Otter to request the generation of an OSDfile that can be read from the OTTER visualization tool The only attribute that can be specified is the name of the osd file The file name is relative to the outputdir parameter of the project see Section 2 2 SystemC to request the generation of a SYSTEMC netlist of the imple mented network Two parameters can be specified name is the netlist file name and mk is the name of the makefile to compile the SYSTEMC netlist and obtain an executable simulation The file name and the makefile are relative to the outputdir parameter of the project see Section 2 2 Make sure that the COSIROOT environment variable and the SYSTEMC element in the COSI NOC configuration file are correctl
34. ple of the xml description of the library of communication components for a 100nm technology and operating frequency equal to 1 5Ghz 26 e Technology that contains the value of all the parameters needed to char acterize the impact of the technology node on the performance and cost of the communication links In this release we only consider copper wires but the library con be easily extended to include other types of interconnect The attributes that must be specified are fclk that denotes the operating frequency We characterize the en ergy dissipation and we derive the power consumption depending on the switching factor see Section 2 5 and the actual bandwidth car ried by a point to point link The clock frequency is used to compute the leakage power that does not depend on the effective bandwidth carried by a link vdd that denotes the supply voltage ioff that denotes the transistor s off current wmin that denotes the width of the minimum sized inverter isc that denotes the transistor s short circuit current r0 that denotes the transistor s output resistance cp that denotes the transistor s output capacitance c0 that denotes the transistor s input capacitance nlayers that denotes the number of metal layers In this implemen tation of COSI NOC we assume that the network links are imple mented by global wires i e metal layer 6 e Wire that describe the properti
35. rendered image can be saved in any other format 3 2 The DoT Output The DoT language was originally developed at AT amp T Research Labs It allows to describe a graph in a textual format independently from the final visualization A set of rendering engine is available to read the graph description and automatically present a laid out graph to the user The DOT representation is very useful to understand the logical structure of the synthesis result Each IP core is represented by a rectangle with an associated name the name of the IP core Each router is a record The information stored in the record are the entries of the routing table The first column of the record is the name of the router By convention the name of a router is obtained by the prefix R followed by a unique integer identifier The following columns are the entry of the routing table Each entry has two rows The top row identifies a flow by its source and its destination The bottom row denotes the next router to which the current router sends packets belonging to that flow 3 3 The SYSTEMC Output COSI NOC can generate a SYSTEMC netlist of the implemented network In order to generate an executable simulation the netlist must be compiled to gether with the SYSTEMC library of components provided in the distribution For convenience a makefile that compiles the netlist can be also generated When we generate the netlist we transform the result of the synth
36. ribute set is a space separated list of constraint identifiers Remark 2 3 2 On exclusion sets One might think that exclusion sets are not needed since it should be always possible to transform the specification into another one with average or worst case end to end constraints It turns out that this is not always true Consider the 2 x 2 CMP design in Figure 1 1 One might be tempted to transform that design into another one where each constraint has a bandwidth requirement equal to 192 Gbps without specifying any mutual exclusion This is the case of worst case design If the clock frequency is 1 6 Ghz and the flit width is 128 the problem is unfeasible because both source and destination interfaces can only handle one constraints 1 6e9 x 128 192Gbps The other transformation is to assign a bandwidth requirement equal to 192 3 Gbps to each constraint This is the case of average design where the solution could have links with an assigned bandwidth that is a fraction of 192 Gbps leading to a under utilization of the network capacity 2 4 Specification of the Library Components The library of communication components is also described in an XML file A library file can contain more than one library each identified by a unique name For instance a library could contain the performance cost characteriza tion of on chip routers and links for the same technology but for different clock frequencies of different flit widths In COSI NOC o
37. rization of a global wire Metal 6 lt xml version 1 0 gt lt Library name Mylib gt lt Technology fclk 1 6e9 vdd 1 2 wmin 200e 9 ioff 0 15 isc 65e 6 r0 10 0e3 cp 2 5e 15 c0 1 5e 15 nlayers 7 gt lt Wire type copper layer 6 r 103 9e3 c 154 0e 12 pitch 460e 9 gt 11 lt Routers to be added here gt lt Library gt For each wire three attributes must be specified the resistance and capacitance per unit length and the wire pitch that is used to compute the area occupied by a point to point link The last component to characterize is the on chip router While the model that we use for wires is an analytical model routers are characterized by tables that give the energy per flit and area of a router depending on the number of input and output ports lt xml version 1 0 gt lt Library name Mylib gt lt Technology fclk 1 6e9 vdd 1 2 wmin 200e 9 1011 0 15 isc 65e 6 r0 10 0e3 cp 2 5e 15 c0 1 5e 15 nlayers 7 gt lt Wire type copper layer 6 r 103 9e3 c 154 0e 12 pitch 460e 9 gt lt Router maxin 3 maxout 3 maxbw 1 6e9 energy 1 8e 11 1 2e 12 2e 11 2e 12 2 3e 11 2 7e 12 3 3e 11 2e 12 4 Te 11 3 3e 12 5 2e 11 4 5e 12 4 Te 11 3e 12 6 4e 11 4 6e 12 8 7e 11 6 2e 12 area 7168 25600 34816 32768 51200 69632 49152 76800 104448 gt lt Library gt The values are approximations of the real numbers that we pr
38. s possible to generate an executable simulation of the NoC Enter the directory home myname project results and type make f cmp2x2 mk 16 m mm e j B Pa mo m o Cs P3 to PO Eri m a e to PO P2 to Pl P2 Nil z Figure 1 3 Visualization of the NoC using DOTTY an executable file called cmp2x2 x is generated Running the simulation will print out the simulation results at run time In particular the average band width and delay for each constraint is printed to screen The following snippet is the report relative to the destination core P4 Bandwidth report Average Average Average Delay report for Average Average Average for D4 bandwidth from source bandwidth from source bandwidth from source D4 latency from source 1 NO latency from source 2 latency from source 3 1 88975e 10 1 889366e 10 1 88923e 10 53227 0427 21759 The report shows the average bandwidth from each source and the average delay of packets from each source 17 Chapter 2 The Input Format COSI NOC takes as input an XML XML file called project A project contains the description of the communication synthesis problem i e the input that are necessary to the COSI NOC synthesis engine The structure of a COSI NoC XMLproject is shown in Figure 2 1 The root element is the Project that is made of up to four elements The elements that must be present are the Constraints th
39. s that we consider are bandwidth and latency For instance Figure 1 1 explicitly shows a communication constraint between P2 and P3 the required minimum bandwidth is 192 Gbps and the maximum delay is 10 t The project file for this example is the following The root element specified by the tag Project defines the project Its attributes are the project name the directory where all the input files are stored inputdir and the directory where all the output files should be saved outputdir The attribute inputdir is considered a prefix for all input files i e the file containing the constraints and the file containing the library descrip tion and outputdir is considered a prefix for all output files i e any output that the user asks COSI NOC to generate The Project element contains four elements e the specification of the point to point constrains marked with the tag Constraints This information is stored in a separate XMLfile The attribute of this elements is just a pointer to an external XMLfile that describes the communication constraints refer to Section 2 3 e The description of the library components marked with the tag Library This information is also stored into a separate XMLfile The attribute of this element is just a pointer to an external X MLfile that contains the description of the library elements refer to Section 2 4 e The set of synthesis parameters marked with the tag Parameters refer to Section 2 5
40. the source of this constraint e dest is the identifier of the IP core that is the destination of this constraint e bw is the bandwidth requirement in bps e Tis the latency requirement in number of hops recall that COSI NoCcurrently supports only synchronous implementations of NOCs where each router operates at the same clock frequency For each constraint both the source and the destination IP core identifiers must have been specified in the name attribute of some previously defined IP core Usually a source IP core communicates with many other sources To specify that some data must be broadcasted to several destinations it is equivalent to say that all the corresponding constraints are active at the same time If broadcast communication is not supported then the IP core can send data to one destination at the time In order to model this situation the user can define sets of constraints that are mutually exclusive using an Exclusion element 24 The semantics of exclusion sets is tightly related to the dynamic behav ior of the application Two constraints that are in an exclusion set are never active at the same time Since we don t explicitly capture the notion of time this statement simply means that when two paths that implement a pair of mutually exclusive constraints share the same resources only the one with tighter constraints determines the performance cost trade off of such resources An Exclusion element has one att
41. y specified Report to request a report of the synthesis result in textual format The only attribute that can be specified is the name of the text file The file name is relative to the outputdir parameter of the project see Sec tion 2 2 TabAppend to request COSI NOC to append the synthesis results as a single row in a tab separated file This feature is very useful when COSI NOC is used to synthesis many SoCs and the results must be then visu alized using Excel If an element is not specified the corresponding output is not generated by COSI NOoC Please refer to Chapter 3 for an explanation of how to use the generated output 30 Chapter 3 The Output Format This chapter describes the various outputs tha can be generated by COSI NoC and how these outputs can be used to analyze the network 3 1 The Svc Output The SvG output is the pictorial description of the on chip network An SvG file is an XML description that can be interpreted and rendered to create a picture The XML elements that we use are simple circles and rectangles Sources and destinations are represented by filled circles Sources are colored in red while destination are colored in black We assume that ports are located at the bottom left corner of each IP even if this information can be explicitly given to the floor planner and retrieved by parsing the floor planning result Note that the 0 0 corner of the SVG representation is the top left cor
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