DS92LV3241/DS92LV3242 Demonstration Kit User Manual
Contents
1. ERE 14 TRODUBLESHOO i aa COP Fo ea Qvi Pea EUR TREE E ER CU 16 APPENDIX tA tui uui 17 BOM CBILL OF WVIATERTIALS SERIALIZER La t ui 17 BONE BILL OE MATERIALS DESERIAEIZER 565 nane 18 SERIALIZER TX PCDBSCHEMATIC L 19 DESERIALIZER RX PCB SCHEMATIC 23 SERIADIZER UX PCB TAYOUDL ev CR VE ER URN Ue CER 27 SERIALIZER IX PCB STA CRU Pe u 30 DESERIAEIZER RX PCB LAYOULS 31 DESERIALIZER RX PCB STACKUP 34 National Semiconductor Corporation Date 9 28 2009 Page 2 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Introduction National Semiconductors SERDES evaluation kit contains one 1 DS92LV3241 Serializer Tx board 1 DS92LV3242 Deserializer Rx board and one 1 standard 2 meter CAT 6 style cable assembly Note The demo boaras are not in2. National Semiconductor MADE U S 48 33 a P1 BOTTOM SIDE OUT2 NC 25 R22 17 OUT3 NC IEE R236 4 188BBBBE 46 e R24 C7 m 00 O C10 62 52 C12 C13 C14 H S1 L 3 JP4 51 8 e ASSY DS92LV3241 TX DEMO REV e e rev MM o National Semiconductor Corporation Date 9 28 2009 Page 6 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Configuration Settings for the Serializer Board 51 Serializer Input Features Selection PWDNB PoWerDowN Bar Bowers Down BISTEN BIST ENable Latch input data on Rising or Falling edge of TCLK DB Q mode Default RES 0 REServed V SEL LVDS output 440 mVp p 850 mVp p SELect Default pat eH operation Default BIST mode enabled Rising Edge BIST mode disabled Default Falling Edge Default MUST be Not allowed tied low for normal operation Default JP2 Serializer Input Features Selection Reference Description Default External _ 1 8V input option For 1 8V input swing IOVDD is connected to VDDI VDDI must be applied on JP1 pin 1 1 8V EXT Pi to VDD J7 VDD 59 JP2 VDDIC VDDI t VDDIC VDDI National Semiconductor Corporation TPWDNB 1 8V EXT Pt
3. VDD JP2 VDDIC VDDI Date 9 28 2009 Page 7 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 JP4 VR1 Pre Emphasis Feature Selection floating Path to GND JP4 Pre Emphasis helps to Disabled Enabled increase the eye pattern no jumper With jumper opening in the LVDS Default streams by providing current HE boost Pre Emphasis adjustment Clockwise Counter via screw Clockwise JP1 MUST have a jumper to use VH1 potentiometer VR1 VR1 VR1 00 to 20 JP1 12 H84 increases decreases 712 maximum pre Rpre value Rpre value emphasis to which which 32 minimum pre decreases increases emphasis pre pre 1 2 x 40 emphasis emphasis RPRE minimum gt 12 maximum is based resistor value In this case 32KQ value is based on the 12 fixed resistor plus 20K maximum potentiometer value User can use hundreds of k Ohms to reduce the pre emphasis value Pre emphasis user note Pre emphasis must be adjusted correctly based on application frequency cable quality cable length and connector quality Maximum pre emphasis should only be used under worse case conditions for example at the upper frequency specification of the part and or low grade cables at maximum cable lengths Typically all that is needed is minimum pre emphasis Users should start with no pre emphasis first and gradually
4. DETAIL SCALE 11 MO X 032 SLOT FULL F 932 DRILL AT SLOT PER HZ FILE 1 5 5 000 7 7 5 0 000 10 100 CORP A6 R 2 008 TX BOARD 4 PL cs a u 5516206J150 551 REV EALL 4 000 4 11 0 400 National Semiconductor Corporation SEE DETAL _ sze ary ToL f 000 32 ves 003 x oom 33 ves 008 0035 ves 003 0 043 85 ves 005 Ptr pm pnm ppm lt wo 003 A ons 005 000 B one ves C ozs 2 ves 05 D 00x 3 ves too NOTES UNLESS OTHERWISE SPECIFIED PRIMARY COMPONENT SDE 15 SHOWN HOLES MARKED ARE TOOLING HOLES UNPLATED AMD SHALL BE ONCE DRILLED FABRICATE USING MASTER FILM 551620380 001 REV USE GERBER FILE BS75B04 PHO FOR BOARD ROUTE ACCEPTABLITY SHALL BE BASED 600 CLASS 7 MATERIAL MATERIAL 15 FR 320HR OR EQUIVALENT COLOR GREEN 0 050 005 INCH HOM THCKHESS COPPER CLADDING SHALL BE 1 07 PLATING ALL HOLES AHD CONDUCTIVE SURFACES SHALL BE PLATED WITH OF 001 INCH COPPER SURFACE PLATING BE ELECTROLESS HCKEL 000150 IMMERSION GOLD 000050 ENG FABRICATION TOLERANCES END PRODUCT CONDUCTOR WIDTHS LAND DIAHETERS SHALL VA
5. Revision 1 Part 0 1uF open0402 22uF 2 2uF O 1uF 22uF 0 01uF O 1uF 2 Pin Header open 2 Pin Header IDC2X33 Unshrouded IDC2X2 Unshrouded BANANA 2x4 pin Jumper OPEN CONN JACK PWR open 0603 green LED RJ 45 8pin 332 ohm open 10K 0 Ohm 0402 SW DIP 4 05921 3242 LM3940 SOT223 open PCB Footprint CAP HDC 0603 CAP HDC 0402 CAP N 3528 21 EIA CAP HDC 1206 CAP EIA B 3528 21 CAP HDC 0603 CAP HDC 0603 Header 2P Header 2P IDC 66 IDC 2x2 CON BANANA S IDC 2x4 3 terminal thru hole power jack 0603 Super Thin RJ 45 thru hole RES HDC 0805 RES HDC 0805 RES HDC 0402 DIP 8 64ld TQFP 50 223 Date 9 28 2009 Page 18 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Serializer Tx PCB Schematic B C D E LAYOUT NOTES 1 4 layer board 2 Use standard FR 370HR 3 5 impedance tolerance 4 Minimum 4 standoffs on each corner of board 0 156 X 4 1 Primary component side 1 oz Cu layer 1 2 Ground plane 1 oz Cu layer 2 42 0 mil Core Power plane 1 oz Cu 1 3 Prepreg Material Cara Mater 121 BH core Material 05921 3241 Tx Demo Board Board Stackup Size Document Number Re A 05921 V3241 Tx Demo Board ber 18 2009 National Semiconductor Corporation Date 9 28 2009 Page 19 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 VDDLOc VDDLOc S VDDL VDDL1c VDDL1c VDDSOc VDDSOc VDDS VDDS1c VDDS1c VDDPLLOc
6. 9 28 2009 Page 33 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Deserializer Rx PCB Stackup ASSEMBLY SIDE 1 SILKSCREEM ASSY SIDE 1 1 102 LAYER 1 SOLDERMASK ASSY SIDE z lt lt sur or PLATED To _ FULL uv DETAIL kl D32 DRILL SLOT CENTER i PRIMARY COMPONENT SIDE IS SHOWN 2 HOLES MARKED ARE TOOLING HOLES UNPLATED AND SHALL BE ONCE DRILLED 3 FABRICATE USING WASTER FILM 551500387 001 REV USE GERBER FILE B577B04 PHO FOR BOARD ROUTE 4 SHALL BE BASED GH IPC A 800 CLASS 2 5 MATERIAL MATERIAL 5 GOLA 15410 EQUIVALENT COLOR GREEN 0 080 005 NOM THICKHESS COPPER CLADDING SHALL BE 1 07 6 PLATING ALL HOLES AND COMDUCTIVE SURFACES SHALL BE PLATED WITH MIN OF 007 INCH COPPER SURFACE PLATING BE ELECTROLESS NICKEL 000150 IMMERSION GOLD 000030 7 FABRICATION TOLERANCES PRODUCT CONDUCTOR WIDTHS AND LAND DIAMETERS SHALL NOT VARY MORE THAN 002 INCH FROM THE 1 1 DIMENSIONS THE MASTER PATTERN THE CONDUCTIVE PATTERN SHALL BE POSITIONED SO THAT THE LOCATION OF ANY LAND SHALL BE WITHM 002 INCH DIAMETER TO THE TRUE POSITION OF THE HOLE IT CIRCUMSCREES THE MIMIMUM ANHULAR RING SHALL 002 INCH BOW TWIST SHALL EXCEED 87 INCH PER 8 SOLDERMASK BOTH SIDES PER IPC SW B40 A CLASS B COLOR
7. DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 ohm single ended impedance traces 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 LAYOUT NOTE 1 50 ohm single ended impedance requirement on these traces 2 Matched trace length on RxOUT0 31 RxCLKOUT 3 Mount 9 41 as close as physically possible to U1 National Semiconductor Corporation Date 9 28 2009 Page 25 of 34 CONN JACK open OUTPUT GND heatsink DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 VDD 1 VDDOR1 79 SY VDDOR1c 1 C70 22uF 01uFD 1uF Place near pin 9 of U1 VSS VDDLOc gt VDDLOc ow TuF near pin 61 of U1 ow per VDDPLL 9 fc C71 22uF 01uFD 1uF Place near pin 1 of U1 VDDPLL39 C66 22uF 01uF D 1uF Place near pin 64 of U1 VDDDc gt 9 C55 22uF 01uF D 1uF Place near pin 17 of U1 VDD 1 VDDAc 0 gt gt VDDAc C46 22uF 01uF D 1uF Place near pin 55 of U1 vss National Semiconductor Corporation VDDOR2 76 SY VDDOR2c 1 C45 22uF O1uF D 1uF Place near pin 26 of U1 vss VODLIC NY O1uF D 1uF yss prep VDD VDDPLL 6 22 VDDPLL2c 9 22uF 01uF D 1uF Place near pin 40 of vss U1 Date 9 28 2009 Pag
8. Except where mandated by government requirements testing of all parameters of each product is not necessarily performed assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using Tl components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of th
9. GREEM THERE SHALL BE NO SOLDERMASK ANY LAND 9 SILKSCREEM THE LEGEND ON BOTH SIDES USING NON CONDUCTIVE EPOXY INK COLOR WHITE THERE SHALL BE WO INK OM ANY LAND THE 005 TRACES LAYER 1 TO BE 50 SINGLE ENDED IMPEDANCE THE 0044 TRACES LAYER 1 TO BE 100 OHM DIFFERENTIAL IMPEDAMCE AND THE DIELECTRIC REFERENCED M BOARD STACK DETAL 5 SUGESTED HOWEVER TRACE WIDTHS AND OR DIELECTRIC THICKMESS MAY WICRO WODIFIED H ORDER TO FABRICATE BOARDS THE REQUIRED IMPEDANCE NOWIMALS TO A TOLERANCE OF 10 TL THE SHALL ROHS COMPLIANT National Semiconductor Corporation Date 9 28 2009 Page 34 of 34 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty
10. Manual Version 1 0 Deserializer Rx Board The RJ 45 connector P1 provides the interface connection for LVDS signals to the deserializer board The deserializer board is powered externally from the J6 VDD and J7 VSS connectors shown below For the deserializer to be operational the Power Down PWDNB and Receiver Enable REN switches on S1 must be set HIGH Rising or falling edge output clock is also selected by S1 R FB HIGH rising or LOW falling The 50 pin IDC Connector J1 provides access to the 32 LVCMOS data and clock outputs 4 Je J7 Note Vpp and Gnd MUST be J applied externally here 4 45V RXOUT Jl 3 si lt RO rry 17 lt gt lt gt lt gt 2 C C4 29 IN o e c27 B 2 J1 P1 E H C22 INS NC 24 5 cn C1 da d 4 20 c5 21 07 22 LVDS INPUTS 2 2 LVCMOS OUTPUTS LED 25 FUNCTION CONTROLS 26 POWER SUPPLY National Semiconductor 30 MADE IN U S COPYRIGHT 2009 R ASSYDS92LV3242 RX DEMO REV e National Semiconductor Corporation Date 9 28 2009 Page 10 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Configuration Settings for the Deserializer Board 51 Deserializer Input Features Selection ReS
11. National Semiconductor Corporation Date 9 28 2009 Page 21 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 VDD 5 VDDLOc gt gt VDDLOc VDD 5 VDDL gt gt VDDL1c 7 C38 19 18 C16 22uF 22uF O1uF D 1uF Place near pin 7 of U1 O1uF D 1uF Place near pin 42 of U1 vss vss VDDS0c VDD VDDS1c yppsic C35 622 15 22uF 22uF 01uF D 1uF Place near pin 18 of U1 O1uFD 1uF Place near pin 32 of U1 VSS VSS VDDPLL09 10 VDD VDDPLL19 vpppi 1e C34 4 25 C3 22uF 22uF O1uF D TuF Place near pin 56 of U1 O1uF D 1uF Place near 53 of U1 vss GND heatsink LM3940 SOT223 VDDAc gt gt VDDAC 26 22uF 01uF D 1uF Place near pin 26 of U1 1 8V option IOVDD gt gt VDDIc CS C8 JP1 22u 22u 0 1 01uF D 1uF Place near pin 49 of U1 VSS yss National Semiconductor Corporation Date 9 28 2009 Page 22 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Deserializer Rx Schematic LAYOUT NOTES 1 4 layer board 2 Use standard FR 406 or FR 370HR 3 5 impedance tolerance 4 Minimum 4 standoffs on each corner of board 0 156 X 4 Primary component side 1 oz Cu layer 1 1 2 Ground plane 1 oz Cu layer 2 39 0 mil Core Std FR 370HR Power plane 1 oz Cu layer 3 Secondary component side 1 oz 05921 3242 Rx Demo Board Board Stackup National
12. Semiconductor Corporation Size Document Number Re A 05921 3242 Rx Demo Board iday September 18 2009 Date 9 28 2009 Page 23 of 34 VDDOR1c VDDOR2c VDDOR1c VDDOR2c VDDLOc VDDLOc VDDL1 1 VDDL1c VDDPLL 1 VDDPLL1c VDDPLL2c VDDPLL2c VDDPLL3c VDDPLL3c VDDDc VDDDc VDDAc VDDAc gt VDD vss gt VSS LAYOUT NOTE Mount P2 on bottom Co 4 Cn C 74 Co DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 INO 1 2 01 RxINO INO 2 2 0 1 RxIND 1 3 2 RxIN1 IN1 4 2 0 1 1 IN2 zl 2 01 RxIN2 NC IN2 09 IN3 57 IN3 a LAYOUT NOTE 100 ohm differential impedance traces IN3 01 RxIN2 NC O 1uF RxIN3 NC 0 1 RxIN3 NC National Semiconductor Corporation LAYOUT NOTE 100 ohm differential impedance traces RxPWDNB 4 REN RxINO RxINO RxIN1 RxIN1 VDDAc VSS RxIN2 NC RxIN2 NC RxIN3 NC RxIN3 NC VDDLOc VSS VSS VDDPLL3c LAYOUT NOTE NO impedance requirements or matched trace LAYOUT NOTE Hide R51 on backside of board RSVD 50 ohm single ended impedance traces RxOUTO RxOUT1 RxOUT2 RxOUT3 RxOUT4 RxOUT4 RxOUT2 RxOUT3 F RxOUTS 50 oh single ended impedance traces RxOUT7 RxOUTS RxOUT10 RxOUT 11 RxOUTS RxOUT6 RxOUT7 RxOUTB RxOUTS RxOUT10 RxOUT11 RxOUT6 RxOUT11 Date 9 28 2009 Page 24 of 34
13. Source Host PC Graphics Board Video Processor Pixel Data DS92LV3241 Serializer LVCMOS 2 4 LVDS Pairs dee d LVDS L Figure 1 Typical SERDE Display LCD Monitor LCD TV Digital TV DE Pixel Data Display HSYNC VSYNC gt 059213242 Digital Deserializer LVCMOS The chipset supports up to 30 bit color depth TFT LCD Panels The picture below shows a typical test set up using a Graphics Controller and LCD Panel Digital RGB TTL from Graphic Contoller Transmitter Board Board e 9 H D 0 LVDS Interface reus Cable O Digital RGB TTL to Panel LIIS IIIS 1 lt lt lt lt lt Graphics Controller Video Processor Board Contents of Demo Kit LCD Panel Figure 2 Typical SERDES Setup of LCD Panel Application National Semiconductor Corporation Date 9 28 2009 Page 14 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1
14. VDDPLL1c ohm single ended impedance traces VDDPLLOc VDDPLL 1c VDDAc gt gt VDDAc moe 80 VSS U1 LAYOUT NOTE 100 ohm differential impedance LAYOUT NOTE 100 ohm differential impedance traces TxOUTO 0 1uF OUTOP TxOUTO 0 10 OUTON Wi VDDS1c TXOUT14 OUTIP VSS 55 SUT TxOUTO H VDDPLLic TxOUTO 55 TxOUT TxOUT1 D ik VSS 4 T OUT1 xOU l VDDAc VSS 5 VDDPLLOc VSS TxOUT2 NC TxIN16 DS92LV3241 LX LET TxOUT2 NC OUTS NC TxOUT3 NC XOUT3 NC TxOUT3 NC VSEL TxOUT1 1 0 1uF OUTiN TxOUT2 NC ev TxOUT2 NC 2 0 1uF OUT2N TxOUT3 NC O 1uF OUT3P 2 01 OUTSN TxIN14 Xx z 0 1 OUT2P impedance traces TxOUT3 NC VSEL PRE EMPH VDD VSS VDDSOc VSS LAYOUT NOTE 100 1 differentia impedance traces OUT1N OUT3N 7 C n Wh TxPWDNB BISTEN R FB LAYOUT NOTE MODE LAYOUT NOTE Mount P1 on bottom RSVD LAYOUT NOTE Place R45 amp R52 VSEL NO impedance on backside of requirements or board matched trace lengths RSVD2 required on these traces impedance traces LAYOUT NOTE 51 NO impedance uirements itle req SW DIP 6 matched trace 05921 V3241 Tx Demo Board 05921 V3241 Serializer Size Document Number DS92LV3241 Tx Demo Board lengths required on these traces Date 9 28 2009 Page 20 of 34 National Semicondu
15. apply pre emphasis until there is clock lock and no data errors The best way to monitor the pre emphasis effect is to hook up a differential probe across the AC coupling capacitors for the and inputs of the LVDS channels on the DS92LV3242 Rx demo board NOT across the AC coupling capacitors for the LVDS channels on the DS92LV3241 Tx demo board National Semiconductor Corporation Date 9 28 2009 Page 8 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Serializer LVCMOS and LVDS Pinout by IDC Connector The following two 2 tables illustrate how the serializer inputs are mapped to the IDC connector J1 the LVDS outputs on the RJ 45 connector 1 pinout Note Labels are also printed on the demo boards for both the LVCMOS input and LVDS outputs TTL INPUT J1 Pin No Symbol TxINO TXIN1 TxIN2 TXIN3 TXIN4 TXIN5 TXIN6 TxIN7 TxIN8 TxIN9 TXIN10 TXIN11 TxIN12 TxIN13 TxIN14 TxIN15 TxIN16 TxIN17 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN23 TxIN24 TXIN25 TXIN26 27 TXIN28 TXIN29 TXIN30 TXIN31 TxCLKIN VDS OUTPUT Symbol OUT O OUT O OUT 0 OUT 2 OUT 1 OUT 1 OUT 2 7 OUT 3 OUT 3 NES EN 2 __3 D ue d HE NE L 6 EC NE Odd Pins GND National Semiconductor Corporation Date 9 28 2009 Page 9 of 34 DS92LV3241 3242 Evaluation Kit Users
16. 0 The picture below shows a typical test set up using a generator and scope Transmitter Receiver Board Board 1906 9 DIGITAL 01101010 L Digital RGB wai LVDS Interface Digital Video Source he ad Cable L Contents of Demo Kit Logic Analyzer Oscilloscope Figure 3 Typical SERDES Test Setup for Evaluation National Semiconductor Corporation Date 9 28 2009 Page 15 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Troubleshooting If the demo boards are not performing properly use the following as a guide for quick solutions to potential problems Representative for assistance righ CHECKS If the problem persists please contact the local Sales Check that Power and Ground are connected to both Tx AND Rx boards 4 Check the supply voltage typical 3 3V and also cu
17. DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 National Semiconductor DS92LV3241 DS92LV3242 Demonstration Kit User Manual P N LV32EVKO1 Hev 1 0 National Semiconductor Corporation UU ate 9 28 2009 age 1 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Table of Contents TABLEORCONLIENTS 2 3 CONTENTS OF THE EVALUATION KIT 525 ou uve ve seu 4 HOW SET UP THE EVALUATION KIT 5 POWERCONNECTION 5255 D S u S de ce c saos 5 SERIALIZER TX BOARD DESCRIPTION 6 CONFIGURATION SETTINGS FOR THE SERIALIZER 02 000000000000 7 SERIALIZER LVCMOS AND LVDS PINOUT BY IDC CONNECTOR 9 i 10 CONFIGURATION SETTINGS FOR THE DESERIALIZER BOARD 11 DESERIALIZER LVDS AND LVCMOS PINOUT BY CONNECTOR 12 FLXPICAL APPLICATIONS c uynuy va rosa Oud even epu
18. PASTE LAYER 1 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 National Semiconductor Corporation Date 9 28 2009 Page 28 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 i T A x igh Ji vn B mr COPTRIGHT LE J 190 t National Semiconductor WADE IH U S 18 m wu sm i mie s 48 33 2 T OUT 2 in n QUT 1 1 E 17 n Bu 12 i 3 dances 35 OUTS WC 5 5 F 23 m li ES H tt T fae E E LQ tu ed cH 51 485 O 3 Tak 55 DS92LV3241 DEMO REV ssi 7 5 Une pm L SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 PRIMARY COMP SIDE SILKSCREEN LAYER 1 National Semiconductor Corporation _ Date 9 28 2009 Page 29 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Serializer Tx PCB Stackup St ASSY SOLDERMASK ASSY SIDE 1 060 006 c SLESCREEW 4557 SDE 2 SOLDERWASK ASSY SIDE 2 COMP SDE 102 LAYER PREPREG 004 THE GND 102 LAYER 2 CORE 042 THE PWR PLAME 1 OZ LAYER 3 PREPREG 204 THE SOLDER SIDE 1 02 LAYER 4 THRU HOLE SLOT 120 K JO SLOT y FULL z 120 X 082 SLOT FULL F T F
19. RY MORE 002 INCH FROM THE 11 DIHENSIOHS OF THE WASTER PATTERN THE CONDUCTIVE SHALL BE POSITIONED 52 THAT THE LOCATION OF AHY LAND SHALL BE WITHIN 002 INCH DI amp METER T THE TRUE POSITION OF THE HOLE IT CIRCUMSCRIBES THE MINIMUM AHNULAR SHALL BE 002 INCH BOW TWIST SHALL NOT EXCEED 07 INCH PER SOLDERNASK BOTH SIDES PER 5 840 CLASS COLOR GREEM THERE SHALL BE HO SOLDERMASK ON ANY LAND SLESCREEN THE LEGEND BOTH SIDES USING NOW CONDUCTIVE EPOXY COLGR WHTE THERE SHALL BE INK OM LAND THE 005 TRACES LAYER 1 BE 52 SINGLE ENDED INPEDANCE THE 0044 TRACES LAYER 1 TO 100 OHM DIFFERENTIAL IMPEDANCE AND THE DIELECTRIC REFERENCED BOARD STACK DETAIL IS SUGESTED HOWEVER TRACE WOTHS AND OR DELECTRIC THICKHESS BE MCRO HDDFIED ORDER TO FABRICATE BOARDS THE REQUIRED IMPEDANCE 5 A TOLERANCE OF 10 THE SHALL BE E U ROHS COMFLIAHT Date 9 28 2009 Page 30 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Deserializer Rx PCB Layout BEBE Jb 2 0 IN 1 IN2 NC IN3 NC b m MIR IFI 2 LOM Pi 25 26 27 National s seni Dp Semiconductor 50 M MADE IN U S RKULKDUI ASSY DS92LV3242 RX DEMO REV a O parus a TOP VIEW BOTTOMSIDE VIEW National Sem
20. S signal source such as a video generator word generator or pulse generator and oscilloscope The user needs to provide the proper LVCMOS clock and data inputs to the serializer and also provide a proper interface from the deserializer output to an LCD panel or test equipment serializer and deserializer boards can also be used to evaluate device parameters National Semiconductor Corporation Date 9 28 2009 Page 3 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Refer to the proper datasheet information on Chipsets Tx Rx provided on each board for more detailed information Contents of the Evaluation Kit 1 One serializer board with the DS92LV3241 2 One deserializer board with the DS92LV3242 3 One 2 meter standard CAT 6 cable assembly 4 Evaluation Kit Documentation this manual 5 05921 3241 3242 Datasheet National Semiconductor Corporation Date 9 28 2009 Page 4 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 How to set up the Evaluation Kit The PCB routing for the serializer input pins TxIN have been laid out to accept incoming LVCMOS signals from a 50 pin IDC connector The serial interface between the DS92LV3241 and the 059217 3242 uses a standard RJ 45 connector and CAT 5 6 cable assembly small CAT 6 cable provided The PCB routing for the Rx output pins RxOUT are accessed through a 50 pin IDC connector Please follow these steps to set up the evaluation kit for bench test
21. ctor Corporation DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 TxINO IxN2 10 10 12 12 TINS 14 14 TING 16 16 18 18 TINS 20 20 22 INTE E P j 24 24 DINTI T T 6 26 IINT2 Ll 28 ON 30 tht Ema L aaa T T seu 32 TXINIS j j j j j Ll j TXINIS j j i j j 1 1 P p C T j P SP T O j U UP F T 42 j j j j j J j 44 TXIN2T j j j j j j 46 TxXIN22 j j j Cn Cn cn cn Cn n UR CO Q CO CO Q N O n gt O Ch Q O 7 OQ CO O O h CO O n Q L1 LI j jJ j j j j jJ j j j 1 gg TXCLKIN j j j j j j j LAYOUT NOTE 1 50 ohm single ended impedance requirement on these traces 2 Matched trace length on TxIN0 31 3 Mount R1 R33 as close as physically possible to U1
22. e 26 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Serializer Tx PCB Layout 18V EXT JP1 COPYRIGHT C 2009 National Semiconductor MADE IN U S et 11111112222 OUT 0 0071 0 OUT2 NC IEE OUT3 NC m pp 228 I POP NEAS NEAS NES NES NEAS NEAS NES s N a gt cu ASSY DS92LV3241 TX DEMO REV PWB 551600390 001 REV A PWB DS92LV3241 TX DEMO REV 1 TOP VIEW BOTTOMSIDE VIEW National Semiconductor Corporation Date 9 28 2009 Page 27 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 oer E e PRIMARY COMPONENT SIDE LAYER 1 a eie i _ 11 117 ETT TTT A v38 100 0 1000188 BW le le SECONDARY COMP SIDE LAYER 4 GROUND PLANE 55 LAYER 2 E T 4002 00 ss et et an et LE 2 ss sss 211211 POWER PLANE VDD LAYER 3 T e tz KI e PRIMARY COMP SIDE SOLDER MASK LAYER 1 SECONDARY COMP SIDE SOLDER MASK LAYER 4 d n 7 L JL PRIMARY COMP SIDE SOLDER
23. erVeD MUST be Not allowed tied low for normal operation Default RES 0 RRFB REN RPWDNB C e 4 or Falling edge of Default RxCLKOUT PWDNB PoWerDowN Bar Power Down Normal Disabled Operational Default ENabled Default Output Monitor Pins for the Deserializer Board JP3 Output Lock Monitor Output L Output H _ Receiver PLL LOCK Status Unlocked PLL LOCKED LOCK Note LED1 will DO NOT PUT A SHORTING illuminate LEDI Misit hi JUMPER IN JP3 National Semiconductor Corporation Date 9 28 2009 Page 11 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Deserializer LVDS and LVCMOS Pinout by Connector The following two tables illustrate how the LVDS inputs are mapped to the RJ 45 connector J1 and the Rx outputs are mapped to the IDC connector J1 Note Labels are also printed on the demo boards for both the LVDS inputs and LVCMOS outputs LVCMOS OUTPUT J1 Pin No Symbol RxOUTO RxOUT1 RxOUT2 RxOUT3 RxOUT4 RxOUT5 RxOUT6 RxOUT7 RxOUT8 RxOUT9 RxOUT10 RxOUT11 RxOUT12 RxOUT13 RxOUT14 RxOUT15 RxOUT16 RxOUT17 RxOUT18 RxOUT19 RxOUT20 RxOUT21 RxOUT22 RxOUT23 RxOUT24 RxOUT25 RxOUT26 RxOUT27 RxOUT28 RxOUT29 RxOUT30 RxOUT31 RxCLKOUT LVDS INPUT Symbol P1 Pin No Symbol LING All Even P
24. hm open 0 Ohm 0402 10K SW 6 DS92LV3241 1 3940 50 223 open SVR20K National Semiconductor Corporation PCB Footprint CAP N 3528 21 EIA 1206 0603 CAP EIA B 3528 21 CAP HDC 0603 CAP HDC 0603 Header 2P Header 3P Header 2P IDC 66 IDC 2x2 IDC 2x4 CON BANANA S 3 terminal thru hole power jack RJ 45 thru hole RES HDC 0201 RES HDC 0805 RES HDC 0402 RES HDC 0805 RES HDC 0402 RES HDC 0805 DIP 12 64ld TQFP SOT223 eurface Mount 4mm Square Date 9 28 2009 Page 17 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 BOM Bill of Materials Deserializer PCB DS92LV3242 Rx Demo Board Board Stackup Revised Monday September 21 2009 DS92LV3242 Rx Demo Board Bill Of Materials Item O 10 11 12 13 14 15 16 17 18 19 20 21 22 23 September 21 2009 Qty Reference cO O N lt eek C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 C27 C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C54 C55 C66 C69 C70 C71 C48 C51 C53 C57 C59 C61 C62 C64 C67 C49 C50 C52 C56 C58 C60 C63 C65 C68 JP1 JP2 JP3 J1 J2 J3 J4 J5 6 7 8 19 LED1 P1 R2 R1 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 51 U1 U2 National Semiconductor Corporation
25. iconductor Corporation Date 9 28 2009 Page 31 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 ete LIII iiti e HE gt i e i 3 22 q TY le PRIMARY COMPONENT SIDE LAYER 1 GROUND PLANE VSS LAYER 2 POWER PLANE VDD LAYER 3 le elle m 0 0 iiit se E Tur eii on 2 x me LT e EN 19 le le le SECONDARY COMP SIDE LAYER 4 PRIMARY COMP SIDE SOLDER MASK LAYER 1 SECONDARY COMP SIDE SOLDER MASK LAYER 4 T n 4 L JL PRIMARY COMP SIDE SOLDER PASTE LAYER 1 SECONDARY COMP SIDE SOLDER PASTE LAYER 4 National Semiconductor Corporation Date 9 28 2009 Page 32 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 m m i 71 x at LI d E 2928555815 N TM u ih Hoe EE lt 4 4 T3 T 5 Ugmmm 5 sEsEESEEE i LOCK 3 H D comment 2009 FELLKGUT ASSY DS92LV3242 RX REV mm _ PRIMARY COMP SIDE SILKSCREEN LAYER 1 SILKSCREEN COMP SIDE SILKSCREEN LAYER 4 National Semiconductor Corporation Date
26. ing and performance measurements 1 A two 2 meter CAT 6 connector cable assembly has been included in the kit Connect one side of cable to the serializer board and the other side to the deserializer board This completes the LVDS interface connection 2 Jumpers and switches have been configured at the factory they should not require any changes for immediate operation of the chipset See text on Configuration Settings for more details From the transmitting test equipment connect a flat cable or fly wires not supplied to the Serializer board and connect another flat cable or fly wires not supplied from the Deserializer board to the receiving test equipment Caution The LVCMOS input levels should be within the specified range for optimal performance not to exceed the absolute maximum rating of 0 3V to Vpp 0 Note For 50 ohm signal sources add 50 ohm parallel termination resistors R1 R32 on the DS92LV3241 Serializer board and provide appropriate 3 LVCMOS input signal levels into TxIN 32 0 and TxCLKIN Note The Hx board may require the use of LVCMOS buffers to drive 50 ohm inputs found in some test equipment 3 Power for the Tx and Rx boards must be supplied externally through Power Jack Vpp Grounds for both boards are connected through Power Jack Vss see section below Power Connection The serializer and deserializer boards must be powered by supplying power externally through J7 Vpp and J8 Vss on the
27. ins GND LVCMOS OUTPUT Symbol 1 LOCK PLL 2 GND National Semiconductor Corporation Date 9 28 2009 Page 12 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Typical Connection and Test Equipment The following is a list of typical test equipment that may be used to generate signals for the TX inputs 1 Digital Video Source for generation of specific display timing such as Digital Video Processor or Graphics Controller with digital RGB LVCMOS output 2 Astro Systems VG 835 This video generator may be used for video signal sources for 6 bit Digital TTL RGB 3 Any other signal video generator that generates the correct input levels as specified in the datasheet 4 Logic Analyzer or Oscilloscope The following is a list of typically test equipment that may be used to monitor the output signals from the RX 1 LCD Display Panel which supports digital RGB LVCMOS inputs 2 National Semiconductor DS92LV3241 Serializer Tx 3 Optional Logic Analyzer or Oscilloscope 4 Any SCOPE with a bandwidth of at least 170 MHz for TTL and or 1 GHz for looking at the LVDS signals LVDS signals may be easily measured with high impedance low capacitance high bandwidth differential probes such as the TEK P6330 differential probes National Semiconductor Corporation Date 9 28 2009 Page 13 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Typical Applications Video
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30. rrent draw with both Tx and Rx boards The Serializer board should draw about 150 200 mA with clock and all data bits switching at 85 MHz in Quad Mode 12 The Deserializer board should draw about 240 265mA with clock and all data bits switching at 85 MHz in Quad Mode 8pF RxOUT loading 3 Verify input clock and input data signals meet requirements for Vi min Vi max Viumin tsrc turc also verify that data is strobed on the selected rising falling RFB pin edge of the clock 4 Check that the Jumpers and Switches are set correctly 5 Check that the cable is properly connected TROUBLESHOOTING CHART Problem There is only the output clock There is no output data No output data and clock Power ground input data and input clock are connected correctly but no outputs The devices are pulling more than 1A of current After powering up the demo boards the power supply reads less than when it is set to 3 3V National Semiconductor Corporation Solution Make sure the data is applied to the correct input pin Make sure data is valid at the input Make sure Power is on Input data and clock are active and connected correctly Make sure that the cable is secured to both demo boards Check the Power Down pins of both Serializer and Deserializer boards to make sure that the devices are enabled PWDB Vpp for operation Also check DEN on the Serializer board and REN on the De
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32. serializer Board and 46 VDD and J7 VSS on the deserializer board Note 4V is the absolute MAXIMUM voltage not operating voltage that should ever be applied to the serializer DS92LV3241 or deserializer DS92LV3242 VDD terminal Damage to the device s can result if the voltage maximum is exceeded National Semiconductor Corporation Date 9 28 2009 Page 5 of 34 DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Serializer Tx Board Description The 50 pin IDC connector J1 accepts 32 bits of LVCMOS RGB generic data TxINO TxIN32 along with the clock input TCLK The SERDES serializer board is powered externally from the J7 Vpp and J8 Vss connectors shown below For the serializer to be operational the Power Down PWDNB switch on S1 must be set HIGH The board is factory configured with series O 1uF capacitors on the LVDS outputs Rising or falling edge input clock is also selected on S1 TRFB HIGH rising or LOW falling JP2 is configured from the factory to be tied to Vpp 3 3V which sets the LVCMOS I O pins to operate at 3 3V logic levels The RJ 45 connector P1 on the bottom side of the board provides the interface connection to the LVDS signals to the deserializer board D LVDS OUTPUTS 4 J7 J8 2 LVCMOS INPUTS 3 FUNCTION CONTROLS 4 POWER SUPPLY Note VSS MUST be applied externally here lOVpp default setting IOV pp is connected to COPYRIGHT 2009
33. serializer board is set HIGH Check for shorts in the cables connecting the TX and RX boards Use a larger power supply that will provide enough current for the demo boards a 500mA minimum power supply is recommended Date 9 28 2009 Page 16 of 34 DS92LV3241 Tx Demo Board Bill Of Materials Item 10 11 12 13 14 15 16 17 18 19 20 21 22 24 25 26 27 Q DS92LV3241 3242 Evaluation Kit Users Manual Version 1 0 Appendix BOM Bill of Materials Serializer PCB DS92LV3241 Tx Demo Board Board Stackup Revised Monday September 21 2009 September 21 2009 Qty Reference CA C1 C5 C2 C3 C6 C7 C8 C9 C10 C11 012 C13 C14 15 16 17 026 31 34 35 038 C18 021 022 025 028 C29 C36 C37 C19 C20 023 024 C27 C30 C32 C33 JP1 JP4 JP2 JP3 JP5 J1 J2 J3 J4 J5 J6 J7 J8 J9 P1 R1 R2 R3 R4 R5 R6 R 7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R36 R35 R37 R38 R39 R40 R41 R42 R43 R44 R45 R52 R46 R47 R48 R49 R50 R51 51 U1 U2 Revision 1 Part 22uF 2 2uF 0 1uF 0 1uF 22uF 0 1uF 0 01uF 2 Pin Header 3 Pin Header 2 Pin Header open IDC2X33 Unshrouded IDC2X2 Unshrouded 2x4 pin Jumper OPEN BANANA CONN JACK PWR open RJ 45 8pin open 49 9o0hm open 49 9o0hm open 12 0K 0402 332 o
34. tended for EMI testing These demo boards were designed for easy accessibility to device pins with tap points for monitoring or applying signals and additional pads for termination The DS92LV3241 3242 chipset supports a variety of display and imaging applications Typical applications include navigation displays automated teller machines ATMs POS video cameras global positioning systems GPS portable equipment instruments factory automation printers etc The DS92LV3241 and DS92LV3242 can also be used as a 32 bit general purpose LVDS Serializer and Deserializer chipset designed to transmit data at clocks speeds ranging from 20 to 50 MHz in dual mode or 40MHz to 85 MHz in quad mode The DS92LV3241 serializer board accepts LVCMOS input signals at either 3 3V or 1 8V Note lOVpp must be set 3 3V for 3 3V input levels or 1 8V for 1 8V input levels The LVDS Serializer converts the LVCMOS parallel lines into either two 2 serialized L VDS data pairs with an embedded LVDS clock on each channel or four 4 serialized LVDS data pairs with an embedded LVDS clock on each channel The DS92LV3242 deserializer board accepts the LVDS serialized data streams with embedded clock on each LVDS stream and converts the data back into parallel LVCMOS signals and clock that NO reference clock is needed to prevent harmonic lock as with other devices currently on the market Suggested equipment to evaluate the chipset include an LVCMO
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