Corrections to Manual regarding the USB 2.0 Host/Function Module
Contents
1. RESM SOFR DVST CTRT BEMP NRDY BRDY vests vse vao 0 0 0 0 0 2 Value after reset 0 Note 1 The value is 0 after the MCU is reset and the value is 1 after a USB bus reset Note 2 The value is 1 when the USBO_VBUS pin is high and the value is 0 when the USBO_VBUS pin is low Note 3 The value is 000b after the MCU is reset and the value is 001b after a USB bus reset Page 668 of 1243 The note for bits CRCE and OVRN of the FRMNUM register in 25 2 18 is corrected as follows Before correction Note 1 Only 0 can be written After correction Note 1 When setting each status to 0 write 0 to the bit that is cleared and write 1 to the other bit Page 668 of 1243 The descriptions for the CRCE bit in 25 2 18 is corrected as follows Before correction 1 When the host controller function is selected On detecting a CRC error the USB generates the internal NRDY interrupt request After correction The USB generates an internal NRDY interrupt request when a CRC error is detected 2tENESAS Page 4 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 Page 675 of 1243 The note for bits SQSET and SQCLR of the DCPCTR register in 25 2 25 is corrected as follows Before correction Note 1 This bit is read as 0 Only 1 can be written After correction Note 1 This bit is read as 0 Page 675 of 1243 The following note for bits SUREQCLR and SUREQ of the DCPCTR register in 25 2 25 is2. Value after reset 0 Bit Name FIFO Port Bit Symbol b15tob0 Description This port is used for reading receive data from the FIFO buffer and R W writing transmit data to the FIFO buffer 2 When the MBW bit is 0 Address es CFIFO 000A 0014h DOFIFO 000A 0018h D1FIFO 000A 001Ch Value after reset Bit Name FIFO Port Bit Symbol b7 tob0 L 7 0 Description This port is used for reading receive data from the FIFO buffer and R W writing transmit data to the FIFO buffer FIFO Port Bits Accessing the FIFO port bits allows reading the received data from the FIFO buffer or writing the transmit data to the FIFO buffer Each FIFO port register can be accessed only while the FRDY bit in each FIFO port control register CFIFOCTR DOFIFOCTR or DIFIFOCTR is 1 The valid bits in a FIFO port register depend on the settings of the corresponding MBW bit of the FIFO port select register CFIFOSEL DOFIFOSEL or DIFIFOSEL When the MBW bit is 1 16 bit width the data arrangement may differ from the data arrangement on the RAM depending on the value of the MDE MDE 2 0 bits and the setting of the BIGEND bit CFIFOSEL BIGEND DOFIFOSEL BIGEND or DIFIFOSEL BIGEND Table 25 5 lists the endian operation in 16 bit access Note that if the total number of transmit data bytes is odd access the L 7 0 bits in bytes when writing the last data When the MBW bit is 0 8 bit width access the L 7 0 bits in bytes Table 25 5 Endian Op
3. carried out in the suspended state or while a USB bus reset is being received The USB supports the following functions based on the SOF packet reception These functions also operate normally with SOF recovery if the SOF packet was missing Updating of the frame number e SOFR interrupt timing e TIsochronous transfer interval count If an SOF packet is missing the FRMNUM FRNM 10 0 bits are not updated 2ENESAS Page 12 of 12
4. of the following errors occurs in the SET ADDRESS request a response from the software is necessary bmRequestType is not 00h Any transfer other than a control write transfer wIndex is not 00h Request error wLength is not 00h Any transfer other than a no data control transfer wValue is larger than 7Fh Request error The INTSTSO DVSQ 2 0 bits are 011b configured state Control transfer of a device state error For all requests other than the SET ADDRESS request a response is required from the corresponding software Page 727 of 1243 The descriptions for 1 Counter Initialization in 25 3 8 1 are corrected as follows Before correction 1 Counter Initialization The USB controller initializes the interval counter under the following conditions e Power on reset The ITV 2 0 bits are initialized Buffer memory initialization using the PIPEnCTR ACLRM bit The HT V 2 0 bits are not initialized but the count value is initialized Setting the PIPEnCTR ACLRM bit to 0 starts counting from the value set in the IITV bits After correction 1 Counter Initialization The interval counter is initialized when the MCU is reset or when the PIPEnCTR ACLRM bit is set to 1 The PIPEPERI IITV 2 0 bits are not initialized when the interval counter is initialized by using the ACLRM bit Page 730 of 1243 The descriptions for 1 Counter Initialization when Function Controller is Selected in 25 3 9 3 1 are corrected as follows Befor
5. single buffer mode i 4 USB bus OUT Token Packet Data Packet NAK Handshake Buffer status i I Ready for read access there is no space to receive data i I NRDY interrupt change in corresponding bit in PIPENRDY 2 H CRC bit etc A NRDY interrupt is generated 3 Example of data reception PING token reception single buffer mode I USB bus PING Packet NAK Handshake I Buffer status i Ready for read access there is no space to receive data I NRDY interrupt change in corresponding bit in PIPENRDY 2 A A NRDY interrupt is generated __ Packet transmitted by host device __ Packet transmitted by function device Note 1 The handshake is not used in isochronous transfers Note 2 The CRC and OVRN bits change only while the target pipe is set to isochronous transfers Figure 25 9 Timing of NRDY Interrupt Generation When Function Controller is Selected stENESAS Page 8 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 After correction 1 Example of data transmission single buffer mode i USB bus IN Token Packet NAK Handshake FIFO buffer status Ready for write access there is no data to be transmitted NRDY interrupt NRDYSTS PIPEnNRDY bit An NRDY interrupt occurs 2 Example of data reception OUT token reception single buffer mode I USB bus OUT Token Packet Data Packet NAK Handshake 1 FIFO buffer stat
6. Date 29 2014 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product MPU amp MCU Document TN RX A106A E Category No Corrections to Manual regarding the USB 2 0 Host Information Function Module USBc in the RX111 Group Category nA ea Nouneation Title Apolicable Reference RX111 Group User s Manual capa RX111 Group Document Hardware Rev 1 10 RO1UH0365EJ0110 This document describes corrections to section 25 USB 2 0 Host Function Module USBc in RX111 Group User s Manual Hardware Overall The following function name is corrected Before correction SOF interpolation function After correction SOF recovery function Page 642 of 1243 The following note for the DVSTCTRO WKUP bit in 25 2 3 is deleted Note 1 Only can be written 2013 Renesas Electronics Corporation All rights reserved ad ENESAS Page 1 of 12 RENESAS TECHNICAL UPDATE TN RX A10 A E Date Sep 29 2014 e Pages 645 646 of 1243 The descriptions for registers CFIFO DOFIFO DIFIFO in 25 2 4 are corrected as follows Before correction Address es CFIFO 000A 0014h DOFIFO 000A 0018h D1FIFO 000A 001Ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO FIFOPORT 15 0 Value after reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Symbol Bit Name Description R W b15tob0 FIFOPORT 15 0 FIFO Port The valid bits in a
7. FIFO port register depend on the settings of the R W corresponding MBW CFIFOSEL MBW DOFIFOSEL MBW and D1FIFOSEL MBW and BIGEND bits CFIFOSEL BIGEND DOFIFOSEL BIGEND and D1FIFOSEL BIGEND as shown in Table 25 5 and Table 25 6 FIFOPORT 15 0 Bits FIFO Port Accessing the FIFOPORT 15 0 bits allow reading the received data from the FIFO buffer or writing the transmit data to the FIFO buffer Each FIFO port register can be accessed only while the FRDY bit in each port control register CFIFOSEL DOFIFOSEL or DIFIFOSEL is 1 The valid bits in a FIFO port register depend on the settings of the corresponding MBW and BIGEND bits in a port select register CFIFOSEL DOFIFOSEL or DIFIFOSEL as shown in Table 25 5 and Table 25 6 Table 25 5 Endian Operation in 16 Bit Access CFIFOSEL BIGEND Bit DOFIFOSEL BIGEND Bit D1FIFOSEL BIGEND Bit Bits 15 to 8 Bits 7 to 0 0 N 1 data N 0 data 1 N 0 data N 1 data Table 25 6 Endian Operation in 8 Bit Access CFIFOSEL BIGEND Bit DOFIFOSEL BIGEND Bit D1FIFOSEL BIGEND Bit Bits 15 to 8 Bits 7 to 0 0 Access prohibited 1 N 0 data 1 Access prohibited 1 N 0 data Note 1 Reading from an access prohibited area is not allowed stENESAS Page 2 of 12 RENESAS TECHNICAL UPDATE TN RX A10 A E Date Sep 29 2014 After correction 1 When the MBW bit is 1 Address es CFIFO 000A 0014h DOFIFO 000A 0018h D1FIFO 000A 001Ch b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
8. cause 3 Example of packet transmission single buffer mode the transfer has ended ie USB bus Token Packet H Data Packet H ACK Handshake FIFO buffer status Ready for transmission Ready for write access BRDY interrupt BRDYSTS PIPEnBRDY bit A BRDY interrupt occurs because the FIFO buffer becomes ready for write access C Packet transmitted by host device C Packet transmitted by function device Note 1 The ACK handshake is not used in isochronous transfers Note 2 The FIFO buffer becomes ready for read access under the following condition When a packet is received while no data remains unread in the FIFO buffer on the CPU side Note 3 A transfer ends under either of the following conditions 1 When a short packet including a zero length packet is received 2 When the number of packets specified in the transaction counter are received Figure 25 8 Timing of BRDY Interrupt Generation stENESAS Page 7 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 Page 711 of 1243 Figure 25 9 is corrected as follows Before correction 1 Example of data transmission single buffer mode 4 USB bus IN Token Packet NAK Handshake l Ready for write access there is no data to be transmitted 1 NRDY interrupt H change in corresponding bit in PIPENRDY 7 A NRDY interrupt is generated Buffer status 2 Example of data reception OUT token reception
9. deleted Note 2 Only 1 can be written Page 681 of 1243 Descriptions for the PPPEMAXP MXPS 8 0 bits in 25 2 28 are corrected as follows Before correction Specifies the maximum data payload maximum packet size for the selected pipe These bits should be set to the appropriate value for each transfer type based on USB Specifications 2 0 While MXPS 8 0 0 do not write to the FIFO buffer or set PID to BUF After correction Specifies the maximum data payload maximum packet size for the selected pipe These bits should be set to the appropriate value for each transfer type based on USB Specifications 2 0 Note that the maximum value for PIPE and PIPE2 is 256 While the MXPS 8 0 bits are 000h do not write to the FIFO buffer or do not set the PID 1 0 bits to 01b BUF ePages 683 688 of 1243 The note for bits SQSET and SQCLR of the PIPEnCTR register in 25 2 30 is corrected as follows Before correction Note 1 Only 0 can be read Only can be written After correction Note 1 This bit is read as 0 Page 697 of 1243 The descriptions in 25 3 1 2 are corrected as follows Before correction For the USB the host or function controller can be selected using the DCFM bit in SYSCFG The DCFM bit should be modified in the initial settings immediately after a power on reset or in the D pull up disabled SYSCFG DPRPU bit 0 and D and D pull down disabled SYSCFG DRPD bit 0 state After correction For the USBO th
10. e correction 1 Counter Initialization when Function Controller is Selected The USB initializes the interval counter under the following conditions e Power on Reset The PIPEPERI IITV 2 0 bits are initialized Buffer memory initialization using the ACLRM bit The ITV 2 0 bits are not initialized but the count value is initialized After correction 1 Counter Initialization The interval counter is initialized when the MCU is reset or when the PIPEnCTR ACLRM bit is set to 1 The PIPEPERI IITV 2 0 bits are not initialized when the interval counter is initialized by using the ACLRM bit 2ENESAS Page 11 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 Page 736 of 1243 The descriptions for SOF Interpolation Function in 25 3 10 are corrected as follows Before correction 25 3 10 SOF Interpolation Function When the function controller is selected and if data could not be received at intervals of 1 ms because an SOF packet was corrupted or missing the USB interpolates the SOF The SOF interpolation operation begins when the USBE and SCKE bits in SYSCFG have been set to 1 and an SOF packet is received The interpolation function is initialized under the following conditions e Power on reset e USB bus reset e Suspended state detected The SOF interpolation operates as follows The interpolation function is not activated until an SOF packet is received e After the first SOF packet is received interpolatio
11. e host controller function or function controller function can be selected using the SYSCFG DCFM bit Set the DCFM bit during initialization after a reset is released or while D pull up and D D pull down are disabled bits SYSCFGDPRPU and SYSCFG DRPD are 0 2ENESAS Page 5 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 Page 708 of 1243 Figure 25 8 is corrected as follows Before correction 1 Example of zero length packet reception or data packet reception when BFRE 0 single buffer mode i USB bus Token Packet Data Packet ACK Handshake EIFO buffer status Ready for reception Ready for read access BRDY interrupt P change in corresponding i bit in PIPEBRDY A BRDY interrupt is generated because the buffer becomes ready for read access 2 Example of data packet reception when BFRE 1 single buffer mode USB bus Token Packet lt Last gt Data Packet ACK Handshake Li L FIFO buffer status Ready for reception Ready for read access i cere BRDY interrupt change in corresponding i i bit in PIPEBRDY 4 A The buffer becomes A BRDY interrupt is generated ready for read access because the transfer has ended g 3 Example of packet transmission single buffer mode USB bus Token Packet Data Packet ACK Handshake FIFO buffer status Ready for transmission Ready for write access BRDY interrupt P i OSOSCSS change in corresponding i bit i
12. eration in 16 Bit Access CFIFOSEL BIGEND Bit DOFIFOSEL BIGEND Bit MDE MDE 2 0 bits 000b big endian D1FIFOSEL BIGEND Bit 0 little endian Bits 15 to 8 Data in address N 1 Bits 7 to 0 Data in address N Remarks Bytes reversed 1 big endian Data in address N Data in address N 1 111b little endian 0 little endian Data in address N 1 Data in address N 1 big endian Data in address N Data in address N 1 Bytes reversed stENESAS Page 3 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 Page 651 of 1243 The note for the BCLR bit in registers CFIFOCTR DOFIFOCTR and DIFIFOCTR in 25 2 6 is added as follows Note 1 This bit is read as 0 Page 651 of 1243 The following note for the BVAL bit in registers CFIFOCTR DOFIFOCTR and DIFIFOCTR in 25 2 6 is deleted Note 1 Only 1 can be written Page 659 of 1243 The notes for the value after reset of the INTSTSO register in 25 2 13 are corrected as follows Before correction b15 b14 b13 b12 b11 bi0 b9 b8 b7 b6 b5 b4 b3 b2 b1 bO 0 0 0 id 0 0 0 0 0 0 4 0 0 0 0 Value after reset 0 1 0 1 Note 1 The value is 0 after a power on reset and 1 after a USB bus reset Note 2 The value is 1 when the USBO_VBUS pin is high and 0 when the USBO_VBUS pin is low Note 3 The value is 000b after a power on reset and 001b after a USB bus reset After correction b15 b14 b13 b12 b11 b10 b9 b8 b7 VBINT
13. n PIPEBRDY A BRDY interrupt is generated because the buffer becomes ready for write access C Packet transmitted by host device C Packet transmitted by function device Note 1 The ACK handshake is not used in isochronous transfers Note 2 The FIFO buffer becomes ready for read access under the following condition When a packet is received while no data remains unread in the buffer in the CPU Note 3 A transfer ends under either of the following conditions 1 When a short packet including a zero length packet is received 2 When the number of packets specified in the transaction counter are received Figure 25 8 Timing of BRDY Interrupt Generation stENESAS Page 6 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 After correction 1 Example of zero length packet reception or data packet reception when BFRE 0 single buffer mode A USB bus Token Packet Data Packet ACK Handshake FIFO buffer status Ready for reception Ready for read access BRDY interrupt BRDYSTS PIPEnBRDY bit A BRDY interrupt occurs because the F FO buffer becomes ready for read access 2 Example of data packet reception when BFRE 1 single buffer mode USB bus Token Packet lt Last gt Data Packet ACK Handshake FIFO buffer status Ready for reception Ready for read access i BRDY interrupt i BRDYSTS PIPEnBRDY bit A The FIFO buffer becomes ready for read access A BRDY interrupt occurs be
14. n Packet Data Packet Maximum 1 STALL Handshake Packet size over I BEMP interrupt change in corresponding bit in PIPEBEMP A NRDY interrupt is generated C Packet transmitted by host device C Packet transmitted by function device Note 1 The handshake is not used in isochronous transfers Figure 25 10 Timing of BEMP Interrupt Generation When Function Controller is Selected After correction 1 Example of data transmission USB bus IN Token Packet Data Packet ACK Handshake FIFO buffer status Ready for transmission Ready for write access i there is no data to be 1 transmitted 1 BEMP interrupt BEMPSTS PIPEnBEMP bit A A BEMP interrupt occurs 2 Example of data reception USB bus OUT Token Packet DEG PEGG Merdmum STALL Handshake packet size over BEMP interrupt BEMPSTS PIPEnBEMP bit A BEMP interrupt occurs Packet transmitted by the host device C Packet transmitted by the function device Note 1 The handshake is not used in isochronous transfers Figure 25 10 Timing of BEMP Interrupt Generation When Function Controller Function is Selected stENESAS Page 10 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 Page 726 of 1243 The descriptions for 4 Control Transfer Auto Response Function in 25 3 6 2 are added as follows 4 Control Transfer Auto Response Function The USB automatically responds to a correct SET ADDRESS request If any
15. n is carried out by counting 1 ms with an internal clock of 48 MHz After the second and subsequent SOF packets are received interpolation is carried out at the previous reception interval Interpolation is not carried out in the suspended state or while a USB bus reset is being received The USB supports the following functions based on the SOF packet reception These functions also operate normally with SOF interpolation if the SOF packet was missing Updating of the frame number e SOFR interrupt timing e Isochronous transfer interval count If an SOF packet is missing the FRMNUM FRNM 10 0 bits are not updated After correction 25 3 10 SOF Recovery Function When the function controller is selected and if data could not be received at intervals of 1 ms because an SOF packet was corrupted or missing the USB recovers the SOF The SOF recovery operation begins when the USBE and SCKE bits in SYSCFG have been set to 1 and an SOF packet is received The recovery function is initialized under the following conditions e MCU reset e USB bus reset e Suspended state detected The SOF recovery operates as follows The recovery function is not activated until an SOF packet is received e After the first SOF packet is received recovery is carried out by counting ms with an internal clock of 48 MHz e After the second and subsequent SOF packets are received recovery is carried out at the previous reception interval Recovery is not
16. us Ready for read access there is no space to receive data ii NRDY interrupt NRDYSTS PIPEnNRDY bit L CRCE bit etc An NRDY interrupt occurs 3 Example of data reception PING token reception single buffer mode I USB bus PING Packet NAK Handshake FIFO buffer status 1 I I Ready for read access there is no space to receive data I 1 NRDY interrupt NRDYSTS PIPEnNNRDY bit A An NRDY interrupt occurs Packet transmitted by the host device __ Packet transmitted by the function device Note 1 The handshake is not used in isochronous transfers Note 2 The PIPEnNRDY bit is set to 1 only while the PIPEnCTR PID 1 0 bits are set to 01b BUF response Note 3 The CRCE and the OVRN bits change only while the target pipe is set to isochronous transfers Figure 25 9 Timing of NRDY Interrupt Generation When Function Controller Function is Selected stENESAS Page 9 of 12 RENESAS TECHNICAL UPDATE TN RX A106A E Date Sep 29 2014 Page 712 of 1243 Figure 25 10 is corrected as follows Before correction 1 Example of data transmission USB bus IN Token Packet H Data Packet H ACK Handshake Buffer status Ready for transmission Ready for write access i there is no data to be 1 transmitted 1 BEMP interrupt change in corresponding bit in PIPEBEMP A NRDY interrupt is generated 2 Example of data reception L I USB bus OUT Toke
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