Correction for Incorrect Description Notice RL78/G12 Descriptions in
Contents
1. 4 38 us Note 5 Note 5 fcik 4 84 fcLk 84 us 42 us 21 us 10 5 us 5 25 us 3 5 us Note 5 Note 5 Note 6 foiw 2 A2ifak 42us 214s 10 5ys 5 2548 2 625yus Setting Note 5 Note 5 Note 6 prohibited Low fc1 32 17 fap 608 fcik Setting Setting Setting 76 us 384s 25 33 us voltage prohibited prohibited prohibited Number of 2 fcrx 16 sampling 304 fcLk 76 us 38 us 19us 12 67 us ote foik 8 clock 5 152 fcik 76 us 38 us 19us 9 5 us 6 33 us 5 fAD fcik 6 114 fcik 57 4S 28 5 us 14 25us 7 125us 4 75 us Note 5 Note 5 fcik 5 95 fcik 47 5 us 23 75 us 11 875 us 5 938 us 3 96 us Note 5 Note 5 fcLk 4 76 fcLk 76 us 38 us 9 5 us 4 75 us 3 1718 Note 5 Note 5 Note 6 four 2 38 fk 38us 19 ns 5 Us 4 75us 2 375 us Setting Note 5 Note 6 prohibited Setting prohibited Omitted RE Page 13 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Correct Table 10 3 A D Conversion Time Selection 2 Low voltage Mode Note 1 Date Oct 11 2012 When there is no stabilization wait time software trigger mode hardware trigger no wait mode A D Converter Mode Register 0 ADMO FR2 FR1 FRO LV1 LVO Low voltage 1 Conversion Clock fap feik 32 fcik 16 fcik 8 fcik 6 feik 5 fcik 4 feik 2 Number of2. HOCODIV changed Incorrect descriptions of A D converter mode register 0 ADMO revised Page 297 time selection revised Incorrect descriptions of Figure 19 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector Pages 6 0 6 1 Pages 16 t019 revised Cautions on 24 4 Overview of the data flash Page 722 Page 20 memory added Incorrect descriptions of 24 6 Security Settings revised Page te Page 21 Table 24 12 Security Setting in Each Programmable Mode deleted Page 730 Cautions on 24 7 Flash Memory Programming by Self Programming added Page 731 Page 23 14 Incorrect descriptions of 24 7 1 Flash shield Page 733 Page 24 window function revised Specifications of 28 8 Flash Memory Programming Characteristics determined Page 804 Page 25 ine Correct Gray hatched RE Page 2 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 1 Outline for differences of the RL78 G12 R5F102 and R5F103 added Differences between the R5F102 and R5F103 pages 1 2 Addition CHAPTER 1 OUTLINE 1 1 Differences between the R5F102 and R5F103 Differences between the R5F102 and R5F103 of the RL78 G12 are as follows Data flash mounted not mounted High speed on chip oscillator oscillation frequency accuracy Number of channels of the serial interface DMA function mounted not mounted Safety function mounted not mounted 1 1 1 Data Flash The R5F102 mounts 2KB data flash and
3. In the R5F102Ax when setting to PIORO 1 The number of outputs varies depending on the setting of channels in use and the number of the master see 6 8 3 Operation as multiple PWM output function Caution Since individual library is used when rewriting the flash memory using the user program flash ROM and RAM areas are used Confirm the RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual before using these products ze Page 6 of 26 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 3 Cautions for Memory Map R5F10266 R5F10366 added Page 24 Incorrect Figure 3 1 Memory Map for the R5F10266 and R5F10366 Omitted Notes 1 f the area FEE20H to FFEFFH is prohibi when_using th lf programming function an flash function a his area i for self programming library Omitted Correct Figure 3 1 Memory Map for the R5F10266 and R5F10366 Omitted Notes 1 When rewriting the data flash allocate the stack used for the data flash library to FFEA2H to FFEDFH and the RAM address used for the data flash and DMA transfer to FFEOQOH to FFE19H Fore more details refer to the RL78 Family Data Flash Library Type04 User s Manual Omitted Cautions 2 Since the R5F10266 includes small RAM size of 256 bytes a stack area to execute the data flash library cannot be saved depending on the customer s program specification and writing erasing t
4. 20 years Ta 85 C 10 000 Notes 1 1 erase 1 write after the erase is regarded as 1 rewrite The retaining years are until next rewrite after the rewrite 2 When using flash memory programmer and Renesas Electronics self programming library 3 This characteristics is shown as the flash memory characteristics and based on Renesas Electronics reliability test R Page 25 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 Issued Document History RL78 G12 User s Manual Hardware Rev 1 00 incorrect description notice issued document history Document Number TN RL A002A E Oct 11 2012 First edition issued Incorrect descriptions of No 1 to No 15 revised ze Page 26 of 26 8 lt ENESAS
5. Back Ground Operation BGO is supported Accessing the data flash memory is not possible while rewriting the code flash memory during self programming Because the data flash memory is stopped after a reset ends the data flash control register DFLCTL must be set up in order to use the data flash memory e Manipulating the DFLCTL register is not possible while rewriting the data flash memory e Transition the HALT STOP mode is not possible while rewriting the data flash memory Cautions 1 While the data flash is being rewritten interrupts are disabled only for the R5F10266 Execute the data flash library in the state where the IE flag is cleared 0 by the DI instruction 2 The high speed on chip oscillator needs to oscillate while the data flash is being rewritten When stopping the high speed on chip oscillator oscillate the high speed on chip oscillator clock HIOSTOP 0 and execute the data flash library after 30 us elapses R Page 20 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 11 Incorrect descriptions of Security Settings revised page 729 Incorrect 24 6 Security Settings The RL78 G12 supports a security function that prohibits rewriting the user program written to the internal flash memory so that the program cannot be changed by an unauthorized person The operations shown below can be performed by using the Security Set command Omitted The block erase write and rewriting boot cluste
6. Family Data Flash Library Type04 User s Manual R5F10266 FFE20H to FFEA1H FFEEOH to FFEFFH Allocate the stack used for the data flash library to FFEA2H to FFEDFH and the RAM address used for the data buffer and DMA transfer to FFEQOH to FFE19H R5F102mn R5F103mn FFE20H to FFEFFH m Pin count symbol m 6 7 A n ROM size symbol n 7 8 9 A 3 Since RAM areas of the products shown below is used for the self programming library and data flash library its area cannot be used refer to Figures 3 3 to 3 5 Memory Map R5F102m8 R5F103m8 FFCOOH FFC80H R5F102m9 R5F103m9 FFBOOH FFC80H R5F102mA R5F103mA FFQOOH FFC80H m Pin count symbol m 6 7 R Page 8 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 5 Cautions on Correspondence Between Data Memory and Addressing R5F10266 R5F10366 added page 38 Incorrect Figure 3 8 Correspondence between Data Memory and Addressing for the R5F10266 and R5F10366 Omitted Notes 1 FEE20H to FFEFFH ar lf programming librari nnot lf programming function an flash function ar Omitted Correct Figure 3 8 Correspondence between Data Memory and Addressing for the R5F10266 and R5F10366 Notes 1 When rewriting the data flash allocate the stack used for the data flash library to FFEA2H to FFEDFH and RAM address for the data buffer and DMA transfer to FFEOOH to FFE19H For more details refer to the RL78 Family Data Flash Library Type04 User s M
7. of Generation of Internal Reset inc rre i describtioris Signal by Power on reset Circuit and Voltage Pages 670 671 revised P Detector 24 4 Overview of the data flash memory Page 722 Cautions added 24 6 Security Settings Page 729 Incorrect descriptions revised ee 24 12 Security Setting in Each Programming Page 730 Deleted 24 7 Flash memory programming by Page 731 Gnulione added self programming 24 7 1 Flash shield window function Page 733 Incorrect descriptions revised p ian Specifications 28 8 Flash memory programming characteristics Page 804 Document Improvement The above corrections will be made for the next revision of the User s Manual Hardware c 2012 Renesas Electronics Corporation All rights reserved Page 1 of 26 stENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 Corrections in the User s Manual Hardware Corrections and Applicable Items Document No for corrections 1 1 Outline for differences of the RL78 G12 Pages 1 2 R5F102 and R5F103 added l Page 11 Cautions for Figure 3 1 Memory Ma RSF 10266 R5F10366 added Pages 24 Explanations for cautions on internal data oP memory space control Pages 36 44 46 Page 8 register general purpose register added Cautions on Figure 3 8 Correspondence P Between Data Memory and Addressing for Page 38 Page 9 the R5F10266 and R5F10366 added Cautions on the high speed on chip n oscillator frequency selection register Page 155 Page 10
8. started require the following the reset processing time by LVD required after the voltage has reached LVD detection level VLVDH in addition to the reset processing time by POR and the voltage stabilization wait time required after the voltage has reached VPOR 1 51 V TYP Reset processing time by LVD 0 ms to 0 0701 ms MAX RENESAS Page 18 of 26 RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 3 LVD reset mode option byte 000C1H LVIMDS1 LVIMDSO 1 1 Supplyvoltage VoD VLvD Operating voltage range lower limit setting Vpor 1 51 V TYP Vpor 1 50 V TYP ov i i i Wait for oscillation Wait for oscillation Wait for oscillation accuracy stabilizationN te 2 i accuracy stabilizationN adcuracy stabilization 1 1 aes 1 f i i Note 2 High speed onchip oscillator clock iH i Starting oscillation is i Starting oscillation is o Starting oscillation s High speed H f j peched by software H y specified by sdftware 1 a specified by softwate system clock fix i f ro when X1 osci tion 1 i is seleted Normal operation Reset Normaloperation ko it Normal operation i As period ioh chin 7 Reset peiod ro A i high speed onchip foacilition high speed on chip ggciletion stop high speed on chip Operati _oscillator clock stop oscillator clock i oscillator clock Notet peration in uP p a oe oe eae st
9. the R5F103 does not mount the data flash Part Number Data Flash R5F102 2KB R5F1026A R5F1027A R5F102AA R5F10269 R5F10279 R5F102A9 R5F10268 R5F10278 R5F102A8 R5F 10267 R5F10277 R5F102A7 R5F 10266 R5F103 Not mounted R5F1036A R5F1037A R5F103AA R5F10369 R5F10379 R5F103A9 R5F 10368 R5F10378 R5F103A8 R5F10367 R5F10377 R5F103A7 R5F 10366 Note Since the R5F10266 includes small RAM size of 256 bytes a stack area to execute the data flash library cannot be saved depending on the customer s program specification and writing erasing to the data flash may not be able to performed Caution Since individual library is used when rewriting the flash memory using the user program flash ROM and RAM areas are used Refer to the RL78 Family Flash Self Programming Library Type01 User s Manual and RL78 Family Data Flash Library Type04 User s Manual before using these products R Page 3 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 1 1 2 On chip oscillator characteristics 1 High speed on chip oscillator oscillation frequency accuracy of the R5F102 High speed on chip TA 20 to 85 C oscillator oscillation TA 40 to 20 C frequency accuracy 2 High speed on chip oscillator oscillation frequency accuracy of the R5F103 High speed on chip oscillator oscillation TA 40 to 85 C 5 5 frequency accuracy 1 1 3 Peripheral functi
10. Conversion Clock 19 fap Number of sampling clock 7 faD Conversion Time 608 fcLk Conversion Time Selection 1 8V lt Vpp lt 5 5V Note 2 304 fcLk 152 fcik 114 fcik Setting prohibited fcik 2 MHz Setting prohibited fck 4 MHz Setting prohibited 76 4s fcik 16 MHz 25 33 us 76 us 38 Us 12 67 us 76 4S 38 us 19 us 6 33 us 57 4S 28 5 us 14 25 1s Note 4 4 75 us 95 fcLk 95 us 47 5 1s 23 75 4S 11 875 us Note 4 3 96 us 76 fcLk 76 us 38 us 19 us 9 5 us Note 4 3 17 us Note 5 38 fcLk 38 us 19 us 9 5 us Note 4 4 75 us Note 4 Setting prohibited Low voltage feik 32 2 fcik 16 fcik 8 fcik 6 feik 5 fcik 4 feik 2 17 fab Number of sampling clock 5 faD 544 fcik 272 fcik 136 fcLk 102 fcik Setting prohibited Setting prohibited Setting prohibited 68 us 22 667 1s 68 us 34 us 11 333 ps 68 us 34 us 17 us 5 667 us 51 us 25 5 us 12 7518 Note 4 4 25 us 85 fcik 85 us 42 5 us 21 25 us 10 625 us Note 4 3 542 us 68 fcLk 68 us 34 us 8 5 us Note 4 2 833 us Note 5 34 fcLk 34 us 17 us 4 25 1s Note 4 Setting prohibited Other than the above Setting prohibited Omitte
11. Date Oct 11 2012 RENESAS TECHNICAL UPDATE 1753 Shimonumabe Nakahara ku Kawasaki shi Kanagawa 211 8668 Japan Renesas Electronics Corporation Product Document x Category MPU MCU No TN RL A002A E Rev 1 00 Correction for Incorrect Description Notice Information Title RL78 G12 Descriptions in the Hardware User s Manual Cat Technical Notification Rev 1 00 Changed ategory Lot No Applicable RL78 G12 Group Reference Product R5F102xxx R5F103xxx All lot Document RL78 G12 User s Manual Hardware Rev 1 00 R01UH0200EJ0100 Mar 2012 This document describes misstatements found in the RL78 G12 User s Manual Hardware Rev 1 00 R01UH0200EJ0100 Corrections Applicable Item Applicable Page 1 1 Differences of 1 1 RL78 G12 products R5F102 and R5F103 Pages 1 and 2 Outline added 1 6 Outline of Functions Page 11 Cautions added E aN Memory Map for the R5F10266 and Page 24 Cauti nsad d Cautions on internal data memory space control Pages 36 44 46 Explanations added register general purpose register Figure 3 8 Correspondence Between Data Memory and Addressing for the R5F10266 and R5F10366 Page 38 cautions added High speed on chip oscillator frequency selection register HOCODIV Page 155 Cautions changed A D converter mode register 0 ADMO Page 297 incomeci descriptions revised A D conversion time selection Pages 302 304 Incorrect descriptions revised Figure 19 2 Timing
12. ENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 Correct Figure 19 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector 1 When the external reset input via RESET pin is used VDD Operating voltage range lower limit setting Vpor 1 51 V TYP VPoR 1 50 V TYP Supply voltage voo 10 us min RESET signal Wait for oscillation Wait for oscillation accuracy stabilization i accuracy stabilization 1 m i High speed on chip oscillator clock fin Starting oscillation is Starting oscillation is High d specified by software specified by software igh spee Lot system clock fmx eo f when X1 oscillation oye SMB 1 Reset is selected a ee Normal operation period Reset ifort ime thigh sp ed on chip external re relea n A illati 1 external re elea f Puf y the external reset i se high speed on chip oscillator clock Note2 E y the extemal reset release Seciliator clock Note 2 i CPU Operation mia SIOP na e e Operation stops Voltage stabilization wait time Voltage stabilization wait time 4 0 99 ms TYP 2 30 ms MAX f i 0 99 ms TYP 2 30 ms MAX i i Note3 Normal operation Internal reset signal i Omitted Notes 3 The time until normal operation is started require the following the reset processing time by the external reset release required after RESET signal has been set t
13. ain mode 1 MHz to 16 MHz 2 4 V to 5 5 V 1 MHz to 24 MHz 2 7 V to 5 5 V 2 Set the HOCODIV register while the high speed on chip oscillator clock fiH is selected as the CPU peripheral hardware clock fcLK 3 After the frequency has been changed using the HOCODIV register and the following transition time has been elapsed the frequency is switched e The device operates at the frequency for the duration of 3 clocks before the frequency has been changed e The CPU peripheral hardware clock waits for maximum 3 clocks at the frequency after the frequency has been changed R Page 10 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 7 Incorrect descriptions of A D converter mode register 0 ADMO revised page 297 Incorrect 2 A D converter mode register 0 ADMO Omitted Cautions 1 Change the ADMD FR2 to FRO LV1 LVO and ADCE bits whil nversion i ADCS 2 Do not change the ADCE and ADCS bits from 0 to 1 at the same time by using an 8 bit manipulation instruction Be sure to set these bits in the order described in 10 7 A D Converter Setup Flowchart Correct 2 A D converter mode register 0 ADMO Omitted Cautions 1 Change the ADMD FR2 to FRO LV1 and LVO bits while conversion is stopped ADCS 0 ADCE 0 2 Do not set ADCS 1 and ADCE 0 3 Do not change the ADCS and ADCE bits from 0 to 1 at the same time by using an 8 bit manipulation instruction Be sure to set these b
14. anual Omitted Cautions 2 Since the R5F10266 includes small RAM size of 256 bytes a stack area to execute the data flash library cannot be saved depending on the customer s program specification and writing erasing to the data flash may not be able to be performed For more details refer to the RL78 Family Data Flash Library Typ04 User s Manual 3 The self programming function cannot be used for the R5F10266 and R5F 10366 ze Page 9 of 26 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 6 Cautions on the high speed on chip oscillator frequency selection register HOCODIV changed page 155 Incorrect 8 High speed on chip oscillator frequency selection register HOCODIV Omitted Option byte 000C2H value Operating frequency Operating voltage Flash operation mode A BE range range S low speed main mode 1 MHz to 8 MHz 1 8 V to 5 5 V 1 MHz to 16 MHz 2 4 V to 5 5 V HS high speed main mode 1 MHz to 24 MHz 2 7 V to 5 5 V Correct 8 High speed on chip oscillator frequency selection register HOCODIV Omitted Cautions 1 Set the HOCODIV register within the operable voltage range of the flash operation mode set in the option byte 000C2H before and after the frequency change Option byte 000C2H value Operating frequency Operating voltage Flash operation mode CMODE1 CMODE2 range range LS low speed main mode 1 MHz to 8 MHz 1 8 V to 5 5 V HS high speed m
15. d Cautions 1 Rewrite the FR2 to FRO LV1 and LVO bits to other than the same data while conversion ADCE 0 is stopped ADCS 0 R Page 14 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 4 Low voltage Mode When there is stabilization wait time hardware trigger wait mode A D Converter Mode Conversion Number of Number of Stabilization Stabilization Wait Time Conversion Time Selection Register 0 ADMO Clock _ stabilization Conversion Wait Time 1 8 V lt VDD lt 5 5 V Note3 Note4 fao wait clock Clock Conversion FR2 FR1 FRO LV1 LVO fctk fck fck fck Time 2 MHz 4 MHz 16 MHz 24 MHz Low fc1 32 19 fap 672 fc x Setting Setting Setting 84 us 42 us 28 us voltage Number of prohibited prohibited prohibited umber o 1 fo16 sampling 336 fcux 844s 42 s 21us 1448 fork 8 clock 7 168 fck 84us 42 us 21 us 10 5us 7 us fan Note 5 fcLk 6 126 fcLk 63 us 31 25 ws 15 7548 7 875 us 5 25 us Note 5 Note 5 fcik 5 105 fcik 52 5 us 26 25 us 13 1256 6 563us 4 38 us Note 5 Note 5 fcik 4 84 fcLk 84 us 42 us 21 us 10 5 us 5 25 us 3 5 us Note 5 Note 5 Note 6 foiw 2 A2ifak 42us 214s 10 5ys 5 2548 2 625yus Setting Note 5 Note 5 Note 6 prohibited Low fcrx 32 17 fap 608 fcik Setting Setting Setting 76 us 384s 25 33 us voltage prohib
16. foix 8 clock 5 136 fc x 68 us 34us 17 us 5 5 667 us faD fcik 6 102 fcik 51 us 25 5 us 12 7518 4S 4 25 us Note 4 feik 5 85 fcLk 42 5 us 21 25 s 10 625 us 3 542 us Note 4 fcik 4 68 fcLk 68 us 34 us 8 5 us 2 833 us Note 4 Note 5 foix 2 34 fax 34us 17 us 5 ys 4 258 Setting Note 4 prohibited Other than the above Setting prohibited R Page 12 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 4 Low voltage Mode When there is stabilization wait time hardware trigger wait mode A D Converter Mode Conversion Number of Number of Stabilization Stabilization Wait Time Conversion Time Selection Register 0 ADMO Clock _ stabilization Conversion Wait Time 1 8 V lt VDD lt 5 5 V Note3 Note4 fao wait clock Clock Conversion FR2 FR1 FRO LV1 LVO fctk fck fck fck Time 2 MHz 4 MHz 16 MHz 24 MHz Low fc1 32 19 fap 672 fc x Setting Setting Setting 84 us 42 us 28 us voltage Number of prohibited prohibited prohibited umber o 1 fo x 16 sampling 336 fcux 844s 42 s 21us 1448 fork 8 clock 7 168 fck 84us 42 us 21 us 10 5us 7 us fan Note 5 fcLk 6 126 fcLk 63 us 31 25 ws 15 7548 7 875 us 5 25 us Note 5 Note 5 fcik 5 105 fcik 52 5 us 26 25 us 13 1256 6 563us
17. he only access by CPU instructions is byte reading 4 clock wait 3 clock cycles Because the data flash memory is an area exclusively used for data it cannot be used to execute instructions code fetching Instructions can be executed from the code flash memory while rewriting the data flash memory That is Back Ground Operation BGO is supported Accessing the data flash memory is not possible while rewriting the code flash memory during self programming Because the data flash memory is stopped after a reset ends the data flash control register DFLCTL must be set up in order to use the data flash memory Manipulating the DFLCTL register is not possible while rewriting the data flash memory Transition the HALT STOP mode is not possible while rewriting the data flash memory Correct An overview of the data flash memory is provided below For more details of rewriting the data flash memory refer to the RL78 Family Data Flash Library Type04 User s Manual The data flash memory can be written to by using the flash memory programmer or an external device Programming is performed in 8 bit units Blocks can be deleted in 1 KB units The only access by CPU instructions is byte reading 1 clock wait 3 clock cycles Because the data flash memory is an area exclusively used for data it cannot be used to execute instructions code fetching Instructions can be executed from the code flash memory while rewriting the data flash memory That is
18. ited prohibited prohibited Number of 2 fcrx 16 sampling 304 fcLk 76 us 38 us 19us 12 67 us ote foik 8 clock 5 152 fcik 76 us 38 us 19us 9 5 us 6 33 us 5 fAD fcik 6 114 fcik 57 4S 28 5 us 14 25us 7 125us 4 75 us Note 5 Note 5 fcik 5 95 fcik 47 5 us 23 75 us 11 875 us 5 938 us 3 96 us Note 5 Note 5 fcLk 4 76 fcLk 76 us 38 us 9 5 us 4 75 us 3 1718 Note 5 Note 5 Note 6 four 2 38 fk 38us 19 ns 5 Us 4 75us 2 375 us Setting Note 5 Note 6 prohibited Other than the above Setting prohibited Omitted Cautions 1 Rewrite the FR2 to FRO LV1 and LVO bits to other than the same data while conversion is stopped ADCS 0 ADCE 0 RE Page 15 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 9 Incorrect descriptions of the power on reset circuit on Figure 19 2 revised pages 670 and 671 Incorrect Figure 19 2 Timing of Generation of Internal Reset Signal by Power on reset Circuit and Voltage Detector a When LVD is OFF option byte 000C1H VPOC2 1 Supply voltage VoD Operating voltage range lower limit setting VPOR 1 51 V TYP VPoR 1 50 V TYP ov i 10 us min 10 us min External RESET signal Wait for oscillation i Wait for oseill tion accuracy stabilization i accuracy sta slizationNet 1 Dame i pien i i High
19. its in the order described in 10 7 A D Converter Setup Flowchart ze Page 11 of 26 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 8 Incorrect descriptions of A D conversion time selection revised pages 302 and 304 Incorrect Table 10 3 A D Conversion Time Selection 2 Low voltage Mode When there is no stabilization wait time software trigger mode hardware trigger no wait mode A D Converter Mode Conversion Number of Conversion Conversion Time Selection Register 0 ADMO Clock fap Conversion Time 1 8V lt Vpp lt 55V Note 2 Clock FR2 FR1 FRO LV1 LVO fcik fck fcik 2 MHz 4 MHz 16 MHz Low fcik 32 19 fap 608 fcik Setting Setting Setting 76 us 25 33 us voltage Number of prohibited prohibited prohibited umber oO 1 fcLk 16 sampling 304 fcLk 76 us 38 us Ls 12 67 us foik 8 clock 7 152 fcik 76 us 38 ys 19 us 5 6 33 us faD fcik 6 114 fcik 57 4S 28 5 us 14 2545 LS 4 75 4S Note 4 foix 5 95 fcik 47 5 1s 23 75 us 11 8755 us 3 96 us ote 4 fcik 4 76 fcLk 76 us 38 us 19 us 9 5 us 3 17 us Note 4 Note 5 fc k 2 38 fk 38ys 19us 9 5us 4 75 us Setting Note 4 Note 4 prohibited Low feik 32 17 fap 544 fc x Setting Setting Setting 68 ys 22 667 4s voltage Number of prohibited prohibited prohibited umber oO 2 fox 16 sampling 272 feux 68 us 34 us US 11 333 ps
20. o high level 1 in addition to the voltage stabilization wait time required after the voltage has reached VPOR 1 51 V TYP Reset processing time by the external reset release 0 672 ms TYP 0 832 ms MAX When LVD is used 0 399 ms TYP 0 519 ms MAX When LVD off R Page 17 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Supplyvoltage VoD VLVDH VLVDL Operating voltage range lower limit setting Vpor 1 51 V TYP Vor 1 50 V TYP ov High speed onchip oscillator clock iH High speed system clock fix when X1 oscidtion is seleted cpu Operation stops Internal reset sgnal Date Oct 11 2012 2 LVD interrupt amp reset mode option byte 000C1H LVIMDS1 LVIMDSO 1 0 Wait for oscillation accuracy stabilizationN i a j 1 Normal operation high speed on chip oscilbtor clock 1 se Wait for oscillation accuracy stabilizationN t 2 l Starting oscillation is specified by software Normal operation high speed on chip oscillator clock Not 1 Reset paiod oscillation stop Operation yt Le stops Reset processing timetly LVDN t 4 Voltage stabilization wait time and reset processing timeby POR 1 64 msTYP 3 10 msMAX Reset processing timeby LVDY e 4 Voltage stabilization wait time and reset processing timeby POR 1 64 ms TYP 3 10 msMAX INTLVI Omitted Note 4 The time until normal operation is
21. o the data flash may not be able to be performed For more details refer to the RL78 Family Data Flash Library Typ04 User s Manual 3 The self programming function cannot be used for the R5F10266 and R5F10366 ze Page 7 of 26 8 lt ENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 4 Explanations for cautions on internal data memory space control register qgeneral purpose register added Pages 36 44 46 Incorrect Cautions 1 It is prohibited to use the general purpose register space FFEEQOH to FFEFFH for fetching instructions or as a stack area The internal RAM in the following pr nn k memory when using th lf programming function an flash function refer to figure 3 1 to 3 6 Memory Map R5F10x66 R5F10x67 R5F10x77 R5F10xA7 FFE20H FFEFFH R5F10xA8 R5F10xA9 RSF10xAA R5F10x68 R5F10x78 FFE20H to FFEFFH FEFCOOH to FFC80H R5F10x69 R5F10x79 FFE20H to FFEFFH FEFBOOH to FFC80H R5F10x6A R5F10x7A FFE20H to FFEFFH FF900H to FEC80H x 2 3 Correct Omitted Cautions 1 It is prohibited to use the general purpose register space FFEEQOH to FFEFFH for fetching instructions or as a stack area 2 When self programming or rewriting the data flash do not allocate the stack used by individual library and RAM address used for the data buffer and DMA transfer to RAM areas of the products shown below For more details refer to the RL78 Family Flash Self Programming Library Type01 Users Manual and RL78
22. ons There are differences of peripheral functions listed in the table below between the R5F102 and R5F103 oo Remo o O OoOo RB O RL78 G12 20 and 24 pin 20 and 24 pin 30 pin products 30 pin products products products 2 channels 3 channels 1 channel Simplified 1 C 2 channels 3 channels None DMA Function 2 channels None Safety Function CRC calculation Included None R Page 4 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 2 Cautions on Outline of Functions added Page 11 Incorrect 1 6 Outline of Functions This outline describes the function at the time when Peripheral I O redirection register PIOR is set to OOH except timer output of 30 pin products with data flash 1 2 Dataflashmemoy 28 28s 28e Omitted mites O 418 PWM Output 3 3 7 N The number of outputs varies depending on the setting of channels in use and the number of the master see 6 8 3 Operation as multiple PWM output function R Page 5 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 Correct 1 6 Outline of Functions This outline describes the function at the time when Peripheral I O redirection register PIOR is set to OOH except timer output of the R5F102Ax 1 2 Demme oe d l eel l eo mw o e e e SOS 418 PWM Output 3 3 7 N The self programming function cannot be used for the R5F10266 and R5F 10366
23. ops CPU Operation L r stops i _ Reset processing timeby LYDY i Reset processing timeby LVDN 3 Voltage stabilization wait time and Reset processing timeby LvDNee 4 i Voltage stabilization wait time and i Reset processing timeby POR Reset processing timeby POR _ 1 64 msTYP 3 10 msMAX i i 1 i 1 64 mgTYP 3 10 msMAX Omitted Note 3 The time until normal operation is started require the following the reset processing time by LVD required after the voltage has reached LVD detection level VLVD in addition to the reset processing time by POR and the voltage stabilization wait time required after the voltage has reached VPOR 1 51 V TYP Reset processing time by LVD 0 ms to 0 0701 ms MAX 4 When supply voltage falls and returns after only an internal reset occurs by the voltage detection circuit LVD the following the reset processing time by LVD is required after the voltage has reached LVD detection level VLVD Reset processing time by LVD 0 0629 ms TYP 0 0701 ms MAX RE Page 19 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 10 Cautions on overview of the data flash memory added page 722 Incorrect An overview of the data flash memory is provided below The data flash memory can be written to by using the flash memory programmer or an external device Programming is performed in 8 bit units Blocks can be deleted in 1 KB units T
24. rO commands are enabled by default when the flash memory is shipped ramming The security settings can be used in combination Table 24 11 shows the relationship between the erase and write commands when the RL78 G12 security function is enabled Caution The security function of the flash programmer does not support self programming Correct 24 6 Security Settings The RL78 G12 supports a security function that prohibits rewriting the user program written to the internal flash memory so that the program cannot be changed by an unauthorized person The operations shown below can be performed by using the Security Set command Omitted The block erase write and rewriting boot clusterO commands are enabled by default when the flash memory is shipped Security can be set only by on board off board programming The security settings can be used in combination Table 24 11 shows the relationship between the erase and write commands when the RL78 G12 security function is enabled Caution The security function of the flash programmer does not support self programming R Page 21 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E 12 Security Settings in self programming mode deleted page 730 Incorrect Date Oct 11 2012 Table 24 12 Security Setting in Each Programming Mode 1 On board off board programming Security Security Setting How to Disable Security Setting Prohibition of block erasure Prohibition of w
25. rammer Note To prohibit writing and erasing during on board off board programming refer to 24 6 Security Settings R Page 24 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 15 Specifications of the Flash Memory Programming Characteristics determined page 804 Incorrect 28 8 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Conditions System clock frequency 1 8 V lt Voo lt 5 5 V Code flash memory rewritable times 1 erase 1 write after Retained for 20 the erase is regarded years Self serial as 1 rewrite ye programming Data flash memory rewritable times The retaining years Retained for 1 1 000 000 are until next rewrite years Self serial after the rewrite jote programming Retained for 5 years Self serial programming Note When using flash memory programmer and Renesas Electronics self programming library Correct 28 8 Flash Memory Programming Characteristics Ta 40 to 85 C 1 8 V lt Von lt 5 5 V Vss 0 V Parameter Conditions System clock frequency 1 8 V lt Voo lt 5 5 V Code flash memory rewritable times Retaining years 20 years Ta 85 C a Note 1 2 3 Data flash memory rewritable times Retaining year 1 year ia 25 eNOS 1 000 000 Note 1 2 3 Retaining years 5 years Ta 85 C 100 000 Retaining years
26. riting Prohibition of rewriting boot cluster 0 Use the GUI of dedicated flash memory programmer Cannot be disabled after setting Execute security release command Cannot be disabled after setting Caution The security release command can be applied only when the security is not set as the block erase prohibition and the boot cluster 0 rewrite prohibition with code flash memory area and data flash memory area being blanks Prohibition of rewritin Correct Table 24 12 Security Setting in Each Programming Mode 1 On board off board programming Security Prohibition of block erasure Prohibition of writing Prohibition of rewriting boot cluster 0 Security Setting Use the GUI of dedicated flash memory programmer How to Disable Security Setting Cannot be disabled after setting Execute security release command Cannot be disabled after setting Caution The security release command can be applied only when the security is not set as the block erase prohibition and the boot cluster 0 rewrite prohibition with code flash memory area and data flash memory area being blanks RENESAS Page 22 of 26 RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 13 Cautions on Flash Memory Programming by Self Programming added page 731 Incorrect 24 7 Flash Memory Programming by Self Programming The RL78 G12 supports a self programming function
27. speed on chip oscillator clock fiH J Starting oscillation is Starting oscillation is High speed specified by software specified by software system clock fmx i when X1 oscillation i is selected 7 I pagel Reset processing Normal operation Normal operation oscillation high speed on chip i high speed on chip oscillator clock e stop oscillator clock gt i Operation stops Reset processing te 3 cpu Operation e i stops i 1 Internal reset signal Omitted Notes 3 Reset processing time 265 to 407 ws b When LVD is interrupt amp reset mode option byte 000C1H LVIMDS1 LVIMDSO 1 0 Supply voltage VoD Wat for oscilldion a 9 Wat for oscilldion acduracy stabilizaion 2 i ra acautacy stabiliz ion te High speed onehip oscillator clock fu i Stating oscillation is rot 1 1 Stating oscillation is A speci ed by sd vare tii i specied b y software o ae nni o L IX when X1 oscillation is seleotd Normal operation Rest i Normal operation i on period i i High speed onehip TE oscillation H High speed onehip cpu OPeraion ac oscillator clock 1 a7 stop a oscillator clock stops Rest prod ssing timate 4 a Rest proeessing timete4 j POR proessing time o i POR proessing time Internal reset signal INTLVI Omitted Notes 4 Reset processing time 497 to 720 ws ze Page 16 of 26 s lt ENESAS R
28. ted The window range can be set by specifying the start and end blocks The window range can be set or changed during both on board off board programming_and self programming Omitted Figure 24 14 Setting and changing of the flash shield window function and relations with commands Programming Setting Changing window aiaa da Specify the start block self programming and end block of the done only in the Svinte anon window in th flash window range range self programming During Specify the start block Block erasure can be Writing can be done on board off board and end block of the done also outside the also outside the programming window on the GUI of the window range window range dedicated flash memory programmer Note To prohibit writing and erasing during on board off board programming refer to 24 6 Security Settings Correct 24 7 1 Flash shield window function Omitted The window range can be set by specifying the start and end blocks The window range can be set or changed only during on board off board programming Omitted Figure 24 14 Setting and changing of the flash shield window function and relations with commands Programming Setting Changing window ia During Specify the start block Block erasure can be Writing can be done on board off board and end block of the done also outside the also outside the programming window on the GUI of the window range window range dedicated flash memory prog
29. that can be used to rewrite the flash memory via a user program Because this function allows a user application to rewrite the flash memory by using the RL78 G12 self programming library it can be used to upgrade the program in the field lf programming library in th where the IE flag i l an interr l ar h interr mask fl in wher IE flag i he El instruction and then ex h If programming library Omitted Correct The RL78 G12 supports a self programming function that can be used to rewrite the flash memory via a user program Because this function allows a user application to rewrite the flash memory by using the RL78 G12 self programming library it can be used to upgrade the program in the field Cautions 1 Interrupts are disabled during self programming Execute the self programming library in the state where the IE flag is cleared 0 by the DI instruction Omitted 3 The high speed on chip oscillator needs to oscillate during self programming When stopping the high speed on chip oscillator oscillate the high speed on chip oscillator clock HIOSTOP 0 and execute the self programming library after 30 us elapses 4 The self programming function cannot be used for the R5F10266 and R5F10366 RE Page 23 of 26 sKENESAS RENESAS TECHNICAL UPDATE TN RL A002A E Date Oct 11 2012 14 Incorrect descriptions of the Flash shield window function revised page 733 Incorrect 24 7 1 Flash shield window function Omit
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