IRAUDAMP5 - International Rectifier
Contents
1. Self Oscillating PWM Modulator Switches and Indicators Frequency Lock Synchronization Feature Schematics HERR Bill of 8 2 0 2 hbro cmm 2 2 2 Assembly 4 1 Revision changes descriptions www irf com IRAUDAMP5 REV 3 3 REFERENCE DESIGN Page 1 of 49 International Rectifier Introduction The IRAUDAMPS reference design is a two channel 120W half bridge Class D audio power amplifier This reference design demonstrates how to use the IRS2092S Class D audio controller and gate driver IC implement protection circuits and design an optimum PCB layout using the IRF6645 DirectFET MOSFETs The resulting design requires no heatsink for normal operation one eighth of continuous rated power The reference design provides all the required housekeeping power supplies for ease of use The two channel design is scalable for power and the number of channels Applications AV receivers Home theater systems Mini component stereos Powered speakers Sub woofers Musical Instrument amplifiers Automotive after market amplifiers Features Output Power 120W x 2 channels Total Harmonic Distortion THD N 1 1 kHz Residual Noise 170 IHF2. Floor Noise 20 0c 20 40 60E B V 80 100 120 140 10 20 50 100 200 500 1k 2k 5k 10k 20k Hz Red ACD No signal Self Oscillator 400kHz Blue CH2 ACD No signal Self Oscillator 400kHz Fig 7 Residual Noise ACD Channel Separation 40r A 20 40 50E d B 70E 80 E 205 100 110 1205 20 50 100 200 500 1k 2k 5k 10k 20k Hz Red CHI CH2 60W Blue CH2 CH1 60W F ig 8 Channel Separation vs Frequency www irf com IRAUDAMP5 REV 3 3 Page 8 of 49 International IER Rectifier Red Trace Total Distortion Noise Voltage Green Trace Output Voltage rigger Gil Trigger 500 mVidiv 200 200 usidiv Stop 20 500 mVidiy 200 mVidiv 200 Stop 20 mV offset 0 0 mV ofst 200kS 100MS s Edge Positive D mV offset 0 0 mV ofst 2005 100MS s Edge Positive IRAUDAMPS Theory of Operation Referring to Fig 10 below the input error amplifier of the 20925 forms a front end second order integrator with C21 C23 and R21 This integrator also receives a rectangular feedback waveform from R31 R33 and C17 into the summing node at IN from the Class D power stage switching node connection of DirectFET Q3 and DirectFET Q4 The quadratic oscillatory waveform of the switch node serves as a powered carrier signal from which the audio is recovered at the speaker load through a single stage LC
3. IER Rectitier 5 120W x 2 Channel Class D Audio Power Amplifier Using the IRS2092S and IRF6645 Jun Honda Manuel Rodr guez and Jorge Cerezo Fig 1 CAUTION International Rectifier suggests the following guidelines for safe operation and handling of IRAUDAMP5 Demo Board e Always wear safety glasses whenever operating Demo Board e Avoid personal contact with exposed metal surfaces when operating Demo Board Turn off Demo Board when placing or removing measurement probes www irf com IRAUDAMP5 REV 3 3 Internotionol Rectifier Table of Contents Introd ction ee GRE h Specification Siinai a Connection Setup uen dE ERR Test Pfoced te exer seen OR Mec Typical Performance Theory of Operation 18 20925 System Overview Selectable Dead 2 01 Protection Features E Thermal Considerations Click and Pop Noise Control Startup and Shutdown Sequencing Bus PUMPING Input Output Signal and Volume
4. MOTE CMUIE gt R117 47R 100uF 16 123 5401 International T 47k ISR Rectifier NMBTSSS1 Q107 MMBT5551 R132 47k B Fig 39 www irf com IRAUDAMP5 REV 3 3 Page 35 of 49 International Rectifier Class D Daughter Board REFERENCE DESIGN IRAUDAMPS Bill of Materials 5 2092 3 1_BOM Designator Footprint PartType Quantity PARTNO VENDER C1 C2 C21 C22 C23 C24 805 InF 250V COG 6 445 2325 1 ND DIGI KEY C3 C4 TAN A 10uF 16V Tan 2 495 2236 1 ND DIGI KEY C5 C6 TAN B 10uF 16V Tan 2 399 3706 1 ND DIGI KEY C9 C28 C29 0805 47nF 50V X7R 3 PCC1836CT ND DIGI KEY C10 C11 TAN B 10uF 16V 2 399 3706 1 ND DIGI KEY C12 C16 C18 C19 TAN B 3 3uF 16V X7R 4 445 1432 1 ND DIGI KEY C13 C17 0805 0 1uF 100V X7R 2 399 3486 1 ND DIGI KEY C14 C15 C32 C33 1206 0 1uF 100V X7R 3 PCC2239CT ND DIGI KEY C20 0805 open 1 open C30 C31 0805 10 50 X7R 2 PCC103BNCT ND DIGI KEY 01 02 SOD 323 19 5 7 2 BAVI9WS FDICT ND DIGI KEY 03 04 500 323 1N4148WS 7 F 2 1N4148WS FDICT ND DIGI KEY D5 D6 SMA MURA120T3G 2 MURA120T3GOSCT ND DIGI KEY D7 SMA ES1D 1 ESiDFSCT ND DIGI KEY DS1 DS2 805 LTST C171TBKT 2 160 1645 1 ND DIGI KEY EISA31 EISA3
5. R105 2 805 IOR PIOACT ND Digikey 45 RI3 RI4 2 805 3 3K 1 P3 3KZCT ND Digikey 46 RIS 2 805 22k P22KACT ND Digikey R106 R121 R122 R130 R131 R132 47 R133 R137 R139 R145 R146 16 805 47k P47KACT ND Digikey R147 R149 R150 R151 48 R152 805 Digikey 49 R55 R56 2 805 0 0 Ohms Digikey 50 R39 R40 2 805 470R P470ACT ND Digikey 51 R21 R22 R23 R24 4 open 52 R120 1206 1008 PIO0ECT ND Digikey 53 R29P R30P 2 open 54 R32 2 2512 47 1 PT47KAFCT ND Digikey 55 R33 R34 2 1206 IK PLOKECT ND Digikey www irf com IRAUDAMP5 REV 3 3 Page 38 of 49 International ier REFERENCE DESIG Rectif R109 R118 R119 R123 4 805 1K P1 0KACT ND Digikey 57 R47 R48 2 2512 10 1W PTIOXCT Digikey 58 R49 R50 2 1206 22k P22KECT ND Digikey 59 R68 R69 2 AXIAL 0 3 OPEN Digikey 60 R101 R102 R103 R104 4 2512 47R 1W PT47XCT ND Digikey 61 R107 R138 2 805 4 7K P4 7KACT ND Digikey 62 R108 V_Control CT2265 CT2265 ND Digikey R111 R124 R125 R134 R140 R143 63 R144 R148 8 805 10K PIOKACT ND Digikey 64 R112 805 820R P820ACT ND Digikey 65 R113 POTs 5K POT 3362H 502LF ND Digikey 66 R127 R128 R129 3 1206 6 8k P6 8KECT ND Digikey 67 R135 1 805 82k P82KACT ND Digikey 68 R136 R142 2 805 68k P68KACT ND Dig
6. by 5 R9 108 x SIMUL 5 VD VA 5V v 33108065 DGRD 45V 0 SUK RN SCLK AOUTR Level OUT 2 47R zs Control Volume lt SDATAOAGNDR RII R4 p MUTE AINR gt 47R cu 100R Je Audio in Fig 26 Digital volume Control www irf com IRAUDAMP5 REV 3 3 Page 23 of 49 Internotionol Rectifier REFERENCE DESIGN Bridged Output The IRAUDAMPS is not intended for a bridge tied load or BTL configuration However BTL operation can be achieved by feeding out of phase audio input signals to the two input channels as shown in the figure 27 below In BTL operation minimum load impedance is 8 Ohms and rated power is 240W non clipping The installed clamping diodes 05 D8 are required for BTL operation since reactive energy flowing from one output to the other during clipping can force the output voltage beyond the voltage supply rails if not clamped R31 R33 Ta Y VAA _ c B 21 23 4 gt VB oY L 18520925 ee z gt HO 4 5 5 IRF6645 3B ids i Filter INPUT
7. E 808 100 200 500 1k 10k 20k 40k Bus Pumping Fig24 Since the IRAUDAMPS is a half bridge configuration bus pumping does occur Under normal operation during the first half of the cycle energy flows from one supply through the load and into the other supply thus causing a voltage imbalance by pumping up the bus voltage of the receiving power supply In the second half of the cycle this condition is reversed resulting in bus pumping of the other supply These conditions worsen bus pumping 1 Lower frequencies bus pumping duration is longer per half cycle 2 Higher power output voltage and or lower load impedance more energy transfers between supplies www irf com IRAUDAMP5 REV 3 3 Page 21 of 49 International Rectifier 3 Smaller bus capacitors the same energy will cause a larger voltage increase The IRAUDAMPS has protection features that will shut down the switching operation if the bus voltage becomes too high gt 40V or too low lt 20V One of the easiest countermeasures is to drive both of the channels in a stereo configuration out of phase so that one channel consumes the energy flow from the other and does not return it to the power supply Bus voltage detection is only done on the B supply as the effect of the bus pumping on the supplies is assumed to be symmetrical in amplitude although opposite in phase with the B supply 10 0 V Input Signal A proper input
8. Description 1 IInsulator Thermalfilm 2 2 Shoulder Washer 3 Flat Washer 4 ceir 4 4 40 2 Hex Nut Pan Head Screw l 6 Lockwasher No 4 7 Heatsink B III IIIZ I 7 8 PCB 3 4 6 4 q 5 Item Description 1 IInsulator Thermalfilm 2 L 2 Shoulder Washer 3 4 5 1 4 4 40 UNC 2B Hex Nut Pan Head Screw 6 Lockwasher No 4 7 Heatsink B gt 3 8 PCB lt 3 a 4 Fig 40 www irf com IRAUDAMP5 REV 3 3 Page 40 of 49 International Rectifier IRAUDAMPS PCB Specifications Core 0 062mil Top Layer gt Bottom Layer Figure 41 Motherboard and Daughter board Layer Stack Daughter board Material FR4 UL 125 C Layer Stack 2 Layers 1 oz Cu each Through hole plated Dimensions 3 125 x 1 52 x 0 062 Solder Mask LPI Solder mask SMOBC on Top and Bottom Layers Plating Open copper solder finish Silkscreen On Top and Bottom Layers Motherboard Material FR4 UL 125 C Layer Stack 2 Layers 1 oz Cu Dimensions 5 2 x 5 8 x 0 062 Solder Mask LPI Solder mask SMOBC on Top and Bottom Layers Plating Open copper solder finish Silkscreen On Top and Bottom Layers www irf com IRAUDAMP5 REV 3 3 Page 41 of 49 International TER Rectifier IRAUDAMPS PCB layers Class D Daughter board 3492 mil 513 44 11 39 Figure 42
9. Fig 36 www irf com IRAUDAMP5 REV 3 3 Page 32 of 49 Internotionol REFERENCE DESIGN TOR Rectifier is themully connected with Q3 Class D Daughter Board IRS2092S Module Schematic SCH DB 2092 v3 1 35V Bus cu 35V Bos R7 VAA 0 10 100 Audio Gnd 1 5 DFETI GNDI its IRF GAS 0 1uF 100V m CHI ES T 2 ze 9 13 265683 A26568 ND D4 15 50 14 2 5 12 16 A26570 ND CHI Output to LPFI vss VREF d 35V Bus B 5 18520925 35V Rp2 is themully connected with 05 Rp2 100K 100C MMBTS401 Q 35V Bus 2 5551 2 R8 Ca B 0 1uF 100V Q 10 IRF6645 cis 10 vec 22uF ap 0 1uF 100V 11 sD R53 108 12 1 la 1 A26568 ND InF 250V R27 2 Audio Gnd 2 1 d 1 E i Ds sp 28 5 5 10uF ro A26570 ND CH2 Output to 16 35V Bus RIO 1 K 10nF 50V 1 33uF OCSET IRS20928
10. Sync Oscillator 350kHz THD N Ratio vs Output Power for Different Switching Frequency Lock Synchronization Conditions Fig 34 www irf com IRAUDAMP5 REV 3 3 Page 30 of 49 International Rectifier Class D Daughter Board IRS2092S Module CH1 Schematic Rpl is thenmally connected with Q3 Rpl VAA C32 0 1uF 100V GNDI C14 0 1uF 100V 1 4 2 5 CHI 3 6 CHIO DA A26568 ND 4 9 13 4 10 14 4 15 12 16 A26570 ND CHI Output to LPFI 1 4 35V Bus OCSET International Rectifier www irf com IRAUDAMP5 REV 3 3 Page 31 of 49 International Rectifier Class D Daughter Board IRS2092S Module CH2 Schematic Rp2 is thermally connected with Q5 R35 Rp2 100K 5401 Q OTP2 5551 33 0 1uF 100V CS sp R53 lt 0 1uF 100V 1 IN2 JB 4 1 5 B 4 2 6 4 8 A26570 ND CH2 Output to LPF2 35V Bis International Rectifier 35V Bus
11. With S3 set to INT the two settings H and L will modify the internal clock frequency by about www irf com IRAUDAMP5 REV 3 3 Page 27 of 49 International REFERENCE DESIGN TER Rectifier 20 kHz to 40 kHz either higher H or lower L The actual internal frequency is set by potentiometer R113 INT FREQ 3 Switch S3 is an oscillator selector This three position switch is selectable for internal self oscillator middle position or either internal INT or external EXT clock synchronization R109 1 cua 10 50 e 1200 50V 45V inaiag eno Ma 50V 100x 1 R112 U3 82 SR 1 vec 33 1 qj py SE Rm 2A 5K POT Z 100pF 50V SW 3WAY_A B S3B SW sy aw 4A e GND 4Y aS 74 14 gone sov CLK 5 R118 A Ik NORMAL R119 4 Ik PROTECTION sure LED Switches and Sync frequencies Fig 31 Switching Frequency Lock Synchronization Feature For single channel operation the use of the self oscillating switching scheme will yield the best audio performance The self oscillating frequency however changes with the duty ratio This varying frequency can interfere with AM radio broadcasts where a constant switching frequency with its harmonics sh
12. similar sequence as startup www irf com IRAUDAMP5 REV 3 3 Page 20 of 49 International TER Rectifier Power Supplies The IRAUDAMPS has all the necessary housekeeping power supplies onboard and only requires a pair of symmetric power supplies ranging from 25V to 35V B GND B for operation The internally generated housekeeping power supplies include a 5V supply for analog signal processing preamp etc while a 12V supply VCC referenced to B is included to supply the low and high side Class D gate driver stages For the externally applied power a regulated power supply is preferable for performance measurements but is not always necessary The bus capacitors C31 and C32 on the motherboard along with high frequency bypass caps C14 C15 C32 and C33 on the daughter board address the high frequency ripple current that results from switching action In designs involving unregulated power supplies the designer should place a set of external bus capacitors having enough capacitance to handle the audio ripple current Overall regulation and output voltage ripple for the power supply design are not critical when using the IRAUDAMP5 Class D amplifier as the power supply rejection ratio PSRR of the IRAUDAMPS is excellent as shown on Figure 23 below TT F 1 LCT TL E
13. 2 m2 5 100uF 16V 565 1037 ND Digikey 22 D103 D104 D105 D106 D107 5 SOD 123 INA4148W 7 F 1N4148W FDICT ND Digikey 23 05 06 D7 D8 4 SMA MURA120T3G MURA120T3GOSCT ND Digikey 24 D101 D102 2 SOD 123 MA2YD2300 MA2YD2300LCT ND Digikey 25 1 Heat S6inl HEAT SINK 294 1086 ND Digikey 26 JIA JIB 2 CONEISA 31 CON EISA31 A32934 ND Digikey 27 2 CON POWER CON POWER A32935 ND Digikey 28 33 44 2 MKDS5 2 9 5 277 1022 277 1271 ND or 651 1714971 Digikey Mouser 29 15 16 2 Blue RCA RCJ 055 CP 1422 ND Digikey 30 X 1 J HEADER3 277 1272 277 1272 ND 651 1714984 31 J8 BNC RA CON A32248 ND Digikey 3 EDI567 ED1567 ED1567 Digikey Inductors Sagami 7G17A Sagami 7G17A on 33 LLZ z Inductor 1 1D17A 220M 1D17A 220M Component s Inc 34 NORMAL 1 Led rb2 5 404 1106 ND 160 1143 ND Digikey 35 Pl DIP 6 PVT412 PVT412PBF ND Digikey 36 PROTECTION 1 Led rb2 5 404 1109 ND 160 1140 ND Digikey 37 0101 1 SOT89 FX941 FCX491CT ND Digikey 38 0102 0104 0106 Q111 4 SOT23 BCE 5401 7 MMBT5401 FDICT ND Digikey 39 9105 0107 0108 0109 7 SOT23 BCE 5551 MMBT5551 FDICT ND Digikey 40 R2 R57 R58 R110 R126 6 805 100K Digikey 41 R3 RA 3 805 TOOR PIO0ACT ND Digikey 42 R5 R6 2 1206 4 7R P4 7ECT ND Digikey 43 4 10 R11 R27 R28 R115 R116 9 805 47R P47ACT ND Digikey 44
14. Chassis Gad 47R 74AHC1G04 Power Supply Heat Snk 10uF 50V www irf com 201 R101 4 R102 47k 1 T 150 500V 5 Power Supply 04 MC78M0S 7102 103 0 47uF 400V ___026 0 1uF 400V 5V Power Supply R104 IN 47 ZM4732ADICT 47R 1W 10uF 50 AAA 1W Vin Vout B gt IW 2 Pv ZMA732ADICT MA2YD2300 C101 C102 10uF 50V Fig 38 IRAUDAMP5 REV 3 3 Page 34 of 49 47R IW C103 T 100 50V us 79 05 C104 10uF 50V 0102 Y MA2YD2300 International REFERENCE DESIGN Rectifier Class D Mother Board Clock and House Keeping Schematic R143 SW 3WAY_AB m 15V Qill 40106 5401 0105 gt 1054148 100pF 50 48 100uF 16 50 L S RIIO 0109 5551 EN MES Trip and restart SW3WAY 100 50 115 10uF zo j 82V C114 R135 52 82k 7 50 0108 e 5V J8 F RIIS BNC A24497 EXT CLK R119 5551 Ik 5551 2 DC protection PROTECTION
15. PCB Layout Top Side Solder Mask and Silkscreen www irf com IRAUDAMP5 REV 3 3 Page 42 of 49 International TOR Rectifier REFERENCE DESIGN 9ili72598 aa SOOS Figure 43 Layout Bottom Layer Pads and bottom silk screen www irf com IRAUDAMP5 REV 3 3 Page 43 of 49 International Rectifier PCB Layout Motherboard 0 0 0 o c O 00 010 010 Fig 44 Layer www irf com IRAUDAMP5 REV 3 3 Page 44 of 49 International Rectifier Fig 45 silk screen www irf com IRAUDAMP5 REV 3 3 Page 45 of 49 International TER Rectifier Internotionol Rectifier E eors 41 6105 5101 L se C o 5 gt na CL ay Poo LP Lx TM J _ SL 9 EX pm Zl E3 cum arg i INE 0 sua LI arm BL Lu mH Fig 47 www irf com IRAUDAMP5 REV 3 3 Page 47 of 49 Internotionol Rectifier E eors oria O 41 6105 L ses 1010 2015 l Bi
16. a forward voltage drop of 0 6V at D1 the minimum threshold which can be set for the high side is 0 6V across the drain to source For IRAUDAMPS the high side over current trip level is set to 0 6V across the high side MOSFET For the IRF6645 MOSFETs with a nominal Rps on of 28 mOhms at 25 C this results in 21A maximum trip level Since the Rps on is a function of temperature the trip level is reduced to 14A at 100 C For a complete description of calculating and designing the over current trip limits please refer to the IRS2092S datasheet Positive and Negative Side of Short Circuit versus switching output shut down The plots below show the speed that the IRS2092S responds to a short circuit condition Notice that the envelope behind the sine wave output is actually the switching frequency ripple Bus pumping naturally affects this topology www irf com IRAUDAMP5 REV 3 3 Page 14 of 49 International IER Rectifier vs pin Load current iL MI Load current m WU NM Load current Load current Load current External Faults OVP UVP and DCP are considered external faults In the event that any external fault condition 15 detected the shutdown circuit will disable the output for about three seconds during which time the orange AUDAMPS Protection LED will turn on If the fault condition has not cleared the protection circuit will hiccup until the fault is re
17. a small peak at the corner frequency of the output LC low pass filter The IRAUDAMPS is stable with capacitive loading however it should be noted that the frequency response degrades with heavy capacitive loading of more than 0 1pF Gain Setting Volume Control The IRAUDAMPS has an internal volume control potentiometer R108 labeled VOLUME Fig 26 for gain adjustment Gain settings for both channels are tracked and controlled by the volume control IC U 2 setting the gain from the microcontroller IC U 1 The maximum volume setting clockwise rotation corresponds to a total gain of 37 9dB 78 8V V The total gain is a product of the power stage gain which is constant 23 2dB and the input stage gain that is directly controlled by the volume adjustment The volume range is about 100dB with minimum volume setting to mute the system with an overall gain of less than 60dB For best performance in testing the internal volume control should be set to a gain of 21 9 V V such that 1 Vrms input will result in rated output power 120W into 40 allowing for a gt 11dB overdrive 5V C109 e 45 gt Keir Audio 7 74 16V z 4 7uF 16V 8 1 R3 E VSS VDD ZCEN AINL gt 8 7 MR __ 100R gt lt e __ cs CS AGNDL eae R8 47R 100K un 6 5 SDATAI AOUTL Level OUT 1 RI 9
18. and low side MOSFETs are internal to the 18520925 and the trip levels for both MOSFETs can be set independently In this design the dead time can be selected for optimized performance by minimizing dead time while preventing shoot through As a result there is no gate timing adjustment on the board Selectable dead time through the DT pin voltage is an easy and reliable function which requires only two external resistors R11 and R9 as shown on Figl11 below www irf com IRAUDAMP5 REV 3 3 Page 10 of 49 International Rectifier B A L VAA CSH 8 2 GND VB H3 34 IN HO AUDIO_INPUT 0 COMP VS ee Y 1 5 3 5 0 vcc H2 CH1 1 Lon 1 RI9 12 T DT S m RS 5 IRS2092S System level View of Class D Controller and Gate Driver 16520925 Fig 11 Selectable Dead Time The dead time of the IRS2092S is based on the voltage applied to the DT pin Fig 12 An internal comparator determines the programmed dead time by comparing the voltage at the DT pin with internal reference voltages An internal resistive voltage divider based on different ratios of VCC negates the need for a precise reference voltage and sets threshold voltages for each of the four programmable setti
19. i 1 Modulator vs Eu and enin CH1 V Shift level A GND VCC Integrator LO 4 fT B Li J IRF6645 x gt Y Vv B y x R32 R34 COM S F B C22 1 ie 1 T m 4 t IRF6645 a m LP Filter Modulator vs b and Ac CH2 GND Shift level vec Qs B Integrator E LO 1 f gt o Y COM Bridged configuration Fig 27 Output Filter Design Preamplifier and Performance The audio performance IRAUDAMPS depends on a number of different factors The section entitled Typical Performance presents performance measurements based on the overall system including the preamp and output filter While the preamp and output filter are not part of the Class D power stage they have a significant effect on the overall performance Output filter Since the output filter is not included in the control loop of the IRAUDAMPS the reference design cannot compensate for performance deterioration due to the output filter Therefore it is important to understand what characteristics are preferable when designing the output filter www irf com IRAUDAMP5 REV 3 3 Page 24 of 49 international TOR Rectifier 1 The DC resistance of the inductor should be minimized to 20 mOhms or less 2 The linearity of the output inductor and capacitor should be high with respect to load current and voltage Preamplifier Fig 28 The preamp allows
20. 1 1 A26568 ND DIGI KEY J1B CON EISA31 CON EISA31 1 A26568 ND DIGI KEY POWER CON_POWER 1 A26570 ND DIGI KEY J2B CON_POWER CON_POWER 1 A26570 ND DIGI KEY Q1 SOT23 BCE 5551 1 MMBT5551FSCT ND DIGI KEY Q2 Q7 SOT23 BCE MMBT5401 7 2 MMBT5401 FDICT ND DIGI KEY www irf com IRAUDAMP5 REV 3 3 Page 36 of 49 International Rectifier D FET1 D FET2 D FET3 D FET4 Direct Fet SJ IRF6645 4 IRF6645 IR RI R2 0805 100R 2 P100ACT ND DIGI KEY R3 R4 R9 R10 R15 R16 R27 R28 R30 R32 R8 0805 10R 11 P10ACT ND DIGI KEY R5 R6 0805 3 3K 2 P3 3KACT ND DIGI KEY R7 1206 10R 1 P10ECT ND DIGI KEY R11 R31 R33 R34 R35 R47 0805 100K 2 100 DIGI KEY R12 R45 0805 47K 2 P4 7KACT ND DIGI KEY R13 R14 R19 R20 0805 82K 2 P8 2KACT ND DIGI KEY R24 R48 0805 1K 2 P1 0KACT ND DIGI KEY R7 R18 805 L2k RHM1 2KARCT ND DIGI KEY R21 R22 0805 1k 2 P1 0KACT ND DIGI KEY R23 R26 0805 476 2 P4 7ACT ND DIGI KEY R25 R29 R36 R41 R42 0805 10K 5 DIGI KEY R37 R38 0805 3 P1 0ACT ND DIGI KEY R39 R40 0805 33K 3 RHN33KARCT ND DIGI KEY R43 R44 0805 0 3 RHM0 0ARCT ND DIGI KEY R49 R50 R51 R52 1206 open 3 open Rp2 805 100 3 594 2381 675 21007 MOUSER P1 P2 ST 32 3mm SQ 1k ST32ETB102TR ND DIGI KEY R46 R53 805 3 01k RHM3 01KCCT ND DIGI KEY U1 U2 SOIC16 IR Driver 3 IRS2092S IR www i
21. A weighted AES 17 filter Distortion 0 005 THD N 60W 40 Efficiency 96 120W 4Q single channel driven Class D stage Multiple Protection Features Over current protection OCP high side and low side Over voltage protection OVP Under voltage protection UVP high side and low side DC protection DCP Over temperature protection OTP PWM Modulator Self oscillating half bridge topology with optional clock synchronization www irf com IRAUDAMP5 REV 3 3 Page 2 of 49 Internotionol Rectifier Specifications General Test Conditions unless otherwise noted Supply Voltage Load Impedance Self Oscillating Frequency Gain Setting Electrical Data IR Devices Used REFERENCE DESIGN Notes Conditions 3 5V 8 40 400kHz No input signal Adjustable 26dB 1Vrms input yields rated power Typical Notes Conditions IRS2092S Audio Controller and Gate Driver IRF6645 DirectFET MOSFETs Modulator Power Supply Range Output Power CH1 2 1 THD N Output Power CH1 2 10 THD N Rated Load Impedance Standby Supply Current Total Idle Power Consumption Channel Efficiency Audio Performance THD N 1W THD N 10 THD N 60W THD N 100W Dynamic Range Residual Noise 22Hz 20kHzAES17 Damping Factor Channel Separation Frequency Response 20Hz 20kHz 20Hz 35kHz Thermal Performance Idling 2ch x 15W 1 8 rated power 2ch x 120W Rated power Physical Specifications Dimensions www i
22. E International Rectifier www irf com IRAUDAMP5 REV 3 3 Page 33 of 49 International TOR Rectifier Control Volume 5V REFERENCE DESIGN Class D Mother Board Control Volume and Power Supplies Schematic C19 H 2 2uF 16V R27 47R 74AHCIG04 Cs 10uF 50V Feedback R31 Audio in C109 C107 4 7uF 16V 2 VDD 45 lt 4 7uF 16V R7 47 AGNDL SDATA R8 47R SDATAI C108 10nF 50V SIMUL R9 10R VD VA Al 5V tc wv 3310S06S SCLK RIO 10uF 50V DGRD 47R 4JR SCLK AOUTR R6 International TOR Rectifier VCCUVP R107 1sv 4 7K R106 47K R105 U6 MC78MI2 5401 Vout cc SDATAO AGNDR MUTE CS3310 AINR R2 22uF 16V R28 m 10uF 50V C6 10uF 50V n IX R55 0 0 AV 1 CHI IN 150pF 500V joe 5 IRS20928 MODULE JB m m 7 10 ee 1 P R56 Soo vcc CH2 Feedback R32 R34 25 0 1uF 400V Trace under J7 C31 gt 8 21632 1000uF 50V 1000uF 50V
23. IRAUDAMPS Class D audio power amplifier features self oscillating type PWM modulator for the lowest component count highest performance and robust design This topology represents an analog version of a second order sigma delta modulation having a Class D switching stage inside the loop The benefit of the sigma delta modulation in comparison to the carrier signal based modulation is that all the error in the audible frequency range is shifted to the inaudible upper frequency range by nature of its operation Also sigma delta modulation allows a designer to apply a sufficient amount of correction The self oscillating frequency Fig 30 is determined by the total delay time inside the control loop of the system The delay of the logic circuits the IRS2092S gate driver propagation delay the IRF6645 switching speed the time constant of front end integrator e g R13 R33 R31 R21 C17 C21 C23 and for and variations in the supply voltages are critical factors of the self oscillating frequency Under nominal conditions the switching frequency is around 400kHz with no audio input signal and a 35V supply www irf com IRAUDAMP5 REV 3 3 Page 26 of 49 international TOR Rectifier Adjustments of Self Oscillating Frequency The PWM switching frequency in this type of self oscillating switching scheme greatly impacts the audio performance both in absolute frequency and frequency relative to the other channels In absol
24. d Internal faults are only relevant to the particular channel while external faults affect the whole board For internal faults only the offending channel is stopped The channel will hiccup until the fault is cleared For external faults the whole board is stopped using the shutdown sequencing described earlier In this case the system will also hiccup until the fault is cleared at which time it will restart according to the startup sequencing described earlier R43 DI 19 e R32 io IRF6645 Filter csp U R30 158 IRF6645 R19 RI8 5 1V 4 4 OCREF OCSET COM Trip i i Green Yellow RESET UVP en DCP LEDs next channel e a Functional Block Diagram of Protection Circuit Implementation Fig 13 www irf com IRAUDAMP5 REV 3 3 Page 12 of 49 Internotionol Rectifier Internal Faults OCP and OTP are considered internal faults which will only shutdown the particular channel by pulling low the relevant CSD pin The channel will shutdown for about one half a second and will hiccup until the fault is cleared Over Temperature Protection OTP Fig 14 separate resistor is placed in close proximity to the high side IRF6645 DirectFET MOSEET for each of the amplifier channels If
25. e negative supply should be 100mA 10mA at 35 14 Push S1 switch Trip and Reset push button to restart the sequence of LEDs indicators which should be the same as noted above in steps 6 9 SORES ON A Ge IS Audio Tests 15 Apply 1 V RMS at 1KHz from the Audio Signal Generator 16 Turn control volume up R108 clock wise to obtain an output reading of 100Watts for all subsequent tests as shown on the Audio Precision graphs below where measurements are across J3 and J2 with an AES 17 Filter Typical Performance The tests below were performed under the following conditions B supply 35V load impedance 4Q resistive load 1kHz audio signal Self oscillator 2 400kHz and internal volume control set to give required output with 1 Vrms input signal with AES 17 Filter unless otherwise noted www irf com IRAUDAMP5 REV 3 3 Page 5 of 49 International Rectifier THD versus Power 10 5 2 1 0 5 0 2 96 0 1 0 05 0 02 0 01 0 005 0 002 0 001 100m 200m 500m 1 2 5 10 20 50 100 200 Blue CH1 4 Ohm Red CH2 4 Ohm Figure 18 To
26. filter The modulated signal is created by the fluctuations of the analog input signal at R13 that shifts the average value of this quadratic waveform through the gain relationship between R13 and R31 R33 so that the duty cycle varies according to the instantaneous signal level of the analog input signal at R13 R33 and C17 act to immunize the rectangular waveform from possible narrow noise spikes that may be created by parasitic impedances on the power output stage IRS2092S input integrator then processes the signal from the summing node to create the required triangle wave amplitude at the COMP output The triangle wave then is converted to Pulse Width Modulation or PWM signals that are internally level shifted Down and Up to the negative and positive supply rails The level shifted PWM signals are called LO for low output and HO for high output and have opposite polarity A programmable amount of dead time is added between the gate signals to avoid cross conduction between the power MOSFETs The IRS2092S drives two IRF6645 DirectFET MOSFETs in the power stage to provide the amplified PWM waveform The amplified analog output is reconstructed by demodulating the powered PWM at the switch node called VS Show as VS on the schematic This is done by means of the LC low pass filter LPF formed by L1 and C23A which filters out the Class D switching carrier signal leaving the audio powered output at the speaker load A single stage output filte
27. h a nominal Rps on of 28mOhms at 25 C this results in 23A maximum trip level Since the Rps on is a function of temperature the trip level is reduced to 15 at 100 C www irf com IRAUDAMP5 REV 3 3 Page 13 of 49 International Rectifier R43 Di fo 19 VB 5 x 24 Q3 R32 He ga IRF6645 LP Filter CSD RE mmo VCC PN LO R30 IRF6645 R19 R18 A OCREF OCSET COM Simplified Functional Block Diagram of High Side and Low Side Current Sensing CH1 Fig 15 High Side Current Sensing Fig15 The high side MOSFET is protected from an overload condition and will shutdown the switching operation if the load current exceeds a preset trip level High side over current sensing monitors detect an overload condition by measuring the high side MOSFET s drain to source voltage Vps through the CSH and VS pins The CSH pin detects the drain voltage with reference to the VS pin which is the source of the high side MOSFET In contrast to the low side current sensing the threshold of CSH pin to engage OC protection is internally fixed at 1 2V An external resistive divider R43 R25 and R41 for Chl can be used to program a higher threshold An additional external reverse blocking diode D1 for CH1 is required to block high voltage feeding into the CSH pin during low side conduction By subtracting
28. iciency vs Output Power Single Channel Driven supply 35V IkHz Audio Signal Fig20 www irf com IRAUDAMP5 REV 3 3 Page 17 of 49 Internationa Rectifier Thermal Considerations The daughter board design can handle one eighth of the continuous rated power which is generally considered to be a normal operating condition for safety standards Without the addition of a heatsink or forced air cooling the daughter board cannot handle fully rated continuous power A thermal image of the daughter board is as shown in Fig 21 below Thermal Distribution Thermal image of Daughter Voard Two Channel x 1 8th Rated Power 15W in Operation TC 54 C at Steady State B supply 35V 4O Load 1kHz audio signal Temp ambient 25 C Fig 21 Click and POP noise One of the most important aspects of any audio amplifier is the startup and shutdown procedures Typically transients occurring during these intervals can result in audible pop or click noise from the output speaker Traditionally these transients have been kept away from the speaker through the use of a series relay that connects the speaker to the audio amplifier only after the startup transients have passed and disconnects the speaker prior to shutting down the amplifier Thanks to the click and pop elimination function in the IRS2092S IRAUDAMPS does not use any series relay to disconnect the speaker from the audible transient noise www
29. ifted away from the AM carrier frequency is preferred In addition to AM broadcasts multiple channels can also reduce audio performance at low power and can lead to increased residual noise Clock frequency locking synchronization can address these unwanted characteristics Please note that the switching frequency lock synchronization feature is not possible for all frequencies and duty ratios and operates within a limited frequency and duty ratio range around the self oscillating frequency Figure 32 below www irf com IRAUDAMP5 REV 3 3 Page 28 of 49 International Rectifier 600 Suggested clock frequency Locking ra for maximum locking range a Self oscillating frequency Operating Frequency kHz A 10 20 30 40 50 60 70 80 90 Duty Cycle Typical Lock Frequency Range vs PWM Duty Ratio Self oscillating frequency set to 400 kHz with no input Fig 32 The output power range for which frequency locking is successful depends on what the locking frequency is with respect to the self oscillating frequency As illustrated in Figure 33 the locking frequency 1 lowered from 450kHz to 400kHz to 350kHz and then 300kHz as the output power range where locking is achieved is extended Once locking is lost however the audio performance degrades but the increase in THD seems inde
30. ikey 69 51 Switch SW PB P8010S ND Digikey 70 S2 SW EG1908 ND SW_H L EG1908 ND Digikey 71 S3 SW EG1944 ND SW 3WAY EG1944 ND Digikey 72 01 U2 2 73 U3 U4 2 SOT25 74AHC1G04 296 1089 1 ND Digikey 74 07 08 2 5 75 U9 010 2 5 8 76 Ul 1 SOIC16 CS3310 73C8016 or 72J5420 Newark 77 02 3310S06S 3310 IR01 i Tachyonix 78 U3 74 14 296 1194 1 ND Digikey 79 U4 TO 220 MC78M05CTG MC78M05CTGOS ND Digikey 80 Us TO 220 LM79MO0SCT LM79M0SCT ND Digikey 81 U 6 TO 220 LM78MI2CT LM78MI2CT ND Digikey 82 Z1 72 2103 3 SOD 123 15V BZT52C15 FDICT ND Digikey 83 7101 Z102 2 SMA 47V 1SMA5917BT3GOSCT ND Digikey 84 Z104 SOD 123 24V BZT52C24 FDICT ND Digikey 85 Z105 SOD 123 39V BZT52C39 13 FDICT ND Digikey 86 7106 2107 2 SOD 123 18V BZT52C18 FDICT ND Digikey 87 2108 2109 2 SOD 123 8 2V BZT52C8V2 FDICT ND Digikey 88 Volume Knob Blue Knob MC21060 10M7578 Newark 89 Thermalloy TO 220 mounting kit with screw 3 Kit screw ROHS AAVID 4880G 82K6096 Newark 90 1 2 Standoffs 4 40 5 Standoff 8401K ND Digikey 91 4 40 Nut 5 100 per bag H724 ND Digikey 92 No 4 Lock Washer 5 100 per bag H729 ND Digikey Tachyonix Corporation 14 Gonaka Jimokuji Jimokuji cho Ama gun Aichi JAPAN 490 1111 http www tachyonix co jp info tachyonix co jp www irf com IRAUDAMP5 REV 3 3 Page 39 of 49 International Rectifier IRAUDAMPS Hardware Voltage regulator mounting 5 Item
31. irf com IRAUDAMP5 REV 3 3 Page 18 of 49 International REFERENCE DESIGN Rectifier Click Noise Reduction Circuit Solid State Shunt IRS2092S controller is relatively quiet with respect to class AB but for additional click or POP noise reduction you may add a shunt circuit that further attenuates click or pop transients during turn on sequencing The circuit is not populated on the present demo board for implementation details please refer to the IRAUDAMP4 user s manual at http www irf com technical info refdesigns audiokits html Startup and Shutdown Sequencing Fig 22 The IRAUDAMPS sequencing is achieved through the charging and discharging of the CStart capacitor C117 Along with the charging and discharging of the CSD voltage C10 on daughter board for of IRS2092S this is all that is required for complete sequencing The startup and shutdown timing diagrams are show in Figure 22A below CStart Ref2 CStart A CStart CStart Ref2 eM art Re CSD 2 3VDD CStart External trip CHx O SP s gt gt Audio MUTE Class D shutdown Class D startup Music shutdown Music startup Click Noise Reduction Sequencing at Trip and Reset Fig 22 For startup sequencing the control power supplies start up at different intervals depending on the B supplies As the B supplies reach 5 volts and 5 v
32. moved Once the fault is cleared the green Normal LED will turn on There 15 manual reset option Over Voltage Protection OVP Fig 18 OVP will shut down the amplifier if the bus voltage between GND and B exceeds 40 The threshold is determined by the voltage sum of the Zener diode 7 105 R140 and of 0109 As a result it protects the board from hazardous bus pumping at very low audio signal frequencies by shutting down the amplifier OVP will automatically reset after three seconds Since the B and B supplies are assumed to be symmetrical bus pumping although asymmetrical in time www irf com IRAUDAMP5 REV 3 3 Page 15 of 49 international TOR Rectifier will pump the bus symmetrically in voltage level over a complete audio frequency cycle it is sufficient to sense only one of the two supply voltages for OVP It is therefore up to the user to ensure that the power supplies are symmetrical Under Voltage Protection UVP Fig18 UVP will shutdown the amplifier if the bus voltage between GND and B falls below 20V The threshold is determined by the voltage sum of the Zener diode Z107 R145 and Vgg of 0110 As with OVP UVP will automatically reset after three seconds and only one of the two supply voltages needs to be monitored Speaker DC Voltage Protection DCP Fig 19 DCP is provided to protect against DC current flowing into the speakers This abnormal condition is rare and is likely caused when the p
33. ngs Shown in the table below are component values for programmable dead times between 25 and 105 ns To avoid drift from the input bias current of the DT pin a bias current of greater than 0 SmA is suggested for the external resistor divider circuit Resistors with up to 5 tolerance can be used Selectable Dead Time Dead time mode Dead time R5 R13 DT voltage DTI 25ns 3 3k 8 2k 0 71 x Vec Default DT2 40ns 5 6k 4 7k 0 46 x DT3 65ns 8 2k 3 3k 0 29 x Vec DT4 105ns open lt 10k gets Default 2515 4018 T Dead time 651 10515 0 0 23 0 36 0 57 Vcc Fig 12 Dead time Settings vs Vor Voltage www irf com IRAUDAMP5 REV 3 3 Page 11 of 49 International Rectifier Over Current Protection OCP In the IRAUDAMPS the 520925 gate driver accomplishes OCP internally a feature discussed in greater detail in the Protection section Offset Null DC Offset IRAUDAMPS is designed such that no output offset nullification is required thanks to closed loop operation DC offsets are tested to be less than 20mV Protection The IRAUDAMPS has a number of protection circuits to safeguard the system and speaker as shown in the figure 13 below which fall into one of two categories internal faults and external faults distinguished by the manner in which a fault condition is treate
34. olts respectively the 5V control supplies for the analog input start charging Once B reaches 16V VCC charges Once reaches 20V the UVP is released and CSD and CStart C117 start charging The Class D amplifier is now operational but the preamp output remains muted until CStart reaches Ref2 At this point normal operation begins The entire process takes less than three seconds www irf com IRAUDAMP5 REV 3 3 Page 19 of 49 International REFERENCE DESIGN Rectifier For Shutdown Fig22B sequencing is initiated once UVP is activated As long as the supplies do not discharge too quickly the shutdown sequence can be completed before the IRS2092S trips UVP Once UVP is activated CSD and CStart are discharged at different rates In this case threshold Ref2 is reached first and the preamp audio output is muted It is then possible to shutdown the Class D stage CSD reaches two thirds VDD This process takes less than 200ms i CStart Ref2 CSD 2 3VDD c UVP 20V SP MUTE rp ARES I Audio MUTE A Class D shutdown Music shutdown Conceptual Shutdown Sequencing of Power Supplies and Audio Section Timing Fig22B For any external fault condition OVP UVP or DCP see Protection that does not lead to power supply shutdown the system will trip in a similar manner as described above Once the fault is cleared the system will reset
35. ower amplifier fails and one of the high side or low side IRF6645 DirectFET MOSFETs remain in the ON state DCP is activated if either of the outputs has more than 4V DC offset typical Under this fault condition it is normally required to shutdown the feeding power supplies Since these are external to the reference design board an isolated relay is provided for further systematic evaluation of DC voltage protection This condition is transmitted to the power supply controller through connector J9 whose pins are shorted during a fault condition www irf com IRAUDAMP5 REV 3 3 Page 16 of 49 International Rectifier B R125 10K R126 5401 ie e 105 51 R13 To DCP 47K 9 C DC protection DCP R13 R12 AK 68k 014 RA eme E From CH1 Output o E CH1O 47 5401 R121 CH20 29 R127 68k 68k Ae From CH2 Output B Fig 19 Efficiency Figs 20 demonstrate that IRAUDAMS is highly efficient due to two main factors a DirectFETs offer low Rps on and very low input capacitance and b The PWM operates as Pulse Density Modulation 100 0 90 0 80 0 70 0 60 0 50 0 40 0 4 Power Stage Efficiency 30 0 20 0 10 0 0 0 0 20 40 60 80 100 120 140 160 180 Output Power W Eff
36. p na Fig 48 Bottom Silkscreen www irf com IRAUDAMP5 REV 3 3 Page 48 of 49 International REFERENCE DESIGN Rectifier Revision changes descriptions Revision Changes description Date 3 0 Released 7 27 07 3 1 Schematic error marked on red pages 31 33 1 28 08 R25 and R29 was connected to CSH Fig 40 and Fig 41 updated 3 2 ROHS Compliant BOM updated 5 29 09 3 3 Deleted drawings author and e mail 10 21 09 3 4 BOM updated Ice Components as a second 10 28 09 vender of the inductor 3 5 Correct Deadtime setting graph Fig 12 05 03 11 International Rectifier WORLD HEADQUARTERS 233 Kansas St El Segundo California 90245 Tel 310 252 7105 Data and specifications subject to change without notice 7 27 2007 www irf com IRAUDAMPS5 REV Page 49 of 49 International Rectifier www irf com IRAUDAMP5 REV 3 3 Page 50 of 49
37. partial gain of the input signal and controls the volume in the IRAUDAMPS The preamp itself will add distortion and noise to the input signal resulting in a gain through the Class D output stage and appearing at the output Even a few micro volts of noise can add significantly to the output noise of the overall amplifier It is possible to evaluate the performance without the preamp and volume control by moving resistors R13 and R14 to R71 and R72 respectively This effectively bypasses the preamp and connects the RCA inputs directly to the Class D power stage input Improving the selection of preamp and or output filter components will improve the overall system performance approaching that of the stand alone Class D power stage In the Typical Performance section only limited data for the stand alone Class D power stage is given For example Fig 20 below shows the results for THD N vs Output Power are provided utilizing a range of different inductors By changing the inductor and repeating this test a designer can quickly evaluate a particular inductor www irf com IRAUDAMP5 REV 3 3 Page 25 of 49 International Rectifier I IRAUDAMPS can be used as output inductors evaluation tool 100 0 1 0 01 0 001 0 0001 100m 200m 500m 1 2 5 10 20 50 100 200 w Results of THD N vs Output Power with Different Output Inductors Fig 29 Self Oscillating PWM Modulator The
38. pendent from the clock frequency Therefore a 300 kHz clock frequency is recommended as shown on Fig 34 It 15 possible to improve the THD performance by increasing the corner frequency of the high pass filter HPF R17 and C15 for Ch1 Fig 33 that is used to inject the clock signal as shown in Figure 33 below This drop in THD however comes at the cost of reducing the locking range Resistor values of up to 100 kOhms and capacitor values down to 10 may be used www irf com IRAUDAMP5 REV 3 3 Page 29 of 49 International Rectifier In IRAUDAMPS this switching frequency lock synchronization feature Fig 31 and Fig 33 is achieved with either an internal or external clock input selectable through S3 If an internal INT clock is selected an internally generated clock signal is used adjusted by setting potentiometer R113 INT FREQ If external EXT clock signal is selected a 0 5V square wave 50 duty ratio logic signal must be applied to BNC connector J17 10 5 2 1 0 5 0 2 0 1 0 05 0 02 0 01 0 005 0 002 0 001 100m 200 500m 1 2 5 10 20 50 100 200 Red Self Oscillator 400kHz Pink CH1 Sync Oscillator 400kHz Blue CH1 Sync Oscillator 450kHz Cyan CH1
39. r can be used with switching www irf com IRAUDAMP5 REV 3 3 Page 9 of 49 International REFERENCE DESIGN Rectifier frequencies of 400 kHz and greater lower switching frequencies may require additional filter components VCC is referenced to B and provides the supply voltage to the LO gate driver D6 and C5 form a bootstrap supply that provides a floating voltage to the HO gate driver The VAA and VSS input supplies are derived from B and B via R52 and C18 and R50 and C12 respectively Thus a fully functional Class D PWM amplifier plus driver circuit is realized in an 5016 package with just a few small components R31 R33 fle R52 5 I e 18 VNAV DirectFet r OV lt 03 IRF6645 LP Filter OV Modulator and 1 Shift level C23 Q4 J IRF6645 Integrator 1 DirectFet 12 B R50 Simplified Block Diagram of IRAUDAMPS Class D Amplifier Fig 10 System overview IRS2092S Gate Driver The IRAUDAMPS uses IRS2092S a high voltage up to 200V high speed power MOSFET PWM generator and gate driver with internal dead time and protection functions specifically designed for Class D audio amplifier applications These functions include OCP and UVP Bi directional current protection for both the high side
40. rf com Self oscillating second order sigma delta modulation analog input 25V to 435V Bipolar power supply 120W 1kHz 170W 1kHz 8 40 Resistive load 100mA No input signal 7W No input signal 96 Single channel driven 120W Class D stage Before Class D Notes Conditions Demodulator Output 0 009 0 01 0 003 0 004 Single channel driven 0 003 0 005 0 008 0 010 101dB 101dB A weighted AES 17 filter Single channel operation 170uV 170uV Saelf oscillating 400kHz 2000 170 relative to 40 load 95dB 90dB 100Hz 85dB 80dB 2 75dB 65dB 10kHz me 198 1W 4Q 8Q Load Typical Notes Conditions 30 C No signal input T 25 C 279 Tc 54 C Continuous 25 67 80 At OTP shutdown 150 sec 106 259 5 8 L x 5 2 W IRAUDAMP5 REV 3 3 Page 3 of 49 International TOR Rectifier Note Class D Specifications are typical Before demodulator refers to audio performance measurements of the Class D output power stage only with preamp and output filter bypassed this means performance measured before the low pass filter Connection Setup Typical Test Setup Fig 2 Connector Description CH1 IN J6 Analog input for CH1 CH2 IN J5 Analog input for CH2 POWER J7 Positive and negative supply B B OUT J3 Output for CH1 CH2 OUT J4 Output for CH2 EXT CLK J8 External clock sync DCP OUT J9 DC protection relay o
41. rf com IRAUDAMP5 REV 3 3 Page 37 of 49 International Rectifier Class D Motherboard IRAUDAMP5 MOTHERBOARD BILL OF MATERIAL NO Designator Footprint Part Type Part No Vender 1 T C101 C102 C103 C104 C105 19 RB2 5 10uF 50V 565 1106 ND Digikey 2 C2 C3 2 RB2 5 22uF 50V 565 1103 ND Digikey 3 C7 C8 C9 CIO 4 open 4 C12 C14 4 open 5 CI5 C16 2 805 33pF 478 1281 1 ND Digikey 6 C17 C18 2 AXIALO 19R 150 500 338 2598 ND Digikey 7 C19 C20 2 1206 22uF 16V PCCIO3ICT ND Digikey 8 C119 1 1206 0 1uF 50V PCC104BCT ND Digikey 9 C23 C24 2 CAP MKP 0 47uF 400V 495 1315 ND Digikey 0 1 C25 C26 2 CAP MKPs 400V 495 1311 ND Digikey C27 C28 C29 C30 C40 C41 C42 C43 2 C45 C46 C47 R29 R30 R55 R56 R60 R61 R62 R63 3 R64 R65 R66 R67 R71 R72 14 805 OPEN 4 C31 C32 2 RB5 12 5 1000uF 50V 565 1114 ND Digikey 5 C34 C48 C49 4 AXIALO IR OPEN Digikey 6 C107 C109 2 805 16V PCC2323CT ND Digikey 7 108 114 2 805 50 PCC103BNCT ND Digikey 8 805 50V PCC102CGCT ND Digikey 9 2 805 100 50V PCC101CGCT ND Digikey 20 CID 805 1200pF 50V 478 1372 1 ND Digikey 21 CII6 CII7
42. signal is an analog signal below 20 kHz up to 3 5V peak having a source impedance of less than 600 ohms A 30 60 kHz input signal can cause LC resonance in the output LPF resulting in an abnormally large amount of reactive current flowing through the switching stage especially at 8 ohms or higher impedance towards open load and causing OCP activation The IRAUDAMPS has RC network Fig25 or Zobel network R47 and C25 to dampen the resonance and protect the board in such an event but is not thermally rated to handle continuous supersonic frequencies These supersonic input frequencies therefore should be avoided Separate mono RCA connectors provide input to each of the two channels Although both channels share a common ground it is necessary to connect each channel separately to limit noise and crosstalk between channels www irf com IRAUDAMP5 REV 3 3 Page 22 of 49 Internotionol Rectifier LP Filter lt 2 0 L ON ono b em C23 s C252 57 Zobel Filter and Output filter demodulator Fig 25 Output Both outputs for the IRAUDAMPS single ended and therefore have terminals labeled and with the terminal connected to power ground Each channel is optimized for a 4 Ohm speaker load for a maximum output power 120W but is capable of operating with higher load impedances at reduced power at which point the frequency response will have
43. tal Harmonics Distortion Noise THD N versus power output Fig 3 4 2 1 0E A d E B r E 6E AE 8E 9 10 20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k 200k Hz Frequency Response Red CHI 4 Ohm 2V Output Blue 8 Ohm 2V Output Frequency Characteristics vs Load Impedance Fig 4 www irf com IRAUDAMP5 3 3 Page 6 of 49 International TER Rectifier THD versus Frequency 100 50 0 1 0 05 0 001 0 0005 0 0001 20 Pink 1W Output Blue 10W Output Cyan 50W Output Green 100W Output THD N Ratio vs Frequency Fig 5 Frequency Spectrum 0 10 20 30 40 50 60 70 80 90 100 110 20 50 100 200 500 1k 2k 5k 10k 20k Red 1kHz Self Oscillator 400kHz Blue CH2 1kHz Self Oscillator 400kHz F ig 6 Frequency Spectrum www irf com IRAUDAMP5 REV 3 3 Page 7 of 49 International Rectifier REFERENCE DESIGN
44. the resistor temperature rises above 100 C the OTP is activated The OTP protection will only shutdown the relevant channel by pulling the CSD pin low and will recover once the temperature at the PTC has dropped sufficiently This temperature protection limit yields a PCB temperature at the MOSFET of about 100 C which is limited by the PCB material and not by the operating range of the MOSFET Over Current Protection OCP The OCP internal to the IRS2092S shuts down the IC if an OCP is sensed in either of the output MOSFETs For a complete description of the OCP circuitry please refer to the IRS2092S datasheet 15 brief description Low Side Current Sensing Fig 15 shows the low side as is protected from an overload condition by measuring the low side MOSFET drain to source voltage during the low side on state and will shut down the switching operation if the load current exceeds a preset trip level The voltage setting on the OCSET pin programs the threshold for low side over current sensing Thus if the VS voltage during low side conduction is higher than the OCSET voltage the IRS2092S will trip and CSD goes down It is recommended to use VREF to supply a reference voltage to a resistive divider R19 and R18 for CH1 to generate a voltage to OCSET this gives better variability against VCC fluctuations For IRAUDAMPS the low side over current trip level is set to 0 65V For IRF6645 DirectFET MOSFETs wit
45. ute terms at higher frequencies distortion due to switching time becomes significant while at lower frequencies the bandwidth of the amplifier suffers In relative terms interference between channels is most significant if the relative frequency difference is within the audible range Normally when adjusting the self oscillating frequency of the different channels it is best to either match the frequencies accurately or have them separated by at least 25kHz With the installed components it is possible to change the self oscillating frequency from about 300kHz up to 450kHz as shown on Fig 30 Switches and Indicators There are four different indicators on the reference design as shown in the figure 31 below 1 An orange LED signifying a fault shutdown condition when lit A green LED on the motherboard signifying conditions are normal and fault condition is present 3 A blue LED on the daughter board module signifying there are HO pulses for 4 blue LED on the daughter board module signifying there are HO pulses for CH2 There are three switches on the reference design 1 Switch 51 is a trip and reset push button Pushing this button has the same effect as a fault condition The circuit will restart about three seconds after the shutdown button is released 2 Switch 52 is an internal clock sync frequency selector This feature allows the designer to modify the switching frequency in order to avoid AM radio interference
46. utput www irf com IRAUDAMP5 REV 3 3 Page 4 of 49 Internationa Rectifier Test Procedures Connect 4 250W load to outputs connectors 13 and J4 and Audio Precision analyzer AP Connect Audio Signal Generator to J6 and 15 for and CH2 respectively AP Connect a dual power supply to J7 pre adjusted to 35V as shown in Figure 2 above Set switch S3 to middle position self oscillating Set volume level knob R108 fully counter clockwise minimum volume Turn on the power supply Note always apply or remove the 35V at the same time Orange LED Protection should turn on almost immediately and turn off after about 3s Green LED Normal then turns on after orange LED is extinguished and should stay on One second after the green LED turns on the two blue LEDS on the Daughter Board should turn on and stay on for each channel indicating that a PWM signal is present at LO 10 With an Oscilloscope monitor switching waveform at test points and TP2 of CH1 and 2 on Daughter Board 11 If necessary adjust the self oscillating switching frequency AUDAMPS to 400KHz 5kHz using potentiometer R29P For IRAUDAMPS the self oscillating switching frequency is pre calibrated to 400 KHz To modify the AUDAMPS frequency change the values of potentiometers R21 and R22 for CH1 and CH2 respectively 12 Quiescent current for the positive supply should be 70mA 10mA at 35V 13 Quiescent current for th
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