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1. amp CALCULATE BREAKER AMP RATING USING LONG TIME MULTILIER amp amp 18 888 88 8 8c 88 8 88 B88 AAA AAA 8 8 8B 8B 8B BB BB 8 8 8 BB KEK REE GET THE LONG TIME OR FULL LOAD SWITCH VALUE BRAT LTEMPL POINT TO LONG TIME SWITCH TEMP MEM LOCATION PACKET NUMBER 5 SKABT 0 CHECK FOR MOTOR PROTECT TU RC NOT MOTOR PROTECT TU RESET CARRY LTS ACC LONG TIME SWITCH LS SWITCH VALUE XADR LTEMPH TIME SWITCH HIGH NIBBLE SET TEMP STORAGE LOCATIONS TO ZERO LAI 008 0 SLOW TRIP CURRENT SETTING NIBBLE ST LHL MIDDLE TRIP CURRENT SETTING NIBBLE ST LHU HIGH TRIP CURRENT SETTING NIBBLE GJMP TCS amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER 1 amp BEBE EEE SEES ESSE SEE SESE EE EERE EERE EERE KARR EE ORG OCOH DB OE8H DE2H O7EH 0 2 DOCH D18H 083H 0D6H 053H OOOH 023 08 DB OCAHOCAHOOD DB O3H D4H D5H 05H D5H 05H 06H OSH 07H 07H D9H AMPI RT ADD COMPLEMENTED LTS VALUE RATING TO CALCULATE BREAKER LT CURRENT TCS ST STORE DATA RC LHU TEMPI AMP LOW NIBBLE LADR LTEMPL ACC COMPLEMENTED LONG TIME SWITCH LOW NIBBLE ACSC HD NOP ST DLS POINT TO AMP MIDD
2. 1 THE FOLLOWING 31 BYTE DEFINITIONS REPRESENT THE TRANSMIT BUFFER B TRIP STATUS BYTE 1 BYTE 00 PICK UP TRIP INDICATOR A PHASE 5 RMB 2 2 PHASE RMS RMB 2 PHASE B CURRENT B OVPU SCRIN RB 1 OVERLOAD PU SC RESTR IN B C PEASE RMS RMB 2 PHASE C CURRENT B CURRENT ma 2 GROUND FAULT CURRENT B SC PU GF PU RMB 1 C amp P U amp PICKUPS REPLACES GF PU PU G MAX PHASE I RB 2 MAXIMUM PHASE CURRENT MAX IDENT 1 9 MAXIMUM PHASE IDENTIFIER SENSR_TU_ID RMB 1 SENSOR BREAKER ID RP OPTIONS RB 1 RATING PLUG OPTIONS LT SWITCHES RB 1 LONG TIME SWITCHES ST SWITCHES RMB 1 SHORT TIME SWITCHES IN PU SWITCHES RB 1 INST PU SWITCHES GF SWITCHES RB 1 GF SWITCHES PU TRIP CNT RMB 1 OF PHASE UNBAL TRIPS LT TRIP CNT RMB 1 LT TRIPS SC TRIP CNT RB 1 OF ST TRIPS SOFT TRIP CNT PEASE TRIP I B PHASE TRIP TRIP CAUSE E PEASE TRIP I TRIP CURRENT TI MEM RATIO PEASEA UNBAL PEASEB UNBAL PHASEC UNBAL SOFT VERS ADDRESS CHECK SUM SERIAL BUF END 29 12 5 089 928 30 OF GND FAULT TRIPS CURRENT OF PHASE CAUSING TRIP OF SOFIWARE FAILURE TRIPS PHASE A CURRENT 8 LAST TRIP B PHASE B CURRENT 8 LAST TRIP B CAUSE OF LAST TRIP PHASE C CURRENT 8 LAST TRIP GROUND FAULT CURRENT 8 LAST TRIP LONG TIM
3. ASSIGNMENTS FOR FLAGSS GLOBAL FLAG REGISTER SERIAL EQUAL 01 ids set until valid serial data is available flags WRD_ALIGN_BIT EQUAL 02 set to l word aligned off is dbl word fla RESUILD GF EQUAL 04 bit set when G F memory is true FLAGS KILL WATCHDOG BIT EQUAL 08 shutoff watchdog pulses during trip i sequence flags 50 EQUAL 10 BIT SET IN FLAGSS FOR I SQ IN 16X16 57 BIT EQUAL 20 this bit on in flagsS means short time NO GF BIT EQUAL 40 this bit on in flacs means no GF EQUAL 80 high bit of system flags set pe brkr END OF FLAGSS BIT DEFINITIONS pee ai START OF GF FLAGS BIT DEFINITIONS PHASE UNBALANCE seeeres PUPU BIT EQUAL 501 when in Phase Unbal pick up P U flags DOUBLE 12 BIT EQUAL 08 indicates PUP taken into acct for 172 values USE XS BIT EQUAL 10 for current conversion routine indicates GF c TURN ON DESENSE EQUAL 20 bit set to indicate to turn desense on EQUAL 540 ground fault pick up flag bit SUPER R_DESENSE EQUAL 80 zif peak phase current gt 6xP super desense END GF FLAGS BIT DEFINITIONS PHASE UNBALANCE ererewers START OF LT FLC FLAGS DEFINITIONS SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING LT PU BIT EQUA
4. X POINTS TO ANY 4 BYTE ACCUMULATOR ADDS I 2 IN THE DBL ACCUM TO THE 4 BYTE ACCUM POINTED TO BY X T DBL REGISTER CONTAINS THE 16 BIT VALUE TO ADD TO THE ACCUMULATOR ACCUM4 ADD EU ADDD 2 X ADD DBL ACCUM TO LOW WORD Smp 2X STORE LOW WORD OF 4 BYTE ACCUM ACCUM4 RET CARRY BIT ALL DONE IDD 0 WORD OF 4 BYTE ACCUM ADDD 1 ADD CARRY TO HI WORD STD 0 STORE DBL ACCUM IN HI WORD ACCUM4 RET RTS LT DEC ACCUM Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 5 089 928 91 92 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING THIS ROUTINE IS CALLED BY THE EXEC EVERY 12 MS IF PEAK SQRT IS BELOW PICK UP IT WILL DEC L7 ACCUM BY ONE OF THE FOLLOWING IF LT ACCUM gt 22 SECONDS IT WILL SUBTRACT ACCUM 2 19 FROM IT ACCUM ELSE IT WILL SUBTRACT LT ACCUM 2 16 FROM TEE LT ACCUM CALLED According to description above RETURNS Nothing works on LT ACCUM memory location 4 4 USES ACCB IX RESTORES Nothing 2111111211111011 TEMP USED DEC ACCUM EQU LT ACCUM EQU TEST FOR LT_ACCUM gt 22 SECONDS LDD LT ACCUM LOAD EI WORD LT ACCUM BEQ BI WORD IS 2ERO is hi word
5. 5 TIME DELAY TABLETTTTITTTTTTTTTTTTTTTTTTTTTTTTTT 51 FIXED EQU FIXED DEL EQU 78 173 287 458 78 173 287 458 DW 74 169 283 454 58 153 267 438 Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING DW 67 162 276 447 6 DW 40 135 249 420 205 SHORT TIME 172 IN TABLES 5 ABOVE NOMINAL TO EELP ADJUST FOR EXTENDED BREAKER OPENNING TIMES AT CURRENT VALUES LESS THAN 12xP ST 150 DEL EQU LONG 00000000 00000000 00000000 00000000 LE LoNG 85756673 53672191 32282535 14457823 LONG 500000000 500000000 500000000 500000000 LONG 85756673 53672191 32282535 14457823 LONG 500000000 500000000 500000000 500000000 NE LoNG 84964464 52879981 31490326 13665613 LONG 00000000 00000000 500000000 00000000 LONG 81795626 49711143 28321488 10496775 LONG 500000000 500000000 500000000 500000000 SE LONG 83578097 51493615 30103959 12279247 5 089 928 147 148 LONG 00000000 500000000 500000000 500000000 05 LONG 178230684 46146201 24756545 6931833 TABLES ARE PADDED WITH O s SO SET TBL INDEX ROUTINE WORKS CORRECTLY GROUND FAULT PU TABLE PU TBL EQU 5 SENSOR 1600A DW 45 56 68 79 102 124 147 170 SENSOR 2000A DW 72 81 90 99 108 118 127 136 SEN
6. 361 44 Ping system employs a reliable low power trip indicator 4 208 693 6 1980 Dickens et al 361 94 Circuit that is normally powered from the tripping sys 4 331 997 5 1982 Engel et al 361 93 tem liquid crystal display is used to indicate the 4 331 998 5 1982 Matsko et al 361 93 status of the system and a battery is used as a secondary 4 331 999 5 1982 Engel et al 361 94 power source after a trip terminates the power to the 4 Pic EAT system The battery is enabled by a manual switch or by 4337837 3 1983 Matsko et aoe 361 105 a latch which responds to one of a plurality of trip 4338647 6 1982 Wilson et al id HELD 361 96 signals from the processor The latch also provides 4351012 9 1982 Elms etal UU 361 96 Signals to a driver circuit to drive the LCD Once en 4 351 013 9 1982 et al 7361 96 abled the battery provides power to the latch and the 4 377 836 3 1983 Elms et al 361 96 LCD so that the cause of the trip may be displayed 4 419 619 12 1983 Jindrick et al 323 257 during a power fault The manual switch can be used to 4 428 022 1 1984 Engel et al 351 96 select status signals to be displayed on the LCD and to 4 429 340 1 1984 Howell 361 96 indicate the condition of the battery The LCD includes 10 ion Saletta et ee E En a segment for indicating that the system is energized and ites er vie pov power is being
7. ONBOARD REGISTER LOCATIONS BCLR PORTD X 20 TURN OFF OUTPUT TO DECREASE MEM DELAY RTS ADJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTS oco dede s e de re e de DBL WORDS 4 SEAS SESSA ANE SSS i THIS ROUTINE COMPARES TWO 4 BYTE VALUES IY POINIS TO FIRST 4 BYTE VALUE 5 089 928 79 80 AND IX POINTS TO THE SECOND 4 BYTE VALUE RETURNS THE RESULT OF THE COMPARE AS FOLLOWS FIRST VALUE 2ND VALUE THEN 0 ON RETURN IF 1ST VALUE gt gt 2ND VALUE THEN ACCA 2 ON RETURN IF 1ST VALUE lt lt 2ND VALUE THEN 1 ON RETURN 4 4 44 WORD LDD 0 Y WORD 1ST VALUE 0 WORD 2ND VALUE Square D Company ADE Group Jerry Baack Leon Durivage 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING BHI HIGHER 2 gt X SET HIGHER BIT BLO SET LOWER X gt Y SET LOWER BIT EI WRD EQUAL 2 9 LOW WORD OF 1ST VALUE CPD 2 LOW WORD OF 2ND VALUE BHI SET HIGEER gt X SET HIGHER BIT BLO SET LOWER X gt Y SET LOWER BIT LOW WRD EQUAL EQU S CLRA 1ST AND 2ND ARE EQUAL RTS SET HIGHER LDAA 02 1ST IS GREATER THAN 2ND RTS SET LOWER LDAA 580 1ST IS LESS THAN 2ND RTS CALC LT ACCUM 1 THIS SUBROUTINE CALCULATES LONG TIME MEMORY CAPACITOR EQUIVALENT
8. TEST SEE IF GROUND FAULT 15 INSTALALLED EVEN MS 5 LDAA 2MS GF get 2 mS ground fault timer 2 has 2 ms passed BLO CHECK 07 5 2 mS hasn t passed leave SUBA 2 ireset timer STAA T 2MS GF 5 timer JSR _ CHECK FOR GF time up GF check wow yo vedete je dede de dede vto de o de de de de e ed o HR OUR UR RO RU ER FER s TEST FOR ANY FIXED MS TIMERS ow deve eee de de de de e e ce e e e e e e e eR c He e e e qe o dee dedo d e CHECK 07MS LT memory cap is set on power up and adjusted this time 8 ewm one de ede e e e oe e de e e 7 MS TIMER vedo v de decem in de de de de dee dee dde med LDAA T 07MS GET 17 MS TIMER 07 HAS IT EXPIRED YET BLO CHECK 11MS TIMER HAS NOT EXPIRED THE FOLLOWING CALLS ARE DONE EVERY MS SUBA 7 reset timer STAA T 07 5 CALLS DONE CLEAR 7 MS TIMER JSR INST TABLE read INST switches for interrupt use Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING if serial isn t valid check LT memory BRSET FLAGSS KILL SERIAL BIT CHECK LT MEMORY JSR SERIAL CBAR TO DISP EVERY 12 MS CHECK LT MEMORY EQU BRCLR LT FLAGS SET ACCUM BIT CHECK GTZ BIT LDX 97 RATIO UMP DO FIRST PASS if bit set on first pass make sure we calculate a LT accu
9. 8 8 9 8 Me ds d 8 ORG 40H DB 038H 0590H 07 1H 07BH 083H D91H 097H 9 00000000 078H 080H 085H 089H 093H 098H 09CH LS LAMT RT gt SERIAL PORT INITIALIZATION LA 01018 SERIAL SETUP DATA OP ACCTO SERIAL MODE SELECT REGISTER MSR TIMER INITIALZATION ACCUMULATOR WITH MODULO NIBBLE HL WITH POINTER TO LOW MODULO NIBBLE ST iSTORE ACC IN MEM POINTED TO BY HL TAMMOD TRANSFER ACC AND HL TO MODULO REGISTER LA 00008 DISPLAY FRAME CLOCK FREQUENCY FCL 1024 OCH ACC TO CLOCK MODE SELECT REGISTER TIMER sRESET TIMER COUNT El IMEF F 1 INTERRUPT MASTER ENABLE O7H 7 QNTERRUPT ENABLE REGISTER ALL ENABLED XADR TCNT ACC 0 RESET SOFTDOG TIMER GJMP INTI JUMP TO MEMORY INITALIZATION 5588888888 8 88 858 8 8 8 8 8 8 8 8 8 B 808 8 8 8 8 8 8 58 8 88 5 8 58 8 8 8 8 8 8 8 8 8 85 8 amp TISR SOFTDOG TIMER INTERRUPT ROUTINE amp x amp 84882 82884883884448488848484838884888888444888444884888 4888 XADR ACCTMP RC 151 v ira MM CM MM CMM II C MI S amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER amp amp amp 5 089 928 163 164 ORG DB O20H0EBH D65H DBOH 0E2H 035H 078H D40H D83H DD6H DB 008 000 00 DB OSH 05 OSH OSH D6H 06H 07H 07H
10. 95005089928 United States Patent ij Patent Number 5 089 928 Durivage III et al 45 Date of Patent Feb 18 1992 54 PROCESSOR CONTROLLED CIRCUIT 4 706 155 11 1987 Durivage et al 361 64 BREAKER TRIP SYSTEM HAVING 4 709 339 11 1987 Fernandes 2 364 492 RELIABLE STATUS DISPLAY 4 717 985 1 1988 Demeyer 361 96 4 747 061 5 1988 Lagree et al 364 483 75 Inventors Leon W Durivage III Marion 4 752 853 6 1988 Matsko et 361 94 William J Bacher Cedar Rapids 4 783 748 11 1988 Swarztrauber 364 483 both of Towa 4 794 369 12 1988 Haferd 344 166 4 803 635 2 1989 Andow 364 483 73 Assignee Square D Company Palatine Ill 4 996 646 2 1991 Farrington 364 483 21 Appl No 403 244 OTHER PUBLICATIONS 22 Filed Aug 31 1989 General Electric Publication GEH 4291 51 H02H 3 04 Schematic of Circuit Board Including a Ground Fault 361 94 Test Transducer Sold by Square D i 340 664 364 483 Primary Examiner Todd E DeBoer 58 Field of Search 361 93 97 Attorney Agent or Firm Larry 1 Golden Jose W 340 662 664 307 66 364 483 Jimenez 56 References Cited 57 ABSTRACT U S PATENT DOCUMENTS A fault powered processor based circuit breaker trip 4 121 269 10 1978 Hobson
11. MY se ve Se PORTA X GF RES OUT CLEAR GF RESTRAINT OUTPUT BIT BSET GF RESTRN TIME SFF SET TIMER NUMBER TO NULL RIS GROUND FAULT RETENTION TIME OUT CALLED When the GF retention timer counts down to 0 after amp GF pick vp No registers are passed into the routine 7 se Se 54 09 t 44 t RETURNS GF accumulator cleared restrained delay timer set to SFFIT unrestrained timer set to 33 and the DOUBLE 12 bit cleared USED ACCA ACCB RESTORED Nothing 9e ve so we 44 4 4 25 4 a GF_RETN_TIMOUT EW 0000 STD GF_ACCUM CLIAR WORD GF ACCUMULATER STD GF ACCUM 2 CLEAR LOW WORD OF GF ACCUMULATER LDAA 33 34 MS GF FAST TIMER VALUE STAA FTIMER SET IN GF FAST TIMER CEECK FOR GROUND FAULT FIXED DELAY TIMER ACTIVE IF SO THEN CANCEL IT LDD 5 GET NULL VALUE STD GF LONG TIME RESET FIXED RSTRN DELAY STD RETN TIME NULL RETENTION TIMER GF_FLAGS DOUBLE_I2_ don t double 172 calculations na GROUND FAULT ROUTINES PAGE Q v te tewt tt teetevttetete MUL 16 16 z we CALLED From long time accum calculation serial data conversicn routine amp locked rotor routines with IX an
12. of trip long time BCLR PU TRIP CNT 40 cause of trip phase unbal BCLR SC TRIP 40 cause of trip short circuit BCLR GF TRIP CNT S40 cause of trip fault BSET SOFT TRIP CNT 40 cause of trip soft dog JM GLOBAL TRIP igo to global trip wait for watch dog r t t DECREMENT ROUTINE t9 29 9 t y 22 CALLED From the one second timer whenever there is active softdceg timer RETURNS Clears any errors that have timed out If no remaining errors exist resets the error counter 2 USED RESTORED NOTHING 111111111101 a ee n ng SOFT DOG 5 LDX DOG TIMERl get timer value DEX decrement it STX SOFT DOG TIMERI ssave it back again BNE CHECK SOFT T2 timer 1 hasn t timed out go 2 LDX SOFT poc TIMER2 iget timer 2 value STX SOFT DOG TIMER1 it into timer 1 10 0000 load 0 to clear STD SOFT DOG TIMER2 clear timer 2 DEC SOFT DOG CNTR decrement the softdog counter BNE HOME still have more errors LDAA get softdog reset value STAA DOG CNTR reset the counter 60 HOME return to routine 5 22 EQU Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 83 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING IDX SOFT DOG TIMER2 get timer 2 BEQ G
13. 88 8 8 8 8 8 8 8 8 888380858 888 85 58 8 88 8885 LIC amp ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER AT AMP7 ORG 24H DB _ 088HD6AH D80H D7AH DACH 082H D94H D2EH OA4H D10H DAAH OBCH DB 0F2H0D4H0D DB 013H18HD1BH D1CH D 1DH O1EH O20H D22H D24H 027H 028 O2BH 030H DB RT 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 5 5 ARAT RATING MIDDLE AND HIGH NIBBLE 5555555555555555555555555555555555555555555555555555555555555555555555555555 DLS AMP RATING MIDDLE NIBBLE BT2 ST STORE MIDDLE NIBBLE SC LADR ACC x RATING PLUG POINTER DLS AMP RATING HIGH NIBBLE RT CONTINUE WITH 10X RATING CALCULATION DLS 5 GJMP TRATI RT TRATI ST DES GJMP TRAT2 ANOTHER ITERATION RT CALCULATION DONE RETURN IF OVERFLOW ERROR IE ESEREEEAEAAERARRANESASSESKESESKESERESSESKEKERRENEEEEE ESSE EEK ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT AMPB ORG D8 000H 040H D28H 072H 060H 012 DB 040H080H00 5 089 928 173 174 DB 019H01FH023H 024H
14. LHU PACKET 3 SAVE ONLY HIGH BYTE 0 2 TOTHE LONG TIME DATA BYTE SKAEM GJMP HBI TEA SERIAL HIGH BYTE XADR TLTS LAJ 07H 5 089 928 189 190 WU 115 ANL XADR TLTS GJMP El EXT TEA SERIAL HIGH BYTE LOW NIBBLE XADR THLSN TEMP HIGH BYTE LSN TOA SERIAL HIGH BYTE HIGH NIBBLE XADR THMSN HIGH BYTE MSN GJMP El AND STORE LOW DATA BYTE B4 PACKET 3 RETURN SKAEM GJMP 841 GJMP B41 LADR BC XAE EXCHANGE ACC AND E REGISTERS DES DECREMENT E REG BC 1 GJMP B7 GJMP RETURN IF UNDERFLOW B7 XAE ACC AND E REGISTERS SKAEM 1 1 GJMP E LA 048 RATING PLUG BYTE 1 SKAEM GJMP LB GJMP B LB TEA SERIAL LOW BYTE LOW NIBBLE XADR TLLSN TEMP LOW BYTE LSN TDA SERIAL LOW BYTE HIGH NIBBLE XADR TLMSN LOW BYTE MSN GJMP E SAVESENSORID 85 TSD HL POINT TO SENSOR ID ACC SERIAL LOW NIBBLE ST STORE SENSOR GJMP El sSAVE RATING PLUG B TEA ACC SERIAL LOW XADR STORE RATING PLUG TDA ACC x SERIAL HIGH XADR STORE TRIP UNIT OPTIONS _ ACCTMP RT 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 BCD HEX TO BCD CONVERSION ROUTINE i SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
15. END OF FLAG BIT ASSIGNMENTS START OF PORT BITS USED SOR RO e e o TRIP BIT O LED 52 1 RESTR BIT_OUT 27 EQUAL EQUAL EQUAL 52 RESTRAINT BIT IN Gz _ 5 BIT OUT RES OUT FORES IN REST ACTIVE T INACTIVE BIT WATCEDOG BIT MOTOR PROT BIT VOLTS OK EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL DESENSE THRESHOLD EQUAL CAP BIT 2 TRANSMIT DONE MAX Sw POS SWITCH MASK EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL PROD TEST DESIGNATOR Sorina VERSION EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL RAM 80 08 10 EQUAL EQUAL 20 02 40 80 40 10 02 171 20 10 08 580 277 1 EQUAL 13 10 3FFF 34 30 11DB 11D 5 089 928 28 BIT OF PORTA FOR TRIP BIT OF PORTA FOR FLASHING LED INST ST restraint output bit 04 restraint input bit 04 2 PORT D ALSO MISO OF SPI ground fault restraint output bit ground fault restraint input bit bit in serial comm for GF restraint status 1 set to one timer is not active hardware watchdog bit this bit set in serial comm for motor code this bit set means we have 15 Volts for trip desense threshold 3xP peak zbit to charge memory capacitor ibit to toggle for EEPROM serial clock this amp serial data bit for EEPROM SDA need switched transmit reg empty bit SCSR register maximum allowable switch position mask valu
16. SQRT RMS SQROOT GOTO TEST_64MS T_PHASEB_2MS d Se 5 Se Se 4 Ye ve IF T PHASEB RMS lt 8 TEST PHASEC ELSE IF B PHASE CONV 0 GOTO TEST PHASEC ELSE PHASE UNBALENCE SQRT IF SERIAL POINTER PHASE RMS ELSE 5 4 454 te 4 H a Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING CONVERSION PEASB SQRT B PHASE B PHASE CONV 0 GOTO TEST 64MS TEST PHASEC PHASEC RMS lt 64 TEST PEASEC 2 5 C PHASE CONV 1 T PHASEC RMS RMS 64 AVG RMS 3 SQRT RMS_SOROOT GOTO TEST 64MS TEST PHASEC 2MS IF T_PHASEC_RMS lt 8 GOTO TEST 64MS ELSE IF C PHASE CONV 0 TEST 64 5 ELSE PHASE UNBALENCE PHASC_SORT IF SERIAL POINTER PHRASE RMS ELSE I CONVERSION PHASC SQRT C PEASE R 0 TEST 64MS T 64MS lt 64 GOTO 250MS ELSE T 64MS 64MS 64 LT SERIAL BITS FIND SORT LONG TIMEQ 5 089 928 49 50 IF 250 MS TIMER lt 250 1 SEC gt ELSE T 250MS T 250MS 250 T 1000 5 KILL SERIAL 0 CHECK LED SET TRI
17. Square D Company ADE Group Jerry Baack Leon Durivage 8 16 89 153 5 089 928 154 SERIES ELECTRONIC TRIP SYSTEM SOFIWARE LISTING 522 PRODUCTION TEST CODE 15 HERE dede dede deed demnm PRODUCTION TEST EQU CLR DDRD REGSTART LDAA PORTA REGSTART ANDA 4501 BNE WALK A 1 set potrD to inputs check for gf cap mask all but zif 0 cap is discharged JMP CHECK RAM MEM RETENTION WALK A 1 EQU 5 LDX END 1 LDD 55 DECREMENT AND STORE EQU STD 0 DEX DEX CPX 00 DECREMENT AND STORE LDX END 3 IDY SWITCHES to GF RAM locations load value store bit pattern up 1 it again check for bottom not done so store again point to RAM locations storage case of error JSR CHECK RAM RETENTION BSET IN PU SWITCHES 70 BRA RAM TEST CHECK RAM MEM RETENTION EQU LDD 555 LDX LONG TIME 1 PU SWITCHES JSR RAM RETENTION GF RAM TEST OK EQU JSR RESET COP PAGE set to indicate not tested branch around test load value point to GF RAM locations storage in case of error zkeep the puppy happy CHECKSUM TEST DONE HERE e tesuewwwetetwrvtetewietrwETY 5 test takes roughly 81 000 clock cycles or 40 mSec wil
18. tripping tripped condition RETURNS No values only sends a byte out the SPI amp SCI ports Se ba be 4 4 to te USED ACCA ACCB IX RESTORED NOTHING 1111111 5 54 t t ve t a s COMMENTS TEE CALLING ROUTINE IS RESPONSIBLE TO MAKE SURE THE SCI REGISTER IS CLEAR BEFORE CALLING THIS ROUTINE in SCSR is set 9 This routine automatically runs through transmit buffer and sends Out according to the serial comm spec Data is sent out SPI amp SCI ports Data is sent out in 8 byte packets Data transmission is in grours of rotating packets packet 0 1 2 0 1 3 0 1 4 0 1 5 0 1 6 0 1 7 4 49 9 9 te t Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING then repeated from 0 1 2 0 1 3 EOULTEGCIHESO211111 11 113 TEMP USED 11111 1913 1 2 12108 09 02 202 1313 p E093 91 9 9 1 Initial section checks byte pointer for byte 0 6 or 7 exception bytes Byte 0 is always trip status byte amp packet Byte 6 is the trip unit address upward compatability Byte 7 is always the checksum of the previous bytes Bytes 1 thru 5 are trip unit data see serial comm spec for details 5 se 5 5 089 928 125 126 SERIAL IDX SERIAL pointer for serial buffer BY
19. PESENSE i BCLR FLAGS TURN ON DESENSE turn off desense LDX REGSTART point to registers PORTD X Gr DESENSE OUT turn off desense CLR VALS EQU LDD 00 VALUE OF 0 FOR PEAK RESET STD ST PEAK RESET ST PEAK FOR NEXT 12 mSEC PEAK 5 089 928 101 102 Square D Company ADE Group Jerry Baack Leon Durivage 8 16 83 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING STD PHASEX6 clear peak of A phase STD B PHASEX6 clear peak of B phase STD C PHASEX6 clear peak of C phase RTS STFU IS EITHER CLEARED OR LEFT SET SO RETURN DTTTTTTTTTTTTTTTTTTTITTTTTITIT ST RETN TIMOUT CALLED From 3 mSec ST retention timer time out RETURNS ST accumulator cleared ST 172 out timer cleared Unrestrained ST timer amp Double Accumulator flag cleared USED amp RESTORED NOTHING EE TIMOUT EQU LDAA 33 st fast timer value 33ms STAA ST FTIMER st fast timer to 33ms LDD FFFF load timer nui value STD ST 12 OUT TIMER null 1 2 out timer STAA ST RETN TIMER null ST retention timer CLR ST ACCUM EQU clear I 2in accumulator here 0000 STD ST ACCUM set hi word st accum to zero STD ST 2 iset low word st accum to zero BCLR 51 FLAGS DOUBLE ST I2 don t double 1 2 values RTS retur
20. SWITCH COMMUNICATIONS MUST BE KEPT OR TEMP MUST HOLD LT SWITCH VALUE JSR LT FLC SW COMM GO DO SERIAL COMM FOR SWITCHES RTS RETURN TO MAIN FLOW peek ewe eRe TE WE EXCEED LT DELAY VALUE WE END UP HERE eeettteweenneae LT_TRIP EQU SEI MORE INTERUUPTS PLEASE JSR RESET COP go reset the softdog LDX REGSTART BCLR TRIP STATUS 570 CLEAR TRIP CAUSE BSET TRIP STATUS BYTE 10 SET CAUSE OF TRIP AS LT TRIP COMMON LONG 5 LDAA TRIP increment of LT trips 7 ANDA 63 mask off unused bits CMPA 63 max trip BES CLR LT TRIPS if high bit clear leave INC LT TRIP CNT still room increment counters JMP GLBAL continue CLR LT TRIPS EQU CLR LT TRIP CNT clear counter for rollover GO_GLBAL 5 BCLR FLAGSS KILL WATCHDOG snot soft trip so clr kill bit LDX REGSTART onboard register locations LDAA 1 0 get value to turn on LT trip line STAA PORTA X turn line on STAA TRIP FLAG SAVE FOR TRIP OUTDICATOR BSET LT TRIP CNT 40 cause of trip long time BCLR PU TRIP 540 cause of trip phase unbal BCLR SC TRIP CNI 40 cause of trip short circuit BCLR GF TRIP 40 cause of trip gnd fault BCLR SOFT TRIP 540 cause of trip soft dog 4DELAY 32MS JMP CHECK GO CHECK TRIP VOLTAGE o8 dee c dee dee e de dece e e e de ded dede n ACCUM4 ADD dde se de de ee e de ede ede
21. the number of samples time at discrete intervals determined by the accumulation rate and the true RMS value of current through the breaker During fault the trip unit will begin to sum the current squared value as soon as the current exceeds a predetermined level for a predetermined period of time or the selected overload condition The electronic trip system will maintain an internal accumulation register to store a value that is proportional to the square of the current and that is incremented periodically based on the accumulation rate Assuming a constant fault level of current a fixed accumulation rate and a known con dition of the accumulation register at t O the value the accumulation register will increase at a determinate rate and will contain a known value at any giyen time t For example assume that a continuous fault is mea sured at 70 71 amperes RMS with an accumulation period of 64 milliseconds Further assume that the accu mulation register is at zero prior to the fault The mi crocomputer 120 will accumulate the squared value of the current every 64 milliseconds into the register caus ing it to increase at a constant rate With a continuous fixed level fault as time increases the internal accumulation register increases proportion ally In order to protect the system from this fault this increasing accumulated value is compared periodically 20 25 30 35 45 55 60
22. 18848888888888888882888888488884448888888888882888888888 amp amp ROM LOOKUP ROUTINE FOR LCD DATA LEFT SIDE OF CHAR amp amp 8888888888888888488888488884888888488888888888844888444 ORG 480H DLEFT DB 60204460640 LEFT RT MAIN DATA ROUTINE PROGRAM FLOW CONTROL AND DATA PROCESSING SUBROUTINES CALLED SOFTWARE WATCHDOG RESET PRCNT PERCENT OF RATING CALC AND DISPLAY BCD BCD CONVERSION i DSPLY DISPLAY CURRENT IN AMPERES ORG 490H TIMER START RESET THE SOFTWARE WATCHDOG TIMER QOH XADR TCNT WAIT FOR COMPLETE DATA PACKET TRANSMISSION THE SERIAL ISR SETS THE READY FLAG RDY WATI LADR FOR SERIAL DATA AVAILABLE SKAE GJMP WAIT NOT READY WAIT TRANSFER THE TEMPORARY CURRENT INFORMATION INTO PERMANENT MEMORY LOCATIONS AFTER ALL PACKET DATA HAS BEEN SENT BY TRIP UNIT CALL XFER CLEAR THE DATA READY FLAG LA 5 ACCUMULATOR TO ZERO XADR ROY EXCHANGE ACCUMLATOR WITH DATA READY ADDRESS 5 089 928 185 186 DONT DISPLAY IF 2 OR 3 WERE LAST RCVD LADR PAK SKAEI GJMP 1 GJMP M3 SKAEI GJMP MAIN CONVERT HEX DATA INTO BCD M3 CALL BCD DISPLAY THE BREAKER OPERATION CURRENT CALL DSPLY CALCULATE AND DISPLAY THE PERCENT OF RATING BAR SEGMENTS CALL RATING CALL PRCNT GJMP MAIN RESTART THE CYCLE 555555555555555555555555555555555555555555555555555555555555555555
23. EQU 5 ST FOR PEAK OF 12 msEC BLS SCRIN CODE LESS THAN PREVIOUS PEAKS BRANCH STX ST PEAK IS GREATER SO SAVE BCLR 503 new peak phase so clear IDENT combine max phase with comm location STAA MAX IDENT save back to comm buffer SCRIN CODE EQ 5 controls SC restraint bit in comm buffer LDX REGSTART get start of onboard registers IF SC RESTRAINT IS HIGH THERE IS NO SC RESTRAINT COMING IN BRSET PORTA X SC RESTRAINT BIT IN CLR SCRINBIT BSET OVPU_SCRIN 40 is low we have restraint JMP RETURN CALLER go return LR SCRINBIT EQU BCLR OVPU_SCRIN 40 SC restraint so clear bit amp chk ST RETURN TO CALLER EQU RTS return to main motor IIIIIIIIIIIIIIIIIITIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIlIIII UP FOR INST PU TABLE amp PU SWITCH REMOVES OVERHEAD FROM INTERRUPT Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES ELECTRONIC TRIP SYSTEM SOFTWARE LISTING CALLED Relies on PE BRKR BIT and NO ST BIT to be set correctly RETURNS INST TABLE VAL points to table location of INST PU INST SWITCH holds value of INSTPU switch INST OFF bit is set cleared depending on ST amp INST switch pos INST switch value in serial comm buffer for transmission USES All registers except IY Uses TEMP RAM location to pass row value through routine No used registers are rest
24. TEST FOR GF Me se e Se Se Se Sa Se Se Se te Se Se Se Se 5e Se se Ss Se Se Se Se Se Se Se gt e e IF GF_PU_BIT 0 GOTO CLEAR GF PEAK Square D ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING ELSE IF GF RES IN 1 GOTO CLEAR PEAK RESTRAINT LINE HAVE INVERTERS ON INFUTS ELSE IF GF DELAY SWITCH lt 6 GOTO LEAR_GF_PEAK ELSE GF 150 IN CLEAR GF PEAK CHECK 13 5 64MS PHASE 64 MS TIMER IF T PHASEA RMS lt 64 5 PHASEA 2MS A PHASE CONV 1 T PHASEA RMS T RMS 64 AVG RMS SUMSQR 1 SQRT RMS SQROOT GOTO TEST 64MS e 9 9 Se Se Ss Se Se Se te gt e ce ta Se te se ve Se e 2 5 5 2 5 IF T PHASEA RMS lt 8 TEST PHASEB CELSE IF A PHASE CONV 0 TEST ELSE PHASE UNBALENCE PHASA SORT IF SERIAL POINTER PHASE RMS GOTO ST 64MS ELSE i 5 4 se HJ teo sa ty 5 089 928 47 48 1 CONVERSION SQRT A PEASE _ CONV 0 GOTO TEST _ 64MS sa 9 Se te te rj 57 IF T PHASEB RMS lt 64 TEST PHASEB 2 5 B PHASE 1 PHASES RMS PEASEB RMS 64 AVG RMS SSUMSQH 2
25. USED ACCB IX amp IY restored NOTHING TEMP USED FOR GF EQ 5 IDX REGSTART GET ONBOARD REGISTER START 5 089 928 103 104 IN SET IF WE BAVE GF REST IN SET BCLR REST ACTIVE NO GF REST SO CLEAR GF REST XET 15 GF INSTALLED SO CONTINUE WITH GF CHECKS Sz7 BSET MAX IDENT GF REST ACTIVE RECEIVING GF REST SO SET GF REST 15 GF INSTALLED EQU NON FLAGSS NO GF BIT SET GF PEAK 0 SET GO DO ST JMP EXIT GF NOT INSTALLED LEAVE GF SECTICN GF EQU LDAB LOAD CURRENT VALUE CLR CUR GF CLEAR 2mSEC GF PEAK MEMORY GF PEAK COMPARE NEW GF TO GF PEAX DATA BLS GF INSTALLED NEW VALUE IS LOWER ERANCH STAB GF PEAK AP NEW IS HIGHER SO IT PEAK GF PHASE STORE NEW GF PEAK 200200000000 INSTALLED LDAB SENSOR READ SENSOR SWITCH IN THE B ACCUM ANDB SWITCH MASK bits above CMPB 1 sensor BLS CONTINUE WITH GFPU LDAB 1 load max sensor CONTINUE WITH EQU SuBB 510 SUBTRACT 10 for 1600 sensor BMI SET TO ZERO if sensor lt 1600A result is so branch LSRS SEIFT ACCUM B TO TEE RIGET DIVIDE BY 2 LDAA 16 16 BYTES IN TABLE FOR EACH SENSOR MUL GET TABLE POSITION FOR THIS SENSOR JMP ADD_TEMP GO ADD
26. to value point to storage igo convert to xmit format FLAGSS KILL WATCHDOG TRIP V if soft trip don t send tri start of onboard regs Get trip supply location 0 VOLTS OK KILL TRIP V if low voltage kill trip coil 85 LDAA ANDA 506 4506 BEQ RESTRAINT BSET TRIP 5 540 JMP SAVE DATA EQU BCLR TRIP CAUSE 40 5 JSR ADDRESS WEE JSR WRITE EE EQU 538 RESET CLI LDAB MAX IDENT ANDB 4503 CMPB 503 BLO NORM PEAK JSR DO GF CONV LDD GF CURRENT STD PHASE I JMP CHECK TRIP V EU S 5 PEAK LDX PHASE I JSR CONVERSION EQU BRSET LDX REGSTART TRIP SUPPLY BRCLR LDAB TRIP FLAG get cause of trip Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING KILL TRIP V SERIAL RESET CEECK AGAIN NEXT PHASE oe ede de ede e ee e e e de de de de e ode de de d en PAGE LDAA ANDA ABA STAA BSET JMP EQU BCLR EQU BRCLR JSR EQU LDX EQU CMPB BLS CLR EQU INX CPX BIS LDAA PORTA X amp TRIP PORTA X PORTA X TRIP CHECK SERIAL PORTA X TRIP SCSR X TRANSMIT RESET SERIAL PHASEA 0 X 510 NEXT PHASE 250 5 REPETE GF CHECK AGAIN 250 5 RE INIT NO WRITE INITIALIZE read
27. 0 0 RC RESET CARRY LHU TEMPI POINT TO LOW BYTE LSN LADR BRL COMPLEMENT AMP RATING LOW NIBBLE DOR BRM COMPLEMENT AMP RATING MIDDLE NIBBLE LADA COMPLEMENT RATING HIGH NIBBLE v COMPLEMENT NIBBLE FOR LOW 3 NIBBLES GJMP COPYRIGHT MESSAGE DB CONV v8 us 1 5 51 EEE 8 2 BRH SET CALCULATED RATING HIGH NIBBLE BRM SET CALCULATED RATING MIDDLE NIBBLE BRL SET 02H CALCULATED RATING LOW NIBBLE 5 089 928 203 SET 10H TEMPTRIP UNIT OPTIONS TUS SET TEMPLONG TIME SWITCH TRPID SET 12H RATING PLUG ID TSD SET 13H TEMP SENSOR ID TSH SET 14H TEMPORARY SERIAL DATA HIGH TCNT SET ISH TIMERINTERRUPT COUNTER PTEMP SET 16H TEMPORARY PACKET NUMBER 204 TPAK SET VH PACKET NUMBER AFTER DATA READY SET 18H COMPARE OPTIONS MEMORY CLTS SET COMPARE LTS CRPID SET COMPARE CSID SET IBH COMPARE SID 4 SET ICH MOST SIG DIGT BCD3 SET 10H BCD2 SET BCD SET EAST SG DIGT ROY SET 20H SERIAL DATA READY BC SET 21H BYTE COUNTER BC SET 22H BYTE COUNTER TEST VALUE THMSNSET 23 TEMP HIGH BYTE MSN T
28. 2 7 compare to off position if ST on BHS INST IS OFF 7 gif switch gt position 8 INST off ADDB 2 swith ST on INST table moves up 1 value UMP FINISH TABLE POINTER ACCB has correct position so finish INST 15 OFF BRSET INST FLAGS I TIMR BIT FINISH TABLE POINTER if INST active don t CLR INST CNTR 4 clear INST PU counter LDAA 2 100 get INST timer reset value STAA INST TIMER reset the INST timer BCLR INST FLAGS INST PU 1 correct flag bits BSET INST FLAGS INST OFF BIT INST is off so set bit p switch pos 8 so set to max STX TABLE VAL store trip value JMP HOMEWORK DONE all done so leave FINISH TABLE POZNTER EQU 5 LDX TEMP get row value Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING add column position to row STX INST TABLE VAL now points to INST PU value BCLR INST FLAGS INST be sure INST is on INST HOMEWORK DONE EQU RTS 7GO BACK TO MAIN IIIIIIIIIIIIIIITIIIIIIIIIIIIIIIIIIIITIIIIITIIIIIIIIIIIIIITIIIIIIIIIITIIIIII TTTTTTTTTITTTTTTTTTTTTTTTTTTTTTTTTTTTTTTT THIS SUBROUTINE READS PU SWITCHES AND DETERMINES TYPE OF TRIP UNIT ACCA amp ACCB are used in this routine and not restored CALLED Without any preset conditions Reads ST amp GF pickup and delay switches Ma 5e Se gt e Na 44 4 RETURNS Serial communications buffers set for
29. USED IX RESTORED NOTHING PY Se Se se Se gt s Se Se se ve se so RECK GF 13 5 LDX GF TABLE POS table position in IX CLRA clear high byte LDAB GF PEAK GET PEAK OF GF VALUES FOR LAST 13 mSEC CPD 0 COMPARE VALUE TO TABLE BHS IN PU sATOD IS ABOVE THE TABLE LEAVE PU ON BCLR SC PU GF PU GF PU BIT 7CLEAR IN XMIT BUFFER BCLR GF FLAGS GF BIT CLEAR PU BSET GFL LONG TIME T_ INACTIVE put timer to sleep IN PU EQU 5 5 089 928 111 112 CLR CLEAR FOR NEW 13mSEC GF PEAK RTS RETURN TO CALLING LOCATION Square D Company ADE Group Jerry Baack Leon Durivage 8 16 29 SERIES III ELECTRONIC TRi SYSTEM SOFIWARE LISTING TITTTITITIT 11 5 RESTRAINT TIME OUT CALLED When the GF restraint timer times ovt RETURNS GF restraint timer set to SFF RESET VALUZ USED IX RESTORED NOTHING de eee ede e eode e d e deo de de dede EERE 1 TERETE RETESET HERE TERE TEIS CODE CAN ONLY BE REACHED VIA A 11 MS GF RESTRAINT HOLD TIME OUT RESTRN OFF EQ LDX REGSTART
30. find lookup table position i 17 mask off any high bits 2 rms 54005 guess y guess into rms sqroot do start of iteration loop templ rms mean 256 take only upper 16 bits temp2 rms mean 255 16 mask off low nibble of low byte F temp3 rms mean templ 256 temp2 16 get final result templ rms_scroot get resins of initial division remainder templ sqroot get remainder Square D Company ADE Group Jerry Baack Leon Durivage 8 16 85 SERIES III ELECTRONIC 5 SOFTWARE LISTING temp2 remainder 16 shift remainder and add next 4 bi result result 16 temp2 rms sqroot get 2nd result remainder temp2 rms_sqroot get 2nd remainder temp3 remainder 16 get next dividend result result 16 temp3 rms final result remainder temp3 rms sqroot final remainder remainder 2 double the remainder if remainder gt rms sqroot if remainder gt 5 increment result ra result result rms sqroot 2 find next guess temp rt rms sqgroot temporary storage n rms 50700 result put result into rums 54 005 for next iteration 2 remainder abs result temp rt find guess amp iteration difference 5 089 928 117 118
31. go check next clear PU bits get value it if low do next phase set 09 pu in communications get phase square root compare to pick if lower no pickup set for phase pick up go check next sclear PU bits Date 8 16 88 SERIES III ELECTRONIC TRI SYSTEM SOFIWARE LISTING BITS SET 11111 oe ee ee to ri t t v S7 150 IN DOUSLE FOR INIT SHORT LDD BIO BSET EQU RTS END LONG TIME PRASC SORT 0 Y BITS SET OVPU SCRIN 04 ROUTINES ST 150 ht dede cie he ie de de ede e dee n dn de de de dede m value compare it if low do next phase set 09 5 pu in communications return to calling T I M E R o U T i N E Ste dee nde START HERE CALLED Every llmSec when ST 172 in delay calculation is needed RETURNS Returns with ST ACCUM increased by Ipeak 2 or never returns and trips the breaker USED ACCA ACCB IX amp IY EQU LDX LDY JSR EQU LDX LDD JSR LDD ADDD STD 45 PEAK 5 PEAK I SQUARE 5 ACCUM RESULT 2 ACCUM4_ADD RESULT ST_ACCUM ST_ACCUM POINT TO LATEST PEAK PHASE IN X REG POINT TO LATEST PEAK PHASE IN Y REG MULT X TIMES Y X REG TO ST ACCUMULATER LOW WORD OF I SQUARE RESULT ADD I 2 TO 4 BYTE ST ACCUMULATER WORD OF I SQUARE ADD
32. 5 RMS PHASE RMS TIMER INC T RMS INCREMENT PHASE RMS TIMER INC PHASEC RMS INCREMENT PHASE C RMS TIMER INC T 64MS INCREMENT 64 mSEC TIMER INC 250 5 INCREMENT 250 mSEC TIMER JMP STROBE WDOG leave interrupt e Tm dede ASRS SALE EET TCT PPP 2 DECREMENT ALL QUEUED TIMERS DECREMENT Q TIMERS EQU LDAA INST RESET TIMER get the timer ST if negative bit set it is asleep off if 0 bypass DECA STAA INST RESET TIMER 5 089 928 141 ST EQU LDAA ST RETN TIMER retention timer value BLE TO RESTRAIN YOURSELF 214 negative it is asleep off DECA STAA ST RETN TIMER TRY TO RESTRAIN YOURSELF tT LDAA 5 RESTRN TIMER BLE OUT 12 if negative we asleep off DECA STAA SC RESTRN TIMER 142 Square D Company Group Jerry Baack Leon Durivage Date 8 16 85 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING TRY OUT 12 LDX ST I2 OUT TIMER BLE GF 5 branch if asleep off 0 DEX STX ST I2 OUT TIMER DEC GF TIMERS BRSET FLAGSS NO GF BIT STROBE WDOG if GF 55 LDAA GF RESTRN get restraint timer BLE RETN TIMR 15 asleep or null bypass DECA decrement STAA GF_RESTRN_TIME save value CEX RETN TIMA EQ LOX RETN TIME get restraint timer ELE LONG TIMR
33. 685 710 731 761 813 853 914 974 1015 1066 1096 1219 600 731 914 1030 1065 1096 1143 1219 1280 1370 1463 1523 1600 1644 1 I 630 AMP 767 960 1081 1119 1152 1199 1280 1344 1439 1536 1598 1679 1728 1 800 974 1219 1372 1421 1462 1524 1626 1706 1829 1950 2030 2133 2194 1 1200 AMP 1462 1829 2057 2131 2194 2285 2437 2540 2742 2925 3045 3200 3290 1 1250 DW 1524 1905 2144 2221 2285 2380 2540 2666 2857 3047 3173 3332 3427 1600 1949 2437 2748 2842 2924 3047 3252 3413 3656 3900 4060 4265 4392 I 2000 AMP DW 2437 3047 3430 3553 3656 3808 4064 4265 4570 4875 5077 5332 5485 I 2500 DW 3047 3808 4289 4441 4570 4760 5081 5332 5712 6093 6345 6732 6925 I 3000 AMP DW 3656 4570 5146 5329 5485 5712 6096 6398 6856 7313 7614 7998 8227 X 3200 AMP DW 3900 4875 5490 5684 5850 6094 6503 6825 7313 7800 8122 8532 8774 I 4000 4975 6094 6862 7106 7313 7617 8129 8532 9142 9750 10153 10664 10970 12 TO PHASE DW 578 value to make current conversion usable w GF PRETO RETO SESE WEES GUESS This is a first guess table for the seed for the square root routine GUESS 08 139 194 1DE 521 5258 528 2BD S2EA 315 33D 364 389 3AC 3 3EF 40F 42 440 46A 487 54 54 5409 4F3 550 5525 53 556 556 5585 559 5583 559 552
34. A4 77 181 25D 371 44E 52B 6D A4 F7 181 25D 371 530 7C8 LONG TIME 97 RATIO TAELES eee ed 104 255 234 365 574 836 1046 1256 THIS ROW AND 104 158 237 370 582 852 1275 1729 THIS ROW MUST CONTIGUOUS e de dede de de e dede e den LT DEL TBL LT LE LT ME LT NE LT PE 17 5 EQU LONG LONG LONG LONG 5161217 10777994 16203159 25245100 39712206 57796089 72263195 86730301 7161217 10777994 16203189 25245100 39712206 57796089 72263195 86730301 7144197 10760974 16186138 25228080 39695186 57779069 72246175 86713281 7076116 10692893 16118058 25159999 39627106 57710988 72178095 86645201 7114412 10731188 16156353 25198295 39665401 57749284 86683496 130084815 5 089 928 151 152 LT DS LONG 6999526 10616302 16041467 25083409 LONG 39550515 57634398 86568610 129969929 1 15 IS THE TABLE FOR CONVERTING RAW A D TO CURRENT VALUES Tables have been adjusted 3 high for low communication values Single bit accuracy be found by dividing table value 256 Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING CURRENT CONV TBL EQU 1 20 244 303 342 354 363 380 406 416 457 487 507 533 549 609 250 DW 304 380 429 444 456 475 508 533 571 609 634 665 679 761 400 Dw 487 609
35. Data Byte 5 Last Phase B Current Low Byte Packet 6 0 1 1 0 Data Byte 1 Last Fault System Status Byte Data Byte 2 Last Phase C Current High Byte Data Byte 3 Last Phase C Current Low Byte Data Byte 4 Last Ground Fault Current High Byte Data Byte 5 Last Ground Fault Current Low Byte Packet 7 0 1 1 1 Data Byte Long Time Memory Ratio Data Byte 2 Phase A Unbalance Data Byte 3 Phase B Unbalance Data Byte 4 Phase C Unbalance Data Byte 5 Software Version Identifier Byte Accordingly the microcomputer 120 transmits infor mation in four substantive classes The first class consti tutes trip status information as set forth in the first byte of each packet The second and third classes involve current measurement information the second class in cluding current measurement information on each line 106 as set forth in packets 0 and 1 and the third class including the maximum current status information as set forth in packet 2 The last class of information relates to the present configuration of the tripping system and is contained in packets 3 through 7 H Appendices The attached appendices respectively illustrate the preferred manner in which the microcomputer 120 of FIG 1 and the display processor 316 of FIG 3a may be programmed to implement the system as set forth above in the preferred embodiment TABLE 1 SAMPLE TIME I t 16 SQUARED SUMMATION X90 0 SQUARED SUMMATION
36. E presser ALL INTERRUPTS EXCEPT RESET AND TIMER 1 JUMP TO THIS POINT ANY INTERRUPTS OTHER THAN RESET AND TIMER 1 ARE ERRORS teeeseeees iNIT 1 uCONTROLLER REGISTERS SET UP LDX REGSTART x to point at bottom of registers LDAA 4589 set softdog to 65 mSec reset time STAA A D section clock monitor wait 100uS before doing A D LDAA 4528 5 HPRIO X CLR PORTD X LDAA 53 STAA DDRD X set 1 as highest priority interrupt clear PORT D output bit enable PORT D as output to charge MEM DEL CAP amp turn on DESENSE p LDAA 503 Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING STAA vp parallel I O registler not used in expanded LDAA 4530 for 9600 baud LDAA 550 STAA 5 1 set for 9 data bits 1 start amp 1 stop bit LDAA 508 STAA SCCR2 X enable transmit mode on the sci LDAA 1 sets SPI for master idle high data true on STAA SPCR X 125X z set up SPI but don t turn it on 00 clear to shut off i shut down portA outputs for successful output compares STAA set any bits in reg 1 for compares qedex des dedo de shut down output compares for thru TOCS STAA
37. Number ms Amps Amps Amps Binary Binary Binary 1 0 0 0 00 0 00 000 0 0 0 2 0 5 18 74 351 12 351 12 48 2304 2304 3 10 36 81 1355 16 1706 27 94 8836 11140 4 1 5 53 58 2871 10 4577 38 137 18769 29909 5 20 68 45 4686 05 9263 42 175 30625 60534 6 2 5 80 90 6545 08 15808 51 206 42436 102970 7 3 0 90 48 8187 12 23995 62 231 53361 156331 8 3 5 96 86 9381 53 33377 16 247 61009 217340 9 4 0 99 80 9960 57 43337 73 254 64516 281856 10 4 5 99 21 9842 92 53180 65 253 64009 345865 11 5 0 95 11 9045 09 62225 73 243 59049 404914 12 5 5 87 63 7679 14 69904 87 223 49729 454643 13 6 0 77 05 5936 91 75841 78 196 38416 493059 14 6 5 63 74 4063 10 79904 88 163 26569 519628 15 7 0 48 18 2320 87 82225 75 123 15129 534757 5 089 928 21 22 TABLE i continued TIME 19 0 SQUARED SUMMATION I t Kt SQUARED Number ms Amps Amps Amps Binary Binary 16 7 5 30 90 954 92 83180 67 79 6241 17 8 0 12 53 157 09 83337 75 32 1024 18 8 5 6 28 39 43 83377 18 16 256 19 9 0 24 87 618 46 83995 64 63 3969 20 9 5 42 58 1812 87 85808 52 109 11881 21 10 0 58 78 3454 91 89263 43 150 22500 22 10 5 72 90 5313 94 94577 37 186 34596 23 11 0 84 43 7128 89 101706 26 215 46225 24 11 5 92 98 8644 84 110351 10 237 56169 25 12 0 98 23 9648 88 19999 97 250 62500 26 12 5 100 00 10000 00 129999 97 255 65025 27 13 0 98 23 9648 89 139648 86 250 62500 28 13 5 92 98 8644 85 148293 71 237 56169 29 14 0 84 43 7128 91 155422 62 215 46225 30 14 5 72 90 5313 96 1
38. POINT TO 10005 DIGT LEFT SIDE CALL LEFT CHARACTER LEFT SIDE DATA AND STORE RT 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 5 RATING CALCULATE AMPERE RATING RATING 5 5555555555555555555555555555555555555555555555555555555555555555555555555555 UP THE RATING PLUG AND SENSOR VALUES 00 801 02 03 XADR TEMPI 0 SKAEM CALL RATI LADR SKAEM CALL RATI LHL LTS LADR CLTS SKAEM CALL LADR SKAEM CALL RAT XADR TEMPI SKAEI OIK LADR 90 GJMP 01 GJMP ADOR GJMP 02 GJMP SID3 GJMP GJMP ADORA GET SENSOR ID REG SENSOR RATING PLUG POINTER 504 5105 506 5 07 08 909 5010 5011 DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP DES GJMP GJMP 05 ADDRS 906 6 807 ADDR7 08 ADORG 509 ADORO 010 ADDR1O 011 ADDR11 ADDR13 ADORI2 199 5 089 928 AMP RATING USING RATING PLUG AS OFFSET POINTER Ct RATING CL RATING BTI CL RATING BTI CL RATING BTI CL RATING LHU CL RATING CL AMP RATING LOW NIBBLE _ AMP RATING LOW NIBBLE RATING L
39. STAA ST RETN TIMER save it to retention timer so So t t Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING d LDD 5 reset value STD ST I2 OUT TIMER set to reset STAA SC RESTRN TIMER the restraint timer LDAB STDELSW read the delay switch ANDB SW POS mask off bits not wanted 2 3 maximum 1 2 out position BLS ST LONG TIME 172 out so branch BSET ST FLAGS DOUBLE ST 12 BIT set flag to double first 172 valu JMP 15 MEM ACTIVE 790 GF initialization ST LONG TIME EQU LDX 5 FIXED DEL GET START LOCATION OF FIXED DELAY TABLE STDELSW SWITCH ADDRESS LDAA 8 MULT BY 8 FOR OF ENTRIES PER ROW BSET FLAGS WRD_ALIGN_BIT 11 WORD BOUNDARY JSR TBL INDX CALL INDEX ROUTINE 0 LOAD TIMER VALUE FROM TABLE SUBD 6 subtract INIT time for ST STD ST I2 OUT TIMER save to timer 2 BSET ST 12 OUT TIMER T INACTIVE put timer to sleep 15 MEM ACTIVE EQU 5 QUEUE 5 SECOND GF RETENTION TIMER G F MEMORY NOT ACTIVE J ETE IE IE E eoe ener This section sets up Short Time to take into account the time to initialize the trip unit when powering up nto a fault reset timer is started to run normal times after 250 mSec ERE dede od RR UU OR HON
40. STACK IS SEI 5 PEAK LDX PHASE I JSR 1 CONVERSION 06 SC 8 WAIT FOR ATOD READ WAZT FOR HI EQU check if phase max check if B phase max is gt so branch 7B is phase max check if C phase max previous is gt so branch is phase max get multiplier it save max current of trip TRIPPING SO CLEAN UP TEE STACK stack pointer to IX 9 bytes on stack so load add 9 to stack pointer put it back in the Stack Pointer CLEANED UP AT THIS POINT NOW GO TRIP set So don t interrupt tripping spoint to value point to storage 280 convert to xmit format stripping so leave don t finish A D TO COMPLETE CUR PHASEA B or C ARE ONLY VALUES USED OUTSIDE OF INTERRUPT L PEASE 4 HI PHASE ARE USED AS INTERMEDIATES IN INTERRUPT eereees ADRI REGSTART PHASE HIGH GAIN A D 5 save value for check in trip routine 5 6 BLS USE HI PHASEA suse the low gain A D value for 1 2 summation LDAA PEASEA LDAB 6 STD CUR JMP DO PHASEA SUMMATION 90 do 172 summation USz PHASEA EQU CLR CUR_PHASEA STAB CUR PHASEA 1 PUT IN CUR ATOD PTR TABLE DO PHASEA SUMMATION EQU THIS POINT EITHER LOW OR HIGH GAIN HAS BEEN STORED CUR PHASEA FOR USE TBA move low byte to for
41. TABLE POS saved table position LDD ST PEAK get latest ST peak CPD to pu tbl BLS SHORT NOT INSTALLED table no pick up clear flac if in STPU turn on super desense BSET FLAGS SUPER DESENSE turn super desense BRA SET DESENSE FLAG turn on normal flag pi x k WE GET HERE WE DO NOT HAVE SHORT TIME PICK UP SHORT TIME INSTALLED BCLR 51 FLAGS ST PU BIT WE DON T HAVE PU SO CLEAR IT BCLR SC PU Gr PU 807 pickup so clear all phase pickups 1 MOTOR PROTECTION WILL CALL AT TEIS POINT TO CLEAR OF 5 5 RETURN CLEARED EQU 5 LDD ST PEAK GET PEAK OF LAST 11 mSzC BRSET INST FLAGS INST OFF BIT CHECK FOR 3XP IF INST OFF DON T CHE LDX INST TASLE VAL get inst PU value i turn Desense ON or OFF as appropriate via the ST PEAK value determined 1 in the MAIN task This gives the desense a less reactive appearance 0 compare to Inst pick up value BLO CHECK FOR 3XP check for norm desense BSET GF FLAGS SUPER DESENSE turn on super desense BRA SET DESENSE FLAG turn on normal flag CEZCK FOR EQU BCLR GF_FLAGS SUPER DESENSE if lt 6xP turn super desense of DESENSE THRESHOLD compare to Desense threshold BLO CIRI DESENSE if below jump SET_DESENSE FLAG BSET GF FLAGS TURN ON DESENSE turn on desense JMP CLR PK VALS 289 clear ST peaks for next llmS values
42. max GF run normal square GF gt max allowed get max allcwed SENSOR 0 FROM TEMP ADD SENSOR OFFSET INTO INDEX igez max Gr 2 Date 8 16 89 SERIES III ELECTRONIC TRl SYSTEM SOFTWARE LISTING STD EQU LDAB MUL STD EQU LDX JSR NORM ADD ACCUMUL 8 RESULT ACCUMUL 8 GF PEAK RESULT ACCUM ACCUM4 ADD suse result as holding reg temp in use alread go add to G F A GF value move it to ACCA square it double now has GFI 2 suse result as holding temp in use alread sADDFESS OF GF ACCUMULATER sADD GF I SQUARE TO THE GF ACCUMULATER BRCLR GF FLAGS DOUBLE I2 BIT CHECK SPEC 12 TRIP BCLR FLAGS DOUBLE 12 BIT LDD SPEC I2 TRIP RESULT ACCUMUL 8 EQU clear double bit saved value back sdouble 1 2 value for init time A 2 NOW CALCULATE THE INDEX INTO GF 150 DELAY TABLE TO TEST FOR TRIP JSR CMPB BHS LDAS EQU SUBB BNE CLRA LDAB BEQ LDX MP EQU LSRS ADDB LDAA MUL EQU ADDD XGDX EQU GOCD_BRKR ADD DELSW FREAD DELAY VALU AT THIS POINT LDAB ANDB SUBB READ BREAKER 9 4508 GOOD ERKR 4508 5 4508 NOT A TEMP ADD DELSW 4 2500 TRIP TBL READ DELAY VALU 16 6 I SQ DEL GFDELSW SW POS 08 igo read the breaker tyre smask off bit 4 if PE or gt value is good set for
43. subtract below Brkrs PE breaker type is 8 set top byte of to 0 get sensor size sbrk is PE2000 trip table for 2500A PE SIX has start of 172 in table divide by 2 for 0 1 2 values sensor masked brkr type 16 bytes row entry row offset for brkr 6 sensor table location move to IX POINTS TO THE CORRECT ROW OF THE CORRECT 172 IN DELAY TABLE iget the del switch setting smask off bit 0 high nibble for GF 172 table 5 089 928 109 110 1518 valves are 4 bytes so shift left 2 ABX location to row pointer 2 now holds the location of the GF I 2in trip FOR GFTRIP EQU 6 ACCUM get accumulator location JSR DEL WORD go compare accumulator to trip value CMPA 00 compare BGE GF_TRIP zif positive trip RTS return from routine GRO UND FAUL T TRI p CALLED From any Ground Fault routines that are allowed to generate Ground Fault trip 74 4 4 7 7 t se t se RETURNS Doesn t trips the breaker Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 III ELECTRONIC SYSTEM SOFTWARE LISTING USED amp IX RESTORES NOTHING 1111111111 UR Sf TRIP EQ SEI NO MORE INTERUUPTS P
44. 0 branch CPD 5051 22 SECONDS LT GT 22SECS YES IT S ABOVE 22 SECONDS BLO CONT LT DEC lower so dec by 1 2 16 LDD LT ACCUM 2 GET LOW WORD OF LT ACCUM BNE LT GT 22SECS WORD S051C LOW WORD gt 0 JMP CONT DEC low word 0 EI WORD IS ZERO SUBTRACT 1 FROM LOW WORD OF 4 BYTE ACCUM IF WORD 0 amp LOW gt 0 LDD LT ACCUM 2 GET LOW WORD OF 4 BYTE ACCUM BNE LT SUB 1 NOT ZERO YET BCLR LT FLAGS LT GTZ BIT CLEAR LT ACCUM GT ZERO BIT RTS LT 6081 082 1 SUB ONE STD LT ACCUM 2 PUT IN LOW WORD OF 4 BYTE ACCUM BNE LT_RETURN NOT ZERO FLAGS LT GT2 CLEAR LT ACCUM GT ZERO BIT RETURN EQU RTS Z2ERO WORD RETURN CONT LT DEC LDX 1 ACCUM SET X TO ADDRESS OF LT ACCUM JSR SUB 2 16 DEC LT ACCUM BY 2 16 RTS DONE RETURN TO EXEC LT 225 5 EQU SUBTRACT 2 19 FROM LT ACCUM LDD LT ACCUM LOAD HI WORD OF LT ACCUM LSRD DIVIDE BY 2 LSRD DIVIDE BY 4 LSRD DIVIDE BY 2 2 19 STD TEMP 2 16 IN TEMP LDD LT ACCUM 2 get LT ACCUM SUBD TEMP Subtract LTA 2 19 STD LT_ACCUM 2 Save TO LT ACCUM DONE W SUBT carry needed so done LDX LT ACCUM SET X BACK TO LT ACCUM DEX STX LT ACCUM X BACK TO LT ACCUM DONE W SUBT Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIk SYSTEM SOFTWARE LISTING RTS Itt eee SUB 2 16 SUBRO
45. 0 check BEQ LAST_A_ADD MUL smultiply low byte by low byte ADDD RMS SUMSQ 1 add double to low 16 bits Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING STD RMS SUMSQ 1 WORD OK LDX RMS SUMSQH 1 INX STX RMS SUMSQH 1 EZ WORD OK LDAA CUR 1 LDAB CUR BEQ A 1 SQUARE DONE MUL 1510 save it 1 carry set increment the high byte save it low byte get high byte for 0 check if high byte 0 we s done result is shifted to multiply by 2 same as 2 multiplies amp an add ADDD RMS_SUMSQE_1 1 STD RMS SUMSQH 1 1 LAST ADD INC RMS 504508 1 LAST A ADD EQU LDAA PHASEA BEQ SQUARE DONE add low high to middie 16 bits save it Carry was set increment the high byte get high byte if 0 we re finished move to ACCB 137 ADDD STD RMS SUMSQE 1 SQUARE DONE 5 089 928 138 multiply for last value to high 16 bits store back to accumulator 27 AT THIS POINT PHASE 172 SUMMATION IS FINISHED AND 5 IS STARTED LDAB ADR2 REGSTART STAS HI_PHASES QPB 5 6 BLS USE EI GET PHASE B HIGH GAIN A D save value for check in trip routine 1 USE LOW GAIN PHASEB SQUARE amp ADD TO TEE SUM OF PHASES SQUARES LDAA PHASEB 80 do 172 summati
46. 11 output compare 2 5 are not used shut down input captures for thru TIC4 xxxii 5 089 928 35 36 STAA 2 input capture LDAA 580 STAA TMSK1 X allow only timer 1 output compare interrupts LDAA 1 read the interrupt flag register STAA TFLG1 X rand store to clear any pending timer interrup PRR RARER Re mask off all TFLAG2 interrupts tfe fe de dede de de d CLR TMSK2 X mask off all TFLG2 interrupts CLR TFLG2 X turn off unwanted interrupts LDAA 580 PACTL X PortA bit 7 is set for output pulse accum o LDS END stack at end of RAM FINISH SETTING REGISTERS UP HERE oe oe i SZT UP FOR LOW GAIN CHANNEL ZERO SET A D TO 30 HIGH GAIN amp GROUND FAULT SET A D TO 34 FOR LOW GAIN amp MEMORY DELAY CAP BSET ADCTL X 34 a conversion for lst reading w MEM DELA FOR PRODUCTION TEST DESIGNATOR HERE RATING PLUG DESIGNATOR OEH LDAA RATING PLUG R value ANDA 1 mask RP designator bits amp PROD TEST DESIGNATOR compare to prod test value BNE CONTINUE INIT 1 2 0 JMP PRODUCTION TEST go run production tests EQU CONTINUE INIT THIS CHECKS TO S Te T 4 te te EE IF GF MEMORY RETENTION IS STILL LIVE If this point is reached frcm softdog error or GF is off all mem
47. 8 8c ORG DB 50H 020 052H 080H 02 60H DB O80H 000H 0 0 DB 032 046H 048H 53H 057H 05DH D64H 68H 06 DB 070H 07DH AMP12 LAMT RT ISSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 5 MERGE MERGE TWO SEVEN DATA BYTES 5 5 ISSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS MERGE LADR TLMSN LOW BYTE MSN RAR 4XRAR RAL BIT 0 2 SHIFT TO 1 3 RAR RAR XADR TLMSN SHIFTED LEFT NIBBLE RC THMSN ACC HIGH BYTE MSN RAR ROTATE RIGHT THRU CARRY THMSN SAVE ROTATED NIBBLE LADR THLSN HIGH BYTE LSN RAR ROTATE RIGHT THRU CARRY XADR THLSN SAVE ROTATED NIBBLE TLMSN ACC LOW BYTE MSN SHIFTED LEFT RAR CARRY INTO LMSN XADR TLMSN 5 089 928 179 180 ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT AMP13 s ASABSASAASASAAABAASASAASASASLABAGAASAASAAAARAAAARALAGAA ORG 3COH 080H 020H 4 022H DABH 02EH 050H 000H 032H 088H DB OAOHO40H0D DB 04 057H O5BH O5DH 061H 068H 06DH 07 5H D7DH 082H 088 DB O8CH O9CH AMP13 LAMT RT 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 5 TRANSFER TEMPORARY DATA INTO PERMANENT LOCATIONS i SSSSSSSSSSSSSSSSSESSSSSSSSSSSSSSSSSSSSSSSESSSOSSESSSSSSSOSSSESSESSSSSSSSSSS
48. ACCUMULATOR VALUE THE LONG TIME DELAY SWITCH IS USED TO LOOK UP THE CORRECT MULTIPLIER FROM TABLE LOCATION IN IX TEE MUL 16X16 SUBROUTINE IS USED FOR THE MULTIPLICATION THE RESULT IS PUT INTO A 4 BYTE RAM LOCATION CALLED RESULT CALLED WITH SET FOR EITHER LT OR FLC REBUILDING TABLE M 4 4 VELEELPEEEIEEEE RESULT USED 1011100 P EL DELL ETE L EE E E NH NS CALC LT ACCUM EQU LTDELSW read the delay switch ANDB SW POS off invalid ABX to index JSR READ SW find if brkr SE or PB CMPB 508 0A SE BLS READ RATIO correct so read ratio 16 get offset for next row ABX add it to index READ RATIO EQU 5 1 X REGISTER IS NOW POINTING TO THE PROPER TASLE POSITION z points to A D MEM DELAY CAP VALUE JSR 16 16 FIGURE MEM DELAY DIGITAL mem ratio drops the least significant byte so adjust the result byte to the left multiply by LDD RESULT 1 LOW BYTE HIGH WORD STD RESULT STORE IT TO HIGH BYTE HIGH WORD LDD RESULT 3 GET LOW BYTE LOW WORD EXTRA BYTE STD RESULT 2 STORE TO LOW WORD DATA HAS BEEN SHIFTED RATIO 1 memory ratio LDAA 564 get 100 into MUL smultiply for percent STAA LT MEM RATIO store byte for transmission RIS p eewre useatrseustesses repHASE UNSALANCE w e waxd erwttte
49. CHECK SUM isave result to checksum buffer DO PARITY EQU Temp holds the number of high bits for parity generation ACCB is set to 9 since all parity checking is done after checking for 0 CLR scleaz location for checksum counting clear carry for parity testing LDAB 09 set for 9 shifts PARITY RORA put bit zero in carry bit shave we done all 8 bits BEQ PARITY SET ACCS 0 on Sth shift so parity is done PARITY this bit is a zero INC TEMP this bit is one JMP X PARITY 290 211 8 bits PARITY SET EQU Parity bit is set or cleared here depending on the 0 bit 02 TEMP Bit 0 1 set parity bit bit 0 0 clear parity bit LOX REGSTART 26811 io base address 1000 BRCLR TEMP 1 CLR P is bit zero a 0 BSET SCCR1 X 40 55 set parity bit on Su TRANSMIT CIR EQU BCLR 5 1 540 bits are even clear parity bit TRANSMIT EQU data should be all set up by here so send it to SPI amp SCI transmit registers 5 5 read SCI status register STAA SCDR X put data sci data register amp clr TDRE 5 089 928 129 130 SPSR X SPI status registe SPDR X read data to clear SPIF flag SPI finished STAA SPDR X store to start transmission SERIAL DONE EQU RTS eereeeeTETS ROUTINE RESETS THE INST TIMER 100 mSEC AFTER AN INITIAL 10025 CALLED When the INST RESET T
50. CLEAR bit set if restr line is lo LDAB GFDELSW T READ GF DELAY SWITCH ANDB MAX SW POS OFF 0 06 CHECK FOR 172 IN DELAYS BLS CLEAR GF PEAK SWITCH lt 6 DON T DO GF I 2 IN JSR 150 CALL GF I 2 DELAY ROUTINE CLEAR GF PEAK EQU cox JSR CHECK GF 13MS GO IF NEED TO CLR GFPU 64 mSEC CEECKS PES ESE SS Four 64 mSec timers are run here One timer for each phase one for Long Time pick up check routines After each phase calculates its RMS value flag is set to do serial comm conversion and phase unbalance 5 ota 5 64 5 5 LDAA PHASEA RMS CURRENT A PHASE TIMER VALUE TEST PHASEA EQU 64 5 PHASE MS TIMER EXPIRED YET BLO TEST PHASEA 2MS GO SEE IF 2 MS RAVE EXPIRED SINCE A PHASE RMS SUBA 64 reset the timer STAA T PHASEA RMS save the reset timer Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING BSET LT FLAGS A PHASE CONV conv so set FLAG LDX 5 SUMSQR _ i location of the SUM 2 FOR CHAN 1 JSR AVG AVERAGE I 2 VALUE CHAN 1 LDD RMS SQROOT 50 ROOT FROM AVG ROUTINE STD PHASA SQRT LAST 64 MS SQ ROOT OF CURRENT FOR CEAN 1 JMP TEST_64MS CONTINUE MAIN EXEC LOOP TEST PHASEA 2MS EQU HAS 2 MS EXPIRED YET 8 HAS PHASE MS TIMER EXPIRE
51. HI WORD OF ST ACCUM RESULT IN ST ACCUM BRCLR ST FLAGS DOUBLE ST I2 CALCULATE_ ST_TRIP if double bit not set don t double 172 addition 5 089 928 97 98 BCLR ST FLAGS DOUBLE ST 12 before rerun 1 2 add JMP DOUBLE FOR INIT 760 double 1 2 accumulation CALCULATE ST TRIP LDX 45 150 DEL SET X REG TO ST I 2 DEL TABLE STDELSW SET Y REGISTER TO ST DELAY SW LDAA 432 MULT BY 16 SHIFT LEFT 4 BCLR FLAGSS WRD ALIGN SET FOR DBL WORD BOUNDARY REQUEST JSR TBL INDX CALL TABLE INDEX ROUTINE LDY ST_ACCUM 2151 COMPARE VALUE IN Y JSR WORD ST ACCUM TO DELAY TABLE CMPA 00 ST TRIP 5 ACCUM gt TABLE DELAY RTS RETURN FROM ST I 2 CODE MAIN REET H o R T T I M E TRI P 1 SE SG we te CALLED Frem any SHORT TIME routine that needs to generate a trir INST amp call the pertion of this routine that starts at DO SC TRIP to finish setting up historic data before jumping to GLOBAL TRIP 74 4 ta 4 Se 5s stored to EEPROM Se se t t Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIr SYSTEM SOFTWARE LISTING USED ACCS amp IX RESTORED NOTHING TRIPS BREAKER T v 2 e ee dec doe dee od deo
52. ILLEGAL OP FDB SOFTDOG INTERRUPT FFF8 CC FAIL INT FDB SOFTDOG_INTERRUPT FFFA CLOCK FAIL INT FDB SOFTDOG_INTERRUPT RESET FDB INITIALIZE END Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 APPENDIX SERIES TRIP UNIT ADD ON AMMETER MODULE USTING 12 21 88 ASSEMBLER NEC 5 75 DESIGNER ANDY HAUN SQUARE PART 48155 166 01 49449 e ORG OOH sINMALIZE THE SYSTEM ONLY DONE START UP sINTIALIZE MEMORY RESET LA OOH RI DLS GJMP LAI O8H _ INITIALIZE STACK POINTER TO TAMSP ST UP IN PHASE LAI OFH XADR OFT OPTIONS TO INVALID VALUE FORCING A AMPERE RATING UPDATE GJMP NITIALZE SYTEM ORG 10H SOFTDOG ROM VECTOR ADDRESS PSHHL PSHDE CALL TSR TIMER INTERRUPT SERVICE ROUTINE POPDE POPHL RTPSW 5 089 928 161 162 ORG 20H INTO S SERIAL ROM VECTOR ADDRESS CALL SSR SERIAL INTERRUPT SERVICE ROUTINE ORG 30H INT SWITCH ROM VECTOR ADDRESS PSHDE PSISR PHASE SELECT INTERRUPT SERVICE ROUTINE POPDE POPHL RIPSW E 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EEE EEE KEE KEKE EEE de de 8 amp ROM LOOKUP ROUTINE FOR LONG TIME SWITCH ENTER 715 amp amp E 1 7 1 1 7 1 7 1 1 1 1 EE KEKE EEE 1 1 1 1
53. JMP igo rotate data into RAM ROTATE DATA 5 089 928 75 76 CLRC clr carry to rotate a 0 into RAM ROTATE DATA ROL 0 rotate into RAM pointed to IY BCLR PORTD X SCL set the clock low DECB decrement bit counter BNE GET NEXT BIT not 8 bits yet so get next bit TEE ACKNOWLEDGE BIT IS SENT EERE BCLR PORTD X SDA data kline low BSET DDRD X SDA turn data to output BSET PORID X SCL set clock high to catch acknowledge INY increment the byte pointer RATIO compare to lst non hysterical byte BES GO STOP rif all bytes recvd send stop bit BCLR PORTD X SCL set the clock low BCLR DDRD X SDA return data line to an input JMP UNLOAD go get the next byte GO STOP BSET PORTD X SDA set data clk high for stop BSET SPCR X 40 turn SPI on again RTS all recalled so return READREADREADREADREADREADREADREADREADREADREADREADREADREADREADREADREADREADRERAD EZ WAIT RTS GENERATES A WAIT WHILE WAITING FOR E 2 ERASE TO TRIP This routine resets the microP onboard COP computer operating propperly CALLED With nothing preset to any conditions Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYST
54. LAST APEASZ GET LAST PHASE PEAK LDAB 6 get multiplier amp MUL multiply it Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING PHASEX6 COMPARE TO PEAK OF PHASE BLS TRY PHASE B RESULT lt SAVE VALUE BRANCH STD 5 6 zand store it PEASE EQU LDAA LAST BPHASE LAST B PHASE LDAB 6 i CPD 5 6 9 COMPARE PEAK OF PHASE BLS TRY PHASE C STD IF RESULT lt SAVE VALUE BRANCH se TRY PHASE EQU n il LDAA LAST CPEASE GET LAST C PHASE PEAK 6 CPD PEAK OF PHASE BLS FIND PEAK OF 1F RESULT lt SAVE VALUE BRANCH STD 5 6 FIND PEAK PHASES EQU d LDAA 00 STAA LAST APEASE STAA LAST BPEASE STAA LAST CPEASE Clear all last phases CLEAR LAST 2mSec PEAK CLEAR LAST 2mSec PEAK CLEAR LAST 2mSec IP XD 5 089 928 65 66 LDX PHASEX6 get 6x low gain input ACCA is left at 0 for phase max phase CPX PHASEX6 to phase BHS CHK_C_PEASE gt B so branch LDX 5 6 get B phase LDAA 01 for B phase max C EQU CPX PHASzX6 compare to C phase BES FOUND ST PEAK gt phase C branch LDX 5 6 get phase LDAA 02 set for C phase peak FOUND ST
55. OUT get value to turn on SC trip line STAA turn line on RETURNS Jumps to GLOBAL TRIP with historic data locations ready te 5 089 928 99 100 STAA TRIP FLAG 5 for trip outdicator display use BCLR LT TRIP CNT 40 cause of trip long time BCLR PU TRIP CNT 40 of trip phase unbal BSET SC TRIP 540 of trip short circuit BCLR GF TRIP CNT S40 of trip fault BCLR SOFT TRIP 540 cause of trip soft dog BCLR FLAGSS KILL WATCHDOG not a soft trip so clr kill bit DELAY_2MS iget 2 mS delay JMP VT CHECK GO CHECK TRIP VOLTAGE 2274 C H E c K S T 1 2 M S CALLED Every 12mSec to do Short Time peak function checks Square D Company ADE Group Jerry Baack Leon Durivage 8 16 23 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING No preset conditions are required for calling Motor Protection shares part of the same routine to clear its peak LRC values RETURNS Peak phase currents for all 3 phases are cleared ST is cleared GF desense and ST pick up are set or cleared as needed USED IX RESTORED NOTHING EERE EEE EER RERE EERE EERE EEE RENE TER EEE EEE CHECK ST_12MS EQU BRSET ST FLAGS NO ST BIT SHORT TIME NOT INSTALLED ST NOT INSTALLED JUST CLEAR STPU BIT DON T CHECK FOR PU LDX 65
56. Preferred component values are for example 10 K ohms for resistors 565 and 567 20 K ohms for resistor 569 19 6 ohms for resistor 573 10 ohms for resistor 575 0 033 microfarads for capacitor 577 part No LM124 for amplifier 579 and part No BS170 for IGFET 581 3 Providing System Power Power for the tripping system is provided directly from the current on lines 106 and current on any one of the lines 106 can be used This feature allows the trip ping system to power up on any one of the three phases and to be powered when a ground fault on one or more of the phase lines 106 is present The output currents which are induced by the trans formers 510 512 and 514 are routed through the recti fier bridges 516 518 520 and 522 to provide the current for the power supply 122 On the right side of the recti fier bridges 516 522 at lead 524 the output currents are summed and fed directly to a Darlington transistor 568 a 9 1 volts zener diode 570 and a bias resistor 572 Most of this current flows directly through the transistor 568 to ground to create a constant 9 1 volt level at the base of the transistor 568 Because it has a nominal emitter to base voltage Veb of about 1 0 volts the emitter of the transistor 568 is at approximately 10 volts The transis tor 568 will strive to maintain 10 volts across it from emitter to collector regardless of the current through 20 25 35 40 45 50 55 65 12 it
57. READ AND STORE ALL 3 LOW GAIN A D CHANNELS amp MEMORY CAP 5 TURN SPI OFF AND TURN DESENSE ON or OFF AS REQUIRED 6 RUN INSTANTANEOUS TIMER AND PICKUP 1 READ EACH PEASE OF HI GAIN ATOD COMPARE EACE PHASE TO TEE MAXIMUM HI GAIN VALUE OF HEX F6 TO SELECT HI OR LOW GAIN A D VALUE TO SUM INTO RMS SQUARED SUMMATION TABLE 5 Se a Se v Se va Sa ta Se Te e 8 READ THE GROUND FAULT ATOD VALUE 9 RESET A D HARDWARE FOR READING LOW GAIN CONTINUOSLY 10 TEST THE ONE MILLISECOND IF IS ON GOTO 11 ELSE GOTO 13 EVERY ONE MILLISECOND 11 INCREMENT ALL FIXED DELAY TIMERS BY ONE MILLISECONDS Se 12 GOTO 14 13 DECREMENT ALL VARIABLE QUE TIMERS ONE MILLISECOND 5 089 928 131 132 14 STROBE HARDWARE WATCHDOG OFF SET PORT LOW 15 TURN SPI ON 16 RETURN FROM TIMER INTERRUPT TTtTYTT SEYESSTER TETETERTETETETERTtUUTTOTETESTYT t Y INTERRUPT P LDX amp REGSTART 5 6811 io base register address Square D Company ADE Group Jerry Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING LDAA 1 release all current interrupts STAA TFLG1 X 1 RESET THE 500 USEC TIMER LDD TCNT X get timer count ADDD 970 970 Susec 30 usece 500us
58. Register 3 Timer Output Compare Register Timer Output Compare Register Timer Output Compare Register Timer Output Compare Register E d LISTING Timer Output Compare Register 5 Timer Control Register 1 Timer Control Register 2 Main Timer Interrupt Mask Reg 1 Main Timer Interrupt Flag Reg 1 Timer Interrupt Mask Reg 2 Timer Interrupt Flag Reg 2 Pulse Accumulator Control Register Pulse Accumulator Count Register SPI Control Register SPI Status Register SPI Data Register SCI Baud Rate Control Register 5 Control Register 1 SCI Control Register 2 SCI Status Register SCI Data Register A D Control Status Register A D Result Register 1 Result Register 2 A D Result Register 3 A D Result Register 4 System Configuration Options 5 089 928 25 26 COPRST EQUAL 3A ARM Reset COP Timer Circuitry EQUAL 3B EEPROM Programming Register BPRIO EQUAL 3C Highest Priority Interrupt and Misc INIT EQUAL 30 RAM and I O Mapping Register 5 EQUAL 3E Factory Test Register CONFIG EQUAL 3F Configuration Control Register usable only in bootstrap mode PAGE Wow X X UR x SYSTEM CONSTANTS WHICH CAN CEANGE DURING DEVELOPMENT de dede de dece e de dede dee dede ye de oie dee e ie fe eee de e e ede de e e de od ode e e e d e deem
59. STD RMS SUMSQH 3 store back to accumulator C I SQUARE DONE EQU Read the Ground fault data FLT EQU LDAB ADR4 REGSTART GET GROUND FAULT A D in low byte Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP 5 5 SOFTWARE LISTING BRCLR GF_FLAGS SUPER_DESENSE NORM GF read A D as normal if clear LSRB 2603 shift LSRB rights to divide LSRB result by eight NORM GF EQU STAB GF save new value for trip use CMPB CUR GF 15 new GF larger BLS RESET LOW GN sold is larger so leave as is STAB GF new is larger so save it i RESET THE FOR THE LOW GAIN READ RESET_LOW_GN EQU LDAA 4534 GET VALUE SET A Ds FOR LOW GAIN APs STAA ADCTL REGSTART STORE TO ONBOARD TO DO CORRECT A Ds 1 TEST FOR ONE MS TOGGLE FLAG TO DECREMENT ALL TIMERS TEST FOR 1 5 BRSET IFLAGS ONz MSBIT ONE MILS IF 1mSEC BIT SET DO 1 MSEC STUFF BSET 5 MSBIT 5 1 mSEC ME DECREMENT_Q TIMERS 290 do the Que timers ONE_MTLS 5 BCLR IFLAGS ONE_MSBIT ARE 1 mSEC SO CLEAR 1 mSEC BIT INCREMENT ALL POSITIVE MS TIMERS FROM SMALLEST TO LARGEST INC T 2MS ST increment 215 ST timer INC 2MS GF increment 2ms GF timer INC 07 5 INCREMENT 17 mSEC TIMER INC 11MS INCREMENT 11 mSEC TIMER INC 12MS INCREMENT 12 mSEC TIMER INC 13MS 13 mSEC TIMER INC
60. The resistors 527 of the rating plug are connected in parallel with the resistors 529 and hence cause a decrease in the combined resistance Therefore the resistors 529 set the minimum current rating for the tripping system In a preferred arrangement for example the minimum cur rent rating corresponds to 40 of the maximum current rating The resistors 527 in the rating plug scale the voltages A read by the microcomputer This enables the resolution of the A D converter in the mi crocomputer to be the same in terms of a fraction of the rated current for both the minimum and maximum cur 5 089 928 13 rent rating Consequently there is not any sacrifice converter resolution for the minimum current rating In FIGS 6a and 6b the rating plug 531 is shown to include the resistors 527 mounted on a printed circuit board 587 A connector 588 is used to interconnect the rating plug with the remaining portion of the tripping system 100 When the rating plug is absent from the tripping system the system reverts to its minimum rat ing The rating plug 531 further includes copper fusible printed circuit links A B C and D which are selectively disconnected opened from a printed circuit connec tion 589 to inform the microcomputer 120 of the resistor values or the burden voltage current ratio in the bur den resistor arrangement 530 The printed circuit con nection 589 is connected to the 5 V signal via one of the co
61. amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER 4 amp amp D 11171 1 1 1 1 11 1 1 1 1 1 11 1 1 1 1 1 1 1 1 2 1 1 1 1 1 ORG MOH DB OE0H 98H 0FOH OSCH O50H 020 OE 4H DABH DB 078 030 00 OB 02 04 1H D49H DAEH 052H 057 DSDH O6 1H DB 069H 075H 11 RT 5 089 928 177 178 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 COMP COMPLEMENT THE BAR GRAPH DATA FOR SUBTRACTION 5 5555555555555555555555555555555555555555555555555555555555555555555555555555 ZERO ZERO VALUE sc THE CARRY FLAG TO ADD 1 LADR BRL BREAKER AMP LOW VALUE CMA COMPLEMENT ACCUMULATOR ACSC ADO 1 NOP XADR BRL SAVE COMPLEMENTED VALUE LADR ACC BREAKER AMP MIDDLE VALUE CMA COMPLEMENT ACCUMULATOR ACSC ADD CARRY NOP XADR BRM COMPLEMENTED VALUE BRH BREAKER AMP HIGH VALUE CMA COMPLEMENT ACCUMULATOR ACSC ADD CARRY NOP XADR COMPLEMENTED VALUE RT BAR GRAPH DISPLAY CONTINUED DES DECREMENT COUNTER TWICE CALL UNDERFLOW DONT TURN ON ANY BAR SEG S ALSSAAASSAAAASAASAAASAAASBAABBAAAABAASAAABABSAAASAAREAE ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT 12 amp 883 8 8 8 8 8 8 8 5 8888 8 8 88 8 8 8 5 8
62. are run LOAD 1 SEC TIMER 4 250 mS 1 Sec IS IT DUE YET 2 IS NOT DUE reset the timer save timer back to memory prepare sensor breaker for xmit buffer CHECK TIMR Q 21 no soft errors do timer igo decrement 10 min softdog timer IIEAXERXEVERAYUYY Ou T FERE TEST FOR ANY VARIABLE MS TIMERS THAT HAVE EXPIRED e e tte de e ie e e e e e e oe ie e ie e e e oe e e e n e ic e e e e e e e e de e ic ee e e de e de de de e e e e de ie e e e e de dee de de on JSR ALL TIMERS JMP FLOW 555555555555555555555 END MAIN check mSec timers CONTINUE MAIN EXEC FLOW EXEC FLOW 555555555555555555 STTTTTTTT THIS SECTION CHECKS mSEC TIMERS FOR ANY THAT ARE DUE and IX do not have any guaranteed values upon exit of this routine one lt T te CHECK ALL TIMERS EQU LDAA INST RESET TIMER BNE U RESTRAINED JSR INST TIMER RST R U RESTRAINED EQU LDAA SC_RESTRN_TIMER BNE HOLD ST JSR SC RESTRN OFF EOLD ST EQU LDAA ST RETN TIMER BNE ST TIM OUT JSR ST RETN TIMOUT ST TIME OUT EQU LDX 5 I2 OUT TIMER BNE 5 JMP 5 TRIP G TIMZRS EQU icheck GF timers here if any have timed Square D Company ADE Group Jerry Baack Leon Durivage ACCA amp IX are used to load timer values for timer due checks If any routines are called ACCB and IY may also be destro
63. at lead 524 The current at lead 524 is used for the power supply 122 which is discussed in the third part of this section On the left negative side of the rectifier bridges 516 520 negative phase current signals are carried through the burden resistor arrangement 530 and trip ping system ground and are returned to the rectifier bridges 516 520 through the power supply 122 This current path establishes voltage signals A B and C each referred to as a burden voltage for measurement by the microcomputer 120 via the gain circuit 134 In FIG 4 the signals A B and C are presented to the respective dual gain sections for inversion and am plification The gain circuit 134 of FIG 4 is shown with one of its three identical dual gain sections generally designated as 533 in expanded form The dual gain section 533 receives phase signal A Each dual gain section includes a pair of low pass filters 532 and a pair of amplifiers 534 and 536 The low pass filters 532 pro vide noise suppression and the amplifiers 534 and 536 reduce the signal magnitude by 0 5 and increase the signal magnitude by a factor of 3 respectively for the desired resolution This arrangement allows the mi crocomputer 120 to instantaneously measure these cur rent levels without wasting time changing any gain circuitry Preferred component values are for example 10 K ohms for resistors 541 543 545 553 and 555 4 75 K ohms for resistors 547 and 559 60 K ohm
64. carry BCC LOW if carry is low branch BSET PORTD X SDA carry is set so set data bit high 5 089 928 73 74 JMP DEC go Gecrement bit counter LOW EQU BCLR PORTD X SDA carry was clear so clear data bit EQU BSET PORTD X SCL set clock high to set data DECB decrement byte loop counter SET if not 0 go send the next byte BCLR PORID X SCL set clock low for acknowledge bit DDRD X SDA turn portd to input for ack bit LDAA 5 0 1 max wait SDA get mask WAIT FOR ACK EQU dec max time BEQ if time out leave ANDB PORID X read port d for ack bit BNE WAIT FOR sEEPROM not ready yet NO ACK EQU NOP BSET PORTD X SCL set clock line high for acknowledge bit INY increment IY to next byte MEM RATIO first byte thats not history data BLO LOAD NEXT BYTE get ready to write next byte 45 000 to address flag ELO SEND STOP if not address go send stop byte BCLR PORTD X SCL SDA set clock data lines low RTS return to address routine SEND STOP EQU BCLR PORTD X SCL SDA set the clock low to prepare for stop BSET DDRD X SDA 5 data line to output BSET PORTD X SCL set clock biut high BSET PORTD X SDA set data bit high to signal stop BSET SPCR X 40 turn SPI on again RTS return to calling routine SWRAIWRIWRIWRIWAIWRIWR
65. drawn from the current path but that 4 631 625 12 1986 et al 361 94 amount of power is below all fault levels and insuffi 4 680 706 7 1987 Bray 364 492 to operate the system 4 682 264 7 1987 Demeyer 361 96 4 689 712 7 1987 Demeyer 361 96 13 Claims 10 Drawing Sheets el 1 372 79373 317 375 W370 DISPLAY PROCESSOR INT Sheet 1 of 10 5 089 928 Feb 18 1992 U S Patent e 00 109412 123135 8350 061 E pol 83160dW02082IN QN AV1dS10 dL W901 0 I 161 13938 30V J831NI 024 31033 13538 8 901 or iw 238 6 4013133 1 9 Wels WVU gt 19 T 821 mE 1 1 Oh o NY lt AG zni AHONW3N W WNH3HI 914 5 305435 170 3 1112812 100 2 4 1931533 201 g bli 9017 SONY V 901 N 401 601 901 801 U S Patent Feb 18 1992 Sheet 2 of 10 5 089 928 Sheet 3 of 10 5 089 928 Feb 18 1992 1 5 Patent 918 0 1 4055320 4 4610 1SAH 0 5 Patent 376 INITIALIZE MEMORY 378 RESET TIMER WAIT FOR DATA READY FLAG STORE DATA AN
66. e e e e ee e e ci e e edd 13 MS TIMER CHECK ft se e e e le de c e e e e e e i de den CC computer operating propperly reset Ground Fault comm GF 172 in routine and GF Peak Detector clear run on th s time base ox HECK_13MS LDAA T 13MS GET 13 mS TIMER VALUE 13 IS IT TIME FOR 13 mS ROUTINES BLO CHECK 64 5 NO IT BAS NOT EXPIRED FOLLOWING CALLS ARE DONE 13 5 REREKEAREKKKEKKKKK SUBA 13 gt reset the timer STAA 13 5 save the reset timer JSR RESET COP IF GROUND FAULT IS INSTALLED go check if need to run I square GF routines BRCLR FLAGSS NO GF BIT CHECK ISQ CLR GFI CURRENT ground fault not installed so CLR GF 1 clear any current values JMP CHECK 64MS don t do GF code GF not installed NO GROUND FAULT PICK UP CONTINUE ON TO 17MS TIMER GF 150 EQU LDX SERIAL POINTER get location of byte last sent CPX GF_CURRENT did we send half of GF current BNE D SERIAL CONV if not OK to do serial conversion JMP TEST FOR GF PU 1 GO CHECK FOR GF PICK UP DO SERIAL CONV EQU JSR GF CONV igo do ground fault conversions for xmit BCLR FLAGS USE XS clear for correct conversions TEST FOR GF PU EQU BRCLR GF FLAGS GF PU BIT CLEAR GF PEAK no GFPU so branch 5 089 928 57 58 LDX REGSTART get onboard register addresses BRSET PORTA X GP RES IN
67. excessive amount of current through the links thereby causing the copper links to burn This is preferably performed before the rating plug 531 is installed in the tripping system Thus once installed the rating plug 531 automatically informs the microcomputer 120 of its resistor values and there is no need to adjust any settings or otherwise inform the microcomputer of the type of rating plug being used The microcomputer may adjust the values read from its A D converter by a predetermined scale factor corre sponding to the binary coded resistor value to compute actual current values which are independent of the resistor values in the rating plug 531 0 25 30 35 40 45 50 65 14 C Bi metal Deflection Simulation The microcomputer 120 is programmed to simulate accurately the bi metal deflection mechanism that is commonly used in processor less tripping systems This is accomplished by accumulating the squared values of the measured current samples that are sensed by the analog input circuit 108 The sum of the squared values of that current is proportional to the accumulated heat in the tripping system 100 To simulate the bi metal deflection during cooling the microcomputer 120 is programmed to decrement logarithmically the accumulated square of the current In other words during a sampling interval the accumu lated value A of I t is decremented by an amount proportional to A to account for the fact
68. gain circuit 134 amplifies each phase signal A B and C through respective dual gain sec tions from which the microcomputer 120 measures 5 20 25 30 35 40 45 50 55 60 65 4 each amplified signal using its A D circuitry By viding two gain stages for each signal and the microcomputer 120 can immediately perform a high gain or low gain measurement for each current phase depending on the resolution needed at any given time The analog input circuit 108 is also utilized to provide a reliable power source to the tripping system 100 Using current developed from the lines 106 the analog input circuit 108 operates with a power supply 122 to provide three power signals VT 9 v and 5 v to the tripping system 100 The power signal is moni tored by the microcomputer 120 through decoding circuit 130 to enhance system dependability System dependability is further enhanced through the use of a thermal memory 138 which the microcomputer 120 interacts with to simulate a bi metal deflection mechanism The thermal memory 138 provides an accu rate secondary estimate of the heat in the tripping sys tem 100 in the event power to the microcomputer 120 is interrupted The ground fault sensor 110 is used to detect the presence of ground faults on one or more of the lines 106 and to report the faults to the microcomputer 120 Using user selected trip characteristics the microcom puter
69. if asleep or null bypass decrement STX GF RETN save value LONG TIMA EQU LDX GF LONG 4 restraint timer ELE STROBE_WDOG 7 zif asleep or null bypass DEX decrement STX GF LONG save value pem GE TIMERS DECREMENTED THIS POINT tewuwrtr rew STROBE_WDOG LDX REGSTART BCLR PORTA X WATCHDOG set watchdog bit low SPCR X S5E turn SPI back on for transmissions RTI pervert eee eee ee ee ee OF SmSEC INTERRUPT ROUTINE dedere eode dde f wee rue rt FOLLOWING ARE TEE SOFTDOG ERROR TRIP ROUTINES CALLED From any interrupt except timer output comparel TOC1 and RESET_VECTOR RETURNS Doesn t return this routine reinitializes the trip unit to try to run code normally If 3 soft errors occur in 10 minutes the breaker will trip 85 Se Se Se ve 5e gt e Se gt e Q 5842564 Se Se t se me te gt USED ACCB IX RESTORED NOTHING FTDOG INTERRUPT EQU Sz1 set interrupts to stop any incoming LOX REGSTART get start of onboard regs LDAA TFLG1 X clear timer any interrupt STAA TFLG1 X now it s clear LDAA 4589 setup value for option register STAA OPTION X reset option register in case of trash LDAA SOFT DOG CN
70. in memory and the data ready flag is reset At blocks 382 and 384 the display processor utilizes a conventional conversion technique to convert the stored data to BCD format for display at the LCD display 322 of FIG 3a The data that is sent and dis played at the LCD display 322 is chosen by the operator using the switch 311 to sequence through each of the three phase currents and the ground fault current as indicated in the data that is received from the mi crocomputer 120 of FIG 1 At block 386 the display processor utilizes received data including the sensor identification the rating plug type and the long time pickup level to determine the percentage of rated trip current being carried on lines 106 of FIG 1 At block 388 the bar segments 324 and 332 335 of FIG are driven by the display processor in response to this determination From block 388 flow returns to block 378 Blocks 400 406 of FIG 3b represent a second inter rupt routine which the display processor may be pro grammed to execute in response to the depression of the switch 311 At block 400 of this second interrupt rou tine the display processor determines which phase or ground fault current the operator has selected by de 40 45 50 55 60 65 pressing the switch 311 At blocks 402 and 404 the display processor monitors its I O port to determine when the switch 311 is released and to debounce the signal received from the switch 31
71. line down so much that 2mSec pass before 10 4 realizes it is self restra ned TEST GF DELAYS 5 test for line active here active low mcus LDX REGSTART start of onboard registers BRCLR PORTA X GF RES IN GF RESTRN DELAYS if GFRI active use restrain DO NOT HAVE RESTRAINED DELAYS USE GF FAST TIMER DEC decrement fast timer DEC GF_FTINER decrement fast timer BGT EXIT GF gt timer 0 branch JMP GF TRIP eilse go trip 5 089 928 105 106 RESTRN DELAYS EQU VALUE IN ACCB FROM BEFORE TEST DELAYS IS USED SO CAREFUL 06 IF gt 6 1 2 DELAY EXIT SIT IS GF I 2 IN RUN ON 13mSEC TIME FRAME GROUND FAULT RESTRAINED FIXED DELAYS CHECK FOR ACTIVE TIMER LDD LONG TIME get Isg out timer 5 we even have timer BEO Gr SCEZD TIMER start a timer GF LONG TIME T INACTIVE timer up if asleep EXIT GF CONTINUE IN MAIN FLOW SCEED TINER EQU LDX FIXED DEL GET START LOCATION OF FIXED DELAY TAELE LDY GFDELSW GF SWITCE ADDRESS LDAA 8 MULT BY 8 FOR OF ENTRIES PER ROW BSET FLAGSS W3D ALIGN 1 WORD BOUNDARY JSR TEL INDX CALL INDEX ROUTINE LDX 0 LOAD TIMER VALUE FROM TABLE STX LONG TIME save to timer 4 JMP EXIT_GF GO BACK TO MAIN FLOW Eo 5 EXIT GF 5 RTS return to main motor routi
72. mSec RETURN TO TEST TOP start repeating tests again T_250MS clr timer PORTA REGSTART portA values complement portA values MAX_IDENT 04 STORE_INVERSE SC restr off don t mask 588 don t reset watchdog PORTA REGSTART store the inverse 157 RETURN TO TEST TOP JMP PAGE EQU MULTI TEST 5 089 928 158 go to top amp run again SUBROUTINES ARE EERE dedo omo dede MOVE TO SERIAL EQU LDAA STAA CLRA EQU LDAB 1510 LSRB STAB INX INY INX EQU DEC BNE STAA RTS DO_NEXT_BYTE X 15 OK 4 5 0 X 0 RATIO X IS OK TEMP DO NEXT BYTE 0 Y OF PASSES save it clr for rebuilding data load ACCB from pointer iformat data finish format save off sincrement pointers gare we pointing at memory ratio ino move to correct position count down move next byte done store high bits RETENTION TEST DONE HERE PRARALALALALALZIL ELLE LARS CHECK RAM RETENTION X CPD BNE DEX DEX CPX Square D Company ADE Group Jerry Baack Leon Durivage EQU 0 X RAM FAILURE 00 5 COMPARE DATA FOR GOOD VALUE 4 not 0 RAM was bad bottom of Date 8 16 89 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING BGE CLRA BRA RAM FAILURE EQU XGDX LSLD LSRB RAM REMEMBERS EQU STD RTS
73. power up the capacitor 153 becomes recharged through a diode 157 and a pull up resistor 159 Preferred component values for example are 365 K ohms for resistor 161 10 micro farads for capacitor 153 part No 74HC14 for Schmitt trigger 155 1N4148 for diode 157 and 47 ohms for resistor 159 Another important aspect of the tripping system 100 is its ability to transfer information between itself and the user This information includes the real time current and phase measurements on the lines 106 the system configuration of the tripping system 100 and informa tion relating to the history of trip causes reasons why the microcomputer 120 tripped the contactors 114 As discussed above the real time line measurements are precisely determined using the analog input circuitry 5 089 928 5 108 and the gain circuit 134 The system configuration of the tripping system 100 and other related information is readily available from ROM 128 and the user select circuit 132 The information relating to the history of trip causes is available from a nonvolatile trip memory 144 Information of this type is displayed for the user either locally at a local display 150 or remotely at a conventional display terminal 162 via remote interface 160 To communicate with the display terminal 162 the tripping system utilizes an asynchronous communica tion interface internal to the microcomputer 120 Using the 68 the serial communications interfa
74. system 100 is operatively coupled with a conventional electrical distribution system not shown through input and output restraint circuits 105 and 107 Signals received from the input restraint circuit 105 indicate that a downstream circuit breaker is in an over load or over current condition The output restraint circuit 107 is used to send signals to upstream circuit breakers to indicate the status of its own and all down stream circuit breaker conditions In general the trip ping system 100 will delay tripping of the contactors 114 when a downstream breaker is in an overload or over current condition assuming that the downstream circuit breaker opens and clears the condition Other wise the tripping system 100 should not delay tripping of the contactors 114 For further detail regarding re straint in restraint out electrical distribution systems reference may be made to U S Pat No 4 706 155 to Durivage et al Other circuits are used along with the above circuits to provide reliability and integrity to the tripping sys tem 100 For instance the microcomputer 120 utilizes the analog input circuit 108 along with a gain circuit 134 to measure precisely the RMS Root Mean Squared current on each phase of the lines 106 The accuracy of this measurement is maintained even in the presence of non linear loads The analog input circuit 108 develops phase signals A B and C that are representative of the current on lines 106 The
75. watchdog sallow interrupts MULTI TESTING DONE HERE 99 w 2 t dWiwk MULTI TEST EQU LDAA PACKET PTR BEQ TRY NEXT j VAL 1 0 don t corrupt data LDX PHASEA start of retrieval LDY RMS storage location start JSR MOVE TO SERIAL move raw A D data TRY NEXT VAL EQU E LDAA PACKET PTR packet for check DECA subtract 1 to check for data conflict BEQ PORTA if go read porta input LOX L_PHASEA retrieve from Loy PHASE RMS store to JSR MOVE TO SERIAL move raw A D data READ PORTA 5 LDAA PORTA REGSTART read port 5 IDENT to serial buffer CRECK FOR DESENSE EQU BRCLR 02 TEE GF 245 restraint is high CLR GF FLAGS restraint so clear LDX REGSTART get start of registers BCLR PORTD X GF DESENSE BIT OUT clr restraint line BRA DESENSE SET DESENSE THE GF EQU BSET GF FLAGS TURN ON DESENSE set flag for desense Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIv SYSTEM SOFTWARE LISTING DESENSE SET EQU TRY TRANSMIT EQU LDAA BLO CLR JSR JSR TOGGLE PORTA EQU LDAA CMPA BLO CLR LDAA COMA BRSET 2 ANDA STORE INVERSE EQU STAA T 2MS ST get 2 mSec timer 2 TOGGLE PORTA if lt 2 branch T 2MS T SERIAL T 250MS get timer 50 check for 50
76. 025H 027H D29H 2 D32H 036 DB 8 RT 15555555555555555555565555555555555555555555555555555555555555555555555555555 5 5 5 GETCON GET BCD CONVERTED VALUE ISSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS GETCON ST STORE CONVERTED VALUE XADR TEMPI CONVERTED VALUE XADR CONVERTED VALUE XADR 2 CONVERTED VALUE XADR BT2 CONVERTED VALUE XADR TEMP3 GET CONVERTED VALUE XADR BT3 STORE CONVERTED VALUE IES INCREMENT BCD VALUE RT E 1 1 3 1 3 1 1 3 31 1 1 1 3 2 1 3 1 3 1 3 3 3 1 1 1 1 1 AALALA 1 1 1 3 1 1 1 1 1 3 1 1 1 amp CALCULATE RUNNING CURRENT TIMES TEN amp amp 188 8 Rc BB c 8 B B R8 8 8 0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 TTA INITIALIZE MEMORY STORAGE AND COUNT VALUE LAI COUNT FOR TEN TAE LAI DATA TO LHL TEMPI DLS 2 DLS DLS sTEMP4 DLS TEMPS GJMP 2 E 1 7 1 1 7 7 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 EEE EEE EEE amp amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER amp x amp E 1 1 1 1 1 3 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 88 888 88 d T d d T 8 8 ORG 2COH 010H 096H 004H 012H 080H 098H OSCH 050H 020H 0 0 O1FH 027H 02BH D
77. 07 POINTTO CENTER ST STORE MASKED VALUE RC LADR BCD2 105 DIGT CALL CENTER CHARACTER CENTER DATA LHL 07H POINTTO CENTER VALUE FOR 10 CHAR ORL ST RESTORE BCD VALUE RC LADR BCD2 ACC 105 DIGI POINT TO 105 DIGI LEFT SDE CALL LEFT CHARACTER LEFT SIDE DATA AND STORE DISPLAY 1005 DIST RC RESET CARRY LADR BCD3 1005 LHU POINTTO 1005 DIGIT RIGHT SIDE CALL RIGHT GET CHARACTER RIGHT SIDE DATA AND STORE POINTTO VALUE 01H LADR OAH CENTER OF CHAR ANL MASK LOW 3 BITS OAH POINTTO CENTER ST STORE MASKED VALUE RC LADR 1005 DIGT CALL CENTER CHARACTER CENTER DATA POINT TO CENTER VALUE FOR 1005 CHAR ORL ST RESTORE BCD VALUE RC LADR BCD3 1005 DIGT LHL POINTTO 1005 DIGIT LEFT SIDE LEFT CHARACTER LEFT SIDE DATA AND STORE 5 089 928 197 198 DISPLAY 10005 DIGIT RC RESET CARRY LADR BCD4 10005 DIGI POINT TO 10005 DIGT RIGHT SIDE CALL RIGHT GET CHARACTER RIGHT SIDE DATA AND STORE ONE POINTTO VALUE 01H LADR CENTER OF CHAR ANL MASK LOW 3 BITS CENTER ST STORE MASKED VALUE RC D LADR BCD4 10005 DIGIT CALL CENTER CHARACTER CENTER DATA POINTTO CENTER VALUE FOR 10005 CHAR ORL ST RESTORE BCD VALUE RC LADR BCD4 ACC 10005 DIGIT OEH
78. 1 At block 406 the display processor executes a return from interrupt com mand It should be noted that the display processor 316 is optional for the local display 150 and therefore not required for its operation Further the local display 150 is itself an option to the tripping system and is not re quired for operating the tripping system B Current and Ground Fault Detection FIG 4 illustrates an expanded view of the analog input circuit 108 the ground fault sensor 110 the power supply 122 and the gain circuit 134 of FIG 1 Each of these circuits receives power from the three phase cur rent lines 106 Using this power these circuits provide signals from which the tripping system 100 1 deter mines the phase and current levels on lines 106 2 detects the presence of any ground fault 3 provides system power and 4 establishes its current rating 1 Determining Phase and Current Levels In FIG 4 the analog input and ground fault sensing circuits 108 and 110 include current transformers 510 512 and 514 that are suitably located adjacent the lines 106 for receiving energy from each respective phase current path A B and C Each current transformer 510 512 and 514 is constructed to produce a current output that is proportional to the primary current in a fixed ratio This ratio is set so that when the primary current is 100 of the rated current transformer size or sensor size the current transformer is producing a fi
79. 1 EEE 55 1 12 1 1 RAKE 5 amp amp 5 5 5 5 5 amp amp ROM LOOKUP ROUTINE FOR LCD DATA CENTER OF CHAR amp amp E 1 1 1 1 1 1 11 71 7 7 7 1 2 7 7 1 1 3 13 1 1 1 1 1 1 1 1 ORG 440H DCENT DB OAH O OEH OEH OEH 8 OEH O CENTER TO TEMP STORAGE LAMT XAM HL TEMPI RT 5555555555555555555555555555555555555555555555555555655555555555555555555555 5 5 5 BARON TURN ON APPROPRIATE BAR SEGMENTS 5 5 5555555555555555555555555555555555555555555555556555555555555655565555555555 BARON LHU 40 PERCENT SEGMENT LA ORL O DES GJMP BO2 RT BO2 DES DECREMENT COUNTER TWICE GJMP BON2 RT UNDERFLOW RETURN BON2 LHU 60 PERCENT SEGMENT OlH ORL SET BT O ST DES GJMP RT BO3 DES DECREMENT COUNTER TWICE GJMP BON3 RT UNDERFLOW RETURN 5 089 928 183 184 07H 80 PERCENT SEGMENT LAI OIH ORL BIT O ST DES GJMP RT BO4 DES DECREMENT COUNTER TWICE GJMP BONA RT UNDERFLOW RETURN BONA LHL O4H 100 PERCENT SEGMENT LAI O1H ORL 3 ST 55955895555595595595555555555555555958955555955995595559595555555555599555 i 5 5 RAT UPDATE BAR GRAPH VARIABLE LIST 5 5 45555555555555555555955555555555555555555555555555555555555555555555555555555 ST STORE THE NEW VARIABLE LAI OIH SET THE NEW VARIABLE CALCULATION FLAG XADR TEMPI RT
80. 120 determines whether or not the ground fault is present for a sufficient time period at a sufficient level to trip the contactors 114 The microcomputer 120 accu mulates the ground fault delay time in its internal RAM A RAM retention circuit 140 is used to preserve the ground fault history for a certain period of time during power interruptions The RAM retention circuit 140 exploits the built in capability of the microcomputer 120 to hold the con tents of its internal RAM provided that an external supply voltage is applied to its MOPDB Vstby input 141 This external supply voltage is stored on a 150 microfarad electrolytic capacitor 143 that is charged from the 9 volt supply through a 6 2 K ohm resistor 145 The capacitor 143 is charged from the 9 volt supply and clamped by diodes to the 5 volt supply so that the capacitor will be rapidly charged during pow er up The ground fault delay time stored in internal RAM becomes insignificant after a power interruption that lasts longer than about 3 6 seconds To test whether such an interruption has occurred the RAM retention circuit 140 includes an analog timer 149 having a resis tor 161 and a capacitor 153 establishing a certain time constant and a Schmitt trigger inverter 155 sensing whether the supply of power to the microcomputer 120 has been interrupted for a time sufficient for the capaci tor 153 to discharge Shortly after the microcomputer reads the Schmitt trigger 155 during
81. 2 to 4 byte gf accumulater BRCLR GF FLAGS DOUBLE 12 I2 TRIP BCLR GF FLAGS DOUBLE 121 BIT double bit LDD RESULT saved value back ADD_IT_AGAIN sdouble 1 2 value for init time 12 EU 5 150 DEL address of gf i 2 table in X GFDELSW saderess of gf delay switch Y LDAA 32 MULT BY 16 SHIFT LEFT 4 107 BCLR FLAGSS WnD ALIGN JSR SET TEL INDX IDY ACCUM JSR DBL WORD CMPA 00 BLT NO TRIP RETURN JMP GF TRIPS NO RETURN RTS 5 089 928 108 for double word boundary call table index routine Y points to gf accum comp gf accum to delay table not tripping so return 6 ACCUM gt DELAY TABLE return to main flow 2 t tev ua CODE FOR SENSORS gt 1600 AMPS BEGINS HERE eseseeees TRE FOLLOWING CODE IS THE SPECIAL JUMPED TO WITH ACCB HOLDING TEE 231111132 EEE E012 121 1111111 RESULT USED 150 Square D Company ADE 512 TEMP MAX Gr ATOD 4 0 GF PEAK NORM ADD 150 TEL TEMP 0 Group Jerry Baack Leon Durivage CODE FOR SENSOR gt 2000 AMPS SENSOR SIZE OF THE BREAKER convert to 0 2 4 6 for gt 2000A frame SENSOR 0E IN TEMP get location of max GF table add frame offset to location max GF value compare GF to max GF value zif lt
82. 2DH 2 034H 036H 041H 044H O46H O4EH 9995 AMPO LAMT E SCONTINUE WITH 10X RATING CALCULATION GAMP ADD NUMBER TO ITSELF FOR TEN 5 TAMP2 RC RESET CARRY 5 089 928 175 176 05 TEMPS GJMP TAMPI RT RETURN IF OVERFLOW ERROR amp ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER 10 amp amp ORG 300H DB 010HOD4H O0ECH OF4H 098 1 5 D20H OSEH 078H DB OE4HOABHOO 027H 030H 036H D38H D3AH O3DH O41H 044H D49H 51H 055 DB 057H 061H 10 RT CONTINUE WITH TEN TIMES CURRENT CALCULATION TAMP TAMP1 DES GJMP 2 ANOTHER ITTERATION RT CALCULATION DONE 15555555555555555555555555555555555555555555555555555555555555555555555555555 5 BAROFF TURN OFF ALL BAR SEGMENTS 5 5 ISSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS BAROFF 40 PERCENT SEGMENT LA OEH ANL RESET O ST 0 PERCENT SEGMENT OEH ANL RESET ST 07H BO0PERCENT SEGMENT ANL RESET ST O4H 100 PERCENT SEGMENT O ST RT E 1715171 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 121 1 1 1 1 1 1 12 8 9 12 1 421 121 1212 12 15 1212 8 i
83. 4 54 Se 5e te USED IX IY RESTORED NOTHING TEMP USED G0 ECU TOE EEE E RESULT USED oe ex wore ote md ALLA SESS L SSAA RARE DO CONV EQU LDAA GF peak of GF STAA 1 store for use CLR TEMP clear high byte amp GO DO IT peak current location LOX TO 5 conversion value location JSR 16X16 do conversion LDD RESULT 1 get result 256 for integer math STD TEM save for conversion to xnit value BSET GF FLAGS USE XS BIT 5 bit for 1 5 I conv routine location of converted value CURRENT xmit buffer location CONTINUE TO CURRENT CONVERSION ROUTINE pev e ees ROUTINE TO CONVERT DATA FROM RAW A D TO SERIAL FORMAT CALLED With IY LOCATION OF CURRENT TO CONVERT to serial format IX LOCATION TO STORE CONVERTED CURRENT INTO USUALLY XMIT BUFFER Pc SENSOR SIZE AND RATING PLUG ARE USED TO DETERMINE TEE CONVERSION VALUE USE XS is set if conversion is done on GF value 5 089 928 121 122 2 RETURNS Current in serial format in memory location pointed to IX i USED IX IY RESTORED NOTHING UU 999999999 9 99799
84. 4 megohm resistor 613 provides a fixed time constant of 324 seconds or ap proximately 5 4 minutes Control over the voltage on the RC circuit 610 is provided using IGFET transistors 618 and 620 such as part Nos 0808 and 85170 respectively During normal quiescent conditions the microcomputer 120 will not be in an overload condition and will drive a logic low at the gate of the transistor 620 thereby dis abling transistors 620 and 622 and allowing the capaci tor 611 to discharge to tripping system ground Transis tors 618 and 620 work in connection with resistors 621 623 and 625 which have values for example of 100 K ohms 47 K ohms and 5 1 K ohms respectively During overload conditions the microcomputer 120 accumulates current information in its internal RAM to simulate the heat level and drives a logic high at the gate of the transistor 620 to allow the capacitor 611 to charge to a selected corresponding level While the capacitor 611 is charging the microcomputer 120 moni tors the voltage level using the analog buffer 612 When the selected level is reached the microcomputer drives a logic low at the gate of the transistor 620 to prevent further charging The voltage on the capacitor 611 is 5 089 928 15 limited to five volts using clamping diode 622 The forward voltage drop across the clamping diode 622 is balanced by the voltage drop through a series diode 625 For example assume that an overload conditi
85. 5555555555 5 i SISR SERIAL INTERRUPT SERVICE ROUTINE 5 5 SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS SISR XADR ACCTMP TSH MEM POINT TO TEMP SERIAL HIGH BYTE TSIOAM TRANSFER SERIAL DATA INTO MEM HL AND ACCUMULATOR 50 SERIAL TAD TRANSFER SER HIGH D REGISTER XADR TSH ACCUMULATOR SERIAL LOW TAE REGISTER SERIAL LOW TDA ACCUMULATOR D REG SERIAL HIGH FOR PACKET NUMBER BYTE 0 2 IF SO SETUP CHECKSUM AND BYTE COUNT SKABT 3 STATUS PACKET BYTE 3 SET Pl GJMP PACKET NUM BYTE TEST BYTE COUNT TEA ACC SERIAL LOW XADR PTEMP SAVE TEMP PACKET NUMBER TEA SKAEI 024 2 BYTE GJMP P2 PACKET O OR 1 XADR CHECKSUM BYTE 0 LAI DATAREADYFLAG 0 XADR RESETDATA READY FLAG SKAE ROY WAS XFER PREVIOUS PACKET CALL LAI BCis4 XADR 0 P2 SKAEI PACKET 1 BYTE GJMP P3 PACKET 0 BYTE XADR CHECKSUM BYTE O LADR RDY TESTFOR DATA READY FLAG SKAEI NOT SET CONTINUE GJMP FLAG SET RETURN LADR ACC PHASE SELECT BYTE SKAEI 02 PHASE GJMP P21 1 FORC PHASE GJMP P21 SKAEI OIH GFPHASE GJMP NEITHER C OR RETURN 03 3 FOR GF PHASE 5 089 928 187 188 P3 SKAEI XADR CHECKSU
86. 6 16 6b Sheet 8 of 10 5 089 928 Feb 18 1992 U S Patent Sheet 9 of 10 5 089 928 Feb 18 1992 U S Patent 9213 OL 9141 900H21VM 8 913 peste SE _ o 22 m 024 Jf qe 4 BN ibiz 624 922 304 T 4 L 292 E 624 02 01 13538 164 4 4 4 bb4 94 924 _ _ 1 AG 4 x Neue East Mast v 4 7 Sheet 10 of 10 5 089 928 Feb 18 1992 17 6 Patent 914 01 W033 5 089 928 1 PROCESSOR CONTROLLED CIRCUIT BREAKER TRIP SYSTEM HAVING RELIABLE STATUS DISPLAY TECHNICAL FIELD The present invention relates generally to circuit breakers and more particularly to processor con trolled trip arrangements for circuit breakers BACKGROUND ART Trip systems are designed to respond to power faults detected in circuit breakers Most simple trip systems employ an electromagnet to trip the circuit in response to short circuit or overload faults The electromagnet provides a magnetic field in response to the current flowing through the breaker When the current level increases beyond a predetermined threshold the mag 10 netic field trips a mechanism which causes a set of 20 circuit breaker contacts to release thereby breaking the circuit path Many si
87. 6 one for each of the current transformers 510 512 and 514 and one for the neutral current path trans former 506 which is optional The toroid 508 has a single output winding 509 which provides a summed current signal The ground fault sensing toroid 508 includes another winding 550 to allow a test signal to be applied at termi nals 552 Using momentary switch 554 the test signal creates a pseudo ground fault for the tripping system The tripping system reacts to this pseudo ground fault in the same manner as a true ground fault The test winding 550 is protected by a positive coefficient resis tor 556 that increases its resistance as it heats thereby limiting the current through it and the winding 550 The 5 089 928 11 positive coefficient resistor is for example a Keystone PTC Resettable Fuse part No RL3510 110 120 PTF The test winding 550 eliminates the need for a separate test transformer which has been utilized by systems in the prior art The operation of the ground fault sensing toroid 508 is best understood by considering the operation of the tripping system with a ground fault and without a ground fault In a balanced three phase system without a ground fault the current magnitude in each phase is equal but 120 degrees out of phase with the other pha ses and no neutral current exists thus the output wind ing 509 produces no current As the current through any phase A B or C increases the current in the neu tr
88. 60736 58 186 34596 3 15 0 58 78 3454 93 164191 51 150 22500 32 15 5 42 58 1812 89 166004 40 109 11881 33 16 0 24 87 618 47 166622 87 63 3969 34 16 5 6 28 3943 166662 30 16 256 35 17 0 12 53 157 08 166819 38 32 1024 36 17 5 30 90 954 9 167774 29 79 6241 37 18 0 48 18 2320 85 170095 14 123 15129 38 18 5 63 74 4063 08 174158 22 163 26569 39 19 0 77 05 5936 89 180095 11 196 38416 40 19 5 87 63 7679 12 187774 23 223 49729 41 20 0 95 11 9045 08 196819 31 243 59049 42 20 5 99 21 9842 91 206662 22 253 64009 43 21 0 99 80 9960 58 216622 79 254 64516 44 21 5 96 86 9381 54 226004 34 247 61009 45 22 0 90 48 8187 13 234191 47 231 53361 46 22 5 80 90 6545 10 240736 57 206 42436 47 23 0 68 45 4686 07 245422 64 175 30625 48 23 5 53 58 2871 12 248293 76 137 18769 49 24 0 36 81 1355 17 249648 93 94 8836 50 24 5 18 74 351 12 250000 05 48 2304 MEAN OF THE SUMMATION 5000 00103 MEAN OF THE SUMMATION CALC RMS VALUE Amps 70 7106854 CALC RMS VALUE Binary ACTUAL RMS VALUE 70 7106781 ACTUAL RMS VALUE APPENDIX A SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING wer e Be e Fe Fe Ie e He e Pe e Fe e e e e Ye e de SERIES THREE TRIP SYSTEM wo dde ede de dee fefe eje dede Memory Map for SERIES III BOARD REKKEREREK RAM START EQUAL 0000 Start of 256 bytes of RAM END EQUAL 00 end of 256 byte RAM memory REGS
89. 65 16 against a predetermined threshold value that has been chosen to represent the maximum allowed heat content of the system When the accumulated value equals or exceeds this predetermined threshold value the trip ping system will trip the breaker A valuable aspect of accumulating the current squared value is that as the current doubles the current squared value quadruples and the internal accumulation register increases at a more rapid rate resulting in a more rapid trip Thus if the delay time the period before the detected power fault causes a trip is x sec onds at some current level as the current doubles the delay time will be x 4 seconds The formula for calculating the delay time for any constant current is ARXK po cR where the accumulation rate in seconds predetermined final accumulation value and I the true RMS value of current flowing through the breaker D Reset Circuitry Referring now to FIG 8 an expanded view of the reset circuit 124 is shown to include a power up reset circuit 710 and a watch dog circuit 712 to maintain the integrity of the tripping system 100 The power up reset circuit 710 performs two functions both of which occur during power up it provides a reset signal asserted low on line 743 to maintain the microcomputer 120 in reset condition until the tripping system 100 develops sufficient operating power from the current lines 106 and it provides a reset sign
90. 99299999 9 9920992072 9999299999992 99 9 v6 9T tevevevtee Square D Company ADE Group Jerry Baack Leon Durivage 8 16 25 SERIES III ELECTRONIC TRIP YSTEM SOFTWARE LISTING 210113110111211217 2 11202 211 RESULT USED 1111111112 193121912929 9 93 D 9 12 0 01 QIUETYEWEWEWENWLWEWETESTETETETERTETRETETETETETETRETSTTERREEREWETET STNTSESTTSET T ET T EN TY I CONVERSION 5 PSEX save storage location for later use SENSOR read the sensor size ANDB 5 MASK mask unused bits 1 sensor size BLS BY 14 ssensor is OK go multiply LDAB 1 zload max sensor MULT BY 14 15 ALREADY SET FOR WORD MULTIPLY SO EQUALS OF WORDS LDAA 14 714 words per row MUL find correct starting row ADDD CONV TBL to start of conversion multiplier table XGDX put into IX for index use BRCLR GF_FLAGS USE_XS_BIT READ THE RPLUG if GF bit clear read the LDAB 1 get value for GF calculations 4 JM PLUG 69 Co calculations READ RPLUG EQU LDAB RATING PLUG read rating plug value ANDB SWITCH 5 mask it 51 check for UTS or PROD tester PLUG have an honest to goodness RP 00 zif tester default to 4 multiplier PLUG add plug to row offset points to value JSR 16X16 go do multiplication ITT RESULT IS NOW IN 32 BIT RESUL
91. AA 180 get 90 mSec value STAA INST TIMER set INST for 90 mSec to run discriminator JMP START DISCRIM go turn on discriminator SET DS AT 20 EQ LDAA 40 DS instantaneous timer 20ms STAA INST TIMER zstore to INST timer START DISCRIM EQU 5 BSET INST FLAGS I 5 INST timer bit start INST timer UMP EEPROM ERASE can t be PE or erase EEPROM Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING NOT AN SE EQU TE WE HAVE PE TEE BREAKER BIT IS SET HERE is i yee d ee ae de de de ve dede we CHECK_FOR_PE 08 sis it a breaker BNE CHECK EE ERASE no branch PE 5 if brkr type is undefined then set to PE S FLAGS PE BRKR PE breaker bit PE breaker check is moved then LDAB must be added to the CHECK EE ERASE routine CHECK EE ERASE EQU IF BREAKER TYPE CODE IS AN THEN CLEAR THE EEPROM eeee CMPB 581 MASK if breaker type lE erase all EEPROM BNE EEPROM ERASE type so don t erase EEPROM JMP EEPROM ERASE igo erase the EEPROM amp trip the breaker NO EZPROM ERASE EQU JSR SENSOR_BREAKR ido breaker sensor conversion for xmit routine SET TEE THREE RMS PHASE TIMERS AT STAGGERED TIMES The 3 timers are staggered at l6mSec intervals to allow system ti
92. AA AAA AAA ORG 180H DB ODEH DAEH DOEH O56H DC4H D64H OSH D7AH DBOH DE2H DB 028 9 020 DB QU COSH LOCH DIE DOFSUDTOHOY HO TAH OT DB OI6HO18H MEMORY INITIALZATION CONTINUED SO sSERIAL SETUP LA ZERO POINTTO ZERO DATA MEM ST MEM LOC TO ZERO POINT TO ONE DATA ST MEM LOC TO 1 OLS ST 05 ST OLS ST XADR HMSN FOR BCD CONVERSION gt PORTS INTIALIZATION CO 6 MODE SELECT REGISTER SET TO INPUT MODE OP MSR gt LCD DISPLAY INTIALIZATION 00108 DISPLAY SETUP DATA OP ACCTO DISPLAY MODE SELECT REGISTER MSR GJMP MAIN JUMP TO MAIN ROUTINE 5 089 928 169 170 BB SE 888 88888888 888 c AA cA c EE Ac Ro A Ac Ac B A c la A c amp amp ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER AT AMPS amp amp ORG 1 DB O80H DAOH 094H 288 002 070H 000H 00 058 DB 020H040H00 D8 COCH 0 1 OIH OTAR DIBH DB OICHDIFH 15565555555555555555555555555555555555555555555555555555555555555555555555555 5 5 P PSISR PHASE SELECT INTERRUPT SERVICE ROUTINE iS SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS ROTATE THE LCD PHASE ADDR
93. ANDA 457 UMP CHECKSUM LINDA SUE EQ Clears byte and serial pointers checks set for next byte load the address into mask off high bit checksum before transmission for packet pointer increment and if tripping locks at packet 2 Does housekeeping for pointers CLR BYTE CLR SERIAL 1 LDAA PACKET Square D Company ADE Group Jerry Baack Leon Durivage new packet so clear byte pointer pointer to 0 before checksum 4 packet pointer Date 8 16 89 SEPIES III ELECTRONIC TRIP 5 51 SOFTWARE LISTING BEQ PACKET packet 0 so increment to 1 01 15 packet is 1 LOAD NEXT PACKET next packet from packet holder LDAA TRIP STATUS BYTE we in trip ANDA 570 mask all but trip bits BEQ NORM DATA if 0 we are not tripping 570 15 this test data BEQ NORM DATA yes transmit normally JMP SEND_PACK T2 no we are tripping DATA EQU CLR PACKET no trip so clear packet pointer JM SEND 5 send the checksum De PACKET miae t transition of packet 0 INC SEND CRECKSUM LCAD NEXT PACKET EQU to 1 Bypassed if tripping pointer 0 set to 1 90 send the Packet holder 5 track of packets 2 7 Packet pointer is used to point 5 089 928 127 128 into the correct positio
94. BIT SET STATE TO LT PICK UP BSET LT FLAGS LT 612 SET LT ACCUM gt ZERO BCLR LT FLAGS LT PU9 amp 1 IN 100 STATE CANT T BE IN 90 LDX REGSTART 9 set index to start of 6811 registers BSET PORTA X LED have pick up so set led LDX SQRT SET X REGISTER FOR MULTIPLY SET Y REGISTER FOR MULTIPLY JSR SQUARE SQUARE THE RMS ROOT IDD RESULT 2 THE I SQUARE LOW WORD LDX LT_ACCUM X POINTS TO LT ACCUM JSR 4 ADD ADD I 2 TO LT ACCUM LDD RESULT HI WORD OF CURRENT SQUARED ADDD LT ACCUM ADD Hi WORD OF LT ACCUM STD ACCUM STORE IN Hi WORD OF LT ACCUM LDX DEL DELAY TABLE START ADDRESS IN X LTDELSW LT DEZLSW ADDRESS IN Y LDAA 32 MULTIPLY BY 32 5 SHIFT LEFTS 5 089 928 89 90 BCLR FLAGSS WRD ALIGN CLEAR 1 FOR DBL WORD INDEX JSR SET TBL INDX 4 BYTE INDEX POINTER COMPARE THE LT ACCUMULATOR TO THE DELAY TABLE LDY LT_ACCUM 31ST COMPARE VALUE IN Y JSR WORD THE DOUBLE WORDS CMPA 00 IF gt 0 TIME TO TRIP BGE LT TRIP LT ACCUM gt gt TABLE DELAY VALUE UMP DO SWITCHES ARE STILL ALIVE Square D Company ADE Group Jerry Baack Leon Dur vage Date 8 16 88 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING LT G7 90 790 PICK UP SEQUENCE BSET LT FLAGS LT 090 STATE TO 90 PICK UP DO SWITCHES EQU
95. BSET FLAGSS NO GF WE HAVE NO GROUND FAULT CLR SWITCHES GF installed so clear switch values BSET OPTIONS NO_GF_BIT SET TO SHOW GF NOT INSTALLED NO GF branch around switch set code Wz EAVE GF EQU LSRB shift to get PU to low 3 bits LDAA GFDELSW delay value Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING ANDA SW POS mask off unused bits LSLA shift to bits 3 5 LSLA shift to bits 3 5 ABA to PU switch value 5 GF SWITCHES store in xmit location FLAGSS NO CLEAR FLAG TO SHOW GF INSTALLED BCLR RP OPTIONS NO GF CLEAR TO SHOW GF INSTALLED NO GF EQU BCLR RP OPTIONS SOF clear rating plug bits LDAA RATING PLUG read the rating plug ANDA SWITCH_MASK mask off unused bits LSRA move to correct location for xmit byte OPTIONS combine with rest of the byte STAA OPTIONS put it back to xmit byte RTS the party s over bye bye PTT u ALL E SQUARED CODE IS IN THIS SECTION EEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEEZERZ gw THIS SUBROUTINE ERASES TEE EEPROM fe se de de e ede fe dede de e dene den den Only IX is used besides doesn t make any difference Breaker is tripped after E 2 is erased CALLED This is called when breaker type switch 15
96. CCUM 0 GOTO CHECK ADJUST LT VOLTS amp LT 97 RATIO GOTO CHECK 11MS 5 Se 5e 4 o Se ta e GTZ BIT LT 622 0 GOTO CHECK 11 5 ADJUST LT VOLTS amp LT RATIO TABLE e 9 4 5e Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING CHECK 11MS IF T 11MS TIMER lt 11 GOTO 12MS T 11 5 T 11 5 11 SERIAL POINTER MAX PHASE CURRENT GOTO TEST ST INSTALLED I CONVERSION ST TEST ST INSTALLED IF ST PU BIT 0 GOTO CLEAR ST PEAK ELSE IF SC RESTRAINT BIT IN 0 GOTO LEAR ST PEAK ELSE SW POS lt 6 GOTO CLEAR 57 ELSE ST 150 44 Se te CLEAR ST PEAK 5 089 928 45 46 CEECK ST 12 5 CEECK 12 5 IF T 12MS 12 GOTO CHECK 13MS t T 12MS T 12MS 12 IF LT 672 0 CHECK 13MS ELSE IF LT PU 1 GOTO CHECK 13 5 LT DEC CHECK 13MS IF T 13MS lt 13 GOTO CHECK 17 5 T 13MS T 13MS 13 RESET COP IF NO GF BIT 0 GOTO CHECK GF ISQ GF CURRENT 0 CHECK 64 6 CHECK GF 150 IF SERIAL POINTER amp GF CURRENT GOTO DO GF SERIAL CONV GOTO TEST FOR GF PU DO GF SERIAL CONV 8 8 CONV 0 5 m SE
97. CL set data direction to output BCLR SPCR X 40 disable SPI connect port D LDAB 08 set for 8 clock cycles SEND_NEXT_CLOCK EQU BCLR PORTD X SCL iclock low NOP NOP BSET PORTD X SDA clock high BSET PORTD X SCL clock high NOP BCLR PORTD X SDA clock low start count down to 0 BNE SEND NEXT CLOCK if not 8 clocks send next clock RTS return with clock high RSTRSTASTRSTRSTRSTRSTRSTRSRTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTASTRSTRSTRSTRSTR ADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDR This Subroutine sends the correct address to send data to and tells the EEPROM to wake up Called with no parameters set ACCA ACCB IX amp IY are not restored Uses a portion of the WRITE_EE routine to address the EEPROM IMPORTANT THIS ROUTINE MUST BE CALLED BEFORE CALLING EE READ or EE WRITE EEE ERE ADDRESS WEE IDY 5 000 mark to leave after sending address LDX REGSTART load IX with start of regs to send data BSET 50 5 clock amp data line high to prepare for sta bit ESET DDRD X SDA SCL set serial data for output BCLR SPCR X 40 shut down spi connect portD to output NOP insert no ops for timing NOP ito make sure delay is long enough for start BCLR PORTD X SDA pull data line low for start bit LDAA 0 address for serial EE amp write to addr 0 JSR ADDR go send firs
98. CURRENT gt 2700H SET DISPLAY VALUE TO 9999 BCD HIGH BYTE MSN OEH COMPLEMENT OF 2 FOR TEST RC RESET CARRY ACSC FOR VALUE gt 2 GJMP CONV LESS THAN 2 CONTINUE CONVERSION TAE RC DES DECREMENT TEST VALUE GREATER THAN 2 SET VALUE 9999 TEST VALUE 2 TEST NEXT NIBBLE FOR gt 7 HIGH BYTE LSN kc OH COMPLEMENT OF 7 FOR TEST ACSC FOR VALUE gt 7 GJMP CONV LESS THAN 7 CONTINUE CONVERSION 5 089 928 191 192 CURRENT TOO HIGH SET VALUE TO 9999 OFLW LHLI BCD4 POINT TO BCD DATA STORAGE 9 ST 10005 DIGT 9 POINTTO BCD DATA STORAGE 1005 DIGT 9 BCD2 BCD DATA STORAGE ST 105 DIGT 9 1 POINTTO BCD DATA STORAGE ST YS DIGI 9 RT CONTINUE WITH BCD COVERSION SUBTRACT 1000 UNTIL VALUE BECOMES NEGATIVE TO DETERMINE 10005 DIGIT CONV LA RESET COUNT VALUE TO ZERO TAE THOUS RC CARRY POINT TO VALUE TO BE CONVERTED LOW BYTE LSN LA 08H VALUETO BE ADDED FOR 1000 TO LOW BYTE LSN ACSC sADD VALUES NOP TEMPI TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE 872 POINT TO VALUE TO BE CONVERTED LOW BYTE MSN VALUE TO BE ADDED FOR 1000 TO LOW BYTE MSN ACSC ADD VALUES NOP 2 POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED
99. D RESET FLAG CONVERT DATA TO BCD FORMAT SEND DATA TO LCD DISPLAY DETERMINE OF TRIP RATING 380 382 384 386 388 SEND DETERMINED TO LCD DISPLAY GRAPH Feb 18 1992 BEGIN INTERRUPT 1 VALIDATE DATA RETURN FROM INTERRUPT Sheet 4 of 10 5 089 928 BEGIN INTERRUPT 2 400 DETERMINE PHASE SELECTOR WAIT FOR SWITCH RELEASE DEBOUNCE SWITCH RETURN FROM INTERRUPT LAST 402 404 392 406 CHECKSUM 396 SET DATA READY FLAG 396 FIG 3b Sheet 5 of 10 5 089 928 Feb 18 1992 U S Patent 8 914 4 did 900H21VM rasal 5 68 66 4 696 285 zes 1295 8 u31ndWO2082IN p Nto 666 9 6 cmd rS 48 6 E 66 6 at GGG 1499 EGG 22 01 K 24 l4 226 8 adus 04804 EN EMEND PSI 606 oaf 186 966 296 Ez prs 6 6 446 46 241 p eoe bis 566 296 Xy prx bli 90 Xy i Tee Old D 0 5 Patent Feb 18 1992 Sheet 6 of 10 5 089 928 0 0 2 5 50 75 100 125 150 17 5 200 225 TIME ms FIG 5 0 5 Patent Feb 18 1992 Sheet 7 of 10 5 089 928 527 531 1
100. D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING RESTRN DELAY EQU LDAB STDELSW READ ST DELAY SWITCH ANDB SW POS MASX ZERO CMPB 06 S4 gt 6 1 2 IN BHI EXIT SEORT 58 SET FOR I 2 IN WAIT FOR llmS ROUTINE SHORT TIME SWITCH IS SET FOR FIXED DELAY ST DELAY EQU 5 089 928 53 54 LDD ST 12 OUZ TIMER get I squared out timer 5 to null value BEQ SCHED TIER no timer so start one BCLR ST I2 OUT TIMER T_INACTIVE_BIT stimer may be asleep wake JMe EXIT SEORT TIME have active timer so leave SCEED TIMER EQU LDX ST_FIXED DEL 5 FIXED DELAY TABLE START STDELSW ST DELAY SW ADDRESS LDAA 8 MULT BY 8 BSET FLAGSS WnD ALIGN 21 WORD BOUNDARY REQUEST JSR SET TBL INDX CALL TABLE CREATE SUBROUTINE LDX 0 X GET TIMER VALUE FROM TABLE STX ST_I2_OUT_TIMER start 172 out timer EXIT SHORT TIME CONTINUE IN MAIN FLOW ST OFF EQU CHECK INACTIVE FOR ANY FIXED DELAY TIMERS THAT ARE RUNNING amp PUT TEEM SLE BRSET ST FLAGS ST PU BIT EXIT SHORT TIME 14 have old PU t cir BSET ST_ 712 OUT TIMER T INACTIVE put any active timers to sl EXIT SHORT TIME EQU THIS CODE IS EXECUTED EVERY TWO MIILISECONDS WHEN THE GROUND FAULT 2mSEC TIMER COMES DUE ALL GROUND FAULT PICKUP CODE IS EXECUTED
101. D YET BLO TEST GO SEE IF TIME TO DO PHASE B RMS BRCLR LT FLAGS A PHASE CONV TEST PHASEB PHASE CONVERSION FLAG IS SET DO SERIAL CONVERSION BCLR FLAGS A PEASE CONV DONE SO CLEAR FLAG LOX SQRT STORAGE LOCATION FOR RMS VALUE JSR PHASE UNBALENCE PHASE UNBALENCE FOR DISPLAY 1528 to 1 value for serial comm STAB PHASEA UNBAL STORE TO DISPLAY BUFFER LDX SERIAL POINTER check to see if we are sending phase curren PHASE RMS e 4 gt BNE DO SERIAL CONV 70k to convert TEST 64MS GO CHECK FOR 64 mS DO SERIAL CONV EQU PHASA_SORT get a phase square root location LDX PHASE RMS storage location JSR 1 CONVERSION igo do transmit conversion amp storage BCLR FLAGS A PHASE CONV DONE SO CLEAR FLAG JMP 64 5 CHECK FOR 64 mS 52 PHASEB EQU LDAA RMS B PHASE TIMER 64 5 PHASE B MS TIMER EXPIRED YET BLO TEST PHASEB 2MS GO SEE IF 2 MS HAVE EXPIRED SUBA 64 STAA T PHASEB RMS CLEAR TEE TIMER IDX RMS_SUMSQH_2 location of squared SUM FOR CHAN 2 JSR AVG AVERAGE I 2 VALUE CHAN 2 LDD RMS SQROOT 50 ROOT FROM AVG ROUTINE STD PHASB_SORT LAST 64 MS SQ ROOT OF I FOR CHAN 2 BSET 11 FLAGS B PHASE CONV CONV DONE SO CLEAR FLAG JMP TEST 64MS CONTINUE MAIN EXEC LOOP 5 PHASEB 2MS CMPA 8 3 5 PHASE RMS TIMER EX
102. E POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN OFH BE ADDED FOR 100 TO HIGH BYTE LSN ACSC ADD VALUES CALCULATE HUNDREDS VALUE GETCON GJMP HUNDS SUBTRACT 10 UNTIL VALUE BECOMES NEGATIVE TO DETERMINE 10 DIGIT 5 TEA x HUNDREDS DIGIT SKAEI OOH 1005 10005 DIGITS ARE 0 SUPRESS CHARACTER GJMP CTI LADR 4 10005 DIGIT FOR SUPRESSION GJMP CTI GJMP CT2 CT2 XADR BCD3 HUNDREDS DIGIT LAI COUNT VALUE TO ZERO TAE 5 RC RESET CARRY POINTTO VALUE TO BE CONVERTED LOW BYTE LSN LAI OSH BE ADDED FOR 10 TO LOW BYTE LSN ACSC ADD VALUES NOP TEMPI POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE 812 VALUE TO BE CONVERTED LOW BYTE MSN LAI VALUE BE ADDED FOR 10 TO LOW BYTE MSN ACSC ADD VALUES NOP LHL 2 POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE 873 VALUE TO BE CONVERTED HIGH BYTE LSN LAI VALUE TO BE ADDED FOR 10 TO HIGH BYTE LSN ACSC ADD VALUES NOP LHLI TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE LHLI POINT TO VALUE TO BE CONVERTED HIGH BYTE LSN LAI OFH TO BE ADDED FOR 10 TO HIGH BYTE LSN ACSC ADD VALUES GJMP CONES CALCULATE HUNDREDS VALUE
103. E CONV DONE SO CLEAR FLAG TEST 64MS J CONTINUE MAIN EXEC LOOP EST PHASEC 2MS EQU 5 5 8 HAS PHASE MS TIMER EXPIRED YET BLO TEST 64MS GO SEE IF TIME TO DO PHASE B RMS BRCLR LT FLAGS C PHASE CONV TEST 64MS Conversion bit is set so do serial comm and phase unbalance routines LDX SQRT PHASE RMS LOCATION JSR PHASE UNBALENCE DO PBASE C UNBALANCE 1588 convert to 1 value for serial comm STAB UNBAL STORE UNBALANCE FOR DISPLAY LDX SERIAL POINTER tget location of byte last sent CPX PHASE RMS zis ti the first half of phase current BNE SERIAL CONV C 1 not OK to do serial conversion JMP TEST_64MS CEECK FOR 64 mS DO SERIAL CONV C EQU P PHASC_SOQRT a phase square root location LDX PHASE RMS storage location JSR I CONVERSION 00 do transmit conversion amp storage BCLR LT FLAGS C PHASE CONV DONE SO CLEAR FLAG TEST_64MS EQU 5 LDAA T 64MS GET 64 mS TIMER VALUE 64 HAS ALL 64 MS EXPIRED FOR THIS CYCLE BLO CHECK 250 5 CONTINUE MAIN FLOW SUBA 64 reset the timer STAA T 64MS RESET RMS 64 MS CYCLE TIMER RMS 64 MS TIMZR BAS EXPIRED UR peewee ROO FOLLOWING CALLS ARE DONE EVERY 64 MS JSR LT SERIAL BITS 290 set LT serial comm bits JSR FIND SQRT find peak of RMS for Long Time amp
104. E MEMORY RATIO 0 1005 BYTE 28 PHASE UNSALENCE BYTE 29 PHASE B UNBALENCE B BYTE 30 PHASE C UNBALENCE SOFTWARE VERSION BREAKER ADDRESS TO MAKE UPRARD COMPATIBLE CHECKSUM BYTE B TO END OF DISPLAY BUFFER BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB MILLISECOND TIMERS STORED IN THIS AREA T 2MS ST TMS GF 07 5 RMB RMB RMB 1 1 1 22 mS short time timer 2 mS ground fault timer 7 MS TIMER SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING 211 MS TIMER 112 MS TIMER 113 MS TIMER TIMER FOR PHASE SQUARE ROOT TIMER FOR PHASE B SQUARE ROOT TIMER FOR PHASE C SQUARE ROOT 64 MS TIMER 7250 MS TIMER 41 SEC TIMER peak storage for phase unbalance of all phases for ST table position for STPU 11mS max current to transmit table pos for GF PU 13mS peak storage pass location speak storage pass location storage pass location storage for phase pickup storage for phase pickup storage for phase pickup CHANNELS MUST STAY CONTIGUOS CCCCCCCCCCCCCCCCCCCCCC 1 phase low gain A D 7B phase low gain A D phase low gain A D ichannel one atod multiplexor phase high gain A D phase high gain A D phase high gain A D for trip routine usage RMB CCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCCC 16 Start of the current working A D va
105. EM SOFIWARE LISTING RETURNS With IX set to start of onboard registers ACCA equal to SAA ok o de dede dede dede dede sede gk o ok ode oc eo Rok RESET COP LDX REGSTART LDAA 4555 LOAD 01010101 STAA COPRST X WRITE IT TO COP REGISTER LDAA SAA LOAD 10101010 TO STAA COPRST X FINISH RESETTING COP RTS COPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOP COPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCOPCO STISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTI DIRE TR Ry TR ERTERYY Y ET ET YTER ER YR YRYT Y YT Y TARTE T THIS SUBROUTINE SET TBL INDX READS THE BREAKER ID AND THE SWITCH gt POSITION AND CALCULATES TEE CORRECT POSITION IN A 1 WORD 2 WORD DELAY TABLE CALLED THE X REGISTER MUST CONTAIN TEE CORRECT START OF TABLE THE Y REGISTER MUST CONTAIN THE CORRECT SWITCH ADDRESS TEE A ACCUM CONTAINS THE NUMSER TO MULTIPLY BY TO FIND ROW IF FLAGSS WORD ALIGN IS SET TO 1 CREATE A 1 WORD INDEX IF FLAGSS WORD ALIGN IS ZERO CREATE A 2 WORD INDEX 44 7 Se RETURNS THE X REGISTER POINTS THE CORRECT TABLE VALUE UPON RETURN ACCA amp ACCB are not set to any given value IY is not chancec 9 5e SET TBL INDX EQU JSR READ BREAKER SW read the breakr type switch CONT TO SET
106. ERIERTEREITAIE EY YATEXEIEEETEEXTIYTERXIEREE RETI RTAEERE E X P z H d o ADJUST FLC VOLTS EQU ADJUST LT VOLTS EQU BRCLR LT FLAGS SET ACCUM BIT ACCUM ALREADY SET SET ACCUM is high then we to reconstruct a LT FLC accumulator JSR LT ACCUM GO GET MEMORY RATIO VOLTAGE amp FIGURE ACCUMULA LDD RESULT load LT rebuilt accumulator result hi word STD ACCUM Store LT accumulator into memory LDD RESULT 2 load rebuilt low STD 2 store low word to memory SET THE LT ACCUM GREATER THAN ZERO FLAG IN LT FLAGS BSET FLAGS LT 6 2 BCLR LT FLAGS ACCUM clear bit since Accum is calculated 5 Fall done so leave ACCUM ALREADY SET EQU E JSR LT ACCUM RESULT LDX ACCUM GO GET MEMORY RATIO VOLTAGE amp FIGURE ACCUMULA CALCULATED LT OR FLC ACCUMULATOR HI WORD OF LT OR FLC ACCUMULATOR te JSR ACCUMULATOR VALUES 00 JARE HIGH WORDS THE SAME BGT ADJUST DOWN RATIO gt gt LT ACCUM FLC ACCUM BLT ADJUST UP RATIO LT ACCUM FLC ACCUM IF WE GET HERE BOTH CALCULATED AND LT ACCUM ARE EQUAL RTS ADJUST UP SET PORT BIT HIGH TO ADJUST VOLTAGE LEVEL UP LDX REGSTART ONBOARD REGISTER LOCATIONS BSET PORTD X 20 TURN ON OUTPUT TO INCREASE MEM DELAY RTS ADJUST DOWN SET PORT BIT LOW TO ADJUST VOLTAGE LEVEL DOWN LDX
107. ESS RIGHT FOUR TIMES TO POINT TO NEXT PHASE PSISR XADR ACCTMP TIMER RESET SOFTWARE RESET TIMER PHASE INDICATOR RC RESET CARRY RAR SKAEI OOH FOR A PHASE GJMP PS O8H SETFOR PHASE 51 XADR SELECTED PHASE SKAE OIH SELECT CHECK TO SEE IF GF IS INSTALLED GJMP PS2 LADR OFT SKABT 2 OPTION INSTALLED GJMP PS2 GJMP 511 52 RC LA QOH ST GJMP 521 8 Bec B RB c BR 8 888 8 58 8 8 8 8 05 8 KEE 5 58 85 858 8 5 8 8 amp amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT AMP amp ET 200H 07 D58H 020H O4CH 040H ODOH 28H 080H 010H O04H DEOH 0 0 012H 017H 01AH01BH 01CH01DH 020 023H 025H 027H 029 99555 LAMT 4 5 SELECT ISR CONTINUED PS21 LAI SETTHE DEBOUNCE COUNT FOR 16 50 OSH SKIP IF TIMER INTERRUPT OCCURRED OH START COUNTING GJMP RESET PS5 ST COUNT 5 089 928 171 172 PS3 OSH GET PORT 5 INPUTS SKABT SWITCH GJMP PS4 GJMP PS21 FOR SWITCH RELEASE PS4 DES DECREMENT COUNTER RETURN IF UNDERFLOW GJMP PS3 TDA GJMP PSEX GJMP PS22 PSEX XADR ACCTMP RT 288 8 8 8 88 8088 8 5
108. ESTRAINED DELAY LDX REGSTART start of registers BRSET PORTA X SC RESTRAINT IN CLEAR ST PEAK STDELSW READ ST DELAY SWITCH ANDB SW POS MASK OFF BIT O 06 gt 6 i 2 BLS CLEAR ST PEAK POSITIONS 0 3 ARE 1 2 OUT FIXED TIMERS JSR ST 150 IN 60 DO 172 IN ST DELAY ROUTINE LEAR ST PEAK EQU JSR CHECK ST 12MS ST PEAK STPU AS NEEDED PPR xe e dee END OF 11 MS OPERATIONS PIIIISZZIIIIEZILRIIZARRRRARIRRRRAARAS qTX X Rn RH HORE RU RU 12 MS TIMER CHECK ede oe d dede de de o de n de er n Serial communications and Long Time Accumulator decrement are run on this CHECK 12MS time base LDAA 12MS 12 MS TIMER 12 HAS EXPIRED YET BLO CHECK 13MS NO IT HAS NOT EXPIRED xe e THE FOLLOWING CALLS ARE DONE EVERY 12 MS SUBA 12 the timer STAA 12 5 save r set timer Square D Company ADE Group Jerry Baack Leon Durivage Date 6 16 09 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING LT ACCUM ACCUM GT ZERO IS NOT SET DON T CALL LT DEC ACCUM BRCLR LT FLAGS LT GTZ 13 5 if LTA 0 check 1375 timer BRSET LT FLAGS LTI PU BIT CHECK 13MS if LTPU set don t decrement JSR LT ACCUM DEC 4 ACCUM IF BELOW PICKUP END OF THE 12 MS CALLS c fe e e de qe ee e e qe de de 9 owe e
109. G value for trip indicator DE RETURNS nothing reinitializes breaker code if no current for HN more than 128 5 P1111 TEMP USED GLOBAL TRIP EQU JSR RESET COP resest the watchdog ESET IFLAGS TRIPPING set tripping flag so INST isn t run in interr CLR 250 5 iclearz 250 mSec timer LDX REGSTART GET START OF ONBOARD REGISTERS BCLR PORTD X MEM turn off LT memory cap charging LDAA 4502 packet 2 PACKET stripping so only send packet 2 STAA PACKET EOLDER stripping so only send packet 2 CLR BYTE reset to byte 0 CLR CHECK SUM clear checksum to start again JSR SERIAL 20 send first byte to tell of trip LDAA RATING PLUG check for UTS ANDA SWITCH MASK mask unused bits 1 compare to tester or RP BGE EE WAITE if tester or UTS don t write to EE JSR RESET COP reset the softdog timer THIS SECTION PASSES ALL THE CURRENT DATA BEFORE WRITING TO EEPROM LDX A PHASE RMS GET POINTER FOR CURRENT PHASE TRIP I historical data pointer MOVE DATA EQU LDD O X get current data STD 0 9 store it to history LDAB 502 current a 16 bit word ABX add to pointer ABY to pointer Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 85 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING SCRIN compare to odd byte BNE HISTORY CLASS OVER see if all data xfere
110. GETCON GJMP TENS REMAINING LOW NIBBLE OF VALUE IS EQUAL TO ONES DIGT CONES TEA TENS DIGT SKAEI OOH 105 AND 1005 DIGIS ARE 0 SUPRESS CHARACTER GJMP LADR BCD3 1005 DIGIT FOR SUPRESSION QAH GJMP GJMP 02 CO2 XADR 2 TENS DIGT XADR BT GETLAST CONVERTED VALUE XADR BCD STORE CONVERTED VALUE RT 15655555555555555555555566555555555555555555555555555555555555555555555555555 5 5 DSPLY DISPLAY BREAKER OPERATING CURRENT 5 SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 5 089 928 195 196 DISPLAY 15 DIGIT DSPLY RC CARRY LADR 1S DIGT O3H POINTTO 15 DIGI RIGHT SIDE CALL RIGHT GET CHARACTER RIGHT SIDE DATA AND STORE ONE PONTTO VALUE 01H LADR CENTER OF CHAR C MASK LOW 3 BITS 048 POINT TO CENTER ST STORE MASKED VALUE RC BCD ACC 15 DIGT CALL CENTER CHARACTER CENTER DATA POINT TO CENTER VALUE FOR 15 CHAR ORL ST RESTORE BCD VALUE RC LADR BCD ACC lSDIGIT POINTTO 15 DIGIT LEFT SIDE CALL LEFT CHARACTER LEFT SIDE DATA AND STORE DISPLAY 105 DIGIT RC RESET CARRY LADR BCD2 ACC 10S DIGIT POINTTO 105 DIGIT RIGHT SIDE CALL RIGHT GET CHARACTER RIGHT SIDE DATA AND STORE ONE POINTTO VALUE O1H LADR 07H CENTER OF CHAR ANL MASK LOW 3 BITS
111. HLSN SET 24H TEMP HIGH BYTE LSN TLMSN SET 25H TEMP LOW BYTE MSN TLSN SET 26H TEMPLOW BYTE LSN ZERO SET 27H 2ERO VALUE MEMORY LOCATION ARH SET 28H AMPERE RATING HIGH NIBBLE ARM SET 29H AMPERE RATING MIDOLE NIBBLE ARL SET 2 AMPERE RATING LOW NIBBLE CHK SET 30H CHECKSUM 4 NPCT SET NUMBER OF TEN PERCENT OF BREAKER RATING ACCIMP SET 32H INTERRUPI ROUTINE ACCUMULATOR STORAGE VMSN SET 33H VERY MSN FOR 10X CALC HMSN SET BYTE MSN HLSN SET 35H HKGH BYTE LSN LMSN SET 36H BYTE MSN USN SET 37H BYTE LSN OPT SET 40H UNIT OPTIONS PAK SET PACKET NUMBER ONE SET 42H VALUE MEMORY LOCATION BTS SET 43H TEMPORARY BINARY VALUE 4 SET 44H TEMPORARY BINARY VALUE SET 45H BINARY VALUE BT2 SET 46H TEMPORARY BINARY VALUE SET 47H TEMPORARY BINARY VALUE LMOO SET MODULO LOW NIBBLE FOR TIMER SID SET SENSOR LOOKUP ID SET 524 PLUG LOOKUP ID TEMPS SET 53H NIBBLE SET 54H NIBBLE TEMP3 SET 55H NIBBLE TEMP2 SET 56H TEMP NIBBLE TEMPI SET 57H TEMP NIBBLE LTS SET 60H LONG TIME SWITCH SETTING LTEMPH SET 61H iONGTMESWITCH STORAGE HIGH NIBBLE LTEMPLSET 62H TIME SWITCH STORAGE LOW NIBBLE END We claim 1 A circuit breaker tripping system comprising a processor which analyzes current in the circuit brea
112. I tW xde dee de L e N G T I M E 1 Square D Company ADE Group Jerry Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING 1 THIS SUB ROUTINE IS CALLED EVERY 64 MS BY EXEC IF PEAK SQRT IS ABOVE PICK UP TABLE VALUE PEAK SQUARE IS ADDED TO LT ACCUM IT COMPARES THE LT ACCUM TO TRIP ACCUMULATION TABLE VALUE IF THE LT ACCUM IS gt TABLE A TRIP SEQUENCE IS EXEXCUTED CALLED When all 3 phase RMS values have been computed H RETURNS With any Long Time pick up flags set H USES ACCA ACCB IX IY RESTORES nothing TEMP USED 11 1 E I E n 2121120100122 20111120 111111 RESULT USED 1111111121220 220 2 2 1 8 8 111 12 0 1 LONG TIME LDX PU LDAB LTPUSW READ LT PU SW SETTING ANDB SW POS MASK OFF BIT ZERO STAB TEMP SAVE SWITCH VALUE ABX X TO OFFSET IN LT PU TABLE 100 SQRT PEAK FOR LAST 64 MS 0 X COM TO TABLE SW POSITION BHS LT PICK UP IN PICK UP STATE BCLR LT FLAGS LT PU BIT CLEAR PU STATE BIT LDX PU90 X TO POINT TO 90 PU TBL LDAB TEMP SAVED LT SWITCE VALUE ABX IS SW INDEX 100 SQRT RELOAD PEAK SQUARE ROOT CPD 0 X TEST FOR 90 PICK UP BHS LT_GT_90 WE ARE IN 90 PU STATE BCLR LT FLAGS LT PU90 amp BIT CLEAR 90 PU BIT JMP DO_SWITCHES ALL DONE SPARKY LT_PICK_UP BSET LT FLAGS LT PU
113. IF PE BREAKER TYPE INDEX ADDRESS OF PE 1 55 OF OTHER BREAKER TABLES EM ta ee IF PEAK PHASE gt ST PU TABLE GOTO ST_PICK_UP Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING CLEAR PICK UP BIT ST PU 0 GOTO ST OFF 5 se 5 089 928 43 44 ST U 7 ST PU 1 OUTPUT 1 TEST INPUT RESTRAINT FOR DELAYS INPUT 1 GOTO SEORT TIME ST FTIMER 2 TC DECREMENT TIMER BY 2 IF ST FTIMER 0 GOTO ST TRIP SEORT TIME ST TIMER 36 IF ST_SWICHES I 2 GOTO EXIT SHORT TIME ST FIXED DELAY IF ST I2 OUT TIMER RESET SCHEDULE TIMER ELSE IF ST 12 OUT TIMER INACTIVE RESTART H 9 EXIT SHORT TIME SCHEDULT TIMER ST 12 OUT TIMER DELAY TABLE DELAY SWITCH POSITION 54 54 54 4 E Seo Se Se Sa Se Se Sp Se Sa Se Ss EXIT SHORT GROUND FAULT CODE 15 EXECUTED 9 wa ve se te EVEN MS IF 2MS GF TIMER gt 2 2MS GF TIMER 2MS GF TIMER 2 9 5a te CHECK FOR GF CHECK 07MS T 4 4 IF T 07MS gt 7 T 07MS T 07MS 7 GET INST TABLE IF KILL SERIAL BIT 1 GOTO CHECK LT MEMORY SERIAL CHECK LT MEMORY IF SET A
114. IMER reaches 0 RETURNS INST TIMER reset to 200 or leaves if an active counter is encountered USED ACCA RESTORED NOTHING 4 4 e ta 5a t 5e gt we t se ve to OPERATION HAS BEEN COMPLETED s eeez sueeweweeesee INST TIMER RST BRSET INST FLAGS I TIMR BIT GO TO MAIN 214 there is an active timer leave LDAA 200 get value to reset timer to 100 mSec STAA INST TIMER reset the timer TO MAIN EQU Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING LDAA value to null reset timer STAA INST RESET TIMER null the timer RTS RETURN TO MAIN 29 wow YR AOROROROR OR ERO HORN rts Slt go do d INTERRUPT routine to handle Output Compare Register Interrupts THIS OUTPUT COMPARE REGISTER INTERRUPT IS PROGRAMMED OCCUR CONTINUOUSLY EVERY 500 MICRO SECONDS OR 5 MILLISECONDS THE INTERRUPT CODE DOES THE FOLLOWING EVERY HALF MILLISECOND 1 CLEAR TIMER INTERRUPTS AND RESET THE COMPARE REGISTER TO ANOTEER 500 MICRO SECONDS BY ADDING 970 DECIMAL TO THE CURRENT FREE RUNNING 16 BIT TIMER COUNTER 970 takes into account interrupt latency time 74 4 T Te Se Se Se 5e Se IF THERE ISN T A SOFTDOG TRIP STROBE HARDWARE WATCHDOG BIT ON 7 5 ot te N 3 INITIATE HI GAIN READ 4
115. INDX LSRB from word to a byte boundary 5 089 928 71 78 DECB make type 0 1 2 3 4 5 BLE READ SW IN REG Y MULT BY TWO EQU MUL MULTIPLY TO FIND CORRECT ROW FOR BREAKER ASX add breaker offset to x meg ates read and calculate the switch position to add to the x rescister READ SW IN REG Y EQU LDAB 0 read the switch value ANDB SW POS OFF 0 BRSET FLAGSS WRD ALIGN BIT NOT DBLWRD IF SET BRANCE amp DON T SEIFT LSLB 32 word boundary NOT_DBLWRD 5 ABX ADD TO INDEX X TO POINT TO CORRECT VALUE RTS 7GO KROME STISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTISTI DJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTSADJUST LT VOLTS Y Y TET rtYYTTEEY ADJUST LT VOLTS THIS SUBROUTINE CALCULATES THE LONG TIME MEMORY CAP ACCUMULATOR VALUE THEN COMPARES IT TO TEE LONG TIME ACCUMULATOR AND ADJUSTS THE VOLTAGE ACCORDINGLY turns portD bit 5 on or off H Square D Company ADE Group Jerry Leon Durivage Date 8 16 85 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING THIS ROUTINE IS CALLED WITH INDEX X SET FOR FLC OR LT RATIO TAZIE or on power up to 97 ratio tables Se te If SET_ACCUM_BIT is set we have powered up with a voltage on the LT FLC memory cap and the LTA is restored RESULT is used to return accumulator value from memory BESSEREN ERE EY AORO
116. IWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWAI H THIS ROUTINE READS TEE EEPROM AND STORES THE DATA INTO THE CORRECT 2 LOCATIONS FOR HISTORICAL DATA Square D Company ADE Group Jerry Baack Leon Durivage ADDRESS WEE MUST BE CALLED FIRST TO POSITION THE DATA POINTER TO TEE CALLED WITH OR IY SET TO ANYTHING ALL VARIABLES IN THESE LOCATIONS ARE DESTROYED EEEE E E Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING Tbv 35 000 value to indicate sending address LDX REGSTART index location for port D BSET PORTD X SDA zset clock amp data lines high BSET DDRD X SCL SDA set data amp clock for output BSET PORTD X SCL set the clock high NOP need to add delay for EE timing NOP this is to make sure start timing NOP sufficient time BCLR PORTD X SDA set data line low for start bit 1 address for reading data JSR SEND ADDR zgo send read command 2 after returning the scl Tine low LDY TRIP start of historical RAM locations EQU A 08 78 bits byte NEXT EQU BSET PORTD X SCL set clock high to hold data BRCLR PORTD X SDA CLRC BIT see if this works to replace next 3 lin brset takes 2 less instruction cycles SEC set carry for 1
117. L 01 CURRENT LEVEL IS ABOVE PICK UP LT 908 1 PIT EQUAL 02 CURRENT LEVEL IS ABOVE 90 OF PICKUP EQUAL 01 CURRENT LEVEL IS ABOVE PICK UP PUSOS 1 BIT EQUAL 02 CURRENT LEVEL IS ABOVE 90 OF PICKUF SET ACCUM EQUAL 04 bit set until LT FLC accum is set on power 672 1 EQUAL 508 JLT ACCUM gt ZERO FIT GTZ BIT EQUAL 08 FLC ACCUM gt ZERO PEASE CONV EQUAL 10 to do phase serial conversion PEASE CONV EQUAL 20 flag to do phase serial conversion PEASE CONV EQUAL 40 to do A phase serial conversion START OF LT FLC FLAGS BIT DEFINITIONS RARER ER puree START OF SC LRC FLAGS DEFINITIONS dese de de de de e de de e e e de de e fe de efe ede ede de de e dee T 1 PU BIT EQUAL 01 short time pick up flag bit LR PU EQUAL 01 locked rotor pick up flag bit DOUSLE ST 12 EQUAL 802 double ist 122 calculation INST PU EQUAL 10 nst pickup flag bit I EQUAL 20 7 instantaneous timer is active bit INST EQUAL 540 set if ST installed amp INST is of px END OF SC LRC FLAGS BIT DEFINITIONS eov dede dee START OF INTERRUPT FLAGS desse jede deed eee gode dde MSBIT EQUAL 01 BIT NUMBER FOR 1 MS IFLAGS TRIPPING EQUAL 80 BIT SET TO KEEP INST FROM RUNNING IN INTERRUP
118. LE NIBBLE TEMP2 LADR LTEMPH ACC COMPLEMENTED LONG TIME SWITCH HIGH NIBBLE ACSC HD NOP ST DLS POINT TO AMP HIGH NIBBLE TEMP3 COMPLEMENTED LONG TIME SWITCH HIGH NIBBLE ACSC NOP ST DLS POINT TO AMP VERY HIGH NIBBLE LAI COMPLEMENT NIBBLE FOR LOW 2 NIBBLES ACSC HL C NOP ST DLS POINT TO AMP SUPER HIGH NIBBLE TEMPS ACSC RT NO CARRY STOP ITTERATIONS CALCULATION DONE ST GJMP TCS2 5 089 928 165 166 DC MD C E ROM LOOKUP ROUTINE FOR BREAKER RATING ENTER AMP2 amp ORG 100H 040H 0DO0H DCAH D1DH 060H DCA4H O6BH OFOH OBSH D80H 005H DACH DB O010H0A0H00 Sie DBH AMP2 LAMT RT A3NCREMENT THE TRIP CURRENT SETTING COUNTER TCS2 RC 1 LHU POINT TO TRIP CURRENT SETTING LOW NIBBLE ACSC GJMP TICS CARRY STORE AND DO ANOTHER ST L OOH 0 LHU BRM POINT TO TRIP CURRENT SETTING MIDDLE NIBBLE ACSC GJMP TICS CARRY STORE AND DO ANOTHER ITERATION ST LA 0 POINTTO TRIP CURRENT SETTING HIGH NIBBLE ACSC TICS GJMP TCS CARRY STORE AND DO ANOTHER ITTERATION RT CARRY ERROR AND CONTINUE BAR GRAPH DISPLAY CONTINUED CALL AS LA ACSC GJMP BO CARRY THEN S
119. LEASE JSR stroeb SD BCLR TRIP STATUS 570 CLEAR TRIP CAUSE BSET STATUS BYTE 40 CAUSE OF TRIP AS gf TRIP BSET MAX_IDENT 03 clear max phase LDAA GF TRIP get of trips ANDA 63 max trips to store 63 check for max trips BES count INC GF TRIP CNT increment of SC TRIPS JMP GLBAL 209 set up for jump to global trip Gr 5 CLR GF TRIP clear counter for rollover G_GLEAL EQU 5 LDX REGSTART LDAA GF_RES_OUT value to turn on GF trip line STAA turn line on STAA TRIP FLAG 5 for display BCLR LT TRIP CNT 40 cause of trip long time BCLR PU TRIP CNT 40 of trip phase unbal BCLR SC TRIP CNT 40 cause of trip short circuit BSET GF TRIP CNT 40 cause of trip fault BCLR SOFT TRIP CNT 40 cause of trip soft dog BCLR FLAGSS KILL WATCHDOG BIT snot soft trip so clr kill bit 32MS 32mS delay CHECK 60 CHECK TRIP VOLTAGE 1 13MS CALLED Every 13 5 from main or motor flow code RETURNS GF peak cleared GFPU set cleared as appropriate p communicatiions bit set cleared as needed and sleeps 1 2 out timer if needed
120. M BYTE 0 LADR RDY TESTFOR DATA READY FLAG SKAEI NOT SET CONTINUE GJMP FLAG SET RETURN OFH PHASE SELECT BYTE SKAEI O8H GJMP P31 1 FOR PHASE GJMP 31 SKAEI O4H BPHASE GJMP E NEITHER A OR B RETURN O3H 3FORBPHASE GJMP 4 SKAEI 3 BYTE XADR CHECKSUM BYTE 0 READY FLAG 0 XADR ROY RESET DATA READY FLAG SKAEI ROY WAS SET XFER PREVIOUS PACKET CALL XFER LAI BCI 1LONG TIME SWITCH GJMP TEST FOR BYTE COUNT lt 6 IF NOT RETURN IF T IS PROCESS THE DATA Bl BC ACC BC SKAEI 07H 7 RETURN GJMP 82 GJMP E B2 XAE BC IES E 1 XADR BC STORE NEW LADR BC ACC SKAEI 07H BC 7 VERIFY CHECKSUM AND SET DATA READY FLAG IF CORRECT GJMP B3 TEA SERIAL LOW CHECKSUM POINT TO CHECKSUM SKAEM CHECKSUM GJMP E LAI SETDATA READY FLAG XADR ROY LADR PTEMP XADR TPAK GJMP El ADD CHECKSUM SAVE DATA IF REQUIRED B3 HL POINT TO CHECKSUM TEA SERIAL LOW NIBBLE ASC ACC SERIAL LOW CHECKSUM NOP ST STORE CHECKSUM TO BYTE COUNT SELECTOR LADR BC SKAEM 1 GJMP B4 4 SENSORBYTE SKAEM GJMP HB GJMP B5
121. ME CODE CHECK FOR ST LDAA T 2MS ST 2 mS short time timer 2 scheck for expired ST timer PEAK COMM if ST timer greater run ST JMP EVEN MS else do GF routines DO PEAK COMM EQU SUBA 2 subtract 2 from timer to reset STAA 2MS ST save timer again JSR SET PHASEA PEAK peak routines for ST amp Communicatn ST INSTALLED EQU WE HAVE SHORT TIME INSTALLED IN TRIP SYSTEM BRCLR FLAGSS NO ST BIT SHORT TIME TEST PU IF CLEAR CHECK FOR IS 5 089 928 51 52 Square D Company ADE Group Jerry Baack Leon Durivage 8 16 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING INSERT CHECK FOR SC PHASE BITS IN CASE OF NO ST JMP EXIT SHORT TIME ST SET SO DON T DO SHORT TIME SBORT ROUTINE TO TEST FOR SEORT TIME PICK UP SSSSSSSSSSSSSSSSSSSSSSSSSSSSS SEORT TIME TEST PU EQU TEST SHORT TIME FOR PE OR ALL OTHERS LDX ST_PU_TBL set for usual brkr type FLAGSS PE BIT READ 51 SW if bit set brkr type is PE LDX PU TBL ibit Was set so use the PE breaker table LDAB SENSOR sensor size ANDB SWITCE_MASK mask off unused bits 1 max sensor size FOR PE2000 if less check for PE LDAB 4 51 load with max sensor FOR PE2000 EQU 512 compare to 2000A sensor BLO READ ST SW zif lt 2000A sensor use norma
122. ND C PHASE IS STARTED ADR3 REGSTART STAB HI PHASEC CMPB 5 6 BLS USE HI PHASEC GET PHASE C HIGH GAIN A D save value for check in trip routine USE LOW GAIN PHASEC SQUARE IT AND ADD TO THE PHASEC SQUARE SUM LDAA 1 PHASEC zgo 172 summation THIS POINT EITHER LOW OR EIGH GAIN HAS BEEN STORED TO CUR FOR USE IDAB 6 MUL STD CUR JMP DO PHASEC SUMMATION USE HI PHASEC uis CLR PHASEC STAB CUR 1 DO PHASEC SUMMATION EQU TBA BEQ LAST C ADD ADDD RMS SUMSQ 3 STD RMS SUMSQ 3 BCC WORD C OK LDX RMS SUMSQE 3 INX STX RMS SUMSQH 3 move low byte to for 0 check smultiply low byte by low byte double to low 16 bits save it if carry set increment the high byte save it 5 089 928 139 140 EZ WORD C OK EQU 5 LDAA 5 1 low byte LDAB CUR PHASEC iget high byte for 0 check BEQ SQUARE if high byte 0 we s done MUL 1512 result is shifted to multiply by 2 same as 2 multiplies amp add ADDD RMS SUMSQH 3 1 low high to middle 16 bits STD RMS SUMSQE 3 1 zand save it BCC LAST C ADD INC SUMSQE 3 Carry was set increment the high byte LAST_C_ADD LDAA CUR PEASEC get high byte BEQ SQUARE DONE if 0 we re finished TAB move to ACCB MUL multiply for last value ADDD RMS SUMSQH 3 to high 16 bits
123. O PE No calling requirements reads and reports breaker type UPON RETURN 5 ACCB is equal to 2x the breaker type breaker type is PE then PE is set in FLAGSS else PE is cleared 255555555555555555555555555555555555555555555555555555555555555555555555555555 READ BREAKER SW EQU LDAB READ BREAKER TYPE SWITCH ANDB SWITCH_MASK mask unused bits BEQ FOR PE 1 0 default to PE 50 0 is DS breaker BHI FOR if gt 0 default type 508 PE is type 08 BEQ SET FOR PZ to PE BCLR FLAGSS PZ clear PE bit in flags JMP SET FOR PE LDAB 508 get type for BSET 55 set PE bit in flags BRKR SET RTS all done return to calling routine 65 lt 55555555555555555555555555555555555555555555555555555555555555555555555555 SHORT TIME PRE CALCULATION FUNCTIONS ARE Only IY is not used for calculations in this routine CALLED With LAST B and C PHASE holding RAW low gain A D valu RETURNS A B and PHASEX6 holding values to use for ST calculations LAST A B C PHASE cleared for next 2mSec peak in interrupt ST and max phase set for communications routine use i Receiving SC restraint bit set cleared in comm buffer AUR RUN ew EQU LDAA
124. O ROME timer is already 0 so leave DEX decrement counter STX SOFT DOG TIMER2 restore timer GO HOME RTS return 5 089 928 145 146 PAGE ALL PICK UP AND DELAY TABLES IN THIS LOCATION TITTITITITITIT COMMENT gt BBBB L 5555555 T A B B L E S T AA B B L E S T ARAAA BBBB L EEEEEEE 5555555 T B B L E S T A A B B L E S T A A BBBB LLLLLLL EEEEEEE 5555555 INSTANTANEOUS PICK UP TABLES 1 FOR ALL BREAKERS EXCEPT THE PE INST PU TBL 41 61 82 102 123 164 205 246 FOR TEE PE BREAKER INST PE PU TBL EQU DW 41 51 61 82 102 123 143 164 INST 2000A PE DW 41 51 61 72 82 92 103 123 LI INST 2500 EQU 5 DW 41 45 51 61 72 82 92 102 Stable is shifted to allow for working of INST routine swith ST INPU switch value is shifted up 1 position SHORT TIME PU TABLE ST PU DW 246 308 370 493 617 740 987 1234 ST PU TBL PU TABLE FOR PE BREAKER ONLY DW 246 308 370 493 617 740 863 987 57 2000A PE EQU PU TABLE FOR 2000A BREAKER ONLY DW 246 308 370 430 493 553 617 740 ST 2500A PE PU TABLE FOR 2500A PE BREAKER ONLY DW 246 270 308 370 430 493 553 617
125. OOT guess LDD RMS MEAN 1 get mean for dividend IDIV the division LSLD start shifting to clear low LSID nibble to bring in next 1512 nibble to continue division process LSLD yall shifts done low nibble is clear STD REMAINDER save remainder for use XGDX put ACCX into to work with quotient LSLD start shifting quotient 1512 to make room for next LSLD division result LSLD least significant nibble now clear STD RESULT store off the result LDAS RMS MEAN 3 low byte of mean value LSR2 do 4 shifts to move LSR3 the high nibble to LSR3 the low nibble LSRB shifts all done CLRA clear out high byte ADDD REMAINDER sadd remainder to low nibble for new dividerc LDX gt RMS SQROOT iget divisor again for next divide IDIV sdivide LSLD shift the remainder 1510 to room for LSLD the final nibble 1510 slew nibble now 0 STD REMAINDER store off remainder for later use XGDX Swap to get quotient into ADDD RESULT new result to last result LSLD dc four shifts 1512 to make room for 1519 the next nibble 1510 shifting all done 572 RESULT save the result 5 089 928 119 120 RMS 3 get low byte ANDB 40FH mask off high nibble CLRA clear high byte of ADDD REMAINDER low nibble to the remainder LDX RMS SQROOT divisor IDIV divide LSLD multiply remain
126. OR e de BRCLR FLAGSS REBUILD GF RESET GF JMP RESET INST mem active so do INST GF EQU LDAA 33 15 load GF unrestrained timer value TAA GF_FTIMER GF unrestrained timer LDD 4250 GF after 1 4 second STD GF RESET RETENTION TIMER LDD 4SFFTF RESET VALUE NULL STD GF LONG TIME to timer RESTRN TIME RESET RESTRAINT TIMER LDAB GFDELSW read the delay switch ANDB SW POS mask off bits not wanted 2 3 smaximum 172 out position BLS GF LONG TIME 172 out so branch BSET GF FLAGS DOUBLE 12 set flag to double first 172 value JMP RESET INST go do INST stuff SzT GF LONG EQU LDX 6 FIXED DEL START LOCATION OF FIXED DELAY TAZIE LDY GFDELSW GF SWITCH ADDRESS LDAA 48 MULT BY 8 OF ENTRIES PER ROW BSET FLAGSS WRD ALIGN 1 WORD BOUNDARY JSR SET TBL INDX CALL INDEX ROUTINE 100 0 LOAD TIMER VALUE FROM TABLE SUBD 15 subtract INIT time for GF STD GF LONG TIME save to timer BSET LONG TIME T INACTIVE put timer to sleep When the retention timers time out the ST amp GF will be reset to norm values H 5 089 928 41 42 RESET INST EQU Square D Company ADE Group Jerry Baack Leon Durivage 8 16 85 SERIES ELECTRONIC TRir SYSTEM SOFTWARE LISTING 5 to reset IN
127. OTOR PROTECTION USED MEMORY TRI APHASE RB 2 storage for LRC pick up check LAC RMB 2 I storage for LRC pick up check CPHASE RB 2 1 storage for LRC pick up check 2 TNERL PEAK RMB 1 phase unbalance RMB 2 SUM OF ADDING PHASE RB 2 PEAK SQ ROOT FOR LAST 64 MS RMB 2 PEAX OF MODIFIED SQRT FOR MOTOR CODE 2 2 START OF SQUARE ROOT CALCULATION USE AREA RMS MEAN RMB 2 HIGH WORD OF 2 WORD MEAN PMS RMB 2 BYTE OF 2 WORD MEAN RMS_SQROOT RMB 2 REMAINDER 2 location for remainder storage TEMP RS 2 716 BIT WORK AREA 2111 TEM IS NOT CONFINED TO RMS CALCULATION USE ONLY 111111 a SUM SQUARES deese ye eoe dede de e de e defe ee de ee ie e dede x RMS SUMSQRH RMB 2 iA phase HIGHEST OF TWO WORDS RMS SUMSQ i Ra 2 LOW BYTE OF LOW WORD X Rus_SUMSOH 2 RMB 2 phase x RMS SUMSQ 2 RB 2 x RMS SUMSQH 3 RB 2 C phase x 5 SUMSQ 3 RB 2 x 22 poete FLAGS ACCUMULATORS amp TIMERS FOR FUNCTION USE t xeeeeeee p IN GENERAL TIMERS USE 7 80 FOR THE SLEEP w r rrwxttt t r AND THE VALUE 522 FOR TEE RESET CONDITION rwetwew 1 tr x ttt CHECK ROUTINES FOR ACTUAL CONDITIONS wwrwreruewwkd eee INST TABLE VAL RMB INST TIMER RMB storage for table pointer resets the inst timer to 100 5 FLC FLAGS
128. OW NIBBLE RATING LOW NIBBLE RATING LOW NIBBLE RATING LOW NIBBLE RATING LOW NIBBLE CHU AMP RATING LOW NIBBLE CL GOTRATING LHU CL GOTRATNG RATING LOW NIBBLE 200 5 089 928 201 202 ADDRO RATING LOW NIBBLE CALL AMP9 CALL ARAT AMP9 GJMP CL RATING ADDR1O RATING LOW NIBBLE AMPIO CALL AMPIO GJMP CL RATING ADDR11 AMP RATING LOW NIBBLE AMPI CALL CALL 11 GJMP ADDR12 LHL BTI RATING LOW NIBBLE CALL 12 CALL 12 GJMP GOTRATING ADOR13 LHU RATING LOW NIBBLE CALL CALL AMP13 05 BT4 ST STORE RATING HIGH NIBBLE TRAT CALCULATE RATING TIMES CALL BRAT CALCULATE RATING BASED ON LTS COMPLEMENT TRIP CURRENT SETTING RT 3 5 5 PRCNT PERCENT OF TRIP RATING BAR GRAPH DISPLAY 5 5 15555556556655556555555555555555555555555555555555555555555555555555555555555 COMPLEMENT THE RATING TO PERFORM SUBTRACTION CALCULATE CURRENT TIMES TEN THE COMPLEMENTED AMP RATING TO THE RUNNING CURRENT OVER AND OVER UNTIL CURRENT IS EQUAL TO ZERO THE NUMBER OF 5 IS THE NUMBER TIMES PERCENT OF OPERATION LAI
129. P UNIT GOTO CE ECK TIMR 0 E Square D Company gt ADE Group Jerry Baack Leon Purivage Date 8 1 6 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING EZCK 1 SEC IF T 1000MS lt 4 GOTO CHECK 0 ELSE T 1000MS T 1000MS 4 SENSOR BREAKR IF SOFT DOG CNTR RESET GOTO CHECK 0 ELSE DEC_SOFT_DOG TIMA 0 CEECK ALL 5 GOTO MAIN FLOW Biniiiiiii END PSUEDO CODE MAINS 755 559555555555555555 MAIN EXEC FLOW 555555555555555555555555 BRSET GF 5 PU GF RESTRAINT if set go check for rest vies JMP SCPU SHORT CIRCUIT PICK UP check odd even mS RESTRAINT 5 Tr WE GET HERE WE HAVE gf PICK UP SO ADJUST TEE RESTRAINT HOLD TIMER 11 STAA TIME istart restart SC restraint timer DO SCPU CEK EQU INST OR ST PU FLAGS THE RESTRAINT HOLD TIMER BRSET INST FLAGS INST PU BIT CHK RESTRAINT if set go check for rescraint BRSET ST FLAGS ST PU RESTRAINT if set go check for restrai JMP FOR ST NO SEORT CIRCUIT PICK UP check odd even mSec RESTRAINT WE GET WE HAVE A SC PICK UP SO ADJUST THE RESTRAINT HOLD TIMER LDAA 10 STAA 5 RESTRN TIMER start restart SC restraint timer CODE HERE CHECKS 2MS TIMER FOR ST 2 TIMER gt 2 DO SHORT TI
130. PAGE ORIGIN 5 RESERVED FDB RESERVED2 FDB RESERVED3 FDB RESERVED4 FDB RESERVEDS FDB RESERVED6 FDB RESERVED FDB RESERVEDS FDB RESERVED9 FDB RESERVEDA FDB RESERVEDB FDB SCI INT FDB 5 INT FDB PATI INT FDB INT FDB TOV INT FDB CHECK RAM RETENTION RAM REMEMBERS 5 510 0 SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT SOFTDOG INTERRUPT next 16 bit check clear so error bit not set passed test move for formatting set vp for transmit format set error bit store error return good or error set FFCO 2 3FFC4 FFC6 2 FFD4 FFD6 5 089 928 159 160 TOC INT FDB SOFTDOG INTERRUPT TOC4 INT FDB SOFTDOG INTERRUPT 2 TOC3 INT FDB SOFTDOG_INTERRUPT FFE4 TOC2_INT FDB SOFTDOG_INTERRUPT FFE6 TOC1_INT FDB INTERRUPT T1C3 INT FDB SOFTDOG INTERRUPT FFEA TICZ INT FDB INTERRUPT INT FDB SOFTDOG_INTERRUPT RTI INT FDB SOFTDOG_INTERRUPT INT FDB SOFTDOG_INTERRUPT FFF2 XiRZ INT FDB SOFTDOG INTERRUPT FFF4 INT FDB SOFTDOG_INTERRUPT 6
131. PIRED YET BLO TEST GO SEE IF TIME TO DO PHASE B RMS BRCLR LT FLAGS B PHASE CONV TEST PHASEC Conversion bit is set do serial comm and phase unbalance routines BCLR LT_FLAGS B PHASE CONV CONV DONE SO CLEAR FLAG LDX 5 SORT PHASE RMS VALUE LOCATION JSR PHASE UNSALENCE CALCULATE B PHASE UNBALANCE LSRB convert to 1 value for serial com 5 089 928 59 60 STAB PHASEB UNEAL STORE PHASE UNBALANCE LDX SERIAL POINTER to see if we are sending A phase curren CPX B PHASE RMS 2 BNE SERIAL CONV B ok to convert JMP TEST 64MS GO CHECK FOR 64 mS DO SERIAL CONV B LDY 5 SQRT a phase square root location LDX PHASE RMS storage location JSR CONVERSION go do transmit conversion amp storage BCLR LT_FLAGS 8 PHASE CONV CONV DONE SO CLEAR FLAG TEST 64 5 CHECK FOR 64 mS Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING TEST PHASEC LDAA T_PHASEC_RMS PHASE RMS TIMER 64 HAS 60 MS EXPIRED YET BLO TEST PEASEC 2MS WE CYCLED ALL 64 MS SUBA 64 reset the timer STAA RMS PHASE C TIMER LDX SUMSQH 3 location of squared SUM FOR CHAN 3 JSR AVG AVERAGE I 2 VALUE CHAN 3 LDD RMS SQROOT 50 ROOT FROM AVG ROUTINE STD SQRT LAST 64 MS SQ ROOT OF I FOR CEAN 3 BSET LT FLAGS C PHAS
132. Preferred component values are for example part No 2N6285 for Darlington transistor 568 1N4739 for zener diode 570 and 220 ohms for resistor 572 At the emitter of the transistor 568 the power signal trip voltage is provided The 5 v signal is a regulated 5 v power supply output signal that is provided using a voltage regulator 571 part No LP2950ACZ 5 0 and a capacitor 582 which prevents the output of the regulator 571 from oscillating The volt ge regulator takes its input from VT via a diode 576 The diode 576 charges capacitor 584 to within one diode drop 0 6 v of VT and creates a second supply source of approximately 9 v which is referred to as the 9 V power supply The energy stored in the capacitor 584 enables the electronic cir cuitry being powered by the 9 V power supply to remain powered for some time after a trip occurs capacitor 574 connected at the emitter of the transistor 568 aids in filtering voltage ripple The capacitor 574 is also utilized as the energy storage element for the sole noid 112 which is activated when a power IGFET 583 is turned on by signals from the microcomputer 120 in FIG 1 or from a watchdog circuit 712 in FIG 8 The trip signals are combined by respective diodes 591 593 The solenoid 112 is also activated by an over voltage condition sensed by a 16 volt zener diode 595 such as part No 1N5246 Preferred component values are for example 220 microfarads fo
133. RB 0 pointer for flags LT FLAGS RB 1 BITS USED FOR LT LOGIC FLC ACCUM RMB 0 pointer for FLC accumulator LT 4 4 BYTE I 2 ACCUM FOR LONG TIME ST FTIMER 1 ST FIXED UNRESTRAINED DELAY 33 MS LRC ACCUM RB 0 pointer for LRC accumulator ST ACCUM RMB 4 SHORT TIME I 2 4 BYTE ACCUMULATOR MER ROU ST_RETN_TIMER RB 1 short time retention timer ST I2 OUT TIMER RB 2 restrained ST delay timer SC RESTRN TIMER RMB 1 short circuit restraint timer LRC FLAGS 0 high bits used for locked rotor logic ST FLAGS RMB 0 HIGH BITS USED FOR SHORT TIME LOGIC INST FLAGS RMB 1 LOW BITS USED FOR INSTANTANEOUS LOGIC INST SWITCE RMB 5 storage for INST switch position 1 INST TIMER RMB i 2100 MS INSTANTANEOUS TIMER INST_CNTR_4 RMB i INST COUNTER FOR 4 PU S IN ROW PU_FLAGS RMB 0 HIGH BITS FOR PHASE UNBALANCE LOGIC GF LAGS RMB i LOW BITS FOR GROUND FAULT LOGIC RESULT RMB 4 HOLDS ANSWER FOR MULT 16X16 RES BUF RO 1 buffer space SERIAL COMMUNICATIONS HOUSEKEEPING VARIABLES ARE HERE D Square D Company Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING PACKET PTR RB 1 pointer for current packet being transmitted RB 1 TO NEXT DISP CHAR 5 089 928 33 34 SERIAL POINTER RMB 2 pointer to byte that was last sent HOLDER 1 5 3rd packet to transmit INTERRUPT a
134. SENS2500 DW 90 1 SENS3000 56540 SENS3200 DW 6049 SENS4000 53 04 GF I SQ DEL TEL EQ 5 PE 2000 LONG 2017473 1226116 698544 258901 SE 2000 LONG 2061438 1270080 742508 302865 5 2000 LONG 1929545 1138187 610615 170972 5 089 928 149 150 Sz 2500 LONG 1319320 812851 475205 193834 Ds 2500 LONG 1234909 728440 390794 109422 52 3000 LONG 916194 564480 330004 113460 5 3000 LONG 857575 505861 271385 75988 Sz 3200 LONG 805249 496125 290042 118307 Ds 3200 LONG 753728 444604 238522 66786 SE 4000 LONG 515359 317520 185627 75716 Ds 4000 LONG 482386 284547 152654 42743 Square D Company ADE Group Jerry Baack Leon Durivage 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFIWARE LISTING 2500 TRIP TBL 2 LT PU LT PUS04 TBL LT RATIO TABLE DW LT RATIO SE De A LT 978 RATIO DW 52 LT 97 RATIO DW EQU LONG DW these values are used with 2500A 1291183 784714 447068 165697 LONG TIME PU TABLE 45 55 64 68 73 82 88 92 LONG TIME 90 PU TABLE 40 49 57 61 65 74 79 82 LONG TIME RATIO TABLES 6D
135. SOR_2500A DW 58 65 72 79 86 94 101 108 SENSOR 3000A DW 48 54 60 66 72 78 85 90 SENSOR 3200A DW 45 50 57 62 68 73 79 85 SENSOR 400A 36 41 45 50 54 59 63 68 GROUND FAULT DELAY TABLE 54 5 511 51 4E SAD 11F 1CA DW 54 54 9 511 51 6 DW 99 10B 1B6 DW 543 5 2 5114 51 528 587 5 9 51 4 150 DEL LONG 500000000 500000000 500000000 500000000 LE LONG 2115172 1323814 796242 356599 LONG 500000000 00000000 500000000 00000000 ME LONG 2115172 1323814 796242 356599 LONG 500000000 500000000 500000000 500000000 NE LONG 2095632 1304274 776703 337060 LONG 500000000 500000000 00000000 00000000 LONG 2017473 1226116 698544 258901 LONG 500000000 500000000 500000000 500000000 SE Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFIWARE LISTING LONG 2061438 1270080 742508 302865 LONG 00000000 500000000 500000000 500000000 5 LONG 1929545 1138187 610615 170972 TABLES ARE PADDED WITH 0 s SO SET TBL INDEX ROUTINE WORKS CORRECTLY p r tables below are used to limit I 2in values to 2000 A max for delay Calculations eeewewwewee eee eee eee eee ERATE MAX_GF_ATOD_TBL EQu 2000 252 52500 DW 201 3000 DW 168 3200 157 54000 126 MAX GF ISQ EQU SENS2000 DW SF810
136. ST TRIP SEI NO MORE INTERUUPTS PLEASE TEIS SECTION CONTAINS TRIP CODE FOR SHORT TIME COMMON ST 5 BCLR SC PU GF 07 clear SC PU bits to set phase s gt PU IDX ST TABLE POS saved table position O X pick up value in double CPD 5 6 to phase for comm bits BHI TEST NEXT PHASE if PU gt value try next phase BSET SC GF PU S01 5 A PHASE SC TEST NEXT PEASE EQU Lo CPD PHASEX6 to B phase for comm bits BHI TEST C PHASE NEXT if PU gt value try next phase BSET SC PU GF 602 SET B PHASE SC BIT TEST C PHASE NEXT EQU 5 CPD C PHASEX6 compare to C phase for comm bits SC TRIP zif PU gt value try next phase BSET SC PU PU 04 5 C PHASE SC BIT Itt INST LRC TRIP USE COMMON CODE FROM THIS POINT ON DO SC TRIP JSR COP reset the softdog keep it happy LDX REGSTART li BCLR TRIP STATUS 970 CLEAR TRIP CAUSE BSET TRIP STATUS BYTE 20 SET CAUSE OF TRIP AS SC TRIP LDAA SC TRIP CNT get of trips ANDA 63 ymax trips to store 63 compare to max of trips BES SC clear count INC TRIP CNT increment 4 of SC TRIPS JMP 60 GLOBAL zif high bit clear leave Cin SC CNT EQU CLR SC TRIP counter for rollover GO GLOBAL EU LDX REGSTART LDAA 5 RESTR
137. ST function after 100 mSec have passedtkrrrkirwwrrrrwrri JSR INST TABLE INST switches for interrupt use 100 set time before resetting inst timer STAA INST RESET TIMER set time to reset INST timer P Historic data is read from the EEPROM before SPI is enabled JSR reset to finish out any bad data JSR ADDRESS WEE address the EEPROM for talking JSR READ read the EEPROM into RAM Turn on SPI and set up the micro to start runnung breaker code LDX REGSTART 25 6811 INTERNAL REGISTERS AT 1000 EEX LDAA 55 this turns SPI at 125kHz and as master STAA SPCR X turn it on LDAA TFLG1 X 7LOAD AND STORE TIMER INTERRUPTS STAA TFLG1 X TO CLEAR ALL INTERRUPTS LDD TCNT X get timer count ADDD 1000 7 1000 5usec 500usec interrupt STD TOCLl X load back into output compare register 1 BSET 5 1 580 sallow output compare register 1 CLI enable all interrupts END OF ALL INITIALAZION FOR SERIES III xxxi eee ee PSUEDO CODE FOR MAIN EXEC 22 5 IF GROUND FAULT PICKUP GF RESTRAINT TIMER 14 5 IF SHRORT CIRCUIT PICKUP ST RESTRAINT TIMER 10 MS CEECK FOR ST IF 2MS ST TIMER gt 2 2MS ST TIMER 2MS ST 2 SET PHASEA PEAK IS ST INSTALLED IF SHORT TIME IS INSTALLED GOTO HORT TIME TEST m GOTO EXIT SHORT TIME SHORT TIME TEST PU
138. START OF TAELE PLACED IN TEMP CLEAR TEE DOUBLE ACCUMULATOR IF SENSOR VALUE IS ZERO SzT TO ZERO EQU CLRA CLRB ADD TEMP EQU ADDD GF PU ADD GF PU TBL ADDRESS TO SENSOR CALCULATION XGDX TABLE POSITION IN DBL ACCUM SET IN X LDAB GFPUSW READ GF PICK UP SWITCH IN ACCUM B ANDB SW POS MASK ALL BITS EXCEPT VALID SWITCH BITS ABX ADD SWITCH VALUE TABLE INDEX STX GF POS save for comparison in GF l3mS routine CLRA clear high byte LDAB GF PEAK PEAK OF GF VALUES FOR LAST 1 2 CYCLE CPD VALUE TO TASLE BHS GF PICK UP ATOD IS ABOVE THE TABLE RUN GF ROUTINES GF OFF PICK UP GF PICK UP CAN BE SET HERE BUT ONLY CLEARED IN THE 13 mSEC PEAK ROUTINE LDX REGSTART 36811 REGISTER BASE ADDRESS BSET PORTA X GF_RES OUT TURN ON GF RESTRAINT LINE BSET 1 65 6 PU PU WE HAVE BSET SC PU PU S40 FOR IN BUFFER Sqeare D Company ADE Group Jerry Baack Leon Durivage Date 8 16 65 SERIES III ELECTRONIC TR SYSTEM SOFTWARE LISTING set reset the 11 mSec restraint time the retention timer LDAA 11 11 MS TIMER STAA RESTRN TIME 5000 45 Sec TIMER STX GF RETN TIME GFDELSW READ GF DELAY SWITCH ANDB SW POS MASK OFF BIT O 1 TEE ABOVE IS TO ALLOW TIME FOR THE SLEW RATE OF THE RESTRAINT OUT LINZ The filter slows the restraint
139. T LOCATION PULX get storage location LDD RESULT 1 sget result low byte CPD MAX_SERTAL I transmission value BLS SERIAL_DATA_OK serial is in good range LDD MAX SERCAL 1load max value to indicate full scale SERIAL DATA OK EQU 15 0 clear low bit shift high bit to carry LSRB shift low byte back to 7 bits ANDA 57 mask off high bit STD 0 5 high byte RTS YO JOE WE RE DONE GO HOME eee SENSOR BREAKER ROUTINE FOR TRANSMISSION t 2 299 CALLED Once every second no values are passed to routine RETURNS Sensor and Breaker type information in serial comm buffer fc J transmission USED ACCB RESTORED NOTHING 4 te 9 t SENSOR 5 BCLR MAX IDENT 3C clear breaker type xmit byte JSR READ SW 15 8 shift into correct position for xzit byte ORAS IDENT combine with max phase data Sqcare D Company ADE Group Jerry Baack Leon Durivage Date 8 16 8 5 089 928 123 124 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING STAB IDENT store back to xmit byte LDAB SENSOR read the sensor ANDB 5 mask it CMPB 1 check for gt max sensor BLS SHIFT sensor ok
140. T LT FLAGS LT 090 BIT PHASE IN PU if gt 90 PU find phases BCLR SCRIN S3F clear all 90 amp PU bits JMP BITS done so leave PEASE IN PU IDX PU TABLE LOCATION PUSOS check 90 amp pu NOT MTR CODE CLR COMM BITS BPHASE CLR SER BITS TRY CPHASE CLEAR SER BITS 95 LTPUSW ANDB SW POS ARX ABY LDD PHASA_SORT CPD 0 BLO CLR COMM BITS BSET OVPU_SCRIN 09 JP BCLR OVPU_SCRIN 09 LDD SORT CPD 0 BLO TRY_BPEASE BSET OVPU_SCRIN 01 LDD PHASB_SORT CPD 0 BLO CLR SER BITS BSET OVPU_SCRIN 12 UMP TRY CPEASE EQU BCLR OVPU_SCRIN 12 LDD PHASE SORT CPD 0 BLO TRY BSET SCRIN 02 LDD SQRT CPD O X BLO CLEAR SER BITS BSET OVPU_SCRIN 24 JMP BITS SET BCLR OVPU_SCRIN 24 Square D Company ADE Group Jerry Baack Leon Durivage 5 089 928 96 LONG TIME PU SWITCH mask off unused readings add offset directly to IX add it to IY get phase square root to pick up if lower no pickup for phase pick vp igo check next clear PU bits get value it zif low do next phase set 09 pu in communications get phase square root to pick up zif lower no pickup set for A phase pick up
141. T PEAK RTS RETURN WITH DATA LT S4 COMM 5 SECTION DOES THE COMMON i SWITCH COMMUNICATIONS FOR LT FLC SWITCEES CALLED No variables passed to routine RETURNS LT SWITCHES set to Long Time PU amp delay values USES RESTORES NOTHING YY d ETTET TT T E T T T E E E E S E E E E E S a E E a S S a a iaai LT SW COMM LDAA LTPUSW get PU position ANDA SW POS mask off unwanted bits LSRA shift to low 3 bits LTDELSW get delay switch value ANDB SW POS off unwanted bits LSLB shift to high 3 bits LSLB 5 as above Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 898 SERIES III ELECTRONIC TR SYSTEM SOFTWARE LISTING ABA combine bits from ACCB STAA SWITCHES save for xmit 10 4 RIS e de e de ede dede e de de 132454544 ee dee SERIAL BITS dede de dede decide dede 5 SECTION SETS LT PU COMMUNICATION BITS w reeksurte ses CALLED Without any values passed t RETURNS Overload pick vp nformation for each phase in OVPU SCRIN communication buffer memory ve USES ACCB IX IY RESTORES Nothing EE LT SERIAL BITS EQU 5 LT FLAGS LT PU IN PU if in PU find phases BRSE
142. TART EQUAL 1000 Start of 64 byte Register Block RATING PLUG EQUAL 2000 iMemory location of Rating Plug nibble TRIP SUPPLY EQUAL 2001 15 supply amp Motor 72 Protection sensor location LIFUSW EQUAL 4000 Long Time Pickup Switch LTDELSW EQUAL 4001 Long Time Delay Switch FLCPUSW EQUAL 4000 Full Load Pickup Switch FLCDELSW EQUAL 4001 Full Load Delay Switch STPUSW EQUAL 4002 Short Time Pickup Switch STDELSW EQUAL 4003 Short Time Delay Switch LRCPUSW EQUAL 4002 Locked Rotor Pickup Switch SUMMATION Binary 540998 542022 542278 546247 558128 580628 615224 661449 717618 780118 845143 907643 963812 1010037 1044633 1067133 1079014 1082983 1083239 1084263 1090504 1105633 1132202 1170618 1220347 1279396 1343405 1407921 1468930 1522291 1564727 1595352 1614121 1622957 1625261 32505 180 180 312229 LRCDELSW INPUSW PUPUSW GF gt USW GFDELSW SENSOR 5 END Or PAGE 23 EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL 4003 4004 4005 4006 4007 8000 8001 5 089 928 24 Locked Rotor Delay Switch Instantaneous Pickup Switch Phase Unbalance Pickup Switch Ground Fault Pickup Switch Ground Fault Delay Switch memory location of sensor nibble location of type of breaker MEMORY MAP 1 pueeeeweere Register Block Address Assignment IN
143. TE pointer for byte to send EEQ SEND STATUS BYTE 1 byte 0 send status byte 06 112 byte 6 send address SEND ADDRESS senc address right before check sum LINDA 505 send checksum and go to next packet This section picks the correct byte from the correct packet saves the ipcinter to check for word wide conversion conflicts and masks the high bit 0 the byte being sent bytes 1 5 LDAB keep set to packet 0 LDAA 45 75 data bytes packet MUL get packet base _ BYTE pointer to correct byte ARX to serial buffer base STX SERIAL store for compare for 2 byte values INC BYTE set for next byte LDAA 0 put byte in ACCA ANDA 457 masx off high bit JMP CEEZCKSUM igo checksum before transmission SzND STATUS EQU up status byte here and start of checksum generation BCLR TRIP STATUS 50 packet in status PACKET packet being sent ORAS TRIP STATUS BYTE set correct status bits STAB STATUS BYTE store back to location BSET TRIP STATUS BYTE 80 set high bit to indicate byte 0 LDAA 0 get status byte INC BYTE point to next byte CLR CHECK SUM new packet clear checksum CHECKSUM start checksum EQU SZND ADDRESS used in present series3 communications INC BYTE LDAA ADDRESS
144. TE HIGH WORD ADCA 00 ADD WITH CARRY TO BRING IN ANY CARRY STAA RESULT STORE BACK TO RAM MUL NEXT BYTE EQU 5 BRSET FLAGSS I SQ BIT MUL LAST BYTE IF SQUARING DON T DO THIS MULTIFL LDAA 0 JEI BYTE OF MULTIPLIER BEQ MUL_RETURN IF EIGH BYTE 0 we are finished LDAB 1 Y LOW BYTE OF MULTIPLICAND ULTIPLY IT ADDD RESULT i STD RESULT 1 ADD RESULT TO COVER DOUBLE WORD BOUNDARY STORZ BACK INTO RAM BYTE HIGH WORD 74 5 te so LDAA RESULT 00 ADD WITH CARRY TO BRING IN ANY CARRY STAA RESULT STORE BACK TO RAM MIL LAST BYTE EQU 5 LDAA 0 BYTE OF MULTIPLIER BEQ RETURN 0 WE RE DONE LDAB 0 BYTE OF MULTIPLICAND BEQ RETURN 1F ACCB 0 WE RE DONE MUL MULTIPLY HIGH BYTES ADDD RESULT TO HIGH WORD STD RESULT STORE HIGH WORD BACK RAM RETURN BCLR FLAGSS I SQ CLEAR SQUARE RIS RETURN t wxw w w wtt ws 9 x954qx 9 59 9xx m9 wen TTTTTTOTOTTUTTtTTUETTOUTRTTET9TY T t TtTtTU T t S t t te9ett te9tettttteve AVG takes the values in SUMSQ and does 1 rotate left and drops the low byte to get the averace of the square 128 X is loaded with the 02252 for sum location before the call The average is used to the square root by the NEWTON RAPHSON METHOD CALLED From main with IX pointing to the memory locaticn of the value Square D Company ADE Gr
145. TE STEP TO NEXT BYTE VARS WE CLEARED ALL VARS CLR MEM NO SO CONTINUE CLEARING AT THIS POINT TO ENSURE CORRECT INITIAL CONDITIONS pesas aaa see CHECK FOR INSTALLATION OF ST amp GF FUNCTIONS _JSR LDAA STAA SET OF TRIP UNIT go set trip unit type 50 VERSION software version revision level SOFT VERS save to transmit buffer location 5 089 928 37 38 SET INST FUNCTION FOR 94 mSEC ALLOW FOR POWER UP SET INST TO 20 mSEC IF SE DS WITH INST INSTALLED OR 90 mSEC IF INST NOT INSTALLED DISCRIMINATOR FUNCTION LDAA 188 100 5 6mS for initialization time STAA INST TIMER 5 the timer for all except ds LDAB TYPE read type of breaker ANDB SWITCH_MASK mask off bit 4 BEQ SET 10 is undefined brkr so set for CMPB 50 HEX C IS maximum legal defined breaker type BHI SET PE BIT brkr type is greater than OC default PE CMPB 450 0 SE 1 SE or DS we need discriminator AN SE ERKR discriminator isn t needed don t do IP WE ARE HERE WE HAVE DS or A SE BREAKER TEST FOR INSTANEOUS ON BRSET FLAGS NO ST BIT SET DS AT 20 no ST so INST must be on LDAB INPUSW ST 15 installed so read the INST PU switch ANDB SW POS mask off unused bits QPB PAX SW POS sis INST in off position 8 BNE SET DS 20 so set INST to 20 mSec LD
146. TERNAL 6811 REGISTERS OFFSET VALUES FROM 1000 We AO dx dede do dede 2 PORTA PIOC PORTC PORTB PORTCL DDRC PORTD DDRD PORTE CFORC OC1M OC1D TIC2 TIC3 TOCl TOC2 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE 5 TCTL2 5 TMSK2 TFLG2 PACTL PACNT SPCR SPSR SPDR BAUD SCCR SCCR2 SCSR SCDR ADCTL ADRL ADR2 ADR3 ADRA OPTION EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL EQUAL 00 02 03 04 05 07 08 09 0A 08 05 50 0 10 12 14 16 18 1A 1c 1 20 21 22 23 24 25 26 27 28 29 52 52 52 520 2 22 30 31 32 33 34 39 Port Data Register Parallel 1 0 Control Register Port C Data Register Port B Data Register Port C Latched Data Register Data Direction Register for Port C Port D Data Register Direction Register for Port D Port E Data Register Timer Compare Force Recister Output Compare 1 Mask Register Output Compare 1 Data Register Timer Control Register Timer Input Capture Register 1 Timer Input Capture Register 2 Timer Input Capture
147. TOP ITERATIONS ST IES INCREMENT COUNTER GJMP PC ANOTHER GJMP PCT2 28858 8 8 88 8 8 8 8 8 8 88 8 88 8 8 8 8 8 58 58 8 8 8 8 88 8 88 8 8 8 8 8 8588 8 8 8 8 8 8 88 3 amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT amp amp 28 8 8 8 RR RR c 8 888 E 8 BB 8 Sc cc S8 8 8 8 8 8 8 8 88 8 8 8 8 8 8 8 8 8 8 8 3 5 ORG MOH DB O60H 088H 034H DACH 010 DASH D68H O94H OCOH 088 082 DB 018H 070H 0 0 DB O11H 012H D13H O14H DB 15 217 E 1 1 2 1 1 1 1 1 1 1 3 1 T 1 1 T 5 0 1 1 1 9 3 0 3 0 2 0 1 T 1 9 1 amp amp CALCULATE BREAKER RATING TIMES TEN amp amp amp 555555555555 88555555555555555555555555555555555555555 MEMORY STORAGE AND COUNT VALUE TRAT LAI COUNTFORTEN NITIALCE DATA TO 00 TEMPI 2 BEER 5 089 928 167 168 DLS ST 05 ST DLS 5 ST ADD NUMBER TO ITSELF FOR TEN ITTERATIONS TRAT2 RC RESET CARRY LHU TEMPI LADR ACSC NOP ST DLS 2 LADR BT2 ACSC NOP ST DLS GJMP TRAT3 amp amp ROM LOOKUP ROUTINE FOR BREAKER AMP RATING ENTER AT AMP4 amp KEKE KKK EEEEE EEE KEE ERE EE ESKER 1 AAAA AA
148. TR of soft errors CMPA to reset value BNE NEXT ERROR already have 1 or more errors LDD 600 2600 seconds 10 minutes STD DOG TIMER start ist soft timer LDAA 4501 load 1 error STAA SOFT DOG CNTR clr flag 1 error JMP INIT 1 go reinitialize the trip unit Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 5 089 928 143 144 5 III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING NEXT ERROR LDAA 5 DOG CNTR get of errors 502 see if we have 2 errors already BHS SOFT TRIP zthis is error 3 go trip INC SOFT DOG CNTR 2nd error inc counter Lop 600 value for 2nd timer STD DOG TIMER2 save it to the 2nd timer JMP INIT reinitialize trip unit TRIP SEI turn interrupts off JSR reset the softdog BSET FLAGSS KILL WATCHDOG are trip don t strobe WD LDAA 5 2 CAUSE OF TRIP PACKET 2 STAA TRIP STATUS BYTE 5 TO TRIP CAUSE LOCATION LDAA SOFT TRIP CNT of trips ANDA 63 max trips to store CMPA 63 max of trips BES SF clear count INC of SC TRIPS JMP TRIP 216 high bit clear leave SF EQU CLR SOFT TRIP else clear soft trips TRIP EQU LDX REGSTART start of onboard regs CER PORTA X wait for watchdog trip BCLR LT TRIP CNT 40
149. UTINE ERREUR ERE SUBTRACTS 2 16 FROM ANY 4 BYTE ACCUM POINTED TO BY X SVE 2 16 219575 2 GET LOW WORD OF 4 BYTE ACCUM SUBD 0 X SUBTRACT HI WORD OF 4 BYTE ACCUM STD 2 X STORE LOW WORD OF 4 BYTE ACCUM 5 089 928 93 _ 94 BCC SUB CARRY CLEAR ALL DONE LDD 0 7GET HI WORD OF 4 BYTE ACCUM SUBD 1 SUBTRACT CARRY STD 0 X STORE WORD OF 4 BYTE ACCUM SUS RETRN EQU RTS wow moo odd d oe oe e Y EROR OE EE ORO d dee d dee d o e PUTA AERA eee eee END OF LONG TIME ACCUMULATOR DECREMENT eee ere e e wm 332253445444 4344444 FIND SQRT PK dt lt e e he e e ede e e de e ee e de d ROUTINE SETS THE PEAK RMS OF THE THREE PHASES CALLED No values passed uses square root memory values RETURNS With PEAK SQRT holding maximum square root value ET 9 USES RESTORES Nothing aeo de de de eoe e e ee e e e e deo deo e de de de de e dee dede dee deo dd dn IND SQRT PK LDX SQRT get A phase root CPX PHASB SQRT it to B phase BHS CHECK PHASEC zif is high or branch LDX SQRT else load B phase CPX 5 to C phase BHS STORE NU PEAK zif current double still high go store it LDX SQRT else get phase C current STORE NU STX SQRT istore double to SQR
150. VALUE POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN BE ADDED FOR 1000 TO HIGH BYTE LSN ACSC ADD VALUES NOP TEMP3 POINT TO TEMP STORAGE FOR CONVERTED VALUE STORE CONVERTED VALUE 814 POINTTO VALUE TO BE CONVERTED HIGH BYTE LSN LAI VALUE TO BE ADDED FOR 1000 TO HIGH BYTE LSN ACSC ADD VALUES GJMP CHUND CALCULATE HUNDREDS VALUE GETCON GJMP THOUS SUBTRACT 100 UNTIL VALUE BECOMES NEGATIVE TO DETERMINE 1005 DIGIT CHUND TEA ACC x THOUSANDS DIGIT SKAEI IS ZERO SUPRESS THE CHARACTER GJMP CH LA POINTTO BLANK CHARACTER CH XADR BCD4 SAVE THOUSANDS DIGIT LAI RESET COUNT VALUE TO ZERO HUNDS RC RESET CARRY LHLI BTI POINTTO VALUE TO BE CONVERTED LOW BYTE LSN LAI BE ADDED FOR 100 TO LOW BYTE LSN ACSC ADD VALUES NOP TEMPI POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE 812 POINTTO VALUE TO BE CONVERTED LOW BYTE MSN LAI VALUE TO BE ADDED FOR 100 TO LOW BYTE MSN ACSC VALUES NOP 2 POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALUE VALUE TO BE CONVERTED HIGH BYTE LSN LAI VALUETO BE ADDED FOR 100 TO HIGH BYTE LSN 5 089 928 193 194 ACSC ADD VALUES NOP TEMP3 POINT TO TEMP STORAGE FOR CONVERTED VALUE ST STORE CONVERTED VALU
151. XFER LADR TRANSFER ONLY DATA IN THIS PACKET XADR PAK LADR PAK SKAEI 02H GJMP 1 XFER PACKET 2 DATA LADR TSD XADR CSID LADR TRPID XADR CRPID LADR TOPT XADR COPT XFER PACKET 3 DATA XFl SKAEI GJMP XF2 LADR TLTS XADR CLTS RT 5 11 1421 TAATIRAA AAAA R AAAA TAATA 1911 993 n ROM LOOKUP ROUTINE FOR LCD DATA RIGHT SIDE OF CHAR ORG 400H DRIGHT DB 66455225550 RIGHT LAMT RT XFER PACKET OR 1 DATA XF2 MERGE MERGE 2X7 BIT BYTES INTO 1X6 AND 1X8 BYTES LADR THMSN TEMPORARY DATA BYTES INTO ACCUMULATOR LHU 5 HL TO ADDRESS OF PERM MEM LOCATION ST STORE THE ACCUMULATOR AT ADDRESS POINTED TO BY HL BT4 ST LADR THLSN LHL ST ST LADR TLMSN LMSN ST 812 LADR TLLSN 5 089 928 181 182 ST ST RT 5555555555555555555555555555555555555555555555555555555555555555555555555555 5 AS DO AN ADDITION CALCULATION 5 5 15555555555555555555555555555555555555555555555555555555555555555555555555555 ADDITION SEQUENCE AS ACSC NOP ST ISTORE OLS DECREMENT DATA MEMORY POINTER RT PERCENT BAR GRAPH DISPLAY CONTINUED 2 LA OVERFLOW SET COUNTER TO TEN TAE OFF ALL BAR SEGMENTS BO CALL BAROFF STURN ON ALL APPROPRIATE BAR SEGMENTS DES GJMP RT E 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1
152. able continuous current in the current path The bar segment 324 is controlled by the 5 V signal via a separate LCD driver 330 The LCD driver 330 operates in conjunction with the oscillator circuit 328 in the same manner as the LCD driver 326 However the LCD driver 330 and the oscillator circuit 328 will function at a relatively low operating voltage approximately two to three volts An MC14070 integrated circuit available from Motorola Inc may used to implement the LCD drivers 330 and 326 Thus when the tripping system fails to provide the display processor 316 with sufficient operating power or current the LCD driver 330 is still able to drive the bar segment 324 The LCD driver 330 drives the bar segment 324 whenever the tripping system detects that less than about 20 of the rated trip current is being carried on lines 106 to the load As an alternative embodiment the bar segment 324 may be disabled by disconnecting the LCD driver 330 Additional bar segments 332 335 are driven by the display processor 316 to respectively indicate when at least 20 40 40 60 60 80 and 80 100 of the rated trip current is being carried on lines 106 to the Joad The oscillator 328 also uses part No MC14070 in a standard CMOS oscillator circuit including resistors 329 336 and a capacitor 331 that have values for exam ple of 1 megohm 1 megohm and 0 001 microfarads respectively Even when a power fault causes the system to trip and inte
153. ably about every 200 millisec onds on lead 714 These pulses are passed through a capacitor 718 to activate an IGFET transistor 720 which in turn discharges an RC timing circuit 724 through a circuit limiting resistor 733 A resistor 730 and a clamping diode 732 are used to reference the pulses from the capacitor 718 to ground The pulses on lead 714 prevent the RC timing circuit 724 from charging up past a reference voltage Vref at the input of a comparator 726 If the RC timing circuit 724 charges up past Vref the comparator 726 sends a trip signal to the solenoid 112 to interrupt the current path in lines 106 The reference voltage for example is provided by a 4 3 volt zener diode 427 supplied with current through a resistor 729 Preferred component values are for example 0 001 microfarads for capacitor 718 27K ohms for resistor 730 part No 1N4148 for diode 732 part No BS170 for transistor 720 10 ohms for resistor 733 820K megohms for resistor 737 0 22 microfarads for capacitor 735 part No LM29031 for comparator 726 1N4687 for diode 727 100K ohms for resistor 729 and 10K ohms for resistor 751 E User Select Switches As introduced above the user select circuit 132 is illustrated in FIG 9 In addition to the buffer 820 for the rating plug the user select circuit 132 includes a plural ity of user interface circuits 810 each having a pair of BCD dials 812 and a tri state buffer 814 which is en abled
154. al asserted low via lead 744 to the watch dog circuit 712 to prevent the watch dog circuit from engaging the solenoid 112 during power up This latter function prevents nuisance tripping Preferably the power up reset circuit includes an under voltage sensing integrated circuit 745 that detects whether or not the output voltage of the 5 volt supply is less than a predetermined reference voltage at which the microcomputer 120 in FIG 1 may properly func tion The integrated circuit 745 is for example part No MC33064P 5 which holds the reset line 743 low until the output voltage of the 5 volt supply rises above 4 6 volts The microcomputer 120 may operate at 4 5 volts or above The preferred reset circuit also includes a pull up resistor 741 a capacitor 739 and a diode 753 connecting the integrated circuit 745 to the watchdog circuit 712 The resistor 741 for example has a value of 47K ohms and the capacitor 739 has a value of 0 01 microfarads The diode 753 ensures that the reset circuit 710 affects the watchdog circuit 712 only when the microcomputer 160 is being reset The watch dog circuit 712 protects the tripping sys tem from microcomputer malfunctions Thus it is de signed to engage the solenoid 112 if the microcomputer 120 fails to reset the watch dog circuit 712 within a predetermined time period The microcomputer 120 resets the watch dog circuit 712 by regularly generating 5 089 928 17 logic high pulses prefer
155. al path is vectorially equal in magnitude but opposite in direction to the increase in phase current and the magnetic summation is still zero When a ground fault is present current flows through an inadvertent path to an earth grounded object by passing the neutral trans former 506 and creating a current signal in the trans former 509 Thus the transformer 509 produces a cur rent signal only when a ground fault is present The current signal from the output transformer 509 of the ground fault sensing toroid 508 is routed through the rectifier bridge 522 the power supply 122 and re turned through the burden resistor arrangement 530 The burden resistor arrangement 530 and the rectifier bridge 522 convert that current signal into an A C rectified signal 558 that is inverted with respect to trip ping system ground and that has a voltage that is pro portional to the current in the transformer 509 The A C rectified signal 558 is filtered by filter 560 for noise suppression and then inverted using analog invertor 562 From the analog invertor 562 a positive going signal is carried to an A D input at the mi crocomputer 120 The microcomputer 120 measures the peak levels at the output of the analog invertor 562 to detect the presence of a ground fault A conventional voltage divider switch 564 is controlled by the mi crocomputer 120 to selectively reduce that signal by two thirds as may be required under severe ground fault conditions
156. apparent upon reading the following detailed description and upon reference to the accompanying drawings in which FIG 1 is a block diagram of a microprocessor based circuit breaker tripping system according to the present invention FIG 2 is a perspective view of the circuit breaker tripping system as set forth in the block diagram of FIG FIG is a diagram illustrating a local display 150 of FIG 1 FIG 3b is a flow chart illustrating a manner in which a display processor 316 of FIG 3a may be programmed to control an LCD display 322 of FIG FIG 4 is a schematic diagram illustrating an analog input circuit 108 a ground fault sensor circuit 110 a gain circuit 134 and a power supply 122 of FIG 1 FIG 5 is a timing diagram illustrating the preferred manner in which signals received from the gain circuit 134 are sampled by the microcomputer 120 of FIG 1 FIG 6a is a side view of a rating plug 531 of FIG 4 FIG 6b is a top view of the rating plug 531 of FIG 4 FIG 7 is a schematic diagram illustrating a thermal memory 138 of FIG 1 FIG 8 is a schematic diagram illustrating the reset circuit 124 of FIG 1 and FIG 9 is an illustration of a user select circuit 132 of FIG 1 While the invention is susceptible to various modifi cations and alternative forms a specific embodiment thereof has been shown by way of example in the draw ings and will herein be described in detail It should be understood how
157. ata Byte 2 Phase A Current Low Byte Data Byte 3 Phase B Current High Byte Data Byte 4 Phase B Current Low Byte Data Byte 5 Overload Pickups amp Short Circuit Restraint In Packet 1 000 1 Data Byte 1 Phase C Current High Byte Data Byte 2 Phase C Current Low Byte Data Byte 3 Ground Fault Current High Byte Data Byte 4 Ground Fault Current Low Byte Data Byte 5 Short Circuit Phase Unbalance amp Ground Fault Pickups Packet 2 00 1 0 45 50 20 continued Data Byte 1 Maximum Phase Current High Byte Data Byte 2 Maximum Phase Current Low Byte Data Byte 3 Maximum Phase Identification A Breaker Identification amp Ground Fault Restraint In Data Byte 4 Trip Unit Sensor Identification Data Byte 5 Rating Plug Options Packet 3 00 1 1 Data Byte 1 Long Time Switches Data Byte 2 Short Time Switches Data Byte 3 Instantaneous Phase Unbalance Switches Data Byte 4 Ground Fault Switches Data Byte 5 Phase Unbalance Trips Packet 4 0 1 0 0 Data Byte 1 Long Time Trips Data Byte 2 Short Circuit Trips Data Byte 3 Ground Fault Trips Data Byte 4 Last Maximum Phase Current High Byte Data Byte 5 Last Maximum Phase Current Low Byte Packet 5 0 10 1 Data Byte 1 Software Failure Trips Data Byte 2 Last Phase A Current High Byte Data Byte 3 Last Phase A Current Low Byte Data Byte 4 Last Phase B Current High Byte
158. ce SCI may be utilized FIG 2 is a perspective view of the tripping system 100 as utilized in a circuit breaker housing or frame 210 The lines 106 carrying phase currents A B and C are shown passing through line embedded current trans formers 510 512 and 514 in dashed lines which are part of the analog input circuit 108 Once the solenoid 112 also in dashed lines breaks the current path in lines 106 the user reconnects the current path using a circuit breaker handle 220 Except for the circuit breaker handle 220 the inter face between the tripping system 100 and the user is included at a switch panel 222 an LCD display panel 300 and a communication port 224 The switch panel 222 provides access holes 230 to permit the user to adjust binary coded decimal BCD dials FIG 8 in the user select circuit 132 The communication port 224 may be used to transfer information to the display termi nal 162 via an optic link not shown In the following sections the tripping system 100 is further described in detail Local Display FIG 3a is a schematic diagram of the local display 150 of FIG 1 The local display 150 is physically sepa rated from the remaining portion of the tripping system 100 but coupled thereto using a conventional connec tor assembly 310 The connector assembly 310 carries a plurality of communication lines 312 from the mi crocomputer 120 to the local display 150 These lines 312 include tripping syste
159. communication procedure that permits the tripping system 100 to communicate with a relatively low power processor in the display processor 316 procedure utilizes a software interrupt mechanism to track the frequency with which information is sent on the interfaces 151 and 191 During normal operation one 8 bit byte of information is sent every seven milli seconds During tripping conditions information is sent continuously as fast as the microcomputer 120 can transmit This procedure allows the display terminal 162 and the display processor 316 to display continu ously status messages from the tripping system 100 without dedicating their processors exclusively to this reception function Equally important this procedure permits the microcomputer 120 to perform a variety of tasks including continuous analysis of the current on lines 106 Status messages are preferably transmitted using an 8 byte per packet multi packet transmission technique The type of information included in each packet may be 5 089 928 19 categorized into eight different groups or eight differ ent packets packet 0 through packet 7 first byte of each packet is used to identify the byte and packet num bers and the trip status of the tripping system 100 For example the first byte may contain one bit to identify 5 the byte type four bits to identify the packet number and three bits to identify the trip status no trip condi tion current overl
160. d igo past odd byte INY it to me too i Mec PU GF PU are we pointing past the last byte BLO DATA no move next word LDX PHASE I load max peak of phases LDAB MAX IDENT get phase causing trip max current ANDB 4503 mask for trip phases only 4503 compare for GF trip cause BLO NOT GF CAUSE strip not caused by GF LDX CURRENT GF trip so save it to historical data TUN ex LAST MAX I store to EEPROM saved RAM CLR TRIP CAUSE clear phase bits LDAA SCRIN iget phases gt ovid ANDA 4538 mask all but ovid STAA TRIP CAUSZ save it LDAA 5 PU GF PU SC pick up phases ANDA 507 maskall but SCPU TRIP CAUSE STAA TRIP CAUSE SC amp ovid saved LDX REGSTART onboard reg locations NO RESTRAINT SAVE DATA NO EE WRITE DO NORM PEAK TRIP V signal Square D Company ADE Group Jerry Baack Leon Durivage 5 089 928 86 read restraints mask for restraint lines compare for restr ino active restraints high no restr set bit restraint is off address the EEPROM for listening igo write to EEPROM reset the COP TURN INTERRUPTS BACK ON max phase to send masx off unwanted data 145 this GF no don t do prebyte multiply zgo do GF xmit conversion get conversion result store to max phase cause of trip current go check trip voltage
161. d IY pointing to the memory location of the 16 bit multiplier and multiplicand RETURNS Result of the multiplication in 32 bit location called RESULT If called at SQUARE the routine will do 172 on the values both IX amp IY must point to same location for 1 2 e 4 9e 4 4 94 Se 4 vs USED RESTORED amp IY return as set Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING RESULT USED 22 3 02 13224 00 2 0 0 01 5 089 928 113 114 1 SQUARE EQ BSET FLAGSS 1 SQ SET FOR SQUARE INSTEAD OF MUL 16 16 16x16 5 CLR RESULT BYTE Or EI WORD OF RESULT CLR RESULT 1 CLEAR LOW BYTE OF EI WORD OF RESULT LDAA 1 LOW BYTE OF MULTIPLIER 1 7 LOW BYTE OF MULTIPLICAND MUL SMJLTIPLY IT STD RESULT 2 STORE IN LOW WORD RESULT LDAA 1 LOW BYTE OF MULTIPLIER O Y BYTE OF MULTIPLICAND BEQ BYTE EIGH BYTE 0 WHY MULTIPLY GO TO NEXT 1 TEST FOR I SQUARE MULTIPLY IT BRCLR FLAGSS I SQ BIT ADD RESULT BIT CLEAR TEIS ISN T 5800855 LSLD WE EAVE SQ REQUEST so double 2nd proczcz ADD RESULT EQU ADDD RESULT 1 ADD RESULT IN TO COVER DOUBLE WORD EOUNDARY STD RESULT 1 STORE ANSWER BACK TO LOCATION LDAA RESULT GET EIGE BY
162. der by 2 RMS SQROOT zis 2xREMAINDER gt divisor BLS INC no don t increment quotient INX increment the quotient INC EQU XGDX quotient in ADDD RESULT finish result RMS SQROOT guess to quotient LSRD divide 2 CPD RMS SQROCT if same we ve found the root BEQ QUIT all done quit LDX SQROOT the criginal divisor Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 29 SERIES III ELECTRONIC TRIF 2 5 SOFTWARE LISTING Y STD RMS SQROOT store last iteration XGDX move old root into ACCD SUBD RMS 08001 find the difference between old 6 new 0001 1 to allow 1 bit difference 0002 result lt 2 BLS QUIT if so we re close enough JMP SQRCAL otherwise try again QUIT EQU PULX restore ACCY Lop 0000 value to clear STD 0 clear high word of squared sums STD 2 X clear low word RTS END OF SQUARE ROOT ROUTINE ww tet t4ktttt wneen tnt t en ee FAGE vaserese ut ROUTINE TO CONVERT DATA FROM GF TO PHASE VALUES CALLED From GF communications routine to begin conversion of cata fro raw A D format to serial comm fcrmat RETURNS This routine goes to the I_CONVERSION routine to fini sh converting from A D values to serial format values Passes GF_CURRENT to next routine as storage for result e Ss 5
163. e for switches 51 rating plug value to get to prod test software version 1 3 Apr 25 1989 shardware version 1 0 Feb 3 1989 maximum current value that can be sent 16383 VALUE TO SET A D to low gain inputs VALUE TO SET A D to high gain inputs value for 32mS delay VT CHECK routine value for 2mS delay in VT CHECK routine EL ERE LR DATA AREA e de de e e e e e e de de dede de e e e e e e e e e e de e de m dede de e d dmm SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING ORIGIN ABSOLUTE START_VARS ppeeeeeeeee START 55 ACCUM FTIMER Gz 1 RESTRN TIME RETN TIME GF LONG TIME ASOVE GF VARS 0000 RMB RMB RMB RMB RMB RMB POINTER TO START OF MEMORY CLEAR 0 OF MEMORY CLEAR WHEN G F MEMORY IS NOT CHARGZD 5 5 FLAG BITS GROUND FAULT 1 2 ACCUMULATOR GROUND FAULT UNRESTRAINED TIMER TIMER FOR 10 MS Gr RESTRAINT HOLD GF 5 SECOND RETENTION TIMER QUE TIMER FOR GF RESTRAINT DELAYS start of memory clear when G F mem high de ve e f Sce de Wc e de e e e e ee e ee je de de je jede e de o e e e coe eie e e de ee ee de e eee e de e dee dee ode e dede dede jede dee dede SERIAL BUF RMB 0 31 character sci transmit buffer
164. ec interrupt STD TOCi X load back into output compare register 1 2 Strobe the watchdog bit high on each 500 usec interrupt BRSET FLAGSS KILL WATCEDOG BIT LOW GAIN RD if we are in trip don t sir WD BSET PORTA X WATCHDOG set watchdog bit high NOW SET THE FOR GAIN READ THE AREA BETWEEN THE COMMENTED A MUST BE KEPT TOGETHER TEE A D CONVERTER IS SWITCHED FROM LOW TO HIGH GAIN AND THE LOW GAIN VALUES MUST BE READ WITHIN 64 uSzC OR THEY WILL BE OVER WRITTEN WITH HIGH LOW GAIN RD EOU 5 LDAA 530 VALUE SET FOR HIGH GAIN A D READ STAA ADCTL X STORE TO ONBOARD TO START CONVERSION ON HI GN t 99 t t A D TRANSFER STARTS FOR THE LOW GAIN A D rurs Store peak detect routine take 8uS phase A D conversions take 16uS phase LDAA READ LOW GAIN A D PHASE STAA PHASEA STORE A PHASE A D TO RAM CMPA LAST APEASEZ compare to last BLS DO 214 lower or same don t mess STAA LAST APEASE Jif higher save new value DO LDAA ADR2 X READ LOW GAIN A D B PHASE STAA STORE B PHASE A D TO RAM LAST compare to last BLS DO CEE if lower same don t mess STAA LAST 5 214 higher save new value DO CEE 5 D LDAA ADR3 X READ LOW GAIN A D C PHASE STAA STORE C PHASE A D TO RAM LAST CPEASE compare to last 815 RD MEM RATIO 15 lowe
165. ed I t Amps The column labeled I t SQUARED Amps gives the squared values and the column labeled SUMMATION Amps shows the accumulation of the squared current values over time The mean of the summation depicted at the bottom of TABLE 1 is equal to the final accumu lation divided by the number of samples or 50 The square root of this value yields 70 7106854 which is less than 0 00001 in error The other columns in TABLE 1 detail the binary equivalent data that the microcomputer would process using the ratio that 100 amps equals 255 binary The value will accurately reflect the heating effect of the current waveform that existed from t 0 to t N This current waveform is typically an A C wave form with a fundamental frequency of 50 to 60 Hertz but may contain many upper harmonics i e multiples of the fundamental frequency In practical implementations several factors affect the accuracy of the Irms calculation including the sample rate and the number of samples In the preferred embodiment the sample rate is 2 000 Hertz and at least 128 samples are taken before the current magnitude is estimated 2 Detecting The Presence Of A Ground Fault The ground fault sensing toroid 508 magnetically adds the current signals from the input windings 540 542 544 and 546 to indicate whether or not a ground fault is present on lines 106 The toroid 508 is con structed with four identical input windings 540 542 544 and 54
166. end of do while loop while remainder gt 1 iterations are 1 2 end of 5 root routine simulation scoare root routine RESULT USED 1311111 3 13 312 1 1 1 21 2 4 1 AVG 0 get high word for 0 check BNE CONT zif not 0 continue LDD 2 X get low word check for 0 57F slow 7 bits get masked off so 572 0 CONT if gt 72 do square root LDD 0000 0 for result STD RMS 505007 store 0 for result RIS CONZ AVG 15 3 shift low byte for carry mult by 2 ROL 2 X rotate next byte for carry ROL 1 rotate to pull in carry ROL O X rotate to get carry bit LDD 1 word boundary to drop lowest byte STD RMS_MEAN LW store into mean variable location 0 get high byte of average CLRA clear out high byte for mean value STD RMS MEAN store high byte of the mean PSHX save X for later use AVERAGE IS FINISHED BEING CALCULATED LSLB shift left for guess value Square D Company ADE Group Jerry Baack Leon Durivage 2 16 25 III ELECTRONIC TRIP STEM SOFTWARE LISTING GUESS load Y with GUESS location ABY aca in offset from accb LEX 0 load indexed guess into IX STX 5 SQROOT store off initial guess in case of luck RMS SQR
167. ever that it is not intended to limit the invention to the particular form disclosed but on the contrary the intention is to cover all modifications equivalents and alternatives falling within the spirit and scope of the invention as defined by the appended claims BEST MODES FOR CARRYING OUT THE INVENTION System Overview The present invention has direct application for mon itoring and interrupting a current path in an electrical distribution system according to specifications that may be programmed by the user While any type of current path would benefit from the present invention it is particularly useful for monitoring and interrupting a three phase current path Turning now to the drawings FIG 1 shows a block diagram of an integral microprocessor controlled trip ping system 100 for use with a three phase current path on lines 106 having source inputs 102 and load outputs 5 089 928 3 104 The tripping system 100 uses an analog input cir cuit 108 and a ground fault sensor 110 to detect three phase current on the current path 106 When the trip ping system detects an overload short circuit or ground fault condition or otherwise determines that the cur rent path should be interrupted it engages a solenoid 112 which trips a set of contactors 114 to break the current path carrying phases A B and C Consequently any ground fault circuit through the earth ground path or through an optional neutral line N is also br
168. ker and generates a plurality of trip signals and a trip indicator circuit responsive to the trip signals and operating from power provided by the tripping system including a battery latch means responsive to the processor for latch ing at least one of the trip signals and for assert ing a battery enable signal display 8 driver circuit responsive to the latch means for driving the display means for arbitrating power to the latch means and the trip indicator circuit either from the tripping 5 089 928 205 system or from the battery when said battery enable signal is asserted and witch means for permitting an operator to assert said battery enable signal independently of the trip signals from the processor 2 A circuit breaker tripping system according to claim 1 further including an electrical connector for connecting the trip indicator circuit to a remaining portion of the tripping system wherein a terminal of the battery is connected to said connector such that current from the battery must pass through the electrical con nector to prevent power being drawn from the battery without the trip indicator circuit being connected to the remaining portion of the tripping system 3 A tripping system according to claim 1 wherein the trip indicator circuit further includes a display con trol processor responsive to the processor for control ling the display 4 A tripping system according to claim 1 wherei
169. l PE LDX 457 2000A PE load 2000A tabie CMPB 512 compare to 2000A sensor BEQ READ ST SW if 2000A we have correct table LDX 5 2500A 2500A load correct table READ ST SW EQU mV LDAB STPUSW load accb with ST switch ANDB SW POS mask off bit O ABX sw offset to x reg table position STX ST TABLE POS for use 1115 routine LDD get latest table value JST PEAK to ST peak BLO ST PICK UP gt table we have pick up WE GET HERE WE DO NOT HAVE A SEORT TIME PICK JMP ST OFF CEECK FOR ACTIVE TIMER TEEN LEAVE ST ROUTINE WE DO HAVE SHORT TIME PICK UP WEEN WE REACH HERE ST PICK UP EQU 5 REGSTART x to 6811 io base BSET PORTA RESTR OUT turn on restraint out restraint is turned on here to al 110 for slew rate in self restrained brkrs BSET ST FLAGS ST PU BIT SET ST PICK UP FLAG START RESET ST MEMORY RETENTION TIMER LDAA 436 retention time is 36 mSec STAA ST RETN TIMER sStart reset timer RESTRAINT NOW TEST FOR A RESTRAINT INPUT TO BYPASS THE ST FAST TIMER BRCLR PORTA Y SC RESTRAINT IN RESTRN DELAY do we have restrained delays DEC ST FTIMER no restraint use fast timer DEC ST FTIMER BGT EXIT ST has not expired JMP ST TRIP itimer has expired so trip EXIT ST EQU JMP EXIT SEORT GO LEAVE ST ROUTINE 9 Square
170. l not trip CEECKSUM TEST EQU CLRB 5 ADD NEXT BYTE ADDB 0 INY BNE NEXT BYTE ADCB 0 STAB MAX PHASE I Square D Company ADE Group Jerry Baack Leon Durivage CLEAR FOR CHECKSUM bottom of PROM byte to sdecrement IX go add next byte carry back all done so save it Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING qjestaeruuue eraut EEPROM TEST DONE HERE tiar sr kriere EEPROM TEST JSR RESET COP LDAA PORTA REGSTART ANDA 504 BEQ EEPROM TEST keep the puppy happy read port mask for SC restraint sloop back THIS SECTION LOOPED BY PULLING THE ST RESTRAINT LINE EIGH xewwes 5 089 928 155 156 RESTART INTERRUPTS AT THIS POINT BSET IDX BSET BSET LDAA STAA LDD ADDD STD BSET BSET BSET CLI Ton de od o de e dd m TRIP STATUS 70 5 for prod test REGSTART start of onboard registers DDRD X 3E set up portd data direction PORTD X 3E set up data TFLG1 X read interrupts TFLG1 X clear interrupts TCNT X get timer 970 value for SmSec interrrept 1 load output compare register TMSK1 X 80 sallow timer 1 interrupt IFLAGS TRIPPING shut down instantaneous FLAGSS KILL WATCEDOG shut down
171. ls This area contains the current A D values that are used for all calculations wow wc eode e de e fe n d de ddnde d 5 SQRT MUST STAY CONTIGUOS wx C T 11MS RB 1 T 12 5 RB 1 13 5 RB 1 T RMS RB 1 PEASEB RMS RB 1 RMS 1 64MS RMB 1 250MS RB 1 T_1000Ms RB 1 77 END OF MILLISECOND PEAK_FOR_PU RB 2 ST_PEAK FMB 2 ST TABLE POS RB 2 PEAK RB 2 POS RB 2 LAST APHASE RB 1 LAST BPHASE RMB 1 LAST CPHASE RB 1 5 6 RB 2 B_PEASEX6 RB 2 C_PHASEX6 FB 2 1 L_PHASEA RMB 1 L RB 1 L PEASEC Re 1 MEM RATIO 2 EI PHASEA RMB 1 RB 1 PEASEC RB 1 NEW GF 1 CUR ATOD PTR RB 0 CUR PEASEA RB 2 CUR RMB 2 CUR PEASEC 2 CUR GF RB 2 PEAS SORTS RB 0 _ 0 Re 2 PHASB_SORT Ra 2 PEASC SQRT RB 2 END SQRTS RB 0 TO ALL 3 SQ ROOTS SQRT PHAS A 5027 PHAS B J SQRT PHAS C POINTER END OF SQ ROOTS 5 089 928 31 32 MOTOR PROTECTION FUNCTION VARIABLE STORAGE PU APH RMB 1 5 phase unbalance PU RMB 1 5 phase unbalance PU 1 5 phase unbalance Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 _ peak of modified FLC POINTER RMB pointer to modifier for I LRC code END OF M
172. m ground the 5 V signal from the power supply 122 serial communication lines 314 for a display processor 316 and data lines 318 for a latch 320 The data lines 318 include four trip indication lines overload short circuit ground fault and phase unbalance which are clocked into the latch 320 by yet another one of the lines 318 An LCD display 322 displays status information pro vided by the latch 320 and the display processor 316 Different segments of the LCD display 322 may be implemented using a variety of devices including a combination static drive multiplex custom or semi cus tom LCD available from Hamlin Inc Lake Mills Wis For additional information on custom or semi custom displays reference may be made to a brochure available from Hamlin Inc and entitled Liguid Crystal Display The latch 320 controls the segments 370 373 to re spectively indicate the trip conditions listed above Each of these segments 370 373 is controlled by the latch 320 using an LCD driver circuit 326 and an oscil lator circuit 328 The corresponding segment 370 373 illuminates when the associated output signal from the latch 320 is at a logic high level The display processor 316 controls four seven seg ment digits 317 as an ammeter to display the current in the lines 106 The display processor 316 for example is 20 25 30 35 40 60 65 6 an NEC part No UPD7502 LCD Controller Driver which includes a four bit CMOS micropr
173. m percent JMP DONE return to main FIND TEE EQU LDX THREE PHASE SUM diff of three phase sum amp 3 phase LDD RESULT numerator is three phase sum FDIV fractional divide XGDX put result into double register CLRB 1 ACCB for percent LSLA shift into carry 2 go check bit 2 ADDB 100 if set 2 1 2 LSIA shift into carry _3 290 check bit 3 ADDB 50 if set add 2 2 szT 3 LSLA shift into carry 4 290 check bit 4 ADDB 25 if set 2 3 4 EQU LSLA shift into carry 5 240 check bit 5 Square D Company ADE Group Jerry Baack Leon Durivage 8 16 89 SERIES III ELECIRONIC TRIP SYSTEM SOFTWARE LISTING ADDB 12 2 4 BIT 5 EQU LSLA sshift into carry BCC 6 go check bit 6 ADDB 6 2 5 BIT 6 EQU LSLA shift into carry go check bit 7 ADDB 3 2 6 BIT 7 5 089 928 83 84 LSLA shift into carry 8 all done so leave ADDB 2 2 7 RIT 8 LSLA shift into carry BIT_DON 11 done so leave ADDB 1 2 7 DONZ EQU RTS result in ACCB 2x percent n dede GLOBAL TRIP THIS IS THE GLOBAL TRIP ROUTINE CALLED BY ALL THE INDIVIDUAL TRIP ROUTINES CALLED MAX phase causing trip or 22 TRIP FLA
174. me to catch up with any exceptionally long RMS calculations Tot LDAA 48 begin A PHASE 48 mS to stagger RMS calc STAA RMS store to PHASE timer LDAA 32 begin B PHASE 8 32 mS to stagger RMS calc STAA PHASES 5 store to B PHASE timer LDAA 16 begin C PHASE 8 16 mS to stagger RMS calc STAA T_PHASEC_RMS 5 to C PHASE timer LDAA 1 5 2 5 ST ST 21 timer to 1 mS READ_MEMORY EQU pte OVERLOAD MEMORY CAP VOLTS IS gt 3 VOLTS SET SO OVERLOAD ACCUMULATOR IS CALCULATED ON lst PASS THRU 7mSEC ROUTINE LDAB 1034 sget A D into ACCB 4510 to 10 hex BLO SET FAST TIMERS if low bypass setting flag BSET FLAGS SET ACCUM bit so Ovid Accum is calculated 5 089 928 39 40 FAST TIMERS Set SHORT TIME FAST TRIP TIMER 33MS STARTUP TIME 27MS GROUND FAULT FAST TRIP TIMER TO 33MS STARTUP TIME 18 5 RETENTION TIMERS ARE STARTED TO RESET THE FAST UNRESTRAINED GF amp ST TIMERS we LDAA 33 6 load ST unrestrained timer value STAA ST_FTIMER into unrestrained timer location DO_ST_RETN 5 QUE THE SHORT TIME MEMORY RETENTION TIMER FOR 36 MS RETENTION timer is loaded so that after 36mSec the initialization time is added to any timers ese e AYERTETERERAETESTETETRATETESRENEREREREAXYTERETETERSENRESERETETSENTS LDAA 0036 36 ms timer
175. mp TRIP FLAG IFLAGS RB 1 CURRENT VAR MS TIMERS IN USE TAIP FLAG 1 5 LOCATION FOR CAUSE OF TRIP UNBAL CTR 1 counter timer for phase unbalance delay S 1 I END OF RAM VARIABLES TO BE CLEARED ZERO STARTUP f tereeeiee END VARS RB 0 POINTER TO END OF MEMORY CLEAR SOFTDOG MEMORY AREA NOT CLEARED ON POWER UP de fe cie e dede de ee ex This section not cleared so that on softdog errors the error counter isn t cleared by accident 5 DOG TIMER RMB 2 SO T TIMER2 RB 2 5 CNTR RS 1 pp vk END ADDRESS POINTER DEFINITIONS de e dede e e de dee e eve cde e de e e n KE RELATIVE CODE ORIGIN 52000 CODESTART DB 55 VER DB SERIES 3 ver 1 3 COPYRIGET DB COPYRIGHT 1987 SQUARE D CO MAIN CODE STARTS EERE 1 1 1 191 1 1 3 T 1 P E 0 1 0 INITIALIZE EQU POWER UP RESET STARTS HERE AND RESETS SOFTDOG COUNTERS AND TIMERS TO ZERO SEI disable all interrupts LDD 0000 load double to clear soft dog timers STD SOFT DOG TIMERl clear ist softdog timer STD SOFT poc TIMER2 clear 2nd soft timer LDAA SFF_ set high bit to indicate no soft errors STAA DOG CNTR clear soft error counter 222222335444 444444444444 44
176. mple trip systems also employ a slower re sponding bi metallic strip which is useful for detecting a more subtle overload fault This is because the extent of the strip s deflection represents an accurate thermal history of the circuit breaker and therefore even slight current overloads Generally heat generated by the current overload will cause the bi metallic strip to de flect into the tripping mechanism to break the circuit path The tripping systems discussed above are generally adequate for many simple circuit breaker applications but there has been an increasing demand for a more intelligent and flexible tripping system For example many industries today include 3 phase power equip ment that must be adjusted and monitored on a regular basis Processor based tripping systems have been de veloped to meet these needs Processor based tripping systems typically indicate the status of the tripping system in an expensive and power inefficient manner One known system for exam ple employs a pop up plunger to indicate certain types of trip causes The pop up plunger includes a solenoid mechanism that is not only expensive but also requires an excessive amount of power Other systems use light emitting diodes LEDs to indicate the status of the tripping system LEDs are less expensive than the pop up plunger devices but due to their power consumption require a relatively expensive external power source Accordingly in addition
177. mulator CEECK GTZ BIT EQU 5 BRCLR LT FLAGS LT 2 11 5 215 LTA 0 check 64mS timer IDX RATIO TABLE DO FIRST PASS EQU JSR ADJUST LT VOLTS ADJUST MEMORY DELAY CAP VOLTAGE ago edo de desee weed ea END OF 5 MS CALLS ELA LE ESSA ESR ERE TEE SS p WW deed AREER EERE TERE 31 MS TIMER CHECK Maximum currert for communications Short Time 1 2 is run and ST Peak Detectors are cleared on this time base CEECK 11 5 EQU LDAA 11 5 G T 11 MS TIMER 11 5 EXPIRED YET BLO CHECK 12MS NO IT HAS NOT EXPIRED YET 5 089 928 55 56 THE FOLLOWING CALLS ARE DONE EVERY 11 MS SUBA 11 reset timer STAA 11 5 store reset timer LDX SERIAL POINTER location of byte last sent CPX PHASE 1 sis ti the first half of max current BNE DO SERIAL CONV if not OK to do serial conversion UMP TEST ST INSTALLED GO CHECK FOR 64 mS DO MAX SERIAL CONV EQU UP AUT LDX 4MAX PEASE d Storage location for max phase current 57 max phase current to convert JSR I CONVERSION do conversion for peak current xuit 5 ST INSTALLED 1 SHORT TIME PICKUP IS CLEAR BYPASS SHORT TIME SUBROUTINE BRCLR ST FLAGS ST PU BIT CLEAR ST PEAK IF SHORT RESTRAINT IN BIT IS SET WE DON T HAVE R
178. n the trip indicator circuit further includes indicator means having display means for indicating that the operating power provided by the tripping system is in excess of a first level and control means operative in response to the power provided by the tripping system being in excess of a second level that is greater than the first level for controlling the indicator means 5 A tripping system according to claim 4 wherein the second level corresponds to the system providing operating power to the trip indicator circuit 6 A tripping system according to claim 5 wherein the display is an LCD type and the indicator means includes an LCD bar segment 7 A tripping system according to claim 4 wherein the second level corresponds to the system providing operating power to the trip indicator circuit and wherein the display is an LCD type and the indicator means includes an LCD bar segment 206 8 A tripping system according to claim 1 wherein the trip indicator circuit is optionally connected to a remaining portion of the tripping system through electrical connector 9 For use in a circuit breaker tripping system a trip indicator circuit which is normally powered via a cur rent path from current monitored by the tripping sys tem comprising indicator means including display means for indicat ing that the power from the tripping system current path is in excess of a first level and control means opera
179. n in the Serial buffer for the packet bei Ping sent Packet pointer values will follow 0 1 2 0 1 3 0 1 4 2 pattern Hope the pattern looks familiar LDAA PACKET HOLDER get next packet to send STAA store to pointer for use CMPA 07 zif packet 7 BLO NOT TO TOP YET don t reset not at top of buffer yet LDAA 2 load reset value 5 HOLDER save it to packet holder JMP SEND CHECKSUM packet holder is reset go send checksum TOP INC packet 7 so increment packet JMP SEND CHECKSUM igo send checksum SEND 2 EQU 5 When tripping we come here It s a good place to eat 2111111111111 Makes sure only packet 2 is sent 11111111111111 LDAA 2 sload packet 2 for trip communication STAA save to packet pointer for use BSET STATUS 82 set status byte 2 NOW GO AHEAD AND SEND THE CEECKSUMee eene SEN2 5 EQU LDAA CHECK SUM get the checksum ANDA 57 clear high bit DO PARITY 90 check parity DO CRECKSUM EQU Value to send is transferred to ACCB then checksum value is added to it stored back for next calculation TAB TO ACCB FOR CHECKSUM TESTING ADDB CHECK SUM byte to checksum Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFIWARE LISTING STAB
180. n to caller 10 MS RESTRAINT TIME OUT se CALLED From an llmSec ST restraint timer time out RETURNS SC RESTRN reset to SFF USED IX RESTORED NOTHING A YY TYTRETTRTTEA TRUTTYYEYTURETETETETERETY RETE E xx C RESTRN OFF EQU a Se Se se se ve WE GET HERE THERE ARE NO SC PICK UPS SO CLEAR SC RESTRAINT OUTPUT LDX REGSTART BCLR PORTA X SC RESTR OUT clear restraint bit BSET SC TIMER SFF set timer number to null RTS pe terereeete SEORT TIME ROUTINES 3 PRSE re ALL GROUND FAULT ROUTINES ARE HERE TOP wore e o o er n CHECK FOR GF 8388 CALLED Every 2mSec from breaker or motor protection code No preset conditions or values passed in any registers RETURNS Condition of GF restr in line 2mSec GF peak cleared 2mSec GF peak is passed to the 13 5 GF peak location maybe GF pick up bit set if in pick up GF switches stored for Communication purposes Starts GF retention timer if needed and appropriate GF delay timer accumulator se Se ta te gt e 5e se Se t t o 4 Se gt e te vs 2 Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 683 SERIES III ELECTRONIC SYSTEM SOFTWARE LISTING
181. n x BSET PORTA X SC RESTR OUT restraint output INC CNTR 4 step pu counter LDAB INST CNTRL 4 get current inst pu counter 2 test for limit of 2 BLO WAIT FOR HI not reached 2 yet e ww et e e v THIS SECTION ONLY IF WE ARE TRIPPING 9 9 BCLR SC PU GF PU 07 1 before setting phase s gt SCPU LI PHASEA check if phase gt INST PU BHI CHECK B FOR PU if A phase low check B phase BSET SC PU PU S01 set bit for A phase gt SC PU CHECK B FOR PU 5 check if B phase gt INST PU BHI C FOR PU if B phase low check C phase Square D Company ADE Group Jerry Baack Leon Durivage 8 16 85 SERIE ES III ELECTRONIC TRIP SYSTEM SOFIWARE LISTING BSET 5 PU GF 502 set bit for B phase gt SC PU C FOR PU EQU e PHASEC check if C phase gt INST PU BHI FINISH INST if C phase low continue BSET SC PU GF 0 504 5 bit for C phase gt SC PU FINISH INST 135 5 089 928 136 v9 dried dede ee o de th FIND OF 3 PHASES Pede e n md LDAA CMPA L PHASEB BEI 15 C INST PEAK LDAA L 15 C INST PEAK EQU 5 L PHASEC BEI C_ISNT_INST_PEAK LDAA 1 PHAS C C_ISNT_INST_PEAK EQU E 06 MUL STD ST PEAK Q X E i t w WP ART TSX LDAB 409 ABX _ TXS H
182. ne 22 END OF MAIN GROUND FAULT ROUTINE GROUND FAULT 1 2 99 9999 292992 999 CALLED Every l3mSec from main motor flow when GF 172 in accum calculation is needed Se 4 74 4 RETURNS Either updated accum value never returns and trips the breaker If sensor is greater than 1600 Amps a branch is taken to execute exception code M 4 Szuare D Company ADE Group Jerry Baack Leon Durivage 8 16 22 5 5 III ELECTRONIC SYSTEM SOFIWARE LISTING 7 USED ACCB IX IY RESTORED NOTHING 2111121012122 OPPO ener RESULT USED 111111112 00 12 2 2 20 0 12 1 2 0 0 2 2120 08 1 08 2 1 0 12 f n 1 6 150 IN EU E LDAB SENSOR red GF sensor code ANDB SWITCH_MASK smask it to max switch QPB 5 4000A sensor none bigger BLS CONT 67150 CALC LDAB 51 load max sensor CONT 50 CALC EQU 512 compare to 2000A frame BES GF SPECIAL 21 or gt frame size is gt 2000A TEE FOLLOWING CODE IS THE NORMAL GROUND FAULT I SQUARE SOFTWARE NORMAL GF ISQ EQU LDAA GF PEAK GF peak in TAB smove GF peak to ACCB MUL 1 sSCcBre it ACCB STD RESULT use RESULT as a holding register AGAIN EQU 5 LDX 6 ACCUM 5 X to the gf accumulater JSR ACCUM4 ADD 199
183. ntact points on the connector 588 This connec tion 589 allows the tripping system to encode the printed circuit links A B C and D in binary logic such that one of 16 values of each parallel resistor arrange ment is defined therefrom In a preferred arrangement the binary codes 1111 and 1110 are reserved for testing purposes and the fourteen codes 0000 to 1101 correspond to current rating multipliers of 0 400 to 1 000 as follows Code Current Rating Multiplier 0000 0 400 0001 0 500 0010 0 536 0011 0 583 0100 0 600 0101 0 625 0110 0 667 0111 0 700 1000 0 750 1001 0 800 1010 0 833 1011 0 875 1100 0 900 1101 1 000 pM d The user select circuit 132 of FIG 9 includes the interface circuit used by the microcomputer 120 to read the binary coded resistor value from the rating plug 531 A tri state buffer 820 allows the microcomputer 120 to selectively read the logic level of each of the four leads representing the status of the four fusible printed circuit links on the rating plug 531 A logic high at the input of the buffer 820 provided by the connection between the fusible printed circuit link and 5 V signal indicates that the corresponding link is closed A logic low at the input of the buffer 820 provided by pull down resistors 826 at the input of the buffer 820 indicates that the corresponding link is open The fusible printed circuit links A B C and D may be opened using a current generator to send an
184. oad trip short circuit trip instanta neous trip ground fault trip and phase unbalance trip Bytes two through six of each packet vary depending on the packet number Byte 7 is used to identify the tripping system sending the information for a multiple system configuration and byte 8 is used checksum to verify the integrity of the data The microcomputer alternates the type of informa tion included in each packet depending upon the prior ity type of the information During normal non trip ping conditions the trip unit will transmit Packet Number 0 followed by Packet Number 1 followed by one of the remaining defined Packet Numbers 2 through 7 The sequence is graphically shown as Packet 0 Packet 1 Packet 2 Packet 0 Packet 1 Packet 3 3 Packet O Packet Packet 4 Repeat until Trip 25 4 Packet 0 Packet 1 Packet 5 Occurs 5 Packet 0 Packet 1 Packet 6 6 Packet 0 Packet 1 Packet 7 During a trip condition the normal operation packet 30 transmission sequence is interrupted and Packet number 2 is transmitted continuously until power is lost The transmission rate will be increased to the fastest rate possible The five bytes of each packet that vary according to packet number are configured for a total of eight differ ent packets 0 7 The information in these bytes is im plemented for each packet number as follows 35 40 Packet 0 0000 Data Byte 1 Phase A Current High Byte D
185. ocessor and a 2k ROM This NEC part is described in NEC UPD7501 02 03 CMOS 4 Single Chip Microproces sor Users Manual available from NEC Mountain View Calif Other segments 375 of the LCD display 322 may be controlled by the display processor 316 or by other means to display various types of status mes sages For example a push button switch 311 may be uti lized to test a battery 338 To perform this test the battery 338 is connected through a diode 313 to one of the segmerits 375 so that when the switch 311 is pressed the condition of the battery is indicated The push but ton switch 311 preferably resets the latch 320 when the switch is depressed For this purpose the switch 311 activates a transistor 315 The latch for example is a 40174 integrated circuit Additionally the switch 311 may be used to select the phase current to be displayed on the LCD display 322 to control segments 375 such that they identify the phase current A B C or N on lines 106 being dis played on the four seven segment digits 317 For this purpose the switch 311 activates a transistor 327 to invert a signal provided from the battery and to inter rupt the display processor 316 Each time the display processor 316 is interrupted the phase current that is displayed changes for example from phase A to B to C to ground fault to A etc An optional bar segment 324 is included in the LCD display 322 to indicate a percentage of the maximum allow
186. oken The tripping system 100 of FIG 1 utilizes a number of circuits to determine when the current path should be interrupted This determination is centralized at a mi crocomputer 120 preferably an MC68HC11A1 which is described in MC68HC11 HCMOS Single Chip crocomputer Programmer s Reference Manual 1985 and MC68HC1148 Advance Information HCMOS Single Chip Microcomputer 1985 all being available from Mo torola Inc Schaumburg Ill Peripheral circuits that support the microcomputer 120 include a reset circuit 124 that verifies the sanity of the tripping system 100 a voltage reference circuit 126 that provides a stable and reliable reference for analog to digital A D circuitry located within the microcomputer 120 ROM 128 that stores the operating instructions for the microcomputer 120 and a conventional address and data decoding circuit 130 for interfacing the microcomputer 120 with various circuits including the ROM 128 and a user se lect circuit 132 The address and data decoding circuit 130 for example includes an address decoder part No 74HC138 and an eight bit latch part No 74HC373 to latch the lower eight address bits which are alternately multiplexed with eight data bits in conventional fashion The ROM for example is part No 27C64 The user select circuit 132 allows the user to designate tripping characteristics for the tripping system 100 such as over load and phase imbalance fault conditions The tripping
187. om the microcomputer 120 of FIG 1 The software timer provides a conven tional software watchdog function to maintain the san ity of the display processor If the software timer is not reset periodically within a certain time interval the display processor resets itself The data ready flag is set in an interrupt routine illustrated by blocks 390 through 398 of FIG 35 The display processor is programmed to execute the inter rupt routine when it receives data from the microcom puter 120 of FIG 1 At block 390 of the interrupt rou tine a test is performed to determine if the data byte just received is the last data byte of the packet sent from the microcomputer If the data byte just received is not the last data byte flow proceeds to block 398 where a re turn from interrupt instruction is executed If the data byte just received is the last data byte flow proceeds to block 392 At block 392 a test is performed to determine the integrity of the received data packet This is accom plished by comparing the 8 bit sum of the previously 25 8 received 7 bytes with the most recently received byte last byte If the 8 bit sum and the last byte are differ ent flow proceeds to block 398 If the 8 bit sum and the last byte are the same the display processor sets the previously referred to data ready flag depicted at block 396 and returns from the interrupt via block 398 to block 380 At block 380 the received data is stored
188. on THIS POINT EITHER LOW OR HIGH GAIN HAS BEEN STORED CUR 5 FOR USE 6 MUL STD CUR lt JMP DO PHASEB SUMMATION EI EQU CLR CUR PHASEB STAB CUR 1 DO PEASEB SUMMATION BEQ LAST B ADD MUL ADDD RMS SUMSQ 2 STD RMS SUMSQ 2 BCC WORD B OK LDX RMS SUMSQE 2 INX STX 5 SUMSQH 2 EZ WORD B OK 5 LDAA CUR 1 LDAB CUR BEQ B_I_SQUARE_DONE MUL LSLD move low byte to ACCA for 0 check multiply low byte by low byte double to low 16 bits save it if set increment the high byte and save it get low byte get high byte for 0 check 15 high byte 0 we s done result is shifted to multiply by 2 sane as 2 multiplies amp an add ADDD RMS SUMSQH 2 1 STD SUMSQH 241 5 D Company ADE Group Jerry Baack Leon Durivage add low high to middle 16 bits sand save it Date 8 16 85 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING BCC LAST B ADD INC RMS SUMSQE 2 LAST B ADD EU S LDAA CUR BEQ B I SQUARE DONE TAB MUL ADDD SUMSQH 2 STD RMS SUMSQE 2 I SQUARE DONE EW 5 Carry was set increment the high byte get high byte 112 0 we re finished move to ACCB smultiply for last value to high 16 bits store back to accumulator AT THIS POINT B PHASE 172 SUMMATION IS FINISHED A
189. on sud denly occurs and the microcomputer 120 has been pro grammed to allow for a two minute delay before gener ating a trip signal at this overload fault level After one minute in this overload condition the microcomputer 120 will have accumulated current information which indicates that it is 50 of the way to tripping The microcomputer will also have enabled the RC circuit 610 to charge to 2 5 v that is 50 of the maximum 5 v Assuming for the purpose of this example that the overload fault condition is removed at this point and the electronic trip system loses operating power when the power to the microcomputer 120 drops to 0 the inter nally stored current accumulation is lost However the voltage across the RC circuit 610 is still present and will start to decay by approximately 63 2 every 5 4 min utes the time constant for the RC circuit 610 There fore after 5 4 minutes without current the voltage across the RC circuit 610 will be 36 8 of 2 5 v or 0 92 v If the overload condition would occur again at this point the microcomputer 120 would power up and measure 0 92 v across the RC circuit 610 The mi crocomputer 120 would then initialize its internal cur rent accumulation to approximately 189 0 92 v di vided by the maximum of 5 0 v of the preprogrammed full trip delay time The accumulation calculations performed by the microcomputer are based on the formula gt gt o 1 where
190. ored FE Fe de e Fe E 5 so o Se 5e gt e 44 Se gt e SET INST TABLE EQU LDAB INPUSW read INST PU switch ANDB SWITCH MASK mask off all but switch actuated bits 2 7 max switch position BLS INST SW GOOD value is good so don t reset it 00 set to minimum INST SW GOOD EQU E STAB INST SWITCE save for INST use move data to BCLR PU SWITCHES 07 clear INST switch data LSRA pshift to position for comm data ORAA PU SWITCEES combine with Phase Unbalance data STAA PU SWITCEES to comm buffer Starts loading PU table location here IDX INST_PU_TBL load x with inst pu table FLAGSS PE BIT STORE TABLE IF NOT PE BREAKER GO READ INST SW LDX PE PU 5 FOR PE BREAKER TYPE LDAB SENSOR read SENSOR size ANDB SWITCH MASK mask it off 2 9 18 is 2000A sensor BLO STORE_ TASLE if less than OE use normal PE LDX INST 2000A get 2000A PE table CPB 2 9 zis 2000 2500A STORE TABLE if equal it is 2000A so branch LDX 11 INST 2500A PE we have 2500A yeereeees THE CORRECT ROW IS FOUND SO SAVE IT TO MEMORY eexeeesieen 5 089 928 67 68 STCRE EQU 5 STX TEMP found correct row so save it LDAB INST SWITCE switch for positioning BRSET FLAGSS NO ST BiT FINISE TABLE POINTER do INST
191. ory is cleared If GF memory is still active REBUILD GF flag is set GF timers are put to sleep amp any active pick ups are cleared eee RE RARE TREES ES RENEE RELEASES EER RERA LDAA 5 CNTR get soft dog error counter BPL ALL if not SFF this is softdog reset so clear LDAA GFPUSW read the GF pick up switch ANDA SWITCH_MASK mask it SW POS maximum on position 8 BHI ALL GF 45 off so don t set memory flag LDAA PORTA X read portA inputs Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING WE RE FIXED ANDA 4501 check for GF memory cap BNE ALL if bit is set clear all memory CLR FLAGSS clr FLAGSS so only rebuild bit is set BSET FLAGSS REBUILD GF SET TO rebuild accum BSET GF LONG TIME T INACTIVE put trip timer to sleep BCLR GF FLAGS GPF PU turn off any pick up GF MEMORY IS STILL ACTIVE SO ONLY CLEAR RAM ABOVE GF VARIABLES EQU memory active so don t clear GF RAM LDX VARS don t clear GF variables JMP CLR MEM igo clear memory CLR ALL MEM CLR MEM RAM IS CLEARED w NO ACTIVE GF MEMORY SO CLEAR ALL RAM LOCATIONS EQU LDX EQU CLR INX BLO START_VARS SET X TO POINT TO VARS TO CLEAR CLEAR ALL VARIABLES IN RAM 7 0 CLEAR BY
192. oup Jerry Baack Leon Durivage 2 16 SERIES III ELECTRONIC TRIP 2 5 SOFTWARE LISTING to find the root mean square for Square sum location 15 assumed 32 bit value 4 contiguous memory locations RETURNS Root Mean Square rcot of number in location RMS 5 Routine makes assumption that 128 values have squared and sumned before this calculation is made COMMENTS Entered from MAIN with 128 values summed from the SQSUM routine takes the average and puts it in MEAN Then uses that valve to calculate the square root Index X equals the location of the sim of the squares for the phase to be calculatec Ss a Se Se ve ca 5e 5 089 928 115 116 USED ACCB IX IY RESTORED IX seus beens aera On PSEUDO CODE FOR MEAN SQUARE ROUTINE THIS IS WRITTEN IN include lt stdlib h gt P include stdio h 24 include math h int x pass min pass max pass avg pass i global variables slong sum tbl1 3 avg pass sum rms mean rms guess 18 255 443 572 677 768 849 923 952 1055 1116 1173 1228 1279 1330 1379 1425 1471 1511 global variables avg i int long templ temp2 temp3 result remainder rt H routine dependant variables rms mean sum tbl x 128 find mean of sums for current channel y rms mean 131072
193. power to activate the solenoid 112 and attempts to do so If VT is read as a logic low the microcomputer 120 determines that there is insufficient power to acti vate the solenoid 112 and waits while repeatedly checking VT in anticipation that an intermittent power fault caused VT to fall Once VT rises beyond the 2 5 3 0 volt level the microcomputer 120 attempts to activate the solenoid once again 20 25 30 45 50 55 60 65 18 G Communication For Information Display The microcomputer 120 sends identical tripping sys tem status information to the local display 150 and the display terminal 162 The information is sent synchro nously on a serial peripheral interface 191 to the local display 150 and asynchronously on a serial communica tion interface 151 to the display terminal 162 The inter faces 151 and 191 may be implemented using the SCI and SPI ports internal to the MC68HC11 The history of the tripping system status information is stored in the nonvolatile trip memory 144 That history includes the specific cause and current level of the last trip and a running accumulation of the different trip causes The trip memory 144 is preferably an electrically erasable programmable ROM EEPROM for exam ple a X24CO4I available from Xicor Inc of Milpitas Calif In this case the serial peripheral interface 191 is used for bidirectional data transfer between the mi crocomputer 120 and the EEPROM 144 This da
194. r BEQ RESET timer 0 so reset INST function STAA INST timer for compare 2 90 145 inst timer above 90ms BLS CHK INST PU so check for INST PU CLR INST CNTR 4 reset inst pick up count JMP WAIT FOR EI 5 so forget instantaneous IF TIMER IS 0 RESET INST TIMER TIMER FLAG AND PICK UP COUNTER RESET TIMER CLR 5 CNTR 4 reset inst pick up count LDAA 2 100 GET RESET VALUE INST TIMER STAA INST TIMER reset inst timer to 100 ms BCLR INST FLAGS I make timer not active THIS SECTION GETS THE INST PU LOCATION FROM MEMORY STORED POINTERS CEX INST PU LDX TABLE VAL table row amp column in IX LDAA 1 get INST PU value for compare OPA compare to phase BLS INST PICK UP if phase current greater we have P U L_PHASES compare to B phase BLS INST_PICK_UP 12 phase current greater we have to C phase ELS INST PICK UP if phase current greater we have P U CLR CNTR 4 reset inst pu counter INST FLAGS INST PU BIT clear inst pu bit WAIT FOR GO wait for A D to get done INST PICK UP BSET INST FLAGS INST PU 5 inst pu flag BSET INST FLAGS I _ set inst timer active bit LDX REGSTART T set 6811 io reg base i
195. r capacitor 574 100 microfarads for capacitor 584 10 microfarads for ca pacitor 582 100 K ohms for resistor 585 10 K ohms for resistor 589 0 1 microfarads for capacitor 587 and part No 6660 for IGFET 583 Diodes 576 and 578 are used to receive current from an optional external power supply not shown 4 Establishing The Current Rating On the left side of the rectifier bridges negative phase signals A B and C from the bridges are provided to the burden resistor arrangement 530 including a rating plug 531 to set the current rating for the tripping sys tem As previously discussed when the primary current is 100 of the rated current or sensor size which is designated using user select circuit 132 the current transformer output current will be 282 8 milliamperes RMS Thus when the microcomputer 120 reads the burden voltages using the gain circuit 134 FIG 1 the microcomputer 120 can calculate the actual current in the lines 106 FIG 4 illustrates parallel connections between re spective resistors 527 and 529 which are used to estab lish the maximum allowable continuous current passing through the lines 106 The resistors 527 are part of the rating plug 531 and the resistors 529 are separate from the rating plug 531 The resistors 529 for example are each 4 99 ohm 1 5 watt resistors This value should be compared to a corresponding value of 12 4 ohms for the burden resistor 525 for the ground fault signal
196. r or same don t mess LAST CPEASE if higher save new value THE VALUES LAST B ARE LOW GAIN PASSED OUT WITHOUT 6x MULTIPLE i THESE VALUES ARE USED ONLY IN SHORT TIME amp MULTIPLIED BEFORE USE RD MEM RATIO EQU LDAA ADR4 X READ MEMORY RATIO A D STORE MEMORY RATIO A D TO RAM SPI IS TURNED OFF EERE BSET DDRD X S3E set portD for all available outputs here BSET PORTD X SCL SDA set data amp clock lines high BRCLR GF FLAGS TURN ON DESENSE FINISH PORTD BSET PORTD X GF DESENSE OUT turn on the desense line FINISH PORTD EQU BCLR 5 540 kill SPI and enable PORTD BRCLR IFLAGS TRIPPING I INSTANTANEOUS JMP WAIT FOR 1 we are tripping don t run INST Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 85 5 089 928 133 134 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING I INSTANTANEZOUS EQU BRSET INST FLAGS I TIMR I TIMER 1 discriminator on timer i BRCLR INST FLAGS INST OFF BIT I TIMER INST on check timer WAIT FOR Wait for hi gain A D TIMZR EQU BRCLR INST FLAGS I TIMR BIT CEX INST PU timer so check PU 3 IF WE GET BERE TEE TIMER MUST BE ACTIVE LDAA INST get INST timer DECA sub 1 ms from inst time
197. rrupt the current on lines 106 the local display is still able to operate on a limited basis This sustained operation is performed using the battery 338 as a sec ondary power source The battery for example is a 3 to 3 6 volt lithium battery having a projected seventeen year life The battery 338 supplies power to portions of the local display 150 only when two conditions are present 1 the latch 320 has received a trip signal from 5 089 928 7 the microcomputer 120 or the test switch 311 is acti vated and 2 the output voltage level of the 5 V power supply is less than the voltage level from the battery 338 When the latch 320 latches in any one of the four trip indication lines from the data lines 318 a control signal is generated on a latch output line 340 The control signal turns on an electronic switch 342 which allows the battery 338 to provide power at Vcc so long as a diode 344 is forward biased The diode 344 is forward biased whenever the second condition is also present Thus when the output voltage level of the 5 V power supply is less than the voltage level from the battery 338 the diode 344 is forward biased and the battery 338 provides power to the local display 150 In addition the diode 344 is forward biased until a switch 346 activated by a power up circuit 348 allows the 5 V signal to provide power at The power up circuit 348 activates the electronic switch 346 only after resetting the displa
198. s for resistor 557 and 0 03 microfarads for capacitors 549 and 561 The amplifiers 551 and 663 are for example part No LM124 Using the gain circuit 134 the microcomputer 120 measures the true RMS current levels on lines 106 by sampling the burden voltages developed at signals A B and C The RMS calculations are based on the for mula y 1 0 2 TRMs where 20 25 40 45 55 65 10 continued the number of samples time at discrete intervals 1 determined by sample rate and the instantaneous value of the Ko current flowing through the breaker The current flowing through the circuit breaker is sampled at fixed time intervals thereby developing The value of this instantaneous current sample is squared and summed with other squared samples for a fixed number of samples N The mean of this summation is found by dividing it by N The final RMS current value is then found by taking the square root of the mean In FIG 5 an example of a rectified sinusoidal current waveform is illustrated for 1 5 cycles of a 60 hertz signal with a peak amplitude of 100 amps The sampled cur rent is full wave rectified The vertical lines represent the discrete points in time that a value of current is sampled With a sample rate of 0 5 milliseconds over 25 milliseconds of time 50 samples will be taken In TABLE 1 the data for the samples from FIG 4 are illustrated the column label
199. serial comm JSR 10 TIME DO LONG TIME ROUTINES r4 d END OF 64 MS ROUTINES THE FOLLOWING ROUTINES ARE DONE EVERY 250 MS xwwwewwweww Every 1 4 Sec Long Time LED is flashed if needed 1 Second timer is incremented and Type of Trip Unit is read for serial comm CHECK 250MS LDAA T 250MS LOAD 250 MS TIMER CMPA 250 215 IT DUE YET BLO CHECK 1 SEC NO IT IS NOT DUE SUBA 250 reset the timer STAA T 250MS ALL ROUTINES DONE CLEAR TIMER INC T 1000MS increment 1 sec timer BCLR FLAGSS KILL SERIAL 25 Sec allow serial comm JSR CHECK LED SET LED ON OR OFF AS REQUIRED BY PICKUP JSR SET TYPE OF TRIP UNIT SWITCH POSITIONS DO TIMR 0 Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 85 61 5 089 928 62 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING CHECK ae and if there are any EECK 1 SEC EQU LDAA BLO SUBA STAA T 1000MS JSR SENSOR BREAKR BRSET SOFT DOG CNTR 80 i T 1000MS checks JSR DEC SOFT DOG CHECK TIMR Q 2 o e e e ee e ce e e det END OF 250 MS ROUTINES de de de ie e je e e ee THE FOLLOWING SOFTWARE IS DONE EVERY SEC x dtke n xx Every Second the Sensor and Breaker type is read for serial transmission Softdog errors those routines
200. set to 50 on power up RETURNS NEVER Trips the breaker we de e de e e e e dee ec e e e e e cfe e e e e e de e de e e e ie e e e e e e e e le e e e e e e e le de ee e e e e fe cf ede re e d d a e te EPROM ERASE EQU LDX TRIP START OF AREA TO ERASE CLRING EQU 5 CLR O X clear data location INX CPX RATIO to last location BLO KEEP CLRING JSR ADDRESS 1 WEE address EEPROM to start write JSR WRITE EE all 05 to EEPROM SEI turn off interrupts WAIT_FOR_WDOG JSR RESET COP don t want softdog trips JSR WAIT sdelay WAIT ut WDOG branch to keep happ RSTRSTRSTRSTRSTRSTRSTRSTRSRTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTRSTR This routine sends 8 start pulses to reset the E 2 part before reading data and ACCB are used and not restored in this routine CALLED From initialization with SPI shut off RETURNS With E squared reset and ready to recieve the rest of the Code to read data from the EEPROM deco wow de eoe de e de e e fe e de e e e sie ede e e ecd e e e e e e e e d RU Y m e ede ded Rt d RESET EE EQU LDX REGSTART get onboard register start BSET PORTD X SDA SCL set clock amp data lines high Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 5 089 928 71 72 SERIES III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING BSET DDRD X SDA S
201. shift it LDAB 1 load good sensor SEIFT IT EQU LSRB shift for correct position in byte STAB SENSR TU ID save to xmit buffer BSET SENSR TU ID HARD VERSION hardware is version 1 3 RTS zall done go back to main dee de eor oie d e men d CHECK LED SUBROUTINE de dece e d d den CALLED Every 25 Sec to check LTPU LED No conditions are passed into the routine Rovtine reads Long Time flags for its decisions RETURNS Lonc Time LED eithe on or off depending on condition of Long Time pick up flag USED IX RESTORES IX not changed ARS ASLA LRA AAAS ASE ES AREER RSE ST SEPT TPP PP PPT Ter ss a LED EQU LDX REGSTART set index to start of 6811 registers BRCLR LT FLAGS LT PU BIT TRY 90 sif pickup bit is off try 90 BSET PORTA X LED have pick up so set led on Se Se gt RTS TRY 90 5 BRSET LT FLAGS LT PU90 BIT TOGL LED 214 90 pick up go toggle BCLR PORTA X LED BIT O else no pickup so turn led off RIS TOGL LED PORTA X LED O CLEAR LED BSET LED BIT 1 Is now off so turn it on RTS CLEAR LED EQU BCLR PORTA X LED turn led off RTS SERIAL TRANSMISSION SUBROUTINE 1 1 1 11 01201 EE P ETE P E E PG E EE EL D ELE E LG CALLED Every 7mSec in normal operating mode or as fast as possible if breaker is
202. switch positions If ST or GF is installed that bit is set OPTIONS for communications If amp in position 9 or 10 is forced to on n position 1 or 2 TRIP EQU 5 z LDAB STPUSW STPU SWITCH VALUE ANDB SWITCH MASK MASK OFF BIT 0 CMPB MAX SW POS CHECK FOR OFF POSITION BLS HAVE ST lt 14 WE HAVE ST INSTALLED BRCLR RP OPTIONS MOTOR PROT BIT ALLOW OFF ANDB SW POS mask high bit if JMP HAVE ST switch is OK do LRC comm ALLOW OFF EQU 5 BSET FLAGSS NO ST SET FLAG TO SHOW ST NOT INSTALLED CLR 5 SWITCHES no ST installed so clear switch values BSET RP OPTIONS NO ST TO SHOW ST NOT INSTALLED ST branch around switch set code EAVE ST EQU 5 x LSRB do shift to get PU in correct position LDAA STDELSW get delay value ANDA SW POS mask off unused bits LSLA shift to bits 3 5 LSLA shift to bits 3 5 ABA to PU switch value STAA ST SWITCHES store in xmit location BCLR 1 55 ST CLEAR FLAG TO SHOW ST INSTALLED BCLR OPTIONS NO ST TO SHOW ST INSTALLED NO S7 EQU LDAB GFPUSW GET GFPU SWITCH VALUE ANDB SWITCH MASK MASK OFF BIT 0 CMPB SW POS 2 FOR OFF POSITION 5 089 928 69 70 BLS HAVE GF lt 14 GF IS INSTALLED
203. t address byte CLRA Clear ACCA for data start location JSR SEND ADDR send start address RTS return to calling routine ADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDRADDR WAIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRIWRI THIS SUBROUTINE WRITES THE DATA POINTED TO BY TO THE EEPROM IF THE ROUTINE IS USED TO ADDRESS THE E 2 ACCA EOLDS TEE DATA AND IY MUST BE SET F000 OR GREATER TO EXIT CORRECTLY 9 5e 4 5e 4 THE ENTIRE HISTORICAL DATA FROM THE RAM WILL BE WRITTEN TO TEE EEPROM IF THE ROUTINE IS ENTERED AT WRITE EE EXTETYETATETESATTETETATETEEATRETERETEEERETETSETERERTARTAETERERRTERSERETTREREERIrTTTTEN WRITE EE EQU ve LDY TRIP FIRST BYTE ADDRESS TO STORE LDX REGSTART get onboard register address for clock data LCAD NEXT BYTE EQU LDAA 0 load indexed from IY 1 a jump to this point sends only what is already loaded into Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 5 III ELECTRONIC TRIP SYSTEM SOFTWARE LISTING ADDR EQU BCLR PORTD X SCL set clocx line low BSET DDRD X SDA turn data into an output clear carry to use as hi low bit indicator LDAB 08 load of shifts for 1 byte CLOCK clock low for loading bit onto serial bus BCLR PORTD X SCL set clock line low LSLA shift high bit to
204. ta transfer is implemented using one line of the serial pe ripheral interface 191 to transfer the data and the other line to transmit a clock signal between the microcom puter 120 and the EEPROM 114 for synchronization During power up of the tripping system 100 the mi crocomputer 120 transmits to the trip memory 144 a unique bit pattern which is interpreted as a data request code The microcomputer 120 then sets the bidirec tional data line as an input and clocks the requested data in from the trip memory 144 The microcomputer 120 maintains a copy of the his tory data in its internal RAM and in the event of trip updates it and transmits it back into trip memory 144 via the interface 191 again utilizing the unique bit pattern to set the trip memory 144 to a receive mode Upon receipt of the data trip memory 144 will reprogram its contents overwriting the old history information with the newly received data During normal operation after power up and without a trip the microcomputer 120 transmits opera tional information over the serial peripheral interface 191 Because this information does not contain the unique bit patterns required to activate the trip memory 144 the trip memory 144 ignores the normal transmis sions However other devices which may be connected to the serial peripheral interface 191 can receive and interpret the information correctly The microcomputer 120 for example is programmed to execute a
205. that the rate of heat loss is proportional to the temperature of the power system conductors above ambient temperature In particular the temperature in the tripping system 100 decreases in response to the current path in lines 106 being broken or intermittent When this occurs how ever the microcomputer 120 loses operating power and therefore can no longer maintain this numerical simula tion This problem is overcome by utilizing the thermal memory 138 of FIG 1 to maintain a history of the accu mulated current for a predetermined period of time during which the operating power to the microcom puter 120 is lost As illustrated in FIG 7 this is accom plished using an RC circuit 610 that is monitored and controlled by the microcomputer 120 to maintain a voltage on the capacitor 611 that is proportional to the accumulated square of the current When the mi crocomputer loses power the voltage across the RC circuit 610 logarithmically decays The decay is gov erned by the equation Voexp t RC Should the microcomputer power up again before the voltage reaches zero the microcomputer 120 reads the voltage across the RC circuit 610 using a conventional analog buffer 612 and initializes its delay accumulator to the correct value The analog buffer 612 for example in cludes an amplifier 627 such as part No LM714 and a 4 7 K ohm resistor 629 The preferred RC circuit 610 including a 100 micro farad capacitor 611 and a 3 2
206. the portA lines check for trip bit in trip cause out to portA turn or keep trip volts if ready for next byte low voltage kill trip signal c if is not set wait TDRE is set so transmit get pointer for current A D current A D value compare to A D value of 10 allow for noise if lower check next phase clear timer not time to re initialize yeti 1 for 8 bit words to memory location until all phases have been checked get timer for reinitialize if we go 128 mSec w no current initialize TU play it again Sam t ll we die no current flowing so reinitialize the TU S dt de dee dede dede de de eoe ede e de e e e e e de de de d do dede c ded m TET dera em ROUTINE TO CHECK VT LINE BEFORE TRIPPING 9 v Called with IY set for delay 1 pass equals 7uSec GE Ra uTUdAXERETETE XTETERTETITETETETA TER ARTTETENTETEYTRETERTTETETENEESXXETEN Y 5 089 928 87 88 VT CHECK LDX SUPPLY trip supply location IS CAP CEARGED EQU BRCLR 0 VOLTS CAP 7 if low voltage decrement amp try BRA GLOBAL JUM return 6 trip RECHECK CAP DEY 4 15 CAP CHARGED 3 cap voltage again GLOBAL JUMP IDX REGSTART start of registers BSET PORTA X TRIP TRIP BREAKER UMP GLOBAL TRIP q
207. through the address and data decoder 130 of FIG 1 Each BCD dial 812 allows the user to select one of several tripping system characteristics For example a pair of BCD switches may be used to designate the longtime pickup and the longtime delay overload trip ping characteristics and another pair of BCD switches may be used to designate the short time pickup and the short time delay short circuit tripping characteristics Other BCD switches may be used to designate sensor and breaker sizes an instantaneous pickup ground fault tripping characteristics and phase unbalance thresh olds F Energy Validation For Solenoid Activation The user select circuit 132 of FIG 1 and 9 also deter mines if there is sufficient energy to activate the sole noid 112 Using the address and data decoding circuit 130 the buffer 820 is selected to read one of its input lines 830 The VT signal from the power supply 122 of FIG 1 feeds the input line 830 with the buffer 820 being protected from excessive voltage by a resistor 832 and a clamping diode 834 The resistor 832 for example has a value of 620K ohms Before the microcomputer 120 engages the solenoid 112 the input line 830 is accessed to determine if VT is read as a logic high or a logic low The buffer 820 pro vides a logic high at its output whenever the input is greater than 2 5 v to 3 v If VT is read as a logic high the microcomputer 120 determines that there is suffi cient
208. tive in response to the power from the tripping system current path being in excess of a second level that is greater than the first level for controlling the indicator means wherein the second level corresponds to the trip indicator circuit receiving power from the monitored cur rent such that the display means indicates when there is at least a minimum of power being drawn from the monitored current but not necessarily sufficient power to operate the control means 10 A trip indicator circuit according to claim 9 wherein the display means includes means to indicate a percentage of maximum allowable continuous current in the current path 11 A trip indicator circuit according to claim 9 wherein the display means includes a plurality of bar indicators for indicating one of a plurality of percent ages of maximum allowable continuous current in the current path 12 A trip indicator circuit according to claim 9 wherein the second level corresponds to the system providing operating power to the trip indicator circuit 13 A trip indicator circuit according to claim 9 wherein the display is an LCD type and the indicator means includes an LCD bar segment s
209. to providing flexibility to power distribution systems processor based tripping systems must also efficiently and reliably display their status in a cost effective manner SUMMARY OF INVENTION In view of the above a preferred embodiment of the present invention includes a fault powered processor based circuit breaker tripping system having a low power trip indicator circuit that is normally powered from the tripping system An LCD is used to indicate the status of the system and a battery is used as a sec ondary power source after a trip terminates the power to the system The battery is activated by a latch which responds to one of a plurality of trip signals from the processor The latch also provides signals to a driver circuit to drive the LCD Once activated the battery 30 35 40 45 50 55 60 65 2 provides power to the LCD driver circuit so that the cause of the trip may be displayed after a power fault Another aspect of the present invention involves an indication to the user that the fault powered system is sensing a low amount of power from the current path A segment is employed on the LCD in response to a steady state signal representing the power in the current path to indicate that a low level of power below all fault levels and insufficient to power the tripping sys tem is in the current path BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become
210. ttwrwwt ese Square D Company ADE Group Jerry Baack Leon Durivage Date 8 16 89 5 089 928 81 82 THIS SUBROUTINE CALCULATES PHASE UNBALANCE FOR ANY OF THE TEREE PHASES CALLED IX points to phase of unbalance wanted RETURNS ACCB holds percent of unbalance 2 used for 5 precision errr rrrerrrrrrrrrrrr rrr 2 27 2 2 UNBALENCE EQU LDD SORT GET A PEASE SQUARE ROOT 7 ADDD 5 SQRT ADD B PEASE ADDD SQRT ADD C PHASE STD THREE PEASE SUM STOR TEE RESULT WE HAVE SUMED UP ALL THREE PHASES NOW GET 3 PEASE VALUE LDD 0 LOAD PHASE UNBALANCE IS WANTED FOR ADDD 0 ADD IT TO ITSELF ADDD 0 DO IT AGAIN SAM STD TEMP save 3 phase value now see if sum Of phases or phases is greater value THREE PHASE SUM COMPARE SUM OF 3 PHASES TO 3 PHASE BLO SUM IS GREATER 3 PHASE SUM IS GREATER SUBD THREE PHASE SUM SUBTRACT 3 PHASE SUM FROM 3 PHASE STD RESULT three phase sum JMP PEASE SUM IS GREATER EQU LDD THREE PHASE SUM PUT 3 PHASE SUM IN ACCD SUBD TEMP SUBTRACT 3 PRASE FROM 3 PHASE SUM STD RESULT three phase sum 3 phase COMPARE RESULT TO THREE PHASE SUM CONT PHASE CPD THREE PHASE SUM is ratio of phase gt sum BLO FIND THE GO FIND UNBALANCE SET amp 99 WEICH IS THE MAXIMUM FOR PHASE UNBALENCE LDAB 199 maximu
211. xed out put current level For example for a 200 Amp circuit breaker each current transformer 510 512 and 514 will produce the same current output signal when operating 5 089 928 9 at 100 200 Amps as a current transformer in 4000 Amp circuit breaker which it is operating at 100 4000 Amps The preferred construction yields a current transformer output current of 282 8 milliamperes RMS when the primary current is 100 of the rated current The output currents provided by the transformers 510 512 and 514 are routed through a ground fault sensing toroid 508 full wave rectifier bridges 516 518 and 520 and the power supply 122 to tripping system ground The output currents are returned from tripping system ground through a burden resistor arrangement 530 The ground fault sensing toroid 508 sums the out put currents from the transformers 510 512 and 514 In a system utilizing a neutral N line 106 the ground fault sensing toroid also sums the output current from a trans former 506 which is coupled to the neutral line N to sense any return current signal representing this current summation is produced at an output winding 509 and is carried to a fourth rectifier bridge 522 The rectifier bridge 522 is used to detect ground fault condi tions and is discussed in the second part of this section On the right positive side of the rectifier bridges 516 522 positive phase current signals are produced and added together
212. y processor 316 The pow er up circuit 348 for example is part No ICL7665 working in connection with resistors 349 351 and 353 having values of 620 K ohms 300 K ohms and 10 meg ohms respectively Power is provided from Vcc only to the latch 320 the LCD driver 326 the LCD driver 330 and the oscil lator circuit 328 The LCD driver 330 and the oscillator circuit 328 receive power from either the battery 338 or the 5 V power supply output via diodes 350 and 352 This arrangement minimizes current drain from the battery 338 while allowing the user to view the status of the tripping system 100 during any power fault situa tion Power cannot be drawn from the battery 338 unless the battery 338 is interconnected with the remaining portion of the tripping system via connector 310 be cause the connector 310 provides the ground connec tion for the negative terminal of the battery 338 This aspect of the local display 150 further prolongs battery life and therefore minimizes system maintenance In FIG 35 a flow chart illustrates the preferred pro gramming of the display processor 316 The flow chart begins at block 376 where the memory internal to the display processor is initialized The memory initializa tion includes clearing internal RAM input output ports and interrupt and stack registers At block 378 a software timer is reset and the display processor waits for a data ready flag which indicates that data has been received fr
213. yed POC CRSP EPR SEE E EE SRE RSE EEE check timer to reset inst timer go check SC restraint timer igo reset the instantaneous timer get the SC restraint timer 14 lt gt 0 check the ST retention timer get restraint timer get retention timer for ST if lt gt 0 check 172 out timer go run ST retention time out code get ST 172 out timer if lt gt 0 continue timer check trip don t return out run correct routines 8 16 85 SERIES ELECIRONIC TRIP SYSTEM SOFTWARE LISTING BRSET FLAGSS NO GF BIT RETURN TOP RESTRN TIME BNE FOR RETN JSR RESTRN OFF FOR RETN EQU LDX GF KETN TIME _ CHECK FOR FIXED JSR RETN TIMOUT FOR FIXED EQU zif no GF bypass get restraint time zif not 0 continue stimer 0 go kill restraint line retention time if not 0 continue timez 0 go reset timers 5 089 928 63 64 LDX GF LONG TIMZ restraint timer RETURN TO TOP if not 0 continue JM TRIP timer 0 go trip RETURN TO EQU 3 RIS return to main END OF CHECK ALL TIMERS ROUTINE x3 dede eder 55555555555555555555555555555555555555555555555555555555555555555555555555555 SWITCH READ HERE AND ANY NON DEFINED TYPE IS SET T

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