Maxim Integrated - DS26324DK Datasheet Maxim Integrated
Contents
1. 11 SUFTNABE ECONFIGURATBJIB A 12 UCK START 12 MEMOR OO 12 Table DS26334DK Relative Address MOD ea YR CREE ak CARE x ERA AR RARE 12 Table 7 General Purpose FPGA Memory Map sass a 12 ID REGISTER 13 13 25510404 INFORMA NON 21 320224 INFORMATION 21 DS26334DK DS26324DK INFORMATION c ee ee rer erre erre eee e nono aenean 21 MM 21 15 21 SCHEMATICS 21 2 46 DS26334 DS26324 Design Kit COMPONENT LIST DESIGNATION QTY DESCRIPTION C1 CA C6 C7 C31 C33 C41 43 46 C49 C51 C54 56 66 0 1uF 20 16V X7R ceramic capacitors 0603 0603YC104MAT C58 61 93 95 108 C2 C3 C27 C37 Panasonic C42 C48 C50 10 1uF 21096 16V ceramic capacitors 1206 C55 C59 C60 ECJ 3YB1C105K C5 C16 C26 C30 Panasonic C34 C35 C942. IO 137 106 U3 IOS CY62128U IO3 SOIC 102 010 CY62128UL 70SC o 000 65 5 o9 L9 RUN_KIT_USR FLASH_UPP MICRODATA_ lt 15 gt TIM_16H_8L CY62128U SOIC 2128 705 MICRODATA_ lt 15 gt MICRORDD 17 MASTER MODE BOOT INTERNAL 2 INTERNAL FLASH EN TITLE DATE SRAM TCLK334 16 TCLK334_ lt 16 TCLK334_ lt 16 TCLK334_ lt 16 RCLK334 16 RCLK334_ lt 16 RCLK334 16 RCLK334_ lt 16 TPOS334_ lt 16 TPOS334_ lt 16 TPOS334_ lt 16 TPOS334_ lt 16 RPOS334_ lt 16 RPOS334_ lt 16 5334 16 RPOS334_ lt 16 TNEG334_ lt 16 334_ 16 TNEG334_ lt 16 TNEG334_ lt 16 RNEG334_ lt 16 RNEG334_ lt 16 RNEG334_ lt 16 RNEG334_ lt 16 RLOS334 16 RLOS334_ lt 16 RLOS334_ lt 16 RLOS334_ lt 16 TCLK334_ lt 16 TCLK334 16 TCLK334_ lt 16 TCLK334_ lt 16 RCLK334 16 RCLK334_ lt 16 RCLK334_ lt 16 RCLK334_ lt 16 TPOS334_ lt 16 TPOS334_ lt 16 TPOS334_ lt 16 TPOS334_ lt 16 RPOS334_ lt 16 RPOS334_ lt 16 RPOS334_ lt 16 S RPOS33A 16 TNEG334 16 4 lt 1 P TNEG334 16 TNEG334_ lt 16 RN
3. 2175 CONN 14P 1907 51 1 2185 CONN 14P 18 7 RES1 20D4 2185 CONN 14P 1907 2161 CONN 14P 19 5 RES1 2084 21 2 CONN 14P 1905 2 n2 CONN 14P 1965 RES1 981 CONN 14P 1905 RES1 1781 R114 ENGINEER _ RES1 RES1 RES1 RES1 19 5 RES1 Sce RES1 RES1 RES1 RES1 1 RES1 Sce RES1 1885 RES1 20D6 RES1 aca RES1 1886 RES1 aca RES1 2002 RES1 20C6 RES1 RES1 10 2 RES1 2 B2 RES1 RES1 2005 RES1 20C6 RES1 1105 RES1 2082 RES1 20D6 RES1 RES1 RES1 1082 RES1 RES1 2105 RES1 1282 RES1 RES1 2007 RES1 RES1 RES1 RES1 5 RES1 RES1 RES1 RES1 RES1 RES1 5 RES1 RES1 RES1 PUSHBUTTON 1185 PUSHBUTTON 1788 SWITCH_DPDT_SLIDE_6P 1886 SWITCH_DPDT_SLIDE_6P 15 4 SWITCH_DPDT_SLIDE_6P 1888 PUSHBUTTON 12B3 SWITCH 8 1282 XFMR QURDT1E1 TGB3 U 783 787 7B3 7C3 7 7 703 707 XFMR_QUADT1E1_TGB3_U BBS 8B XFMR QURDT1E1 TGB3 U 983 2 9C3 9 7 902 907 XFMR_QUADT1E1_TGB3_U 1883 1087 1082 1087 10 1807 1803 1807 FT245BM U 16 5 2107 1 17 2 17 CY6
4. 1 USER GLK 1118 S 4RST334 INT334 2 4 TITLE DATE RLOS INT LEDs PROG CLKS 70533400 5 RCLKENABLE_BERT RCLKIN BERT TDI 48 29 42 1 Aja BICLKOUT BERT TuS ES 9 15 XC18U02 21 25 WR LOCRL SPI 0526334 1 2TDAT BERT RESET CFGPRM 13 ly 14 ALE334 SCLK 0525334 CPx 185334 _MCLK334 CSB 0526334 5 1 23 TCK RCLK_EN YVDD lt gt VDD 1 0 21740 UA 052174 SERIAL FLASH ADDRESS_LOCAL_ lt 8 QUICK LIU CFG SPI gt CS_BERT RD_LOCAL 8 WR_LOCAL 143 15 05 808 SWITCH 3 3 0198 EUQPREDAM SWS MAX6816 GND UCC 50 _ lt 7 25 TCLK_EN TCLKENABLE_BERT GND gt GND lt 1 gt GND lt 2 gt GND 3 22 29 43 3 ICLKENABLE BERT e R61 JDS3340UT_SPI_PROM_IN 1 2 JTDO TITLE DATE EBERT x 1 SPI PROM UccINTs D4 uccINT4 D13 9 o 10 N13 UCCINT11 P3
5. Bits 7 to 0 D7 to DO These bits control the source of the TCLK for the BERT BTCLK DESCRIPTION 0x00 RCLK Port 1 0x01 RCLK Port 2 0x02 RCLK Port 3 0x03 RCLK Port 4 0x04 RCLK Port 5 0x05 RCLK Port 6 0x06 RCLK Port 7 0x07 RCLK Port 8 0x08 RCLK Port 9 0x09 RCLK Port 10 Ox0A RCLK Port 11 OxOB RCLK Port 12 0 0 RCLK Port 13 OxOD RCLK Port 14 OxOE RCLK Port 15 OxOF RCLK Port 16 0x10 1 544MHz On board oscillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 0526334 0 14 0526334 0 15 TCLKBERT OUT 0x16 OxFF HI Z 15 of 46 0526334 0526324 Design Kit Register Name BRCLK Register Description BERT RCLK SOURCE Register Offset 0 0 Bit 7 6 5 4 3 2 1 0 Name 07 06 05 04 03 02 01 DO Bits 7 to 0 D7 to DO These bits control the source of the RCLK for the BERT BTCLK DESCRIPTION 0x00 RCLK Port 1 0x01 RCLK Port 2 0x02 RCLK Port 3 0x03 RCLK Port 4 0x04 RCLK Port 5 0x05 RCLK Port 6 0x06 RCLK Port 7 0x07 RCLK Port 8 0x08 RCLK Port 9 0x09 RCLK Port 10 Ox0A RCLK Port 11 OxOB RCLK Port 12 0 0 RCLK Port 13 OxOD RCLK Port 14 OxOE RCLK Port 15 OxOF RCLK Port 16 0x10 1 544MHz On board oscillator 0x11 2 048MHz On board oscillator 0x12 User clock 0x13 CLKA DS26334 DS26324 0x14 TECLK DS26334 DS26324 0x15 TCLKBERT OUT 0x16 OxFF
6. MICRO CFG PROM o XCrO2SUO20C DS26334 JTAG CON ON CE JTAG MUX CFG PROM o 16 PORT FOR DS26334 1 61 71 LIU SPI ONLY BOARD PWR LED 1 1 GREEN NOI SPLIT BOARD POWER SUPPLY AND DUT POWER SUPPLY 0017 UDUT_CON REVERSE BIAS PROTECTION DS26334DK ___ 8 Signal Cross Reference for the entire design ADDRESS_LOCAL_ lt 8 gt 283 12 8 1406 1985 ALE334 12C1 gt 14B7 lt gt 19A3 lt gt 2C7 lt CCLK_A 13B3 lt gt 13B1 CFG_DIN_A 13B1 gt 14B3 lt gt CLKOUT 1407 lt 17D3 CLKOUT_MM2187 17C1 lt gt 1704 lt CS _RAM 17C1 lt gt 18D3 1806 lt CS2_BOARD 14844 17C1 lt gt cs334 12C1 gt 14B7 19A3 lt gt 2C7 11 4 lt CSFPGA 14B7 lt gt 1903 CS_BERT 14B7 lt gt 19A3 lt gt 1288 lt 283 1285 14C3 16C5 1984 DONE_FPGA_A 13B3 13A3 lt 13B1 E1 CLK 11B1 15D6 14844 1703 18D7 EBL 14A4 lt gt 17D3 lt gt 1803 lt FLASH_UPP 18876 17D7 lt FPGA_CLKA 11D3 14C3 11 3 FPGA_EN 14B7 1888 lt 19B3 lt gt FPGA_TECLK 11D3 14B3 lt gt 11 3 INT334 14C3 19B3 lt gt 1188 1105 lt INTERUPT 14B3 17B2 lt gt JDE B 18B2 17B1 lt
7. 1805 CONN 14P 1903 2185 Sce CONN 14P 19C3 ca 1 21B7 21B2 CONN 14P 1902 2185 2182 _14 19 1 1 2175 2193 CONN 14P 1901 cs 2183 2182 CONN 14P 1997 2185 2 CONN 14P 1987 2184 1885 CONN 14P 19 2192 CONN 14P 1987 1 902 21B3 JMP OPEN 2P 984 985 2183 1 1008 1805 igca CONN BNC SP 1807 905 2183 CONN BNC SP 18 7 1885 21B2 CONN BNC SP 1802 21B3 CONN BNC SP 983 21 4 2181 _ _2 904 1 2183 BAL _ _2 1088 1282 2185 CONN BNC SP 1887 705 2192 CONN BNC SP 1887 1081 CONN BNC SP 9C3 21B3 CONN BNC SP 903 786 2181 JMP OPEN 2P 988 806 2182 JMP OPEN 2P 1804 886 2181 CONN BNC SP 1003 2181 CONN BNC SP 1 802 21B2 CONN BNC SP 1587 BAS CONN BNC_SP 2187 5 JMP3 2208 2184 5 JMP3 2207 2184 781 JMP3 2207 1588 JMP OPEN 2P 908 2175 JMP OPEN 2P 1884 2184
8. ST 1nd vEESOdH T ST 10 0 1 20815100 VEEDSNY VEEDSNY lt 1 81 gt rEESOdH lt 1 81 gt vEESOdH lt 1 81 gt vEEOJNMH 7791 vEEOJNH LT STALNO vEESOdMH T SI 10 vEESOdH SIOLOCO vPEEO3NMH lt T 9 vEEO3NMH 77 4 21 0 Veen X T ST 10 gt vEE IH 1819 vEEN IH ST SPLA REEN TOY PEEN OH 7781 gt vEEXNIONH T 9SI vE EX oH REGULATOR 2 5U REGULRTOR REGULATOR 0526334 ONBOARD 3 30 REG CORE VOL FPGA S93EUE 33 317 302 QIC 2 A MP AX1 a S2EUR25 5 0 MART 3 3 1793 0 4 21 OUT1 12 e d IN2 OUT2 13 IN2 oou ore IN3 OUT3 14 INA INS INA 15 RESET B INA OUTA qi EAT ROTA SET RESET B RST SET 5 SHDN GND SHDN GND 18 pute d RARE 1782 1 T 45 0 2 2 OUT1 TITLE DECOUPLING CAPS SU DC POWER SUPPLY REVERSE BIAS PROTECTION MMC2107 XCFO2SUO20C XC2S200 SFG J3 JACK RAPC7T 12 Is 25 0 9
9. 2181 CONN BNC SP 1883 2187 2181 CONN BNC SP 1883 1 1588 LED CONN BNC SP 1575 LED 1887 CONN BNC SP 908 16 8 LED 1187 RJ45_8 7B 704 708 2187 LED 11D7 RJ45 8 1688 LED 11C7 COIL 2P 1705 1784 LED 11D7 RES1 1287 1784 LED 11B7 RES1 12B7 1607 LED 11D7 RES1 2188 LED 11B7 RES1 2084 2108 LED 11D7 RES1 20C4 2185 LED 11B7 RES1 2128 LED 11 7 RES1 2185 LED 11B7 RES1 1607 LED 11C7 RES1 20 2 2187 LED 11B7 51 2185 LED 11C7 RES1 20A4 2187 LED 1187 2187 LED 11C7 RES1 2185 LED 1187 51 2184 LED 1382 51 11 4 2184 SCHOTTKYDIODE1 RES1 2 B2 2188 SCHOTTKYDIODE1 RES1 2184 SCHOTTKYDIODE1 RES1 2802 2185 4_40_HDWR 2281 51 11 4 2175 4_40_HDWR 2281 RES1 11D4 2187 4 2281 2005 1 21 1 4_4 _HDWR 2281 RES1 2082 2187 CONN DB9P 1585 RES1 21C5 2186 USB_BCON_U 1508 2005 2187 POWER_JACK 2208 2161 CONN 4UP 1995 RES1 2005 21 2 CONN BNC SP 1101 RES1 20 2 2185 CONN 14P 16 3 51 2185 CONN BNC SP 1182 RES1 2004 2186 CONN BNC SP 1101
10. RLOS IN EBERT x LIU FRONT END FRONT CON END PORTS 13 16 EDs PROG CLKS 7 SPI PROM BOARD MICRO RAM EST EIUS ES TERMINATION ROL FLASH CFG FPGA BANK 1 FPGA BANK 2 USB AND JTAG CONN ECOU CAPS MISC SIGNAL CROSS RE PART CROSS R 25 PART CROSS R ENGINEER COVER PAG DS26334D MODESEL334 MOTEL334 CS334 ALE334 RD_LOCAL WR_LOCAL RDY334 INT334 4 4 JTCLK JDS3340UT_SPI_PROM_IN JFPGAOQUT_DS3341N JIRST B RST334 D7 R12 T14 D14 ALS 15 B13 E15 B5 MODESEL MOTEL CSx SCLK RLE RSx RDK RW SDI WRX DS INT CLKE MUX JTCLK JTDO JTDI JTMS JTRST RST Ue DS26334_U CONTROL UDDOS2 MCLK 5 1 2 lt 4 gt 5 gt D 1 D 2 D 3 D 4 5 D 6 0 lt 7 gt 455052 RS MCLK334 SCANMODE334 ADDRESS_LOCAL_ lt 8 0 DATA_ lt 7 gt TITLE ENGINEER DS26334 CONTROL DS26334 DATE 6 TRINGO1 E2 RRING334_ lt 16 1 gt 1 4 416 1 Al 4 00 416 1 1 D3 RNEG334_DUT lt 16 1 gt 1
11. 2 1 Oscillator crystal clock SaRonix 1 544 2 1 5440 5 of 46 0526334 0526324 Design Kit BOARD FLOORPLAN cs OOOO GM RLOS PORTS 9 12 TPOS RPOS TECLK CLK A R TNEG RNEG JTAG PORTS 9 16 CON CON XFMR LIU PWR JUMPER Tx Rx CLOCK ON BOARD DATA uC SWITCH MUX RST BOARD RST 0526334 SRAM SWITCHES CON amp lt 05 0 14 lt USER RLOS 0000 OSC TNEG RNEG XFMR E1 T1 750 BNC Qe Losuen 8 Beene 6 of 46 DS26334 DS26324 Design Kit BASIC OPERATION This design kit relies upon several supporting files which are available for downloading on our website at www maxim ic com DS26334DK The support files are used with an evaluation program called ChipView which is available for download at www maxim ic com telecom HARDWARE CONFIGURATION Quick Start Hardware Settings Single Power Supply For single power supply operation short jumpers J44 J45 J46 between the 3 3V pin and the pin This connects VDD of the 0526334 0526324 to the 3 3V supply on the design kit Ensure that the FLASH switch SW3 is in the RUN position Ensure that the FPGA switch SW5 is in the ON position Ensure that SPI PROM switch SW7 is in the OFF position If using the
12. RPOS334_DUT lt 16 1 gt 1 F4 RLOS334_ lt 16 1 gt 1 D2 RRING RTIP RCLK RNEG RPOS RLOS 0526334 0 PORT TRING TTIP TCLK CU TNEG TPOS DATA E2 1 TRINGS34_ lt 16 1 gt 1g 16 1 FS 1 4 TCLK334_ lt 16 1 gt 16 334_ 16 1 gt FB 1 6 lt 16 1 gt TRING 2 Fe RRING334_ lt 16 C2 RTIP334_ lt 16 1 gt 2 C1 RCLK334_DUT lt 16 1 gt RNEG334_DUT lt 16 1 gt GS RPOS334_DUT lt 16 1 gt RLOS334_ lt 16 1 gt 2 G2 RRING RTIP RCLK RPOS RLOS DS26334_U PORT TRING TTIP TCLK CU TNEG TPOS DATA F2 2 RING334_ lt 16 1 gt 2 1 4 15 1 G4 TCLK334_ lt 16 1 gt 114 24 TNEG334_ lt 16 1 gt 2 1205334_ lt 16 1 9 0526334 TRING 3 K2 RRING334_ lt 16 1 gt H2 RTIP334_ lt 16 1 gt H1 RCLK334_DUT lt 16 1 gt 3 K3 RNEG334_DUT lt 16 1 gt 63 4 RPOS334_DUT lt 16 1 gt 3 L3 RLOS334_ lt 16 1 gt J2 RRING RTIP RCLK RNEG RPOS I RLOS 0526334 PORT TRING TTIP TCLK TNEG TPOS DRTR K2 TRINGS34_ lt 16 1 gt sg TITP334_ lt 16 1 gt 1 4 lt 1 1 gt 15 4 416 1 15 5334 lt 1 1 gt TRINGO4 RRI
13. 12 140334_ lt 16 1 gt SMT_XFMR __ 14 2 112334_ lt 16 130 143 CONN BNC UERT 144 SMT _XFMR 004 _ _5 TX1475 235 1 2 15 RTIP334_ lt 16 41 ING334 lt 16 15 RRING334 16 21 LIU FRONT DATE END PORTS 13 16 tad DS26334DK emo poe U1z125 4 INT3341 ann 2 CONN BNC SP 3 FPGA_CLKA 2 1 Y CLOCK 0141127 5 6 0141124 351 SCAN MODE BIAS NA 2138 1 2SCANMODE334 1 NC7SZ86 _ _5 1 FPGA_TECLK 1 TS 4 JS 0141126 5 11 10 1129014 158 U18 E 5 RLOS334 1 amp 1 U18 12 1132 U18 133 E U18 MCLK334 MCLK_FPGA ON BOARD OSCILLATORS 4019 FPGA_CLKA FPGA_TECLK RLOS334_ lt 16 1141 _5 1 2 10K 017 RLOS 7 CLKA MUX 33 RLOS_15 4 a 10 y 6 LED RLOS15 I134 2 15 5 018 398 2 0480 05 28 1142 Wat RLOS 7 TECLK 16 LED RLOS16 RLOS_162 S 1 2 1 CLK 5 8 RLOS334 16 I44 Di7 RED SP LED 0515 zi dm 526334 BED LED 0515
14. Bit 7 0516 This bit enables the RLOS16 LED This should not be enabled when driving from the DS26334 DS26324 If ENRLOS16 LOW the RLOS16 LED is not enabled If ENRLOS16 HIGH the RLOS16 LED is enabled and lights when RLOS16 is high Bit 6 ENRLOS15 This bit enables the RLOS15 LED This should not be enabled when driving CLKA from the 0 26334 0 26324 If ENRLOS15 LOW the RLOS15 LED is not enabled If ENRLOS15 HIGH RLOS15 LED is enabled and lights when RLOS15 is high Bit 5 CLKE This bit sets the CLKE pin on the 0526334 0526324 This is only active when SPI Bit 0 is HIGH If SPI Bit 0 is low CLKE is always low If CLKE LOW SDO is clocked out on the rising edge of SCLK If CLKE HIGH SDO is clocked out on the falling edge of SCLK Bit 4 SPI SWAP This bit sets the BSWP A5 on the 0526334 0526324 This is only active when SPI Bit 0 is HIGH If SPI SWAP LOW the SPI bus is LSB first If SPI SWAP HIGH the SPI bus is MSB first Bit 3 SPI This bit sets up the FPGA to use serial mode This bit also changes the mode pin on the DS26334 DS26324 If SPI LOW the parallel bus is used for all read write access This also sets the MODE on the DS26334 DS26324 to logic 1 If SPI HIGH the SPI bus is used for all read write access This also sets the MODE pin on the DS26334 DS26324 to logic 0 Bit 2 OE This bit controls the OE pin to the DS26334 Bits 1 and 0 MCLK1 a
15. D12 14 4_ lt 16 1 TNEG LF 14 TNEG334_ lt 16 1 gt 14 1205334_ lt 16 1 gt 06 1 TRING15 B7 RRING334 16 1 gis RTIP334_ lt 16 1 gt 15 RCLK334_DUT lt 16 1 gt 15 F8 RNEG334_DUT lt 16 1 gt 15 RPOS334_DUT lt 16 1 gt 15 RLOS334_ lt 16 1 gt 15 E11 RRING RTIP RCLK RNEG RPOS I RLOS 0526334 PORT TRING TTIP TCLK TNEG TPOS DATA B 15 TRINGS34_ lt 16 1 gt 5 4 16 1 15 TCLK334_ lt 16 1 gt 15 TNEG334_ lt 16 1 gt 2 15 TPOS334_ lt 16 1 gt TRING16 86 RRING334_ lt 16 1 gt 6 4 416 1 15 RCLK334 DUT 16 4d re RNEG334_DUT lt 16 25 J3 RPO5334_DUT lt 16 5 ES RLOS334_ lt 15 1 gt 1518 RRING RTIP RCLK RNEG RPOS I RLOS 0526334 PORT TRING TTIP TCLK TNEG TPOS DRTR 16 TRING334_ lt 16 1 gt 166 TTIP334_ lt 16 1 gt Dil 16 TCLK334_ lt 16 1 gt 16 1 60334_ lt 16 1 gt 05 15 TPOS334_ lt 16 1 gt TITLE DATE DS26334 PORTS 13 16 4 lt 1 4 16 1 TRING334_ lt 16 1 gt TRING334_ lt 16 1 gt TX1475 NA SMT_XFMR RTIP334_ lt 16
16. HI Z 16 of 46 0526334 0526324 Design Kit Register Name BRDAT Register Description BERT RDAT SOURCE Register Offset Bit 7 6 5 4 3 2 1 0 Name 07 06 05 04 03 02 01 DO Bits 7 to 0 D7 to DO These bits control the source of the RDAT for the BERT Note that the 0526334 0526324 must be in single rail mode for BERT to function properly BRDAT DESCRIPTION 0x00 RPOS Port 1 0x01 Port 2 0x02 RPOS Port 3 0x03 RPOS Port 4 0x04 RPOS Port 5 0x05 RPOS Port 6 0x06 RPOS Port 7 0x07 RPOS Port 8 0x08 RPOS Port 9 0x09 RPOS Port 10 RPOS Port 11 OxOB RPOS Port 12 0 0 RPOS Port 13 0 0 RPOS Port 14 OxOE RPOS Port 15 OxOF RPOS Port 16 0x10 1 544MHz On board oscillator 0x11 2 048 On board oscillator 0x12 User clock 0x13 CLKA DS26334 DS26324 0x14 TECLK DS26334 DS26324 0x15 TCLKBERT OUT 0x16 OxFF HI Z 17 of 46 0526334 0526324 Design Kit Register Name TCLK Register Description PORT TCLK SOURCE Register Offset 0x10 Bit 4 7 6 5 4 3 2 1 0 Name 07 06 05 04 03 02 01 DO Note This is an indirect register that is related to ABSP 0x0A See register description Bits 7 to 0 07 to 00 These bits control the source of the port TCLK for the 0526334 052
17. LLB TNEG P6 5 TNEG334_ lt 16 1 gt amp 4 5 4 16 1 D 2 S26334 TRINGO R10 06 RRING334_ lt 16 1 gt 7 ot RS RTIP334_ lt 16 1 gt 7 RCLK334 DUT 16 4 P10 RNEGS3A DUT 16 4 RPOS334_DUT lt 16 1 RLOS334_ lt 16 1 gt 7 84 _ 2 67 R4 RRING RTIP RCLK RNEG RPOS I RLOS 0526334 0 PORT TRING TTIP TCLK TNEG TPOS DRTR 7 TRINGS34_ lt 16 1 gt Ti 4 TITP334_ lt 16 1 gt 10 7 TCLK334_ lt 16 1 gt P TNEG334_ lt 16 1 gt 12 7 TPOS5S334_ lt 16 1 gt TRINGOS8 R11 RRING334_ lt 16 1 gt R13 RTIPS34 16 1 T13 RCLK334_DUT lt 16 l RNEG334_DUT lt 16 RPOS334_DUT lt 16 49 RLOS334_ lt 16 1 gt 8 RRING RTIP RCLK RNEG RPOS I RLOS 0526334 PORT TRING TTIP TCLK TNEG TPOS DRTR TRING334_ lt 16 1 gt T11 ITIP334_ lt 16 1 gt PS ICLK334 16 1 334 4116 1 M11 5334_ 16 1 gt TITLE DATE DS26334 PORTS 5 8 06 8 TRINGOS 15 RRING334_ lt 16 1 gt T15 i 9 115 4 lt 16 1 gt T16 RCLK334_DUT lt 16 19 RNEG334_DUT lt 16 9 RPOS334_DUT lt 16
18. gt 1783 lt 1885 lt TNEG334_ lt 16 1 gt 3B1 gt 385 gt 3C1 gt 5 4B1 485 4 1 4 5 581 585 SC1 gt 5 5 6B5 6 1 gt 5 1986 1505 1988 lt 19C2 19 4 19 6 19 8 1902 1904 1905 19D8 TPOS334_ lt 16 1 gt 3B1 gt 3B5 3C1 gt 5 481 485 4C1 gt 4 5 gt 581 585 5 1 gt 5 5 685 6 1 gt 5 1986 1405 1587 1988 lt 19 2 19 4 19 6 19 8 1902 1904 1906 1908 TRING334 18 TTIP334_ lt 16 TXE_USB USER CLK USER_IN1 USER_IN2 USER_LED1 USER LED2 UDDSYN UDUT_CON USSSSYN WR LOCAL WR_USB XTAL 1 385 gt 301 305 481 gt 485 401 405 581 585 501 505 BB1 685 501 05 7 7 5 701 705 BB1 6BS gt 801 805 981 985 901 305 1081 1085 1001 1005 1 3B5 gt 3 1 gt 3C5 gt 481 485 4 1 gt 4 5 581 585 5 1 5 5 6B1 gt 685 6C1 gt 5 7 1 5 701 705 881 885 801 805 981 985 901 905 1881 1085 1801 1005 14830 1685 lt 11824 14 7 lt 17B3 19B3 lt gt 17A2 lt 17B3 19B3 lt gt 17A2 lt 17B3 17A2 lt 17B3 1782 lt 1706 lt gt 21D4o 22870 1784 lt 12 1 1487 lt gt 19434 2B7 lt 1288 lt 14844 1685 17836 17B2 lt gt TITLE DATE ENGINEER PAGE 14 1 1 35 01 Part Cross Reference for the entire design CONN 14P 19 3
19. 1 gt OO OS RTIP334_ lt 16 RRING334_ lt 16 1 gt e 2 RRINGS34_ lt 16 TTIP334_ lt 16 1 gt 4 16 4 TRING334_ lt 16 1 gt D IRING334 16 1 5 4 lt 1 1 gt RTIP334_ lt 16 1 gt 9 eo RRING334_ lt 16 1 gt RRING334_ lt 16 1 gt TITLE DATE LIU FRONT END PORTS 1 4 43223 814 124 RJ45 APORT 4 lt 1 1 gt ITIP334 186 1 7 J54 3 4 16 1 5 IRING334 18 1 5 TX1475 40 BT XFMR 1557 e 4 lt 1 XFMR e 5 2112334_ lt 16 1 OL 5334 lt 16 amp BRING334 lt 16 1 158 SHT XFMR TX1475 TTIP334_ lt 16 1 gt Te gt ITIP334_ lt 16 TRING334_ lt 16 1 gt 4 16 1 lt 16 1 gt 7 lt 16 1 gt 1 e RRING3S34_ lt 16 1 gt e RRING334
20. ChipView e Perform steps in the Quick Start Hardware Configuration Load ChipView software Select COM port Select Register View e From the Programs menu launch the host application named ChipView exe If the default installation options were used click the Start button on the Windows toolbar and select Programs ChipView ChipView Load the DS26334DK def file e Make sure that all the register settings are correct for the proper function desired for the DS26334DK Refer to the 0526334 and 0526324 data sheets for all questions pertaining to device functionality MEMORY MAP The on board microcontroller is configured to start the user address space at 0x81000000 All offsets given below are relative to the beginning of the user address space Table 6 DS26334DK Relative Address REF DES DEVICE OFFSET General Purpose FPGA U5 Tx Rx Clock Data 0 0000 Switch Mux 04 052174 0x1000 DS26334 DS26324 16 U6 T4 E41 J1 LIUs 052008 device registers can be easily modified using the ChipView exe host based user interface software Table 7 General Purpose FPGA Memory Map OFFSET REGISTER NAME TYPE DESCRIPTION 0x00 BRDID Read Only Board ID 0x02 DSIDH Read Only Dallas Extended ID Upper Nibble 0x03 DSIDM Read Only Dallas Extended ID Middle Nibble 0x04 DSIDL Read Only Dallas Extended ID Lower Nibble 0x0
21. IO22 4 1023 5 TPOS334_ lt 16 1 gt IOS TNUREF IOS 7NUREF 1012 7XIRDY TCLK334_ lt 16 1 gt RCLK334_ lt 16 1 gt FPGA BANK 2 _ NEM SWITCH 5 USBDM 55722 QNN_THRU HOLE HDR TSW 107 14 T D DPDT JTMS MIC i 76 XTIN Q g5 FT245 ONCE_TDO_FLASHINA 60 A T245BM 1 USBDP RSTOUT DATA_ lt 7 gt ALIGN KEY JTMS_MIC JDE_B JTRST B 16 XTOUT Lis 058 RESET 14 058 12 RXF USB EESK Au SIWU_USB EEDATA PWREN 10 058 FEST 188750 2 NT 5 2 15 15 PRT1 OUT 4 L 2 5 PRT1 IN i2 SCI1 IN 9 SCI1_OUT 14 PRT1_OUT CONN_DBSP DATE USB AND JTAG CONN CS2_ BOARD CSO _RAM 118 RESET MIC 128 CLKOUT_MM210 R72 10K R79 888 R37 86 cs3x 81 RESET CLKOUT 93 129 SWII ISHIT T TOIT TOWN
22. Interrupt for 29 CSHU 526334 0526324 INT lt 26334 0526324 27 ALELIU Address Latch Enable 28 FPGAEN FPGA Enable Pin 29 RD Read Signal 30 UIN1 User Input 1 31 WR Write Signal 32 UIN2 User Input 2 33 MODESEL Mode Select 34 36 3 3V Board 3 3V 35 RSTLIU Reset DS26334 DS26324 37 40 GND Ground DS26334 DS26324 Design Kit Telecom Clock and Data Test Points The DS26334DK has high impedance test points for all the telecom signals that are related to the LIU These signals are split up by port number and marked with easy to read silkscreen labels Table 3 shows the telecom connector for port 1 The pinout for this connector is repeated for all 16 ports Table 3 Telecom Connector Pinout PIN NAME FUNCTION 1 TCLK Transmit Clock Input 2 4 6 8 10 12 1 GND Ground 3 Receive Clock Output 5 TPOS Transmit Positive Data Input 7 9 RPOS Receive Positive Data Output TNEG Transmit Negative Data Input 11 RNEG Receive Positive Data Output 13 RLOS Receive Loss of Signal Output Note that the input signals in the telecom connector go from the connector to the on board FPGA then to the 0526334 0526324 The FPGA was designed to perform specific signal routing functions such as looping back RPOS to TPOS on a particular port or transferring data from the on board BERT If you are using user defined data and drive the signal on the connector be sure to
23. Precision Test Points for All Clocks and Signals On Board T1 and E1 Crystal Oscillators for Stable Clock Generation On Board BERT for Testing and Pattern Generation REV 120905 DS26334 DS26324 Design Kit TABLE OF CONTENTS COMPONENT LS e P 3 BOARD FLOORPLAN end MEAM MM MM MEME M PI NEM MM MN 6 BASIL OPERATION aecenas sanaa aaas aae Eiane Rs 7 HARDWARE CONFIGURATION PE 7 QUICK START HARDWARE SETTINGS SINGLE POWER 1 7 a MAR DELE da M PARE ER 7 y chess no JO C 7 IB GR NK 8 ADDRESS DATA BUS setae 8 8 TELECOM CLOCK AND DATA TEST 8 2 14 4 9 Tulle Clor FINOU P HM carats ot 9 DNSSOARDBITERRORHSATE TESTER BERT 9 Table 4 BERT CG npector PINOUT MMC 9 PROSE IGURA TION S acid nA NAAT 10 Figure TAg Dagan mm 10 Figure 3 SFI Conhguratoh WS PROM a 11 Table
24. RRING334_ lt 16 1 gt 12515 4 416 1 12016 RCLK334_DUT lt 16 F12 RNEG334_DUT lt 16 2 F11 RPO5334_DUT lt 16 2 14 RLOS334_ lt 15 1 gt 12 HIS RRING RTIP RCLK RNEG RPOS I RLOS 0526334 PORT TRING TTIP TCLK TNEG TPOS DRTR F15 12 TRING334 16 1 F16 12 TIIP334_ lt 16 1 gt 12 12 TCLK334_ lt 16 1 gt E13 12 TNEG334 16 1 gt C14 12 12 05334_ lt 16 1 gt TITLE DATE DS26334 PORTS 9 12 06 3 TRING13 B12 RRING334_ lt 16 l gt 13816 4 416 1 13 A16 RCLK334_DUT lt 16 1 gt 13 RNEG334_DUT lt 16 1 13 E10 RPOS334_DUT lt 16 1 gt 13 C12 RLOS334_ lt 16 1 gt 513 B10 RRING RTIP RCLK RNEG RPOS RLOS 0526334 0 FORT TRING 812 13 LRING334_ lt 16 1 81213 TTIP334_ lt 16 1 C11 13 TCLK334_ lt 16 1 gt CU TNEG 68 134 TNEG334_ lt 16 1 gt TPos Dara 13 5334_ 16 1 TRING14 11 RRING334_ lt 16 1 gt 14 814 4 416 1 14814 RCLK334 DUT 1G dr4 ES RNEG334_DUT lt 15 4 RPOS334_DUT lt 15 RLOS334_ lt 16 1 gt 14 RRING RTIP RCLK RPOS RLOS 0526334 0 PORT TRING334 lt 16 1 gt 811 14 TTIP334_ lt 16 1
25. gt DALLAS DS26334DK DS26324DK 3 3V 16 Channel E1 T1 J1 Short Long Haul LIU Design Kit www maxim ic com d FEATURES GENERAL DESCRIPTION The DS26334DK DS26324DK is a fully integrated design kit for the DS26334 and DS26324 3 3V 16 channel E1 T1 J1 line interface units LIUs This design kit contains all the necessary circuitry to evaluate the 0526334 0526324 in all modes of operation The design kit also includes an on board microprocessor to run real time code for further part evaluation DESIGN KIT CONTENTS DS26334DK Board with 0526324 0526334 AC DC Adapter 3ft USB Cable Download ChipView Software DS26334DK DS26324DK def Definition File DS26334DK DS26324DK Data Sheet ORDERING INFORMATION PART DESCRIPTION DS26334DK Design Kit Board for 0526334 DS26324DK Design Kit Board for 0526324 Windows is a registered trademark of Microsoft Corp om ten Qe Expedites New Designs by Eliminating First Pass Prototyping Demonstrates Key Functions of the DS26334 DS26324 Includes DS26334 DS26324 x 16 Port LIU Transformers 75Q BNC Connectors RJ 48 Connectors and Termination Passives Communicates Directly with any PC with a USB or RS 232 Serial Interface High Level Windows Based Software Provides Visual Access to All Registers Software Controlled Register Mapped Configuration Switches Facilitate Real Time Clock and Signal Routing
26. tri state the input signal in the FPGA FAILURE TO DO SO COULD CAUSE DAMAGE TO THE FPGA On Board Bit Error Rate Tester BERT The DS26334DK has an on board bit error rate tester BERT to generate and detect errors in either pseudorandom or user defined patterns The BERT on the DS26334DK is the DS2174 A header for the relevant signals related to the BERT is located on the board J22 See Table 4 for the pinout of the BERT connector The BERT signals are routed into the and can be muxed into any of the 16 0526334 0526324 LIU ports under software control For all questions concerning the operation of the on board BERT refer to the device data sheet available online at www maxim ic com telecom If you are using user defined data and driver the signal on the connector be sure to tri state the input signal in the FPGA FAILURE TO DO SO COULD CAUSE DAMAGE TO THE FPGA Table 4 BERT Connector Pinout PIN NAME FUNCTION 1 TCLK EN BERT TCLK Enable 2 4 6 8 10 42 1 GND Ground TCLKIN BERT TCLK Input RCLKIN BERT RCLK Input 3 5 TCLKO BERT TCLK Output 7 9 RCLKEN BERT RCLK Enable 11 TDAT BERT TDAT Output 13 RDAT BERT RDAT Input 9 of 46 0526334 0526324 Design Kit PROM SPI Configuration In software mode it is possible to configure the DS26334 DS26324 using a parallel interface or a serial peripheral interface SPI Most advanced microcontrollers have both a paral
27. 1 4 8 bit FIFO USB UART FTDI 32 pin LOFP FT245BM Motorola U2 1 MCORE Microcontroller 144 pin LQFP MMC2107PV 128k x 8 SRAM Cypress U3 U10 2 32 SO CY62128VL 70SC 4 of 46 0526334 0526324 Design Kit SUPPLIER DESIGNATION QTY DESCRIPTION PART NUMBER UA 1 052174 EBERT Dallas Semiconductor 44 PLCC 0 C to 70 C DS2174Q 05 1 Spartan ll 2 5V FPGA 200k gate Xilinx 256 pin BGA XC2S200 5F G256C 06 1 3 3V 16 channel E1 T1 J1 long haul LIU Dallas Semiconductor 256 pin BGA 0 C to 70 C DS26334 07 1 Dual RS 232 transmitter receiver Dallas Semiconductor 150 mil 16 pin SO DS232AR Fairchild Semiconductor U8 U11 2 High speed buffers NC7SZ86 U9 U20 2 1 5W 3 3V or adj 1A linear regulators Maxim 16 TSSOP EP MAX1793EUE 33 U12 1 for FPGA Xilinx 44 pin XC18V02VQ44C U13 U14 U18 3 Hex inverters 14 SO Toshiba TC74HCO4AFN U15 1 2 5V or adj linear regulator Maxim 8 uMAX SO MAX1792EUA25 Platform flash in system programmable configuration Ue P RM 2Mb 20 pin TSSOP U17 1 Quad 2 gate Toshiba 14 pin SO TC74HCOOAFN U19 1 Switch debouncer Maxim 4 pin SOT143 MAX6816EUS T Pletronics X1 1 6 00MHz low profile crystal LP49 26 6 00M Ecliptek Corp X2 1 8 000 low profile crystal EC1 8 000M Y1 1 Oscillator crystal clock SaRonix 5V 2 048MHz 2 0480
28. 15 0 1017 0 018 0 1019 1020_0 101 102 307 103 104 106 3 197 06 5 T010_3 VREF XC2S_F G256 TO11_3 D4 IO12 1 1013 1 IO15 1 IO17 1 1916 21 IO19 1 IO20 1 102 1 IO2 2NUREF T03_2 D3 04 2 105 2 I06_2 D2 107 2 01 2 10922 IO10 2NUREF 1011_2 1018 2 013 2 00 BUSY 1014 2 1015 2 1015 2 1017 2 018 2 1018 2 1020_2 IO21 2 1022 2 IO23 2 IO24 2 IO13_3 TRDY IO17 3 FPGA_CLKA MCLK_FPGA INT334 DATA_ lt 7 9 014 CFG_DIN_A 15 RXF USB H14 NTFRUP 4 Gl4 RDY334 615 4 TXE_USB MOTEL334 MODESEL 334 RST334 TEA TA 15 N14 M13 L14 L13 N16 M16 RD RCLI TCLKOI TCLKI 5 15 FPGA BANK 1 RPOS334_ lt 16 1 gt RNEG334_ lt 16 1 gt TO2_S VREF GCKO T01_6 TRDY 101 4 I02 6 102 4 1093 5 IO3_4 VREF 104_6 VREF 104_4 105 5 05_4 PLD 107 65 200 5F G25ec I08 6 108 4 5 109 6 109 4 106 4 1 ILI 25 107 4 1010 1019 4 XC25 FG256 1011 6 10114 I012 6 IO12 4 IC13 6 IO13 4 1014 5 1014 4 I015 6 IO15 4 101 5 5 IO16 4 017 6 IO17 4 IC18 6 IO18 4 1019 5 1018 4 1020 5 IO20 4 1021 5 IO21 4 1022 6
29. 16 TITLE DATE LIU FRO END PORTS 5 8 TTIP334_ lt 16 1 gt ga 11129334_ lt 16 1 _ _ 16 1 T3 5 IRING334 16 1 51475 SMT XFM RTIP334_ lt 16 1 gt 4 144 SMT_XFMR NA CONN 1475 5 OHM CONN_BNC_SP 11 RTIP334_ lt 16 1 20 13 J36 Bs SRM E e RRING334_ lt 16 1 TTIP3S34_ lt 16 1 gt 12 TTIP334_ lt 16 1 gt 2 4 TRING334_ lt 16 1 gt 12 4 TRING33A 16 1 e 12 RTIPS34 16 1 12 4 lt 16 3 3 TX1475 SMT XFMR 111 12 RRING334 16 TITLE DATE LIU FRONT END PORTS 9 12 e 12 RRINGS34_ lt 16 125 CONN BNC 75 OHM VERT 004 _ _5 TTIP334_ lt 16 1 gt 15 TTIP334_ lt 16 1 gt T4 TX1475 4 16 1 TRING334_ lt 16 e IBINGS34 186 1 NA SMT_XFMR 158 e 15 RTIP334_ lt 16 1 RTIP334_ lt 16 Ii CONN BNC 75 OHM VERT 004 CONN_BNC_SP o CENE e 13 _ RRING334_ lt 16 1 e is 416 sd 14 4 lt 16 1 gt 16 TTIP334_ lt 16 1 gt 14 TX1475 TRING334_ lt 16 1 gt 15
30. 19 M14 RLOS334_ lt 16 1 gt R14 RRING RTIP RCLK RNEG RPOS RLOS 0526334 0 PORT mis IRING334 16 1 gt 34 416 1 TCLK334_ lt 16 1 gt TNEG L12 TNEG334_ lt 16 1 gt RDATA 111 TPOS334 16 1 TRING10 115 RRING334_ lt 16 1 gt gieP15 4 416 1 18216 RCLK334 DUT 16 14 RNEG334_DUT lt 165 L14 RPOS334_DUT lt 15 RLOS334_ lt 16 1 gt 18 NIS RRING RTIP RCLK RPOS RLOS 0526334_0 PORT TRING334 lt 16 1 gt L16 12 TTIP334_ lt 16 1 K12 10 TCLK334_ lt 16 1 gt TNEG 212 10 TNEG334_ lt 16 1 gt 211 19 334_ 16 1 06 9 11 615 RRING334_ lt 16 1 gt 1 J15 4 416 1 11 J16 RCLK334_DUT lt 16 G13 RNEG334_DUT lt 16 101 F13 RPOS334_DUT lt 16 G12 RLOS334_ lt 16 1 gt 11 K15 RRING RTIP RCLK RNEG RPOS I RLOS 0526334 0 PORT TRING TTIP TCLK TNEG TPOS DATA 515 11 TRINGS34_ lt 16 1 gt 516 11 TTTP334_ lt 16 1 gt F14 11 TCLK334_ lt 16 1 gt 11 TNEG334_ lt 16 1 gt 511 11 6 TPOS334_ lt 16 1 gt TRING12 F15
31. 2128V_2 18C7 052174 1207 XC2S_FG256 1306 1405 1505 DS26334_U 285 3B3 3B 303 307 483 487 403 407 583 587 503 507 583 587 603 507 05232 1587 NCTSZB5 U 1102 MAX1793_U 2107 2128 2 18C3 NC7SZB5 U 1102 XC1BV 2VQ44C 1203 74 04 U 1187 1187 1188 1383 1786 2282 74 04 04 11 11 8 1107 1108 MAX1792_1 XcFS vo28 74 00 74 04 U 815 2 Mexi793 U XTAL_U XTAL osca osca 1785 2282 1188 1188 11C7 1107 11CB TITLE DATE ENGINEER PAGE 1212 0151 25 01
32. 4 US U6 ONCE 5 4 JTMS ON BOARD FLASH MEM uC FOR FPGA FLASH MEM FOR SPI U2 ON BOARD uC Address Data Bus Connector The DS26334DK has a connector J4 to monitor all local bus activity for the design kit All the signals can be captured with a high impedance probe and displayed on an oscilloscope or logic analyzer Note If the FPGA switch SW5 is the OFF position the on board microcontroller will no longer drive any data onto the local bus Therefore the user can now connect the local bus of the 0526334 0526324 into another system without making any modifications to the hardware See Table 2 for specific pin information for connector J4 Table 2 Address Data Connector Pinout PIN NAME FUNCTION PIN NAME FUNCTION 1 A8 Local Address Bit 8 2 DO Local Data Bit 0 3 AT Local Address Bit 7 4 D1 Local Data Bit 1 5 A6 Local Address Bit 6 6 D2 Local Data Bit 2 7 5 Local Address Bit 5 8 D3 Local Data Bit 3 9 A4 Local Address Bit 4 10 D4 Local Data Bit 4 11 A3 Local Address Bit 3 12 D5 Local Data Bit 5 13 A2 Local Address Bit 2 14 D6 Local Data Bit 6 15 1 Address Bit 1 16 07 Local Data Bit 7 17 0 Local Address Bit 0 18 CLKE SPI Clock Edge Select 19 MUX Mux 20 RDY Ready Handshake from LIU 21 CSFPGA Select FPGA 22 OE Output Enable LIU 23 CSBERT Chip Select 052174 24 MOTEL Motorola Intel Select Chip Select
33. 5 19 8 1902 1904 1905 1908 20 20 5 2008 RCLK334_DUT lt 16 1 gt 5 lt 3B8 lt 5 lt 3CB 4B4 488 lt 4 4 lt 4CB 5 4 lt SBB SC4 5 8 4 BB8 5 5 lt 8 2005 2005 20 7 20 7 RCLKENABLE BERT 14A6 lt gt 13884 1286 lt 1207 RCLKIN BERT 1486 lt gt 19AB lt gt 12D7 RCON 1484 1707 lt 1882 lt RDAT_BERT 1486 lt gt 19A8 lt gt 1208 RDY334 14B3 19840 RD_LOCAL 14B7 19A3 lt gt 2C7 lt 12 8 lt RD_USB 1486 lt gt 16C5 gt RESET 16B3 lt gt 17A7 lt RESET_B 13B1 lt gt 17AB lt gt 21 5 21 8 2103 RESET_CFGPRM 1283 lt gt 12 3 RESET_MIC 1786 17C1 lt gt RLOS334_ lt 16 1 gt 1986 4 3 4 484 lt 488 4C4 4CB SA4 lt SAB lt 5 4 lt 5 8 6A4 lt BRB 4 lt BCB 1185 11 5 11CB 19BB8 19 2 19 4 1906 19 8 1902 1904 1906 19D8 RLOS_15 14044 11 5 lt RLOS_16 14D4 lt gt 11B5 RNEG334_ lt 16 1 gt 1985 1504 19 8 lt 19C2 19 4 1966 19 8 1902 1904 1906 1908 2081 2883 2081 2083 RNEG334_DUT lt 16 1 gt 385 lt 5 3CB 4 4 488 lt 4C4 4 8 lt 5 4 lt 588 lt 5 4 lt 5 lt 684 lt 688 5 6 8 2073 2084 2083 RPOS334_ lt 16 1 gt 1986 1507 19BB lt 19 2 18 4 19 5 19 8 1902 1904 1905 1908 28 1 2001 0 RPOS334_DUT lt 16 1 gt 5 3B8 3C5 3CB 4 4 lt 488 lt 4C4 lt 4CB
34. 5 4 lt SBB 5 4 lt SCB 4 5B8 BC5 BCB 2 C3 RRING334 18 1 781 784 7C1 gt 7 5 881 BAS gt 885 381 385 SC5 1081 1485 18 1 18 5 gt 3B4 305 lt 4 4 lt 4884 4044 4084 5 4 lt 588 lt 504 508 4 BB8 4 lt 08 lt RST334 11AS lt gt 14834 1983 2 7 lt 4 15 1 7C1 gt 7 5 881 885 BC5 985 8 9 1 gt 9 5 gt 1081 1885 1 C1 gt 10 5 3B4 3B8 3C4 3CB 484 lt 4C4 4CB 5 4 lt SBB 5 4 5 6B4 lt BB8 6C4 lt RUN_KIT_USR 17B3 18 lt RW 14A4 lt gt 1707 lt gt RXF USB 14B3 lt gt 1685 R_PB_CFG 12A2 lt gt 12B2 gt SCANMODE334 2C3 1105 SCI1_IN 1685 17B4 lt gt SCI1 O0UT 1 4 lt 16AB lt 5 14870 17C1 lt gt SIWU_USB 1404 lt gt 1685 ss 14B7 lt gt 17B1 lt gt TA_CLK 11 1 lt 15C7 TA 14836 17D7 lt gt TCLK334_ lt 16 1 gt 3B1 gt 3B5 3C1 gt 5 4B1 485 4 1 4 5 581 585 5 1 gt 5 5 6B1 gt 6B5 6 1 gt 5 1986 1584 1988 lt 19C2 19 4 19 6 19 8 1902 1904 1906 19D8 TCLKENABLE_BERT 14854 1988 1286 lt 1288 lt TCLKIN BERT 1485 1988 12 8 lt TCLKOUT BERT 1486 lt gt 1988 lt gt 1205 TDRT BERT 1486 lt gt 19AB lt gt 12 5 lt TEA 14836 17D7 lt gt TEST 17C3 lt gt TIM_16H_8L 17D3 lt
35. 5 BRDREV Read Only Board Rev 0x06 ASMREV Read Only Assembly Rev 0x07 FPGAREV Read Only FPGA Firmware Rev 0x08 CTRL1 Control Control Register 1 ABSP Control Address Bank Select Pointer 0x0B BTCLK Control BERT TCLK Input 0 0 BRCLK Control BERT RCLK Input BRDAT Control BERT RDAT Input 0x10 TCLK Control Indirect Register for TCLK Source Control 0x11 TPOS Control Indirect Register for TPOS Source Control 0x12 TNEG Control Indirect Register for TPOS Source Control 12 of 46 0526334 0526324 Design Kit ID REGISTERS BID BOARD ID Offset 0X0000 BID is read only with a value of OxD XBIDH HIGH NIBBLE EXTENDED BOARD ID Offset 0X0002 XBIDH is read only with value of 0x0 XBIDM MIDDLE NIBBLE EXTENDED BOARD ID Offset 0X0003 XBIDM is read only with a value of Ox1 XBIDL LOW NIBBLE EXTENDED BOARD ID Offset 0X0004 XBIDL is read only with a value of 0x6 BREV BOARD REVISION Offset 0X0005 BREV is read only and displays the current fab revision AREV BOARD ASSEMBLY REVISION Offset 0X0006 AREV is read only and displays the current assembly revision PREV FPGA REVISION Offset 0X0007 PREV is read only and displays the current PLD firmware revision CONTROL REGISTERS Register Name CTRL 1 Register Description DS26334DK FPGA CONTROL REGISTER 1 Register Offset 0x08 Bit 7 6 5 4 3 2 1 0 Name ENRLOS16 ENRLOS15 CLKE SPI SWAP SPI OE MCLK1 MCLKO
36. 6324 TCLK DESCRIPTION 0x00 RCLK Port 1 0x01 RCLK Port 2 0x02 RCLK Port 3 0x03 RCLK Port 4 0x04 RCLK Port 5 0x05 RCLK Port 6 0x06 RCLK Port 7 0x07 RCLK Port 8 0x08 RCLK Port 9 0x09 RCLK Port 10 Ox0A RCLK Port 11 OxOB RCLK Port 12 0 0 RCLK Port 13 OxOD RCLK Port 14 OxOE RCLK Port 15 OxOF RCLK Port 16 0x10 1 544MHz On board oscillator 0x11 2 048 On board oscillator 0x12 User clock 0x13 CLKA DS26334 DS26324 0x14 TECLK DS26334 DS26324 0x15 TCLKBERT OUT 0x16 OxFF HI Z 18 of 46 0526334 0526324 Design Kit Register Name TPOS Register Description PORT TPOS SOURCE Register Offset 0x11 Bit 4 7 6 5 4 3 2 1 0 Name 07 06 05 04 03 02 01 DO Note This is an indirect register that is related to ABSP 0x0A See register description Bits 7 to 0 07 to 00 These bits control the source of the port TPOS for the 0526334 0526324 TPOS DESCRIPTION 0x00 RPOS Port 1 0x01 RPOS Port 2 0x02 RPOS Port 3 0x03 RPOS Port 4 0x04 RPOS Port 5 0x05 RPOS Port 6 0x06 RPOS Port 7 0x07 RPOS Port 8 0x08 RPOS Port 9 0x09 RPOS Port 10 RPOS Port 11 OxOB RPOS Port 12 0 0 RPOS Port 13 OxOD RPOS Port 14 OxOE RPOS Port 15 OxOF RPOS Port 16 0x10 1 544MHz On board oscillator 0x11 2 048MHz On boa
37. 7 10uF 20 10V ceramic capacitors 1206 ECJ 3YB1A106M 8 14 C17 C25 16 470pF 41096 100V ceramic capacitors 0603 20 ene C15 1 6 8 310 6 3V ceramic capacitors 1206 7 T C28 C29 C32 Panasonic C109 C410 5 68uF 20 16V tantalum capacitors D case ECS T1CD686R C36 C38 C47 3 22pF 5 25V ceramic capacitors 0603 9 40 2 10pF 5 50V ceramic capacitors 1206 tall case D1 020 2 Green LEDs SMD 02 019 18 Red LEDs SMD 22 21 022 023 3 40V Schottky diodes 21 1 4 4 4 40 Not applicable 0 75 nylon standoff and 0 25 nylon screw 4 40 2 J1 1 DB9 right angle connector short case MM J2 1 Black single right angle Type B AR J3 1 2 5mm connector Switchcraft Power jack right angle PC board mount RAPC712 44 1 40 terminal strip dual row vertical 95 97 J8 28 31 Cambridge J34 J37 J40 J43 19 5 pin 750 BNC connectors vertical CENCHO J J49 J52 J6 J9 J25 18 14 pin headers dual row vertical Es J26 J27 J32 J33 Samtec 138 J39 447 448 8 2 pin headers 0 100in centers vertical TSW 102 07 T S 444 45 J46 3 100 mil 3 position jumpers Nd cepe Molex J53 J54 2 8 pin 4 port RJ45 jacks right angle 43223 8140 L1 1 1 0uH 320 2 SMT inductor BUE R1 R20 R61 R90 5 Resistors 0603 2 R138 DO NOT POPULATE 3 of 46 DS26334 DS26324 Design Kit DESIGNATION QTY
38. DESCRIPTION SUPPLIER PART NUMBER R2 R23 R37 R38 R39 R42 R45 47 50 R52 R53 R55 R57 R60 R66 R69 R71 R72 R74 R76 R79 R80 38 10 5 1 16W resistors 0603 Panasonic ERJ 3GEYJ103V R3 R19 R21 R22 R24 R36 R41 R44 R46 R51 R63 R64 R65 R81 R82 R102 Panasonic R109 R116 R120 60 330 5 1 16W resistors 0603 4 R121 R122 R126 ERJ 3GEYJ330V R130 R131 R132 R134 R137 R139 R140 R148 R151 R153 R40 R70 R73 R77 R78 R83 R84 R86 R87 R92 R93 R95 20 3300 5 1 16W resistors 0603 ERJ 3GEYJ331V R98 R100 R101 R106 R107 R108 Panasonic R43 R62 2 15 5 1 16W resistors 0603 ERJ 3GEYJ153V Resistor 1206 nee 1 DO NOT POPULATE R56 1 4700 5 1 16W resistor 0603 ERJ 3GEYJ471V 5 Panasonic R94 1 510 5 1 16W resistor 0603 ERJ 3GEYJ510V R111 R115 R117 R118 R119 R123 R124 R125 R127 Banasohie R128 R129 R133 32 60 40 1 1 16W resistors 0603 R141 R144 R146 ERJJEKFGORAY R147 R149 R150 R152 R154 R161 Panasonic R145 1 22 5 1 16W resistor 0603 ERJ 3GEYJ223V es Panasonic 5 1 SW2 SW6 3 4 pin single pole switch 4 SW3 SW4 SW5 em Tyco Electronics SW7 4 6 pin slide switches DPDT through hole SSA22 T1 T4 4 32 pin transmit receive SMT transformers Pulse Engineering 1 2 and 1 1 1475 U
39. DSO BI OSIW ISONW 144 MMC2107PU 14 U2 2107 CONTROL IIX IB H9T WIL CNT 84351 cust 41351 _ USER 16 1 USER IN1 1 USER IN2 1 ON BOARD MICRO 000000 DS26334DK PAGE TEST TXDL RXD1 53 1 2 55 58 11 66 TXD2 58 RXD2 TEST 63 59 72 I2 SCI1 O0UT SCI1 IN 2 CLKOUT GND OSC_MCU USSSSYN 23 3 4 7 7 S gt z Y zl 9 TSSN 2557 ESSN Edaao PSSA vado 5550 5007 8557 45501 4 550 8007 NASSSn Nasaan 1550 RESET_MIC VSSA 3 _ IC2107PV ed I3 l4 MM MMC2107 HSU 14 va Agisn 5 1 6a era 144 15 29 12 PD28 PD26 UST ULUGOHOIAW MICROADD_ lt 17 gt ENABLE MICRO 148 SWITCH NA SSA22 SWS DPDT fos 1 1
40. EG334_ lt 16 RNEG334_ lt 16 RNEG334_ lt 16 4 RNEG334_ lt 16 05334 lt 1 05334 lt 1 05334 416 05334 416 TCLK334 16 RCLK334 16 TPOS334_ lt 16 RPOS334_ lt 16 TNEG334_ lt 16 RNEG334 16 RLOS334 16 TCLK334_ lt 16 RCLK334_ lt 16 TPOS334_ lt 16 RPOS334_ lt 16 TNEG334_ lt 16 RNEG334_ lt 16 RLOS334_ lt 16 mi 5 11334 9 USFR_IN2 a 0 uv Mo 18 MUX CLKE334 19 22 28 RDY334 21 22 22 4 28 FPGR EN 30 USFR_IN1 m w 2 mde 8 TSW 120 07 T D THROUGH HOLE 31 32 33 33 34 34 RST334 35 55 3s 36 IT 18 27 28 25 5 25 __26 17 27 TCLKENABLE_BERT1 TCLKIN_BERT TCLKOUT BERT 5 7 ADDRESS_LOCAL_ lt 8 0 RCLKENABLE_BERTS TDAT BERT 11 RDAT_BERT CLKE33419 CSEPGA 21 CS_BERT 23 5 gt 4 24 MOTEL 334 CS334 ALE334 RD_LOCAI WR_LOCAL MODESEL 334 BERT TEST POINTS CO TITLE DATE TEST POINTS 77 gt vEESOdH lt 1 891 gt vEEOJNH LIU SERIES TERMINATION ENGINEER DS26334DK PAGE 28
41. Isb msb Isb msb WRITE ACCESS ENABLED SDO Figure shows a simplified diagram of the XC18V00 device and the 0526334 0526324 in SPI serial mode Notice a few key points about this diagram First the CLK for the XC18V00 is the MCLK for the LIU but this is not the SCLK for the SPI interface The SCLK can be programmed as needed See Table 5 for an example of the memory map Second the programming for this device begins when OE on the 18 00 goes high Therefore consideration must be taken if some delay is necessary Generally it is sufficient for the OE pin to be connected to some power up delay device The OE delay is not necessary on this DK 10 of 46 DS26334 DS26324 Design Kit Figure 3 SPI Configuration with PROM XC18V00 CFG SCLK PROM DS26334 SDI 0526324 Table 5 Configuration Memory 0x00 1 0 0 Start of Write Cycle 0x01 0 0 0 Bit AO 0x02 0 1 0 Always a 0 for a write 2 2 oor 0 2 2 2 2 0 2 5 2 Bit DO LSB s gto a a T ane T 2 T T et eje 2 5 2 End of Write Cycle 11 of 46 0526334 0526324 Design Kit SOFTWARE CONFIGURATION Quick Start Software
42. NG334_ lt 16 1 gt 4 4 416 1 g4 RCLK334_DUT lt 16 1254 KS RNEG334_DUT lt 16 1 gt 4 RPOS334_DUT lt 16 1 gt 4 14 RLOS334_ lt 16 1 gt RRING RTIP RCLK RNEG RPOS I RLOS 0526334 PORT TRING TTIP TCLK TNEG TPOS DRTR La 4 TRING3S34_ lt 16 1 gt 11 4 9 16 1 HS 4 4 lt 16 1 gt 518 4 334 16 1 4 S 1205334_ lt 16 1 gt TITLE DATE DS26334 PORTS 1 4 1 TRING S RS U6 RRING334_ lt 16 1 gt 5 4 lt 16 1 gt 5 RCLK334_DUT lt 16 J19 RNEG334_DUT lt 16 d RPOS334_DUT lt 16 19 RLOS334_ lt 16 1 gt 5 RRING RTIP RCLK RNEG RPOS RLOS DS26334 U FOBT RS 5 4 416 1 TRING 25 TRIP 15 5 IIIP334 16 1 sg TCLK334_ lt 16 1 gt TNEG M6 s TNEG334_ lt 16 1 gt RDATA 19 s5 4 TPOS334 16 1 TRINGOG6 RRING334_ lt 16 1 gt 6 R3 RTIP334_ lt 16 1 gt 6 RCLK334 DUT 1G de RNEG334 DUT 16 gde RPOS334_DUT lt 16 Je RLOS334_ lt 16 1 gt 6 T2 RRING RTIP RCLK RPOS RLOS 0526334 0 POR TRING 85 4 lt 1 1 gt 16 TTIP334_ lt 15 1 gt 18 TCLK334_ lt 16 1 gt
43. P14 UCCINTL 5 ES uccINTs E12 UCCINT7 MS M12 UCCINT12 14 o 1 JTMS LINX JFLASHOUT_FPGAIN OK 25200 5F G256C JTCLK UCCO3 SERIAL CFG FLASH FOR FPGA 4 X X 3 5 JFPGROUT DSS34IN US XC2S FG256 PROGRAM 215 PROGRAM_FPGA_A 815 CCLK_A CONTROL pone R14 DONE_FPGA_A 1 11 P2 ___ CCLK R Ml vccoi2 R3 CEx 18 DONE_FPGA_A ONCE_TDQ_ELASHIN 4 13 Ucccia4 Re JIMS s OE RESETx 8 RESET_B 15 crx _7 PROGRAM FPGA 6 UCCC16 17 JFLASHOUT F PGA 5 020 12850 U13 2188 DONE_FPGA_A 8 1 TITLE DATE FPGA CONTROL FLASH CFG pons eee DS26334DK USER_CLK ADDRESS_LOCAL_ lt 8 gt CLKOUT TPOS334_ lt 16 1 gt SB USB 210 101 1 5 IOA 1NUREF 13 5 7 I02_1 WRITEX GCK3 101 0 102 103 0 104 0 105 0 06 0 MICRORDD 17 0 MOSI MISO 55 SCK FPGA_EN ALE3S34 CSFPGA CS334 CS_BERT RD LOCAL WR LOCAL IO7_ VREF 108 0 9 010 0 10118 1012 0 1013_0 1014 0 1015 0 10
44. gt JDS3340UT SPI PROM IN 128826 1203 lt JFLASHOUT FPGRIN 1381 gt 13C3 JFPGROUT DS83341N 13 3 2B7 lt JTCLK 1203 16C3 lt gt 17B2 lt gt 2B7 lt 13B3 13C3 16B2 lt JTDI 1BC3 17D2 lt gt JTDO 1203 15 4 lt 1281 JTMS 1BC3 2 7 1203 13B3 13C3 16B1 lt JTMS MIC 18B2 16 4 17B2 lt gt JTRST B 1BB2 17B2 287 lt LED_RLOS15 11AB lt gt 11B4 gt LED_RLOS16 11AB lt gt 1184 MCLK334 2C3 11 4 lt 12 3 MCLK_FPGA 14C3 11 3 MICRORDD 17 0 1487 1784 1884 1888 MICRODATA_ lt 15 gt 1485 1788 1802 1805 MISO 14B7 lt gt 1782 MODESEL334 14B3 1983 MOSI 14B7 1782 MOTEL334 14B3 19B3 2C7 lt MUX_CLKE334 14B3 19A4 lt gt 19B4 2 7 lt 14844 1707 lt 18D3 18D7 OE334 14B3 19B3 287 lt ONCE TDO FLASHIN 16C4 lt gt 17D2 lt gt 13B3 OSC MCU 17B2 17B4 lt gt PD16 17B8 18B3 PD17 17BB 18B3 8 17BB 18A4 lt PD19 17B8 lt gt 18A2 lt PD2 1788 lt gt PD21 17CB lt gt 18B2 PD22 17CB 18B2 PD23 17CB lt gt 18B2 PD24 17 8 PD25 17CB lt gt PD26 17 8 PD27 PD28 17CB lt gt PD29 17 8 17CB lt gt PD31 17 8 PROGRAM_FPGA_A 1381 13B3 16AB lt gt 16AB lt PRT1 OUT 1686 lt gt 1585 PWREN USB 14D4 lt gt 1685 RCLK334_ lt 16 1 gt 1986 1585 1988 lt 19C2 19C4 19
45. lel interface and SPI interface such as the microcontroller on the DS26334DK The command you send to the microcontroller through either the USB or serial port determines if that data is placed on the parallel or SPI bus Refer to the data sheet for ChipView on the particular commands required to switch data ports A unique feature with the SPI port is that a PROM can be used to provide the LIU with the specific data needed for configuration If the data in the PROM is formatted a certain way it can seem as the PROM is acting like a controller with a SPI interface in master mode The most common PROMS to use for this type of application are those with an internal address accumulator This feature for the PROM is important because the device must automatically jump to the next available address in the configuration memory The Xilinx 18 00 device family is a byte wide nonvolatile memory with an autoincrement address function The family of devices is available in 1Mb 2Mb and 4Mb densities The PROM is also useful because the device can perform in circuit programming with the JTAG port Refer the data sheet for the XC18V00 for the JTAG codes for programming the configuration memory Figure 2 shows a general relationship of the timing for a SPI bus For this case all data is clocked into the slave device on the rising edge of SCLK This feature can be configurable on the 0526334 0526324 Figure 2 SPI Timing Diagram b adrs
46. nd MCLKO These bits control the MCLK pin to the 0526334 0526324 MCLK1 MCLKO DESCRIPTION OF MCLK 0 0 MCLK high impedance mode 0 1 MCLK on board T1 oscillator 1 0 MCLK on board 1 oscillator 1 1 MCLK user clock input 13 of 46 0526334 0526324 Design Kit Register Name ABSP Register Description ADDRESS BANK SWAP POINTER Register Offset 0 0 Bit 7 6 5 4 3 2 1 0 Name 07 06 05 04 03 02 01 DO Bits 7 to 0 07 to 00 These bits control the address bank for address 0x10 TCLK 0x11 TPOS and 0x12 TNEG ABSP DESCRIPTION 0x00 Bank Address Value for Port 1 0x01 Bank Address Value for Port 2 0x02 Bank Address Value for Port 3 0x03 Bank Address Value for Port 4 0x04 Bank Address Value for Port 5 0x05 Bank Address Value for Port 6 0x06 Bank Address Value for Port 7 0x07 Bank Address Value for Port 8 0x08 Bank Address Value for Port 9 0x09 Bank Address Value for Port 10 Bank Address Value for Port 11 0x0B Bank Address Value for Port 12 0 0 Bank Address Value for Port 13 0x0D Bank Address Value for Port 14 OxOE Bank Address Value for Port 15 OxOF Bank Address Value for Port 16 14 of 46 0526334 0526324 Design Kit Register Name BTCLK Register Description BERT TCLK SOURCE Register Offset 0 0 Bit 7 6 5 4 3 2 1 0 Name 07 06 05 04 03 02 01 DO
47. rd oscillator 0x12 User clock 0x13 CLKA DS26334 DS26324 0x14 TECLK DS26334 DS26324 0x15 TDATBERT OUT 0 16 HI Z 19 46 0526334 0526324 Design Kit Register Name TNEG Register Description PORT TNEG SOURCE Register Offset 0x12 Bit 7 6 5 4 3 2 1 0 Name 07 06 05 04 03 02 01 DO Note This is an indirect register that is related to ABSP 0x0A See register description Bits 7 to 0 D7 to DO These bits control the source of the port TNEG for the DS26334 DS26324 TNEG DESCRIPTION 0x00 RNEG Port 1 0x01 2 0 02 Port 3 0x03 RNEG Port 4 0x04 RNEG Port 5 0x05 RNEG Port 6 0x06 RNEG Port 7 0x07 8 0 08 Port 9 0x09 RNEG Port 10 11 OxOB RNEG Port 12 0 0 13 OxOD RNEG Port 14 OxOE RNEG Port 15 OxOF RNEG Port 16 0x10 1 544MHz On board oscillator 0 11 2 048MHz oscillator 0x12 User clock 0x13 CLKA DS26334 DS26324 0x14 TECLK DS26334 DS26324 0x15 Drive Logic 0 0x16 OxFF HI Z 20 of 46 0526334 0526324 Design Kit DS26334 INFORMATION For more information about the DS26334 refer to the DS26334 data sheet available on our website at www maxim ic com DS26334 DS26324 INFORMATION For more information about the 0526324 refer to the 0526324 data sheet available on our
48. serial port connect an RS 232 serial cable from DS26334DK J1 to the PC If using the USB port connect a USB cable from DS26334DK J2 to the PC Connect AC DC adapter with AC power source and the DS26334DK J3 PWR LED should be JTAG Configuration The JTAG chain is controlled by the connector JTAG CON J6 and two on board switches FLASH SW3 and ONCE JTAG SW4 Depending on the function such as programming the internal microcontroller flash or performing boundary scan operations the JTAG CON connector can be used and the switches can be configured to accomplish the desired task For information on programming the internal flash of the on board microcontroller refer to the MMC2107 microcontroller user manual and board schematic For most purposes having the complete JTAG chain is sufficient Figure 1 shows the complete chain as well as what order the devices appear during boundary scan Table 1 shows the pinout of the JTAG connector Connect any JTAG cable to the connector to perform all operations Note the JTAG chain changes depending on the switch SWA The ONCE location of SW4 is used for programming the on board microcontroller only Table 1 JTAG Connector J6 Pinout PIN NAME 1 JTDI 2 4 6 7 GND 3 JTDO 5 JTCLK 8 ALIGN KEY 9 BRD RST 10 JTMS 11 BRD V3 3 12 JDE 13 N C 14 JTRST 7 of 46 DS26334 DS26324 Design Kit Figure 1 05263340 JTAG Chain SW
49. website at www maxim ic com DS26324 DS26334DK DS26324DK INFORMATION For more information about the DS26334DK DS26324DK including software downloads go to www maxim ic com DS26334DK TECHNICAL SUPPORT For additional technical support go to www maxim ic com support ERRATA On page 18 of the schematic EBO and EB1 were swapped in the design on U3 and U10 respectively These changes have been made to the board using jumper wires SCHEMATICS The DS26334DK DS26324DK schematics are featured in the following 25 pages 21 of 46 Maxim Dallas Semiconductor cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Dallas Semiconductor product No circuit patent licenses are implied Maxim Dallas Semiconductor reserves the right to change the circuitry and specifications without notice at any time Maxim Integrated Products 120 San Gabriel Drive Sunnyvale CA 94086 408 737 7600 2005 Maxim Integrated Products e Printed USA The Maxim logo is a registered trademark of Maxim Integrated Products Inc The Dallas logo is a registered trademark of Dallas Semiconductor Corporation DS2 DS2 DS2 052 052 ON 42 ER PAG 6334 CONTROL 6334 PORTS 1 4 6334 PORTS 6334 PORTS 6334 PORTS COPS LIU FRON END PORTS 9 12 LIU FRON
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