TB-A7-200T-IMG Hardware User Manual
Contents
1. aes Bias network 10kohm U24 populated Ooh Oohm CLKOp ANN M ANN B35 IO MRCC pin P5 Oohm Oohm CLKOn B35 IO MRCC pin 4 Source 1 Differential 515338 Termination S Termination network 100ohm CLK1p 200ohm I li Wet not populated CLK1n not populated uic CLK2p CLK2n CLK3p CLK3n FPGA MMCX SP Bias network Connectors m 155 jos Jo am B35 IO MRCC pin R6 J21 BM t Differential B35 IO MRCC pin R5 AC coupling I ee 100nF 22 Termination 100 1 L Z Figure 7 11 User Clocks 1 The CLKO output of the onboard Si5338 is connected to a global clock input of the FPGA The default hardware configuration supports a single ended 3V3 CMOS clock Note If required the user may configure the Si5338 to drive a differential clock input however soldering is required Any soldering voids the warranty Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 2 Apair of MMCX receptacles are designed to be driven by an external differential clock source As per the diagram the MMCX inputs are provisioned with ESD protection and are AC coupled Following the AC coupling capacitors the signals are re biased and terminated by 100 ohms as required by the FPGA due to VCCO 3 3V on that bank Note If required the user may drive a single ended clock into the MMCX conn2. 1 2 _ 49 The PHY has 25MHz crystal oscillator from which it derives all its line interface timing The RX CLK and TX CLK signals on the MRCC FPGA pins can operate at up to 125MHz for Gigabit line rate supporting DDR transfer rates of 250Mb s per pin on each of the four RGMII pins in each direction The user is cautioned about relying on these clocks for unrelated circuitry in the FPGA as the frequency is line rate dependent and RX CLK can exhibit disturbances as the line status changes The 88E1116R PHY device provides some reset time configuration options selected by shunt clips on several 1x3 headers as follows shorted pin pairs indicated Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Note Only two shunt clips must be used at a time one for either J11 or J12 and the other for either J13 or J14 N A Not Allowed Incorrect operation can result in permanent damage to the board Table 7 9 Ethernet PHY reset Configuration Selection Header Header Header Header J11 J12 J13 J14 PHY configuration function Disable Auto crossover PHY SMBus address A4 0 Enable Auto crossover PHY SMBus address A4 1 Note PHY SMBus address bits 3 0 are fixed on the PCB at b0111 Ethernet line connection is provided through a Halo HFJ11 1G01ERL shielded integrated magnetics 8P8C modular jack that contains 4 lane isolating transformers
3. TB A7 200T IMG Hardware User Manual Rev 2 04 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 1 inreviun Revision History 2 01 2015 09 30 Updated following review Morita Odajima 2 02 2015 09 30 Updated with additional dimensions on top dimension ST HN RF es ot ee 2 03 2015 10 1 Updated with additional dimensions on bottom dimension ST Fe RN 2 04 2015 10 9 Updated with additional dimensions on bottom dimension Morita drawing Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 2 Table of Contents Pre VISION mio A EE EE 2 Introduction and Product Safety cccccecccccccesecceceeeceeeeeeeeeeeeeeeeeseeeeeeeseeeeeeeseeeeeesseeeeeesseeeeessaeeseeseas 6 1 Related Documents and Accessories 9 Eo PH 10 S TO I 6 M 11 A WSOC ERR 12 External View Of ING 13 E 15 7 Description 18 PVs y Ay uu esta 18 7 1 1 Power TAU COMMEG O u 19 7 1 2 Input Power Protection Circuit
4. a 19 7 1 3 Board Power Switch 20 7 1 4 Power Supply Architecture sararan E 20 7 1 5 CUS ING NG NE EE RETE 21 7 1 6 Voltage Rails Test Points 21 7 1 7 Power and Miscellaneous 8 21 7 1 8 FMC VADJ Voltage Selecto a i bada 22 2 bPOABahksASSIgDITIe DIS 24 l SVS IE ee 25 7 3 1 Main System Clock 25 EMIL Oe ARIOGCIOCKO u 26 7 4 1 mulescundenmcm P 27 7 4 2 Yser CIOCR e 28 7 4 3 DORS m 29 75 5 PMC Connector IAC aCe Pase Pose attin e bna 29 Z5 PMG HPC 1 J19 IO Allocation iiia nag a idu 31 7 5 2 FMC HPC 2 J19 IO Allocation u u 36 76 DDR3 SDRAM SODIMM secca dcdit ados use 42 Ils tReet jO 1000 Mea EE 46 7 8 USB to UART 47 AO OPO u een PET 49 7 10 Quad x4 SPI Flash and FPGA 50 AiL d
5. HP jal HB8N 22 HROP GND 3 j HP 4 _ GND Ho N 25 HOP GND _ 26 HN j HOP 27 4 GND 28 HB8P 1 GND 9 mon HB13P GND 8 GD Jj GND 139 GD 4 a GND t1 VREAMC GND 4 j GD _ 5 CLKOMCN ignoLiip AF29 laoo P 6 GND 1 j GD BAN LASP 9 GND GD jn LAN __ j GD 14 PP GND LAMN GND 1 5 BENE NENNEN Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun PIN FMC PIN NAME PIN 12 IOLO2N AJ34 LA20 N 22 LA19 P AJ31 12 10LO7P p oN LA22 o aan lt NENNEN rouse me ep _ 1 29 31 LA28P S 2 _ 94 AP33 moue _ ew O GOD GND 8 LAN J VAD 89 GND O GND 4 Jw VA _ i 1 vREBMC pp _ NENNEN NE GND L Wws P HA3N 26 12 OL2iN
6. Jeouenbes J MOd juejiq e oejde2ey gv 0oJol A INDY 50149 seiddng sal ddng 1ewog 9 0 s qeud SINdjNO JOMOd JIdd S xow EE FUN SV L ndu Jesn E aper noses 1 sues WEL uey 1490 99S1 19442 L00ZVZ9X iene qWOSZ I ii NU IM 2 E r S ll a XEN S LIN 008 ss oov o E O 12 9 WWIGOS euoq T ou m as nS ane ae se l4Vn orasn IN9 0LrcdO plaius IWS E gy OJol N LINI VOd4 LIA S AO pi JepeeH H su s Yoel ie m INMd N 5 3 A O dnos6 ca epis god uo JojoAuoo OWS EAE LL SOUIIMS esoding je eues HABA sjey Jeouenbes E sepis pue do gag uo jejeued ml cJ Sseydiq ZHI OEP BAL te esoding je1euec p ee INVH8SOOA LNIOON OAL eee siey sepis pue do gag uo jejejed _ ulejs S 84341 esoding eJeuec e e qH AS Acl NOWA TRHSABOS JOPSUUND OWA JOPSUUOD OWA FAVA LOWS CAYA Lol Z olda 01 L olaa jeduin 8 TLL OO VH 01 1 cz oolvH 01 1 _ _ J oJJUoO 194 d AG 10 Ag L
7. esses nnne 19 Figure 7 4 Board Power SWIIKuu u l inea ente eres he EUR UE icc tu Raton taco di au CU 20 Figure 7 5 VADJ Voltage Selection Header shunt Positions 23 Figure 7 6 XC7A200T FFG1156 Bank 5 24 Figure 7 7 TB A7 200T IMG User Bank Function Assignments 24 Figure 7 8 Main Clock 25 Figure 7 9 FMC HR IO Clock Assignments 27 Figure 7 10 GTP Clock Assignments 28 FOUS FV MS GIO R Scun 28 Figure 7 12 VITA 7 1 PMG HPO EPG Pin Gl 30 Figure 7 13 DDR3 SDRAM SODIMM 42 Figure 7 14 USB UART 47 cC Sere nama ene ee eee 49 Figure 7 16 FPGA SPI Flash Configuration Structure 50 Figure 7 17 Pmod Connections cccccccccceceeeseeeeceeeeeeeaeeseeeeeeeeeeeeeeeeeeeeeeesssaeaseeeeeeessssaaaaeeeeeeeeesaaas 53 Figure 7 18 SPDIF Digital Audio Interface 57 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 4 inreviunW List of Tables Table Wel FCC CSS Oe NETTE TTE TES 9 Table 7 1 V
8. I 5 5 L LI L Hd Hen SS 3 1 M s wee Hn r d pee M 1 Uu 4k T 1 1 D DTE et 4 d TX 1 ee H i H rm ue HET t E LU ein 1 7 f of uH re T 9 09 j s a ie n I ee a i LI T JM mem ee L av Cl 441 ee B 0 b k 1 br Ho z m t 1 B y4 t mac LI r Tu Im TT mU 1 P s JEN gt te n lt 1 rr y x m gt EM i san F a LT HU ow jam TIEF ai DC Input Artix 200T FMC VADJ 12V FPGA Config Figure 5 1 TB A7 200T IMG Board Top View Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 13 TB A7 200T IMG Hardware User Manual The TB A7 200T IMG board s bottom side components are shown in Figure 5 2 HPC FMC1 Connector HPC FMC2 Connector General Purpose Tact Switches General Purpose DIP Switches FPGA Program Switch Rev 2 04 IPAE Mp XILINX ARTIX Figure 5 2 TB A7 200T IMG Board Bottom View TOKYO ELECTRON DEVICE LIMITED POWER OFf 14 inreviun 6 Board Specifications External Dimensions Number of Layers Board Thickness Material FPGA Included Connectors FMC HPC CC Connector
9. A o lqejo j s jeduunf ZONA pue LOWS CAYA dems 10H i Aci yoer pueg 12 TOKYO ELECTRON DEVICE LIMITED Rev 2 04 TB A7 200T IMG Hardware User Manual 5 External View of the Board The TB A7 200T IMG board s top side components are shown in Figure 5 1 JTAG 800MT S 64 bit DDR3 Connector SODIMM slot 006 ee o 7 m i EL bel ae B I p P rt incen 2271 T Me d B j e Tt ad O HT y r ry T S PDIF in out LIII Ba TV p ES JT Gigabit BE PT M i T LA 4 orba a 45 4 lt muu O Peleo ct ERU EE SS aa 1 s a RAS thernet E zu H URL 774 IF gt ad wort ee I at 0002 005 d bota USB UART ET i Jue E E a On ar tener ae vas 9 18 AT DOT ING 2 t DL REV an m TTTTTYT Sere ee ee me s s ss sss ee p o Moore HERR General TT TE un MN PN i E pugno Purpose bbs mura Tact Switches FPGA Program Switch Power d 4 5 4 h gt yy s i gt s 1 LII z TI TM s t l J _ 4 L 1 i 1 e
10. G25 LA25N 28 127 16 10009 NN m er wow 16 IOLOBP H26 16noLosn G26 1 29 31 LAP H27 1610007 ww L gwo ej woon 1ellOLI7P H31 _ P e 16IOLt7ZN G31 34 Las0P H32 teloLtP ww LEBER 8 E tassp J31 LA33 37 LA32P 129 16 0018 _ b Jaf LA32N 13 ionan ____ VD 3 GND _ j d wawan a Hae E E 2 GND j GND _ GN 4 Gv 5 Jel w GND 8 HAO2N T34 9 j HAHP 1121 GD GND 14 HATON 134 _ po HMA4P GND Haan 16 HAZPCC ev Jt HAZNOCC _ ee GND ss HM8N li HAMP GND HN j GD He2N 22 ew a j aP GND HN HPC J ev Ja monce GND sss HN 28 HB6PCC o S Hoe reco HBiP j 3 GND Rev 2 04 TOKYO ELECTRON DEVICE LIMITED m inreviun BANK IO 4 PIN
11. HP 4 25 HBOPCO E HBONCC ss GND NENNEN HP 27 4 GND epo GND _ 29 HBeNCC 1 _____ 5 CLK2 BIDIRN woo Jel V32 7 HA2P Loue 9 GNO sss Los aca haor N 10 ft ee nen 4 AC28 HAHP 12 GND 1 l HAN moe apes 5 ss Dese m _ ke nais con maip _12 20 26 HA22P 21 BEEN K26 AM26 AN26 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED m inreviun PIN FMC PIN NAME PIN BANK IO 11_ 30 GND BN HOP po j GND 82 BION y HBP 3 GND HBBN 4 HBP S o GD 135 HN HBHP GND Jj HBB8N 37 HBIZPCC GD 3 HBIZNCO VOBMC 39 po GD Note CLK DIR PRSNT PG are all inverted before application to FPGA 7 5 2 FMC HPC 2 J19 IO Allocation This FMC connects all 34 LAxx differential pairs and 12 HAxx differential pairs to banks on the FPGA ports are not connected Eight high speed DP lanes provisioned with GTP pairs TX a
12. MINAS 2 19 11 14 RVR FFLT NLS c BZX84C10 LT Rv m eu 4 DNS DIODE ZENER 10V 350MW SOT23 3 c Peu eE cx ZENER 1DV 350MW SOT23 3 FLT N LATCH 17 T PAD GND 4 V TIMER 5 4 wan C499 O 1uF TPS24T20RG e IC POS HOT WAP CTRLR FAST 18v 16QFN 280 A A0 Figure 7 3 Input Power Protection Circuit The main 12V rail smoothly rises from OV on either switch ON or hot plug in power switch is the recommended method requiring approximately 10msec with two maximum capacitance FMC modules installed on the board The Controller s Under Voltage detection ensures that the input voltage exceeds 9 8V before enabling and shuts down on input over voltages exceeding 14 2V Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 1 3 Board Power Switch The TB A7 200T IMG also features a system power ON OFF control that allows the use of a low current low voltage SPST switch on the board or a remote panel or enclosure mounted switch using the optional header J25 to the right of the switch in the photo below The slide style switch is shown in the OFF position The actuator of the switch extends approximately 1 5mm off the edge of the PCB Figure 7 4 Board Power Switch 7 1 4 Power Supply Architecture The TB A7 200T IMG power system consists of eleven high efficiency switching buck regulators and three linear LDO regulators All regulators except the DDR3 VTT source si
13. 12 we NOTE 5V IO devices are not supported To avoid possible damage do not connect peripherals with 5V IO levels to the Pmod IO receptacles 7 13 General Purpose User LEDs The TB A7 200T IMG has two rows of four user programmable LEDs one row on each PCB side Each LED in a row is parallel connected with a corresponding LED in the row on the other side of the PCB hence there are 4 control signals used for all 8 LEDs All eight LEDs are Green color and the FPGA lOs drive active high logic high to turn on the LED and a logic low to turn it off The user must ensure the FPGA configuration load contains definite IO states to the four LED signals as they must not be left floating after configuration is completed The following table details the FPGA IO assignment for driving the two LED groups Note that they do not all originate from a single FPGA bank Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 17 User LEDs Pin Assignment LED RefDes top bottom Signal Name FPGA Bank IO function D11 D38 GRN LED 1 B14 10 4 004 D13 D39 GRN LED 2 B14_IO L4_N TO D05 a D14 D40 GRN_LED 3 B15 10 25 D15 D41 GRN_LED 4 B16 10 25 With PUDC FPGA Bank 14 W26 pulled low the LEDs all activate on power up during FPGA configuration as the LED control signal IOs are pulled high internally Note that this will not be the case if the optional PCB stuffing of PUDC_N R84 in R85 out pulls t
14. gt gt gt n n n n Bank 35 ON O ESD 80000 Protection 9 2 B 1 PMOD2 0 7 eer QOOOQOO 7 a9na amp aaa8 gt gt gt n n n n Figure 7 17 Pmod Connections Since the connector IO pins drive straight from FPGA IOs protective TVS diode clamping blocks are attached to each group of signals to counter any ESD or surge injection into the connector pins The following tables detail the mapping of the two Pmod IO connector pins to FPGA IO pins There is no series resistance present in the signal lines and the full output drive capability of the FPGA IOs is available Refer to Xilinx document DS181 Artix 7 FPGAs Data Sheet DC and AC Switching Characteristics for the IO capabilities Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 15 Pmod 1 FPGA Pin Assignments Pmod Pin Signal Name FPGA Bank O functions FPGA Pin 8 PMODL 8350 2 P U ADIZP _ 3 PMODL2 B35JO 2 N M9 GND VCC PMOD1 4 B35 IO L3 N TO DQOS 5 wa P w PMOD1 6 B35_10 L4_N TO PMOD1_7 B35 IO L5 P TO AD13 Table 7 16 Pmod 2 FPGA Pin Assignments PmodzPin Signal Name FPGABank O FPGA Pin 1 PMOD20 83 0AS _ s PMop i 6 GD w 8 PMOD2S B35 10 8 p ryapiap MS 9 PMOD 6 Ma w Gb
15. 46 SIO s Il ANS _ Ho owe o SMiO is Pl aa _ ow AS _ Hos p i12 83210A3 P TU DQS P AMI _ 1207 vason 10 N T DOS Hos pase 29 BXLIO S P DQS P vasin mak Yu rss aes Huo pasze 5 P IDOS P Hui vasan 45 832 0 us passe 6t B3LIO ULP TyDOS P Al emo DON _ maf 137 B34IO A3 P UDOS P wa Hus N 135 N TDOS N we _ 16 basso 4 eios emis 6 bos 12 BAJAS N OOSN v2 _ Hus passe iu P IDOS P asz _ Hus vasen 169 10 115 ABL _ 1220 pasze 188 P _ sera ox ona was 2221 even 98 esos _ Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 7 Ethernet 100 1000 Interface The TB A7 200T IMG contains a 100 1000 Ethernet PHY and RJ45 jack that can accept a standard Ethernet twisted pair cable The PHY is a Marvell Alaska 88E1116R Gigabit Ethernet Transceiver that features Auto MDI MDIX integrated loopback capability programmable LED functions and multi IO standard RGMII interface The following table details the PHY RGMII pin interconnection to FPGA Bank 36 pins Table 7 8 Ethernet PHY FPGA Pin Assignment CK PHY IO LI9_N TaVREF
16. j29 Dbe cmn DP3CMMP 30 2 31 GND GND _ 32 C2M P B19 216 MGTPTX3 ___ GND 3 A19 216 MGTPTXS DPA CAMP 4 DPAC AMN 35 GND GND 36 DPeCeMP 022 26MGTPTXI ml mcr Dre CMN w __ Gp J Ro Jj po I 1 PGCM r I DP COMP 2 GND f 2 3 GD NENNEN 2 6 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED m inreviun 4 PIN FMC PIN NAME PIN BANK IO 116 MGTP E15 DPO M2C N 7 GND 29 Se pots _ iwepP 1 1 GD GND 6 GND a GND NENNEN LM8PCC 2 GND ev a iasan t5 ooN NENNEN NN IAM 27 26 LA26P J24 1610006 27 27 LA26N H24 16 OL0N 1 R 1 Ttk 850 TD ____ GND 3 ono 3 ms GND TRSTL 2 35 aave 0 GND 36 sSPSV NENNEN a ramo 2 1 3 J 1 HAS5SP 6 GND S 8 HAN M34 15101220 HOP 9 1 Pp Jal
17. 53 Table 7 15 Pmod 1 FPGA Pin ASSIQ ImamlS uuu uuu SL Sus 54 Table 7 16 Pmod 2 FPGA Pin Assignments a a 54 Table 7 17 User LEDs Pin Assignment a a 55 Table 7 18 DIP Switches FPGA Pin Assignment a 56 Table 7 19 Push button Switches FPGA Pin Assignment 56 Table 7 20 SPDIF to FPGA Bank 35 Pin Assignment a a 57 Table 7 21 Fan control to FPGA Pin Assignment a a 58 Table 8 1 Default Jumper Configuration Selection by shunts across indicated pins 59 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 5 inreviun Introduction and Product Safety Thank you for purchasing the TB A7 200T IMG board Before using the product be sure to carefully read this user manual and fully understand how to correctly use the product First read through this manual and always keep it handy SAFETY PRECAUTIONS Observe the precautions listed below to prevent injuries to you or other personnel or damage to property e Before using the product read these safety precautions carefully to ensure proper
18. FMC PIN NAME PIN BANK IO HB11 N 31 HB10 P ____ GD 3 HBP 133 _ GND 34 HBMP ____ GD 3 J eP Jae _ HBiBN 3 HBZPCC GD 3 HBIZNOCC VOBMC 3 L GND j40 Note PRSNT and PG signal are inverted before it is applied to FPGA IO Note As the two FMCs share a single I2C bus FMC 2 is set for a higher I2C slave address Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 6 DDR3 SDRAM SODIMM Connector The TB A7 200T IMG development board includes a JEDEC standard 204 pin DDR3 SODIMM receptacle that can accept a DDR3 SDRAM module Since the Data lines originate at FPGA SelectlO pins the 2 speed grade device on this board can support up to 800MT s 400MHz Clock in a 64 bit controller structure see Xilinx datasheet DS181 Artix 7 FPGAs DC and Switching Characteristics The clock generator CLK1 output generates the clock timing for the DDR3 controller through SYSCLK and can be set anywhere between 200 400MHz depending on the SDRAM speed grade DDR3 SDRAM SODIMM 1V5_DDR3 gt VCCO E DO D31 FPGA IO BANK 32 DQSOpn DQS3pn DMO DM3 0V75 VREF SYSCLK AO A15 200MHz P VCCO BA0 BA2 lt 1V5_DDR3 0V75_VTTREF RAS be CAS_N lt q 3 3V VDD SPD 1V5 DDR3 gt VCCO WE
19. SODIMM Connector Ethernet Connector Micro USB Connector S PDIF Connector Connector XADC Connector Fansink Connector Power Input Connector Pmod Connectors VADJ select header Xilinx JTAG Connector Optional connectors 200 mm W x 200 mm H 16 layers 2 964 mm 10 FR 4 Xilinx Artix 7 XC7A200T 2FFG1156C 35mmx35mm BGA package Samtec ASP 134486 01 10x40 pos 10mm stacking height TE Connectivity 2 2013289 1 HALO HFJ11 1G01ERL GigE integrated magnetics RJ45 8P8C no LEDs Hirose Electric ZX62D AB 5P8 KYCON KLPX 0848A 2 O Orange color RCA jack Molex 73415 2063 Harwin M20 8760342 2x3 pos 2 54mm pitch Header Molex 22 11 2032 3 pos 2 54mm pitch latching Header CUI PJ 002AH SMT TR 2 0mm pin 5 5mm OD Sullins PPTCOG2LJBN RC 2x6 pos 2 54mm pitch right angle socket Harwin M20 8760342 2x3 pos 2 54mm pitch Header Molex 87832 1420 2x7 pos 2mm pitch shrouded Header Power remote Connector Samtec TSM 102 01 T SV 2 pos 2 54mm pitch Header Note all Header type connectors are vertically oriented unless otherwise noted Rev 2 04 TOKYO ELECTRON DEVICE LIMITED Rev 2 04 Figure 6 1 shows the board assembly top side details and dimensions inreviun 200 i i ka E EJ ilii Sa 78 s n ET NH 2 re iis zz 997 T 196 192 163 07 160 78 104 14 93 22 116 33 100 08 4 064 196 Figure 6 1 Board Dimensions top vi
20. Series FPGAs Memory Resources User Guide UG474 7 Series FPGAs Configurable Logic Block User Guide UG475 7 Series FPGAs Packaging and Pinouts Product Specifications User Guide UG479 7 Series FPGAs DSP48E1 Slice User Guide UG480 7 Series FPGAs Zynq 7000 All Programmable SoC XADC Dual 12 bit 1MSPS Analog to Digital Converter User Guide UG482 7 Series FPGAs GTP Transceivers User Guide UG483 7 Series FPGAs PCB Design Guide UG586 Zynq 7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions v2 3 User Guide UG769 LogiCORE IP 7 Series FPGAs Transceivers Wizard v2 6 User Guide In addition to the ACDC A7 Carrier card the following table outlines the included accessories Table 1 1 Accessories Desktop power adapter 40W 12V PN GST40A12 P14J or equivalent Mean Well Cable 0 91m 18AWG NEMA 5 15P to IEC320 C13 or equivalent Tripp Lite Cables 1 83m USB A male MicroB Male Tripp Lite Standoffs 35mm M2 6 Hiosgi 6 opacer w Brass Screw 35mm M2 6 Hiosgi 6 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 9 inreviun 2 Overview The TB A7 200T IMG development board for the Xilinx Artix 7 FPGA is a reduced cost platform for evaluating and developing designs targeting Artix 7 FPGAs Revision 2 0 of this board provides a fansink cooled FFG1156 package 2 speed grade device The base platform common feature set includes Xilinx Artix 7 FPGA device e wo 57 1 high pin count FPGA mezzani
21. access to the FMC JTAG loop as well with the FMC data path chained from the FPGA JTAG TDO Onboard circuitry ensures that the JTAG data path loop is properly closed when only one FMC module is present automatically shunting JTAG TDI to TDO in any unoccupied FMC slot Note Only one JTAG connection should be used at a time Either Digilent JTAG or JTAG header Do not plug into both at the same time Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 13 J2 Xilinx 14 pin JTAG Pinout Pin Xilinx 14 pin JTAG Pin s GND TK 6 7 ow mo s GND TD 10 Note VREF is driven VADJ FMC1 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 14 FPGA Bank 0 JTAG Pin Assignment As mentioned in the SPI Flash section the FPGA can be directly configured from JTAG JTAG configuration mode is activated by installing a shorting shunt across header pins J26 standard 2 54mm pitch 7 12 2 Pmod Interface The TB A7 200T IMG features two Digilent Pmod standard 2 54mm right angle 2x6 female receptacles for interconnections that include eight bi directional digital CMOS level I O signals 3 3V and ground These connectors directly support 6 or 12 pin Pmod standard peripheral modules that feature a large number of general and special IO functions ON 3 3V d ESD 2860000 Protection 5 PMOD1_ 0 7 OOOQOOQOLJ J Pmod 1 QOOOQOO 7 e95888
22. and HV capacitor for the line side common mode returns often called the Bob Smith Termination The Ethernet Status LEDs are mounted the PCB LED 023 indicates Link status 022 indicates line activity and D21 can be user programmed for any special Ethernet condition indication per the LED options provided by the PHY 7 8 USB to UART Controller The TB A7 200T IMG features a Silicon Labs CP2103 USB to UART interface to communicate with a PC This module creates a virtual COM port on the computer driver installation required refer to silabs com for PN CP2103 to allow the user to connect through standard USB The USB interface on this card is Micro USB Type AB which mates with either Micro A or Micro B cables TB A7 200T IMG Terminal Micro USB Program Connector Micro USB SiLabs Cable rr CP2103 NE Bank 36 Protection Figure 7 14 USB UART Interface Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 10 Micro USB Type B and AB Compatibility F l m W AL 1 The UART signals are connected to the FPGA s single ended pins on Bank 36 Provided below is table indicating where the signals connect Both the UART transmit and receive data signals are connected as well as flow control signals Using the PC s virtual COM port drivers there are different supported baud ra
23. on the line The line is also received in true logic and no inversions are required prior to application to the FPGA input pin In addition to the transmit and receive PHY function the FPGA also controls both the receiver and transmitter enables to shut down the receiver line driver device when not active Note that the RX enable is active low while the TX enable is active high Table 7 20 SPDIF to FPGA Bank 35 Pin Assignment Signal Name SPDIF SPDIF SPDIF_TX SPDIF TX Note The SPDIF TX and both EN signals must be defined in the FPGA code and not allowed to float When the SPDIF RX EN Nis high the SPDIF RX signal is pulled high The SPDIF interface is tolerant of accidental reverse connection however the user must ensure that the source and destination are both SPDIF compliant to ensure correct operation The input and output jacks present DC terminations to avoid damaging the board do not apply DC voltages greater than 2 5V on the receive port and 3V on the transmit port For more details on the electrical specification of SPDIF refer to international standard IEC60958 3 Digital Audio Interface Part 3 Consumer Applications Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 16 Fan Interface The TB A7 200T IMG provides an active heatsink fansink for the FPGA since a full activation of all the GTP ports plus configurations full of high speed internal logic can readily push the d
24. with a typical capacity of 150mAhrs far exceeding the shelf life of the battery SR44 Silver Oxide cells may also be used however they may contain mercury and can become hazardous if leakage develops after long use Regardless of battery chemistry the battery cell should be replaced at timely intervals 3 4yrs max to reduce the possibility of leakage which could damage the holder and PCB Refere to manufacturer s requirements If any leakage is observed the battery cell must be immediately removed from the holder using appropriate safe handling procedures Any leaked material should be cleaned away from the PCB using a suitable board wash solution and the PCB area where leaked material was found closely examined for damage that might impact operation Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 10 Quad x4 SPI Flash and FPGA Configuration The TB A7 200T IMG has a single 256Mbit quad SPI flash memory for FPGA configuration and user data storage purposes Since the XC7A200T consumes 78Mbits of space for configuration at least 128Mb is available for user data storage Please refer to UG470 7 Series FPGAs Configuration User Guide for details on the operation of device configuration Device Micron N25Q256A13EF840E 256Mbit x1 x2 x4 support Data Rate 100 MHz maximum clock frequency in single transfer rate mode Access to programming the FPGA configuration image as well as user data store in the Flash has been provided t
25. 100 00MHz Bank 116 MGTREFCLK1 Although the device defaults to factory programmed settings all settings can be modified through the 2 interface The Si5338B presents a slave address of 0x70h to the local I2C bus hosted from FPGA bank35 Refer to Silicon Labs document Si5338 RM for details on the internal structure and register set The user may change any of the clock frequencies to suit application requirements however the output types must remain as specified in the preceding table Note that the FPGA uses its own internal clock for configuration from the SPI Flash and is not dependent upon any of the clocks generated by the Si5338B In addition to the crystal oscillator the Si5338B provides several inputs that can feed the reference or feedback inputs of the first PLL stage phase detector Inputs 5 and 6 which can operate differentially or single ended run from 3 3V FPGA IOs on bank 35 The FPGA IO pair 1019 can be set for TMDS 33 differential output mode to properly drive the input at up to 350MHz Alternate termination options in layout can also allow other modes Input is optionally provided as an LVCMOS Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun single ended signal from FPGA bank 35 and can serve as an input to the PLL for FPGA based feedback loop logic Notes reserved clock pll clock out1 set property IOSTANDARD LVCMOSS33 get ports adj pl set property PACKAGE PIN P5 get port
26. Bxx in increasing numeric order Please refer to the following FMC connector to FPGA IO pin mapping tables for details on the two FMC FPGA IO assignments of the board Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 30 inreviun 7 5 1 FMC HPC 1 J18 IO Allocation This FMC connects all 34 LAxx differential pairs and all 24 HAxx differential pairs to banks on the FPGA HBxx ports are not connected Eight high speed DP lanes are provisioned with GTP pairs TX and RX and both GBT Clocks are received Summary High Speed FPGA Bank 113 Bank 213 8 GTP channels 4 4 connected to DP pairs Low Speed FPGA Bank 12 Bank 13 Bank 14 e 34 differential LA pairs _ assigned to bank 13 SRCC port LAO1 assigned to bank 13 port LA17 assigned to bank 12 MRCC port LA18 CC assigned to bank 12 SRCC port e 24 differential HA pairs HAOO assigned to bank 14 SRCC port HAO1 assigned to bank 14 SRCC port HA17 CC assigned to bank 14 MRCC port HA18 CC assigned to bank 12 SRCC port Rev 2 04 TOKYO ELECTRON DEVICE LIMITED Table 7 5 FMC 1 18 to FPGA Pinout PIN FMC PIN NAME PIN 1 ioo _ sswarex 1 DPiMeGP 2 _213 A1 DP MeECN 3 GND 4 pewcP cmn 7 DPs ra N lj 213 MGTPRX AL20 DP2M2CP 6_ s 213 MGTPRX 20 DP2 MON 7 NENNEN a
27. GND HATZ PP GD AD HA2N Rev 2 04 TOKYO ELECTRON DEVICE LIMITED m inreviun BANK IO 4 PIN FMC PIN NAME PIN BANK IO HA16 P 15 GND ____ Haen 16 HAI P ev Jt CHAN hoP As b HAON li ev 2 HMeN j oP GND HB8N 22 HB2P ew a HEN j j ____ HB5P GOD f ____ HB5N 2 HOP fJ ev J j ____ oP 2 GND 28 HB8P ev 29 j j HP Jsl HBI2P ev 3 BAN HP 3 GND ____ 34 HHP fJ ev 3 j HBMP 3 onb Han 37 H amp BOP O Z U 38 lt c oD i 16NOLI3P J29 3 w 1 6 GND a 24 9 L amp 8P 2 GND NNNM LA2P 5 GND ae LM6P GND MEN LAP GND sn 1 llOLiSP 929 TOKYO ELECTRON DEVICE LIMITED m inreviun 4 PIN FMC PIN NAME PIN BANK IO GND 23 LA19 N J25 16 IOLO4N LP 22 GND f eso enois iwsp z Gp
28. ITED 29 inreviun K J H G F E D 2 GND CIK3 BID PO DPI MAE 3 GND CIK3 BDIRN GND CIKI MCN 4 GIK2 BDE P CIKOM2C P GND BIDIRN GND CLKOM2CN GND 6 7 GND AP GND N avp W GND GND LA15 P 20 GND ABN _ VK _ CC 21 GND 22 H HB03 LA18 P CC 23 HB02 GND LA23P LA18 NCC 24 GND P HBEP TAN GND 25 HB00 P CC HB01 N HB04 P HB05 N 26 HB00N CC GND GND HBN GND 1 LAZP 2 GND HBU7P GND LA25P_ LAN AZN BE 28 HB06 P CC LA24P LA25N HB08 P HB09 N 29 HB06 N CC cD DPBCMMN 30 GND GND 149P GND HBi3 P 31 HB11 N HB12 P HB13 N 3 HBIQN GND LA28N GND ktB2N GND 33 GND HB15 HB19 P 34 HB14 P HB15 HB16 P HB19 N 36 HB14 N HBI6 N 36 GND HB18 F HB21 P 37 HB17 P CC HBIS N LAN HB20 P HB21 N GND HBT7 N CC GND 39 _ VIO B 2 40 B M2C GND LPC Connector LPC Connector LPC Connector LPC Connector Figure 7 12 VITA 57 1 FMC HPC LPC Pinout Note Not all of the IO pins shown in the pinout above are assigned on the TB A7 200T IMG FMC connectors The pin assignment conforms to the VITA 57 1 mandated progression of LAxx population followed by HAxx and H
29. N 0V75_VTTREF gt VREF 50 51 FPGA IO BANK 33 DDR3 CLKOpn DDR3 CLK1pn DDR3 CKE1 SOCKET DDR3 DDR3 ODT1 RESET N 1V5 DDR3 J99 VCCO 032 063 p FPGA IO BANK 34 DQS4pn DQS7pn DM4 DM7 p 0V75_VTTREF gt VREF BANK35 1025 q EVENT BANK35 LOCAL I2C 2 e SA0 1 I2C ADDRESS 0xA6 Figure 7 13 DDR3 SDRAM SODIMM Structure The DDR3 bank arrangement DQS IO assignments clock connections and Vref provisions follow the suggested memory structure in Xilinx document UG586 Zynq 7000 All Programmable SoC and 7 Series Devices Memory Interface Solutions User Guide Using features built into the Vivado Suite a DDR3 memory controller can be readily and easily generated following the procedure described Chapter 1 The following table group provides the Pin IO mapping of the DDR3 Banks to the SODIMM module Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 7 FPGA IO PINOUT MAPPING TO SODIMM SOCKET SODIMM SODIMM PIN FPGA BANK FPGA PIN amem ono Meh Peas Pr AG ola 9 aa 4 3 BIOS AG _ 6 3 AM _ 7 A 9 A6 _ sf A 2 A7 s A s pomas _ 84 PSC _ ras ess o a NIJSRCC _ 5 Ba 18 53310A8
30. N 8 Ee ee ae 213 MGTPRX AL18 2 10 j 213 MGTPRX 18 11 ee GN e Mao _ 7 113 MGTPRXO_ GND 13 DP7M CN 17 113 MGTPRXO_ MSMGTPRXi AL16 4 2 14 GND s MSMGTPRXi 16 4 2 15 GND GND 16 DPeMeCP ANS 113 MGTPRX2 5 113 MGTPRX2_ 11 a313 0 5 18 GND o o 113 13 0 5 19 GND ew _ x j Gp AN23 DP1 C2M P AP23 DP1 CaM N GD O AL22 roe AM22 DP2_C2M_N 1 GND GND DP9 C2M N Gp Gp Hue uus WAR GND GND sMGTPTXS ANI3 0 5 38 GD o o GD d J RESO j GND t PGCM ed NNNM GND pT GD 5 GBTCLKO MC N ND DP7_C2M_P N AJ17 AK17 AJ15 AK15 AN17 A 10 11 12 13 14 15 16 17 18 125 28 ss 24 NENNEN EE NENNEN 2 GND 27 GND 28 8 x _ 17_ 38 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED m inreviun PIN FMC n NAME PIN BANK IO 213 MGTPRX AJ19 DPO M2C P 7 _ j 8 LAM PCC L ew 9 we No _
31. SRCC CLK FPGA QSPI C Uj N3 FPGA_QSPI_S_N FPGA_QSPI_OE_N 7 11 EEPROM 2kbit 12C An onboard 2kbit 126 EEPROM 24 02 is programmed with various manufacturing information The EEPROM is permanently enabled for writing It is permissible to store custom data in this EEPROM however one must be careful to ensure that the manufacturing information is never overwritten ___8 35 0 14 PTAISRCC 15 B35_IO L9_N T1 DQS_N AD7 N B35_1O L10_P T1 AD15_P_ 835 10 10 NTIADIGN B35_IO L11_P T1 SRCC_ P4 95 35 IO L11_N TI SRCC P3 ___835 10 14 NTZ SRCC T4 35 35 35 35 35 35 35 The contents of the EEPROM are displayed in Appendix A Note The user must be cognizant that the FMC 126 EEPROM is always write enabled As it contains critical information one must never overwrite the factory settings 7 12 JTAG and Pmod Interface 7 12 1 Optional JTAG Connector The TB A7 200T IMG provides an optional JTAG interface that follows the Xilinx 14 pin JTAG standard The user may connect the Xilinx development system to the board either by Xilinx USB Platform Cable adapter through the JTAG header or via USB directly through J27 Micro USB type A B and the Digilent JTAG interface module U55 Stuffing options are provided to allow the Digilent module to control its JTAG bus buffer through a GPIO on the module or unconditionally enable or disable the buffer The JTAG interface has
32. _ SN pe aon _ oo S o 1 GN 27 T P AG31 19 OLISN AF27 LAION 15 LAO _ GND 17 1 13 AG 13 10019 AD tata pte LAN _ AH26 18 IOLI9N _ soon Am LAM N GND 1 GND 2 PCC AL30 1210012 _ 21 1270112 TMOLMP 29 LAI8 22 GND Akso Late 23 1 23 es GND M p26 _ AL34 12 OLOIP 12 OLOAN AL33 LA27N 27 LA26N AM34 12 OLOIN GND BERN NEN SsiOoldN TO SCL 0 mo 09 804 81 TOO j GD aef 33AX GD ms GND 4 j tV 35 GM m PG_ AF34 HAoipcc 2 Gp 2 NCC 3 j GND A HAOPCC po GD 5 HAONCC 1WioLoP v33 HAOS P 6 NENNEN maos n r Le GND 8 HAN Awe Hee P 9 _ HAO8 N AB34 Haia P 2 GOD AC32 HA13_N HA12_P AA29 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED m inreviun PIN FMC PIN NAME PIN GND 14 HA12 N AB29 14 IOL22N GND HAIN _ poo po GD 20 HM9N
33. circuitry P3 1 2 0 0 Fl 05010108 1 11 08 14 DM 51811 46R JUMPER TIN SMD T5 12V IN 1 4 ALA 1 worn 3 amp 17 12 14 22 07 14 DNS 5 PJ 002AH SMT TR CMS4402 1718 10 CONN JACK WSW 2 16V RIA SMT CHOKE ARRAY COM MODE 170 OHM 204 SMD 15 09 14 DM BNXD16 D1 P5 FILTER EMI 154 25 1 00RHz 1GHZ 1 2 11 68 14 DM 5 1971 46R JUMPER TIN SMD Figure 7 2 Power Input Circuit 7 1 2 Input Power Protection Circuit The TB A7 200T IMG features an input power protection circuit based on the Texas Instruments TPS24720 Hot Swap Controller This circuit isolates the large distributed capacitance of the board approx 2500uF plus as much as 2000uF depending on the two FMC modules preventing large transient currents from the AC adapter s output capacitors when hot plugged into the board No more than 100nF of capacitance is directly presented to the adapter output and the in rush current is ramped up softly preventing potentially damaging voltage spikes from being produced through the inductance of the DC cord TOP SIDE PROTECTED 12V TEST ATTACH POINT TOP SIDE 12V INPUT TEST ATTACH POINT 12V IN lt R248 SS10P4 M3 86A 49 9 21 _ DIODE SCHOTTKY 10A 40V SMPC CSD16403Q5 e R496 10 MOSFET N CH 25V 284 8SON 7 p 11 e 7 10 R255 10 114148 dx 3 2 OUT 8 D37 41453 3 lil NC 2 OUT O TuF ONS
34. disassemble repair or modify the product Otherwise a fire or electric shock may occur due to a short circuit or heat generation For inspection modification or repair contact our sales personnel Do not touch a cooling fan As a cooling fan rotates in high speed do not put your hand close to it Otherwise it may cause injury to persons Never touch a rotating cooling fan Do not place the product on unstable locations Otherwise it may drop or fall resulting in injury to persons or failure If the product is dropped or damaged do not use it as is Otherwise a fire or electric shock may occur Do not touch the product with a metallic object Otherwise a fire or electric shock may occur Do not place the product in dusty or humid locations or where water may splash Otherwise a fire or electric shock may occur Do not get the product wet or touch it with a wet hand Otherwise the product may break down or it may cause a fire smoking or electric shock Do not touch a connector on the product gold plated portion Otherwise the surface of a connector may be contaminated with sweat or skin oil resulting in contact failure of a connector or it may cause a malfunction fire or electric shock due to static electricity TOKYO ELECTRON DEVICE LIMITED 7 inreviun A Caution Do not use or place the product in the following locations Humid and dusty locations Airless locations such as closet or bookshelf Locations wh
35. e 7 19 Push button Switches FPGA Pin Assignment Push button RefDes top bottom Signal Name FPGA Bank IO function SW3 SW11 PUSHBUTTON 1 14 IO L6 N TO DOS VREF SWA4 SW12 PUSHBUTTON 2 B14 10 25 SW6 SW13 PUSHBUTTON 3 B13 10 0 AD23 SW7 SW14 PUSHBUTTON 4 B13 10 25 AF24 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 15 SPDIF Interface The TB A7 200T IMG features a pair of SPDIF Sony Philips Digital Interface COAX interconnect jacks one for Transmit and the other for Receive The jacks are industry standard RCA Phono style designed to accept a 75 ohm COAX cable with an RCA style plug The connector shells are industry standard Orange color that is commonly associated with wire non optical consumer Digital Audio interface i e SPDIF Transmit and Receive are identified by silkscreen text on the PCB top and bottom sides The 75 ohm line is supported using an Intersil ISL3176 RS 485 receiver line driver device Although the device supports differential line interface both RX and TX are used in single ended mode and are both AC coupled to the line The line driver output level applied to the jack is adjusted to SPDIF specified level with an impedance matched resistive pad network The schematic of the interface is shown below Figure 7 18 SPDIF Digital Audio Interface The data on the line is presented in true logic where a rising transition on the FPGA output pin produces a rising transition
36. e HR Ref clock assignments are shown in the following figure Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 26 inreviun VADJ CLK2 BIDIR FMC1 3 HAT P MRCC BANK HAOO CC 14 lt o lt Haor CC SRCC SRCC CLKO M2C LAOT CC HR BANK FMC1 lt lt cLK3 BIDIR E 13 lt lt OHS PRI gt SRCC lt SRCC CLK1 M2C a LA17 CC q HR BANK LA18 CC 12 lt q lt SRCC VADJ CLK1 M2C FMC2 LA18 CC i HR BANK LA17 CC 16 lt o lt HA01 CC SRCC SRCC EEE CLKO M2C 4 1400 CC q HR BANK LA01 CC 15 T lt L0 cC SRCC gt SRCC Figure 7 9 FMC HR IO Clock Assignments Assignment of FMC global M2C and bank CC clocks to the MRCC and SRCC inputs of their respective banks allows either FMC position to be configured within the FPGA to drive internal multi regional and global clocking domains The MRCC inputs in particular can supply direct clocking to multiple regions within the FPGA and have been assigned with the global M2C clocks from both FMC positions The bank associated CC clocks of the FMCs supply the more limited SRCC clock inputs that drive the regional logic of the banks assigned to their respective FMC IO groups LAOO 16 LA17 33 HA00 16 HA17 33 Refer to Xilinx document UG472 7 Series FPGAs Clocking Resources User Guide for details on the internal r
37. ectors however soldering is required Any soldering voids the warranty Note Prior to driving the MMCX connectors review Xilinx s guidelines on signal type and maximum amplitude Incorrect levels if applied to the MMCX connectors could permanently damage the FPGA board or both Note connector input clock set property IOSTANDARD TMDS 33 get ports user n user pj set property PACKAGE PIN R5 get ports user clk n set property PACKAGE PIN R6 get ports user clk p 7 4 3 DDR3 Clock Channel 1 of the programmable clock generator drives the MRCC inputs of Bank 33 the middle bank of three assigned to the DDR3 DRAM SODIMM interface Although the clock can be distributed globally this clock channel should be reserved exclusively for the DDR3 interface logic and it s frequency determined by the DDR3 operation speed requirements 7 5 FMC Connector Interface The TB A7 200T IMG board has two high pin count HPC 400 pin FMC connectors FMC 1 and 2 on board as shown on the block diagram These FMC connectors follow the VITA 57 1 standard using Samtec ASP 134486 01 receptacles that accept Samtec ASP 134488 01 or equivalent plugs present on FMC modules The connectors are located beside each other to accept either two single FMC modules or one double width FMC module per VITA 57 1 Presented below is the ANSI VITA 57 1 standard pin assignment of high pin count HPC FMC connectors Rev 2 04 TOKYO ELECTRON DEVICE LIM
38. encer EN 6A PG to Sequencer lt MGTAVTT 1 20V 2 5 gt TPS84621 CAT from Sequencer o Be EN 6A PG VCCAUX 1 80V 5 gt TPS84621 6A _ PG Blocks 0 17 37 1 80V 5 1 to Sequencer lt to Sequencer lt VCCO DDR3 1 5V 5 from Sequencer gt EN 6A 1 5V DDR3 gt DDR3 VTT 0 75V 3 3V board TPS51200 LDO 3A max sink source med EN Termination 3A VCCO HR 1 5 1 8 2 5 3 3V 5 0 25A e sa and TPS84320 FMC1 VADJ 2 75A max 9 W EN 3A PG 9 VCCO HR 1 5 1 8 2 5 3 3V 5 0 25A max e TPS84320 FMC2 VADJ 2 75A max EN 3A PG Do FMC 3 3V x2 TPS84621 3A x2 6A max EN 6A PG i FMC 12V x2 1A x2 2A max TPS84320 3 3V board 3A max PEN 3A PG o TPS84320 1 8V board 3A max gt gt EN 3A PG B gt EN 70mA max PG Figure 7 1 Power Supply Structure Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 1 1 Power Input connector The TB A7 200T IMG has a single power input connector on the board a standard DC power jack with 2 0mm pin and 5 5mm barrel dimensions Use only the power supply brick specified by inrevium The center pin is positive and the barrel is negative the center pin is fuse protected Both conductors pass through an optional common mode filter choke array as well as an EMI filter block before being applied to board
39. esources and clock distribution capabilities 7 4 1 FMC GTP Clocks The GTP clocks are associated with the high speed differential FPGA serial link blocks which on the TB A7 200T IMG are evenly divided between the two FMC modules 8 per module All GTP clocks are driven in differential CML mode from the FMC positions as well as the clock generator The FPGA MGTP ref clock inputs internally provide correct termination of the AC coupled clock signals The GTP Ref clock assignments are shown in the following figure Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun MGTP BLOCK 113 GBT CLK1 M2C p gt MGT REFCLKO FMC1 GBT CLKO M2C p gt MGT REFCLKO MGTP BLOCK 213 CLK2 MGT REFCLK1 15338 CLK3 MGT REFCLK1 MGTP BLOCK 116 GBT CLKO M2C MGT REFCLKO 1 MGTP BLOCK 216 GBT CLK1 M2C gt MGT REFCLKO Figure 7 10 GTP Clock Assignments The Si5338B clock generator shown is the main system clock generator outputs 2 and 3 are assigned to provide clock reference to the high speed serial links of FMC 1 and FMC 2 respectively and are programmed to a default frequency of 100MHz These clocks can be used as a timing reference to the GTP blocks in absence of a ref clock source on the respective FMC module 7 4 2 User Clocks Two general purpose user clock sources may drive the FPGA as depicted below p
40. evice power consumption over 10W The 3 pin fan connector J24 is located near the FPGA and has a pinout that conforms to the Intel ATX standard The fan power comes from the main hot plug protected 12V and the fan s DC can be PWM modulated on the low side through an output of the FPGA The Fan Tach signal represents the rotor speed and produces a pulse on each revolution The Tach signal is provided to another IO on the FPGA and can be used in a user designed fan control feedback loop that regulates the fan speed through PWM Table 7 21 Fan control to FPGA Pin Assignment Signal Name FPGA Bank 10 function FPGA Pin LS FAN TACH B15 10 0 LS FAN PWM B16_IO 0 The PWM signal from the FPGA passes through the 90120A sequencer device which acts as a failsafe mechanism in case a design error or other cause would force the PWM signal to be held low fan OFF This is important since a dissipation of 10W in the FPGA can quickly raise the die temperature to damaging levels if the fan is not operating An optional bypass strap R582 is provided in case the user s PWM control logic includes failsafe provision and can be trusted enough to eliminate the 90120A protection In that option the user must ensure the PUDC N FPGA Bank 14 pin W26 is pulled low so that the fan runs during FPGA configuration Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 8 Default Settings The TB A7 200T IMG contains a small number of user selectable setti
41. ew TOKYO ELECTRON DEVICE LIMITED inreviun Figure 6 2 shows the board assembly bottom side details and dimensions 196 163 07 160 78 104 14 100 08 93 22 90 68 34 04 30 23 O 4 064 I M 131 83 186 45 190 5 Figure 6 2 Board Dimensions bottom view Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 17 TB A7 200T IMG Hardware User Manual fi UI UT ag 7 Description of Components 7 1 Power System The TB A7 200T IMG board s power supply structure is shown in the figure below The major parts of the power supply system are then discussed Power Switch Y In rush MAIN 12V OE Controller 3 34A max ida TPS24720 Pc p gt m EN to power converters PG from power p SUPPLY convenes SEQUENCER o 430kHz bi phase for LDO 3V3_VMON gt MONITOR M VCCINT converters gt TLV1117 33 60 MAIN 12V bi phase current SYNC share 12A max gt TPS84621 VCCINT 1 00V 5 from Sequencer EN 6A PG 11 3A max SYNC TPS84621 VCCBRAM 1 00V 5 EN 6A PG 0 7A max to Sequencer lt MGTAVCC 1 00V 3 gt TPS84621 GA from Sequ
42. he pin high to the Bank s VCCO Under this condition the LED control signals will float and any of the LEDs may or may not light up during configuration depending on uncontrolled electrical characteristics Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 14 General Purpose User Switches 7 14 1 User DIP Switches The TB A7 200T IMG is equipped with two Copal Electronics CHS 04TA SPST 4 positions DIP switches The switches are wired to pull the sensed IOs to logic Low in the ON position and read logic high when open Table 7 18 DIP Switches FPGA Pin Assignment Switch RefDes Signal Name FPGA Bank IO function Switch RefDes Signal Name FPGA Bank IO function FPGA Pin SWITCH1 1 B12 10 0 AJ24 SWITCH1 2 12 10 122 P T3 27 SWITCH1 3 B12 0 122 N T3 AN27 SWITCH1 4 B12 123 P T3 AL25 SWITCH2 1 B12_10 L23_N T3 AM25 SWITCH2 2 812 124 P T3 AP25 SW5 SWITCH2 3 B12 10 124 N T3 AP26 SWITCH2 4 812 10 25 AL24 7 14 2 User Push Switches The board also features two sets of four C amp K Components KMR211GLFS momentary push buttons One set of 4 are on the PCB top the other on the bottom directly underneath the top set Each button is wired in parallel with its matching button on the other side so all eight buttons are sensed with four lOs In resting state the sensed lOs read logic high pressing a button either top or bottom side pulls the corresponding sense IO to logic low Tabl
43. ich receive oily smoke or steam Locations exposed to direct sunlight Locations close to heating equipment Closed inside of a car where the temperature becomes high Staticky locations Locations close to water or chemicals Otherwise a fire electric shock accident or deformation may occur due to a short circuit or heat generation Do not place heavy things on the product Otherwise the product may be damaged Disclaimer This product is an evaluation board intended for development of video data with Xilinx Artix FPGA Tokyo Electron Device Limited assumes no responsibility for any damages resulting from the use of this product for purposes other than those stated Even if the product is used properly Tokyo Electron Device Limited assumes no responsibility for any damages caused by 1 Earthquake thunder natural disaster or fire resulting from the use beyond our responsibility acts by a third party or other accidents the customer s willful or accidental misuse or use under other abnormal conditions 2 Secondary impact arising from use of this product or its unusable state business interruption or others 3 Use of this product against the instructions given in this manual 4 Malfunctions due to connection to other devices Tokyo Electron Device Limited assumes no responsibility or liability for 1 Erasure or corruption of data arising from use of this product 2 Any consequences or other abnormalities arising f
44. l converter amplifiers etc A third linear regulator the Texas Instruments TPS51200 is powered from 1 5V and 3 3V and is used to generate the DDR3 VTT supply This regulator is specially designed for DDR termination and can both sink and source up to 3 Amps with its main power path supplied by the output of the 1V5 DDR3 switching regulator Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 20 inreviun 7 1 5 Power Sequencing The FPGA requires specific supply rail sequences in order to avoid large transient currents during power up and power down This is achieved using a discrete power sequencing circuit The circuit accepts Power Good indicators from the various DC DC converters and then sequences the DC DC converter Enable signals appropriately 7 1 6 Voltage Rails Test Points The development board features several power rail test points that can be used for debugging or other types of measurements Table 7 1 Voltage Rails Test Points 7 1 7 Power and Miscellaneous LEDs Shown below are the different LEDs present on the board which serve as power indication or general purpose programmable LEDs Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 2 Board LEDs FPGA Programming INIT signal Bicolor Green Red Red Programming in progress Green Programming complete be Gen FPGA Programming DONE signa D11 top D38 Bottom User LED 1 D14 en D40 Bottom IS Ethernet LED1 undefined defa
45. m 5 Loh O e O f Figure 7 5 VADJ Voltage Selection Header shunt Positions Lad cm Note Only place one shunt jumper per header in a valid desired configuration above or permanent board damage may occur TOKYO ELECTRON DEVICE LIMITED Rev 2 04 TB A7 200T IMG Hardware User Manual fi UI UT 7 2 FPGA Banks Assignments The TB A7 200T IMG supports the Xilinx Artix 7 FPGA in the FFG1156 package The figures below present the Artix 7 bank structure and user bank function assignments on this board using the XC7A200T FFG1156 Package XC7A200T only All HRI O banks and the GTP Quads are fully bonded out in this package Quad Quad Right VO Column GTPs GTPs Column Banks Banks Horizontal Center CMT Clocking CMT Backbone Backbone Backbone UG4T 04 Figure 7 6 XC7A200T FFG1156 Bank Structure FMC2 3 FMC DP4 7 Ethernet RGMII Bank Bank FMC2 LA00 16 HA00 02 06 USBUART 246 LED4 Fan PWM Pmod QSPI Flash SPDIF be il FMC2 LA17 33 1 07 11 2 local and Bank 15 HR LEDS Fan Tach FMC1 17 QSPI Flash cfg VADH EDs1 2 Pushbuttons1 2 DDR3 SODIMM vabi FMC1 LAO0 16 HA19 21 Pushbuttons3 4 Bank 12 HR VAD FMC1 LA17 33 HA18 22 23 DIP Switches FMC1 DP4 7 FMC1 Figure 7 7 TB A7 200T IMG User Bank Function Assignments Notes e Bank 0 is the FPGA co
46. n header two channel Micro USB user UART interface via Silicon Labs CP2103 GM Micro USB to JTAG configuration link via Digilent 410 308 P DC Barrel jack 2 0 5 5mm for 12VDC filtered and fuse protected Power switch 2 pos slide switch optional header for remote switch in parallel Fan header 3 pin ATX pinout 12V Tach connection User push switches four on each PCB side parallel wired User LEDs Green four on each PCB side parallel wired DIP switches two 4 pos actuating 8 GPIOs Pmod compatible 2x12 PCB edge sockets 2 sets JTAG header Xilinx standard 14 pin 2mm with keyed shroud Optional Power ON OFF remote switch header 2 pin Refer to VITA 57 1 FMC Standard http www samtec com standards vita aspx Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 11 5 o pus G im u e N n m 4 Block Diagram The following figure shows the block diagram of TB A7 200T IMG yer 1LLA140 SOWA Xew A suoddng JOjoeuuo2 JOjoeuuo2 wiPOWd uid Zy wiPOWd 9 Eig giBS s BBEG IS amaaa mimi JO 8Jeuec YOO D jndjno geeesis ZHW Sc 000900 0 s JOAISOSUBI 000200007 Ol 9 OVI 8j 4911 3989 N INVHOOMSd V9dJ slivy 3ONVHOSIG 9 N LINI
47. nd RX and both GBT Clocks are received Quick Summary High Speed FPGA Bank 116 Bank 216 8 GTP channels 4 4 connected to DP pairs Low Speed FPGA Bank 15 Bank 16 e 34 differential LA pairs LAOO CC assigned to bank 15 MRCC port LAO1 assigned to bank 15 SRCC port LA17 assigned to bank 16 SRCC port LA18 CC assigned to bank 16 MRCC port e 12 differential HA pairs HAOO assigned to bank 15 SRCC port HAO1 CC assigned to bank 16 SRCC port Rev 2 04 TOKYO ELECTRON DEVICE LIMITED Table 7 6 FMC 2 J19 to FPGA Pinout BANK IO PIN FMC PIN NAME PIN 1 cwm 0 1 McP 2 3 GND ND aj ms 3 a j E 5 DP MCN X 6 _ D MCN 7 GND GND 8 ___ 1 GD 9 beamen 2 j GND DP mec N GD OND 12 D18 216 MGTPRX3_ 2 ph OP CHR _ 4 2 14 GND s DPA 2 15 GND GND 6 D20 2 6 GND _ 17 DP6M2CN C20 216 MGTPRX1_ 216MGTP F21 GND ss 216MGTP E21 GND NENNEN NNNM j GND _ DPi_caMN 23 Jo ws GND 24 DP9C MP GND DP9CMN DP2CMMP 20 GND 2 2 27 GOD NENNEN 28 ___
48. ne cards FMC connectors with many I O and 8 multi gigabit transceivers MGT s available on each e DDR3 SO DIMM module e 100 1000MBaseT Ethernet RJ45 style port e Digital Audio S PDIF coaxial TX and RX jacks e Micro USB port for FPGA configuration e Micro USB UART port e 4 general purpose pushbuttons and LEDs 8 positions general purpose DIP switches e On board programmable clock generator e User clock input MMCX jacks e 256Mb QSPI Flash for configuration and user data Two Digilent Pmod 12 pin peripheral sockets 1 Pmod is a trademark of Digilent Inc The Pmod Interface Specification is the property of Digilent Inc Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 10 inreviun 3 Features FPGA Xilinx Artix 7 XC7A200T 2 speed grade in FFG1156 package fansink cooling Memory Single 204 pin 64 bit DDR3 SODIMM slot 256Mbit Quad SPI Flash EEPROM 2k bit manufacturing information Clocks On board Silicon Labs Si5338B 4 channel clock generator with 25 0000MHz crystal reference Interfaces FMC VITA 57 1 Connectors 2 x Samtec ASP 134486 01 400 pos HPC socket Featuring four VADJ voltage settings 1 5 1 8 2 5 3 3V for each FMC Setting via headers jumpers RJ45 jack for Marvell 88E1116R Gigabit Ethernet Transceiver RGMII interface three status LEDs on PCB S PDIF Digital Audio coaxial jacks RCA 75 ohms separate TX and RX via 20Mbps line driver and receiver receptacle pair for external differential clock XADC 6 pi
49. nfiguration control bank and is not represented in the User bank function assignment diagram The QSPI Flash connection to Bank 14 is active only during FPGA configuration User access to the QSPI Flash should be conducted through Bank 35 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 3 Clock System 7 3 1 Main System Clock generator The TB A7 200T IMG has a single quad output programmable clock generator the Silicon Labs Si5338B to generate the main board clocks This device supports an external 25 000MHz crystal as a frequency reference and can be programmed through an 12 interface to produce a wide range of frequencies independently on the four output channels Additionally the type of output driver for each channel can be programmed and the chip provides independent IO voltage rails for each channel Figure 7 8 Main Clock Generator An internal one time programmable OTP NV memory can be pre programmed by the chip manufacturer to customer required default frequencies and output types For this board the Sib338 s OTP NV storage is pre programmed the default input source is selected to be the on chip crystal oscillator and the four outputs are programmed in the following manner Table 7 4 Clock Generator Output Details Output Default Frequency IO Voltage Output Type Destination Input CLKO 50 00MHz LVCMOS Bank 35 CLK1 200 00MHz HSTL Bank 33 CLK2 100 00MHz Bank 213 MGTREFCLK1 CLK3
50. ngs set by shorting shunts on headers Table 8 1 Default Jumper Configuration Selection by shunts across indicated pins c WA 12 x x X Eth PHY TX CIK Delayed RX CLK on RXD stable _ Lx ox x 34 x PMGMISAEV 000 x x x x x 34 FMQVADI 25V o Px ox ox none x x FPGA configures Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 9 Appendix A EEPROM Contents Currently not available TOKYO ELECTRON DEVICE LIMITED inreviun DE TOKYO ELECTRON DEVICE IN Inrevium Company URL http solutions inrevium com http solutions inrevium com jp E mail psd support teldevice co jp HEAD Quarter Yokohama East Square 1 4 Kinko cho Kanagawa ku Yokohama City Kanagawa Japan 221 0056 TEL 81 45 443 4031 FAX 81 45 443 4063 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED
51. nk LDO are powered from the main 12V The switching regulators can efficiently provide full rated current without additional heat sinking beyond that provided through the PCB coupled cooling The switching converters made by Texas Instruments are compact integrated modules that contain all but the input and output capacitors There are only two different Tl switching converter types employed on the TB A7 200T IMG the TPS84320 for 3 Amp capacity and the TPS84621 for 6 Amp capacity The VCCINT VCCBRAM converter must supply up to 12Amps to the FPGA core this supply consists of a pair 6 Amp 584621 converters in parallel shared output configuration using bi phase synchronization to reduce peak input ripple current The bi phase synchronization is achieved through driving the CLK input of each converter with the same frequency at 180 degrees phase shift relative to each other Two linear regulators operating from 12V provide 60 80mA of current e The 3V3 VMON rail is a system rail generated from the 12V output of the Hot Swap controller stage Texas Instruments TLV1117 33 This rail is primarily used in the power sequence interface logic and must be stable before the power ON sequence commences Stage 1 e he 5V HD regulator also operates from the 12V output of the Hot Swap controller stage Texas Instruments LP2992A This rail is provided to the XADC header for attached analog signal conditioning circuitry buffers filters differentia
52. nm _ af 32 _ 0 no ess onson AD n us ess onapo rsa pao s onmo AM s D 4 A2 9 vos 6 BONO _ rao Do Rev 2 04 TOKYO ELECTRON DEVICE LIMITED No SODIMM SODIMM PIN FPGA BANK FPGA PIN P rerum women sume 4 Do AM 4 vao AS bo 2 A4 _ rae DQ 34 8920011 PSC AS 49 36 B32 40 11 AMS _ rsa am 40 ezone ANS _ reo vox 82102 NIS AMO _ erf DQ 2 2 AM _ amp Aui res ox us V9 res vos ve Dou 158 _ rsa paso 5 _ Rev 2 04 TOKYO ELECTRON DEVICE LIMITED No SODIMM SODIMM PIN FPGA BANK FPGA PIN feme women suma rss os slO e PI MS ss vos ve A _ os eson Pi rsa AG 193 NIS MS _ ovo 1 AG DM 28 83210Ai2 P TH MRCC A6 ho ovo
53. o the Xilinx core through Bank 35 GPIO pins shown in figure below VADJ FMC1 VADJ FMC1 3 3V BANK 0 FPGA CCLK CLK QSPI p DQ0 DQ3 TXB0108 Flash Bi directional ELn gt N25Q256 SPI FPGA Level Shifter CONFIG PINS BANK 14 3 3V 3 3V GPIOs TXB0108 Bi directional BANK 35 Level Shifter DISABLE during CONFIG Figure 7 16 FPGA SPI Flash Configuration Structure The flash may be programmed via JTAG either through the JTAG header or via the Digilent USB to JTAG interface module The JTAG configuration process uses the FPGAs built in SPI Flash writing facility in conjunction with Vivado which requires specific Bank 14 attachment using a supported SPI flash device Additionally the FPGA can be configured via SPI or JTAG JTAG configuration mode is activated by installing a shorting shunt across header pins J26 standard 2 54mm pitch Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun Table 7 12 SPI Flash Memory to FPGA Pin Assignment Signal Name FPGABank FPGA Pin Name FPGA Pin FPGA Configuration Flash IO QSPI_VADJ_D1 B14 IO L1 P TO DOO MOSI V29 QSPI VADJ D2 B14 IO L2 002 V26 QSPI VADJ D3 B14 IO L2 N TO DOS3 V27 CLK FPGA CCLK BO CCLK Xilinx Flash User B35 14 P T2 SRCC B35 IO L9 N T1 DQS N AD7 N B35 IO L10 P T1 AD15 P B35 IO L10 N T1 AD15 N B35 IO L11 P T1 SRCC B35 IO L11 N T1 SRCC B35 14 N T2
54. oltage Rails Test Points 21 Table 7 2 Board 5 22 Table 7 3 VADJ connected Banks uuu u pa lec custo edt Een 22 Table 7 4 Clock Generator Output Details a a 25 Table 7 5 FMC 1 J18 to FPGA 32 Table 7 6 FMC 2 119 to FPGA Pinoutl ed abu RO uk una uade 37 Table 7 7 FPGA IO PINOUT MAPPING TO SODIMM SOCKET I 43 Table 7 8 Ethernet PHY FPGA Pin Assignment esseeeesssseessseseeeee nennen nennen 46 Table 7 9 Ethernet PHY reset Configuration Selection 47 Table 7 10 Micro USB Type B and AB Compalibilily a 48 Table 7 11 UART Interface FPGA Bank 36 Pin Assignment 48 Table 7 12 SPI Flash Memory to FPGA Pin Assignment 51 Table 7 13 J2 Xilinx 14 pin JTAG Pinoutl a a a 52 Table 7 14 FPGA Bank 0 JTAG Pin Assignment a nnns
55. rom use of this product or 3 Damage of this product not due to our responsibility or failure due to modification This product has been developed by assuming its use for research testing or evaluation It is not authorized for use in any system or application that requires high reliability Repair of this product is carried out by replacing it on a chargeable basis not repairing the faulty devices However non chargeable replacement is offered for initial failure if such notification is received within two weeks after delivery of the product The specification of this product is subject to change without prior notice The product is subject to discontinuation without prior notice Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 8 inreviun 1 Related Documents and Accessories Related documents All inrevium documents relating to this board can be downloaded from our website Please see attached paper on the products Xilinx FPGA support documents may require Xilinx User registration to download htto www xilinx com support index html content xilinx en supportNav silicon devices foga artix 7 html DS180 7 Series FPGAs Overview DS181 Artix 7 FPGAs Data Sheet DC and AC Switching Characteristics DS874 ChipScope Integrated Bit Error Ratio Test IBERT for 7 Series GTP UG470 7 Series FPGAs Configuration User Guide UG471 7 Series FPGAs SelectlO Resources User Guide UG472 7 Series FPGAs Clocking Resources User Guide UG473 7
56. s clk adj clk p reference and system clock pll clock out2 set property IOSTANDARD DIFF SSTL15 get ports sysclk n sysclk pj set property PACKAGE PIN AE6 get ports sysclk clk n set property PACKAGE PIN AD6 get ports sysclk p 515338 pll clock in set property IOGTANDARD TMDS 33 get ports out cg n out cg pl set property PACKAGE PIN R7 get ports clk out cg n set property PACKAGE PIN R8 get ports out cg p 7 4 FMCHRIO Clocks The HR IO clocks are associated with the general logic lOs provided by the FPGA to FMC modules and fall into three categories module global M2C Module to Carrier bank associated CC bi directional and module global BIDIR bi directional BIDIR clocks are available since this board supports HPC type FMC connections Note that only FMC position 1 supports the BIDIR clocks and they are left unconnected on FMC position 2 Refer to FMC specification ANSI VITA 57 1 for more details regarding the application of the various clocks The HR IO clock signals are all directly DC connected from the FMC clock pins Users should ensure correct configuration of the clock input type and that terminations are enabled Users should also be aware that many FPGA HR IO modes are VCCIO VADJ dependent and must insure that the IO standard used can operate at the selected VADJ voltage Refer to Xilinx document UG471 7 Series SelectlO Resources User Guide for more information Th
57. tes that are compatible with this controller and can be set during the COM port configuration Table 7 11 UART Interface FPGA Bank 36 Pin Assignment USB UART TX USB UART USB _UART_RTS_N USB UART CTS Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviun 7 9 Battery Option The TB A7 200T IMG contains an optional not populated LR44 11 6 mm coin cell battery holder connected to the FPGA VBATT pin which serves as a battery backup supply for the FPGA s internal RAM that stores the key for AES decryption The coin cell an LR44 1 5V battery silver oxide or Alkaline cell provides the memory state retention power required The holder is not installed and is a factory option please contact our sales representative if you require this option Note that the battery holder outer metal cage connects to the positive pole of the battery and can be used as a probe TP to measure the voltage A series resistance not populated in the negative pole protects the cell from dead shorts however avoid touching the holder cage exposed metal with grounded metal objects such as grounded probe clips At maximum specified FPGA VBAT current the voltage drop across the protection resistor is 1 5mV VCCBAT 26 05 15 RvR BHX1 LR44 PC RETAINER BATT LR44 INSULATED TH DNS Figure 7 15 Battery Circuit The maximum battery current specified for the Artix 7 series is 150nA This calculates to 10 hours of backup using common Alkaline LR44 cells
58. ue E 51 7 12 JTAG and Pmod IMENICE cuna lala 51 7 12 1 JTAG CONMCCION uuu ull cider 51 1 dc ee ee 53 7 13 General Purpose User 8 54 7 14 General Purpose User Switches 56 AL a U 6 DI Wi HI c ee eee 56 rA User Push SWIGhGSR uuu lll UL cielo enslave 56 T SPDIE cc S u u ee 57 7 16 Fan MES UR T TTE EOS T mtem 58 SEE SAUNT Ili uu 59 9 Appendix EEPROM COMENTS cercarne nine e OE E 60 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED inreviunW List of Figures Figure 4 1 Block VAI AIM TET 12 Figure 5 1 TB A7 200T IMG Board View 13 Figure 6 1 Board Dimensions top 16 Figure 6 2 Board Dimensions bottom 17 Figure 7 1 Power Supply Structure c ccesseecceceescccesseeeeceeecscceeseeeeeeeecesccsseeeeeeeesenccesseseeeeesenes 18 Figure 7 2 Power Input Circuit a aa nnn nnn nnns nnn nnns nnn nnns 19 Figure 7 3 Input Power Protection Circuit
59. ult D Gren EemelED2 Adiiy 7 1 8 VADJ Voltage Selection The two FMC module positions on the TB A7 200T IMG can provide independently selectable VADJ voltage rails to the attached FMC modules These rails are selected by a pair of 2x3 2 54mm headers that accept a single standard 2 pin shorting shunt on each The shunts can select one of four voltages which are presented to their respective FMC module receptacles The voltages must be determined and shunts installed prior to power up of the TB A7 200T IMG board Since VADJ1 FMC position 1 is also used as the power rail for the BO bank of the FPGA protective measures are incorporated to ensure the FPGA is not damaged through accidental change or loss of shunts while the board is powered up following table outlines the banks powered by each of the two adjustable supplies Notes 1 The VADJ voltages must be set prior to applying power They must not be changed while the board is powered 2 The VADJ voltage is determined based on the needs of the FMC module and the respective FPGA bank Table 7 3 VADJ connected Banks VADJ Number Connected Banks Voltage VADJ1 BO B12 B13 14 1 5 1 8 2 5 3 3V VADJ2 B15 B16 Rev 2 04 TOKYO ELECTRON DEVICE LIMITED TB A7 200T IMG Hardware User Manual fi UI The Shunt voltage selection positions for both headers J40 J41 shown below 3 3V 25V 1 8V 1 5V 1 EN O L O 4 mu
60. use e These precautions contain serious safety instructions that must be followed e After reading through this manual be sure to always keep it handy The following conventions are used to indicate the possibility of injury damage and classify precautions if the product is handled incorrectly Indicates the high possibility of serious injury or death if the product is handled incorrectly Danger Indicates the possibility of serious injury or death if the product is handled Warning incorrectly Indicates the possibility of injury or physical damage in connection with houses or Caution household goods if the product is handled incorrectly The following graphical symbols are used to indicate and classify precautions in this manual Examples Turn off the power switch Do not disassemble the product Do not attempt this Rev 2 04 TOKYO ELECTRON DEVICE LIMITED 6 TB A7 200T IMG Hardware User Manual fi eV Rev 2 04 N Warning In the event of a failure disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately and contact our sales personnel for repair If an unpleasant smell or smoking occurs disconnect the power supply If the product is used as is a fire or electric shock may occur Disconnect the power supply immediately After verifying that no smoking is observed contact our sales personnel for repair Do not
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