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DT9840 Series User`s Manual

1. 66 duty cycle Rate Generation Rate Generation Operation Starts Operation Stops Figure 6 Example of Rate Generation Mode Principles of Operation Measure Use measure mode to measure the interval between a selected start edge and a selected stop edge of a signal connected to the external C T input pin or external gate input pin of the counter timer Refer to page 47 for more information on edge types and how to use them to measure frequency period and pulse width When you trigger the counter timer in software the counter increments from the time it detects the selected start edge until it detects the stop edge When it detects the selected stop edge the counter stops counting You can determine whether the measure mode operation is complete or not using software When the operation is complete you can read the value of the counter Use the following equations to determine the frequency period and pulse width of the signal Frequency 18 MHz Number of Counts e Period 1 Frequency Pulse width Number of Counts 18 MHz Note In measure mode the internal C T clock is used to calculate the interval of the signal between the specified start and stop edges The pulse width and period count are automatically set to 0 You can specify the polarity of the output signal during and after the measurement Figure 7 shows an example of how to measure the pulse width of a signal Ensure that th
2. Bit Register Description Value Type 26 Indicates whether the A D 1 A D converters are finished R W conversion is done A D Read converting the data This bit is clears cleared set to 0 automatically when the DSP reads the data This bit asserts EXT INT6 0 A D conversions are not finished 27 Indicates whether an A D 1 A D data was not read before the R W overrun error occurred next conversion was completed interrupt EXT_INT4 is asserted This bit must be cleared set to 0 by the DSP or host Conversions do not stop however the data may be corrupt 0 A D data was read before the next conversion was completed no error 28 Indicates whether A D and D A 1 Enables A D and D A interrupts R W interrupts are enabled This bit 0 Disables A D and D A interrupts is controlled by the DSP 29 Indicates whether an external 1 A D and D A conversion process R W trigger is used This bit is controlled by the DSP starts on the low to high transition on the Ext Trigger BNC 0 Software trigger is used Register Description Table 5 Hardware Control and Status Register Address 0xB0000000 cont Bit Register Description Value Type 30 Indicates that an external clock is used This bit is controlled by the DSP 1 A D and D A clock must be provided on the Ext Clock BNC This bit must be set to 1 on any slave modules For the DT9841 DT9841E
3. suus 25 Scan Loop Operations 6 00 eee k 20 Block Loop Operations sssssssseese 26 Contents List Loop Operations 00 eee eee 26 TELS BOTS eeneg erete p cens diet esate pany e 27 Scalable Bus oer eR RR daa RR ee ER ERES et ean as 29 LEDS rp TERES ep ee rg de teens 31 Analog Input Features 2 0 060 6 KK KK KK KK KK KK KK KK 32 Analog Input Channels WL KK KK KK KK 32 IEPE Funtsei oet eet em d ne t t kod al 33 Input Resolution u 2 p erei ep n n a e 34 Input Range and Gain 00 0 e KK KK KK KK 34 Data Format 5 8 xa k RR etn Mz GRE Tee de pagine 29 Data Transfer 0 0 0 0 cece ccna 35 Error Conditions 45e Aer Rer Re AR abba es 36 Analog Output Features 0 6 KK KK KK KK KK KK KK KK 37 Analog Output Channels LAL KK KK KK KK KK KS 37 Output Resolution lt sea k n e e dn os 38 Output Range and Gain KK KK KK KK KK 38 Output Filters uere re kann WE Pa d dk REC 38 Data Format ya s 524 0 a san de RR REP 4ha d la 39 Data Iransfer i c k da sala bana sk eee es PERS 39 Error Conditions 000 cee KK KK KK KK KK KK KK kk 40 Digital I O Features cies Re e a A W ek a 40 Digital I O Lines ies eye eek 40 Interrupt On Change sey H 5 x3 axx xd 4e m l dn kk eee eee 41 Counter Timer Features Wk k KK KK KK KK eee KK KK 42 C T Channels cete PERDU ces aliya atau 42 C T C
4. a All bits power up in the 0 state Typically these bits are controlled from the host through the host port interface Bits 26 and 27 control the termination multiplexer In differential mode any or all of the analog input Lo signals can be terminated with the 1 kQbias return resistor to the isolated analog common The termination function can be initiated independently from all other b functions On the DT9841 DT9841E and DT9841 VIB the frequency of the MCLK signal is multiplied by 512 and then divided by 2 the base frequency is 36 00 MHz For example if you specify a frequency of 100 KHz for the internal sample clock the MCLK signal 100 kHz is multiplied by 512 51 2 MHz and then divided by two 25 6 MHz synchronized to the CAL command of the serial input and buffered for output in the Spartan chip After the A D reset is released valid data is available in 1116 1 sample rate or 11 16 ms at 100 kHz Refer to the documentation for CY22150 for programming information the address of CY22150 is 0x69h 3 ms settling time required for the DLL The module has Xicor X9258US24 2 7 EE potentiometers to support software calibration of the A D subsystem All calibration is done in differential mode with all channels connected together and to analog common Data is continuously acquired at 50 kHz the results of the averaged conversions are printed to the display A low noise programmable voltage source similar to Ele
5. 06 103 Count Seguen eese occorre epe redak honed 4 Hu 105 Event Counting Equations sees 105 Output Period Frequency Equations 106 Output Pulse Width and Duty Cycle Equations 107 Counter Initialization W easan KK KK KK RR KK KK 108 MemoELy 5 2w d an nd dalal d e eee Hecan de aa Meade 110 Scalable Bus eme E menan absentee tetas 0000 EAR 113 Contents Chapter 3 Calibration 000 eee eee 119 Using the DT9841 Calibration Utility 0 121 Calibrating the Analog Input Subsystem 122 Connecting a Precision Voltage Source 122 Using the Auto Calibration Procedure 122 Using the Manual Calibration Procedure 124 Calibrating the Analog Output Subsystem 126 Appendix A Specifications 0005 129 Appendix B Connector Pin Assignments 145 DT9841 DT9842 2 and DT9842 8 Modules 146 DT9841E Module sese 157 Sleek Box Front Panel 0000 c KK KK KK KK eee 167 EP358E Accessory Panel L LL 0000 eee eee 172 Index uu HESS hag PREISE ERE RITU REE ERE 7 About this Manual This manual describes the hardware features of the DT9840 Series modules Intended Audience This document is intended for engineers scientists technicians or others responsible for using and or programming the DT9840 Series modules
6. and Trigger Minds D A Serial The DT9841 VIB Data 8 has 16 digital I O gt s lines c 8 Ch D Clock ES 8 E Data A Y nee 2or8 lt Q Jo 5 a 2 lt q fe x g Z2 Z2 a 2or 24 Bit heban 0 S S g 8 S 5 m E Delta Sigma Bess 5 e 3 E 5 Q g SZ or 8 16 Bit Successive Approximation A Ds 32 M x 32 L2 Memory 9 SDRAM DSP 256 KBytes INT 7 SB A A Flash RAM FIFO ee INT 4 occurs with A Y Trig Ctr Over Dig JTAG 16 bit Scalable Bus 16 bit Scalable Bus Mb DERI Serial Port 1 McBSP The DT9841 and DT9841 VIB features 8 24 bit A Ds and 2 24 bit DACs The DT9841E features 2 24 bit A Ds and 2 24 bit DACs The DT9842 2 features 8 16 bit A Ds and 2 16 bit DACs This is serial on the DT9841 DT9841E and DT9841 VIB and parallel on the DT9842 2 and DT9842 8 Figure 1 Block Diagram of the DT9840 Series Modules 16 Principles of Operation System Features The DT9840 Series modules provide the following system level features Memory described below Clock sources described on page 18 Conversion modes described on page 22 Triggers described on page 27 Connections for multiple modules described on page 29 LEDs described on page 31 Memory All DT9840 Series modules provide 128 MB of onboard SDRAM and 2 MB of flash memory Flash memory is divided into two sections a single 64 KB block is reserved for user data the remaining memory 2 MB 64 K
7. 1024 LSBs 0 01 Differential linearity 64 LSBs 1 LSB Zero error Software adjustable to Software adjustable to zero zero Gain error 2048 LSBs 2 LSBs Output ranges 10 V and 2 5 V bipolar 10 V bipolar Throughput full scale 100 kHz 100 kHz Current output 5 mA minimum 10 V 2 KO 5 mA minimum 10 V 2 kQ Output impedance 0 3 Q typical 0 3 Q typical Capacitive drive capability 0 001 uF minimum no oscillations 0 001 uF minimum no oscillations Protection Short circuit to analog common Short circuit to analog common Power on voltage 0 V 10 mV maximum 0 V 10 mV maximum Specifications Table 4 Analog Output Subsystem Specifications cont DT9841 DT9841E and DT9841 VIB Feature Specifications DT9842 Specifications Settling time to 0 01 of FSR 10 us 20 V step 10 us 20 V step filtering off Total harmonic distortion 94 dB 88 dB Glitch area 10 nV Seconds typical Slew rate 5 V us 5 V us Group delay 34 conversion 340 us 100 kHz _ rate Passband 0 454 x Throughput Stopband 0 546 x Throughput Pass band ripple 0 002 dB Software selectable 4 pole 20 kHz or 5 kHz filter FIFO DSP memory DSP memory 135 Appendix A Table 5 lists the specifications for the digital input subsystem Table 5 Digital Input Subsystem Specifications
8. 36 Principles of Operation Analog Output Features io This section describes the following features specific to the analog output D A subsystem e Analog output channels described below Output resolution described on page 38 Output range and gain described on page 38 Output filters described on page 38 Data format described on page 39 Data transfer described on page 39 Error conditions described on page 40 Analog Output Channels The DT9841 DT9841E DT9841 VIB and DT9842 2 modules support two analog output channels 0 and 1 that are simultaneously clocked The DT9842 8 module supports eight analog output channels 0 to 7 On the DT9841 DT9841E and DT9841 VIB modules these analog output channels use Delta Sigma digital to analog converters DACs that provide anti aliasing filters based on the clock rate to reduce noise On the DT9842 2 and DT9842 8 these analog output channels use successive approximation DACs no filtering is supported Within each DAC the digital data is double buffered to prevent spurious outputs before it is output as an analog signal Both DACs power up to a value of 0 V 10 mV Resetting the module does not clear the values in the DACs Refer to the DT9840 Series Getting Started Manual for information on how to wire analog output signals to the module 37 Chapter 1 Output Resolution The output resolution of the DT9841 DT9841E and DT9841 VIB modules is
9. Feature Specifications Number of lines For DT9841 VIB 16 Ports 0 and 1 each consisting of 8 programmable digital I O lines For all other DT9840 Series modules 24 Ports 0 1 and 2 each consisting of 8 programmable digital I O lines Termination 22 kQ pull up series 22 Q Input type HCT 5 V tolerant Yes Input load 22 kQ pull up to 3 3 V Inputs Input type Level sensitive Input load 1 HCT High level input voltage 2 4 V minimum Low level input voltage 0 8 V maximum High level input current 0 uA Low level input current 0 2 mA Back EMF diodes Yes a When port 0 is configured for digital input you can configure the software to interrupt the host computer whenever any of the bits changes state In addition to reduce noise and minimize false state changes you can enable a 10 ms deglitch function for port 0 when it is configured for digital input 136 Specifications Table 6 lists the specifications for the digital output subsystem Table 6 Digital Output Subsystem Specifications Feature Specifications Number of lines For DT9841 VIB 16 Ports 0 and 1 each consisting of 8 programmable digital I O lines For all other DT9840 Series modules 24 Ports 0 1 and 2 each consisting of 8 programmable digital I O lines Termination 22 kQ pull up series 22 Q Outputs Output driver CMOS Output driver high voltage 22 kQ pull up to 3 3 V Output driv
10. For example if you specify an internal clock frequency of 100 kHz internally the module sets the oscillator to 51 2 MHz then divides the resulting signal by 2 to provide a 25 6 MHz signal with a 50 duty cycle to the A D and D A converters In addition if you specify a sampling frequency between 200 Hz and 5 kHz the DT9841 DT9841E and DT9841 VIB modules automatically filter the data using decimation and interpolation filters Refer to the DT9840 Series DSP Library User s Manual for more information on how these filters are implemented 19 Chapter 1 20 Once the sample clock is started the DT9841 DT9841E and DT9841 VIB modules require 37 clock pulses before the first conversion is completed at 100 kHz this delay is 370 us Thereafter the data is converted without delay at 100 kHz sampling occurs every 10 us This initial delay is required by the filtering algorithms of the A D and D A converters DT9842 2 and DT9842 8 Internal Clock Because the DT9842 2 and DT9842 8 use successive approximation A D converters and provides no inherent filtering no initial delay occurs like on the DT9841 DT9841E and DT9841 VIB Therefore the converter always runs as fast as possible at 100 kHz sampling occurs every 10 us Internally the DT9842 2 and DT9842 8 hardware divides the 18 MHz time base by a 32 bit value to achieve the closest rate to the sampling rate you requested External Clock An external clock is use
11. J6 Pin Assignments Pin Signal Name Cable Wire 1 45V USB Red 2 USB D White 3 USB D Green 4 AGND1 Black a This signal is not used USB connector is type B Connector Pin Assignments Table 17 Power Input Connector J11 Pin Assignments Pin Signal Description 1 5 V Input 6A 2 5 V Input 6 A 3 Isolated Power Ground 4 Isolated Power Ground a You must consider the wire size and length before connecting power to connector J11 The module requirement is 5 V 0 25 V at the connector with less than 50 mV pp of ripple The power supply must also be isolated from the computer or from the power commons up to 500 V minimum Table 18 Scalable Bus Connectors J12 and J13 Pin Assignments Pin Signal Description Pin Signal Description 2 SBO 1 SBO Return 4 SB1 3 SB1 Return 6 SB2 5 SB2 Return 8 SB3 7 SB3 Return 10 SB4 9 SB4_Return 12 SB5 11 SB5_ Return 14 SB6 13 SB6 Return 16 SB7 15 SB7_ Return 18 SB8 17 SB8_Return 20 SB9 19 SB9_Return 22 SB10 21 SB10 Return 24 SB11 23 SB11 Return 151 Appendix B 152 Table 18 Scalable Bus Connectors J12 and J13 Pin Assignments cont Pin Signal Description Pin Signal Description 26 SB12 25 SB12 Return 28 SB13 27 SB13 Return 30 SB14 29 SB14 Return 32 SB15 31 SB15 Return 34 SB Strobe 33 SB Strobe Return 36
12. counter timer reset measurement It is also cleared when the host writes 0 to the user measure trigger enable command bit of the control register 7 Reserved 2 31 8 Reserved 102 Register Description Counter Timer Operation Modes The following software selectable modes are provided for each user counter timer Retriggerable one shot In retriggerable one shot mode an external gate rising or falling edge or a transition from software logic low to software logic high can be used to trigger a pulse output signal When the gate is active the counter begins incrementing When the counter increments to the value specified in the pulse register the user output is activated The user output stays active until the counter increments to the terminal count The user output is then deactivated and the counter is automatically reloaded with the initial count which is specified in the period register The user output then stays inactive and the counter stays disabled until the next active gate signal Note that all gates that occur while the counter is incrementing are ignored The active polarity of the user output is software selectable Non retriggerable one shot Non retriggerable one shot mode is the same as retriggerable one shot mode with the following exception when the counter reaches the terminal count the module clears the one shot trigger enable bit The module ignores subsequent gate signals un
13. 0 0 Disables the 10 ms deglitch function on digital port 0 21 Indicates whether Digital Port 1 Enables the interrupt on change R W Register Description Table 5 Hardware Control and Status Register Address 0xB0000000 cont Bit Register Description Value Type 22 For the DT9841 DT9841E Bit 23 Bit 22 R W 23 and DT9841 VIB indicates 0 0 Switches ON the 4 pole whether D A filters or 0 V 5 kHz filters for both outputs are used D A outputs 0 1 Switches ON the 4 pole For the DT9842 2 and 20 kHz filters for both DT9842 8 these bits are D A outputs reserved 1 0 Passes the D A data out without filtering 1 1 Sends 0 V out 24 Indicates that the D A data is 1 D A ready for new data R ready D A Write clears Data is clocked out of the data register This bit is cleared set to 0 automatically when new D A data is loaded into the data register 0 D A converting data 25d Indicates whether a D A 1 New data has not been loaded R W underrun error occurred into the two D A data registers before the next clock pulse interrupt EXT_INT4 is asserted This bit must be cleared by the DSP or the host Conversions do not stop however the data may be corrupt 0 New data has been loaded into the two D A data registers before the next sample clock no error 71 Chapter 2 72 Table 5 Hardware Control and Status Register Address 0xB0000000 cont
14. 0 R W 0xB000C004 User Period Register 1 Counter 1 R W 0xB000C008 User Period Register 2 Counter 1 R W 0xB000C00C Reserved 0xB000C010 User Pulse Register 0 W 0xB000C014 User Pulse Register 1 W 0xB000C018 User Pulse Register 2 W 0xB000C01C Reserved 0xB000C020 User Control 0 W 0xB000C024 User Control 1 W 0xB000C028 User Control 2 W 0xB000C02C Reserved 0xB000C030 Counter Timer Status R 111 Chapter 2 Table 15 Memory Space Address Map cont Address Register Description Type 0xB0010000 Digital Port 0 INT Mask Register R W Right Justified Data 0xB0010004 Digital Data Port 0 Right Justified Data R W 0xB0010008 Digital Data Port 1 Right Justified Data R W 0xB001000C Digital Data Port 2 Right Justified Data R W 0xB0014000 SB Control amp Address Register CE3 R W 0xA0000000 16 Bit SB Data Register CE2 20 ns set up W for 2 cycles 0xA0000004 16 Bit SB Data Register CE2 20 ns R ECLKIN 2 a Refer to the DT9840 Series DSP Library User s Manual for more information on the CDB file b For the DT9841 VIB module bit 0 of digital port 2 is used as the SCL clock and bit 1 of digital port 2 is used as the SDA data output the remaining bits 2 7 of digital port 2 are reserved See page 75 for more information c This register contains eight debug LEDs that are right hand justified Debug LEDs are not supported on the DT9841E Bits 0 DO through 7
15. 15 contain the data locations for the Ww Data Scalable Bus The master module writes to address Address OxAO000A000 on the selected slave with a 40 0 ns delay between writes ECLKIN divided by 2 2 setup After 512 16 bit words are written the FIFO half full flag on the addressed slave asserts interrupt EXT_INT7 for a 512 sample transfer to memory using DMA channel 7 When the module address is removed indicating that the transfer is done the slave module checks the FIFO not empty flag to complete the data transfer 0xA0000004 Read Once the Enable bit is set the selected slave can R Data write to the master through the Scalable Bus in the Address same manor as the master writes to the slave The only exception is that the first data point is the number of samples in the data file to be transferred If the slave module needs to send data to the master it asserts DONE L which asserts interrupt EXT INTA4 The master then queries each slave for the request When the slave module is addressed the first data point is the number of samples in the data file to be transferred The data is then written from the slave to the master If the selected slave did not request the bus then all zeros are placed in the bus 117 Chapter 2 118 Calibration Using the DT9841 Calibration Utility 121 Calibrating the Analog Input Subsystem 122 Calibrating the Analog Output S
16. 165 DT9842 2 151 156 DT9842 8 151 156 Index J12 connector pin assignments 147 168 DT9841 151 J13 connector pin assignments 147 168 DT9841 151 DT9842 2 151 DT9842 8 151 J15 connector pin assignments 147 J16 connector pin assignments 147 J17 connector pin assignments 147 DT9841 153 DT9842 2 153 DT9842 8 153 J18 connector pin assignments 148 DT9841 155 DT9842 2 155 DT9842 8 155 J19 connector pin assignments 148 167 172 Sleek Box 171 J2 connector pin assignments 146 157 167 172 DT9841 148 DT9841E 162 DT9842 2 148 DT9842 8 148 Sleek Box 169 J201 connector pin assignments 172 174 J202 connector pin assignments 172 173 J3 connector pin assignments 146 157 DT9841 149 DT9841E 163 DT9842 2 149 DT9842 8 149 J4 connector pin assignments 146 157 168 DT9841 149 DT9841E 164 DT9842 2 149 DT9842 8 149 J6 connector pin assignments 146 158 168 DT9841 150 DT9841E 165 DT9842 2 150 DT9842 8 150 JTAG connector 146 157 DT9841 149 DT9841E 163 DT9842 2 149 DT9842 8 149 L LEDs address 74 116 CR1 31 74 CR10 31 74 CR11 31 74 CR12 31 74 CR13 31 74 CR14 31 74 CR15 74 116 CR6 31 74 CR7 31 74 CR8 31 74 CR9 31 74 debug 31 112 level gate type high 45 low 46 181 Index 182 logic high level gate type 45 logic low level gate type 46 low to high pulse output 49 M master module 29 measure mode 55 measuring frequency 55 56 measuring period 55 measuring pulse width 55 m
17. 9 DSP TCK 10 DGND 11 DSP TCK 12 DGND 13 DSP_EMUO 14 DSP_EMU1 Table 15 Serial Port Connector J4 Pin Assignments McBSP Internal Pull J4 Signal McBSP McBSP Up or Pull Pin Name Signal Description Pin Function Down 1 CLKS1 External Clock E1 Input Internal Pull Source Down 2 DR1 Receive Data M2 Input Internal Pull Up 3 DX1 Transmit Data L2 Output Internal Pull Tristate Up 4 CLKR1 Receive Clock M1 Input Output Internal Pull Tristate Down 5 Isolated Ground Common 6 CLKX1 Transmit Clock L3 Input Output Internal Pull Tristate Down 149 Appendix B Table 15 Serial Port Connector J4 Pin Assignments cont McBSP Internal Pull J4 Signal McBSP McBSP Up or Pull Pin Name Signal Description Pin Function Down 7 FSX1 Transmit Frame L1 Input Output Internal Pull Sync Tristate Down 8 FSR1 Receive Frame Sync M3 Input Output Internal Pull Tristate Down 9 5 V PWR 45 V 25 mA I maximum a If you want to access this port for debugging purposes it is recommended that you use the EP354 serial adapter and EP335 serial cable refer to the DT9840 Series Getting Started Manual for connection information and to the DT9840 Series DSP Library User s Manual for information on the serial debugging functions If you want to program this serial port refer to the data sheet for the TMS320C6713 from Texas Instruments for more information 150 Table 16 USB Connector
18. Control register described in Table 16 is used to control the operation of the Scalable Bus 113 Chapter 2 Table 16 SB Control Register Address 0xB0014000 Bit Register Description Type 0 to 22 These are the slave addresses for modules 1 through 7 RAN For slaves set these bits to a unique address for the module For the master set these bits to 000 3 1 The module is the master determined at initial setup R W The master determines if each slave module is reading from or writing to the Scalable Bus 0 The module is a slave 4 1 Broadcast mode In broadcast mode the master writes R W to all slaves 0 Broadcast mode is not used 5 1 The master writes to the selected address with a R W 40 0 ns delay between writes Refer to CE2 described on page 112 The 40 ns delay is implemented using two cycles in the write setup 0 A read operation is performed Slaves are read only devices 6 Reserved ni 7b 1 Enable transfer request Ack Out acknowledge R W strobe After the modules are set up the enable is asserted 200 ns later to deglitch the setup operation The Scalable Bus is now activated and data can be transferred at full bus rates When the master finishes reading a single word of Transfer Request it generates a pulse on this line write bit to 1 then 0 Slaves are read only devices 0 Disable transfer request acknowledge strobe 114 Regist
19. D code on the proper code Data must also be averaged for maximum reliability It is suggested a minimum of 16 values be taken for the averaging routine To calibrate the A D converters on the DT9841 DT9841E and DT9841 VIB do the following 4 Setthe A D converters to 0 by applying 0 00000 volts on all channels and adjust the potentiometer on each A D channel for a code of 00000000h Refer to Table 7 on page 79 for the address of each potentiometer 5 Set the full scale range by applying 9 37500 V on each channel and adjust the potentiometer on each A D channel for a code of 2013265664 or 77FFFFO00h 82 Register Description To calibrate the A D converters on the DT9842 2 and DT9842 8 do the following 1 Set the A D converters to 0 by applying 0 00000 volts on all channels and adjust the potentiometer on each A D channel for a code of 00000000h Refer to Table 7 on page 79 for the address of each potentiometer 2 Set the full scale range by applying 9 37500 V on each channel and adjust the potentiometer on each A D channel for a code of 63488 or F8000000h To store the A D calibration transfer the contents of PO through P3 to their respective RO through R3 registers This is a nonvolatile write operation and require 10 ms before any other operation When the module powers up the values in the RO locations are automatically moved to the WCR location placing the calibration values on the outputs The value stored i
20. DT9841 VIB the D A data must always be output as two 32 bit words channel 0 then channel 1 The data is clocked into the internal serial output register on the second word address The initial value must be the code for 0 V output to preventing glitching after power up On the DT9842 2 and DT9842 8 the D A data is output only when the corresponding register in the Spartan chip is written Bits 23 and 22 of the Hardware and Control Status register described in Table 5 on page 67 must be set to 1 on power up The digital output address follows the D A address so that it can be included in the DMA list Bit 25 of the Hardware and Control Status register described in Table 5 on page 67 is set if the data in the input latch has not been updated on the next D A clock This will be 10 us at the fastest clock rate The error bit must be cleared by the host 91 Chapter 2 Table 9 describes the D A data address map Table 11 D A Data Address Map Address Register Description Type 0xB0008000 D A Data 0 above physical memory w 0xB0008004 D A Data 1 above physical memory W 0xB0008008 Reserved zeros digital port 22 digital W port 1 digital port 0 a For the DT9841 VIB module bit 0 of digital port 2 is used as the SCL clock and bit 1 of digital port 2 is used as the SDA data output the remaining bits 2 7 of digital port 2 are reserved See page 75 for more information 92 Register Descri
21. Isolated Common 35 Isolated Common 38 Module Address Select 0 37 Module Address Select 1 40 Module Address Select 2 39 Module Address Select 3 42 Broadcast 41 SB Enable 44 SB Read Write L 43 Done L 46 Master Serial Port 0 Data 45 Master Serial Port 0 Clock 48 Left Right Clock 47 Isolated Common 50 Master ADClock 49 Master A D Clock L a The Scalable Bus connectors are set up for intermodule communication at speeds up to 50 MBytes s maximum software rate is 13 MBytes s The first and last modules must use software selectable 100 Q termination resistors The data can be clocked out every 40 ns The negative strobe pulse must be 12 ns minimum with the data valid for 10 ns before the rising edge The hold time is 0 ns Connector Pin Assignments Table 19 Analog Output Digital I O and Counter Timer Connector J17 Pin Assignments Pin Signal Description Pin Signal Description 34 Analog Output 00 68 Analog Output 00 Return 33 Analog Output 01 67 Analog Output 01 Return 32 Analog Output 022 66 Analog Output 02 Return 31 Analog Output 032 65 Analog Output 03 Return 30 Analog Output 042 64 Analog Output 04 Return 29 Analog Output 052 63 Analog Output 05 Return 28 Analog Output 062 62 Analog Output 06 Return 27 Analog Output 072 61 Analog Output 07 Return 26 External D A Trigger 60 Isolated Digital Ground 25 External D A Clock 59 I
22. Note The edge type applies only to measure mode and continuous measure mode operations When measure mode described on page 55 or continuous measure mode described on page 56 is selected you must specify the edge of the signal that starts and stops the measurement In measure mode the counter increments from the specified start edge to the specified stop edge In continuous measure mode the counter increments from the specified start edge to the next start edge DT9840 Series modules provide the following edge types Rising edge external gate input In measure mode starts or stops the measurement when the signal connected to the external gate input pin goes from low to high rising edge In continuous measure mode starts the measurement when the signal connected to the external gate input goes from low to high rising edge the measurement stops on the next rising edge of the gate signal Falling edge external gate input In measure mode starts or stops the measurement when the signal connected to the external gate input pin goes from high to low falling edge In continuous measure mode starts the measurement when the signal connected to the external gate input goes from high to low falling edge the measurement stops on the next falling edge of the gate signal Rising edge external clock input In measure mode starts or stops the measurement when the signal connected to the external C T clock input p
23. Operation Up Down Counting Use up down counting mode if you want to increment the counter when the specified external gate signal is enabled and decrement the counter when the specified external gate signal is disabled This mode is useful when monitoring the position of an object such as a lift on a shaker table that can move in two directions When using a normal gate type the counter timer is incremented when the gate signal is high and decremented when the gate signal is low If you are using an inverted gate signal the counter timer is incremented when the gate signal is low and decremented when the gate signal is high Note This mode should be used only when the position of the object being monitored stays within the range of the counter since the operation is not be reliable if the counter increments above FFFFFFFh or decrements below 0 You can read the value of the counter at any time using software To use this mode specify an external C T clock source and either a normal or inverted external gate type Refer to page 43 for more information on the external C T clock source refer to page 45 for more information on gate types Figure 5 shows an example of an up down counting operation Ensure that the signals are wired appropriately Refer to the DT9840 Series Getting Started Manual for wiring examples 59 Chapter 1 60 High level count
24. Status register 0 Counter timer 0 has not overflowed 28 1 A FIFO Full Error occurred on the Scalable Bus 0 A FIFO Full Error did not occur on the Scalable Bus 29 1 A D A trigger occurred 0 A D A trigger did not occur 30 1 An A D trigger error occurred 0 An A D trigger error did not occur 31 1 An A D trigger occurred 0 An A D trigger did not occur 89 Chapter 2 Analog Output Subsystem The DT9841 DT9841E and DT9841 VIB support two 24 bit analog output channels The major components of the analog output subsystem are the DACs parallel to serial shifter and the 20 kHz and 5 kHz output filters The DT9842 2 supports two 16 bit analog output channels and the DT9842 8 supports eight 16 bit analog output channels The major components of the analog output subsystem are the DACs no filtering is supported The clock and trigger are the same as the analog input subsystem described on page 85 Updating the DACs is a multistep process The DSP must first write a value to the Spartan chip the Spartan chip then performs a parallel to serial conversion shifting the clocked data out to the appropriate DAC The digital data is double buffered within each DAC to prevent spurious outputs Data in the second register stage of the DAC is output as an analog signal Upon power up both DACs are initialized to 0 V by the hardware Note that a system reset does not change the value in either register
25. The BNC labelled TTL Trigger is provided for attaching an external trigger signal Analog In Out Connector J1 A 37 pin connector provided for attaching analog I O signals Refer to Table 31 on page 168 for more information on this connector Digital In Out Connector J2 A 37 pin connector provided for attaching digital I O signals Refer to Table 32 on page 169 for more information on this connector e Counter Timer Connector J19 A 25 pin connector provided for attaching counter timer signals Refer to Table 33 on page 171 for more information on this connector Screw terminal block A screw terminal block is provided for attaching an external 5 V power output signal Table 22 on page 157 for more information on this screw terminal block 167 Appendix B The back panel of the Sleek Box provides these connectors Scalable Bus Connectors J12 and J13 Refer to Table 18 on page 151 for the pin assignments of these connectors Serial Port J4 Refer to Table 15 on page 149 for the pin assignments of this connector 5 V Power Input Connector J11 Refer to Table 17 on page 151 for the pin assignments of this connector USB connector J6 Refer to Table 16 on page 150 for the pin assignments of this connector Table 31 Analog In Out Connector J1 Pin Assignments on the Sleek Box J1 Pin J1 Pin Assignment Signal Description Assig
26. Timer Subsystem cco 2 3 55002 dees d ku e eae es 94 5r 0 EE 110 Scalable Bus i eise e kala k RR eere ewes 113 65 Chapter 2 66 This section describes the registers that are used to program the DT9840 Series modules Note that the following designations are used for the register types e R Read e W Write e R W Read and Write All addresses discussed are in hexadecimal notation Register Description USB Bus DSP Hardware Interface Communication between the USB and DSP through the isolation barrier uses the 16 bit host port interface of the Texas Instruments TMS320C6713 DSP processor Note that a 100 ns delay is required to pass data through the isolators Refer to the DT9840 Series DSP Library Reference Manual for more information on programming the DSP The Hardware Control and Status register described in Table 5 is located at address OxB0000000 Table 5 Hardware Control and Status Register Address 0xB0000000 Bit Register Description Value Type 0 Indicates whether power is ok 1 All power supplies are correct R W 0 Power supplies are not correct 1 Indicates whether the USB 1 USB cable is connected R W cable was disconnected EXT_INT4 is connected disconnected asserted Set this bit to 0 to clear it See also bit 17 of the Calibration register 0 USB cable was not connected disconnected 2 Indicates whether a 1 A low to high transition was R W low
27. addressed or unaddressed unaddressed EXT_INT4 is asserted 0 No Scalable Bus activity 69 Chapter 2 70 Table 5 Hardware Control and Status Register Address 0xB0000000 cont 0 is enabled for EXT_INT4 function for EXT_INT4 0 Disables the interrupt on change function for EXT_INT4 Bit Register Description Value Type 13 Indicates whether the digital 1 The data of digital port 0 has R port 0 changed state changed 0 The data of digital port 0 has not changed 14 Indicates whether interrupt 1 Enables the external trigger to R W EXT_INT4 is asserted by the assert EXT_INT4 external trigger 0 Disables the assertion of EXT_INT4 by the external trigger 15 Reserved 0 R 16 Indicates whether to reset the 1 Normal operation R W A D and D A subsystems 0 Resets the A D and D A The A D and D A should be reset each time the sample clock is changed 17 Indicates whether digital port 2 1 Port 2 is an output port R W is enabled for input or output 0 Port 2 is an input port 18 Indicates whether digital port 1 1 Port 1 is an output port RAN is enabled for input or output 0 Port 1 is an input port 19 Indicates whether digital 0 is 1 Port 0 is an output port R W enabled for input or output 0 Port 0 is an input port 20 Indicates whether a deglitch 1 Enables a 10 ms deglitch R W function is used on digital function on digital port 0 port
28. and DT9841 VIB the frequency of of the external clock source that is used must be 256 times the required sampling frequency For example if the required sampling frequency is 100 kHz use an external clock source with a frequency of 25 6 MHz 0 The internal clock is used R W 31 Indicates where the clock and trigger signals come from This bit is controlled by the DSP 1 The module receives all A D and D A clocks and triggers from the scalable bus The internal DSP and counter timers operate on their own independent clock This setting is used for slave modules 0 The module receives all A D and D A clocks and triggers from its own inputs not from the scalable bus This setting is typically used by the master module only R W a All bits power up in the 0 state When all the power supplies are correct bit 0 switches to 1 indicating the module is ready for use b This mode is currently not supported in software 73 Chapter 2 74 c A two color LED CR6 on the DT9841E module CR1 on all other modules is visible from the back of the module When power is applied to the module this LED turns green When the module is recognized by the host and the firmware is downloaded to the module the LED turns red When the Windows driver is loaded and started the LED turns orange When you download and run your DSP program this LED flashes green and orange When you download and
29. and DT9841 VIB data to the D A MDI line For the DT9842 2 and DT9842 8 this bit is reserved For the DT9841 DT9841E and DT9841 VIB clock for the D A MC line For the DT9842 2 and DT9842 8 this bit is reserved R W R W 24 For the DT9841 DT9841E and DT9841 VIB select for the D A ML line For the DT9842 2 and DT9842 8 this bit is reserved R W 25 When 1 enables the Scalable Bus 100 Q termination resistors write to address OXBOO0000C When 0 disables the Scalable Bus 100 Q termination resistors R W 26 Data bit for the chip that controls the 1 KQ termination resistors on the A D inputs see bits 20 and 27 R W 27 Serial clock for the chip that controls the 1 kQ termination resistors on the A D inputs see bits 20 and 26 R W 28 Data bit for the programmable clock chip CY data R W 76 Register Description Table 6 Calibration and Setup Register Address 0xB0000004 cont Bit Register Description Type 29 Clocks the serial port of the CY clock address 69h R W 30 Data output bit for the Xicor potentiometers see bit R W 31 When 1 the pin is in tristate so that the data can be read at bit 19 write to address OxBOOO000C 31 Clocks the serial port of the Xicor Xicor X9258WS R W potentiometers that are used for calibrating the zero and full scale values of the A Ds and D As write to address 0xB000000C
30. before the first analog input conversion is completed the first 37 analog samples that are acquired after the trigger are actually pre trigger samples The 38th sample corresponds to the first data point after the trigger Digital input and counter timer data is always acquired immediately after the trigger and is not delayed by 37 samples Since the DT9842 2 and DT9842 8 do not have a group delay the samples acquired after the trigger correspond directly to the data that was acquired Triggers are ignored for single value operations and single scan operations These operations are performed immediately after the functions are executed Scalable Bus Note The Scalable Bus is not supported by DT9841E modules The architecture of the DT9840 Series supports connecting up to eight modules together through the Scalable Bus one of the modules is the master and the remaining modules are slaves This connection scheme allows you to synchronize the operation of all modules at the frequency of the master clock source or to communicate with multiple modules that are operating asynchronously from each other The modules connect together using EP342 cables and the 50 pin Scalable Bus connectors J12 and J13 Refer to the DT9840 Series Getting Started Manual for more information on connecting modules using the Scalable Bus connectors 29 Chapter 1 30 Using the DT9840 Series Control Panel application you must enable the Sc
31. controls the sampling rate of both the A D and D A converters The value of this register divides the onboard 18 MHz sample clock oscillator The default value of this register at system reset and the maximum value that this register should be set to is 180 0xB4 this value results in a maximum sampling rate of 100 kSamples s Using bit 30 of the Hardware and Control Status register described in Table 5 on page 67 you can select either an internal or external clock source MCLK is programmed using bits 28 and 29 of the Calibration and Setup register described in Table 6 on page 75 When the external clock is selected conversion begin on the high to low transition after a rising edge of the internal CAL signal 85 Chapter 2 86 On the DT9841 and DT9841E any or all of the analog input low signals can be terminated with a 1 kQbias return resistor to the isolated analog common Bits 20 26 and 27 of the Calibration and Setup register described in Table 6 on page 75 control the termination multiplexer The termination function can be initiated independently from all other functions To initialize the A D subsystem on the DT9841 DT9841E or DT9841 VIB serial port 0 TI PCM1804 is used in SPI mode and the A Ds are set up for control port mode Oversampling mode is 64x with a data width of 24 bits and twos complement data encoding high pass filtering is defeated Note that this serial port is also used to synchronize up to se
32. fixed at 24 bits The output resolution of the DT9842 2 and DT9842 8 modules is fixed at 16 bits Output Range and Gain Each analog output channel on a DT9841 DT9841E or DT9841 VIB module can output bipolar analog output signals in the range of 10 V or 2 5 V The output range is software selectable The gain is fixed at 1 The DT9842 2 and DT9842 8 modules support an output range of 10 V only Output Filters Note Output filters are supported on the DT9841 DT9841E and DT9841 VIB modules only Each analog output channel on the DT9841 DT9841E or DT9841 VIB supports a software selectable four pole 5 kHz filter or a four pole 20 KHz filter Both are Bessel filters and are useful if you want to smooth the analog output values For fast clock rates it is recommended that you use the 20 kHz filter For slow clock rates it is recommended that you use the 5 kHz filter On power up or reset no filter is used 38 Principles of Operation Data Format The analog output data encoding used by the DT9841 DT9841E an DT9841 VIB modules is floating point The data is 32 bit wide and left justified the right eight bits are filled with zeros The DT9842 2 and DT9842 8 modules use twos complement data encoding The data is 32 bit wide and left justified the right 16 bits are filled with zeros You can use software to convert a voltage value into a twos complement code Data Transfer The module packs 32 bits into e
33. for more information on this connector Digital In Out Connector J2 A 37 pin connector provided for attaching digital I O signals Refer to Table 32 on page 169 for more information on this connector Counter Timer Connector J19 A 25 pin connector provided for attaching counter timer signals Refer to Table 33 on page 171 for more information on this connector The back of the EP358E accessory panel provides these connectors e J202 Connector 68 pin connector for connecting the EP358E accessory panel to the J2 connector of the DT9841E module This connector brings out all the analog input signals from the module to the accessory panel e J201 Connector 68 pin connector for connecting the EP358E accessory panel to the J1 connector of the DT9841E module This connector brings out all of the analog output digital I O and counter timer signals as well as an external clock and external trigger input signals from the module to the accessory panel Connector Pin Assignments Table 34 Pin Assignments for Connector J202 on the EP358E Accessory Panel Pin Signal Description Pin Signal Description 1 5 V Isolated Output 2 Amp Low 3 Reserved 4 Reserved 5 Reserved 6 Reserved 7 Reserved 8 Reserved 9 Reserved 10 Reserved 11 Reserved 12 Reserved 13 Reserved 14 Reserved 15 Reserved 16 Reserved 17 Reserved 18 Reserved 19 Reserved 20 Reserved 21 Reserved 2
34. must also be isolated from the computer or from the power commons up to 500 V minimum 165 Appendix B Table 29 Secondary Power Connector TB2 Screw Terminal Assignments on the DT9841E Screw Terminal Signal Name 1 5 V Input 2 Ground 3 Chassis Ground Table 30 Fan Output Connector TB3 Screw Terminal Assignments on the DT9841E Screw Terminal Signal Name 1 Fan 2 Fan a These signals are provided for attaching an external 5 VDC 100 mA fan output signal The fan will turn on with an onboard temperature sensor if the DT9840 Series module exceeds 45 C If the module exceeds 60 C an interrupt is generated The following fan is recommended Sunon model number KDE0505PFB3 8GN or Data Translation part number 19372 166 Connector Pin Assignments Sleek Box Front Panel The following connectors are provided on the front panel of the Sleek Box BNC connectors BNCs labelled AD Ch0 to AD Ch7 are provided for attaching eight analog input signals The BNCs are wired on the box to reflect the channel configuration single ended or differential of your module On the DT9841 and DT9842 2 Sleek Box BNCs labelled DAC Ch0 to DAC Ch3 are provided for attaching four analog output signals On the DT9842 8 BNCs labelled DAC Ch0 to DAC Ch7 are provided for attaching eight analog output signals The BNC labelled TTL Clock is provided for attaching an external clock signal
35. run your DSP program this LED flashes green and orange If the downloaded program stops running this LED turns stops flashing in either the green or orange state to indicate that an error occurred and the debug LEDs CR7 to CR14 turn on You can define the state of the debug LEDs using software Four address LEDs CR15 indicate the Scalable Bus address position M is the master and positions 1 2 and 4 are turned on as needed to represent the slave address The intensity of the LEDs for the addressed module is brighter than the LEDs for the nonaddressed modules Debug and Address LEDs are not supported on the DT9841E d This bit is set if the data in the input latch has not been updated on the next D A clock At the fastest clock rate this means that the data must be updated within 10 us e This bit will be set if the A D clock is faster than the A D converter specification or if the data was not read fast enough by the DSP or host Register Description Calibration and Setup The Calibration and Setup register described in Table 6 is located at address 0xB0000004 Address 0xB0000001 is the control register for the Xicor potentiometers bias return resistors and Scalable Bus termination resistors The register select is CE3 described in Table 15 on page 110 and requires a clock divider of four 40 ns Table 6 Calibration and Setup Register Address 0xB0000004 Bit Register Description Type 0 to 13 Res
36. to high transition was detected on the External Trigger detected on the external BNC To clear this bit set this bit trigger line or bit 29 to 0 0 No external trigger occurred 67 Chapter 2 Table 5 Hardware Control and Status Register Address 0xB0000000 cont Bit Register Description Value Type 3 For the DT9841 DT9841E 1 Enables turbo mode for the A D R W and DT9841 VIB indicates and D A subsystems The whether turbo mode is maximum clock rate is the same selected for the A D and D A at 51 2 MHz for 200 kHz subsystems throughput The accuracy degrades to 12 bits above 0 5 For the DT9842 2 and Nyquist P DT9842 8 this bit is reserved 0 Disables turbo mode 49 Indicates whether the green 1 Turn on the green switch of LED R W switch of LED CR1 or CR6 on CR1 or CR6 on the DT9841E the DT9841E is lit 0 Turn off the green switch of LED CR1 or CR6 on the DT9841E 5 Indicates whether the red 1 Turn on the red switch of LED R W switch of LED CR1 or CR6 on CR1 or CR6 on the DT9841E the DT9841E is lit 0 Turn off the red switch of LED CR1 or CR6 on the DT9841E 6 Indicates whether EXT_INT4 1 Enables EXT INTA if R W is enabled if counter timer 2 counter timer 2 overflows overflows underflows underflows 0 Disables EXT_INT4 if counter timer 2 overflows underflows 7 Indicates whether 1 Counter timer 2 has overflowed R W counter tim
37. written is immediately loaded into the counter When the user counter counts the counter increments from the initial count to the terminal count When it reaches the terminal count the counter is reloaded with the initial count The terminal count is defined as 0 Therefore the counter counts from period reg to FFFFFFFFh rolls over to 0 and then reloads to period reg Event Counting Equations When the user counter is used to count events load the period register with a value from 1 to FFFFFFFFh Use the following formula to determine the number of events that occurred events ctr period reg where ctr is the value read from the counter For example if reading the counter returns a value of 4 and period reg 1 three events occurred 105 Chapter 2 Output Period Frequency Equations When the user counter is used to generate an output signal load the period register with a value from 1 to FFFFFFFFh The following equations relate to the output period and frequency clks per output period FFFFFFFFh 2 period reg For example if period_reg FFFFFFFEh three clocks occur for each output period In this example the counter counts FFFFFFFEh FFFFFFFFh 0 FFFFFFFEh FFFFFFFFh 0 and so on output period clks per output period x clock period For example if three clocks occur for each output period and the clock period is 55 555 ns then the output period is 166 666 ns output frequency 1 output pe
38. 0 Measure auxiliary mode for the user 0 1 Up down counter timer They only 1 0 Reserved matter if the mode select bits 1 1 Reserved specify auxiliary mode These bits reset to 00 on power up or Counter Timer reset 11 10 User Measure Start Select Bit 11 Bit10 Ww 1 0 0 0 Selected gate external These bits specify the edge that starts the measurement These bits reset to 00 on power up or Counter Timer reset external inverted or software rises 0 1 Selected gate external external inverted or software falls 0 External clock rises 1 External clock falls ot Chapter 2 Table 13 User Control Registers Addresses 0xB000C020 0xB000C024 0xB000C028 cont Bit Register Description Value Type 13 12 User Measure Stop Select Bit 13 Bit12 W 1 0 0 0 Selected gate external These bits specify the edge external inverted or that stops the measurement software rises These bits reset to 00 on 0 1 Selected gate external power up or Counter Timer external inverted or Reset software falls 1 0 External clock rises 1 1 External clock falls 14 User Measure Enable 1 Enables the selected W Command measurement The host should set up all 0 Clears the measure enable the features characteristics flag of the counter before issuing this command 15 Reserved 16 Continuous Measure Mode 1 Enables continuous measure W The normal measure mode mod
39. 0 Counter 0 R W 0xB000C004 User Period Register 1 Counter 1 R W 0xB000C008 User Period Register 2 Counter 2 R W 0xB000CO0C Reserved _ 0xB000C010 User Pulse Register 0 0xB000C014 User Pulse Register 1 Z Zj 0xB000C018 User Pulse Register 2 94 Register Description Table 12 Counter Timer Address Map cont Address Register Description Type 0xB000C01C Reserved 0xB000C0209 User Control 0 w 0xB000C0249 User Control 1 w 0xB000C0289 User Control 2 w 0xB000C02C Reserved 0xB000C030 User Status R All registers require 4 bytes of address space Bits 31 to 0 are used to specify the period of the counter timer Data written to this location is stored in the period register and then immediately loaded into the counter timer Reads of this location return the current value of the counter timer This register and counter timer are set to 0 on power up or when the counter timer is reset Bits 31 to 0 are used to specify when the output pulse of the user counter timer is activated Data written to this location is stored in the pulse register This register and counter timer are set to 0 on power up or when the counter timer is reset d See Table 13 See Table 14 on page 100 95 Chapter 2 Table 13 User Control Registers Addresses 0xB000C020 0xB000C024 0xB000C028 This bit specifies the
40. 1 0 0 1 0 1 0 1 0 1 0 Write new value to the Register register pointed to by P1 PO and R1 RO XFR Data 1 1 0 1 1 0 1 0 1 0 1 0 Transfer the contents of Reg to WCR the register pointed to by P1 PO and R1 RO to its associated WCR XFR WCR 1 1 1 0 1 0 1 0 1 0 1 0 Transfer the contents of to Data Reg the WCR pointed to by P1 PO to the register pointed to by R1 RO Register Description Table 8 Xicor Potentiometer Instruction Set cont Instruction Format Instruction I3 l2 l1 10 P1 PO R1 RO Operation Global XFR 1 0 0 1 N A N A 1 0 1 0 Transfer the contents of Data to all four Data Registers WCR pointed to by R1 RO to their respective WCR Global XFR 1 0 0 0 N A N A 1 0 1 0 Transfer the contents of WCR to all WCRs to their Data respective data registers pointed to by R1 RO Inc Dec 1 0 1 0 1 0 1 0 NA N A Enable Wiper increments decrements of the WCR pointed to by P1 PO 81 Chapter 2 Calibrating the Analog Input Subsystem Note For simultaneous sample and hold applications the rising edge of the CAL signal must be timed with the falling edge of the MCLK signal In bipolar mode with 24 bit or 16 bit converters after each WCR write a 500 us delay must be implemented to allow the wiper to settle before reading the next A D conversion The wiper must be incremented through the center value and then be backed off to center the A
41. 172 analog output 167 172 external clock 147 167 172 external trigger 147 167 172 C calibrating the module 75 analog input subsystem 82 122 analog output subsystem 83 126 running the calibration utility 121 Calibration and Setup register 75 cascading counter timers 44 177 Index 178 channels analog input 32 analog output 37 counter timer 42 digital I O 40 clocks external clock 20 external counter timer clock 43 internal clock 18 internal counter timer clock 43 internally cascaded counter timer clock 44 Scalable Bus master 21 connecting multiple modules 29 connector J1 pin assignments 157 167 172 DT9841E 159 connector J11 pin assignments 147 158 168 DT9841 151 156 DT9841E 165 DT9842 2 151 156 DT9842 8 151 156 connector J12 pin assignments 147 168 DT9841 151 connector J13 pin assignments 147 168 DT9841 151 DT9842 21 151 DT9842 8 151 connector J15 pin assignments 147 connector J16 pin assignments 147 connector J17 pin assignments 147 DT9841 153 DT9842 2 153 DT9842 8 153 connector J18 pin assignments 148 DT9841 155 DT9842 2 155 DT9842 8 155 connector J19 pin assignments 148 167 172 connector J2 pin assignments 146 157 167 172 DT9841 148 DT9841E 162 DT9842 2 148 DT9842 8 148 connector J201 pin assignments 172 174 connector J202 pin assignments 172 173 connector J3 pin assignments 146 157 DT9841 149 DT9841E 163 DT9842 2 149 DT9842 8 149 connector J4 pin assignments 146 15
42. 2 Reserved 23 Reserved 24 Reserved 25 Reserved 26 Reserved 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved 32 Reserved 33 Analog Input 01 34 Analog Input 00 35 Isolated Power Ground 36 Analog Common 37 Reserved 38 Reserved 39 Reserved 40 Reserved 41 Reserved 42 Reserved 43 Reserved 44 Reserved 173 Appendix B 174 Table 34 Pin Assignments for Connector J202 on the EP358E Accessory Panel cont Pin Signal Description Pin Signal Description 45 Reserved 46 Reserved 47 Reserved 48 Reserved 49 Reserved 50 Reserved 51 Reserved 52 Reserved 53 Reserved 54 Reserved 55 Reserved 56 Reserved 57 Reserved 58 Reserved 59 Reserved 60 Reserved 61 Reserved 62 Reserved 63 Reserved 64 Reserved 65 Reserved 66 Reserved 67 Analog Input 01 Return 68 Analog Input 00 Return Table 35 Pin Assignments for Connector J201 on the EP358E Accessory Panel Pin Signal Description Pin Signal Description 1 User Counter Output 2 2 User Clock Input 2 Encoder A2 3 User Counter Output 1 4 User Clock Input 1 Encoder A1 5 User Counter Output 0 6 User Clock Input 0 Encoder A0 Connector Pin Assignments Table 35 Pin Assignments for Connector J201 on the EP358E Accessory Panel Pin Signal Description Pin Signal Description 7 Digital Input Output 0 Por
43. 41E module connect the external trigger to pin 24 of connector J1 For all other modules connect the external trigger to the Ext Trig BNC on the module This trigger asserts EXT INTA4 for processing 27 Chapter 1 28 Note If you are using the Scalable Bus to connect multiple modules and you want to externally trigger the master and slave modules at the same time you must supply an external trigger signal to the master and each slave module using external wiring The external trigger signals is not provided through the Scalable Bus cable and connectors Refer to page 29 for more information on using the Scalable Bus When the DT9840 Series module detects the specified trigger event the input and or output operation starts at the clock frequency of the specified clock source Figure 2 illustrates acquisition using an external trigger source In this example an input scan record is acquired on each pulse of the selected clock source when the external trigger event occurs Scan 1 Scan3 Scan4 Scan 6 Scan 7 Scan 9 Scan 2 Scan5 Scan 8 l l l Sample Clock j The module detects a low to high transition on the TTL level signal attached to the Ext Trig BNC Data is acquired on each pulse of the sample clock Figure 2 Acquisition Using an External Trigger Principles of Operation Notes Because the DT9841 DT9841E and DT9841 VIB modules require 37 clock pulses
44. 7 168 DT9841 149 DT9841E 164 DT9842 2 149 DT9842 8 149 connector J6 pin assignments 146 158 168 DT9841 150 DT9841E 165 DT9842 2 150 DT9842 8 150 continuous block operation mode 26 continuous list operation mode 26 continuous measure mode 56 continuous scan operation mode 25 count sequence 105 counter initialization 108 Index Counter Timer Address Map 94 counter timer clock sources 43 cascaded counter timer clock 44 external counter timer clock 43 internal C T clock 43 counter timer connector 167 172 Sleek Box 171 counter timer features 42 cascading internally 44 clock sources 43 edge types 47 gate types 45 operation modes 51 103 pulse output parameters 49 registers 94 specifications 138 units 42 counting events 52 CR1 LED 31 74 CR10 LED 31 74 CR11 LED 31 74 CR12 LED 31 74 CR13 LED 31 74 CR14 LED 31 74 CR15 LED 74 116 CR6 LED 31 74 CR7 LED 31 74 CR8 LED 31 74 CR9 LED 31 74 D D A Data Address Map 92 data encoding 35 39 data format analog input 35 analog output 39 data transfer analog input 35 analog output 39 debug LEDs 31 112 description of the functional subsystems analog input 32 analog output 37 counter timer 42 digital I O 40 digital I O connector 167 172 Sleek Box 169 digital I O features 40 interrupts 41 lines 40 registers 93 specifications 136 137 digital lines 40 digital trigger 27 DMA address map 87 E edge type 47 falling edge 47 fa
45. Analog Input Subsystem Specifications cont DT9841 DT9841E and DT9841 VIB DT9842 2 and DT9842 8 Feature Specifications Specifications 1 LSB 1 192 uV 305 uV 20 v 2 20 v 216 Input signal range 10 V 10 V Coupling For DT9841 and DC DT9841E DC For DT9841 VIB AC 3dB 1 6 Hz DC offset 1 5 mV Zero error 10 001 V 0 001 Drift Zero 40 uV C 20 uV C Gain 100 ppm C 25 ppm C Input impedance For DT9841 and 100 MQ 10 pF DT9841E 100 MO 10 pF For DT9841 VIB 1 MQ 20 pF Input bias current 10 nA 10 nA Common mode voltage 11 V maximum operational 11 V maximum operational 131 Appendix A 132 Table 3 Analog Input Subsystem Specifications cont Feature DT9841 DT9841E and DT9841 VIB Specifications DT9842 2 and DT9842 8 Specifications Maximum input voltage For DT9841 and DT9841E 25 V maximum protection DC For DT9841 VIB 40 V maximum protection DC 25 V maximum protection DC Internal reference 2 5 V 0 002 V 2 5 V 0 002 V A D converter noise 16 LSBs rms 0 75 LSBs rms Channel to channel offset 700 uV 700 uV Channel to channel aperture match 5 ns 3 ns Aperture jitter 100 ps rms 10 ps rms A D conversion time 10 us 8 us A D type Delta Sigma Successive Approximation Group delay DT9841 370 us 100 kHz DT9841E and DT9841 VIB 37
46. B is reserved for storing a DSP program You can download a program into SDRAM using the DT9840 Series Download Utility described in the DT9840 Series Getting Started Manual and then run and debug the program Once you have debugged the program you can store it in flash memory using the DT9840 Series Flash Download Utility described in the DT9840 Series Getting Started Manual This allows the DSP program to run automatically each time the DT9840 Series module is powered on autonomously from the PC If desired you can also copy a user data fie into flash memory using the DT9840 Series Flash Download Utility By copying a user data into flash you can ensure that valuable information such as configuration information or collected data persists across power cycles even if the DT9840 Series module loses power or is turned off 17 Chapter 1 18 Notes Only one DSP program can be running on a module at one time In addition only one user data file can be stored in flash memory at a time Each DT9840 Series module also requires a CDB file for proper operation Refer to the DT9840 Series DSP Library User s Manual for more information on CDB files Clock Sources DT9840 Series modules support the following sample clock sources Internal clock described below External clock described on page 20 Scalable Bus master clock described on page 21 Internal Clock The internal clock has a 36 MHz time base for the D
47. Clr 6 User Clock Input 0 40 Isolated Digital Ground Encoder A0 5 User Counter Output 0 39 External Gate 0 Encoder B0 4 User Clock Input 1 38 Isolated Digital Ground Encoder A1 Connector Pin Assignments Table 23 Analog Output Digital I O Counter Timer Ext Trig Ext Clock Connector J1 Pin Assignments on the DT9841E cont Pin Signal Description Pin Signal Description 3 User Counter Output 1 37 External Gate 1 Encoder B1 2 User Clock Input 2 36 Isolated Digital Ground Encoder A28 1 User Counter Output 2 35 External Gate 2 Encoder B28 a Currently this function is not implemented b Use this pin to connect an external trigger to the DT9841E module c Use this pin to connect an external clock to the DT9841E module 161 Appendix B Table 24 Analog Input Connector J2 Pin Assignments on the DT9841E Pin Signal Description Pin Signal Description 34 Analog Input 00 68 Analog Input 00 Return 33 Analog Input 01 67 Analog Input 01 Return 32 Reserved 66 Reserved 31 Reserved 65 Reserved 30 Reserved 64 Reserved 29 Reserved 63 Reserved 28 Reserved 62 Reserved 27 Reserved 61 Reserved 26 Reserved 60 Reserved 25 Reserved 59 Reserved 24 Reserved 58 Reserved 23 Reserved 57 Reserved 22 Reserved 56 Reserved 21 Reserved 55 Reserved 20 Reserved 54 Reserved 19 Reserved 53 Reserved 18 Res
48. D7 correspond to LEDs CR5 through CR12 The LEDs were numbered differently on some early modules If an error is detected in a running DT9840 Series DSP program these LEDs turn on 112 Register Description Scalable Bus Note The Scalable Bus is not supported by DT9841E modules Two 50 pin connectors J12 and J13 on the DT9840 Series module provide the a Scalable Bus for connecting modules together By plugging EP342 cables from one module to another you can connect up to seven slave modules to a DT9840 Series master module The first module usually the master and the final module usually a slave in the chain must be terminated in software with 100 ohms Bit 25 of the Calibration and Setup register described in Table 6 on page 75 controls the 100 ohm termination resistors The Scalable Bus connector is set up for intermodule communication at speeds up to 50 MBytes s note however that the maximum rate in software is 11 3 MBytes s The negative strobe pulse must be 12 ns minimum with the data valid for 10 ns before the rising edge The hold time is 0 ns When a slave module requests service it asserts interrupt EXT_INT4 The master module reads each slave at a time to determine which module asserted the interrupt line The requesting module places the number of words to transfer on the bus All other modules place zeros on the bus The module is now set up to write the number of words reported The SB
49. DATA TRANSLATION UM 19197 M DT9840 Series User s Manual Twelfth Edition October 2006 Data Translation Inc 100 Locke Drive Marlboro MA 01752 1192 508 481 3700 www datatranslation com Fax 508 481 8620 E mail info datx com Copyright 2003 2006 by Data Translation Inc All rights reserved Information furnished by Data Translation Inc is believed to be accurate and reliable however no responsibility is assumed by Data Translation Inc for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent rights of Data Translation Inc Use duplication or disclosure by the United States Government is subject to restrictions as set forth in subparagraph c 1 ii of the Rights in Technical Data and Computer software clause at 48 C F R 252 227 7013 or in subparagraph c 2 of the Commercial computer Software Registered Rights clause at 48 C F R 52 227 19 as applicable Data Translation Inc 100 Locke Drive Marlboro MA 01752 Data Translation is a registered trademark of Data Translation Inc All other brand and product names are trademarks or registered trademarks of their respective companies Radio and Television Interference This equipment has been tested and found to comply with CISPR EN55022 Class A and EN50082 1 CE requirements and also with the limits for a C
50. FFFFFFFh rolls over to 0 the terminal count and then reloads the period count Use the following equations to determine the period count when performing pulse output operations e PeriodCount FFFFFFFFh 2 clock frequency output frequency For example if the clock input frequency is 18 MHz and the desired pulse output frequency is 6 0 MHz the required PeriodCount is FFFFFFFEh clks per output period FFFFFFFFh 2 PeriodCount For example if PeriodCount FFFFFFFEh three clocks occur for each output period In this example the counter counts FFFFFFFEh FFFFFFFFh 0 FFFFFFFEh FFFFFFFFh 0 and so on output period clks per output period x clock period For example if three clocks occur for each output period and the clock period is 55 555 ns then the output period is 166 666 ns output frequency 1 output period For example if the output period is 166 666 ns then the output frequency is 6 0 MHz 50 Principles of Operation Pulse Width Count The pulse width count determines when the output pulse of the Iz counter timer is activated Values range from 1 to FFFFFFFFh Use the following equations to determine the value for the pulse width count e PulseWidthCount FFFFFFFFh 1 duty cycle x clock frequency output frequency For example if the clock input frequency is 18 MHZ the frequency of the output pulse is 6 0 MHz and the desired duty cycle is 66 6676 then the r
51. Flag Bits Digital Port 2 R Digital Port 1 Digital Port 0 0xB0004024 Counter Timer 0 R 0xB0004028 Counter Timer 1 R 0xB000402C Counter Timer 2 R a Ignore the data in this register for DT9841E modules b For the DT9841 VIB module bit 0 of digital port 2 is used as the SCL clock and bit 1 of digital port 2 is used as the SDA data output the remaining bits 2 7 of digital port 2 are reserved See page 75 for more information c Note that the digital ports are located at address 0xB0004020 along with the flag bits This allows a single burst through the sequential addresses to acquire all the input data and flags Active state 1 All reads are done at the 40 0 ns clock rate using the CE3 setup Refer to Table 10 for more information on the flag bits Refer to Table 15 on page 110 for more information on CE3 Table 10 describes the flags at address 0xB0004020 88 Register Description Table 10 Flags at Address 0xB0004020 Bit Register Description 24 1 Temperature is 65 C or over 0 Temperature is under 65 C 25 1 Counter timer 2 has overflowed this is the same as bit 7 of the Control and Status register 0 Counter timer 2 has not overflowed 26 1 Counter timer 1 has overflowed this is the same as bit 9 of the Control and Status register 0 Counter timer 1 has not overflowed 27 1 Counter timer 0 has overflowed this is the same as bit 11 of the Control and
52. T9841 DT9841E and DT9841 VIB modules and an 18 MHz time base for the DT9842 2 and DT9842 8 modules Conversions start on a high to low transition after a rising edge of the internal calibration signal Use software to specify the internal clock source and the frequency at which to pace the input and output operations and to start the sample clock For the DT9841 DT9841E and DT9841 VIB the sampling frequency ranges from 200 Hz to 100 kHz For the DT9842 2 and DT9842 8 the sampling frequency ranges from 0 Hz to 100 kHz Principles of Operation Note According to sampling theory Nyquist Theorem specify a frequency that is at least twice as fast as the input s highest frequency component For example to accurately sample a 20 kHz signal specify a sampling frequency of at least 40 kHz to avoid aliasing The actual frequency that the module can achieve may be slightly different than the frequency you specified due to the accuracy of the clock 0 01 for the DT9840 Series You can determine the actual clock frequency using software DT9841 DT9841E and DT9841 VIB Internal Clock On the DT9841 DT9841E and DT9841 VIB modules the value that you specify for the internal clock frequency is multiplied by 512 internally to set the oscillator on the module The resulting signal from the oscillator is then divided by 2 to provide a clock signal to the A D and D A converters that is oversampled 256 times and has a 50 duty cycle
53. Throughput Pass band 0 453 x Throughput Stop band 0 547 x Throughput Signal Noise Distortion 92 db 1 kHz 86 db 1 kHz Total Harmonic Distortion 96 db 1 kHz 90 db 1 kHz Spurious Free Dynamic 110 dB 90 dB Range Specifications Table 3 Analog Input Subsystem Specifications cont Feature DT9841 DT9841E and DT9841 VIB Specifications DT9842 2 and DT9842 8 Specifications Channel crosstalk 400 dB 1 kHz 400 dB 1 kHz DT9841 VIB Data Throughput Single channel 100 kS s 100 kS s Scan all channels For DT9841 and 800 kS s DT9841 VIB 800 kS s For DT9841E 200 kS s Accuracy of Clock Oscillator 0 0196 0 0196 IEPE Current Source 4 mA IEPE Current Source Noise DT9841 VIB 10 nA rms 1 kHz Accuracy DT9841 VIB IEPE Compliance Voltage 24 V DT9841 VIB IEPE Current Source 1 0 IEPE Filter DT9841 VIB 2 pole Butterworth 10 kHz 3 dB a Cable capacitance of typically 30 pF per foot must be added 133 Appendix A 134 Table 4 lists the specifications for the analog output subsystem Table 4 Analog Output Subsystem Specifications Feature DT9841 DT9841E and DT9841 VIB Specifications DT9842 Specifications Number of analog output channels 2 2 for DT9842 2 8 for DT9842 8 Resolution 24 bits 16 bits Data encoding Twos complement Offset binary Nonlinearity integral
54. Type 15 1 The address on the Scalable Bus matches the address R of the slave 0 The address on the Scalable Bus does not match the address of the slave 16 18 Bus Address Bits Master Only R W Set these bits to the address of the slave with which the master will communicate 19 1 Enable the Receive FIFO bit on the master R W 0 Disable the Receive FIFO bit on the master 20 1 Enable writing to the FIFO on the slave module as R W long as the slave is addressed or a broadcast message is sent on the bus 0 Disable writing to the FIFO on the slave module 21 31 Reserved a Bits 0 through 3 are written by the host USB to specify the module as a master or slave and to set the address of the slaves Four address LEDs CR15 indicate the Scalable Bus address position M is the master and positions 1 2 and 4 are turned on as needed to represent the slave address The intensity of the LEDs for the addressed module is brighter than the LEDs for the nonaddressed modules The Scalable Bus is not supported by the DT9841E b When a master finishes reading a single word of Transfer Request the master generates a pulse on this line write bit set to 1 then to 0 Register Description Table 17 describes the SB Write Data Address and Read Data Address registers Table 17 SB Write Data Address and Read Data Address Registers Register Typ Address Name Register Description e 0xA0000000 Write Bits 0 to
55. ach transfer The board generates an interrupt EXT_INT5 after the data in the analog output channel has been output For 100 kHz operation both analog output channels must then be updated with the next value to write within 10 us For the DT9841 DT9841E and DT9841 VIB modules analog output data must always be output as two 32 bit words channels 0 then channel 1 The data is clocked into the internal serial output register on the second word address The initial value must be the code for 0 V output to prevent glitching after power up For the DT9842 2 and DT9842 8 when new data is written to any of the analog output data registers all of the analog output channels are updated on the next clock cycle For example assume that you write anew value to analog output channel 0 On the next clock cycle channel 0 is updated with the new value you specified and all the other analog output channels are updated with the existing values in the corresponding data registers 39 Chapter 1 Error Conditions DT9840 Series modules report an analog output underflow error to the host computer if the analog output data is not transferred fast enough within 10 us of the fastest clock rate from the host computer to the module The host computer must clear this error To avoid this error ensure that the host computer provides analog output data to the module faster than the DACs are converting the data Digital I O Features 40 This se
56. al Ground 24 External A D Trigger 58 Isolated Digital Ground 23 External A D Clock 57 Isolated Digital Ground 22 Digital Input Trigger 56 Isolated Digital Ground 21 Digital Input Clock 55 Isolated Digital Ground 20 Digital Output Trigger 54 Isolated Digital Ground 19 Digital Output Clock 53 Isolated Digital Ground 159 Appendix B 160 Table 23 Analog Output Digital I O Counter Timer Ext Trig Ext Clock Connector J1 Pin Assignments on the DT9841E cont Pin Signal Description Pin Signal Description 18 Digital Input Output 3 Port 0 52 Digital Input Output 7 Port 0 17 Digital Input Output 2 Port 0 51 Digital Input Output 6 Port 0 16 Digital Input Output 1 Port 0 50 Digital Input Output 5 Port 0 15 Digital Input Output 0 Port 0 49 Digital Input Output 4 Port 0 14 Digital Input Output 3 Port 1 48 Digital Input Output 7 Port 1 13 Digital Input Output 2 Port 1 47 Digital Input Output 6 Port 1 12 Digital Input Output 1 Port 1 46 Digital Input Output 5 Port 1 11 Digital Input Output 0 Port 1 45 Digital Input Output 4 Port 1 10 Digital Input Output 3 Port 2 44 Digital Input Output 7 Port 2 TINP18 9 Digital Input Output 2 Port 2 43 Digital Input Output 6 Port 2 Encoder 2 Clr 8 Digital Input Output 1 Port 2 42 Digital Input Output 5 Port 2 Encoder 1 Clr 7 Digital Input Output 0 Port 2 41 Digital Input Output 4 Port 2 Encoder 0
57. alable Bus assign a unique address for each module on the bus and configure the final slave module on the bus with 100 Q termination Refer to the DT9840 Series Getting Started Manual for more information on using the DT9840 Series Control Panel application If you want to synchronize the operation of all modules connected on the Scalable Bus do the following 1 Configure the master module to use either an internal or external clock source If you select an external clock ensure that you attach a clock signal to the Ext Clk BNC connector on the master module Set the clock source for each slave module to AD_DA_CLK_SRC_SB_MASTER using the DT_SetupClock function The clock and reset signals are provided to all the slave modules from the master DT9840 Series module through the Scalable Bus cables and connectors In this configuration the Ext Clk BNC connector on the slave modules is not used Configure the master module to use either an internal or external trigger source The Scalable Bus cables and connectors provide the internal trigger signal but not the external trigger signal from the master module to the slave modules Therefore if you are using an internal trigger to trigger the master and slave modules the Ext Clk BNC connector on the slave modules is not used If you select an external trigger ensure that you attach a trigger signal to the Ext Trig BNC connector on the master module and to the Ext Trig BNC connector
58. alog Output Subsystem This section describes how to use the DT9841 Calibration Utility to calibrate the analog output subsystem of a DT9841 DT9841E or DT9841 VIB module To calibrate the analog output circuitry you need to connect an external precision voltmeter to the analog output channels of the DT9841 DT9841E or DT9841 VIB module Do the following to calibrate the analog output circuitry 1 10 11 Select the D A Configuration tab of the DT9841 Calibration Utility Connect an external precision voltmeter to Analog Output 0 DAC Ch0 of the DT9841 DT9841E or DT9841 VIB module In the DAC Output Voltage box select 0 V Adjust the offset by entering values between 0 and 255 in the DAC 0 Offset edit box or by clicking the up down buttons until the voltmeter reads 0 V In the DAC Output Voltage box select 9 375 V Adjust the gain by entering values between 0 and 255 in the DAC 0 Gain edit box or by clicking the up down buttons until the voltmeter reads 9 375 V Connect an external precision voltmeter to Analog Output 1 DAC Ch1 of the DT9840 Series module In the DAC Output Voltage box select 0 V Adjust the offset by entering values between 0 and 255 in the DAC 1 Offset edit box or by clicking the up down buttons until the voltmeter reads 0 V In the DAC Output Voltage box select 9 375 V Adjust the gain by entering values between 0 and 255 in the DAC 1 Gain edit box or by clicking the up down buttons un
59. analog input or other counter timer operations The internal C T clock source starts the rate generation operation when the enabled gate signal software external normal or external inverted is active Refer to page 43 for more information on C T clock sources refer to page 45 for more information on gate types You can specify the polarity of the output signal the frequency of the pulse output signal using the period count and the duty cycle of the pulse output signal using the pulse width count Refer to page 49 for more information on the pulse output parameters 53 Chapter 1 54 External Gate Input Signal Internal C T Clock Input Signal Pulse Output Signal The pulse output is activated when the counter increments to the pulse width count The pulse output stays active until the counter rolls over to 0 the terminal count The pulse output is then deactivated and the counter is automatically reloaded with the period count This sequence is repeated as long as the counter is enabled by the gate Figure 6 shows an example of a rate generation operation using an internal C T clock source normal gate type period count of FFFFFFFEh a low to high output pulse polarity and a pulse width count of FFFFFFFEh to achieve a duty cycle of 66 A 6 0 MHz square wave is the generated output High level enables operation Low level disables operation P 18 MHz frequency 6 0 MHz frequency
60. ation functions that you can use to communicate between a DT9840 Series module and a Windows based host program Refer to the DT9840 Series DSP Library User s Manual and DT9840 Series Host Communications Library User s Manual for more information about the functions included in these libraries For maximum flexibility you can also program your own digital signal processing tasks at the DSP level if you wish Currently the DT9840 Series consists of the DT9841 DT9841E DT9841 VIB DT9842 2 and DT9842 8 modules Table 1 describes the differences among the modules Table 1 DT9840 Series Modules Analog Converter Sampling Analog Analog Scalable Models Inputs Type Resolution Rate Filtering Outputs Bus DT9841 8DI Delta 24 bit 200 Hz to Yes 24 Yes Sigma 100 kHz DT9841 8SE Delta 24 bit 200Hzto Yes 24 Yes VIB Sigma 100 kHz 14 Principles of Operation Table 1 DT9840 Series Modules cont goc m Analog Converter Sampling Analog Analog Scalable Models Inputs Type Resolution Rate Filtering Outputs Bus DT9841 2DI Delta 24 bit 200 Hz to Yes 24 No E Sigma 100 kHz DT9842 8SE Successive 16 bit 0 Hz to No 2f Yes 2 Approximation 100 kHz DT9842 8SE Successive 16 bit 0 Hz to No ef Yes 8 Approximation 100 kHz DI refers to differential mode and SE refers to single ended mode For differential inputs o
61. automatically reloaded with the period count described on page 50 The output then stays inactive and the counter stays disabled until the operation is re enabled with the proper gate signal All gate signals that occur while the counter is incrementing are ignored You can specify the polarity of the output signal refer to page 49 for more information In repetitive one shot mode the internal C T clock source is more useful than an external C T clock source refer to page 43 for more information on the internal C T clock source Figure 11 shows an example of a repetitive one shot operation using an external normal gate a period count of FFFFFFFEh a low to high output pulse polarity and a pulse width count of FFFFFFFEh to achieve a duty cycle of 66 63 Chapter 1 64 Repetitive One Shot Operation Starts External Gate Signal Pulse Output Signal 166 666 ns period 98 8 o dE 66 duty cycle 166 666 ns period p 66 duty cycle Figure 11 Example of Repetitive One Shot Mode 66 duty cycle Register Description USB Bus DSP Hardware Interface 00 67 CalibraHom and Setup 2 2 n ke buna k ee hee e ver 75 Analog Input Subsystem x 5 e nee iata 85 Analog Output Subsystem 0 6 sce ace ee e me tee 90 Digital VO oubeyatem sees 2 A kulk nda kk kul k eee 93 Counter
62. brated When the offset calibration is complete a message appears notifying you to set the input voltage of the first A D channel to 49 375 V 6 Apply a voltage of 9 375V to the selected A D channel and then click OK The gain value is calibrated 7 Connect a precision voltage source to the next selected analog input channel verify that 0 V is applied to the channel and then click OK The offset value is calibrated When the offset calibration is complete a message appears notifying you to set the input voltage of the first A D channel to 49 375 V 8 Apply a voltage of 9 375V to the selected A D channel and then click OK The gain value is calibrated 9 Repeat steps 7 and 8 until all the selected analog input channels are calibrated When the last channel has been calibrated a completion dialog box is displayed 10 Click OK to finalize the analog input calibration process 123 Chapter 3 Note At any time you can click Restore Factory Settings to reset the A D calibration values of the selected channels only to their original factory settings This process will undo any auto or manual calibration settings Using the Manual Calibration Procedure If you want to manually calibrate the analog input circuitry instead of auto calibrating it do the following 1 In the Clock Frequency edit box enter a clock frequency between 5 kHz and 100 kHz at which you will be operating the module Note The calib
63. change If you are using the interrupt on change feature when deglitching is enabled the maximum frequency that any change can be detected is 500 Hz if deglitching is disabled the maximum frequency that any change can be detected is 100 kHz 41 Chapter 1 Counter Timer Features This section describes the following user counter timer features C T channels described below C T clock sources described on page 43 Gate types described on page 45 Pulse types and duty cycles described on page 49 Counter timer operation modes described on page 51 C T Channels All DT9840 Series modules provide three 32 bit counter timer channels The counters are numbered 0 1 and 2 You select the counter timer channel to configure using software Each counter accepts a clock input signal and gate input signal and outputs a clock output signal also called a pulse output signal as shown in Figure 4 Clock Input Signal internal external or __ Counter H Pulse Output Signal internally cascaded 42 Gate Input Signal software or external input Figure 4 Counter Timer Channel Principles of Operation C T Clock Sources The following clock sources are available for each of the user counter timers Internal C T clock e External C T clock Internally cascaded clock You specify the clock source to use for the selected counter timer using software Refer t
64. ction describes the following features specific to the digital input and digital output subsystems Digital I O lines Interrupts Digital I O Lines The DT9841 VIB module supports two 8 bit ports ports 0 and 1 All other DT9840 Series modules support three 8 bit ports ports 0 1 and 2 You can program these ports for digital input or digital output using software If you configure port 0 as a digital input port the interrupt on change feature described in the next section is available On power up or module reset no digital data is output from the modules All the outputs include diode protection to the isolated ground and the isolated 5 V Principles of Operation Interrupt On Change If port 0 is configured for digital input the DT9840 Series module can generate an interrupt when any of the lines of port 0 changes state This feature is useful when you want to monitor critical signals or when you want to signal the host computer to transfer data to or from the module You specify an interrupt handler using software The DT9840 Series modules provide deglitching circuitry that you can enable using software for the digital inputs of port 0 If this circuitry is enabled any state changes that result from noise sources slow rise or fall times or switch bounce on the input source are ignored for approximately 10 ms Deglitching the inputs prevents most situations where multiple interrupts can occur for one state
65. ctronic Development Corporation s Model 501 should be used to calibrate the A D subsystem The following sections describe the calibration process 77 Chapter 2 Setting Up the Xicor Potentiometers Control I O line SDA is provided for serial data and SCL is provided for the serial clock All commands are preceded by a high to low transition on SDA while SCL is high All communication must be terminated with a low to high transition on SDA while SCL is high SCL must be high and low for 5 us minimum 100 kHz Rather than push the high and low timing in a Windows environment it is suggested that a 10 us high and low period be established with the data transitions taking place in the center 50 KHz Slowing the timing down further will not cause any errors Note ACK Acknowledge and Read Back are not be available on the DT9841 DT9841E and DT9841 VIB module To calibrate the module the potentiometer must be reset by writing the lowest value and then incrementing it until the correct value is set After each byte of data is transferred an ACK low going signal can be read on the SDA line on the 9th high going low SCL signal The data is valid 4 7 us after the SCL switches from low to high and 0 3 us after the high to low transition The first byte sent after a start command must be the device type followed by the address The device type is 0101 for a X9258 the addresses for the potentiometers are listed in Tabl
66. d Encoder A0P 5 User Counter Output 0 39 External Gate 0 Encoder B0 4 User Clock Input 1 38 Isolated Digital Ground Encoder A1 gt 3 User Counter Output 1 37 External Gate 1 Encoder B1P 2 User Clock Input 2 36 Isolated Digital Ground Encoder A2P 1 User Counter Output 2 35 External Gate 2 Encoder B2 a Available on the DT9842 8 module only b Currently this function is not implemented Connector Pin Assignments Table 20 Analog Input Connector J18 Pin Assignments Pin Signal Description Pin Signal Description 34 Analog Input 00 68 Analog Input 00 Return 33 Analog Input 01 67 Analog Input 01 Return 32 Analog Input 02 66 Analog Input 02 Return 31 Analog Input 03 65 Analog Input 03 Return 30 Analog Input 04 64 Analog Input 04 Return 29 Analog Input 05 63 Analog Input 05 Return 28 Analog Input 06 62 Analog Input 06 Return 27 Analog Input 07 61 Analog Input 07 Return 26 Reserved 60 Reserved 25 Reserved 59 Reserved 24 Reserved 58 Reserved 23 Reserved 57 Reserved 22 Reserved 56 Reserved 21 Reserved 55 Reserved 20 Reserved 54 Reserved 19 Reserved 53 Reserved 18 Reserved 52 Reserved 17 Reserved 51 Reserved 16 Reserved 50 Reserved 15 Reserved 49 Reserved 14 Reserved 48 Reserved 13 Reserved 47 Reserved 12 Reserved 46 Reserved 155 Appendix B Table 20 Analog Input Connector J18 Pin Assignments c
67. de la class A prescrites dans le R glement sur le brouillage radio lectrique dict par le Minist re des Communications du Canada Table of Contents About this Manual lesen 9 Intended Audience 00 0 KK KK KK KK KK KK KK KK KK kk kk 9 How this Manual is Organized 000 00000 9 Conventions Used in this Manual 2 00005 10 Related Information W Wk k KK KK KK KK KK KK KK KK KK KK 10 Where t Get Hel gt 44 4 542 54 x5428 5 5y4 RR E ER ees 11 Chapter 1 Principles of Operation 13 System Features a 5a c a eee gece sag Patan Pie mete deae 17 Memory sered bite J abe Sie mmma n 17 Clock Sources eher ER RP ERR REP RT ERES 18 Internal Clock AW kk kK kK KK KK KK KK KK KK KK KK 18 D19841 DT9841E and DT9841 VIB Internal CVO CI a ela wa wa We an n ku hakan hoes 19 DT9842 2 and DT9842 8 Internal Clock 20 External Clock 34e ER CREDERE E Rs 20 DT9841 DT9841E and DT9841 VIB External COC icc PIT 21 DT9842 2 and DT9842 8 External Clock 21 Scalable Bus Master Clock 21 Operation Modes sg sus sa xel any s kend k n eee eee 22 Single Value Operations 00000005 22 Single Scan Operations W KK KK KK KK KK 23 Multiple Scan Input Operations 24 Function Generator Output Operations 24 Continuous Loop Operations
68. documents for more information on using the DT9840 Series modules Benefits of the Universal Serial Bus for Data Acquisition This white paper describes why USB is an attractive alternative for data acquisition It is available on the Data Translation web site www datatranslation com DT9840 Series Getting Started Manual UM 19199 This manual included on the DT9840 Series Software CD describes the how to install the DT9840 Series modules and related software DT9840 Series DSP Library User s Manual UM 19591 This manual included on the DT9840 Series Software CD describes how to write a DSP program for the DT9840 Series modules DT9840 Series Host Communication Library User s Manual UM 19593 This manual included on the DT9840 Series Software CD describes how to write a host application program that communicates with the DSP program running on the DT9840 Series module Documentation for Code Composer Studio Integrated Development Environment IDE from Texas Instruments About this Manual e Documentation for Texas Instruments TMS320C6713 DSP processor e Microsoft Windows 2000 or Windows XP documentation Microsoft Visual Studio documentation USB 1 1 and USB 2 0 specifications on the USB web site http www usb org Where to Get Help If you have difficulty using a DT9840 Series module Data Translation s Technical Support Department is available to provide technical assistance To request tec
69. e must also be selected to use 0 Disables continuous measure this feature A starting edge mode must be selected for this mode The stop edge is not used 98 Register Description Table 13 User Control Registers Addresses 0xB000C020 0xB000C024 0xB000C028 cont Bit Register Description Value Type 17 Clear Continuous Measure 1 Enables continuous measure W Mode on Read mode to be cleared when read Bit 16 must also be set to from the CGL address use this feature 0 Disables continuous measure mode from being cleared when read from the CGL address 31 18 Reserved a Bits for this register must always be written with 0 This allows these bits to be redefined as functional bits in the future without impacting existing software 99 Chapter 2 100 Table 14 User Status Register Address 0xB000C030 Bit Register Description Value Type User Counter 0 One Shot 0 One Shot Triggers Disabled R Trigger Enable Flag 1 One Shot Triggers Enabled This flag indicates whether This bit is set when the host writes user counter 0 is enabled to 1 to the user one shot trigger detect one shot triggers This enable command bit of the control bit resets to 0 on power up or register This bit is cleared by the counter timer reset core at the completion of the one shot pulse if the counter is in non retriggerable one shot mode It is also cleared when the user
70. e 7 78 Register Description Table 7 Xicor Potentiometer Addresses and Functions Address Potentiometer Function 0000 0 A D 0 Zero Calibration 0000 1 A D 1 Zero Calibration 0000 2 A D 2 Zero Calibration 0000 3 A D 3 Zero Calibration 0001 0 A D 4 Zero Calibration 0001 1 A D 5 Zero Calibration 0001 2 A D 6 Zero Calibration 0001 3 A D 7 Zero Calibration 0010 0 A D 0 Full Scale Calibration 0010 1 A D 1 Full Scale Calibration 0010 2 A D 2 Full Scale Calibration 0010 3 A D 3 Full Scale Calibration 0011 0 A D 4 Full Scale Calibration 0011 1 A D 5 Full Scale Calibration 0011 2 A D 6 Full Scale Calibration 0011 3 A D 7 Full Scale Calibration 0100 0 D A 0 Zero Calibration 0100 1 D A 1 Zero Calibration 0100 2 D A 0 Full Scale Calibration 0100 3 D A 1 Full Scale Calibration 79 Chapter 2 Table 8 describes the instruction set for the Xicor potentiometers Table 8 Xicor Potentiometer Instruction Set Instruction Format Instruction 13 l2 l1 10 P1 PO R1 RO Operation Read WCR 1 0 0 1 1 0 1 0 N A N A Read the contents of the wiper counter register pointed to by P1 PO Write WCR 1 0 1 0 1 0 1 0 N A N A Write new value to the wiper counter register pointed to by P1 PO Read Data 1 0 1 1 1 0 1 0 1 0 1 0 Read the contents of the Register register pointed to by P1 PO and R1 RO Write Data 1
71. e signals are wired appropriately Refer to the DT9840 Series Getting Started Manual for wiring examples 55 Chapter 1 56 Signal Connected to External Gate Input Pin Rising edge of gate starts Falling edge of gate stops the measure operation the measure operation lt a p The interval is calculated and the number of counts is returned Pulse width Number of Counts 18 MHz Figure 7 Example of Frequency Measurement Continuous Measure Use continuous measure mode to measure the interval between a selected start edge and the next start edge of a signal connected to the external C T input pin or external gate input pin of the counter timer Refer to page 47 for more information on edge types and how to use them to measure frequency and period When it detects the specified start edge the counter begins incrementing The counter stops incrementing when it detects the next start edge The stop edge is ignored When the operation completes the counter remains idle until it is read On the next read the current value of the counter from the previous measurement is returned and the next measurement is started automatically Principles of Operation Note If you read the counter before the measurement is complete 0 is returned For example you might see results similar to the following if you read the counter timer channel as part of the data stream Counter Status of Contin
72. ed at 16 bits Input Range and Gain All DT9840 Series modules provide an input range of 10 V anda fixed gain of 1 34 Principles of Operation Data Format The analog input data encoding used by the DT9841 DT9841E and DT9841 VIB modules is floating point The data is 32 bit wide and left justified the right eight bits are filled with zeros The DT9842 2 and DT9842 8 modules use twos complement data encoding The data is 32 bit wide and left justified the right 16 bits are filled with zeros Note When the module is above range the value FFFFh plus full scale is returned When the module is below range the value 0000h minus full scale is returned You can use software to convert a twos complement code into voltage Data Transfer DT9840 Series modules generate an interrupt EXT_INT6 when the A D conversions are complete The input samples are loaded into the input FIFO for future transmission over the USB bus to host memory or for onboard digital signal processing All samples must be read from the FIFO before the next A D conversion is done 35 Chapter 1 Error Conditions DT9840 Series modules report an overrun error if the data from the previous A D conversion is not read by the DSP or host computer before anew A D conversion occurs The DSP or host computer must clear this error To avoid this error ensure that the host program reads data from the module as fast as it is being acquired
73. emory 17 110 Memory Space Address Map 110 module addresses 29 module specifications 140 141 142 multiple scan operation mode 24 N Nyquist Theorem 19 O one shot mode 60 operation modes 22 continuous block 26 continuous I O 25 continuous list 26 continuous measure 56 continuous scan 25 function generator output 24 measure mode 55 multiple scan 24 one shot pulse output 60 repetitive one shot pulse output 62 single scan 23 single value 22 standard counting 52 output filters 38 output range 38 outputting pulses one shot 60 repetitive one shot 62 P period count 50 period measurement 55 56 physical specifications 140 142 pin assignments board level version 146 157 EP358E 173 174 EP358E accessory panel 172 J1 on DT9841E 159 Sleek Box version 167 polarity active high 49 active low 49 power input connector 147 158 168 DT9841 151 DT9841E 165 DT9842 2 151 DT9842 8 151 power output connector 148 156 167 DT9842 2 156 DT9842 8 156 power output terminal block DT9841 157 DT9842 2 157 DT9842 8 157 power specifications 140 142 pulse output modes one shot 60 repetitive one shot 62 Index pulse output parameters period count 50 polarity 49 pulse width count 51 pulse train output 53 pulse width count 51 pulse width measurement 55 R range analog input 34 analog output 38 rate generation 53 Read Data Address 117 registers analog input subsystem 85 analog output subsystem 90 Calibrati
74. ently not implemented Connector Pin Assignments Table 33 Counter Timer Connector J19 Pin Assignments on the Sleek Box a Currently the encoder signals are not implemented J13 Pin J13 Pin Assignment Signal Description Assignment Signal Description 1 User Counter Output 2 2 User Clock Input 2 Encoder A22 3 User Counter Output 1 4 User Clock Input 1 Encoder A1 5 User Counter Output 0 6 User Clock Input 0 Encoder A0 7 Isolated Digital Ground 8 Isolated Digital Ground 9 Isolated Digital Ground 10 Isolated Digital Ground 11 Isolated Digital Ground 12 Isolated Digital Ground 13 Reserved 14 External Gate 2 Encoder B2 15 Isolated Digital Ground 16 External Gate 1 Encoder B1 17 Isolated Digital Ground 18 External Gate 0 Encoder B0 19 Isolated Digital Ground 20 Isolated Digital Ground 21 Isolated Digital Ground 22 Isolated Digital Ground 23 Isolated Digital Ground 24 Isolated Digital Ground 25 Isolated Digital Ground 171 Appendix B EP358E Accessory Panel 172 The EP358E accessory panel is provided for DT9841E modules The following connectors are provided on the front of the EP358E accessory panel BNC connectors BNCs labelled CHO and CH1 are provided for attaching two differential analog input signals Analog In Out Connector J1 A 37 pin connector provided for attaching analog I O signals Refer to Table 31 on page 168
75. equired PulseWidthCount is FFFFFFFEh e clks per output pulse FFFFFFFFh 1 PulseWidthCount For example if PulseWidthCount FFFFFFFEh two clocks occur for each output pulse In this example the output is active for counts FFFFFFFFh and 0 output pulse width clks per output pulse x clock period For example if the clock period is 55 55 ns and two clock occur for each output pulse then the output pulse width is 111 11 ns output duty cycle output pulse width output period For example if the output pulse width is 222 2 ns and the output pulse period is 333 3 ns then the output duty cycle is 66 66 Counter Timer Operation Modes DT9840 Series modules support the following counter timer operation modes Standard counting this includes event counting and rate generation e Measure 51 Chapter 1 52 Continuous measure e Up down counting One shot e Repetitive one shot You specify the mode using software The following subsections describe these modes in more detail Standard Counting Specify standard counting if you want to use the counter timer to count events or generate a rate based on a count In event counting applications the counter timer counts pulses from an external C T clock when the enabled gate signal software external normal or external inverted is active Refer to page 43 for more information on the external C T clock source refer to page 45 for more i
76. er 2 has underflowed in up down mode overflowed underflowed in This bit must be cleared set to up down counting mode 0 by the DSP 0 Counter timer 2 has not overflowed underflowed in up down mode 68 Register Description Table 5 Hardware Control and Status Register Address 0xB0000000 cont Bit Register Description Value Type 8 Indicates whether EXT_INT4 1 Enables EXT_INT4 if R W is enabled if counter timer 1 counter timer 1 overflows overflows underflows underflows 0 Disables EXT_INT4 if counter timer 1 overflows underflows 9 Indicates whether 1 Counter timer 1 has overflowed R W counter timer 1 has underflowed in up down mode overflowed underflowed in This bit must be cleared set to up down counting mode 0 by the DSP 0 Counter timer 1 has not overflowed underflowed in up down mode 10 Indicates whether EXT_INT4 1 Enables EXT_INT4 if R W is enabled if counter timer 0 counter timer 0 overflows overflows underflows underflows 0 Disables EXT_INT4 if counter timer 0 overflows underflows 11 Indicates whether 1 Counter timer 0 has overflowed R W counter timer 0 has underflowed in up down mode overflowed underflowed in This bit must be cleared set to up down counting mode 0 by the DSP 0 Counter timer 0 has not overflowed underflowed in up down mode 12 Indicates whether the Scalable 1 Scalable Bus has been R Bus has been addressed or
77. er Description Table 16 SB Control Register Address 0xB0014000 cont Bit Register Description Type 8 1 The FIFO is half full on the slave or the master R when the slave is writing to the Scalable Bus Interrupt EXT_INT7 is asserted for 512 DMA transfers to memory 0 The FIFO is not half full on the Scalable Bus 9 1 The FIFO is not empty on the Scalable Bus After the R transfer is completed this bit must be checked to ensure that all the data has been read 0 The FIFO is empty on the Scalable Bus 10 1 A FIFO error occurred on the Scalable Bus R 0 A FIFO error did not occur on the Scalable Bus 11 1 Transfer request strobe output The slave interrupts R W the master to indicate a transfer request Also used to handshake the three word transfer request to the master Read only for master 0 No transfer request from slave 12 1 Transfer request strobe latch Latches the signal on R W bit 11 0 Clears the transfer request strobe latch 13 1 Latch transfer request Ack In Latches the signal on R W bit 7 0 Clears the latch transfer request 14 1 Enable transfer request interrupt Enable the transfer R W request strobe to generate an interrupt on EXT_INT4 on the master 0 Disable transfer request interrupt 115 Chapter 2 116 Table 16 SB Control Register Address 0xB0014000 cont Bit Register Description
78. er increments Low level External counter Gate Input decrements Signal External C T Clock ui Input Signal The counter is incremented by 3 while the gate is high level on the rising edge of the external clock signal Up counting Down counting operation starts operation starts Figure 9 Example of Up Down Counting One Shot Use one shot mode to generate a single pulse output signal from the counter when the operation is enabled by a either an external normal or inverted gate type Refer to page 45 for more information on gate types You can use this pulse output signal as an external digital TIL trigger to start other operations such as an analog input operation When the operation is enabled the counter begins incrementing When the counter increments to the pulse width count described on page 51 the value of the counter is output The output stays active until the counter rolls over to 0 the terminal count Principles of Operation When the counter reaches the terminal count the output is deactivated and the counter is automatically reloaded with the period count described on page 50 The pulse output then stays inactive and the counter stays disabled All subsequent clock and gate signals are ignored You can specify the polarity of the output signal refer to page 49 for more information In one shot mode the internal C T clock source is more useful than an external C T clock source Refer to page 43 for
79. er input signal Refer to Table 17 on page 151 for more information on this connector Note You must consider the wire size and length before connecting power to connector J11 The module requirement is 5 V 0 25 V at the connector with less than 50 mV pp of ripple The power supply must also be isolated from the computer or from the power commons up to 500 V minimum The following power supply is recommended Total Power International number TPES49 05060KPP 4P or Data Translation EP348 part number 19481 e Connectors J12 and J13 50 pin Scalable Bus connectors for attaching additional DT9840 Series modules Each Scalable Bus connector is set up for intermodule communication at speeds up to 50 MBytes s maximum software rate is 13 MBytes s The first and last modules must use software selectable 100 O termination resistors The data can be clocked out every 40 ns The negative strobe pulse must be 12 ns minimum with the data valid for 10 ns before the rising edge The hold time is 0 ns Refer to Table 18 on page 151 for more information on these connectors e Connectors J15 and J16 The BNC connector labelled 15 is provided for attaching an external clock to the module the BNC connector labelled J16 is provided for attaching an external trigger e Connector J17 a 68 pin connector provided for attaching analog output digital I O and counter timer signals Refer to Table 19 on page 153 for more information on thi
80. er low voltage 0 4 V 10 mA Back EMF diodes Yes 137 Table 7 lists the specifications for the C T subsystems Table 7 C T Subsystem Specifications Feature Specifications Number of counter timer channels Clock Inputs Input type High level input voltage Low level input voltage 5 V tolerant Minimum pulse width Maximum frequency HCT with 22 kQ pull up to 3 3 V 2 4 V minimum 0 8 V maximum Yes 25 ns high 25 ns low 20 MHz Gate Inputs Input type High level input voltage Low level input voltage 5 V tolerant Minimum pulse width HCT with 22 kQ pull up to 3 3 V 2 4 V minimum 0 8 V maximum Yes 25 ns high 25 ns low Counter Outputs Output driver high voltage Output driver low voltage 3 0 V minimum 0 1 mA Source 0 4 V maximum 2 mA Sink Specifications Table 8 lists the specifications for the external clock signal to the DT9840 Series modules Table 8 External Clock Specifications Feature Specifications Input type HCT Rising Edge Sensitive with 22 kQ pull up resistor High level input voltage 2 4 V minimum Low level input voltage 0 8 V maximum Minimum pulse width 9 ns high 9 ns low Maximum frequency DT9841 and DT9841E 51 2 MHz DT9842 2 and DT9842 8 100 kHz a For the DT9841 and DT9841E the conversion rate Clock frequency 512 Table 9 lists the specifications for the external tri
81. erved 14 When 1 sets the module for IEPE operation streaming writes to DIO port 2 are disabled When 0 sets the module for normal operation streaming writes to DIO port 2 are enabled R W 15 For the DT9841 DT9841E and DT9841 VIB when 1 sets the DAC voltage range to 2 5 V when 0 sets the DAC voltage range to 10 V For the DT9842 2 and DT9842 8 this bit is reserved The DAC voltage range is always 10 V R W 16 When 1 enables writing to the digital ports under DMA mode when 0 disables writing to the digital ports under DMA mode R W 17 When 1 the USB cable is connected when 0 the USB cable is not connected 18 DSP heartbeat signal readable by the USB interface without having to go through the host port interface This bit is toggled by the DSP program to indicate the program is running R W 75 Chapter 2 Table 6 Calibration and Setup Register Address 0xB0000004 cont Bit Register Description Type 19 Data input bit for the Xicor potentiometer see also bit 31 20 21 When 1 enables the chip that controls the A D 1 kQ termination resistors see bits 26 and 27 When 0 disables the chip that controls the A D termination resistors For the DT9841 DT9841E and DT9841 VIB data from the D A MDO line For the DT9842 2 and DT9842 8 this bit is reserved R W R W 22 23 For the DT9841 DT9841E
82. erved 52 Reserved 17 Reserved 51 Reserved 16 Reserved 50 Reserved 15 Reserved 49 Reserved 14 Reserved 48 Reserved 13 Reserved 47 Reserved 12 Reserved 46 Reserved 162 Connector Pin Assignments Table 24 Analog Input Connector J2 Pin Assignments on the DT9841E Pin Signal Description Pin Signal Description 11 Reserved 45 Reserved 10 Reserved 44 Reserved 9 Reserved 43 Reserved 8 Reserved 42 Reserved 7 Reserved 41 Reserved 6 Reserved 40 Reserved 5 Reserved 39 Reserved 4 Reserved 38 Reserved 3 Reserved 37 Reserved 2 Amp Low 36 Analog Common 1 5 V Isolated Output 35 Isolated Power Ground Table 25 JTAG Connector J3 Pin Assignments on the DT9841E Pin Signal Name Pin Signal Name 1 DSP TMS 2 DSP TRST N 3 DSP TDI 4 DGND 5 3 3 V 6 Not Connected 7 DSP TDO 8 DGND 9 DSP TCK 10 DGND 11 DSP TCK 12 DGND 13 DSP EMUO 14 DSP_EMU1 163 Appendix B Table 26 Serial Port Connector J4 Pin Assignments on the DT9841E McBSP Internal Pull J4 Signal McBSP McBSP Up or Pull Pin Name Signal Description Pin Function Down 1 CLKS1 External Clock E1 Input Internal Pull Source Down 2 CLKX1 Transmit Clock L3 Input Output Internal Pull Tristate Down 3 DR1 Receive Data M2 Input Internal Pull Up 4 FSX1 Transmit Frame L1 Input Output Internal Pul
83. fied aligning with digital port 0 Additionally you can minimize false triggers due to noise on digital input port 0 by enabling a 10 ms deglitch function using bit 20 of the Hardware Control and Status register described in Table 5 on page 67 All digital inputs are 5 V tolerant All digital outputs include diode protection to isolated ground and isolated 5 V The outputs are disabled on power up and remain in the previous state on USB reset 93 Chapter 2 Counter Timer Subsystem User counter timers 0 1 and 2 provide software selectable clocks gates operation modes and output parameters described in more detail from the register perspective in the following sections This provides the capability to generate rates generate one shots count events and determine the signal pulse width signal period and the time between two signals Table 12 describes the counter timer address map Table 13 describes the User Control registers at addresses 0xB000C020 0xB000C024 and 0xB000C028 and Table 14 describes the User Status register at address 0xB000C030 Note Counter timer 3 is a future option designated as counter 1 in the 6713 chip It is 32 bits wide and the input is gated in software This gate is double pinned on top of bit of port 0 and the input is double pinned on top of bit 1 of port 0 Table 12 Counter Timer Address Map Address Register Description Type 0xB000C000 User Period Register
84. for data acquisition operations in the Microsoft Windows 2000 or Windows XP operating system It is assumed that you have familiarity with data acquisition principles and that you understand your application How this Manual is Organized This manual provides detailed information about the operation of the DT9840 Series modules It is organized as follows Chapter 1 Principles of Operation describes the system features and the features of the analog input analog output digital I O and counter timer subsystems Chapter 2 Register Description describes all the registers that are used to program the DT9840 Series modules Chapter 3 Calibration describes the DT9841 Calibration Utility Appendix A Specifications lists the specifications of the module Appendix B Connector Pin Assignments shows the pin assignments for the connectors and the screw terminal assignments for the module An index completes this manual About this Manual 10 Conventions Used in this Manual The following conventions are used in this manual Notes provide useful information or information that requires special emphasis cautions provide information to help you avoid losing data or damaging your equipment and warnings provide information to help you avoid catastrophic damage to yourself or your equipment Items that you select or type are shown in bold Related Information Refer to the following
85. ful when you want to pace acquisitions at rates not available with the internal sample clock or when you want to synchronize a DT9840 Series module with other devices in your system For the DT9841E module connect the external clock to pin 23 of connector J1 For all other modules connect the external clock to the Ext Clk BNC input on the module Use software to specify the external clock source and to start the sample clock Conversions start on a high to low transition of the external clock signal after a rising edge of the internal calibration signal Principles of Operation DT9841 DT9841E and DT9841 VIB External Clock For the DT9841 DT9841E and DT9841 VIB ensure that the external 1 clock source has a 50 duty cycle The resulting frequency of the external clock input is equal to the frequency of the external clock signal that you connected to the module divided by 256 this division is done internally by the module and must be in the range of 200 Hz to 100 kHz For example if you need a sampling frequency of 100 kHz use an external clock source with a frequency of 25 6 MHz Once the external clock is started the DT9841 DT9841E and DT9841 VIB modules require 37 clock pulses before the first conversion is completed at 100 kHz this delay is 370 us Thereafter the data is converted without delay at 100 kHz sampling occurs every 10 us This initial delay is required by the filtering algorithms of the A D and D A co
86. gger signal to the DT9840 Series modules Table 9 External Trigger Specifications Feature Specifications Input type HCT Rising Edge Sensitive with 22 kQ pull up resistor High level input voltage 2 4 V minimum Low level input voltage 0 8 V maximum Minimum pulse width 50 ns high 50 ns low Maximum frequency 50 0 kHz 139 Appendix A 140 Table 10 lists the power physical and environmental specifications for the DT9840 Series modules Table 10 Power Physical and Environmental Specifications 5 V Isolated Power Out Feature Specifications Power DT9841 VIB 5 V 0 25 V 4 A maximum 3 3 A typical 300 mA maximum for IEPE functions All other DT9840 Series modules 5 A maximum 3 A typical DT9841 VIB 700 mA All other DT9840 Series modules 1 A maximum Physical Dimensions Board Level Version Sleek Box Weight Board Level Version Sleek Box DT9841E 280 x 100 x 22 mm All other DT9840 Series modules 233 35 mm x 220 mm 229 mm L x 247 mm W x 114 mm H DT9841E 0 492 Ib 223 g All other DT9840 Series modules 1 572 lbs 713 g 5 85 lbs 2 654 kg Specifications Table 10 Power Physical and Environmental Specifications cont Feature Specifications Environmental Operating temperature range 0 Cto 55 C Storage temperature range 25 C to 85 C Relative humidity To 95 no
87. he green or orange state to indicate that an error occurred and the debug LEDs CR7 to CR14 turn on You can define the state of the debug LEDs using software 31 Chapter 1 Note Debug LEDs are not supported on DT9841E modules Analog Input Features This section describes the following features specific to the analog input A D subsystem Analog input channels described below e TIEPE functions described on page 33 Input resolution described on page 34 Input range and gain described on page 34 Data formats described on page 35 Data transfer described on page 35 Error conditions described on page 36 Analog Input Channels The DT9841E modules support two analog input channels numbered 0 and 1 All other DT9840 Series modules support eight analog input channels numbered 0 to 7 All analog input channels are simultaneously clocked On the DT9841 and DT9841E these channels are configured as differential inputs on the DT9841 VIB DT9842 2 and DT9842 8 these channels are configured as single ended inputs The DT9841 DT9841E and DT9841 VIB use Delta Sigma analog to digital converters ADCs that provide anti aliasing filters down to 200 Hz based on the clock rate These filters remove aliasing which is a condition where high frequency input components erroneously appear as lower frequencies after sampling 32 Principles of Operation The DT9842 2 and DT9842 8 use successive appro
88. hnical support go to our web site at http www datatranslation com and click on the Support link When requesting technical support be prepared to provide the following information Your product serial number The hardware software product you need help on The version of the CD you are using Your contract number if applicable If you are located outside the USA contact your local distributor see our web site www datatranslation com for the name and telephone number of your nearest distributor 11 About this Manual 12 Principles of Operation Systemi POARUIES ces i555 is eL Moat d reines 17 Analog Input Peabires gt 4 4 k n Rd bee hak e bees ss 32 Analog Output Features iiie eee ree 37 Digital J7 O Peatimes co ii citi n o tee eee 40 Counter Timer Features i 2 ia eee e er enda 42 13 Chapter 1 DT9840 Series modules provide simultaneous analog I O digital I O and counter timer operations on the USB bus The hardware design features an embedded Texas Instruments TMS320C6713 DSP processor that manages I O functions on the module This 300 MHz processor provides float point functionality and supports standard programming tools from Texas Instruments including Code Composer Studio Data Translation provides a library of DSP functions that you can use within a standard Code Composer program to access the functionality of the DT9840 Series modules as well a library of communic
89. ibration Utility to calibrate the analog input subsystem of a DT9841 DT9841E or DT9841 VIB module Connecting a Precision Voltage Source To calibrate the analog input circuitry you need to connect an external 9 3750 V precision voltage source to the analog input channels of a DT9841 DT9841E or DT9841 VIB module Using the Auto Calibration Procedure Auto calibration is the easiest to use and is the recommended calibration method To auto calibrate the analog input subsystem do the following 1 Select the A D Configuration tab of the DT9841 Calibration Utility 2 Inthe Clock Frequency edit box enter a clock frequency between 5 kHz and 100 KHz at which you will be operating the module Note The calibration changes at different clock frequencies so it is important that you specify the clock frequency at which you will be operating the module If you later change the operating clock frequency recalibrate the A D channels 122 Calibration 3 Inthe A D Channel Select section select the A D channels that you want to calibrate by clicking the checkboxes next to the channel numbers Each DT9841 channel must be calibrated separately 4 Click Start Auto Calibration You are prompted to verify that OV is applied to the first selected channel 5 Connect a precision voltage source to the first selected analog input channel verify that 0 V is applied to the channel and then click OK The offset value is cali
90. igital output lines on each pulse of the sample clock Once the operation is started the DSP is not used When you are finished outputting the data use software to stop the operation 24 Principles of Operation Continuous Loop Operations DT9840 Series modules support three types of continuous loop operations Scan loop operations described below Block loop operations described on page 26 List loop operations described on page 26 The most appropriate mode depends on your application Use scan loop mode in control loops and other applications where you need to acquire a sample on every tick of the sample clock and process the data as soon as possible This mode is less efficient than block loop and list loop operations but allows more timely access to the data Block and list loop operations process data in blocks Your program gets called only when an entire block of data has been acquired These modes are more efficient than scan loop but give less frequent access to the incoming data Block and list loop operations are very similar in operation The main difference is that block loop uses only two block buffers which are automatically allocated and managed while list loop uses a linked list of as many buffers as you want but your program must allocate and free each buffer appropriately Scan Loop Operations Use software to start a scan loop operation When it detects a trigger event the module contin
91. in goes from low to high rising edge 47 Chapter 1 48 In continuous measure mode starts the measurement when the signal connected to the external C T clock input goes from low to high rising edge the measurement stops on the next rising edge of the C T clock input signal Falling edge external clock input Starts or stops a measure mode or continuous measure mode operation when the signal connected to the external C T clock input pin goes from high to low falling edge In continuous measure mode starts the measurement when the signal connected to the external C T clock input goes from high to low falling edge the measurement stops on the next falling edge of the C T clock input signal If you want to measure the frequency or period of a signal specify the edges as one of the following Start edge rising Stop edge rising Start edge falling Stop edge falling In measure mode only you can measure the pulse width of a signal by specifying the edges as one of the following Start edge rising Stop edge falling Start edge falling Stop edge rising Note In measure mode and continuous measure mode the internal C T clock is used to calculate the interval of the signal between the specified start and stop edges The pulse width and period count are automatically set to 0 In measure mode you can specify the polarity of the output signal during and after the measurement Principle
92. iption Assignment Signal Description 1 Digital In Out 3 Port 0 2 Digital In Out 2 Port 0 3 Digital In Out 1 Port 0 4 Digital In Out 0 Port 0 5 Digital In Out 3 Port 1 6 Digital In Out 2 Port 1 7 Digital In Out 1 Port 1 8 Digital In Out 0 Port 1 9 Digital In Out 3 Port 23 10 Digital In Out 2 Port 22 TINP15 Encoder 2 Clr 11 Digital In Out 1 Port 28 12 Digital In Out 0 Port 23 Encoder 1 Clr Encoder 0 Clr 13 Isolated Digital Ground 14 Isolated Digital Ground 169 Appendix B 170 Table 32 Digital In Out Connector J2 Pin Assignments on the Sleek Box cont J2 Pin J2 Pin Assignment Signal Description Assignment Signal Description 15 Isolated Digital Ground 16 Isolated Digital Ground 17 Isolated Digital Ground 18 Isolated Digital Ground 19 Reserved 20 Digital In Out 7 Port 0 21 Digital In Out 6 Port 0 22 Digital In Out 5 Port 0 23 Digital In Out 4 Port 0 24 Digital In Out 7 Port 1 25 Digital In Out 6 Port 1 26 Digital In Out 5 Port 1 27 Digital In Out 4 Port 1 28 Digital In Out 7 Port 22 29 Digital In Out 6 Port 22 30 Digital In Out 5 Port 22 31 Digital In Out 4 Port 28 32 Isolated Digital Ground 33 Isolated Digital Ground 34 Isolated Digital Ground 35 Isolated Digital Ground 36 Isolated Digital Ground 37 Isolated Digital Ground a Port 2 is not supported on the DT9841 VIB these signals are reserved for the DT9841 VIB b Curr
93. l Sync Tristate Down 5 DX1 Transmit Data L2 Output Internal Pull Tristate Up 6 FSR1 Receive Frame Sync M3 Input Output Internal Pull Tristate Down 7 CLKR1 Receive Clock M1 Input Output Internal Pull Tristate Down 8 5 V PWR 5 V 25 mA 2 m maximum 9 Digital Ground Ground 10 Digital Ground ES Ground a If you want to access this port for debugging purposes it is recommended that you use the EP354 serial adapter and EP335 serial cable refer to the DT9840 Series Getting Started Manual for connection information and to the DT9840 Series DSP Library User s Manual for information on the serial debugging functions If you want to program this serial port refer to the data sheet for the TMS320C6713 from Texas Instruments for more information 164 Connector Pin Assignments Table 27 USB Connector J6 Pin Assignments on the DT9841E Pin Signal Name Cable Wire 1 5V_USB Red 2 USB D White 3 USB D Green 4 AGND1 Black a This signal is not used USB connector is type B Table 28 Power Input Connector J11 Pin Assignments on the DT9841E Pin Signal Description 1 5 V Input 6 A 2 5 V Input 6A 3 Isolated Power Ground 4 Isolated Power Ground a You must consider the wire size and length before connecting power to connector J11 The module requirement is 5 V 0 25 V at the connector with less than 50 mV pp of ripple The power supply
94. lackhawk emulator Refer to Table 25 on page 163 for more information on this connector Connector J4 a 10 pin D shell connector provided for attaching an RS 232 compliant device for debugging purposes using the EP368 cable EP354 serial adapter and EP335 cable Refer to the DT9840 Series Getting Started Manual for connection information and to the DT9840 Series DSP Library User s Manual for information about the serial debugging functions 157 Appendix B 158 Note When used with the EP368 the J4 connector provides the pin assignments shown in Table 26 on page 164 This serial port serial port 1 McBSP of the DSP can also be programmed for several modes of operation at bit rates of up to 33 Mbps Refer to the data sheet for the TMS320C6713 from Texas Instruments part number SPRS088F for more information on programming the serial port Connector J6 a 4 pin USB connector Refer to Table 27 on page 165 for more information on this connector Connector J11 a 4 pin locking connector provided for attaching an external 5 V power input signal Refer to Table 28 on page 165 for more information on this connector Note You must consider the wire size and length before connecting power to connector J11 The module requirement is 5 V 0 25 V at the connector with less than 50 mV pp of ripple The power supply must also be isolated from the computer or from the power commons up to 500 V minimum The following powe
95. lass A digital device pursuant to Part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his own expense Changes or modifications to this equipment not expressly approved by Data Translation could void your authority to operate the equipment under Part 15 of the FCC Rules Note This product was verified to meet FCC requirements under test conditions that included use of shielded cables and connectors between system components It is important that you use shielded cables and connectors to reduce the possibility of causing interference to radio television and other electronic devices Canadian Department of Communications Statement This digital apparatus does not exceed the Class A limits for radio noise emissions from digital apparatus set out in the Radio Interference Regulations of the Canadian Department of Communications Le pr sent appareil num rique n met pas de bruits radio lectriques d passant les limites applicables aux appareils num riques
96. latile write operation that requires 10 ms before any other operation When the module powers up the values in the RO locations are automatically moved to the WCR location placing the calibration values on the outputs The value stored in location R1 is the backup value for RO Register Description Analog Input Subsystem On the DT9841E the A D subsystem consists of two A D converters that are simultaneously clocked On all other DT9840 Series modules the A D subsystem consists of eight A D converters that are simultaneously clocked On the DT9841 DT9841E and DT9841 VIB the major components of this subsystem are the Delta Sigma A D converters and the sample clock oscillator The Delta Sigma converters remove anti aliasing on the analog inputs and outputs The sample clock MCLK determines the sampling rate at which all analog input channels all digital input channels and all counter timer channels are simultaneously sampled The minimum clock rate is 2 kSamples s once the subsystems have been configured and started For lower sampling rates the DSP chip needs to be set up to discard unneeded samples using a filtering algorithm The maximum clock rate is 100 kSamples s A digital filter is used to scale with the sampling rate On the DT9842 2 and DT9842 8 the major components of this subsystem are the successive approximation A D converters and the sample clock oscillator A 32 bit Clock Divider register address 0xB0000008
97. lling edge clock 48 rising edge 47 rising edge clock 47 edge to edge measurement 55 edge to edge measurements 56 encoding data analog input 35 analog output 39 environmental specifications 140 142 EP358E J201 connector 174 J202 connector 173 179 Index 180 equations event counting 105 output period frequency 106 output pulse width and duty cycle 107 errors analog input 36 analog output 40 event counting 52 external clock 20 43 external clock BNC connector 147 167 122 external clock connector 157 external digital trigger 27 external trigger BNC connector 147 167 172 external trigger connector 157 F falling edge clock input 48 falling edge gate type 47 fan output connector 146 159 DT9841 148 DT9841E 166 DT9842 2 148 DT9842 8 148 filters 38 formatting data analog input 35 analog output 39 frequency external sample clock 21 internal sample clock 18 frequency measurement 55 56 front panel of Sleek Box 167 function generator output 24 G gain analog input 34 analog output 38 gate types 45 inverted 46 logic high level 45 on software 45 H Hardware Control and Status register 67 high to low pulse output 49 l IEPE features 33 input range 34 internal clock 18 cascaded counter timer 44 counter timer 43 interrupts digital I O 41 J J1 connector pin assignments 157 167 172 DT9841E 159 Sleek Box 168 J11 connector pin assignments 147 158 168 DT9841 151 156 DT9841E
98. lock So rces rere eet eie Ped 43 Internal C T Clock 0 0 0 0 ccc RR RR KK eee 43 External C T Clock 2 0 0 0 0 ccc eee 43 Internally Cascaded Clock 000 00008 at Gately pes Em 45 Contents Edge Types ees oce Sint praeit pedet vee ees 47 Pulse Output Parameters n a W K KK KK KK KK KK KK 49 Polatity i Re Re Rb Ee RRE EE E rue 49 Period Count 5 ssec tee eve bae bas 50 Pulse Width Count WWW kk KK KK KK KK esses 51 Counter Timer Operation Modes 04 51 Standard Counting WWW kk kk KK KK KK KK KK KK gt 52 Me asut 219v 4e d nen RR d 43 2 b dne 4 55 Continuous Measure WWW 0 KK RR KK KK KK 56 Up Down Counting saa ke eb na bal 59 OnE Shot ssie 2 a13 a4 l aa pie ga SRI RAE RAP Ayk 60 Repetitive One Shot 000 000 KK KK KK 62 Chapter 2 Register Description 65 USB Bus DSP Hardware Interface 0 00 e cece eee 67 Calibration and Setup 0 0 KK KK KK KK KK KK KK KK KK 75 Setting Up the Xicor Potentiometers suue 78 Calibrating the Analog Input Subsystem 82 Calibrating the Analog Output Subsystem 83 Analog Input Subsystem 0 0 0 0 0 cece eee KK 85 Analog Output Subsystem 0 0 00 0 90 Digital I O Subsystem ss aa tn n n eee 93 Counter Timer Subsystem kk kk kk KK KK KK KK KK KK 94 Counter Timer Operation Modes
99. module acquires one value from a specified channel or outputs one value to a specified channel on the next pulse of the sample clock and then stops Triggers are ignored You can acquire data from an analog input channel digital input line or counter timer channel You can output data to either an analog output channel or a digital output line Principles of Operation Single Scan Operations Use software to perform a single scan operation A DT9840 Series module acquires one input scan record and or outputs one output scan record on the next pulse of the sample clock and then stops Triggers are ignored An input scan record consists of the following information Eight analog input values corresponding to analog input channels 0 1 2 3 4 5 6 and 7 For the DT9841 DT9841E and DT9841 VIB these are 24 values for the DT9842 these are 16 bit values Note The DT9841E supports only two analog input channels 0 and 1 Therefore values for channels 2 through 7 in the input scan record should be ignored One 24 bit value corresponding to all the digital input lines For the DT9841 VIB only 16 bits ports 0 and 1 are accessible One 32 bit value containing the state of the digital input lines For the DT9841 VIB the least significant 16 bits of this 32 bit value correspond to the digital inputs of port 0 and port 1 On all other DT9840 Series modules the least significant 24 bits of this 32 bit value c
100. more information on the internal C T clock source Note In the case of a one shot operation use a duty cycle as close to 100 as possible to output a pulse immediately Using a duty cycle closer to 0 acts as a pulse output delay Figure 10 shows an example of a one shot operation using an external normal gate signal a period count FFFFFFFEh a low to high output pulse polarity and a pulse width count of FFFFFFFEh to achieve a duty cycle of 66 61 Chapter 1 62 One Shot Operation Starts External Gate ar Signal 166 666 ns period 66 duty cycle Pulse Output Signal Figure 10 Example of One Shot Mode Repetitive One Shot Use repetitive one shot mode to clean up a poor clock input signal by changing its pulse width and then outputting it If you specify an external normal or inverted gate type a single pulse is output each time the gate signal is active For example you could set up the counter to output a single pulse each time the gate signal changed from a high to low state Refer to page 45 for more information on gate types Principles of Operation When the operation is enabled with an external gate the counter begins incrementing When the counter increments to the pulse width count described on page 51 the value of the counter is output The output stays active until the counter rolls over to 0 the terminal count The output is then deactivated and the counter is
101. n location R1 is the backup value for RO Calibrating the Analog Output Subsystem To calibrate the DACs on the DT9841 DT9841E and DT9841 VIB do the following 1 Set the DACs to 0 V by writing a code of 00000000h on both DACs 2 Set the EEPOT by incrementing to decrease the output or decrementing to increase the output until the outputs equal 0 00000 V 0 0004 V Each step changes the output by 0 3 mV There are a total of 256 steps Refer to Table 7 on page 79 for the address of each potentiometer 3 Set the full scale by writing a code of 77FFFF00h on both DACs and adjusting the appropriate potentiometers for an output voltage of 9 37500 V 83 Chapter 2 84 To calibrate the DACs on the DT9842 2 and DT9842 8 do the following 1 Set the DACs to 10 V by writing a code of 00000000h to both DACs Set the EEPOT by incrementing to decrease the output or decrementing to increase the output until the outputs equal 10 000 V 0 0004 V Each step changes the output by 0 3 mV There are a total of 256 steps Refer to Table 7 on page 79 for the address of each potentiometer Set the full scale by writing a code of FFFF0000h on both DACs and adjusting the appropriate potentiometers for an output voltage of 9 999695 V Refer to Table 7 on page 79 for the address of each potentiometer To store the D A calibration transfer the contents of PO through P3 to their respective RO through R3 registers This is a nonvo
102. n the external gate signal is low For one shot and repetitive one shot operations enables the operation on the transition from the low level to the high level rising edge and disables the operation on the transition from the high level to the low level falling edge For up down counting mode increments the counter when the external gate signal is high and decrements the counter when the external gate signal is low Refer to page 51 for more information on these modes 45 Chapter 1 46 Inverted external gate input For standard counting operations enables the operation when the external gate signal is low and disables the operation when the external gate signal is high For one shot and repetitive one shot operations enables the operation on the transition from the high level to the low level falling edge and disables the operation on the transition from the low level to the high level rising edge For up down counting mode increments the counter when the external gate signal is low and decrements the counter when the external gate signal is high Table 3 lists the pin assignments of connector J17 on the module that correspond to the external gate input signals Table 3 External Gate Input Signals on the DT9840 Series Modules Counter Timer Gate Signal J17 Pin Number External Gate 0 39 External Gate 1 37 External Gate 2 35 Principles of Operation Edge Types
103. n will turn on with an onboard temperature sensor if the DT9840 Series module exceeds 45 C If the module exceeds 60 C an interrupt is generated The following fan is recommended Sunon model number KDE0505PFB3 8GN or Data Translation part number 19372 Refer to Table 13 on page 148 for more information on this connector Connector J3 a 14 pin connector provided for a JTAG device such as a Blackhawk emulator Refer to Table 14 on page 149 for more information on this connector e Connector J4 a 9 pin D shell connector provided for attaching an RS 232 compliant device for debugging purposes using the EP354 serial adapter and EP335 cable Refer to the DT9840 Series Getting Started Manual for connection information and to the DT9840 Series DSP Library User s Manual for information about the serial debugging functions Note Refer to Table 15 on page 149 for more information on the pin assignments for this connector This serial port serial port 1 McBSP of the DSP can also be programmed for several modes of operation at bit rates of up to 33 Mbps Refer to the data sheet for the TMS320C6713 from Texas Instruments part number SPRS088F for more information on programming the serial port e Connector J6 a 4 pin USB connector Refer to Table 16 on page 150 for more information on this connector 146 Connector Pin Assignments e Connector J11 a 4 pin locking connector provided for attaching an external 5 V pow
104. ncondensing Altitude 10 000 feet Table 11 lists the regulatory specifications for the DT9840 Series modules Table 11 Regulatory Specifications Feature Specifications EMI FCC part 15 class A EN 55022 1994 based on CISPR 22 1993 EN 50082 1 1998 IEC 801 2 1984 8 KV air 4 KV contact IEC 801 3 3 V m from 27 to 500 MHz IEC 801 4 1 KV coupled to AC lines 0 5 KV coupled to I O lines VCCI Japan version of CISPR 22 Safety UL CSA RoHS EU Directive 2002 95 EG Compliant as of July 1st 2006 141 Appendix A Table 12 lists the specifications for the connectors on the DT9840 Series modules Sleek Box EP358E and EP342 and EP344 cables Table 12 DT9840 Series Connector Specifications Connector Part Mating Connector Product Connector Number Part Number Sleek Box Analog Input J1 AMP Tyco 5747375 8 AMP Tyco 5 747917 2 Digital I O J2 AMP Tyco 5747301 8 AMP Tyco 5 747916 2 Counter Timer J19 AMP Tyco 5745967 8 AMP Tyco 5 747912 2 J201 and J202 AMP Tyco 6 104068 8 AMP Tyco 3 111196 4 behind front panel Scalable Bus J12 and 3M N10250 52E2PC 3M 10150 6000EC J13 Serial Port J4 AMP Tyco 5747844 4 AMP Tyco 5 747904 2 5 V Power Input J1 15 Kycon KPJX 4S S Kycon KPPX 4P USB J6 AMP Tyco 292304 2 Data Translation EP365 USB cable or AMP Tyco 1487588 3 DT9841 TB38 Ext Fan PCD ELVH02500 PCD ELVP02100 DT9842 2 TB4 5 V Power O
105. nformation on gate types Since each counter timer is 32 bits you can count from 1 to FFFFFFFFh events before the counter rolls over to 0 and starts counting again You can read the value of the counter at any time Using the period count described on page 50 you can specify the initial count that is loaded into the counter timer the counter timer starts counting from this value Using the pulse width count described on page 51 you can specify the count at which the counter timer stops counting when the counter reaches this value a pulse is output from the counter timer You can specify the polarity of this output pulse as described on page 49 Figure 5 shows an example of an event counting operation using an normal external gate type Principles of Operation External Gate Input Signal High level enables operation Low level disables operation External C T Clock Input Signal 3 events are counted while the operation is enabled on the rising edge of the external clock signal Event counting Event countin g operation stops operation starts Figure 5 Example of Event Counting In rate generation applications a pulse output signal is output from the counter continuously this mode is sometimes referred to as continuous pulse output or pulse train output You can use this pulse output signal as an external clock to pace other operations such as
106. nly you can configure the termination resistance in software on a channel by channel basis The input signal range is 10 V Software selectable output filters of 5 kHz and 20 kHz are available Software selectable output ranges of 10 V and 2 5 V are available The DT9841 VIB supports IEPE functions on the analog input channels The DT9841 VIB module has two 8 bit digital I O ports where the standard DT9841 product has three 8 bit digital I O ports The output signal range is 10 V This chapter describes the operation of the DT9840 Series modules from a hardware perspective Figure 1 shows a block diagram of the DT9840 Series hardware architecture to frame the discussion in this chapter Note that bold entries indicate signals you can access For more detailed register level information refer to Chapter 2 starting on page 65 15 Chapter 1 USB Interface ID ROM 128 Kx8 SRAM Input FIFO 9 d e Isolated External SI us 9 Bo 9 5 2 52 i La 5 V Power C5 i onverter 5 d ELZA 6 500 V Isolation Barrier l y y y Programmable FP Clock Up to 24 Isolation ij Digital I O Interface Lines and ud aie Clock 3 Counter a Logic qp
107. nment Signal Description 1 Analog Input 00 2 Analog Input 01 3 Analog Input 02 4 Analog Input 03 5 Analog Input 04 6 Analog Input 05 7 Analog Input 06 8 Analog Input 07 9 Analog Common 10 Analog Output 00 11 Analog Output 01 12 Analog Output 022 13 Analog Output 032 14 Analog Output 042 15 Analog Output 052 16 Analog Output 062 17 Analog Output 072 18 Analog Common 19 Reserved 20 Analog Input 00 Return 21 Analog Input 01 Return 22 Analog Input 02 Return 23 Analog Input 03 Return 24 Analog Input 04 Return 25 Analog Input 05 Return 26 Analog Input 06 Return 27 Analog Input 07 Return 28 Analog Common 168 Connector Pin Assignments Table 31 Analog In Out Connector J1 Pin Assignments on the Sleek Box J1 Pin J1 Pin Assignment Signal Description Assignment Signal Description 29 Analog Output 00 Return 30 Analog Output 01 Return 31 Analog Output 02 Return 32 Analog Output 03 Return 33 Analog Output 04 Return 34 Analog Output 05 Return 35 Analog Output 06 Return 36 Analog Output 07 Return 37 Analog Common a Available on the DT9842 8 module only For all other modules these signals are reserved b For the DT9841 VIB DT9842 2 and DT9842 8 which have single ended analog inputs these signals are analog grounds Table 32 Digital In Out Connector J2 Pin Assignments on the Sleek Box J2 Pin J2 Pin Assignment Signal Descr
108. ntinuous measure mode uses the internal clock to measure the period of a signal on the external gate or external clock input When the next edge is detected the counter resets to 1 and starts counting again Either a rising edge or falling edge can be used The measurement count is latched and can be read from the CGL address of the counter Setting bit 17 in the User Control registers described in Table 13 starting on page 96 clears the measurement count after it is read and stays cleared until the next measurement is complete Up Down In Up Down mode the counter increments if the selected gate is active or decrements if the selected gate is inactive on the rising edge of the clock This mode should be used only with an external clock and external gate normal or inverted This mode is useful in monitoring the position of an object that can move in two directions such as a lift on a shaker table This mode does not support cascaded clocks Register Description The counter should be initialized such that the counter never increments beyond FFFFFFFFh or decrements below 0 Up down mode should be used only when the position of the object being monitored stays within the range of the counter as the operation is not be reliable if the counter increments above FFFFFFFh or decrements below 0 Count Sequence The period register contains the initial count for the counter When the host writes to the period register the value
109. nverters DT9842 2 and DT9842 8 External Clock Because the DT9842 2 and DT9842 8 use successive approximation A D converters and provide no inherent filtering no initial delay occurs like on the DT9841 DT9841E and DT9841 VIB Therefore the resulting frequency of the external clock input is equal to the frequency of the external clock signal that you connected to the module Scalable Bus Master Clock Note The Scalable Bus is not supported by DT9841E modules Use the Scalable Bus Master Clock source only if you are using the Scalable Bus to connect multiple modules and you want to synchronize their operation Refer to page 29 for more information on Scalable Bus operations 21 Chapter 1 22 In this configuration the clock internal trigger and reset signals are provided to the slave modules from the master DT9840 Series module through the Scalable Bus You can configure the master module to use either an internal or external clock source The Ext Clk BNC connector on the slaves is not used Operation Modes DT9840 Series modules support the following operation modes Single value described below Single scan described on page 23 Multiple scan input described on page 24 Function generator output described on page 24 Continuous loop operations scan loop block loop and list loop described on page 25 Single Value Operations Use software to perform a single value operation A DT9840 Series
110. o perform a measurement This bit resets to 0 on power up or counter timer reset 1 Measure Enabled This bit is set when the host writes 1 to the user measure trigger enable command bit of the control register This bit is cleared by the core at the completion of the measurement It is also cleared when the host writes 0 to the user measure trigger enable command bit of the control register 101 Chapter 2 Table 14 User Status Register Address 0xB000C030 cont Bit Register Description Value Type 5 User Counter 1 Measure 0 Measure Disabled R Enable Flag 1 Measure Enabled This signal indicates whether This bit is set when the host writes user counter timer 1 is 1 to the user measure trigger enabled to perform a enable command bit of the control measurement This bit resets register This bit is cleared by the to 0 on power up or core at the completion of the counter timer reset measurement It is also cleared when the host writes 0 to the user measure trigger enable command bit of the control register 6 User Counter 2 Measure 0 Measure Disabled R Enable Flag 1 Measure Enabled This signal indicates whether This bit is set when the host writes user counter timer 2 is 1 to the user measure trigger enabled to perform a enable command bit of the control measurement This bit resets register This bit is cleared by the to 0 on power up or core at the completion of the
111. o the following subsections for more information on each of these clock sources Internal C T Clock The internal C T clock uses a 18 MHz time base Counter timer operations start on the rising edge of the clock input signal External C T Clock An external C T clock is useful when you want to pace counter timer operations at rates not available with the internal C T clock or if you want to pace at uneven intervals Counter timer operations start on the rising edge of the clock input signal Table 2 lists the pin assignments of connector J17 on the module that correspond to the external C T clock input signals Table 2 External C T Clock Signals on the DT9840 Series Modules Counter Timer Signal J17 Pin Number User Clock Input 0 6 User Clock Input 1 4 User Clock Input 2 2 43 Chapter 1 Note For the DT9841 VIB the clock input signal of counter timer 0 is also brought out to a BNC on the face plate CTO Clock If you want to use this signal for a tachometer input ensure that you condition your signal to a TTL input and configure your counter timer for continuous measure mode Internally Cascaded Clock You can use software to internally route or cascade the clock input signal from a specified counter timer to the clock output signal of the proceeding counter timer without externally connecting two counters together For example if you specify a cascaded clock source for c
112. ommand using the User Control registers described in Table 13 on page 96 The user counter timer waits for an active gate trigger to begin counting To initialize a counter timer subsystem for a software triggered one shot operation do the following 1 Select logic low for the gate source using the User Control registers described in Table 13 on page 96 2 Select the desired mode output polarity and clock source using the User Control register described in Table 13 on page 96 3 Load the User Period registers described in Table 12 on page 94 with the desired value 4 Load the User Pulse registers described in Table 12 on page 94 with the desired value 5 Issue a one shot trigger enable command using the User Control registers described in Table 13 on page 96 The user counter timer waits for an active gate logic high to begin counting 6 Select logic high for the gate source using the User Control registers described in Table 13 on page 96 The counter begins counting 109 Chapter 2 Memory All modules have 128 MBytes of SDRAM starting at address 0x80000000 through 0x81F40000 on the TMS230C6713 Additionally 2 MB of flash memory starts at 0x90000000 1 M x 16 This setup information is in the chip support library of Code Composer Studio Table 15 describes the memory space address map Table 15 Memory Space Address Map Address Register Description Type 0x80000000 SDRAM configu
113. on and Setup 75 Counter Timer Address Map 94 counter timer subsystem 94 D A Address Map 92 digital I O subsystem 93 DMA Address Map 87 Hardware Control and Status 67 Memory Space Address 110 Read Data Address 117 SB Control 114 User Control 96 User Status 100 Write Data Address 117 regulatory 141 repetitive one shot mode 62 resolution analog input 34 analog output 38 rising edge clock input 47 rising edge gate type 47 S sample clock 18 sample rate 26 SB Control register 114 Scalable Bus 113 connections 29 master clock 21 Scalable Bus connectors 147 168 Scalable Bus pin assignments DT9841 151 DT9842 2 151 DT9842 8 151 screw terminal block TB1 DT9841 157 DT9842 2 157 DT9842 8 157 screw terminal blocks board level version 148 Sleek Box 167 screw terminal TB2 assignments 158 screw terminal TB3 assignments 159 secondary power connector 158 secondary power connector DT9841E 166 serial port connector 146 157 168 DT9841 149 DT9841E 164 DT9842 2 149 DT9842 8 149 single scan operation mode 23 single value operation mode 22 size module 140 slave modules 29 183 Index 184 Sleek Box back panel pin assignments 168 front panel pin assignments 167 172 software trigger 27 specifications 129 analog input 130 analog output 134 counter timer 138 digital input 136 digital output 137 environmental 140 142 physical 140 142 power 140 142 regulatory 141 subsystem descriptions analog input 32 analog outp
114. on each slave module Refer to the DT 9840 Series Getting Started Manual for more information on attaching signals Principles of Operation For asynchronous operation you can set the clock source for both the master and slave modules to either internal or external but not to Scalable Bus master Each module is then clocked and triggered separately you can communicate with all the modules on the bus using software You can perform the following communication operations on the Scalable Bus using software e Return the address of slave modules Determine whether the module is ready for data transfer e Allocate and deallocate buffers for data transfer Initiate transfer requests from the slave Transfer data and messages from the master to the slave LEDs LED CR6 on the DT9841E module and LED CR1 on the back of all other DT9840 Series modules is a two color device that indicates the state of the DT9840 Series module Refer to the DT9840 Series Getting Started Manual for the location of this LED When power is applied to the module this LED turns green When the module is recognized by the host and the firmware is downloaded to the module the LED turns red When the Windows driver is loaded and started the LED turns orange The module is then ready for use When you download and run your DSP program this LED flashes green and orange If the downloaded program stops running this LED turns stops flashing in either t
115. ons cont Connector Part Mating Connector to the DT9840 Series module or Sleek Box Product Connector Number Part Number EP344 Both connectors AMP Tyco 3 111196 4 AMP Tyco 6 104068 8 EP354 Connector that attaches AMP Tyco 5 747904 2 AMP Tyco 5747844 4 Connector that attaches to the EP335 cable AMP Tyco 747905 7 Male 9 pin D sub connector of the EP335 cable a The following fan is recommended for use withTB3 Sunon model number KDE0505PFB3 8GN b The following power supply is recommended Total Power International model number TPES49 05060KPP 4P or Data Translation part number 19481 EP348 c This cable which is included with the EP354 serial adapter is also available as an off the shelf product from Assmann part number AK131 2 R This cable has a male 9 pin D sub connector on one end and a female 9 pin D sub connector on the other end Connector Pin Assignments DT9841 DT9842 2 and DT9842 8 Modules 146 D ISS4TE Module assess kk a k y ARINA kk kk 157 Sleek Box Front Panel i sk kk ks ks sk kk e kk kal klklk ak 167 EPJGOE Accessory Panel sin ioco k l n e Pee ers Kul 172 145 Appendix B DT9841 DT9842 2 and DT9842 8 Modules The DT9841 DT9842 2 and DT9842 8 modules provide the following connectors e Connector J2 a 2 pin connector provided for attaching an external 5 VDC 100 mA fan output signal The fa
116. ont Pin Signal Description Pin Signal Description 11 Reserved 45 Reserved 10 Reserved 44 Reserved 9 Reserved 43 Reserved 8 Reserved 42 Reserved 7 Reserved 41 Reserved 6 Reserved 40 Reserved 5 Reserved 39 Reserved 4 Reserved 38 Reserved 3 Reserved 37 Reserved 2 Amp Low 36 Analog Common 1 5 V Isolated Output 35 Isolated Power Ground a For the DT9842 2 and DT9842 8 which have single ended analog inputs these signals are analog grounds 156 Table 21 Power Output Connector J19 Pin Assignments Pin Signal Description 1 5 V Output 1 A 2 Isolated Power Ground a Fused at 1 A with a poly fuse Connector Pin Assignments Table 22 Power Output Screw Terminal Block TB1 a Fused at 1 A with a poly fuse Pin Signal Description 1 5 V Output 1 A 2 Isolated Power Ground DT9841E Module The DT9841E module provides the following connectors Connector J1 a 68 pin connector provided for attaching analog output digital I O and counter timer signals as well as an external clock and external trigger input Refer to Table 23 on page 159 for more information on this connector Connector J2 a 68 pin connector provided for attaching analog input signals Refer to Table 24 on page 162 for more information on this connector Connector J3 a 14 pin connector provided for a JTAG device such as a B
117. orrespond to the digital inputs of port 0 port 1 and port 2 Three 32 bit values corresponding to counter timer channels 0 1 and 2 23 Chapter 1 An output scan record consists of the following information For the DT9841 DT9841E and DT9841 VIB two 24 bit values corresponding to analog output channel 0 and 1 For the DT9842 2 two 16 bit values corresponding to analog output channel 0 and 1 For the DT9842 8 eight 16 bit values corresponding to analog output channels 0 to 7 One 24 bit value corresponding to all the digital output lines Multiple Scan Input Operations Use software to perform a multiple scan input operation When it detects a trigger event the DT9840 Series module acquires a specified number of input scan records and then stops An input scan record is acquired on each pulse of the sample clock refer to page 23 for more information on input scan records This is a synchronous operation therefore you cannot perform any other operation while this operation is in process Function Generator Output Operations Use software to start a function generator output operation When it detects an initial trigger the DT9840 Series module outputs a buffer that contains a specified number of output scan records Refer to page 23 for more information on output scan records The module continuously outputs the data in the output scan records from the buffer in memory to the analog output channels and or d
118. ounter timer 2 the clock input of counter timer 2 is internally connected to the clock output of counter timer 1 The C T clock input source for counter timer 1 can be an internal or external C T clock input source or you can cascade counter timer 1 to counter timer 0 if you wish The rising edge of the clock input signal is active Note You cannot select a cascaded clock for counter timer 0 since there is no lower counter timer with which to cascade If you cascade counters you must read the value of each counter timer separately and add the values together For example if counter timers 0 and 1 are cascaded the cascaded count Ctr 0 Ctr1 222 Principles of Operation Gate Types The active edge or level of the gate input signal of the counter enables counter timer operations Note The gate type is ignored for measure mode and continuous measure mode operations Refer to page 55 for more information on measure mode Refer to page 56 for more information on continuous measure mode DT9840 Series modules provide the following gate input types e On A software command enables a specified counter timer operation immediately after execution This gate type is not supported for up down counting one shot or repetitive one shot operations e Normal external gate input For standard counting operations enables the operation when the external gate signal is high and disables the operation whe
119. period register is loaded by the host User Counter 1 One Shot 0 One Shot Triggers Disabled R Trigger Enable Flag This flag indicates whether user counter 1 is enabled to detect one shot triggers This bit resets to 0 on power up or counter timer reset 1 One Shot Triggers Enabled This bit is set when the host writes 1 to the user one shot trigger enable command bit of the control register This bit is cleared by the core at the completion of the one shot pulse if the counter is in non retriggerable one shot mode It is also cleared when the user period register is loaded by the host Register Description Table 14 User Status Register Address 0xB000C030 cont Bit Register Description Value Type User Counter 2 One Shot 0 One Shot Triggers Disabled R Trigger Enable Flag 1 One Shot Triggers Enabled This flag indicates whether This bit is set when the host writes user counter 2 is enabled to 1 to the user one shot trigger detect one shot triggers This enable command bit of the control bit resets to 0 on power up or register This bit is cleared by the counter timer reset core at the completion of the one shot pulse if the counter is in non retriggerable one shot mode It is also cleared when the user period register is loaded by the host Reserved us User Counter 0 Measure 0 Measure Disabled R Enable Flag This signal indicates whether user counter timer 0 is enabled t
120. polarity for the user output This bit resets to 0 on power up or Counter Timer Reset 1 High Active Bit Register Description Value Type 1 0 User Clock Select 1 0 Bit 1 Bit 0 Ww These bits specify the clock 0 0 Internal 18 MHz Clock for the user counter timer 0 1 External Clock These bits resets to 00 on 1 0 Cascaded Clock power up or Counter Timer 1 1 Reserved reset 3 2 User Gate Select 1 0 Bit 3 Bit 2 W These bits specify the gate 0 0 Logic Low disabled for the user counter These 0 1 Logic High enabled bits reset to 00 on power up 1 0 External Gate high or Counter Timer reset active 1 1 External Gate Inverted low active 5 4 User Mode Select 1 0 Bit 5 Bit4 W These bits specify the mode 0 0 Non retriggerable for the user counter These One Shot bits reset to 00 on power up 0 1 Retriggerable One Shot or Counter Timer reset 1 0 Continuous Increment 1 1 Auxiliary see aux mode select bits 6 User Output Polarity 0 Low Active W 96 Register Description Table 13 User Control Registers Addresses 0xB000C020 0xB000C024 0xB000C028 cont Bit Register Description Value Type 7 User One Shot Trigger 0 One shot triggers disabled W Enable Command 1 One shot triggers enabled The host should set up all the features characteristics of the counter before issuing this command 9 8 User Aux Mode Select 1 0 Bit 9 Bit8 W These bits specify the 0
121. ption Digital l O Subsystem The DT9841 VIB provide 16 digital I O signals ports 0 and 1 Bit 0 of digital port 2 is used as the SCL clock and bit 1 of digital port 2 is used as the SDA data output the remaining bits 2 7 of digital port 2 are reserved You must turn streaming writes to digital port 2 off see page 75 for more information All other DT9840 Series modules provide 24 digital I O signals ports 0 1 and 2 You can program each port for input or output using bits 17 18 and 19 of the Hardware Control and Status register described in Table 5 on page 67 As inputs the data on the ports is sampled at 25 MHz To read all the digital ports at once use register 0xB0004020 To write to all the digital ports at once use register 0xB0008008 To read or write to digital port 0 only use register 0xB0010004 To read or write to digital port 1 only use register 0xB0010008 To read or write to digital port 2 only use register OxB001000C Refer to Table 15 on page 110 for more information on these registers When port 0 is configured as an input port you can program the mask register located at address 0xB0010000 to generate an interrupt when any bit of port 0 changes state In this mode the sample rate changes to 1 MHz Refer to Table 15 on page 110 for more information on this register To enable the interrupt set bit 21 of the Hardware Control and Status register described in Table 5 on page 67 The data is right justi
122. put 5 Port 0 51 Digital Input Output 6 Port 0 52 Digital Input Output 7 Port 0 53 Isolated Digital Ground 54 Isolated Digital Ground 55 Isolated Digital Ground 56 Isolated Digital Ground 57 Isolated Digital Ground 58 Isolated Digital Ground 59 Isolated Digital Ground 60 Isolated Digital Ground 61 Reserved 62 Reserved 63 Reserved 64 Reserved 65 Reserved 66 Reserved 67 Analog Output 01 Return 68 Analog Output 00 Return a Currently not implemented 176 A address flags 89 address LEDs 74 116 addresses 29 aliasing 19 analog I O connector 167 172 Sleek Box 168 analog input BNC connector 167 172 analog input connector 148 157 DT9841 155 DT9841E 162 DT9842 2 155 DT9842 8 155 analog input features 32 calibrating 122 channels 32 data format 35 data transfer 35 error conditions 36 gain 34 IEPE functions 33 input range 34 registers 85 resolution 34 specifications 130 analog output BNC connector 167 172 analog output features 37 calibrating 126 channels 37 data format 39 data transfer 39 error conditions 40 Index gain 38 output filters 38 output range 38 registers 90 resolution 38 specifications 134 analog output underflow error 40 analog output digital I O and counter timer connector 147 157 DT9841 153 DT9842 2 153 DT9842 8 153 analog output digital I O counter timer ext trig ext clock connector DT9841E 159 B back panel of Sleek Box 168 BNC connectors analog input 167
123. r supply is recommended Total Power International number TPES49 05060KPP 4P or Data Translation EP348 part number 19481 Screw Terminal Block TB2 a 3 position screw terminal block provided for attaching a 5 V power supply You can use this screw terminal block instead of connector J11 to provide power to the module Refer to Table 29 on page 166 for more information on this screw terminal block Connector Pin Assignments Screw Terminal Block TB3 a 2 position screw terminal block provided for attaching an external 5 VDC 100 mA fan output signal The fan will turn on with an onboard temperature sensor if the DT9841E module exceeds 45 C If the module exceeds 60 C an interrupt is generated The following fan is recommended Sunon model number KDE0505PFB3 8GN or Data Translation part number 19372 Refer to Table 30 on page 166 for more information on this screw terminal block Table 23 Analog Output Digital I O Counter Timer Ext Trig Ext Clock Connector J1 Pin Assignments on the DT9841E Pin Signal Description Pin Signal Description 34 Analog Output 00 68 Analog Output 00 Return 33 Analog Output 01 67 Analog Output 01 Return 32 Reserved 66 Reserved 31 Reserved 65 Reserved 30 Reserved 64 Reserved 29 Reserved 63 Reserved 28 Reserved 62 Reserved 27 Reserved 61 Reserved 26 External D A Trigger 60 Isolated Digital Ground 25 External D A Clock 59 Isolated Digit
124. ration changes at different clock frequencies so it is important that you specify the clock frequency at which you will be operating the module If you later change the operating clock frequency recalibrate the A D channels 2 Inthe Manual Calibration section select an A D channel to calibrate 3 Adjust the offset as follows r Verify that 0 V is applied to the selected channel The current voltage reading for this channel is displayed in the A D Value window s Adjustthe offset by entering values between 0 and 255 in the Offset edit box or by clicking the up down buttons until the A D Value is 0 000 V 124 Calibration 4 Adjust the gain as follows a Verify that 9 375V is applied to the selected A D channel The current voltage reading for this channel is displayed in the A D Value window b Adjust the gain by entering values between 0 and 255 in the Gain edit box or by clicking the up down buttons until the A D Value is 9 3750 5 Repeat steps 2 through 4 for each A D channel that you wish to calibrate manually Note At any time you can click Restore Factory Settings to reset the A D calibration values of the selected channels only to their original factory settings This process will undo any auto or manual calibration settings Once you have finished this procedure continue with Calibrating the Analog Output Subsystem on page 126 125 Chapter 3 126 Calibrating the An
125. red in the CDB file CEO R W 0x90000000 SDRAM1 configured in the CDB file CE1 R W 0xB0000000 Hardware Control and Status Register CE3 R W 0xB0000004 Serial Control Calibration Termination R W Register 0xB0000008 Clock Divider Register on DT9842 2 and RAN DT9842 8 modules only 0xB0001000 Board ID upper 16 bits and FPGA revision R lower 16 bits 0xB0004000 A D Data Channel 0 Left Justified Data 0xB0004004 A D Data Channel 1 Left Justified Data 0xB0004008 A D Data Channel 2 Left Justified Data 0xB000400C A D Data Channel 3 Left Justified Data 0xB0004010 A D Data Channel 4 Left Justified Data 0xB0004014 A D Data Channel 5 Left Justified Data 0xB0004018 A D Data Channel 6 Left Justified Data DID D D D D D D 0xB000401C A D Data Channel 7 Left Justified Data 110 Register Description Table 15 Memory Space Address Map cont Address Register Description Type 0xB0004020 Flags Digital Port 2b Digital Port 1 R Digital Port 0 0xB0004024 Counter Timer 0 R 0xB0004028 Counter Timer 1 R 0xB000402C Counter Timer 2 R 0xB0004030 Firmware Debug R W 0xB0008000 D A Data 0 Left Justified Data WwW 0xB0008004 D A Data 1 Left Justified Data W 0xB0008008 Reserved Os Digital Port 2 Digital Port 1 W Digital Port 0 0xB000C000 User Period Register 0 Counter
126. riod For example if the output period is 166 666 ns then the output frequency is 6 0 MHz Period reg FFFFFFFFh 2 clock frequency output frequency For example if the clock frequency is 18 MHz and the desired output frequency is 6 0 MHz the required period_reg is FFFFFFFEh 106 Register Description Output Pulse Width and Duty Cycle Equations The following equations relate to the output pulse width and duty cycle clks per output pulse FFFFFFFFh 1 pulse reg Da For example if pulse_reg FFFFFFFEh two clocks occur for each output pulse In this example the output is active for counts FFFFFFFFh and 0 Output pulse width clks per output pulse x clock period For example if the clock period is 55 55 ns and two clock occur for each output pulse then the output pulse width is 111 11 ns Output duty cycle output pulse width output period For example if the output pulse width is 222 2 ns and the output pulse period is 333 3 ns then the output duty cycle is 0 66 66 Pulse reg FFFFFFFFh 1 duty cycle x clock frequency output frequency For example if the clock frequency is 18 MHz the output frequency is 6 0 MHz and the desired duty cycle is 2 3 66 then the required pulse_reg is FFFFFFFEh 107 Chapter 2 Counter Initialization To initialize a counter timer subsystem for continuous incrementing do the following 1 Select logic low for the gate source
127. s twos complement Interrupt EXT INT6 is asserted to the DSP chip when the conversion is completed A D Done and the data is ready INT6 pin D2 This interrupt initiates a DMA transfer on DMA channel 6 The acquired data is stored in the input FIFO and either sent to the DSP for further processing or to host memory over the USB bus All samples must be read before the next A D Done An orderly stop is done when the DSP firmware stops sending data to the host but leaves the A D running discarding new data This allows the module to transfer the last sample to the host or memory and restart data collection without performing another calibration The A D error bit bit 27 of the Hardware Control and Status register described in Table 5 on page 67 is set if the A D clock is set faster than the A D converter specification or if the data was not read fast enough by the DSP or host This error must be cleared by the DSP or host Table 9 describes the DMA address map Table 9 DMA Address Map Address Register Description Type 0xB0004000 A D Data 0 above physical R memory read only 0xB0004004 A D Data 1 0xB0004008 A D Data 28 0xB000400C A D Data 3 DiD DdD JJ 0xB0004010 A D Data 4 87 Chapter 2 Table 9 DMA Address Map cont Address Register Description Type 0xB0004014 A D Data 5 R 0xB0004018 A D Data 6 R 0xB000401C A D Data 72 R 0xB0004020
128. s connector 147 Appendix B 148 e Connector J18 a 68 pin connector provided for attaching analog input signals Refer to Table 20 on page 155 for more information on this connector Connector J19 a 2 pin connector provided for attaching and external 5 V output signal Refer to Table 21 on page 156 for more information on this connector Note You can use the 2 position terminal block TB1 instead of connector J19 if you wish Screw terminal block TB1 is provided for attaching an external 5 V power output signal Refer to Table 22 on page 157 for more information on the screw terminal block assignments Note You can use connector J19 instead of screw terminal block TB1 if you wish Table 13 Fan Output Connector J2 Pin Assignments Pin Signal Name 1 Fan 2 Fan a These signals are provided for attaching an external 5 VDC 100 mA fan output signal The fan will turn on with an onboard temperature sensor if the DT9840 Series module exceeds 45 C If the module exceeds 60 C an interrupt is generated The following fan is recommended Sunon model number KDE0505PFB3 8GN or Data Translation part number 19372 Connector Pin Assignments Table 14 JTAG Connector J3 Pin Assignments Pin Signal Name Pin Signal Name 1 DSP_TMS 2 DSP_TRST_N 3 DSP_TDI 4 DGND 5 43 3 V 6 Not Connected 7 DSP TDO 8 DGND
129. s of Operation Pulse Output Parameters DT9840 Series modules can output pulses from each counter timer Table 4 lists the pin assignments of connector J17 on the module that correspond to the pulse output signals Table 4 Pulse Output Signals on the DT9840 Series Modules Counter Timer Pulse Output Signal J17 Pin Number Counter Output 0 5 Counter Output 1 3 Counter Output 2 1 You can specify the following pulse width parameters using software Polarity described below Period count described on page 50 Pulse width count described on page 51 Polarity You can specify one of the following values for the polarity of the pulse output signal Active high low to high transitions The high portion of the total pulse output period is the active portion of the counter timer pulse output signal Active low high to low transitions The low portion of the total pulse output period is the active portion of the counter timer clock output signal 49 Chapter 1 Period Count By specifying the period count you can determine the frequency of the pulse output signal Note You can also use the period count in event counting operations to determine the value at which the counter timer starts counting The period count defines the initial value that is loaded into the specified counter timer Values range from 1 to FFFFFFFFh The counter timer counts from the period count to F
130. solated Digital Ground 24 External A D Trigger 58 Isolated Digital Ground 23 External A D Clock 57 Isolated Digital Ground 22 Digital Input Trigger 56 Isolated Digital Ground 21 Digital Input Clock 55 Isolated Digital Ground 20 Digital Output Trigger 54 Isolated Digital Ground 19 Digital Output Clock 53 Isolated Digital Ground 18 Digital Input Output 3 Port 0 52 Digital Input Output 7 Port 0 17 Digital Input Output 2 Port 0 51 Digital Input Output 6 Port 0 16 Digital Input Output 1 Port 0 50 Digital Input Output 5 Port 0 15 Digital Input Output 0 Port 0 49 Digital Input Output 4 Port 0 14 Digital Input Output 3 Port 1 48 Digital Input Output 7 Port 1 13 Digital Input Output 2 Port 1 47 Digital Input Output 6 Port 1 153 Appendix B 154 Table 19 Analog Output Digital I O and Counter Timer Connector J17 Pin Assignments cont Pin Signal Description Pin Signal Description 12 Digital Input Output 1 Port 1 46 Digital Input Output 5 Port 1 11 Digital Input Output 0 Port 1 45 Digital Input Output 4 Port 1 10 Digital Input Output 3 Port 2 44 Digital Input Output 7 Port 2 TINP1 gt 9 Digital Input Output 2 Port 2 43 Digital Input Output 6 Port 2 Encoder 2 Clr 8 Digital Input Output 1 Port 2 42 Digital Input Output 5 Port 2 Encoder 1 Clr 7 Digital Input Output 0 Port 2 41 Digital Input Output 4 Port 2 Encoder 0 Clr 6 User Clock Input 0 40 Isolated Digital Groun
131. stage of the DACs To initialize the D A subsystem on the DT9841 DT9841E and DT9841 VIB serial port 0 TI PCM1737 is used to set up the DACs and to synchronize up to seven additional modules The added modules must be set up as slaves with an external clock All connected modules receive the same setup information for the A D and D A subsystems over the Scalable Bus see page 113 for more information on the Scalable Bus The serial port is also used to reset and start the DACs The default mode is 128 times the sampling rate 0 dB attenuation DACs enabled mute disabled sharp roll off deemphasis disabled 8 times interpolation and 24 bit standard 90 Register Description format For clock rates over 100 kHz the over sampling rate is 64 times On the DT9842 2 and DT9842 8 a system reset is used to initialize the DACs No other initialization is necessary the DACs are wired for the desired operation Once the DACs are started the serial data is packed as 32 bits in the Spartan chip the data is encoded as twos complement and is left hand justified On the DT9841 DT9841E and DT9841 VIB the right eight bits are filled with zeros On the DT9842 2 and DT9842 8 the data is converted to 16 bit offset binary in the Spartan chip After the data is clocked out the D A Ready register asserts interrupt EXT INT5 Then both DACs must be updated within 10 us for 100 kHz operation using DMA channel 5 On the DT9841 DT9841E and
132. t 2 8 Digital Input Output 1 Port 2 Encoder 0 Clr Encoder 1 Clr 9 Digital Input Output 2 Port 2 10 Digital Input Output 3 Port 2 Encoder 2 Clr TINP12 11 Digital Input Output 0 Port 1 12 Digital Input Output 1 Port 1 13 Digital Input Output 2 Port 1 14 Digital Input Output 3 Port 1 15 Digital Input Output 0 Port 0 16 Digital Input Output 1 Port 0 17 Digital Input Output 2 Port 0 18 Digital Input Output 3 Port 0 19 Digital Output Clock 20 Digital Output Trigger 21 Digital Input Clock 22 Digital Input Trigger 23 External A D Clock 24 External A D Trigger 25 External D A Clock 26 External D A Trigger 27 Reserved 28 Reserved 29 Reserved 30 Reserved 31 Reserved 32 Reserved 33 Analog Output 01 34 Analog Output 00 35 External Gate 2 36 Isolated Digital Ground Encoder B28 37 External Gate 1 38 Isolated Digital Ground Encoder B1 39 External Gate 0 40 Isolated Digital Ground Encoder B0 41 Digital Input Output 4 Port 2 42 Digital Input Output 5 Port 2 43 Digital Input Output 6 Port 2 44 Digital Input Output 7 Port 2 175 Appendix B Table 35 Pin Assignments for Connector J201 on the EP358E Accessory Panel Pin Signal Description Pin Signal Description 45 Digital Input Output 4 Port 1 46 Digital Input Output 5 Port 1 47 Digital Input Output 6 Port 1 48 Digital Input Output 7 Port 1 49 Digital Input Output 4 Port 0 50 Digital Input Out
133. til the voltmeter reads 9 375 V Calibration Note At any time you can click Restore Factory Settings to reset the D A calibration values of both DACs to their original factory settings This process will undo any D A calibration settings Once you have finished this procedure the analog output circuitry is calibrated To close the DT9841 Calibration Utility click the close box in the upper right corner of the window 127 Chapter 3 128 A Specifications 129 Appendix A Table 3 lists the specifications for the analog input subsystem Table 3 Analog Input Subsystem Specifications Feature DT9841 DT9841E and DT9841 VIB Specifications DT9842 2 and DT9842 8 Specifications Number of analog inputs For DT9841 8 differential simultaneously sampled and held SSH For DT9841E 2 differential simultaneously sampled and held SSH For DT9841 VIB 8 single ended simultaneously sampled and held SSH 8 single ended simultaneously sampled and held SSH Number of gains 1 the value is always 1 1 the value is always 1 Resolution 24 bits 16 bits Data encoding Twos complement Twos complement System accuracy For DT9841 and full scale DT9841E 0 02 0 024 For DT9841 VIB 0 044 Nonlinearity integral 4096 LSBs 0 01 Differential linearity monotonic 64 LSBs 1 LSB Specifications Table 3
134. til the host sets the one shot trigger enable bit Continuous increment also known as divide by n In continuous increment mode an external gate high external gate low or software logic high can be used to enable the counter to increment When the counter increments to the value specified in the pulse register the user output is activated The user output stays active until the counter increments to the terminal count The user output is then deactivated and the counter is automatically 103 Chapter 2 104 reloaded with the initial count which is specified in the period register This sequence is repeated as long as the counter is enabled by the gate The active polarity of the user output is software selectable Measure Measure mode uses the internal clock to measure the time interval between the selected measure start edge and the selected measure stop edge Either edge of the external gate or external clock can be independently chosen as the measure start edge or measure stop edge providing the ability to measure the signal pulse width high signal pulse width low signal period or time interval between two signals Once the measure enable command is received from the host the counter increments from the time it detects the selected measure start edge until it detects the selected measure stop edge The counter then stops until it receives the next measure enable command from the host Continuous Measure Co
135. tputs lists of output blocks Each list contains a specified number of input and or output blocks Refer to page 26 for more information on input and output blocks Principles of Operation You can specify whether to stop the operation when the number of blocks have been filled for an input operation or emptied for an output operation or whether to continue the operation starting by overwriting the first block in the list When you are finished acquiring and or outputting data you can use software to stop a continuous operation and free the previously allocated memory Triggers A trigger is an event that occurs based on a specified set of conditions Using software you can specify these conditions by selecting one of the following trigger sources e Software trigger The trigger event occurs immediately when you start the operation the computer issues a write to the module to begin conversions Note If you are using the Scalable Bus to connect multiple modules and you want to use an internal trigger to trigger the master and slave modules no extra wiring is required The internal trigger signal is provided to the slave modules through the Scalable Bus cables and connectors Refer to page 29 for more information on using the Scalable Bus External trigger The trigger event occurs when the module detects a low to high transition on the TTL level signal connected to the external input of the module For the DT98
136. ubsystem 126 119 Chapter 3 120 Use the DT9841 Calibration Utility to calibrate the analog input and analog output circuitry on the DT9841 DT9841E and DT9841 VIB modules Note The DT9841 Calibration Utility is not supported by DT9842 2 and DT9842 8 modules This chapter describes how to calibrate the analog input and output subsystems of a DT9841 DT9841E or DT9841 VIB module using the DT9841 Calibration Utility Calibration Using the DT9841 Calibration Utility Note Ensure that you installed the DT9840 Series software prior to using the DT9841 Calibration Utility Refer to the DT9840 Series Getting Started Manual for more information on installing the software Start the DT9841 Calibration Utility as follows 1 Double click DT9841 Calibration Utility located under Start Programs Data Translation Inc DT9840 Series The main menu appears 2 Select the DT9841 DT9841E or DT9841 VIB module to calibrate and then click OK The firmware is downloaded to the module and the calibration utility starts after a few seconds Once the DT9841 Calibration Utility is running you can calibrate the analog input circuitry either automatically or manually described on page 122 or the analog output circuitry of the DT9841 DT9841E or DT9841 VIB module described on page 126 121 Chapter 3 Calibrating the Analog Input Subsystem This section describes how to use the DT9841 Cal
137. uous Time A D Value Timer Value Measure Mode Operation 10 5002 0 Operation started when the C T subsystem was configured but is not complete 20 5004 0 Operation not complete 30 5003 0 Operation not complete 40 5002 12373 Operation complete 50 5000 0 Next operation started but is not complete 60 5002 0 Operation not complete 70 5004 0 Operation not complete 80 5003 12403 Operation complete 90 5002 0 Next operation started but is not complete Use the following equations to determine the frequency and period of the signal Frequency 18 MHz Number of Counts Period 1 Frequency 57 Chapter 1 58 Note In continuous measure mode the internal C T clock is used to calculate the interval of the signal between the first start edge and the next start edge The pulse width and period count are automatically set to 0 Figure 7 shows an example of how to measure the frequency of a signal Ensure that the signals are wired appropriately Refer to the DT9840 Series Getting Started Manual for wiring examples Rising edge of gate stops Rising edge of gate starts the measure operation the measure operation Signal Connected to External Gate Input Pin The interval is calculated and the number of counts is returned Frequency 18 MHz Number of Counts Figure 8 Example of Continuous Measure Mode Measuring the Frequency Principles of
138. uously acquires an input scan record and or outputs an output scan record on each pulse of the sample clock until you stop the operation Refer to page 23 for more information on input and output scan records 25 Chapter 1 26 The sample rate is determined by the frequency of the sample clock and is the rate at which a single input scan record is acquired and a single output scan record is output refer to page 18 for more information on the sample clock Block Loop Operations Use software to start a block loop operation When it detects a trigger event the module continuously acquires input blocks and or outputs output blocks until you stop the operation Each input block consists of the following information Input scan records refer to page 23 for more information on input scan records e The number of scans in each block e A flag that indicates whether or not the block is full e A pointer to the next block Each output block consists of the following information Output scan records refer to page 23 for more information on output scan records The number of scans in each block Aflag that indicates whether or not the block is full e A pointer to the next block List Loop Operations To perform a list loop operation use software to allocate a linked list of input and or output blocks and start the list loop operation When it detects a trigger event the module acquires lists of input blocks and or ou
139. using the User Control registers described in Table 13 on page 96 2 Select the desired mode output polarity and clock source using the User Control registers described in Table 13 on page 96 3 Load the User Period registers described in Table 12 on page 94 with the desired value 4 Load the User Pulse registers described in Table 12 on page 94 with the desired value Once loaded the user counter timer is waiting for an active gate to begin counting 5 Select the desired gate using the User Control registers described in Table 13 on page 96 If logic high is selected as the gate source the counter timer begins counting immediately If an external gate is selected as the gate source the counter counts when the external gate is active To initialize a counter timer subsystem for an externally triggered one shot operation do the following 1 Select logic low for the gate source using the User Control registers described in Table 13 on page 96 2 Select the desired mode output polarity and clock source using the User Control registers described in Table 13 on page 96 3 Load the User Period registers described in Table 12 on page 94 with the desired value 4 Load the User Pulse registers described in Table 12 on page 94 with the desired value 5 Select the desired gate in the User Control registers described in Table 13 on page 96 108 Register Description 6 Issue a one shot trigger enable c
140. ut 37 counter timer 42 digital I O 40 system features memory 17 operation modes 22 sample clock 18 Scalable Bus connections 29 triggers 27 T TB2 screw terminal block DT9841E 158 166 TB3 screw terminal block DT9841E 159 166 transferring data analog input 35 analog output 39 trigger sources external 27 software 27 TTL trigger 27 U units counter timer 42 USB bus DSP hardware interface 67 USB connector 146 158 168 DT9841 150 DT9841E 165 DT9842 2 150 DT9842 8 150 User Control registers 96 User Status register 100 V voltage range 34 W Write Data Address 117 X Xicor potentiometers addresses and functions 79 instruction set 80 setting up 78
141. utput eae J3 AMP Tyco 5 146130 6 Blackhawk JTAG Poara emulator Level Version J4 AMP Tyco 5747844 4 AMP Tyco 5 747904 2 J6 AMP Tyco 292304 2 Data Translation EP365 USB cable or AMP Tyco 1487588 3 TB1 5 V Power Output Tyco Buchanan Tyco Buchanan 796644 2 796640 2 142 Specifications Table 12 DT9840 Series Connector Specifications cont Connector Part Mating Connector Product Connector Number Part Number DT9841 J115 Kycon KPJX 4S S Kycon KPPX 4P pete J12 and J13 3M N10250 52E2PC 3M 10150 6000EC DT9842 8 Board J15 and J16 BNCs Molex 73101 0161 AMP Tyco 1 221265 1 evel J17 and J18 AMP Tyco 6 104068 8 AMP Tyco 3 111196 4 Version cont DT9841E J1 and J2 AMP Tyco 6 104068 8 AMP Tyco 3 111196 4 om J3 AMP Tyco 5 146130 6 Blackhawk JTAG eye emulator Version J4 3M 30310 6002HB 3M 89110 0101 J6 AMP 292304 2 Data Translation EP365 USB cable or AMP Tyco 1487588 1 J11 Kycon KPJX 4S S Kycon KPPX 4P TB2 Phoenix Contact Phoenix Contact 1707434 1839610 TB3 PCD ELVH02500 PCD ELVP02100 EP358E Analog Input J1 AMP Tyco 5747375 8 AMP Tyco 5 747917 2 Digital I O J2 AMP Tyco 5747301 8 AMP Tyco 5 747916 2 Counter Timer J19 AMP Tyco 5745967 8 AMP Tyco 5 747912 2 J201 and J202 behind front panel AMP Tyco 6 104068 8 AMP Tyco 3 111196 4 143 Appendix A 144 Table 12 DT9840 Series Connector Specificati
142. ven additional slave modules set up with an external clock All connected modules receive the same setup information for the A D and D A subsystems over the Scalable Bus see page 113 for more information on the Scalable Bus Note that the rising edge of the CAL signal must be timed with the falling edge of the MCLK signal for simultaneous sample and hold operations This is synchronized in the Spartan chip on the master module No initialization is required for the A D subsystem on the DT9842 2 and DT9842 8 modules The A D converters are wired for the desired operation A D conversions start on an internal software trigger or external trigger An internal trigger is initiated by a software command An external trigger is initiated by a low to high transition on the external TTL trigger input to the module this trigger asserts EXT_INT4 for processing Scanning is continuous through all A D channels digital inputs and counter timers The DSP program can discard unneeded data On the DT9841 DT9841E and DT9841 VIB once the A Ds are started the serial data is packed as 32 bits in the Spartan chip The data is left hand justified the right 8 bits are filled with zeros and the data encoding is twos complement Register Description On the DT9842 2 and DT9842 8 once the A Ds are started the data is packed as 32 bits in the Spartan chip and the data is left hand justified the right 16 bits are filled with zeros the data encoding i
143. ximation converters no filtering is supported Using software you can configure the DT9841 and DT9841E modules to use 1 kQbias return termination resistance between the low side of each differential channel and isolated analog ground This feature is particularly useful with floating signal sources Refer to the DT9840 Series Getting Started Manual for more information on wiring to inputs to use bias return termination resistance IEPE Functions The DT9841 VIB module supports the following IEPE functions for each of the eight analog inputs Current source Using the DSP library you can enable or disable the use of a 4 mA current source e AC DC coupling Using the DSP library you can select whether AC coupling or DC coupling is used Filtering Using the DSP library you can enable or disable the use of the 2 pole 10 KHz Butterworth filter Figure 3 shows a block diagram of the IEPE functions on one of the analog input channels 33 Chapter 1 30V DC DC A A 5V 2 Pole Butterworth Filter 10kHz 10f8 Channels Filter 25 ChO0 Coupling AC DC T 1 6Hz Channels E Qoid 2 na RN 2 Control Lines Figure 3 IEPE Block Diagram on the DT9841 VIB Input Resolution The input resolution of the DT9841 DT9841E and DT9841 VIB modules is fixed at 24 bits The input resolution of the DT9842 2 and DT9842 8 modules is fix

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