Interfacing I S-Compatible Audio Devices To The
Contents
1. x rl 31 lt scale the sample to the range of 1 0 ay amp r0 DM Left Channel 5 f0 float r0 by rl Call Floating Point Algorithm 7 rl 31 scale the result back up to MSBs Be r8 fix 8 by r1 DM Left Channel r8 nee ope Se eee ee ee ee eee ee eee ee ee ee ee eee user_applic call pc Auto_Double_Tracking DSP processing is finished now playback results to DACs tx_audio_data_out_I2Ss transmit channel A audio data out of SPORTO i2s port tx0A pins r0 dm il m1 get sine data from 4K lookup table rl dm i2 m2 get sine data from 4K lookup table r0 dm Left ChannelA Out get Left Audio channel data rl dm Right ChannelA Out get Right Audio channel data r0 lshift r0 by 8 put back in bits 0 23 for SPORT tx rl lshift rl by 8 put back in bits 0 23 for SPORT tx dm tx0a buf LEFT r0 send i2s left channel tx data send i2s right channel tx data transmit channel B audio data out of SPORTO i2s port tx0A pins rO dm ro Right ChannelB Out lshift rl by 8 dm tx0b buf LEFT r0 dm tx0b buf RIGHT rl i2s tx done rO dm I2S timer r0 r0 1 get Left ADC channel data put back in bits 0 23 for SPORT tx get Right ADC channel data put back in bits 0 23 for SPORT send i2s left channe2. SHBG Application Note Interfacing FS Compatible Audio Devices To The ADSP 21065L Serial Ports Version 1 0A John Tomarakos ADI DSP Applications 4 2 99 0 Introduction The ADSP 21065L is the newest first generation SHARC member to be released enabling 32 bit processing in either fixed or floating point at a cost comparable to lower data word DSPs This application note will cover the new features of the ADSP 21065L Serial Ports the addition of the I S mode of operation which allows a simple glueless interface to a wide range of industry standard audio devices The I S format was developed and promoted by Philips Semiconductor and today many professional and consumer audio manufacturers use this standard interface for interconnection of audio devices and as a result it has become the dominant de facto standard This document will serve as a reference for those who wish to understand the I S serial protocol and the programming of the ADSP 21065L to enable this mode of operation First a short tutorial will be given on the I S bus and then 21065L S mode functionality will be described in detail Finally two I S loopback examples will be demonstrated One was written and tested on the ADSP 21065L EZ LAB with a simple wired loopback on the EMAFE interface while the other example is an audio loopback on the Bittware Research Systems Spinner Audio OEM Board which uses 24 bit 96 kHz PS ADCs and DACs AKM semiconductor conve
3. write DMA receive block chain pointer to TCB buffer CPROA r0 receive block chain pointer initiate rx0 DMA transfers RTS endseg A 2 SPORTO PS Receive Interrupt Service Routine KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SPORTO I2S RX INTERRUPT SERVICE ROUTINE Receives loopback data from SPORTO I2S TX pins via SPORTO I2S RX and then sends the audio data back the output channel locations for the AD1819A Stereo DAC routine KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Serial Port 0 Transmit Interrupt Service Routine performs arithmetic computations on SPORTO receive data buffer rx_buf and sends results to SPORTO transmit data buffer tx_buf i2s_rx_buf 2 DSP SPORTO I28 recieve buffer channel Description DSP Data Memory Address I2S Left Channel Data DM i2s rx buf DM i2s rx buf I2S Right Channel Data DM i2s rx buf DM i2s rx buf i2s tx buf 2 DSP SPORTO 12S transmit buffer channel Description DSP Data Memory Address I2S Left Channel TX Data DM i2s tx buf DM i2s tx buf I2S Right Channel TX Data DM i2s tx buf DM i2s rx buf KOKCKCkCKCkCkCk Ck Ck Ck kk CkCk Kk Ck kk kk kk A Ck kk CkCk kk KC Kk Ck kk Ck Ck kk A k KC RI AR CK Ck Ck kk k ke kk k k kk A kk ko kk k k kk I ko kc kk I I ADSP 21065L System Register bit definitions include def210651 h include new65Ldefs
4. GLOBA GLOBA segment dm Program_DMA_Controller_SPT0 Program I2Smode SPORTO Registers P 21065L System Register bit definitions def210651 h new65Ldefs h define buffer size to match I2S TDM stereo channels define define Var Var Var Var Var Var rx0a buf STEREO LR rxOb buf STEREO LR tx0a buf STEREO LR tx0Ob buf STEREO LR rcv0Oa tcb 8 rcvOb tcb 8 2 0x00000200 SYSTAT bit mask for SHARC B with ID 2 stereo primary receive a buffer stereo secondary receive b buffer stereo primary transmit a buffer stereo secondary transmit b buffer Uy By receive a tcb Uu receive b tcb var xmit0a tcb 8 transmit a tcb War xmitUb teBIS e 0 Up Oy QpoOQ 2y l2 0 transmit b tcb I o o o o o N m E endseg segment pm pm_code n Sport0 Control Register Programming Kf I squared S Mode dma w chain slave mode no pack data 24 big zero Ay anc Program I2Smode SPORTO Registers check if the DSP has ID 2 If ID 2 then clear flagl This will activate a direct connection between that processor and the AKM ADCs and DACs RO dm SYSTAT R1 ID2 RO RO AND R1 IF EQ jump set spt regs if ID 1 keep flag0 set enables SPORT to S
5. DM Audio Data I2S Right DM Right ChannelB In SPORTO ADC data RXOB Loopback Left amp Right Audio Samples SPORTO DAC 2 TXOB DMA Buffer TXOB BUF 2 DM Audio Data DM Left ChannelB Out M Right ChannelB Out I2S Left SPORTO DAC data TXOB KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SPORTO I2S RX INTERRUPT SERVICE ROUTINE Receives AKM ADC data from SPORTO I2S RX pins and then sends the audio data back out to the AKM DAC Line Outputs KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK KK KKK KKK KK KK KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK Serial Port 1 Transmit Interrupt Service Routine performs arithmetic computations on SPORT1 receive data buffer rx_buf and sends results to SPORT1 transmit data buffer rxO0a_buf 2 tx0b buf 2 DSP SPORTO I2S recieve buffers channel Description 0 I2S Left Channel Data DM rx_buf 0 1 2S Right Channel Data DM rx_buf 1 tx0a buf 2 tx0b buf 2 DSP SPORTO I2S transmit buffers channel Description Channel TX Data Channel TX Data I2S Left 2S Right DM tx0a buf 0 DM tx0a buf 1 DM rx0a buf LEFT DM rxO0a buf RIGHT DM rx0a buf LEFT DM tx0a buf RIGHT tx buf DSP Data Memory Address DSP Data Memory Address OK CKCk CK Ck e Ck Ck Ck Kk CkCkC kk Ck kk kk kk Ck kk Ck Ck kk Ck kk Ck kk Ck kk Ck Ck kk AR kk k kk Ck Ck KC k k k k k kk Ck ke kk Ck Ck
6. var I2s rcv tcb 8 gt receive tcb var I2s xmit tcb 8 transmit tcb Note that the DMA count and modify values can be initialized in the buffer declaration so that they are resident after a DSP reset and boot However at runtime further modification of the buffer is required to initiate the DMA autobuffer process To setup and initiate a chain of SPORT DMA operations at runtime the 21065L should follow this sequence 1 Setup SPORT transmit and Receive TCBs transfer control blocks The TCBs are defined in the data variable declaration section of your code Before setting up the values in the TCB and kicking off the DMA process make sure the SPORT registers are programmed along with the appropriate chaining bits required in step 2 2 Write to the SPORTO transmit and receive control registers STCTLO and STCRLO setting the SDEN_A and or SDEN B enable bit to 1 and the SCHEN_A and or SCHEN B chaining enable bit to a 1 3 Write the internal memory index address register IIxxx of the first TCB to the CPxxx register to start the chain The order should be as follows a write the starting address of the SPORT DMA buffer to the TCBs internal index register IIxxx location TCB buffer base address 7 You need to get the starting address of the defined DMA buffer at runtime and copy it into this location in the TCB b write the DMA internal modify register value IMxxx to the TCB TCB buffer base address 6 Note that
7. IITOA 0x70 Channel A DMA Channel 4 Modify Register IMTOA 0x71 DMA Channel 4 Count Register CTOA 0x72 DMA Channel 4 Chain Pointer Register CPTOA 0x73 DMA Channel 4 General Purpose Register GPTOA 0x74 SPORTO Transmit DMA Channel 5 Index Register IITOB 0x50 Channel B DMA Channel 5 Modify Register IMTOB 0x51 DMA Channel 5 Count Register CTOB 0x52 DMA Channel 5 Chain Pointer Register CPTOB 0x53 DMA Channel 5 General Purpose Register GPTOB 0x54 SPORT1 Transmit DMA Channel 6 Index Register IIT1A 0x78 Channel A DMA Channel 6 Modify Register IMTIA 0x79 DMA Channel 6 Count Register CTIA Ox7A DMA Channel 6 Chain Pointer Register CPTIA Ox7B DMA Channel 6 General Purpose Register GPTIA Ox7C SPORT1 Transmit DMA Channel 7 Index Register IITIB 0x58 Channel B DMA Channel 7 Modify Register IMTIB 0x59 DMA Channel 7 Count Register CTIB Ox5A DMA Channel 7 Chain Pointer Register CPTIB Ox5B DMA Channel 7 General Purpose Register GPTIB Ox5C 4 9 Setting Up the 21065L DMA Controller for Chained SPORT DMA Transfers To transmit and receive digital audio data to from an I S device one efficient method is to use serial port DMA Chaining to transfer data between the I S serial bus and the DSP core There are obvious benefits for doing this First of all DMA transfers allow efficient transfer of data between the serial port circuitry and DSP internal memory with zero overhead i e there is no processor intervention of the SHARC core to manually transfer the data Secon
8. WS changes state one SCLK period before the MSB is transmitted In slave mode the data is latched on the leading edge of the serial clock signal The slave determines synchronous timing of the serial data that will be transmitted based on the external clock generated by the master The WS signal is latched on the leading edge of the clock signal The slave takes into account the propagation delays between the master clock and the data and or word select signals Thus the total delay is simply the sum of The delay between the master clock and the slaves internal clock The delay between the internal clock and the data and or the word select signals Other I S Specification Notes e To allow data to be clocked out on a falling edge the delay is specified with respect to the rising edge of the clock signal always giving the reciever sufficient setup time e The data setup and hold time must not be less than the specified reciever set up and hold time e In slave mode the transmitter and receiver meed a clock signal with minimum HIGH and LOW periods so that they can detect the signal e Any device can act as the serial bus master by providing the necessary clock signals 2 Usage of I S Peripherals in 32 bit Audio Applications The following Figures 4 and 5 show how the ADSP 21065L can be used in certain audio applications to take advantage of it 12S mode for processing multiple channels of audio One example shows a surround sound applic
9. h AD1819 SPORTO Rx and Tx Timeslot Definitions define LEFT 0 define RIGHT 1 GLOBAL Process_I2S_Stereo_Data EXTERN Left Channel In EXTERN Right Channel In EXTERN Left Channel Out EXTERN Right Channel Out EXTERN i2s rx buf EXTERN i2s tx buf EXTERN Slapback Echo segment dm dm data VAR I2S Left Channel VAR I2S Right Channel VAR I2S8 timer 0x00000000 endseg Segment pm pm code Process I2S Stereo Data bit set model SRRFL enable secondary registers RO R7 nop 1 cycle latency writing to Model register get prior i2s tx data get previous SPORTO loopback ed i2s left and right data we are getting I2S data that was send in our previous SPORTO interrupt and then feeding this audio data back to the AD1819a DACs m i2s rx buf LEFT Get i2s left channel rx data m i2s_rx_buf RIGHT send_audio_to_AD1819a dm Left_Channel_Out dm Right_Channel_Out r0 rl transmit new AD1819a ADC data out of tx_ADC_data_out_I2s r0 dm Left Channel In rl dm Right Channel In dm i2s tx buf LEFT r0 dm i2s tx buf RIGHT rl i2s_tx_done rti db bit clr model SRRFL Get i2s right channel rx data SPORTO i2s port get AD1819a Left ADC channel data get AD1819 Right ADC channel data send i2s left channel tx data send i2s right channel tx data return from interrupt d
10. interrupt vector address the higher priority interrupt Note that channels A and B for the transmit and receive side of each SPORT share the same interrupt location Thus data for both DMA buffers is processed at the same time or on a conditional basis depending on the state of the buffer status bits in the SPORT control registers Table 7 ADSP 21065L Serial Port Interrupts Priority Interrupt Function SPROI SPORTO receive DMA channels 0 and 1 Highest SPR1I SPORT1 receive DMA channels 2 and 3 SPTOI SPORTO transmit DMA channels 4 and 5 SPT1I SPORT1 transmit DMA channels 6 and 7 EPOI Ext port buffer 0 DMA channel 8 EP11II Ext port buffer 1 DMA channel 9 Lowest 1 Interrupt names are defined in the def21065 h include file supplied with the ADSP 21000 Family Visual DSP Development Software 4 5 Serial Port Related IOP Registers This section briefly highlights the list of available SPORT related IOP registers that you will need to program when configuring the SPORTs for I S mode To program these registers you write to the appropriate address in memory using the symbolic macro definitions supplied in the def210651 h file included with the Visual DSP tools in the INCLUDEJ directory External devices such as another 21065L or a host processor can write and read the SPORT control registers to set up a serial port DMA operation or to enable a particular SPORT These registers are shown in the table be
11. short S is a popular 3 wire serial bus standard protocol developed by Philips for transmission of 2 channel stereo Pulse Code Modulation digital data where each audio sample is sent MSB first VS signals shown in Figures 1 and 2 consist of a bit clock Left Right Clock also is often referred to as the Word Select and alternating left and right channel data This protocol can be compared to synchronous serial ports in TDM mode with 2 timeslots or channels active This multiplexed protocol requires only 1 data path to send receive 2 channels of digital audio information Figure 1 I S Digital Audio Serial Bus Interface Examples Figure 2 Example I S Timing Diagram for 16 bit Stereo PCM Audio Data Transmitter Reciever DSP LR Select Audio Left Right i Serial Bus Master D A FS Cisek Left Channel Select Right Channel Select 1 Serial Bit Clock Delay From LRCLK transistion aa nee serial Date biis EEE SEE SESE LM L s Left Sample ss Right Sample s B BB B Audio LR_Select A D Audio data word sizes supported by various audio converter manufacturers range can be either 16 18 20 or 24 bits As a result today many analog and digital audio front end devices support the rs protocol Some of these devices include e Audio A D and D A converters e PCMultimedia Audio Controllers e Digital Audio Transmitters and Receivers that support serial digital audio transmission standards such as AES EBU SP DIF IEC958 CP 340 and
12. this step may be skipped if it the location in the buffer was initialized in the variable declaration section of your code c write the DMA internal count register Cxxx value to the TCB TCB buffer base address 5 Also note that this step may be skipped if it the location in the buffer was initialized in the variable declaration section of your code d get the IIxxx value of the TCB buffer that was previously stored in step a set the PCI bit with a that internal address value and write the modifed value to the chain pointer location in the TCB TCB buffer base offset 4 e write the same PCI bit set internal address value from step d manually into that DMA channels chain pointer register CPxxx At this moment the DMA chaining begins If the SPORT enable bit was already set otherwise transfers will not begin until the SPORT enable bit is set The DMA interrupt request occurs whenever the Internal Count Register Cxxx decrements to zero SPORT DMA chaining occurs independently for the transmit and receive channels of the serial port After the SPORTO receive buffer is filled with new data a SPORTO receive interrupt is generated and the data placed in the receive buffer is available for processing The DMA controller will autoinitialize itself with the parameters set in the TCB buffer and begin to refill the receive DMA buffer with new data in the next audio frame In our loopback example the processed data is then placed in the SPORT
13. transmit buffer where it will then be DMA ed out from memory to the SPORT DTOA pin After the entire buffer is transmitted from internal memory to the SPORT circuitry the DMA controller will autoinitialize itself with the stored TCB parameters to perform another DMA transfer of new data that will be placed in the same transmit buffer Below are example assembly instructions used to set up the Transfer Control Blocks for SPORTO Channel A in the 21065L EZ LAB example shown in appendix A These values are reloaded from internal memory to the DMA controller after the entire SPORT DMA buffer has been received or transmitted If you want to reduce interrupt overhead these buffers can be made a multiple of 2 which would increase the buffer size Data is interleaved in memory with the left sample first followed by the right sample then the left again and so on segment dm dm I2S define buffer size to match I2S TDM stereo channels define STEREO_LR 2 var I2s rx buf STEREO LR stereo I2S receive buffer var I2s tx buf STEREO LR stereo I2S transmit buffer var I2s rcv tcb 8 0 0 0 0 0 2 1 receive tcb var I2s xmit tcb 8 0 0 0 0 0 2 1 transmit tcb endseg 0 0 DMA Controller Programming For SPORTO I2S Tx and Rx Setup SPORTO I2S for DMA Chaining Program DMA Controller SPTO ri Ox0001FFFF cpx register mask sportO dma control tx chain pointer register r0 I2s tx buf dm I2s x
14. tx chain pointer register r0 tx0a buf dm xmit0a tcb 7 r0 internal dma address used for chaining ro 1 dm xmit0a tcb 6 r0 DMA internal memory DMA modifier ro 2 dm xmit0a tcb 5 r0 DMA internal memory buffer count r0 xmitOa_tcb 7 get DMA chaining int mem pointer containing tx_buf addr r0 rl AND r0 mask the pointer r0 BSET r0 BY 17 dm xmit0a tcb 4 r0 dm CPTOA r0 sportO0 dma channel b r0 txOb buf dm xmitOb tcb 7 r0 ro 1 dm xmitOb_tcb 6 r0 ro 2 dm xmitOb_tcb 5 r0 r0 xmitOb_tcb 7 0 rl AND r0 0 BSET r0 BY 17 m xmitOb_tcb 4 r0 m CPTOB r0 I I a a sportO dma channel a r0 rx0a buf dm rcvO0a tcb 7 r0 ro 1 dm rcvOa_tcbh 6 r0 ro 2 m rcvOa tcb 5 r0 0 rcv0a tcb 7 0 rl AND r0 0 BSET r0 BY 17 m m d r r dm rcvOa tcb 4 r0 dm CPROA r0 sportO dma channel b r0 rx0b_buf dm rcvOb tcb 7 r0 ro 1 dm rcvOb tcb 6 r0 ro 2 dm rcvOb tcb 5 r0 revOb_tcb 7 rl AND r0 r0 BSET r0 BY 17 dm rcvOb tcb 4 r0 dm CPROB r0 RTS endseg control tx chain control rx chain control rx chain set the pci bit write DMA transmit block chain pointer to TCB buffer trans
15. 21065L TFSO TFS1 WS 21065L DTOA DTOB DT1A DTIB SD Serial Data In 21065L Table 5 21065L lS Transmitter in Slave Mode ADSP 2106x Pin PS Device Pin Driven By TCLKO TCLK1 SCLK PS device TFSO TFS1 WS PS device DTOA DTOB DT1A DT1B SD Serial Data In 21065L 4 3 Important Notes from the ADSP 21065L User s Manual Serial Ports Chapter In PS Mode one or both of the transmit channels can transmit and one or both receive channels can receive Each channel either transmits or receives Left and Right Channels In PS Mode when both A and B channels are used they transmit or receive data simultaneously sending or receiving bit 0 on the same edge of the serial clock bit 1 on the next edge of the serial clock and so on The processor always drives never puts the DT pins in a high impedance state except when a serial port is in multichannel mode and an inactive time slot occurs SPORT interrupts occur on the second system clock CLKIN after the serial port latches or drives out the last bit of the serial word A serial port configured for external clock and frame sync can start transmitting or receiving data two CLKIN cycles after becoming enabled In PS mode e Both SPORTs transmit channels Tx A and Tx B always transmit simultaneously each transmitting left and right I2S channels e Both SPORT receive channels Rx A and Rx B always receive simultaneously each receiving left and right I2S channels e Data al
16. A receive and CPTOA register for SPORTO A transmit The transmit and receive SCHEN_A and SCHEN B bits in the SPORTx Control registers enable DMA chaining To autoinitialize repetitive DMA chained transfers the programmer needs to set up a buffer in memory called a Transfer Control Block TCB that will be used to initialize and further continue the chained DMA process Transfer Control Blocks are locations in Internal Memory that store DMA register information in a specified order Figure 9 below demonstrates defined TCBs in internal memory for SPORTO Channel A The Chain Pointer Register CPROA and CPTOA stores the location of the next set of TCB parameters to be automatically be downloaded by the DMA controller at the completion of the DMA transfer which in this case it points back to itself Figure 9 TCBs for Chained DMA Transfers of SPORTO Channel A Receive and Transmit rcvOa_tcb 8 xmitOa tcb 8 DM rcv0a tcb 0 DM xmit0a tcb 0 DM rcv0a tcb 1 DM xmit0a tcb 0 DM rev0a_tcb 2 DM xmit0a_tcb 0 DM rcv0a tcb 3 DM xmit0a_tcb 0 DM rev0a_tcb 4 DM xmit0a_tcb 0 DM rcv0a tcb 5 DM xmit0a_tcb 0 DM rev0a_tcb 6 DM xmit0a_tcb 0 DM rcv0a_tcb 7 DM xmit0a_tcb 0 These TCBs for both the transmit and receive buffers can be defined in the variable declaration section of the DSP assembly or C code In the S example code shown in appendix A the TCBs for SPORTO channel A are defined as follows
17. CP 1201 e Digital Audio Signal Processors e Dedicated Digital Filter Chips e Sample Rate Converters The ADSP 21065L has 4 transmit and receive data pins DTOA DTOB DT1A DT1B providing IS serial port support for interfacing to up to 8 commercially available I S stereo devices yielding 16 channels of audio with only 2 serial ports The ADSP 21065L s built in support for the I S protocol eliminates the need for interface logic with a FPGA and result in a simple glueless interface In addition to the master slave timing generation of the word select and serial clock signals it is also possible to generates the clocks with an external controller or another audio device which in effect makes both I2S devices slaves An example of this is shown in Figure 3 So for multiple devices it is possible to synchronize all samples being transmitted or received with both SPORTS through a common clock and word select signal Figure 3 S Digital Audio Serial Bus Master Controller Word Select and Serial Clock Controller Transmitter Receiver SCLK LR_Select Audio D A Controller Serial Bus So this serial format efficiently transfers two channel audio data for each I2S interconnection while other control status and sub coding signals for example AES EBU devices used in ADAT equipment and SP DIF devices found in DVD players are transferred through a separate interface As shown in the above figures the buses three lines a
18. Ck k kk kk kk kkk I ke kk kkk kkk k ADSP 21065L System Register bit definitions include def210651 h include new65Ldefs h AD1819 SPORTO Rx and Tx Timeslot Definitions define LEFT 0 define RIGHT 1 GLOBAL Process AKM I2S Stereo Data GLOBAL Left ChannelA In GLOBAL Right ChannelA In GLOBAL Left ChannelA Out GLOBAL Right ChannelA Out GLOBAL Left ChannelB In GLOBAL Right ChannelB In GLOBAL Left ChannelB Out GLOBAL Right ChannelB Out EXTERN rxO0a buf EXTERN tx0a buf EXTERN rxOb buf EXTERN tx0Ob buf EXTERN Auto Double Tracking segment dm dm data stereo channel data holders used for DSP processing of audio data VAR Left ChannelA In VAR Right ChannelA In VAR Left ChannelB In VAR Right ChannelB In VAR Left ChannelA Out VAR Right ChannelA Out VAR Left ChannelB Out VAR Right ChannelB Out VAR 28 timer 0x00000000 endseg segment pm pm code Process AKM I2S Stereo Data enable secondary registers RO R7 nop get ADC i2s rx data Get SPORTO I2S r0 dm rx0a buf LEFT r0 lshift r0 by 8 rl dm rx0a buf RIGHT Get i2s right channel rx data rl lshift rl by 8 shift up to MSBs to preserve sign save for audio processing dm Left ChannelA In r0 dm Right ChannelA In r1 Get SPORTO I2S channelB ADC data r0 dm rx0b buf LEFT Get i2
19. HARC A bit clr astat ELGI clr flag 0 LED enables SPORT to SHARC B set_spt_regs sportO0 receive control register RO 0x013C0971 slave mode slen 24 sden_A amp schen_A amp sden_B amp schen_B enabled dm SRCTLO RO sport 0 receive control register sportO transmit control register RO 0x017C8971 slave mode slen 24 sden_A amp schen_A amp sden_B amp schen_B enabled dm STCTLO RO sport 0 transmit control register sport0O I2S word select transmit frame sync divide register RO 0x00000000 TCLKDIV 2xfCLKIN 60MHz SCLKfreq 12MHz 1 dm TDIVO RO TFSDIV TCLKfrq 12 MHz TFSfrq 96 0K 1 sportO0 I2S receive word select divide register RO 0x00000000 dm RDIVO RO sportO receive and transmit multichannel word enable registers RO 0x00000000 multichannel mode disabled dm MRCSO RO dm MTCSO RO sportO0 transmit and receive multichannel companding enable registers RO 0x00000000 no companding dm MRCCSO RO no companding on receive dm MTCCSO R0 no companding on transmit RTS GEE tte ge Rs HS A A a A A d DMA Controller Programming For SPORTO I2S Tx and Rx iiA E i Setup SPORTO I2S for DMA Chaining Dor Soe ee ee PIRA R O n Program DMA Controller SPTO rl 0x0001FFFF cpx register mask sportO dma channel a control
20. ION CONNECTOR LINE IN LINE OUT MIC IN EXPANSION CONNECTOR B B ET B O A RD Standoff O EMAFE INTERFACE CONTROL LOGIC AND AD1819A PROCESSOR EMAFE INTERFACE CONNECTOR EMAFE Signal Description The EZ LAB s EMAFE 96 pin connector routes the following signals from the ADSP 21065L to the EMAFE daughter board 16 Data lines 8 Address lines 3 Parallel Bus Control lines 16 Synchronous Serial Port lines Which Gives Access for I2S Connectivity 1 Interrupt output 1 Flag input The EMAFE 96 pin connector also has the following power connections routed from the 21065L EZ LAB Development Board to the EMAFE interface VDDI Digital power 5V 150 mA VDD2 Digital power 3 3V 150 mA 3VA Analog power 100 mA clean 5VA Analog power 100 mA clean There is one 3x32 pin right angle connector on the EZ LAB with female pins The is mounted on the right end of EZ LAB board The EMAFE daughter board should have one 3x32 pin connector with male pins on the left side of the board EMAFE Functional Description The parallel communication between the ADSP 21065L on the EZ LAB Board and the EMAFE interface consists of some control logic for the control lines MC RD WR CS etc an 8 bit latch that will store the address information MA 7 0 and a transceiver buffer for the data lines MD 15 0 The address lines are latched and the data lines are buffered to reduce digital noise on the MAFE board The 2 synchronous ser
21. MA internal memory DMA modifier DMA internal memory buffer count mask the pointer set the pci bit write DMA receive block chain pointer to TCB buffer receive block chain pointer initiate rx0 DMA transfers 5 Enabling I S Device Connectivity On The 21065L EZ LAB Via The EMAFE Enhanced Modular Analog Front End Interface The 21065L EZ LABs EMAFE connector allows an upgrade path for evaluating present and future I S compatible codec and ADCs AD18xx AD7xxx Crystal Semiconductor converters and digital audio interfaces multi media codecs etc with the ADSP 21065L EZ LAB Development Board The analog front end devices can be placed on a daughter board thus being modular Each EMAFE daughter board can have its own back plate to allow different input connections i e RCA jack mic in speaker out etc The daughter board can be attached to the ADSP 21065L Digital Signal Processor Development Board by a single 96 pin right angle mounted male connector and two mechanical standoffs to give stability to the entire arrangement when the daughter board and 21065L EZ LAB are being attached The 21065L EZ LAB has a 96 pin right angle mounted female connector Figure 10 ADSP 21065L EZ LAB EMAFE Interface ADSP 21065L EZ LAB EVALUATION BOARD CUSTOM ENHANCED MAFE DAUGHTER BOARD EZ FLAGOUT LED Standoff O FLAGINI FLAGIN2 FLAGIN3 FLAGIN4 JE Customer i Defined MR PS Populated EMAFE 3 DAUGHTER SIGNAL EXPANS
22. S A channel Performs a software reset SPEN B SPORT Channel B Enable bit 24 This enables and disables the SPORTS B channel Performs a software reset SDEN A SPORT Channel A DMA Enable bit 18 Enables and disables SPORT DMA operation versus interrupt driven transfers SDEN A 0 disables DMA transfers for channel A interrupt generated for every word transmitted or received SDEN A 1 enables DMA transfers for channel A SDEN B SPORT Channel B DMA Enable bit 20 SDEN B 0 disables DMA transfers for channel B interrupt generated for every word transmitted or received SDEN B 1 enables DMA transfers for channel B SCHEN A SPORT DMA Chaining Channel A Enable bit 19 02 Disables DMA chaining 1 Enables DMA chaining SCHEN B SPORT DMA Chaining Channel B Enable bit 21 0 Disables DMA chaining 1 Enables DMA chaining DITFS Data Independent TFS bit 15 transmit control registers only Selects when the processor toggles the TFS word select signal from low to high or high to low 0 Data dependent TFS TFS signal is generated only when nes data is in the SPORT chennel transmit data buffer 1 Data independent TFS TFS signal generated regardless of the validity of the data present in SPORT channels transmit data buffer The processor generates the TFS signal at the frequency specified by the value you load in the TDIV register TXS A RXS A Transmit and Receive Status Buffers bits 30 and 31 in the SPORT transmit and
23. andardized digital audio bit serial communications protocol for transmitting and receiving two channels of digital audio information through a transmission line balanced or unbalanced XRL microphone cables and audio coax cable with RCA connectors This format of transmission is used to transmit digital audio data over distances of 100 meters Data can be transmitted up to 24 bit resolution along with control status and sample rate information embedded in frame 37 AES EBU is considered to be the standard protocol for professional audio applications It is a common interface that is used in interfacing different professional mixing and DAT recording devices together The AES3 1992 Standard can be obtained from the Audio Engineering Society Figure 6 AES3 Frame Format 0 3 4 27 28 29 30 31 M Up to 24 bit Audio Sample Word Preamble 16 20 24 Data Audio Engineering Society Recommended Practice V Validity AES3 1992 Serial Transmission Format for Two U User Data Channel Linearly Represented Digital Audio Data C Channel Status P Parity Bit SPD IF Sony Philips Digital Interface Format SPD IF is based on the AES EBU standard in operating in consumer mode The physical medium is an unbalanced RCA cable The consumer mode carries less control status information Typical applications where this interface can be found is in home theater equipment Dolby Digital amp DTS Decoders and CD players Digital Audio Receivers typica
24. ation where multiple DACs are required for the playback and placement of 6 channels of audio Notice that for each IS link we have two channels of audio transmission from a stereo ADC or to a stereo DAC The other example shows how the ADSP 21065L can be used in a prosumer application such as a digital mixer or digital recorder Inputs and outputs can be either analog or digital Figure 4 Example Consumer Audio DSP System Using the ADSP 21065L Home Theatre System Left Front Right Front a ADSP 21065L Left Rear Right Rear Center E RCA Connector Subwoofer 4 4 4 4 4 4 Figure 5 Example Prosumer Audio DSP System Using the ADSP 21065L digital 4 track home studio recording playback system 12S Link 2S Link a ADSP 21065L Channel 1 Channel 2 3 Channel 3 3 Channel 4 39 12S Link Connector to DAT machine 3 Digital Audio Interface I S Devices SPD IF amp AES EBU Digital Audio Transmitters and Receivers The ADSP 21065L s IS interface easily allows transmission and reception of audio data using industry standard digital audio serial protocols These devices act as a digital front end for the DSP There are primarily 2 dominant digital protocols used today One is used for professional audio and the other for consumer audio applications AES EBU Audio Engineering Society European Broadcast Union AES EBU is a st
25. cb 6 r0 r0 2 dm xmitOb tcb 5 r0 r0 xmitOb tcb 7 rO rl AND r0 r0 BSET r0 BY 17 dm xmitOb tcb 4 r0 dm CPTOB r0 internal dma address used for chaining DMA internal memory DMA modifier DMA internal memory buffer count get DMA chaining internal mem pointer containing tx buf address mask the pointer set the pci bit write DMA transmit block chain pointer to TCB buffer transmit block chain pointer initiate tx0 DMA transfers sportO dma channel a control rx chain pointer register r0 rx0a buf dm rcvOa tcb 7 r0 r0 1 dm rcvOa tcb 6 r0 r0 2 dm rcvOa tcb 5 r0 r0 rcvOa tcb 7 rO rl AND r0 r0 BSET r0 BY 17 dm rcvOa tcb 4 r0 dm CPROA r0 js js internal dma address used for chaining DMA internal memory DMA modifier DMA internal memory buffer count mask the pointer set the pci bit write DMA receive block chain pointer to TCB buffer receive block chain pointer initiate rx0 DMA transfers sportO dma channel b control rx chain pointer register r0 rx0b_buf dm rcvOb tcb 7 r0 r0 1 dm rcvOb tcb 6 r0 r0 2 dm rcvOb tcb 5 r0 r0 rcvOb tcb 7 rO rl AND r0 r0 BSET r0 BY 17 dm rcvOb tcb 4 r0 dm CPROB r0 RTS endseg js js js P is internal dma address used for chaining D
26. dly there is a one to one correspondence of the location of the left and right P S data in the transmit and receive SPORT DMA buffer locations with the actual PS audio channel on the serial bus Thirdly an entire block of I S audio data can be transmitted or received before generating a single interrupt In our example the DMA buffer is only two words deep so that an interrupt is generated whenever a left sample and a right sample is transmitted or received However the user can further reduce interrupt overhead by making the DMA buffer size larger as long as it is by a factor of two so that data is always interleaved and aligned properly Thus this method of serial port processing is more efficient for the SHARC core to process data versus interrupt driven transfers which would occur more frequently Using chained DMA transfers allows the ADSP 21065L DMA controller to autoinitialize itself between multiple DMA transfers When the entire contents of the current SPORT buffers have been received or transmitted the ADSP 21065L will automatically set up another serial port DMA transfer to repeated again For further information on DMA chaining the reader can refer to page 6 39 in the ADSP 21065L User s Manual The chain pointer register CPxxx is used to point to the next setof TX and RX buffer parameters stored in memory For example SPORTO channel A DMA transfers are initiated by writing the DMA buffer s memory address to the CPROA register for SPORTO
27. ectronic components and materials catalog no data A 1 21065L EZ LAB Example SPORTO S Mode DMA Initializations KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SPORTO I2S Mode Initialization 7 Ry fE These assembly routines set up the ADSP 21065L SPORTO registers for I2S mode for PR transmitting and recieving of data at 48 KHz This routine will set up DMA chaining on au 1x SPORTO to recieve data coming from the AD1819a do an I2S loopback on SPORTO on the af E incoming AD1819a audio data and the results of the loopback will be sent to the AD1819a f DACs The I2S routines can be used as a programming reference to test the digital wire of the I2S ports fas By John Tomarakos ADI DSP Applications x Rev 1 0 12 15 98 Rev 1 1 1 11 98 xf KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK ADSP 21065L System Register bit definitions include def210651 h include new65Ldefs h GLOBAL Program_DMA_Controller_SPT0 GLOBAL Program I2Smode SPORTO Registers GLOBAL i2s rx buf GLOBAL i2s tx buf segment dm dm I2S define buffer size to match I2S TDM stereo channels define STEREO_LR 2 var i2s rx buf STEREO LR stereo I2S receive buffer var i2s tx buf STEREO LR stereo I2S transmit buffer var i2s rcv tcb 8 5 receive tcb var
28. el mode disabled RCSO RO TCSO RO portO0 transmit and receive multichannel companding enable registers 0x00000000 no companding RCCSO RO no companding on receive m MTCCSO R0 no companding on transmit DMA Controller Programming For SPORTO I2S Tx and Rx Setup SPORTO I2S for DMA Chaining Program DMA Controller SPTO rl 0x0001FFFF cpx register mask sportO dma control tx chain pointer register r0 i2s tx buf dm i2s xmit tcb 7 r0 internal dma address used for chaining ro 1 dm i2s_xmit_tcb 6 r0 DMA internal memory DMA modifier ro 2 dm i2s_xmit_tcb 5 r0 DMA internal memory buffer count r0 i2s xmit tcb 7 get DMA chaining internal mem pointer containing tx buf address rO rl AND r0 mask the pointer r0 BSET r0 BY 17 set the pci bit dm dm i2s xmit tcb 4 r0 write DMA transmit block chain pointer to TCB buffer CPTOA r0 transmit block chain pointer initiate tx0 DMA transfers sportO dma control rx chain pointer register r0 i2s rx buf m i2s rcv teb 7 0 internal dma address used for chaining 1 m i2s rcv teb 6 r0 DMA internal memory DMA modifier 2 m i2s rcv tcb 5 r0 DMA internal memory buffer count 0 i2s rcv tcb 7 0 rl AND r0 mask the pointer 0 BSET r0 BY 17 set the pci bit m m i2s rcv tcb 4 B
29. elayed branch restore primary registers RO R7 1 cycle latency writing to MODE1 register APPENDIX B Example Assembly Driver for interfacing to 24 bit 96 KHz AKM Semiconductor ADCs and DACs This example was written and tested on Bittware Research Systems Spinner ADSP 21065L Audio OEM Board For information on that audio OEM development system contact Bittware at 1 800 848 0436 or search their web site at www bittware com This development board contains the following features Visual DSP 4 0 Project Files 2 or 4 channels of 24 bit 96 kHz A D and D A 96 kHz AES EBU digital audio interface Single or dual 180 MFLOPS ADSP 21065L processors 1M FLASH memory with optional boot loading PCI interface or standalone operation 4M 16MB SDRAM Dual 16550 type UART Digital I O port B 1 SPORTO I S Initialization Routine for 2 x Stereo ADCs 2 x Stereo DACs KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK SPORTO I2S Mode Initialization ay These assembly routines set up the ADSP 21065L SPORTO registers for I2S mode for xf transmitting and recieving of data in slave mode at 96 KHz EY By John Tomarakos af ADI DSP Applications it A Rev 1 0 1 27 98 ur KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKK ADS include include GLOBA GLOBA GLOBA GLOBA
30. en 32 sden_A amp schen_A enabled dm STCTLO RO sport 0 transmit control register e The ADSP 2165L provides an internally generated 96 kHz frame sync TFSO It must be a 96 kHz frame rate since the AC97 specified frame rate of the AD1819 is 48 kHz and we get a left and right sample per 48 KHz frame from the AD1819A Thus the word select rate is twice as fast as the AD1819a AC link frame rate in order to send or receive 2 I2S samples per AC97 audio frame sport0 I2S word select transmit frame sync divide register We want to set up a frame sync of 96KHz since this is twice of 48 KHz Data coming from the AD1819a is 48 KHz so to send both left and right data via the I2S ports we need to send the stereo data at a rate 2x of the AD1819a Fs The TFS will toggle every 96 K but both left and right I2S data is being transmitted at a rate of 48K equivalent to the AD1819a frame rate The SPORTO ISR will be called at a rate of 48K since the I2S DMA buffers are 2 words deep RO 0x007C0004 TCLKDIV 2xf CLKIN 60MHz SCLKfreq 12MHz 1 0x0004 dm TDIVO RO TFSDIV TCLKfrq 12 MHz TFSfrq 96 0K 1 124 0x007C sportO0 receive frame sync divide register RO O0x00FF0000 SCKfrq 12 288M RFSfrq 48 0K 1 OxOOFF dm RDIVO RO e No companding sportO transmit and receive multichannel companding enable registers RO 0x00000000 no companding dm MRCCSO RO no companding
31. er WS Description DSP Data Memory Direct Address 0 VS TX Left Channel DM 32s tx buf 0 DM 32s tx buf LEFT 1 rs TXRight Channel DM 3i2s tx buf 1 2 DM 32s tx buf RIGHT 6 1 Processing 16 bit or 24 bit data in 1 31 Fractional Format or IEEE Floating Point Format Data that is received or transmitted in the SPORTO ISR is in a binary 2 s complement format The DSP interprets the data in fractional format where all s are between 1 and 0 9999999 Initially the serial port places the data into internal memory in data bits DO to D15 for 16 bit data and DO to D23 for 24 bit data In order to process the fractional data in 1 31 format the processing routine first shifts the data up by 16 bits or 8 bits for 24 bit data so that it is left justified in the upper data bits D16 to D31 or D8 to D31 for 24 bit data This is necessary to take advantage of the fixed point multiply accumulator s fractional 1 31 mode as well as offer an easy reference for converting from 1 31 fractional to floating point formats This also guarantees that any quantization errors resulting from the computations will remain well below the 16 bit or 24 bit result and thus below the DAC Noise Floor After processing the data the DSP shifts the 1 31 result down so that the data is truncated to a 1 15 or 1 23 number This fractional result is then sent to the DAC Below are example instructions to demonstrate shifting of data before and after the processing of data on
32. h I2S TDM stereo channels define STEREO_LR 2 var rx0a buf STEREO LR stereo I2S primary receive a buffer var rxOb buf STEREO LR stereo I2S secondary receive b buffer var tx0a buf STEREO LR stereo I2S primary transmit a buffer var txOb buf STEREO LR stereo I2S secondary transmit b buffer var rcvO0a tcb 8 receive a tcb var rcvOb tcb 8 d receive b tcb var xmitO0a tcb 8 B transmit a tcb var xmitOb tcb 8 transmit b tcb endseg segment pm pm code DMA Controller Programming For SPORTO Setup SPORTO I2S for DMA Chaining Program DMA Controller SPTO rl Ox0001FFFF cpx register mask sportO dma channel a control tx chain pointer register r0 tx0a_buf dm xmitOa_tcb 7 r0 r0 1 dm xmitOa tcb 6 r0 r022 dm xmitOa tcb 5 r0 r0 xmit0a tcb 7 rO0 rl AND r0 r0 BSET r0 BY 17 dm xmitOa tcb 4 r0 dm CPTOA r0 internal dma address used for chaining DMA internal memory DMA modifier DMA internal memory buffer count get DMA chaining internal mem pointer containing tx buf address mask the pointer set the pci bit write DMA transmit block chain pointer to TCB buffer transmit block chain pointer initiate tx0 DMA transfers sportO dma channel b control tx chain pointer register r0 txOb buf dm xmitOb tcb 7 r0 r0 1 dm xmitOb t
33. he Buyer Designer uses ADI products for any unintended or unauthorized application then Analog Devices cannot be held responsible
34. i2s xmit tcb 8 i transmit tcb endseg Segment pm pm code Sport0 Control Register Programming I squared S Mode dma w chain erly fs act hi fs fall edge no pack data 16 big zero Program I2Smode SPORTO Registers sportO0 receive control register RO 0x000D09F1 slave mode slen 32 sden A amp schen A enabled dm SRCTLO RO sport 0 receive control register sportO transmit control register RO 0x000DODF1 master mode data depend slen 32 sden_A amp schen_A enabled dm STCTLO RO sport 0 transmit control register sport0 I2S word select transmit frame sync divide register We want to set up a frame sync of 96KHz since this is twice of 48 KHz Data coming from the AD1819a is 48 KHz so to send both left and right data via the I2S ports we need to send the stereo data at a rate 2x of the AD1819a Fs The TFS will toggle every 96 K but both left and right I2S data is being transmitted at a rate of 48K equivalent to the AD1819a frame rate The SPORTO ISR will be called at a rate of 48K since the I2S DMA buffers are 2 words deep vA RO 0x007C0004 TCLKDIV 2xfCLKIN 60MHz SCLKfreq 12MHz 1 0x0004v dm TDIVO RO TFSDIV TCLKfrq 12 MHz TFSfrq 96 0K 1 124 0x007C sport0 I2S receive word select divide register 0x00000000 DIVO RO portO0 receive and transmit multichannel word enable registers 0x00000000 multichann
35. ial ports SPORTO and SPORT 1 from the ADSP 21065L processor is also directly wired to the EMAFE connector interface pins Level shifting of serial port signals from the ADSP 21065L processor may be required for 5V non 3 3V compliant peripherals on the EMAFE board or from 5V peripherals on the EMAFE board to the 3 3v non 5V tolerant ADSP 21065L processor Thus the EMAFE serial port pins are used to connect to I S devices on the EMAFE daughter card Additional address and data lines can be used for control and status information to various digital audio devices such as AES EBU and SP DIF transmitters and receivers 6 Using The 21065L EZ LAB EMAFE Interface For The lS Loopback Test The I S reference code listed in Appendix A was tested on the Analog Devices 21065L EZ LAB evaluation board test case shown in Figure 11 The example code implements a digital wire test which consists of looping back incoming ADC data from the AD1819a SoundPort codec via the SPORTO I S interface and the resulting loopback of audio is sent out of the AD1819a DACs The implementation sets up transmit and receive DMA chaining on SPORTI to transfer data between the DSP and the AD1819a while also setting up transmit and receive DMA chaining on SPORTO for the IS master transmitter and the slave receiver To enable the connection wire wrap was used to connect the SPORTO transmit data word select and serial clock pins from the transmitter to the receiver When connect
36. ing the SPORTO pin be careful to use a short straight wire to ensure the best possible noise immunity Figure 11 21065L EZ LAB EMAFE I S Audio Loopback Example 12S transmitter wired back to I2S receive I2S Master 12S Slave Stereo Line Out Left Right EMAFE Speakers Connector Stereo Mic Figure 12 21065L EZ LAB P S Digital Wire DMA amp Memory Signal Paths SPORT1 ADC RX DMA Buffer RX BUF 5 SPORTO I2S TX Master DM Audio Data Holders l28 TX BUF 2 SPORT1 ADC I2S TX Left EAR ADC Left Left In SPORT1 DAC TX DMA Buffer TX_BUF 5 SPORT1 EMAFE Tag Slot Codec Data DM Audio Data Holders Em TX1 register I2S RX Right 12S RX BUF 2 SPORTO I2S TX Master DMA Buffer Table 10 Serial Port IS Channel Assignments DMA Buffer Relationships The DSP SPORT I S Mode Time Slot Map for the SPORTO Channel A I S Loopback Example Slave DS Device Receiver DRO Master I2S Device Transmitter DT0 o Left Channel Receive Left Channel Transmit Right Channel Receive Right Channel Transmit Table 11 ADSP 2106x SPORTO Ch A DMA Buffers Used in the Example SPORTO I2S Driver Appendix A i2s rx buf 2 SPORTO DMA receive I2S buffer WS Description DSP Data Memory Direct Address 0 T S RX Left Channel DM i2s rx buf 0 DM 32s rx buf LEFT 1 PS RX Right Channel DM i2s_rx_buf 1 DM i2s rx buf RIGHT Ds tx buf 2 SPORTO DMA transmit I2S buff
37. ive data buffer channel A data TXO B Oxee SPORTO transmit data buffer channel B data RXO B Oxef SPORTO receive data buffer channel B data TX1 B Oxfe SPORTI transmit data buffer channel B data RX1 B Oxff SPORTI receive data buffer channel B data 4 6 SPORTO I S Mode IOP Register Configuration For 21065L EZ LAB Loopback Test The configuration for SPORTO for the first example in the Appendix A is set up as follows 32 bit serial word length Enable SPORTO transmit and receive DMA functionality Enable DMA chaining functionality for SPORTO transmit and receive Internal TX Serial Clock TCLKO the SPORTO T S transmitter provides the serial clock to the 65L8 SPORTO receiver Internal TFSO thus the SPORTO channel A transmitter is the T S master External RX Serial Clock RCLKO and Word Select RFSO thus the receiver Channel A port is the slave Transmit and Receive DMA chaining enabled The dsp program declares 2 buffers i2s tx buf 2 and i2s rx buf 2 for DMA transfers of SPORTO I2S transmit and receive stereo data on Channel A var i2s rx buf STEREO LR stereo I2S receive buffer var i2s tx buf STEREO LR stereo I2S transmit buffer Program I2Smode SPORTO Registers sport0 receive control register RO Ox000DOO9F1 slave mode slen 32 sden A amp schen A enabled dm SRCTLO RO sport 0 receive control register sportO transmit control register RO OxOOODODF1 master mode data depend sl
38. l send i2s right channel increment count save updated count return from interrupt delayed branch restore primary registers RO R7 Disclaimer Information furnished by Analog Devices Inc is believed to be accurate and reliable However no responsibility is assumed by Analog Devices Inc for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under the patent rights of Analog Devices Analog Devices Inc reserves the right to make changes without further notice to any products listed in this document Analog Devices makes no warranty representation or guarantee regarding the suitability of its DSP products for any particular application nor does Analog Devices assume any liability arising out of the application or use of our DSP based products and specifically disclaims any and all liability including without limitation consequential or incidental damages Operating parameters such as temperature and voltage can and do vary in different applications All operating parameters as specified in Analog Devices data sheets must be validated for each customer application by customer s technical experts Analog Device s DSP based products are not designed intended or authorized for use as components in which the failure of the Analog Devices product could create a situation where personal injury or death may occur If t
39. lly receive AES EBU and SP DIF information and convert the audio information into the IS or parallel format for the ADSP 21065L as well as provide status information through flag pins or a parallel interface that is received along with the audio data Digital Audio Transmitters can take an I S audio stream from the ADSP 21065L and transmit the audio data along with control information in AES EBU and SPD IF formats Control and status information contains useful information such as the sampling rate of the data being transmitted or received 4 Configuring the ADSP 21065L Serial Port Interface In IS Mode When interfacing an I S device to an ADSP 21065L processor the interconnection between both devices can be through either SPORTO or SPORTI In this application note SPORTO is used to demonstrate the I2S loopback test since SPORT is activated for communications with the AD1819a SoundPort Codec Figure 7 ADSP 21065L SPORTs a Rx0 TX0 RX0 TX0 RnRrso0 ADSP TFS am RCKO TCK0 21065L gt RXI TX1 L gt RX TX1 L J RFS1 TFS RCK1 TCK1 In order to facilitate serial communications with an I S compatible device the DSP designer would simply tie the device to either the SPORTO and SPORTI pins as shown in the above diagram Table 1 below
40. low The SPORT DMA IOP registers are covered in section 4 8 As we will see in the next section only a few of the available registers shown below need to be programmed to set up I S mode These registers are highlighted in bold text SPORTO SPORT1 SPORT Data Buffers Table 8 Serial Port IOP Registers Register IOP Address Description STCTLO OxeO SPORTO transmit control register SRCTLO Oxel SPORTO receive control register TDIVO Oxe4 SPORTO transmit divisor RDIVO Oxe6 SPORTO receive divisor MTCSO Oxe8 SPORTO multichannel transmit select MRCSO Oxe9 SPORTO multichannel receive select MTCCSO Oxea SPORTO multichannel transmit compand select MRCCSO Oxeb SPORTO multichannel receive compand select KEYWDO Oxec SPORTO receive comparison register IMASKO Oxed SPORTO receive comparison mask register STCTLI Oxf0 SPORT transmit control register SRCTLI Oxf1 SPORTI receive control register TDIV1 Oxf4 SPORT transmit divisor RDIV1 Oxf6 SPORTI receive divisor MTCSI Oxf8 SPORTI multichannel transmit select MRCSI Oxf9 SPORT 1 multichannel receive select MTCCS1 Oxfa SPORTI multichannel transmit compand select MRCCSI Oxfb SPORTI multichannel receive compand select KEYWDI Oxfc SPORTI receive comparison register IMASKI Oxfd SPORTI receive comparison mask register TX0 A Oxe2 SPORTO transmit data buffer channel A data RXO A Oxe3 SPORTO receive data buffer channel A data TX1 A Oxf2 SPORTI transmit data buffer channel A data RX1 A Oxf3 SPORTI rece
41. mit block chain pointer initiate tx0 DMA xfers pointer register internal dma address used for chaining DMA internal memory DMA modifier DMA internal memory buffer count get DMA chaining int mem pointer containing tx buf addr mask the pointer set the pci bit write DMA transmit block chain pointer to TCB buffer transmit block chain pointer initiate tx0 DMA x fers pointer register internal dma address used for chaining DMA internal memory DMA modifier DMA internal memory buffer count mask the pointer set the pci bit write DMA receive block chain pointer to TCB buffer receive block chain pointer initiate rx0 DMA transfers pointer register internal dma address used for chaining DMA internal memory DMA modifier DMA internal memory buffer count mask the pointer set the pci bit write DMA receive block chain pointer to TCB buffer receive block chain pointer initiate rx0 DMA transfers B 2 SPORTO Interrupt Processing Routine AD DA Audio Loopback Figure 13 Dual ADC DAC Software Driver ISR Data Flow Structure SPORTO ADC 1 RX0A DMA Buffer RX0A_BUF 2 DM Audio Data ane SPORTO ADC data RXOA register DSP Audio Algorithm SPORTO DAC 1 TX0A DMA Buffer TXOA BUF 2 DM Audio Data DM Left ChannelA Out M Right ChannelA Out SPORTO DAC data TXOA register SPORTO ADC 2 RXOB DMA Buffer RXOB BUF 2
42. mit tcb 7 r0 internal dma address used for chaining r0 1 dm I2s xmit tcb 6 r0 DMA internal memory DMA modifier r0 2 dm I2s xmit tcb 5 r0 DMA internal memory buffer count r0 I2s xmit tcb 7 get DMA chaining internal mem pointer containing tx buf address r0 rl AND r0 mask the pointer r0 BSET r0 BY 17 set the pci bit dm I2s xmit tcb 4 r0 write DMA transmit block chain pointer to TCB buffer dm CPTOA r0 transmit block chain pointer initiate tx0 DMA transfers sportO dma control rx chain pointer register r0 I2s rx buf dm I2s rcv tcb 7 r0 internal dma address used for chaining r0 1 dm I2s rcv tcb 6 r0 DMA internal memory DMA modifier r0 2 dm I2s rcv tcb 5 r0 DMA internal memory buffer count r0 I2s rcv tcb 7 r0 rl AND r0 mask the pointer rO BSET r0 BY 17 set the pci bit dm I2s rcv tcb 4 write DMA receive block chain pointer to TCB buffer dm CPROA r0 receive block chain pointer initiate rx0 DMA transfers RTS endseg Below are example assembly instructions used to set up the Transfer Control Blocks for SPORTO Channels A amp B in the 4 channel ADC DAC loopback example shown in Appendix B These values are reloaded from internal memory to the DMA controller after the entire SPORT DMA buffer has been received or transmitted segment dm dm I2S define buffer size to matc
43. on receive dm MTCCSO RO no companding on transmit e Multichannel Mode Disabled sportO0 receive and transmit multichannel word enable registers RO 0x00000000 enable transmit and receive channels 0 8 dm MRCSO RO dm MTCSO 4 7 SPORTO I S Mode IOP Register Configuration For Interfacing to 2 24 bit 96 kHz Stereo ADCs and DACs The configuration for SPORTO for the second example in the Appendix A is set up as follows 24 bit serial word length Enable SPORTO transmit and receive DMA functionality on Channels A amp B Enable DMA chaining functionality for SPORTO transmit and receive on Channels A amp B Slave Mode for the I2S channel A amp B transmitters and receivers e External TX Serial Clock TCLKO the SPORTO I S transmit clock for Channels A amp B is externally generated e External TFSO thus the SPORTO channel A and B transmitters are the TS slave devices e External RX Serial Clock RCLKO and Word Select RFSO thus the receiver Channel A port is the slave Transmit and Receive DMA chaining enabled The dsp program declares 4 DMA buffers tx0a_buf 2 tx0b buf 2 rx0a_buf 2 rx0b buf 2 for DMA transfers of SPORTO transmit and receive serial stereo left right data on channels A amp B define STEREO_LR 2 var rx0a_buf STEREO LR stereo I2S primary receive a buffer var rxO0b buf STEREO LR stereo I2S secondary receive b buffer var tx0a buf STEREO LR
44. r or for the receiver The software application must demultiplex the left and right channel data received by the RX buffer this means that when data is transferred to areceive DMA buffer the data is interleaved where the left and right data alternate in consecutive locations in memory 4 4 SPORT DMA Channels and Interrupt Vectors There are 8 dedicated DMA channels for the I2S channel A and B buffers on both SPORTO and SPORT1 The IOP addresses for the DMA registers are shown in the table below for each corresponding channel and SPORT data buffer Table 6 8 SPORT DMA channels and data buffers Chn Data Buffer Address Description 0 Rx0A 0x0060 0x0064 Serial port 0 receive A data 1 Rx0B 0x0030 0x0034 Serial port 0 receive B data 2 Rx1A 0x0068 0x006C Serial port 1 receive A data 3 Rx1B 0x0038 0x003C Serial port 1 receive B data 4 Tx0A 0x0070 0x0074 Serial port 0 transmit A data 5 Tx0B 0x0050 0x0054 Serial port 0 transmit B data 6 Tx1A 0x0078 0x005C Serial port 1 transmit B data 7 Tx1B 0x0058 0x005C Serial port 1 transmit B data Each serial port has a transmit DMA interrupt and a receive DMA interrupt shown in Table 7 below With serial port DMA disabled interrupts occur on a word by word basis when one word is transmitted or received Table 7 also shows the interrupt priority because of their relative location to one another in the interrupt vector table The lower the
45. re e Continuous serial clock SCK RCLKx or TCLKx if the 21065L is the master e Word Select WS RFSx or TFSx if the 21065L is the master e Serial Data SD DTx DRx on the 21065L SPORTS this is in a 2 channel time division multiplexed format The transmitter receiver or and system clock controller generates the serial clock and word select signals Thus the I2S device that generates the serial clock and word select is the master I2S device The Philips S bus defines the following Serial Data Pins e Serial data is transmitted in two complement format with the MSB transmitted first because the transmitter and receiver may have different word lengths The receiver ignores extra bits from the transmitter if greater than it capable or programmed serial length If the receivers word length is greater than the data sent all missing bits are set to zero internally The transmitter always sends the MSB of the next word one clock period after the WS changes Serial data sent by the Transmitter can be sync d with either the trailing or leading edge of the SCLK The Receiver or the device in Slave Mode always latches data on the leading edge of SCLK Word Select Pins When WS 0 or fow the data is Channel 1 or Left Channel data in a stereo system When WS 0 or tow the data is Channel 2 or Right Channel data in a stereo system WS may change on a trailing or leading edge of the SCLK but it does not need to be symmetrical
46. receive control registers Read only registers Indicates the status of channel A transmit buffer contents 00 empty 10 partially full 11 full 01 reserved This is useful in detecting if the interrupt generated was because of data transmitted received in channel A or channel B for interrupt driven transfers 4 2 States of SPORT Pins When Operating in Master or Slave Mode The following tables 2 through 5 show the states of the pins on both SPORTO and SPORTI when the 21065L is set up for either master mode or slave mode The states of the pins are shown for either a transmitter or reciever The particular pins are matched up with the pins of the connecting I2S device in the second column showing generic definitions for the I2S compatible device which contains a serial clock word select and serial data signals The states of these pins which are either outputs or inputs are indicated in the third column in the tables Table 2 21065L IS Receiver in Master Mode ADSP 2106x Pin PS Device Pin Driven By RCLKO RCLK1 SCLK 21065L RFSO RFS1 WS Word Select 21065L DROA DROB DR1A DRIB SD Serial Data Out PS device Table 3 21065L lS Receiver in Slave Mode ADSP 2106x Pin PS Device Pin Driven By RCLKO RCLK1 SCLK PS device RFSO RFS1 WS Word Select PS device DROA DROB DR1A DRIB SD Serial Data Out PS device Table 4 21065L lS Transmitter in Master Mode ADSP 2106x Pin PS Device Pin Driven By TCLKO TCLK1 SCLK
47. rters Figure 1 ADSP 21065L Serial Port I S Interconnection Pins a RX0a TXO m 3 RX0b TX0 m Rrso ADSP TES lt a RCKO TCK0 21065L 3 RX1a TX1 r RX1b TX1 RFS1 Ts H gt RCK TCK1 4 RX Inputs with lS support 4 TX Outputs with I S support Supports 8 Input Audio Channels Supports 8 Output Audio Channels The ADSP 21065L includes 2 on chip serial ports SPORTO and SPORTI that contain a new I S mode of operation Figure 1 shows the basic serial connections that enable this interface The ADSP 21065L38 two serial ports provide 4 receive inputs and 4 transmit outputs to allow the processing of 8 I S input audio channels and playback through 8 I S output audio channels 1 Philips lS Serial Bus Protocol Overview In consumer and professional audio products of recent years the analog or digital front end of the DSP uses a digital audio serial protocol known as I S Audio interfaces between various ICs in the past was hampered because each manufacturer had dedicated audio interfaces that made it extremely difficult to interface these devices to each other Standardization of audio interfaces was promoted by Philips with the development of the Inter IC Sound I S bus a serial interface developed for digital audio to enable easy connectivity and ensure successful designs In
48. s left channel rx data r0 lshift r0 by 8 shift up to MSBs to preserve sign rl dm rx0b buf RIGHT Get i2s right channel rx data rl lshift rl by 8 shift up to MSBs to preserve sign dm Left ChannelB In r0 dm Right ChannelB In rl loop back unaltered ADC data dm Left ChannelB Out r0 dm Right ChannelB Out rl Ge aR ae OR Ee EEO Re TO ea IE TN RRO EE NRO DE RORY RT BE fE user_applic User Applications Routines Insert DSP Algorithms Here AA x Input L R Data Streams DM Left Channel In DM Right Channel In f Output L R Results DM Left Channel Out DM Right Channel Out XJ BS EJ A These left right data holders are used to pipeline data through multiple modules and JE can be removed if the dsp programmer needs to save instruction cycles Ky J TREIN AANA eG A AA Se A o NERAN oe t ANM AREAN ESAEREN AAE SNAN AAEE AEN Kj i Coding TIP sf yo The samples from the AKM ADCs are 24 bit and are in the lower 24 bits of the the 32 bit xf E word They are shifted to the most significant bit positions in order to preserve the f fr sign of the samples when they are converted to floating point numbers The values are ud JE also scaled to the range 1 0 with the integer to float conversion EY 7E 0 float r0 by r1 ay 2 pe To convert between our assumed 1 31 fractional number and IEEE floating point math pE here are some example assembly instructions
49. shows the function of all of the serial port pins Table 1 ADSP 21065L Serial Port Pins SPORTO SPORT1 Function A Chn B Chn A Chn B Chn Transmit data DTOA DTOB DT1A DT1B Transmit clock TCLKO TCLK1 Transmit frame sync TFSO TFS1 word select Receive data DROA DROB DR1A DR1B Receive cock RCLKO RCLK1 Receive frame sync RFSO RFS1 Notice that both SPORTS have 2 channel or data pins for both the transmit side and the receive side Transmit A Channels DTOA DT1A Transmit B Channels DTOB DT1B Receive A Channels DROA DR1A Receive B Channels DROB DR1B Both the transmitter and receiver have their own serial clocks The TFSx and RFSx pins become word select signals in I2S mode versus being regular small pulse signals that initiate shifting of data Both channel A and channel B share both the serial clock and frame syncs For example DROA and DROB use the RCLKO and RFSO signals to receive data regardless if they are internally or externally generated Since there are 8 data pins 4 transmit and 4 receive channels then for S mode of operation where two channels of data of transmitted or received on each data pin the actual number of channels is doubled Therefore both serial ports combined gives the capability of passing up to 8 input channels of audio to the DSP and 8 output channels of audio giving 16 audio streams with both SPORTS 4 1 l S related bits in the SPORT Transmit and Recei
50. stereo I2S primary transmit a buffer var tx0b buf STEREO LR stereo I2S secondary transmit b buffer Program I2Smode SPORTO Registers sport0 receive control register RO 0x013C0971 slave mode slen 24 sden A amp schen A amp sden B amp schen B enabled dm SRCTLO RO sport 0 receive control register sportO0 transmit control register RO 0x017C8971 slave mode slen 24 sden A amp schen A amp sden B amp schen B enabled dm STCTLO R0 sport 0 transmit control register The ADSP 21065L transmitter and receiver A and B channels accept an externally generated 96 kHz serial clock RCLKO and TCLKO frame sync TFSO and RFSO Therefore the divisor registers are set to zero sport0 I2S word select transmit frame sync divide register RO 0x00000000 TCLKDIV 2xfCLKIN 60MHz SCLKfreq 12MHz 1 dm TDIVO R0 TFSDIV TCLKfrq 12 MHz TFSfrq 96 0K 1 sport0 I2S receive word select divide register RO 0x00000000 dm RDIVO R0 Multichannel Mode Disabled sportO0 receive and transmit multichannel word enable registers RO 0x00000000 multichannel mode disabled dm MRCSO RO dm MTCSO RO No companding sportO transmit and receive multichannel companding enable registers RO 0x00000000 no companding dm MRCCSO RO no companding on receive dm MTCCSO RO no companding on transmit 4 8 DMA Regi
51. sters for the I S Ports The following register descriptions are provided in the defs210651 h file for programming the DMA registers associated with the I O processors DMA controller We will look at how these registers are programmed for DMA chaining in which the DMA registers are reinitialized automatically whenever a serial port interrupt request is generated Table 9 SPORT DMA IOP Registers DMA Register Description DMA Register IOP Address SPORTO Receive DMA Channel 0 Index Register IIROA 0x60 Channel A DMA Channel 0 Modify Register IMROA 0x61 DMA Channel 0 Count Register CROA 0x62 DMA Channel 0 Chain Pointer Register CPROA 0x63 DMA Channel 0 General Purpose Register GPROA 0x64 SPORTO Receive DMA Channel 1 Index Register IIROB 0x30 Channel B DMA Channel 1 Modify Register IMROB 0x31 DMA Channel 1 Count Register CROB 0x32 DMA Channel 1 Chain Pointer Register CPROB 0x33 DMA Channel 1 General Purpose Register GPROB 0x34 SPORT1 Receive DMA Channel 2 Index Register IIRIA 0x68 Channel A DMA Channel 2 Modify Register IMRIA 0x69 DMA Channel 2 Count Register CRIA Ox6A DMA Channel 2 Chain Pointer Register CPRIA 0x6B DMA Channel 2 General Purpose Register GPR1A 0x6C SPORT1 Receive DMA Channel 3 Index Register IIRIB 0x38 Channel B DMA Channel 3 Modify Register IMRIB 0x39 DMA Channel 3 Count Register CRIB Ox3A DMA Channel 3 Chain Pointer Register CPRIB Ox3B DMA Channel 3 General Purpose Register GPRIB Ox3C SPORTO Transmit DMA Channel 4 Index Register
52. the left channel when processing 16 bit samples 32 bit Fixed Point Processing rl dm rx0a_buf 0 get ADC left channel input sample rl lshift rl by 16 shift up to MSBs to preserve sign dm Left Channel r1 save to data holder for processing Process data here data is processed in 1 31 format r15 dm Left Channel get channel 1 output result x15 lshift r6 by 16 put back in bits 0 15 for SPORT tx dm tx0a buf 0 r15 output left result to DAC To convert to a floating point number or from a floating point number back to a fixed point number the ADSP 21065L supports single cycle data format conversion between fixed and floating point numbers as shown below 32 bit Floating Point Processing To convert between our assumed 1 31 fractional number and IEEE floating point math here are some example assembly instructions This assumes that our ADC data has already been converted to floating point format as shown above rl Sih scale the sample to the range of 1 0 DM Left Channel float r0 by rl Call Floating Point Algorithm 31 scale the result back up to MSBs fix 8 by rl eft Channel r8 REFERENCES The following sources contributed information to this applications note 1 ADSP 21065L SHARC User s Manual Analog Devices Inc First Edition 82 001833 01 Analog Devices September 1998 2 Philips I2S Bus Specification Philips Semiconductor El
53. transmitter sends the left channel first and the master receiver shifts in the right channel first The L FIRST control bit is ignored for slave mode refer to anomaly list With these earlier revisions there is no way to select if the first transmitted or received word at startup will align to the left or right I2S channel unless the WS pin is connected to a flag input pin for detection at the enabling of the SPORT SLEN Data Word Length bits 4 8 This bit sets the serial word length the value specified in the register is SLEN The serial data length can be from 3 to 32 bits in length FS BOTH Frame Sync Word Generation bit 22 transmit control registers only This applies for the transmit control register only This bit select when during transmission to issue the word select change in the state of WS If F5 BOTH 0 the word select state change high to low or low to high is issued if data is in either the transmit A or transmit B channel If F5 BOTH 1 the word select toggles state only if data is in BOTH the transmit A and B channels SPL Sport Loopback Mode bit 22 receive control registers only This internally loops back the transmit side to the receive side of the same channel TX A to RX A TX B to RX B This is useful for running internal SPORT tests and debugging code SPL 0 disables loopback mode SPL 1 enables loopback mode SPEN A SPORT Channel A Enable bit 0 This enables and disables the SPORT
54. ve Control Registers The ADSP 21065L has two transmit STCTLO STCLT1 and two receive SRCTLO SRCTL 1 control registers for configuring the timing signals data size and DMA parameters Figure 8 below highlights the related bits Figure 8 12S Control bits in the SPORT Control Registers S enable 9 Sport channel enable SPEN x Word length SLEN S channel transfer order L FIRST Frame sync word select generation Master mode enable DMA channel enable SDEN x DMA chaining enable SCHEN x OPMODE Operation Mode bit 11 Setting this bit to a 1 will enable I2S mode versus standard mode when it is 0 MSTR Master Slave Mode Enable bit 10 When this bit is set to a 1 in the SPORT transmit control register then the transmitter is the master When it is cleared the transmitter is the slave When this bit is set to a 1 in the SPORT receive control register then the receiver is the master When it is cleared the receiver is the slave For Master Mode the frame sync word select and serial clock is internally generated and values must be specified in the transmit or receive divisor registers For Slave Mode the frame sync word select and serial clock is externally generated and any values specified in the divisor registers are ignored For I2S master mode only in revs 0 2 and prior otherwise it is applicable for master and slave parts of revision 0 3 and greater With this bit set the master
55. ways transmits in MSB format e You can select either DMA driven or interrupt driven transfers e TFS and RFS are the transmit and receive word select signals e Multichannel operation and companding are not supported Both transmitters share a common interrupt vector and both receivers share a common interrupt vector To determine the source of an interrupt applications must check the TXSx or RXSx data buffer status bits respectively this applies only for interrupt driven transfers When using both transmitters FS_BOTH 1 and MSTR 1 and DITFS 0 the processor generates a frame sync signal only when both transmit buffers contain data because both transmitters share the same CLKDIV and TFS So for continuous transmission both transmit buffers must contain new data To enable continuous transmission when only one transmit buffer contains data set FS_BOTH 0 When using both transmitters and MSTR 1 and DITFS 1 the processor generates a frame sync signal at the frequency set by FSDIV x whether or not the transmit buffers contain new data In this case the processor ignores the FS_BOTH bit The DMA controller or the application is responsible for filling the transmit buffers with new data The SPORT generates and interrupt when the transmit buffer has a vacancy or whenever the receive buffer has data Each transmitter and receiver has its own set of DMA registers The same DMA channel drives both the left and right I S channels for the transmitte
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