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S3F94C8/F94C4

1. 11 10 11 1 3 PWM Extension Register inneren nnne nens 11 11 12 usEee i2 gpl M 12 1 12 1 Overview of A D Converter 12 1 12 1 1 Using A D Pins for Standard Digital 1 12 2 12 1 2 A D Converter Control Register ADCON 4 12 2 12 1 3 Internal Reference Voltage Levels sss nee 12 3 12 1 4 Conversion Timing a otn transite tnn into Le ao ulin atre VE aera avden 12 4 12 1 5 Internal A D Conversion 12 5 13 EMBEDDED FLASH MEMORY 13 1 13 1 Overview of Embedded Flash Memory 13 1 18 1 1 Flash ROM Configuration 13 1 13 1 1 1 Tool Program 13 2 13 4 1 2 User Program Mode EE aded 13 2 13 2 Flash Memory Control Registers User Program Mode 13 3 13 2 1 Flash Memory Control Register enne nennen nnne nene 13 3 13 2 2 Flash Memory User Programming Enable Register FMUSR 13 3
2. 3 11 3 1 11 Relative Address Mode e retten a pice ee a esae 3 12 3 1 12 Immediate biene need 3 12 4 ADDRESSING REGISTERS Luanda 4 1 4 1 Overview of Control Registers 4 1 4 1 1 ADCON A D Converter Control Register 7 4 5 4 1 2 Basic Timer Control Register DCH 4 6 4 1 3 Clock Control Register 4 nennen 4 7 4 1 4 FLAGS System Flags Register 4 8 4 1 5 FMCON Flash Memory Control Register 1 4 9 4 1 6 FMSECH Flash Memory Sector Address Register High Byte 4 10 4 1 7 FMSECL Flash Memory Sector Address Register Low Byte 4 10 4 1 8 FMUSR Flash Memory User Programming Enable Register 4 10 4 1 9 POCONH Port 0 Control Register High Byte sse 4 11 SAMSUNG ELECTRONICS um 4 1 10 POCONL Port 0 Control Register Low Byte 7 4 12 4 1 11 POPND Port 0 Interrupt Pending Register E8H
3. 2 2 2 2 1 Normal Operating ide i aet 2 2 2 2 2 Smart tens ce doe da bd Duda eaa oc ed ba den nav ade 2 8 2 8 Register ArchIteCture ier eiat 2 5 2 4 Common Working Register Area 1 eene ns 2 7 2 5 System eie a ir e 2 8 2 51 Stack Operations 2 8 2 5 2 Stack Pointer aet Eee Era 2 8 4 ADDRESSING MODES Qu 3 1 3 1 Overview of Addressing Modes 3 1 3 1 1 Register Addressing Mode nennen netter inten 3 2 3 1 2 Indirect Register Addressing cider oe tert ie tinea 3 3 3 1 3 Indirect Register Addressing Mode 1 sss ener nnne nent 3 4 3 1 4 Indirect Register Addressing Mode 2 sse eene tenens 3 5 3 1 5 Indirect Register Addressing Mode 3 sse esent nnne nennen 3 6 3 1 6 Indexed Addressing Mode anal e ft rentrer tx Esa 3 7 3 1 7 Indexed Addressing Mode 1 3 8 3 1 8 Indexed Addressing end 3 9 3 1 9 Direct Address Mode a a 3 10 3 1 10 Direct Address Mode 1
4. 15 3 16 SOP 225 Package 01 15 4 16 TSSOP 0044 Package Dimensions 15 5 S3F94C8 F94C4 Pin Assignments 20 DIP 20SOP 16 2 S3F94C8 F94C4 Pin Assignments 16 5 16 2 PCB design guide for On board programming 16 4 S3F94C8 F94C4 Flash 1 16 6 Development System Configuration sess eee enne 17 2 TB94C8 94C4 Target Board Configuration sse nennen 17 3 DIP Switch for Smart nennen tentent 17 7 20 Pin Connector for 94 8 94 4 sensisse en 17 8 S3F94C8 F94C4 Probe Adapter for 20 DIP 17 8 Table Number Table 1 1 Table 1 2 Table 2 1 Table 4 1 Table 5 1 Table 6 1 Table 6 2 Table 6 3 Table 6 4 Table 6 5 Table 6 6 Table 6 7 Table 8 1 Table 9 1 Table 9 2 Table 11 1 Table 11 2 Table 11 3 Table 11 4 Table 13 1 Table 14 1 Table 14 2 Table 14 3 Table 14 4 Table 14 5 Table 14 6 Table 14 7 Table 14 8 Table 14 9 Table 14 10 Table 14 11 Table 14 12 List of Tables Title Page Number S3F94C8 F94C4
5. Disables watchdog timer function Others Enables watchdog timer function 3 2 Basic Timer Input Clock Selection Code 0 Basic Timer and Timer 0 Divider Clear Bit No effect Clears both dividers NOTE When you write a 1 to BTCON 0 or BTCON 1 the basic timer divider and timer 0 divider basic timer counter are cleared The bit is then cleared automatically to 0 SAMSUNG ELECTRONICS 4 6 S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 3 CLKCON Clock Control Register D4H Bit Identifier Reset Value EN 7 Oscillator IRQ Wake up Function Enable Bit Enables IRQ for main system oscillator wake up function 1 Disables IRQ for main system oscillator wake up function 6 5 Not used for S3F94C8 F94C4 4 3 Divided by Selection Bits for CPU Clock frequency Divide by 16 fOSC 16 1 Divide by 8 fOSC 8 1 Divide by 2 foSC 2 Non divided clock fOSC SAMSUNG ELECTRONICS S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 4 FLAGS System Flags Register D5H Bitidentifier 7 6 5 4 3 2 1 o REETVe x x x _ _ Rw Rw Rw ee 7 Carry Flag C EN Operation does not generate a carry or borrow condition Operation generates a carry out or borrow into high order bit 7 6 Zero Flag Z Operation result is a non zero value Operation result is zero 5 Sign Flag S KI Operation ge
6. nennen nenas 11 6 Extended PWM Waveform 6 5 base 6 bit extension 11 7 PWM Basic Waveform 8 bit 11 8 PWM Basic Waveform 8 bit base 6 bit extension 11 9 PWM Control Register 11 10 PWM Extension Register 11 11 PWM Data Register PWMDATA 2 ccecceeceeeseeceeeeeeeeeeeeeaeecaeecaeecaaesaaeceaeceaeseaesesaeseaeeneeeneesas 11 11 PWM Module Functional Block 11 12 A D Converter Control Register ADCON enhn nennen nennen 12 2 A D Converter Circuit Diagram 12 3 A D Converter Data Register 4 12 3 A D Converter Timing Diagrams 12 4 Recommended A D Converter Circuit for Highest Absolute 12 5 Flash Memory Control Register FMCON nnne nnne nnns 13 8 Flash Memory User Programming Enable Register 13 3 Flash Memory Sector Address Register FMSECH
7. pair working register R11 40 Load flash memory lower address into lower register of pair working register SAMSUNG ELECTRONICS 13 12 Lm S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE RR10 R9 Write data A3H at flash memory location R11 R1 NZ WR_BYTE FMUSR 00H Disable User Program mode RR10 R9 Write data written by R9 at flash memory location R11 RO NZ WR_BYTE SAMSUNG ELECTRONICS 13 13 ex S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 5 Reading The read operation starts by LDC instruction 13 5 1 Program Procedure in User Program Mode 1 Load flash memory upper address into upper register of pair working register 2 Load a flash memory lower address into lower register of pair working register 3 Load received data from flash memory location area on LDC instruction by indirectly addressing mode Example 13 3 Programming Tip Reading Load flash memory s upper address to upper register of pair working register Load flash memory s lower address to lower register of pair working register Read data from flash memory location Between 300H and 3FFH R3 R3 NZ LOOP SAMSUNG ELECTRONICS 13 14 er S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 6 Hard Lock Protection You can set Hard Lock Protection by writing 0110B in FMCON7 4 This function
8. 1 16 3 Comparison of S3F94C8 F94C4 Features 16 3 Reference Table for Connection enne nennen enne nnns nnns 16 5 Operation Results Comparison of Main Flash ROM and Information Blocks 16 6 Components of 94 8 94 4 asta santet 17 4 Power Selection Settings for 4 8 94 4 nnne 17 4 SMDS2 Tool Selection Setting 1 nnns 17 5 Using Single Header Pins to Select Clock Source PWM Operation Mode 17 6 Using Single Header Pins as the Input Path for External Trigger Sources 17 7 SAMSUNG ELECTRONICS er Example Number Example 2 1 Example 2 2 Example 2 3 Example 8 1 Example 10 1 Example 10 2 Example 11 1 Example 12 1 Example 13 1 Example 13 2 Example 13 3 Example 13 4 SAMSUNG ELECTRONICS List of Examples Title Page Number Programming Tip Smart Option Setting 4 2 4 Programming Tip Addressing the Common Working Register 2 7 Programming Tip Standard Stack Operations Using PUSH and POP 2
9. 13 4 Flash Memory Sector Address Register FMSECL sse 13 4 Sector configurations in User Program 13 5 Sector Erase Flowchart in User Program Mode 13 6 Byte Program Flowchart a User Program sse 13 9 Program Flowchart a User Program Mode eene 13 10 Figure 14 1 Figure 14 2 Figure 14 3 Figure 14 4 Figure 14 5 Figure 14 6 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 Figure 15 5 Figure 16 1 Figure 16 2 Figure 16 3 Figure 16 4 Figure 17 1 Figure 17 2 Figure 17 3 Figure 17 4 Figure 17 5 SAMSUNG ELECTRONICS Input Timing Measurement Points enne nnne 14 4 Operating Voltage Range ridet rege ein tx Y ER eta dun pne 14 7 Schmitt Trigger Input Characteristics 14 7 Stop Mode Release Timing When Initiated by a RESET 14 8 Batu 14 9 Circuit Diagram to Improve EFT Characteristics 14 10 20 DIP 300A Package 15 1 20 SOP 375 Package Dimensions sss eene 15 2 20 SSOP 225 Package Dimensions
10. sss nsns tenent 7 2 System Clock Circuit 7 3 SAMSUNG ELECTRONICS ep Figure 8 1 Figure 8 2 Figure 8 3 Figure 8 4 Figure 9 1 Figure 9 2 Figure 9 3 Figure 9 4 Figure 9 5 Figure 9 6 Figure 9 7 Figure 9 8 Figure 9 9 Figure 9 10 Figure 10 1 Figure 10 2 Figure 10 3 Figure 10 4 Figure 10 5 Figure 10 6 Figure 10 7 Figure 11 1 Figure 11 2 Figure 11 3 Figure 11 4 Figure 11 5 Figure 11 6 Figure 11 7 Figure 11 8 Figure 11 9 Figure 11 10 Figure 11 11 Figure 12 1 Figure 12 2 Figure 12 3 Figure 12 4 Figure 12 5 Figure 13 1 Figure 13 2 Figure 13 3 Figure 13 4 Figure 13 5 Figure 13 6 Figure 13 7 Figure 13 8 SAMSUNG ELECTRONICS Low Voltage Reset CircCuit essessssssssssseseseseenene enne nenne tentes estt sentes entis nn nain nn nens 8 2 Recommended External RESET eene nennen nnns 8 3 Reset Block Diagram eite ra ere HEAD deae sri de nis 8 4 Timing for S3F94C8 F94C4 After RESET ener enne nnns 8 4 Port Data Register Format tiere tite eee d vu 9 2 Port 0 Circuit Diagram s e ent eim Fee b rr 9 3 Port 0 Control Register POCONH High Byte 9 4 Port 0 Control Register POCONL Low nennen 9 5 Port 0 Interrupt Pending Regis
11. Schmitt trigger input pull up enable fo i Schmitt trigger input Push pull output A D converter input ADC5 Schmitt trigger input off 1 0 Port 0 P0 4 ADC4 Configuration Bits Schmitt trigger input pull up enable Schmitt trigger input A D converter input ADC4 Schmitt trigger input off SAMSUNG ELECTRONICS 4 11 en S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 10 POCONL Port 0 Control Register Low Byte E7H Bitidentifier 7 6 5 4 3 2 a o o o o o 9 9 9 7 6 Port 0 PO 3 ADC3 Configuration Bits Schmitt trigger input Schmitt trigger input pull up enable Push pull output A D converter input ADC3 Schmitt trigger input off 5 4 Port 0 P0 2 ADC2 Configuration Bits Schmitt trigger input FET Schmitt trigger input pull up enable Push pull output A D converter input ADC2 Schmitt trigger input off 3 2 Port 0 PO 1 ADC1 INT1 Configuration Bits Schmitt trigger input falling edge interrupt input fo i Schmitt trigger input pull up enable falling edge interrupt input Push pull output A D converter input ADC1 Schmitt trigger input off 1 0 Port 0 PO 0 ADCO INTO Configuration Bits Schmitt trigger input falling edge interrupt input Schmitt trigger input pull up enable falling edge interrupt input Jorun A
12. Figure 3 7 Indexed Addressing to Register File SAMSUNG ELECTRONICS 3 7 I S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES 3 1 7 Indexed Addressing Mode 1 Program Memory Register File 4 Bit Working ES gt Register Register Address Point to working Pair register pair pe lie pF added to LSB Selects offset 8 Bit 16 Bit Program Memory or Data memory Value used in OPERAND instruction Sample Instructions LDC 04H RR2 The values in the program address RR2 04H are loaded into register R4 LDE R4 404H RR2 Identical operation to LDC example except that external program memory is accessed Figure 3 8 Indexed Addressing to Program or Data Memory with Short Offset SAMSUNG ELECTRONICS 3 8 im S3F94C8 F94C4_UM_REV 1 00 3 1 8 Indexed Addressing Mode 2 Program Memory dst src 4 Bit Working Register Address LSB Selects 16 Bit Sample Instructions LDC R4 1000H RR2 LDE R4 1000H RR2 Figure 3 9 SAMSUNG ELECTRONICS 3 9 NEXT 3 Bits Point to working register pair 1 of 8 3 ADDRESSING MODES Register File Register 16 Bit address added to offset 16 Bit Program Memory or Datamemory Value used in instruction OPERAND The values in the program address RR2 1000H are loaded into register R4 Identical operation to LDC example except that external program memory is accessed Indexed Addressing to Program or Dat
13. 1 6 13 6 1 7 Gall Procedure ritieni 6 14 6 1 7 5 CCF Complement Carry Flag sse 6 15 6 1 7 6 Cle mE 6 16 6 1 7 COM Gomnplement 2 1 EEG dd ELE a d Rege a dee 6 17 6 1 78 CP Gompalte i dai ere 6 18 61 79 DEG Decrement eire a rede 6 19 6 1 7 10 DI Disable nennen nnn nennen nennen nin 6 20 6 1 7 11 El Enable Interr pts 6 21 6 1 7 12 IDLE Idle Op ration iiie erben tbt nter 6 22 6 1 7 13 ING Inre ment iride ecd rece bor abad ieee ek 6 23 6 1 7 14 IRET Interrupt Return inneren sinn enne 6 24 6 1 7 15 JP iS 6 25 6 1 7 16 JR Jump 6 26 SAMSUNG ELECTRONICS IP LD LO a ER 6 27 6 1 7 18 LDO EDE Load 6 29 6 1 7 19 LDCD LDED Load Memory and Decrement sse 6 32 6 1 7 20 LDCI LDEI Load Memory and 6 33 6 1 7 21 NOP No erre sore ERR 6 34 6 1 7 22 0B Logical OR tee ter c ipto 6 35 6 1 7 23 POP Pop From Stack ui iere Pe n
14. 6 1 7 34 STOP Stop Operation STOP Operation The STOP instruction stops both the CPU clock and system clock and causes the microcontroller to enter the Stop mode During Stop mode the contents of on chip CPU registers peripheral registers and port control and data registers are retained Stop mode can be released by an external reset operation or external interrupt input For the reset operation the RESET pin must be held to Low level until the required oscillation stabilization interval has elapsed Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 7F Example The statement LD STOPCON 0A5H STOP NOP NOP NOP Halts all microcontroller operations When STOPCON register does not have 0A5H value and you use STOP instruction PC is changed to reset address SAMSUNG ELECTRONICS 6 47 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 35 SUB Subtract SUB dst src Operation dst lt dst src The source operand is subtracted from destination operand and the result is stored in destination The contents of the source remain unaffected Subtraction is performed by adding the two s complement of the source operand to the destination operand Flags C Set if a borrow occurred cleared otherwise 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if
15. FMSECH 4 High Address of Sector FMSECL lt Low Address of Sector Set Sector Base Address FMCON lt 10100001B Mode Select amp Start Erase FMUSR 00H User Prgramming Mode Disable Finish One Sector Erase Figure 13 6 Sector Erase Flowchart in User Program Mode NOTE 1 If you erase a sector selected by Flash Memory Sector Address Registers FMSECH and FMSECL FMUSR should be enabled just before starting the sector erase operation To erase a sector Flash Operation Start Bit of FMCON register is written from operation stop 0 to operation start 1 This bit will be cleared automatically just after the corresponding operation is completed In other words when S3F94C8 F94C4 is in a condition where flash memory user programming enable bits are enabled and start operation of sector erase is executed it will get the result of erasing selected sector as user s purpose The Flash Operation Start Bit of FMCON register is also clear automatically 2 f you execute sector erase operation with FMUSR disabled then Flash Operation Start Bit FMCON O bit remains high which means start operation and is not cleared even though next instruction is executed Therefore you should be careful to set FMUSR when executing sector erase for no effect on other flash sectors SAMSUNG ELECTRONICS 13 6 xu S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE Example 13 1 Programming Tip Sector Erase Case1
16. T MAIN lt lt Subroutines gt gt ED DISPLAY SAMSUNG ELECTRONICS 8 10 en S3F94C8 F94C4 UM REV 1 00 8 RESET AND POWER DOWN INT 94C4 EXT_CHK1 EXT_CHK2 EXT_CHK3 END_INT lt lt Interrupt Service Routines gt gt Interrupt enable bit and pending bit check OCON 00000010B TimerO interrupt enable check NEXT CHK1 OCON 00000001B timerO interrupt occurs NZ INT_ ERO TOCON O bit will be set Check PWM overflow interrupt enable Check INTO interrupt enable 01000B Check INT1 interrupt enable 00100B T ET Interrupt return IRET INT TIM lt TimerO interrupt service routine gt TOCON 11110110B Clear Pending bit Interrupt return PWMOVF INT PWM overflow interrupt service routine 11110110B Clear Pending bit Interrupt return INTO INT External interruptO service routine gt POPND 11111110B Clear INTO Pending bit interrupt return SAMSUNG ELECTRONICS ae er S3F94C8 F94C4 UM REV 1 00 8 RESET AND POWER DOWN F External interruptl service routine gt INT1 INT POPND 11111011B Clear INT1 Pending bit Interrupt return SAMSUNG ELECTRONICS 8 12 xu S3F94C8 F94C4_UM_REV 1 00 9 PORTS I O PORTS 9 1 Overview of I O Port
17. 4 3 2 el 0 ise Reset 00H Base 2 for 14 bit PWM PWMDATA F2H Reset 00H PWMEX F1H Reset 00H Ext 1 for 12 14 bit PWM Base Control PWMEX 1 0 base ext control 0 8 bitresolution Base 0 PWMDATA 7 2 Ext 0 PWMDATA 1 0 01 12 bit resolution Base 1 PWMDATA 1 5 0 Ext 1 PWMEX 7 2 11 14 bit resolution Base 2 PWMDATA 1 7 0 Ext 1 PWMEX 7 2 Reset Value 00 8 bit resolution selected Figure 11 1 PWM Data and Extension Registers To program the required PWM output load the appropriate initialization values into the data registers PWMDATA and the extension registers PWMEX To start the PWM counter or to resume the counting set PWMCON 2 to 1 A reset operation disables all PWM output The current counter value is retained when the counter stops When the counter starts counting resumes at the retained value SAMSUNG ELECTRONICS 11 2 er S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION 11 1 1 4 PWM Clock Rate The timing characteristic of PWM output is based on the fOSC clock frequency The PWM counter clock value is determined by setting PWMCON 6 7 Table 11 1 PWM Control and Data Registers Register Name Mnemonic Address Funcion PWMDATA PWM data registers PWMDATA1 PWM waveform output setting registers PWMEX PWM counter stop start resume and PWM control registers PWMCON OSC clock setting 11 1 1 5
18. 4 1 14 P2CONL Port 2 Control Register Low Byte EBH Bitdenifier 7 6 5 4 3 2 a o o o o o 9 9 9 7 6 Part 2 P2 3 Configuration Bits Lo Schmit vggerinputipulperabie SSS of i sermittiggerinput 5 4 Port 2 P2 2 Configuration Bits oo Schmit wooer input purap erae KN esmo o 3 2 Port 2 P2 1 Configuration Bits Co Shmi ager nout paupera Fo 1 Pio Pushputoupst 1 0 Port 2 P2 0 Configuration Bits Schmitt trigger input pull up enable Schmitt trigger input SAMSUNG ELECTRONICS 4 16 ex S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 15 PWMCON PWM Control Register F3H Bitidentitier 7 6 5 4 3 2 a o RESETVaue o o o o o o o nw aw aw aw aw aw RW NOTE PWM Input Clock Selection Bits o o osm 1 fOSC 1 Not used for S3F94C8 F94C4 P z MDATA Reload Interval Selection Bit Reloads from extension up counter overflow 1 Reloads from base up counter overflow PWM Counter Clear Bit No effect 1 Clears the PWM counter when write PWM Counter Enable Bit Stops counter 1 Starts Resumes countering PWM Overflow Interrupt Enable Bit 8 Bit Overflow Disables int
19. 6 36 6 1 7 24 PUSH Push St ck tate reati 6 37 6 1 7 25 Reset Carry 0 nnns nnne tenen 6 38 6 1 7 20 RET Re tumn un ndn 6 39 6 1 7 27 Roiate Left speed 6 40 6 1 7 28 Rotate Left Through Carry 6 41 6 1 7 29 RR Rotate Right 6 42 6 1 7 30 RRC Rotate Right Through Carry sse enne nnne 6 43 6 1 7 31 SBC Subtract With Carry icies 6 44 6 1 7 32 5 Set Carry Flag i ane ans 6 45 6 1 7 33 SRA Shift Right Arithmetic nennen nnne 6 46 6 1 7 34 STOP Stop Operation sunni titt etes Pkt 6 47 61 735 SUB 506 iri Erin or ter pastes eiue E 6 48 6 1 7 36 TCM Test Complement Under Mask sse 6 49 6 1 7 37 TM Test Under seen entren entente nnns nnne en 6 50 6 1 7 38 XOR Logical Exclusive 6 51 7 CLOCK GIRCUIT e 7 1 7 1 Overiew of Clock CiICult baa vet 7 1 Tatt Main Oscillator Ko 7 2 7 1 2 Clock Status During Power Down Modes sse 7 2 7 1 3 System Clock Contr
20. 9 Figure 17 5 S3F94C8 F94C4 Probe Adapter for 20 DIP Package SAMSUNG ELECTRONICS 17 8 er S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS 17 1 6 Third parties for Development Tools Samsung provides complete line of development tools for its microcontrollers The in circuit emulator solution from Samsung covers wide range of capabilities and prices from low cost ICE to complete system with an OTP MTP programmer 17 1 6 1 In Circuit Emulator for SAM8 family e OPENice i500 2000 SmartKit SK 1200 17 1 6 2 OTP MTP Programmer e SPW uni e GW uni 8 gang programmer AS pro 17 1 6 3 Development Tools Suppliers Contact our local sales offices or third party tool suppliers directly for getting these development tools SAMSUNG ELECTRONICS 17 9 er S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS 17 1 6 4 8 bit In Circuit Emulator OPENice 1500 System Telephone 82 31 223 6611 Fax 82 331 223 6613 E mail openice aijisystem com stroh yicsystem com URL http www aijisystem com OPENice i2000 AlJI System Telephone 82 31 223 6611 Fax 82 331 223 6613 E mail openice aijisystem com stroh yicsystem com URL http www aijisystem com SK 1200 Seminix Telephone 82 2 539 7891 Fax 82 2 539 7819 E mail sales seminix com URL http www seminix com SAMSUNG ELECTRONICS 17 10 S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS OTP MTP P
21. A 16 bit address bus supports program memory operations On the other hand a separate 8 bit register bus carries addresses and data between the CPU and internal register file S3F94C8 F94C4 microcontroller has 8Kbytes and 4Kbytes of multi time programmable full flash program memory that is configured in the Internal ROM mode The chip uses all of the 4K 8K internal program memory Also the S3F94C8 F94C4 microcontroller has 208 general purpose registers in its internal register file 32 bytes in the register file are mapped for system and peripheral control functions SAMSUNG ELECTRONICS 2 1 er S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES 2 2 Program Memory ROM 2 2 1 Normal Operating Mode S3F94C8 F94C4 has 8Kbytes and 4Kbytes of internal multi time programmable full flash program memory The program memory address range lies between 0H 1FFFH and OH OFFFH The first 2 bytes of the ROM 0000H 0001H specify the interrupt vector address Unused locations 0002H 00FFH except 3CH be used as normal program memory 3CH 3EH and SFH are used as smart option ROM cell The Program Reset address in ROM is 0100H Decimal HEX 8 191 1FFFH S3F94C8 8 Kbyte Program Memory Flash OFFFH S3F94C4 Program Memory Flash Figure 2 1 Program Memory Address Space SAMSUNG ELECTRONICS 2 2 er S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES 2 2 2 Smart Option Smart option
22. Caution Be careful while designing the related circuits of signal pins The rising falling timing of VPP SCLK and SDAT is important for proper programming er se SCLK I O AW gt To Application circuit SDAT I O MW gt To Application circuit Vpp nRESET gt To Application circuit Creset DD V CVpp are used to improve zi the noise effect SPW uni GW uni AS pro US pro Figure 16 3 PCB design guide for on board programming SAMSUNG ELECTRONICS 16 4 xu S3F94C8 F94C4_UM_REV 1 00 16 S3F94C8 F94C4 FLASH Table 16 3 Reference Table for Connection mode Resistor Vpp nRESET Input Yes CVpp varies from 0 01uF 0 02uF Se RSDAT varies from 2 Kohm 5 Kohm SDAT I O om mm LS est RSCLK varies from 2 Kohm 5 Kohm SCLK I O om m 1 In on board writing mode high speed signal will be provided to SCLK and SDAT pins If the application circuit is designed for handling high speed response such as relay control circuit high speed signals may cause damage to the application circuits connected to or SDAT port If possible the I O configuration of SDAT and pins must be set to input mode 2 The value of and C in this table specifies the recommended value It varies with the circuit of system SAMSUNG ELECTRONICS 16 5 im S3F94C8 F94C4_UM_REV 1 00 16 S3F94C8 F94C
23. Erase one sector E ON LD LD LD LD LD ECTOR FMUSR 0 5 FMSECH 04H FMSECL 00H FMCON 10100001B FMUSR 00H SAMSUNG ELECTRONICS Enable User program mode Set sector address 0400H sector 8 among sector 0 32 Select erase mod nable and Start sector erase Disable User program mode 13 7 ex S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 4 Programming A flash memory is programmed in one byte unit after sector erase The write operation of programming starts by LDC instruction 13 4 1 Program Procedure in User Program Mode 1 2 Erase target sectors before programming Set Flash Memory User Programming Enable Register FMUSR to 10100101B Set Flash Memory Control Register FMCON to 0101000 To write data set Flash Memory Sector Address Register FMSECH and FMSECL to the sector base address of destination address Load transmission data into a working register Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Load transmission data to flash memory location area on LDC instruction by indirectly addressing mode Set Flash Memory User Programming Enable Register FMUSR to 00000000B NOTE In programming mode it does not matter whether FMCON 0 s value is 0 or 1 SAMSUNG ELECTRO
24. Location DAH Is Not Mapped Port 0 Data Register Po Locations E3H E5H Are Not Mapped Port 0 Control Register High POCONH Byte Port 0 Control Register POCON Port 0 Interrupt Pending POPND E8H Register Port 1 Control Register P1CON Port 2 Control Register High D9H Port 2 Control Register Low P2CONL Byte Flash Memory Control Register FMCON SAMSUNG ELECTRONICS 8 7 R W R W R W R W R W R W R W R W R W R W Lo ojo o o 1 9 1 00 ESESESESERESESES S3F94C8 F94C4_UM_REV 1 00 8 RESET AND POWER DOWN Fealster N Address and Location SET mw 7 1 6 Flash Memory User FMUSR EDH R W Programming Enable Register Flash Memory B Address EUER eros EN ow spe p ros one Flash Memory Ser Address FMSECL R W Register Low Byte PWM Data Register 1 PWMDATA1 RW PWM Extension Register PWMEX RW PWM Data Register PWMDATA PWM Control Register PWMCON STOP Control Register STOPCON Locations F5H F6H Are Not Mapped A D Control Register ADCON High japon 00090068 Locations FAH FFH Are Not Mapped NOTE Not mapped or not used x undefined SAMSUNG ELECTRONICS 8 8 im S3F94C8 F94C4_UM_REV 1 00 Example 8 1 ORG 003CH 00H 003CH must be initialized to 0 OO3DH must be initialized to 0 OE7H enable L
25. Register 00H then contains the value 55H and SP points to location OBCH SAMSUNG ELECTRONICS 6 36 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 24 PUSH Push To Stack PUSH src Operation SP lt SP 1 OSP lt src A PUSH instruction decrements the stack pointer value and loads the contents of source src into the location addressed by decremented stack pointer The operation then adds the new value to the top of the stack Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc src 2 8 70 R 8 71 IR Examples Given Register 40H 4FH register 4FH OAAH SP OCOH PUSH 40H gt Register 40H 4FH stack register 4FH SP OBFH PUSH 40H gt Register 40H 4FH register 4FH QAAH stack register OAAH SP In the first example if the stack pointer contains the value OCOH and general register 40H contains the value 4FH the statement PUSH 40H decrements the stack pointer from to It then loads the contents of register 40H into location OBFH Register OBFH then contains the value 4FH and SP points to location OBFH SAMSUNG ELECTRONICS 6 37 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 25 RCF Reset Carry Flag RCF RCF Operation Ce 0 The carry flag is cleared to logic zero regardless of its previous value Flags C Cleared to 0 No other flags are affected Format Bytes Cycles O
26. Register High Byte FMSECH indicates the high byte of sector address FMSECH is needed for S3F94C8 F94C4 since it has 64 32 sectors One sector consists of 128 bytes Each sector s address starts with XXOOH or XX80H that is a base address of sector is XXOOH or XX80H Therefore bit 6 0 of FMSECL does not mean that the value is 1 or 0 The simplest way is to load the sector base address into FMSECH and FMSECL register When programming the flash memory user should program after loading a sector base address which is located in the destination address to write data into FMSECH and FMSECL register If the next operation is also to write one byte data user should check whether next destination address is located in the same sector or not In case of other sectors load the sector address to FMSECH and FMSECL registers according to the sector Refer to Pages 13 11 Programming Programming for more information Flash Memory Sector Address Register FMSECH Flash Memory Sector Address High Byte NOTE High Byte flash memory sector address pointer value is the higher eight bits of the 16 bit pointer address Figure 13 3 Flash Memory Sector Address Register FMSECH Flash Memory Sector Address Register FMSECL EFH R W Don t Care Flash Memory Sector Address Low Byte NOTE The Low Byte flash memory sector address pointer value is the lower eight bits of the 16 bit pointer address Fi
27. This selects one of the nine analog input pins ADCn n 0 8 and sets the conversion start or enable bit The read write ADCON register is located at address F7H During a normal conversion ADC logic sets the successive approximation register to 200H approximate half way point of a 10 bit register This register is then updated automatically during each conversion step The successive approximation block performs 10 bit conversions for one input channel at a time You can dynamically select different channels by manipulating the channel selection bit value ADCON 7 4 in the ADCON register To start A D conversion set the enable bit ADCON 0 When a conversion is completed the end of conversion EOC bit ACON 3 is automatically set to 1 and the result is dumped into the ADDATA register where it can be read The A D converter then enters into an idle state Remember to read the contents of ADDATA before another conversion starts Otherwise the previous result will be overwritten by next conversion result NOTE Since the ADC does not use sample and hold circuitry it is important that any fluctuations in the analog level at ADCO ADCS input pins during a conversion procedure be kept to an absolute minimum Any change in the input level perhaps due to circuit noise will invalidate the result SAMSUNG ELECTRONICS 12 1 xu S3F94C8 F94C4 UM REV 1 00 12 A D CONVERTER 12 1 1 Using A D Pins for Standard Digital Input Th
28. 0061 0103H 4FH 0104H 1A 0105H 6DH and 1104H 88H External data memory locations 0061H BBH 0103H 5FH 0104H 2AH 0105H 7DH and 1104H 98H LDC RO RR2 RR2 RO 01H RR4 01H RR4 01H RR4 RO 01H RR4 RO RO 1000H RR2 RO 1000H RR2 SAMSUNG ELECTRONICS lt contents of program memory location 0104H RO R2 01H R3 04H RO lt contents of external data memory location 0104H RO 2AH R2 01H R3 04H 11H contents of RO is loaded into program memory location 0104H RR2 working registers RO R2 R3 no change 11H contents of RO is loaded into external data memory location 0104H RR2 working registers RO R2 R3 no change RO lt contents of program memory location 0061H 01H RR4 AAH R2 R3 60H RO lt contents of external data memory location 0061H 01H RR4 RO BBH R4 00H R5 60H 11H contents of RO is loaded into program memory location 0061H 01H 0060H 11H contents of RO is loaded into external data memory location 0061H 01H 0060H lt contents of program memory location 1104H 1000H 0104H RO 88H R2 01H R3 04H RO lt contents of external data memory location 1104H 1000H 0104H RO 98H R2 01H R3 04H 6 30 IP S3F94C8 F94C4 UM REV 1 00 1105H RO RO 1104H RO 1104H 1105H RO
29. 127 7FH and result is 128 80H cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst dst opc 1 4 rE r r 0 to dst 2 4 20 R 4 21 IR Examples Given RO 1BH register OOH OCH and register 1BH OFH INC RO gt RO 1CH INC 00H Register 00H INC GRO gt 1BH register 01H 10H In the first example if destination working register RO contains the value 1BH the statement INC RO leaves 1CH value in the same register The next example shows the effect of an INC instruction on register OOH The assumption is INC contains the value OCH In the third example INC is used in Indirect Register IR addressing mode to increment the value of register 1BH from OFH to 10H SAMSUNG ELECTRONICS 6 23 er S3F94C8 F94C4_UM_REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 14 IRET Interrupt Return IRET IRET Operation FLAGS SP SP SP 1 5 SP lt SP 2 SYM 2 lt 1 This instruction is used the end of an interrupt service routine It restores the flag register and program counter It also re enables the global interrupts Flags All flags are restored to their original settings that is the settings before the interrupt occurred Format IRET Bytes Cycles Opcode Normal Hex ope 1 10 BF 12 SAMSUNG ELECTRONICS 6 24 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 15 JP Jump JP cc dst Conditional JP dst Unconditional Operat
30. 13 2 3 Flash Memory Sector Address Registers 13 4 13 3 Sector 8 enk dag ak 13 5 13 3 1 The Sector Erase Procedure User Program 13 6 13 4 Programming 13 8 13 4 1 Program Procedure in User Program Mode sse enne 13 8 13 5 Reading annaia 13 14 13 5 1 Program Procedure in User Program 13 14 13 6 H rd Lock Protection a 13 15 13 6 1 Program Procedure in User Program Mode sse 13 15 TAELECTHICAE DATA keen 14 1 14 1 Overview of Electrical Data t eee 14 1 SAMSUNG ELECTRONICS en 15 15 1 15 1 Overview of Mechanical Data 15 1 16 SJF94G8 FY94C4 FLASH 16 1 16 1 Overview of Flash MCU 16 1 16 2 On Board Wing 16 4 16 2 1 Circuit Design 16 4 16 3 Information BIOGK m 16 6 17 DEVELOPMENT TOOLS 17 1 17 1 Overview of Deve
31. 2009 e Package delete 16SSOP not available in e Some Package Samsung types not available e Package change 16SOP BD300 SG to 16SOP any more 225 16SOP BD300 not available in Samsung e Package add 16 TSSOP BD44 Mar 11 2009 ADC maximum clock 4MHz e According to e ADC conversion time Minimum 12 5us LF13H ADC test ADC operating voltage range 2 0V 5 5V result V0 4 13 2009 Product S3F94C4 gt S3F94C8 F94C4 e Add C8 related contents e CPU core type SAM8RCRI gt SAM88RCRI VPP description change voltage for tool mode entering e Smart option add 1 9V level 10100 e Address Space C8 8K 16TSSOP Package type confirmed 16TSSOP 0044 15 2009 e Change description internal RC VDD 5V TA Emphasis the 25 C Tolerance 1 precision of 1 Apr 17 2009 LVR level 2 3V e Error correction Change error Min 2 0 Typ 2 3 Max 2 6 V0 5 Mar 25 e IDD3 change Typical vale 25C 4 5V 5 5V e According 2009 change from 1 0uA to 0 3uA S3F80PB test e PWM Spec result and PE s Add figure for PWMEX and PWM data register suggestion description e According 9454 Change PWM block diagram according to real real circuit and test circuit PWM extension bit no buffer so delete it result in the diagram e For describe the PWM module more clearly V0 6 Jul 30 2009 Add description about Information Block in e New feature has Chap 16 been verified e Chap 17 modified according to new Tar
32. 3 xu S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION 11 1 1 6 PWM Output Waveform e 6 bit base 2 bit extension mode Table 11 2 PWM output stretch Values for Extension Data bits Ext0 PWMDATA 1 0 PWMDATA Bit Bit1 Bit0 Stretched Cycle Number 000000xxB PWM 000001 xxB Data Register Values PWMDATA 100000xxB 111111xxB Figure 11 2 PWM Basic Waveform 6 bit base SAMSUNG ELECTRONICS 11 4 S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION PWM Clock 4 MHz 000010xxB PWMDATA 0000 1001B Basic Extended waveform waveform ist 2nd 3th 4th 1st 2nd 3th 4th cic OH Figure 11 3 Extended PWM Waveform 6 bit base 2 bit extension SAMSUNG ELECTRONICS 11 5 er S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION 6 bit base 6 bit extension mode Table 11 3 PWM output stretch Values for Extension Data bits PWMEX 7 2 1 3 5 7 9 55 57 59 61 63 0H PWM Clock 4 MHz 0H PWMDATA 1 Register 1H Values Figure 11 4 PWM Basic Waveform 6 bit base SAMSUNG ELECTRONICS 11 6 er S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION PWM Clock PWMDATA 1 Register Values 02H PWMEX 64th Register Values 000100 01B Extended Value is 04H 750ns Figure 11 5 Ex
33. 3 20 SSOP 225 Package Dimensions SAMSUNG ELECTRONICS 15 3 S3F94C8 F94C4 UM REV 1 00 16 SOP 225 S HHHHHHHH SAMSUNG ELECTRONICS 0 50 0 35 NOTE Dimensions are in millimeters Figure 15 4 16 SOP 225 Package Dimensions 15 4 15 MECHANICAL DATA S3F94C8 F94C4 UM REV 1 00 15 MECHANICAL DATA lt o CI p 10 MAX gt 0 65BSC NOTE Dimensions are in millimeters Figure 15 5 16 TSSOP 0044 Package Dimensions SAMSUNG ELECTRONICS 15 5 im S3F94C8 F94C4_UM_REV 1 00 16 S3F94C8 F94C4 FLASH MCU S3F94C8 F94C4 FLASH MCU 16 1 Overview of Flash MCU S3F94C8 F94C4 single chip CMOS microcontroller is a Flash microcontroller unit MCU with on chip ROM of 8K 4K bytes The Flash ROM is accessed by serial data format This serial data is transformed by two pins of the chip namely SCLK and SDAT The SCLK pin specifies the synchronize signal On the other hand the SDAT pin facilitates data transfer using Flash Programmer Tool The corresponding ports of SCLK and SDAT in S3F94C8 F94C4 are P0 0 and P1 1 respectively To enter the Flash Tool mode and to operate the chip high power supply is required Therefore the VDD and VSS of chip must be connected to power and ground respectively The VPP port is reserved for providing high power during Flash operation Its corresponding pin in SSF94C8 F94C4 is nRESET P1 2 pin Table 16 1 shows the detailed description of the p
34. 6 SAM88RCRI INSTRUCTION SET lt contents of program memory location 1104H RO 88H lt contents of external data memory location 1104H RO 98H 11H contents of RO is loaded into program memory location 1105H 1105H lt 11H 11H contents of RO is loaded into external data memory location 1105H 1105H lt 11H NOTE These instructions are not supported by masked ROM type devices SAMSUNG ELECTRONICS 6 31 IP S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 19 LDCD LDED Load Memory and Decrement LDCD LDED dst src Operation dst src rr lt rr 1 These instructions are used for user stacks or block transfers of data from program or data memory to the register file A working register pair specifies the address of the memory location The contents of the source location are loaded into the destination location The memory address is then decremented The contents of source remain unaffected LDCD and LDED reference program memory and external data memory respectively The assembler changes to an even number for program memory and to odd number for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src Examples Given R6 10H R7 33H R8 12H program memory location 1033H OCDH and external data memory location 1033H ODDH LDCD R8 RR6 OCDH contents of program memory location 1033H is loaded
35. AND POWER DOWN 8 1 1 1 External Reset Pin When the nRESET pin transits from VIL low input level of reset pin to VIH high input level of reset pin the reset pulse is generated nRESET S3F94C8 F94C4 NOTES 1 lt 100 Kohm is recommended to make sure that the voltage drop across does not violate the detection of reset pulse Figure 8 2 Recommended External RESET Circuit SAMSUNG ELECTRONICS 83 im S3F94C8 F94C4 UM REV 1 00 8 RESET AND POWER DOWN 8 1 1 2 MCU Initialization Sequence The following sequence of events occurs during Reset operation e All interrupts are disabled e The watchdog function basic timer is enabled e Ports 0 2 are set to input mode e Peripheral control and data registers are disabled and reset to their initial values See Table 8 1 for more information e The program counter is loaded with ROM reset address 0100H e When the programmed oscillation stabilization time interval elapses the address stored in ROM location 0100H and 0101H is fetched and executed Smart Option 7 nRESET Internal nRESET LVR nRESET Watchdog nRESET Figure 8 3 Reset Block Diagram Oscillation Stabilization Wait Time 52 4ms at 10MHz nRESET Input Normal Mode or ELS pe NE Mode Operation Mode Power Down Mode RESET Operation Figure 8 4 Timing for S3F94C8 F94C4 After RESET SAMSUNG ELECTRONICS 8 4 er S3F94C8 F94C4_UM_REV 1 00 8 RESET AND POWER DOWN
36. D converter input ADCO Schmitt trigger input off SAMSUNG ELECTRONICS 4 12 en S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 11 POPND Port 0 Interrupt Pending Register E8H Bit Identifier Les oe E TE adr od mew 9 9 ww aw aw RW SAMSUNG ELECTRONICS Not used for the S3F94C8 F94C4 Port 0 1 ADC1 INT1 Interrupt Enable Bit 0 Disables falling edge interrupt Enables INT1 falling edge interrupt Port 0 1 ADC1 INT1 Interrupt Pending Bit No interrupt pending when read Clears pending bit when write Interrupt is pending when read No effect when write Port 0 0 ADCO INTO Interrupt Enable Bit 0 Disables INTO falling edge interrupt Enables INTO falling edge interrupt Port 0 0 ADCO INTO Interrupt Pending Bit No interrupt pending when read Clears pending bit when write Interrupt pending when read No effect when write 4 13 im S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 12 P1CON Port 1 Control Register E9H a Preserve o o 9 9 Paw aw 7 Part 1 1 N channel open drain Enable Bit Configures P1 1 as a push pull output 1 Configures P1 1 as an n channel open drain output 6 Port 1 0 N channel open drain Enable Bit Configures P1 0 as a push pull output Configures P1 0 as an n channel
37. IR1 IM Ir1 r2 E RR RR LDCD LDCI LD LD LD LDC R1 IR1 r1 lrr2 ri Irr2 R2 R1 R2 IR1 R1 IM r1 Irr2 xs F CALL LD CALL LDC IRR1 IR2 R1 DA1 Irr1 xs SAMSUNG ELECTRONICS 6 7 xu S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET Table 6 6 Opcode Quick Reference 1 SAMSUNG ELECTRONICS 6 8 im S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 6 Condition Codes The opcode of a conditional jump always contains a 4 bit field called the condition code cc This field specifies the conditions under which it has to execute the jump For example a conditional jump with the condition code for equal after a compare operation only jumps if the two operands are equal Table 6 7 lists the condition codes The carry C zero Z sign S and overflow V flags are used to control the operation of conditional jump instructions Table 6 7 Condition Codes mnemonic O I NINJO 10 0 1 1 0 1 0 0 1 1 0 N lt ll ll Greaterthanorequal 6 XOR vizo 0011 Unsigned less than equal C OR Z 1 NOTE 1 Indicates the condition codes related to two different mnemonics that also test the same flag For example Z and EQ are both true if the zero flag Z is set but after an ADD instruction Z may be used after a CP instruction however EQ may be used 2 For operations involving unsigned numbers the special condition codes UGE ULT UGT and ULE mu
38. Memory sse 3 4 Indirect Working Register Addressing to Register File 3 5 Indirect Working Register Addressing to Program or Data Memory 3 6 Indexed Addressing to Register Fila eene nnns 3 7 Indexed Addressing to Program or Data Memory with Short Offset 3 8 Indexed Addressing to Program or Data Memory with Long 3 9 Direct Addressing for Load Instructions enne 3 10 Direct Addressing for Call and Jump Instructions sssssssseeeeneneenn 3 11 Relative Addressing E 3 12 Immediate 5 dens 3 12 Register Description eit 4 4 S3F9 Series Interrupt Type cett eet cR sn 5 1 Interrupt Function Diagram 5 2 S3F94C8 F94C4 Interrupt 11 enne 5 4 system Flags Register FLAGS sss titi 6 4 Main Oscillator Circuit RC Oscillator with Internal Capacitor 7 1 Main Oscillator Circuit Crystal Ceramic 7 1 System Clock Control Register
39. P1 1 lg 25 0 2 1 0 1 1 All input pins Vin Vpp except li i4 p1 2 Vpp 1 8 to 5 5V Vpp 4 5 to 5 5V All input pins Vn 0V except I 2 All output pins Ports 0 2 and P1 0 P1 1 Vin 0 V P1 0 P1 12 Run mode Vpp 4 5 to 5 5V 10 MHz CPU clock 3MHz CPU clock Vpp 2 0V Idle mode Vpp 4 5 to 5 5V 10 MHz CPU clock 3MHz CPU clock Vpp 2 0V 14 3 14 MECHANICAL DATA E E 3 2 d S3F94C8 F94C4 UM REV 1 00 14 MECHANICAL DATA Symbol Conditions Stop mode Vpp 4 5 to 5 5V LVR disable Ty 25 Vpp 4 5 to 5 5V LVR disable Ta 40 to 85 C Vpp 4 5 to 5 5V LVR enable 25 Vpp 2 6 V LVR enable 25 1 Supply current does not include the current drawn through internal pull up resistors or external output current loads and ADC module 2 P1 2 has intrinsic internal pull down resistor Internal VPP circuit whose typical value is about 300Kohm Table 14 3 AC Electrical Characteristics TA 40 C to 85 C VDD 1 8 V to 5 5 V Symbol Conditions Min Max Unit Interrupt input high tINTH INTO INT1 200 ns low width t 2 5V 10 INTL RESET input low width tns Input 1 us Vpp 5V 3 10 96 Figure 14 1 Input Timing Measurement Points SAMSUNG ELECTRONICS 14 4 er S3F94C8 F94C4 UM REV 1 00 14 MECHANICAL DATA Table 14 4 Oscil
40. PWM Function Description The PWM output signal toggles to Low level whenever the lower base counter matches the reference value stored in the module s data register PWMDATA If the value in the PWMDATA register is not zero an overflow of the lower counter causes the PWM output to toggle to High level In this way the reference value written to the data register determines the module s base duty cycle The value in the extension counter is compared to the extension settings in the extension data bits This extension counter value together with extension logic and the PWM module s extension bits is then used to stretch the duty cycle of the PWM output The stretch value is one extra clock period at specific intervals or cycles see Table 11 2 for more information For example if the value in the extension register is 04H in 8 bit base 6 bit extension mode the 32 cycle will be one pulse longer than the other 63 cycles If the base duty cycle is 50 the duty of the 32nd cycle will therefore be stretched to approximately 51 duty If you write 80H to the extension register all odd numbered cycles will be one pulse longer If you write to the extension register all cycles will be stretched by one pulse except the 64 cycle PWM output goes to an output buffer and then to the corresponding PWM output pin In this way you can obtain high output resolution at high frequencies SAMSUNG ELECTRONICS 11
41. Parameter Symbol Conditions Electrostatic discharge SAMSUNG ELECTRONICS 14 10 er S3F94C8 F94C4 UM REV 1 00 15 MECHANICAL DATA MECHANICAL DATA 15 1 Overview of Mechanical Data S3F94C8 F94C4 is available in the following package 20 pin DIP package Samsung 20 DIP 300A 20 pin SOP package Samsung 20 SOP 375 20 pin SSOP package Samsung 20 SSOP 225 16 pin SOP package Samsung 16 SOP 225 16 pin TSSOP package Samsung 16 TSSOP 0044 Figure 15 1 Figure 15 2 Figure 15 3 Figure 15 4 and Figure 15 5 show the dimensions of each package 20 DIP 300A 80 lt 40 0 20 Ti LEN 0 46 0 10 5 08 MAX o el e 1 77 1 52 0 10 4 NOTE Dimensions are in millimeters Figure 15 1 20 DIP 300A Package Dimensions SAMSUNG ELECTRONICS 15 1 er S3F94C8 F94C4 UM REV 1 00 15 MECHANICAL DATA 10 30 0 30 7 50 0 20 0 85 0 20 13 14 12 74 0 20 2 30 0 10 2 50 0 10 MAX 1 27 NOTE Dimensions millimeters Figure 15 2 20 SOP 375 Package Dimensions SAMSUNG ELECTRONICS 15 2 S3F94C8 F94C4 UM REV 1 00 15 MECHANICAL DATA 20 SSOP 225 6 40 0 20 4 40 0 10 0 50 0 20 6 90 6 50 0 20 1 85 MAX s lt MAX 0 22 0 05 NOTE Dimensions are in millimeters Figure 15
42. Pin Descriptions cecceecceeseeeeeeeeeeeeeecaeecaaeceaeecaeecaaecaaecaaesaeseaeseaeeeeseaeeseeeeeneeses 1 6 Descriptions of Pins Used to Read Write the Flash ROM sese 1 7 Register Type Summary o recte 2 5 System and Peripheral Control 4 2 Interrupt Source Control and Data Registers enne enne 5 5 Instruction Group Summary usa 6 2 Flag Notation nennen 6 5 Instruction Set Symbols x ornat eee 6 5 Instruction Notation Conventions enne ennt nnn nnn nnn nnne 6 6 Opcode Quick Beference 6 7 Opcode Quick Reference 1 6 8 Gondition 6 9 Register Values after Reset urriei esitaiat taa 8 7 Overview of S3F94C8 F94C4 Port Configuration 9 1 Port Data Register Summary 9 2 PWM Control and Data nnns nnne 11 3 PWM output stretch Values for Extension Data bits ExtO PWMDATA 1 0 11 4 PWM output stretch Va
43. Register Addressing Mode 1 Program Memory Example Instruction References OPCODE oe Memory Sample Instructions CALL RR2 JP RR2 Point to register pair Value used in instruction Register File REGISTER Program Memory OPERAND 3 ADDRESSING MODES 16 bit address points to program memory Figure 3 4 Indirect Register Addressing to Program Memory SAMSUNG ELECTRONICS 3 4 S3F94C8 F94C4_UM_REV 1 00 3 1 4 Indirect Register Addressing Mode 2 Program Memory 4 Bit Now COo o Address OPCODE Sample Instruction OR R6 R2 3 ADDRESSING MODES Register File Point to the working register 1 of 16 Value used in instruction Figure 3 5 Indirect Working Register Addressing to Register File SAMSUNG ELECTRONICS S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES 3 1 5 Indirect Register Addressing Mode 3 Register File Register Address x Next 3 Bits Point OPCODE to working Example instruction 7 register pai references either 1 of 8 16 Bit program memory or ps address ata memory LSB Selects Program Memory points to or program Data Memory memory or data memory Value used in instruction OPERAND Sample Instructions LCD R5 RR6 Program memory access LDE R3 RR14 External data memory access LDE RR4 R8 External data memory access Figure 3 6 Indirect Working Register Addressing to P
44. TA 25 C Tolerance of Internal RC 5 0 V 40 to 85 C Vpp 2 0 to 5 5 V 40 to 85 C SAMSUNG ELECTRONICS 14 6 im S3F94C8 F94C4_UM_REV 1 00 14 MECHANICAL DATA CPU Clock 10 MHz 8 MHz 3 MH CNN NE 04 6 2 7 4 45 5 550 5 5 5 gt Supply Voltage V Figure 14 2 Operating Voltage Range Figure 14 3 Schmitt Trigger Input Characteristics Diagram Table 14 8 Data Retention Supply Voltage in Stop Mode Ta 40 C to 85 Vpp 1 8 V to 5 5 V Data retention supply Vpppn Stop mode voltage Data retention supply IpppR Stop mode Vpppg 2 0 V 1 uA current NOTE Supply current does not include current drawn through internal pull up resistors or external output current loads SAMSUNG ELECTRONICS 14 7 er S3F94C8 F94C4 UM REV 1 00 14 MECHANICAL DATA RESET Oscillator Stop Occurs Stabilization Mode Data Retention Mode gt V Normal Execution Of gt Operating Stop Instrction Mode NOTE twar is the same as 4096 x 128 x 1 5 Figure 14 4 Stop Mode Release Timing When Initiated by a RESET Table 14 9 A D Converter Electrical Characteristics TA 40 C to 85 Vpp 1 8 V to 5 5 V Vss 0 Resolution Total accuracy Integral linearity error CPU clock Differ
45. bit selection bits 0 No interrupt pending 00 fosc 64 0 Clear pending condition 01 fosc 8 when write 10 fosc 2 1 Interrupt is pending 11 fosc 1 PWM counter interrupt enable bit Not Used 0 Disable PWM OVF interrupt 1 Enable PWM OVF interrupt PWM counter enable bit 0 Stop counter 1 Start resume countering PWMDATA reload interval selection bit 0 Reload from extension up counter PWM counter clear bit overflow 0 No effect 1 Reload from base up counter 1 Clear the PWM counter When write overflow Note 1 PWMCON 3 is not auto cleared You must pay attention when clear pending bit refer to page 11 12 2 PWMCON 5 should always be set to 0 Figure 11 8 PWM Control Register PWMCON SAMSUNG ELECTRONICS 11 10 IP S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION 11 1 3 PWM Extension Register PWMEX The extension register for the PWM module PWMEX is located at register address F1H PWMEX is used for the purpose of resolution selection and extension bits of 6 6 and 8 6 resolution Bit settings in the PWMEX register control the following functions e PWM extension bits for 6 6 resolution and 8 6 resolution mode e PWM resolution selection A reset clears all PWMEX bits to logic zero and choose 6 2 resolution without extension PWM Extension Registers PWMEX F1H R W Reset 00H PWM Extension bits for 6 6 and 846 resolution PWM resolution selection bits x0 8
46. bit 6 2 12 bit 6 6 and 14 bit 8 6 The S3F94C8 F94C4 microcontroller is ideal for use in a wide range of electronic applications requiring simple timer counter PWM and ADC They are currently available in 20 DIP Package 20 16 pin SOP Package 20 SSOP Package and 16 TSSOP Package SAMSUNG ELECTRONICS 1 1 S3F94C8 F94C4_UM_REV 1 00 1 2 Features CPU SAM88RCRI CPU core Memory Internal multi time program Full Flash memory 8Kx8 bits program memory S3F94C8 4Kx8 bits program memory S3F94C4 Sector size 128 Bytes User programmable by LDC instruction Sector erase available Fast programming time External serial programming support Endurance 10 000 erase program cycles o 10 Years data retention e 208 byte general purpose register area o 0 0 0 0 Instruction Set e 41 instructions e Idle and Stop instructions added for power down modes Instruction Execution Time e 400 ns at 10 MHz fOSC minimum Interrupts e 1 interrupt levels and 4 interrupt sources 2 external interrupts and 2 internal interrupts General I O e Three I O ports Max 18 pins e Bit programmable ports 1 ch High speed PWM with Three Selectable Resolutions e 8 bit PWM 6 bit base 2 bit extension e 12 bit PWM 6 bit base 6 bit extension e 14 bit PWM 8 bit base 6 bit extension 1 OVERVIEW OF S3F94C8 94C4 Timer Counters e One 8 bit basic timer for watchdog function One 8 bit timer counter with t
47. bits and for shift and rotate operations the Z flag is set to 1 if the result is logic zero 6 1 4 4 Carry Flag FLAGS 7 C The C flag is set to 1 if the result from an arithmetic operation generates a carryout from or a borrow to the bit 7 position MSB After rotate and shift operations this flag contains the last value shifted out of the specified register Program instructions can set clear or complement the carry flag SAMSUNG ELECTRONICS 6 4 en S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 5 Instruction Set Notation Table 6 2 Flag Notation Conventions o fame o o s sm o a Table 6 3 Instruction Set Symbols Flags register D5H D 8 Bmaymmbersfik SAMSUNG ELECTRONICS 65 iUm S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET Table 6 4 Instruction Notation Conventions Notation Description Operand Range 0 15 Register or working register reg or RRp 0 254 even number only where p 0 2 14 Indirect working register only Rn 0 15 Indirect register or indirect working register QRn or reg reg 0 255 0 15 Indirect working register pair only RRp 0 2 14 Register pair or working register pair Indirect register pair or indirect working RRp or Qreg reg 0 254 even only where register pair p 0 2 14 In
48. carry from the most significant bit MSB of the result cleared otherwise 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 12 6 13 r Ir src dst 3 6 14 R R 6 15 R IR opc dst src 3 6 16 R IM Examples Given R1 10H R2 03H flag 1 register 01H 20H register 02H 03H and register 03H OAH ADC R1 R2 DC R1 R2 ADC 01H 02H Register 01H 24H register 02H 03H ADC 01H 02 Register 01H 2BH register 02H 03H ADC 01H 11H gt Register 01H 32H In the first example destination register R1 contains the value 10H the carry flag is set to 1 and the source working register R2 contains the value 03H The statement ADC R1 R2 adds 03H and the carry flag value 1 to the destination value 10H leaving 14H in register R1 14H R2 03H 1BH R2 03H E gt SAMSUNG ELECTRONICS 6 11 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 2 ADD Add ADD dst src Operation dst lt dst src The source operand is added to the destination operand and the sum is stored in the destination The contents of the source remain unaffected Two s complement addition is performed Flags C Set if there is a carr
49. converter PWM input PWM output or external interrupt input P1 0 P1 1 Bit programmable I O port for Schmitt trigger input E 2 Xin Xour push pull open drain output Pull up resistors or pull down resistors are assigned by software gu 051 Schmitt trigger input port RESET 2 0 2 6 I O Bit programmable port for Schmitt trigger input or E push pull open drain output Pull up resistors are ADC8 CLO assignable by software TO or RC oscillator signal for system mn P1 0 P1 1 clock nRESET Internal LVR or external RESET B INTO INT 1 ET External interrupt input port PO0 0 PO 1 ADCO ADC8 A D converter input E 1 P0 0 P0 7 E P2 6 NOTE P1 2 is also used as VPP pin for flash programming It has an intrinsic internal pull down resistor whose value is about 300Kohm SAMSUNG ELECTRONICS 1 6 er S3F94C8 F94C4_UM_REV 1 00 1 OVERVIEW OF S3F94C8 94C4 Table 1 2 Descriptions of Pins Used to Read Write the Flash ROM Main Chip During Programming PO 1 SDAT Serial data pin output when reading input when writing Input and push pull output port can be assigned 200 19 20 15 16 pin Serial clock pin input only pin RESET P1 2 VPP 4 Power supply pin for entering in the Tool mode It specifies that MTP has entered in the Tool mode When 11 V is applied MTP enters in the Tool mode Vpp Vss Vpp Vss 20 20 pin 16 16 pin Logic power supply pin 1 20
50. direct drive P1 0 and P1 1 are used for oscillator input output by smart option On the other hand P1 2 is used for RESET pin by smart option LVR disable NOTE When P1 2 is configured as a general I O port it can be used only for Schmitt trigger input P1 2 is also shared with VPP pin for Flash Programming so it have intrinsic internal pull down resistor about 300Kohm Consider the pull down resistor when it used as port One control register is used to control port 1 P1CON E9H You can address port 1 bit directly by writing or reading the port 1 data register P1 E1H When you use external oscillator P1 0 and P1 1 must be set to output port to prevent current consumption Pull Up Register 50 typical Pull up Enable Open Drain Smart option P1 Data Output Disable is input mode Input Data Circuit type A Xn or RESET Pull Down Enable Pull Down Register 50 typical Input Data NOTE pins have protection diodes 0 through and Vss Figure 9 6 Port 1 Circuit Diagram SAMSUNG ELECTRONICS 9 7 er S3F94C8 F94C4_UM_REV 1 00 9 PORTS Port 1 Control Register E9H R W 7 Port 1 1 N Channel Open Drain Enable Bit 0 Configure P 1 1 as a push pull output 1 Configure P 1 1 as a n channel open drain output 6 Port 1 0 N Channel Open Drain Enable Bit 0 Configure P 1 0 as a push pull output 1 Configure P 1 0 as a N channel open drain outp
51. flag Z CONV LOOP2 R2 ADDATAH R3 ADDATAL INT TIMI Pending bit clear SAMSUNG ELECTRONICS 12 7 er S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE EMBEDDED FLASH MEMORY INTERFACE 13 1 Overview of Embedded Flash Memory Interface S3F94C8 F94C4 contains an internal on chip flash memory instead of masked ROM that can be accessed by the LDC instruction This flash memory is sector erasable and byte programmable You can program the data in a flash memory area any time you want The embedded 8K 4K byte memory in S3F94C8 F94C4 has two operating features namely Tool Program Mode For more information refer to Chapter 16 S3F94C8 F94C4 Flash MCU e User Program Mode 13 1 1 Flash ROM Configuration The SSF94C8 F94CA flash memory consists of 64 sectors S3F94C8 or 32 sectors S3F94C4 Each sector consists of 128bytes Therefore the total size of flash memory is 64 x 128 8KB or 32 x 128 bytes 4KB You can erase the flash memory by a sector unit at a time and write the data into flash memory by a byte unit at a time e 8K AKbyte Internal flash memory e Sector size 128bytes e 10years data retention e Fast programming Time Sector Erase 8ms minimum Byte Program 25us minimum e Byte programmable e User programmable by LDC instruction e Sector 128 Bytes erase available e Endurance 10 000 Erase Program cycles min SAMSUNG ELECTRONICS 13 1 er S3F94C
52. input characteristics Data retention supply voltage in Stop mode Stop mode release timing when initiated by a RESET A D converter electrical characteristics LVR circuit characteristics LVR reset timing Full Flash Memory Characteristics ESD Characteristics 14 1 S3F94C8 F94C4 UM REV 1 00 14 MECHANICAL DATA Table 14 1 Absolute Maximum Ratings TA 25 C Parameter Symbol Conditions Um Input voltage Output voltage All output ports 0 3 to Vpp 0 3 lou mA Output current high AWOpmsaeadwe mm 89 Output current low SAMSUNG ELECTRONICS 14 2 er S3F94C8 F94C4 UM REV 1 00 TA 40 to 85 VDD Parameter Symbol Operating voltage Main crystal or ceramic fain frequency Input high voltage Vind Vine Input low voltage Vito Output high voltage Output low voltage Input high leakage current lukt Input low leakage current Output high leakage current Output low leakage current Pull up resistors lin live lt lt Rp1 Pull down resistors Rp2 Supply current 1 Ipp1 Ipp2 SAMSUNG ELECTRONICS Table 14 2 1 8 V to 5 5 V fmain 0 4 4 MHz fmain 0 4 10 MHz Vpp 2 7 V to 5 5V 1 8 V to 2 7V DC Electrical Characteristics Ports 0 1 2 and RESET Xn and Ports 0 1 2 and RESET lou 10 mA Ports 0 2 and P1 0
53. is always decremented before a push operation and incremented after a pop operation The stack pointer SP always points to the stack frame stored on the top of stack as shown in Figure 2 5 High Address Top of stack Stack contents Stack contents after a call Low Address after an instruction interrupt Figure 2 5 Stack Operations 2 5 2 Stack Pointer SP Register location D9H contains 8 bit SP that is used for system stack operations After reset the SP value is undetermined Since only internal memory 192 bytes space is implemented in S3F94C8 F94C4 the SP must be initialized to an 8 bit value in the range OOH OCOH In case a Stack Pointer is initialized to 00H it is decreased to FFH when stack operation starts This means that a Stack Pointer accesses invalid stack area It is recommended that a stack pointer is initialized to COH to set upper address of stack to BFH SAMSUNG ELECTRONICS 2 8 ux S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES Example 2 3 Programming Tip Standard Stack Operations Using PUSH and POP The following example shows you how to perform stack operations in the internal register file using PUSH and POP instructions LD SP 0COH SP lt Normally the SP is set to by the initialization routine address address address address address address address address SAMSUNG ELECTRONICS 2 9 I S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES ADDRESSIN
54. jumper in this mode Default setting EVA Mode SAMSUNG ELECTRONICS 17 6 im S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS Table 17 5 Using Single Header Pins as the Input Path for External Trigger Sources Target Board Part Comments Connector from External Trigger External Sources of the Triggers Application System Ch1 TP3 I Ch2 TP4 You can connect an external trigger source to one of the two external trigger channels CH1 or CH2 for SK 1000 SMDS2 breakpoint and trace functions L OW OFF High Default NOTE 1 For EVA chip smart option is determined by DIP switch not software 2 Please keep the reserved bits as default value high Figure 17 3 DIP Switch for Smart Option e IDLELED The IDLE LED is ON when the evaluation chip S3E94C0 is in the idle mode e STOPLED The STOP LED is ON when the evaluation chip S3E94C0 is in the stop mode SAMSUNG ELECTRONICS 17 7 er S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS VSS VDD P1 0 IG P0 0 ADCO INTO P1 1 PO 1 ADG1 INT 1 RESET P1 2 PO 2 ADC2 2 0 II P0 3 ADC3 P2 1 P0 4 ADC4 P2 2 P0 5 ADC5 P2 3 P0 6 ADC6 PWM 1912058 did Nid 02 P2 4 PO 7 ADC7 P2 5 OG P2 6 ADC8 CLO Figure 17 4 20 Connector for TB94C8 94C4 Target Board Target System J101 Target Cable for 20 Pin Connector JOJNUUOD Uld 0Z nm I 5 5 5
55. of source operand mask which is ANDed with the destination operand The zero Z flag can then be checked to determine the result The destination and source operands remain unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 Format Bytes Cycles Opcode Addr Mode Hex dst src 6 73 Ir opc src dst 3 6 74 R R 75 R IR opc dst src 3 6 76 R IM Examples Given RO 0C7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H RO gt 1 02 7 0 RO R1 RO OC7H R1 02H register 02H 23H Z 0 M gt 01H gt Register 00H 2BH register 01H 02H Z 0 M gt O1H Register OOH 2BH register 01H 02H register 02H 23H Z 0 TM 00H 54H gt Register 00 2BH 7 1 In the first example if working register RO contains the value 0C7H 1100011 1 and register R1 contains the value 02H 00000010B the statement TM RO R1 tests bit one in the destination register for a 0 value Since the mask value does not match with the test bit the Z flag is cleared to logic zero and can be tested to determine the result of TM operation SAMSUNG ELECTRONICS 6 50 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 38 XOR Logical Exclusive OR XOR dst src Operation dst dst XOR
56. pin 1 16 pin SAMSUNG ELECTRONICS 1 7 er S3F94C8 F94C4_UM_REV 1 00 1 OVERVIEW OF S3F94C8 94C4 1 6 Pin Circuits P channel IN N channel Figure 1 4 Pin Circuit Type A n o e D gt Figure 1 5 Pin Circuit Type B P1 2 Data Output Disable Figure 1 6 Pin Circuit Type SAMSUNG ELECTRONICS 1 8 er S3F94C8 F94C4_UM_REV 1 00 1 OVERVIEW OF S3F94C8 94C4 Pull up Enable Data Circuit Output Type C Disable Digital Input Figure 1 7 Pin Circuit Type D Open drain Enable Pull up P2CONH enable P2CONL OQ Alternative Output 2 O Output Disable Input Mode Digital Input Analog Input Enable ADC Figure 1 8 Pin Circuit Type E Port2 SAMSUNG ELECTRONICS 1 9 xu S3F94C8 F94C4_UM_REV 1 00 1 ADDRESS SPACES Pull up enable POCONH Alternative Output PO x Output Disable Input Mode Digital Input Interrupt Input Analog Input Enable ADC Figure 1 9 Pin Circuit Type E 1 PortO Open drain Enable Pull up enable Output Disable Input Mode Pull down enable Digital Input XIN Figure 1 10 Pin Circuit Type E 2 P1 0 P1 1 SAMSUNG ELECTRONICS 1 10 er S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES ADDRESS SPACES 2 1 Overview of Address Spaces S3F94C8 F94C4 microcontroller has two kinds of address space namely Internal full flash program memory ROM Internal register file
57. register the least significant byte is always stored in the next 1 odd numbered register n Even address Figure 2 4 16 Bit Register Pairs Example 2 2 Programming Tip Addressing the Common Working Register Area You should access working registers in the common area COH CFH using working register addressing mode and indirect register addressing mode Ta LD OC2H 40H Invalid addressing mode Use working register addressing mode instead LD R2 40H R2 C2H lt the value in location 40H 2 ADD 45H Invalid addressing mode Use working register addressing mode instead ADD R3 45H R3 lt 45H SAMSUNG ELECTRONICS 2 7 en S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES 2 5 System Stack S3F9 series microcontrollers use the system stack for subroutine calls and returns and for storing data The PUSH and POP instructions are used to control system stack operations The S8F94C8 F94C4 architecture supports stack operations in the internal register file 2 5 1 Stack Operations Return addresses for procedure calls and interrupts and data are stored on the stack The contents of the PC are saved on the stack by a CALL instruction and restored by the RET instruction When an interrupt occurs the contents of the Programmer Counter PC and System Flags FLAGS register are pushed to the stack The IRET instruction then pops these values back to their original locations The stack address
58. source peripheral control register If all of the above conditions are met the interrupt request is acknowledged at the end of instruction cycle The CPU then initiates an interrupt machine cycle that completes the following processing sequence 1 Reset clear to 0 the global interrupt enable bit in SYM register DI SYM 3 O to disable all subsequent interrupts 2 Save the program counter and status flags to stack 3 Jump to the interrupt vector to fetch the service routine s address 4 Pass control to the interrupt service routine When the interrupt service routine is completed an Interrupt Return instruction IRET occurs The IRET restores the PC and status flags and sets SYM 3 to 1 El This allows the CPU to process the next interrupt request 5 1 7 Generating interrupt Vector Addresses The interrupt vector area in ROM contains the address of interrupt service routine Vectored interrupt processing follows this sequence 1 Push the program counter s low byte value to stack 2 Push the program counter s high byte value to stack e Push the FLAGS register values to stack Fetch the service routine s high byte address from the vector address 0000H Fetch the service routine s low byte address from the vector address 0001H 6 Branch to the service routine specified by the 16 bit vector address SAMSUNG ELECTRONICS 53 im S3F94C8 F94C4_UM_REV 1 00 5 INTERRUPT STRUCTURE 5 1
59. specifies the ROM option for starting condition of any chip The ROM addresses used by smart option range from 003CH to 003FH The S8F94C8 F94C4 only uses and 003FH Unused ROM address such as 003CH and 003DH must be initialized to OOH The default value of ROM 003EH and 003FH is FFH LVR enable internal RC oscillator ROM Address 003CH Must be initialized to OOH ROM Address 003DH Must be initialized to OOH ROM Address 003EH LVR enable disable bit LVR level selection bits used 0 Disable 10100 1 9 V 1 Enable 11001 23V 10010 3 0 V 00111 3 6 V 01100 3 9 V ROM Address 003FH Oscillator selection bits 00 External crystal ceramic oscillator 01 External RC 10 Internal RC 0 5 MHz in Vpb 5 V 11 Internal RC 3 2 MHz in 5 V NOTES When you use external oscillator P1 0 P1 1 must be set to output port to prevent current consumption The value of unused bits of 3EH 3FH is don t care When LVR is enabled P1 2 nRESET is used as input port and LVR level must be set to appropriate value not default value Figure 2 2 Smart Option SAMSUNG ELECTRONICS 2 3 ux S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES Example 2 1 Programming Tip Smart Option Setting lt lt Interrupt Vector Address gt gt ORG 0000H Vector 00H INT 94C8 S3F94C8 F94C4 has only one interrupt vector lt lt Smart Option Setting gt gt ORG 03CH DB must be ini
60. the CPU clock speed to fOSC fOSC 2 or fOSC 8 System Clock Control Register CLKCON D4H R W Oscillator IRQ wake up enable bit Not used for S3F94C8 F94C4 0 Enable IRQ for main system oscillator wake up function in power down mode Divide by selection bits for 1 Disable IRQ for main system CPU clock frequency oscillator wake up function in 00 fosc 16 power down mode 01 fosc 8 10 fosc 2 11 fosc non divided Not used for S3F94C8 F94C4 Figure 7 3 System Clock Control Register SAMSUNG ELECTRONICS 7 2 er S3F94C8 F94C4_UM_REV 1 00 7 CLOCK CIRCUIT Smart Option SF 1 0 in ROM Stop Instruction 4 3 Oscillator Stop Internal RC Oscillator 3 2MHz Internal RC Oscillator 0 5 MHz Selected External OSC CPU Clock Crystal Ceramic Oscillator Oscillator Wake up External RC Oscillator Noise Filter CLKCON 7 P2CONH 6 4 INT Pin P2 6 CLO NOTE Anexternal interrupt with RC delay noise filter can be used to release stop mode and wake up the main oscillator In the S3F94C8 F94C4 the INTO INT1 external interrupts are of this type Figure 7 4 System Clock Circuit Diagram SAMSUNG ELECTRONICS 7 3 xu S3F94C8 F94C4_UM_REV 1 00 8 RESET AND POWER DOWN RESET AND POWER DOWN 8 1 System Reset 8 1 1 Overview of System Reset Use the Smart option 3EH 7 in ROM to select internal RESET LVR or external RESET While using inte
61. the operands were of opposite signs and the sign of result is the same as sign of the source operand cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 23 r Ir src dst 3 6 24 R R 25 R IR dst src 3 6 26 R IM Examples Given 1 12H R2 03H register 01H 21H register 02 03H register OAH SUB R1 R2 gt 1 OFH R2 03H SUB R1 R2 08H R2 03H SUB 01H 02H Register 01 1EH register 02H 03H SUB 01H 02H Register 01H 17H register 02H 03H SUB O1H 90H Register 01H 91H C S and 1 SUB O1H 65H gt Register 01H 1 V 0 In the first example if working register R1 contains the value 12H and if register R2 contains the value 03H the statement SUB R1 R2 subtracts the source value 03H from the destination value 12H and stores the result OFH in destination register R1 gt 5 SAMSUNG ELECTRONICS 6 48 I S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 36 TCM Test Complement Under Mask TCM dst src Operation NOT dst AND src This instruction tests selected bits in the destination operand for a logic one value The bits to be tested are specified by setting a 1 bit in the corresponding position of the source operand mask The TCM statement complements the destination operand which is then ANDed with the source mask The zero Z flag can then be checked to determine
62. the result The destination and source operands remain unaffected Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 Format Bytes Cycles Opcode Addr Mode Hex dst src 6 63 Ir src dst 3 6 64 R R 65 R IR opc dst src 3 6 66 R IM Examples Given RO 0C7H R1 02H R2 12H register OOH 2BH register 01H 02H and register 02H 23H TCM RO RI gt RO OC7H RL 02H Z 1 TCM RO R1 gt RO OC7H R1 02H register 02H 23H 0 TCM 00H 01H gt Register 00H 2BH register 01H TCM 00H 01H gt Register 00H 2BH register 01 02H register 02H 23H Z I TCM 00H 34 gt Register 00 2BH 7 0 In the first example if working register RO contains the value OC7H 11000111B and register R1 the value 02H 00000010B the statement TCM RO R1 tests bit one in the destination register for a 1 value Since the mask value corresponds to the test bit the Z flag is set to logic one and can be tested to determine the result of TCM operation SAMSUNG ELECTRONICS 6 49 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 37 TM Test Under Mask dst src Operation dst AND src This instruction tests selected bits in the destination operand for logic zero value The bits to be tested are specified by setting a 1 bit in the corresponding position
63. 0 O Port 0 Data Register Po RW o o o o o oj o o Port 1 Data Register Pm RW 0 0 Pot2DataRegstr Pe RW jo ojojo ojo o Locations E3H E5H Are Not Mapped Port 0 Control Register High Byte POCONH RW Port 0 Control Register PocONL RW Port 0 Interrupt Pending Register POPND RW 0000 Port 1 Control Register Picon RW Port 2 Control Register High Byte P2cONH RW Port 2 Control Register Low Byte Pecon RW 0 Flash Memory Control Register RW 0 0j0 0 0 Flash Memory User Programming FMUSR R W Enable Register Flash Memory Address UT 20000050 Flash Memory Address Register FMSECL EFH R W Low Byte PWMDataRegisteri PWMDATAi RW o o o o o PWM Extension Register PWMEX RW ojojo o o PWM Data Register PWMDATA RW o ojojojojo 0 0 SAMSUNG ELECTRONICS 4 2 xu S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS Register Name Location Address RW 7 6 5 41312 110 Control Register PWMCON mW o o o o STOP Control Register STOPCON mw Locations F5H F6H Are Not M
64. 00000B 00000000B 4096 128 Basic timer increment and CPU operations are IDLE mode NOTE Duration of the oscillator stabilization wait time tWAIT when it is released by a Power on reset is 4096 x 128 fosc 3 RC and C are value of external power on Reset Figure 10 2 Oscillation Stabilization Time on RESET SAMSUNG ELECTRONICS 10 4 er S3F94C8 F94C4 UM REV 1 00 External Interrupt RESET STOP Release Signal Oscillator Xour 10 BASIC TIMER AND TIMER 0 Normal Normal Operating Operating Mode Mode STOP Mode Oscillation Stabilization Time STOP Instruction STOP Mode Execution x Release Signal gt Basic Timer Increment NOTE Duration of the oscillator stabilzation wait time tWAIT it is released by an interrupt is determined by the setting in basic timer control register BTCON o 4096 x 128 fosc 52 4 ms oeoa d m Lo maser gt Figure 10 3 Oscillation Stabilization Time on STOP Mode Release SAMSUNG ELECTRONICS 10 5 im S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 Example 10 1 Programming Tip Configuring the Basic Timer This example shows how to configure the basic timer to sample specification ORG 0 VECTOR 00H INT 94C4 S3F94C8 F94C4 has only one interrupt vector lt lt Smart Option gt gt ORG 0 DB OO3CH must be initialized to 0 DB OO3DH mu
65. 1 A D converter input ADC6 schmitt trigger input off 3 2 Port 0 P0 5 ADC5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 A D converter input ADC5 schmitt trigger input off 1 0 Port 0 P0 4 ADC4 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 A D converter input ADC4 schmitt trigger input off Figure 9 3 Port 0 Control Register POCONH High Byte SAMSUNG ELECTRONICS 9 4 er S3F94C8 F94C4_UM_REV 1 00 9 PORTS SAMSUNG ELECTRONICS Port 0 Control Register Low Byte E7H R W 7 6 Port 0 P0 3 ADC3 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 1 1 A D converter input ADC3 schmitt trigger input off 5 4 Port 0 P0 2 ADC2 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 1 1 A D converter input ADC2 schmitt trigger input off 3 2 Port 0 PO 1 ADC1 INT1 Configuration Bits 0 0 Schmitt trigger input falling edge interrupt input 0 1 Schmitt trigger input pull up enable falling edge interrupt input 10 Push pull output 1 1 A D converter input ADC1 schmitt trigger input off 1 0 Port 0 P0 0 ADCO INTO Configuration Bits 0 0 Schmitt trigger input falling edge interrupt input 0 1 S
66. 1 FFH Enable LVR 2 3 000H 003FH External Crystal Oscillator lt lt Initialize System and Peripherals gt gt ORG 0100H DI Disable Interrupt LD BTCON 10100011B Disable Watchdog LD PWMEX 00000000B Configure 6 bit base 2 bit extension LD POCONH 10011010B Configure P0 6 PWM output LD PWMCON 00000110B fOSC 64 Enable counter interrupt PWMEX 00000011B Set extension bits as 00 basic output LD PWMDATA 80H EI Enable interrupt lt lt Main loop gt gt INT 94C4 94 4 interrupt service routine PWMCON 11110110B Clear pending bit SAMSUNG ELECTRONICS 11 13 S3F94C8 F94C4 UM REV 1 00 12 A D CONVERTER A D CONVERTER 12 1 Overview of A D Converter The 10 bit A D converter ADC module uses successive approximation logic to convert analog levels entering at one of the nine input channels to equivalent 10 bit digital values The analog input level must lie between the VDD and VSS values The A D converter has the following components e Analog comparator with successive approximation logic D A converter logic e ADC control register ADCON e Nine multiplexed analog data input pins ADC0 ADC8 e 10 bit A D conversion data output register ADDATAH L To initiate an analog to digital conversion procedure write the channel selection data in the A D converter control register ADCON
67. 10MHz e Operating Temp 40 C to 85 C e Internal RC tolerance 1 typ 3 40 C to 85 C 1 8 5 5V Stop current 1uA typ 20 max 25 C 4 5 5 5V V0 1 Dec 16 2008 PWM block changed add one data register e For improve the PWMDATA1 compatibility e Operating voltage range change to 1 8V 5 5V without conflict and confusion e Spec change to fit the real performance Dec 23 2008 Internal RC precision change to Typ 3 e For more margin to 596 design e ADC maximum clock 2MHz vAccording to the ADC operating voltage 2 7V 5 5V minimum convert time V0 2 Jan 07 2009 e Interrupt low width 200nS typ same with e According to new 9454 noise filter design Reset width 1uS Min same with 9454 e For the reason of e LVR current added gt 1003 stop with LVR operating voltage enable data added change e Reason 2 6V 250C LVR enable parameter same with 9454 30uA typ 60uA Max simulation result 22uA typ 09 06 test chip test result 28uA 2 6V 5V 250C LVR enable simulation result 35uA so according to the relation of current with voltage set the parameter as 50uA Typ 100uA Max 5V 2 6V 30uA 50uA SAMSUNG ELECTRONICS I Revision No Date Description Remark 9454 parameter too large 09 06 test chip test result 38uA 5 0V e LVR Level add 1 9V V0 3 Feb 09 2009 No No Mar 02
68. 12 A D CONVERTER 12 1 3 Internal Reference Voltage Levels In the ADC function block the analog input voltage level is compared to the reference voltage The analog input level must remain within the range of VSS to VDD Different reference voltage levels are generated internally along the resistor tree during analog conversion process for each conversion step The reference voltage level for the first bit conversion is always 1 2 VDD A D Converter Control Register ADCON F7H ADCON 0 ADEN ADCON 7 4 Control Clock ADCON 3 Circuit Selector EOC Flag ADCO PO 0 ADC1 P0 1 ADC2 P0 2 Successive Approximation Circuit Conversion Result Analog Comparator ADG7 P0 7 ADC8 P2 6 amxmrv ircz Vop D A Converter A ADDATAH ADDATAL V data bus Figure 12 2 A D Converter Circuit Diagram ADDATAH mom T T T IIS Figure 12 3 A D Converter Data Register ADDATAH L SAMSUNG ELECTRONICS 12 3 xu S3F94C8 F94C4 UM REV 1 00 12 A D CONVERTER ADCON 0 lt 50 ADC Clock Conversion Start ADDATA Previous ADDATAH 8 Bit ADDATAL 2 Bit Value gt Set 10 clock 40 Clock Figure 12 4 A D Converter Timing Diagram 12 1 4 Conversion Timing The A D conversion process requires four steps 4 clock edges to convert each bit and 10 clocks to step up A D conversion Therefore 50 clocks are required to complete a 10 bit conve
69. 2 TIMEN 10 1 10 2 Basic Timer Bl eei e 10 2 10 2 1 Basic Timer Control Register nennen nennen 10 2 10 2 2 Basic iia 10 3 10 2 2 1 Watchdog Timer Function enne 10 3 10 2 2 2 Oscillation Stabilization Interval Timer Function 10 3 10 3 Aa O 10 7 10 3 1 Timer 0 Control Registers 1 10 7 10 3 2 Timer 0 Function 10 8 10 3 21 Interval Timer irt tte Sistas sete cette ee Kr re esa rea uda 10 8 11 PULSE WIDTH MODULATION 2222222 5252 2xuc cnr 11 1 11 1 Overview of Pulse Width Modulation sessssessssseeees eee ennemis nnne nenas 11 1 Tid FUNeton DESENPUON ER 11 1 G 11 1 11 1 1 2 PWM COUNTENT sicie a 11 1 11 1 1 3 PWM Data and Extension 5 5 11 2 11 1 1 4 PWM Clock 11 3 11 1 1 5 PWM Function DescriptiOni ettet 11 3 11 1 1 6 PWM Output 11 4 11 1 2 PWM Control Register
70. 4 5 and 6 Later you can reference the information in Part as necessary Part II hardware Descriptions has detailed information about specific hardware components of the S3F94C8 94C4 microcontroller Also included Part Il are electrical mechanical flash and development tools data It has 9 chapters Chapter 7 Clock Circuit Chapter 8 Chapter 9 I O Ports Chapter 10 Chapter 11 12 bit PWM Chapter 12 A D Converter SAMSUNG ELECTRONICS RESET and Power Down Basic Timer and Timer 0 Chapter 13 Chapter 14 Chapter 15 Chapter 16 Chapter 17 Embedded Flash Interface Electrical Data Mechanical Data Flash MCU Development Tools Table of Contents 1 OVERVIEW OF S3F94C8 94C4 nrrrnvnnnnnnnnnnnvnnnnnnnvennnnnnnnnnnnnnnnnevennnnnnnnnnnnnnnner 1 1 1 1 SAM88RGRI Micro ontrolleTS i 1 1 1 1 1 SSF94C8 F94CA entere ensi nnn sensns 1 1 AIITEM H 1 2 1 3 Block Diagram of 9 8 94 8 1 3 14 PIM ASSIQMIMEINS UM 1 4 1 5 Description EE 1 6 1 6 Pin CIRCUITS 1 8 2 ADDRESS SPACES dd 2 1 2 1 Overview of Address 2 1 2 2 Program Memory ROM
71. 4 13 4 1 12 PICON Port 1 Control Register 9 4 14 4 1 13 P2CONH Port 2 Control Register High Byte 4 15 4 1 14 P2CONL Port 2 Control Register Low Byte 4 16 4 1 15 PWMCON PWM Control Register F3H nnns 4 17 4 1 16 PWMEX PWM Extension Register F1H 4 18 4 1 17 STOPCON STOP Mode Control Register 4 19 4 1 18 SYM System Mode Register entree nennen senten nennen nns 4 19 4 1 19 TIMER 0 Control Register 2 4 20 5 INTERRUPT STRUCTURE nesen 5 1 5 1 Overview of Interrupt 5 1 5 1 1 Interrupt Processing Control 1 5 1 5 1 2 Enable Disable Interrupt Instructions El 5 2 5 1 3 Interrupt Pending Function Types 5 2 5 1 4 IMLS RU OU Ponty 5 2 5 1 5 Interrupt Source Service 5 nennen nennen en 5 3 5 1 6 Interrupt Service ROutines erint ten e nde ne
72. 4 FLASH 16 3 Information Block The S3F94C8 94C4 provides a special flash area for storing chip ID or customer s information into it called the information block This block is separate from the main flash ROM which includes the flash ROM memory erase write read read protection operation The information in special flash area can be erased written read by Flash Programmer Tools and is not available in the user mode The size of information block is 256Bytes Since it is separate from flash ROM the programming operation chip erase write will not erase change the data in information block You can write the Chip ID different for each chip into it to distinguish every chip This is useful for anti imitation by storing production related information in this area Main Flash ROM 8 191 S3F94C8 Tool Erase write read Hard lock 4 095 Read protection S3F94C4 User Erase write read Information Block Hard lock 255 S3F94C8 C4 Tool Erase write read Figure 16 4 S3F94C8 F94C4 Flash Architecture Table 16 4 Operation Results Comparison of Main Flash ROM and Information Blocks Operation MaimFashROM information Biock SAMSUNG ELECTRONICS 16 6 im S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS DEVELOPMENT TOOLS 17 1 Overview of Development Tools Samsung provides a powerful and easy to use development support system on a turnkey basis The development support system i
73. 8 2 Power Down Modes 8 2 1 Stop Mode Stop mode is invoked by the instruction STOP opcode 7FH In this mode the operation of CPU and all peripherals is halted that is the on chip main oscillator stops and the supply current is reduced to less than 4uA except LVR which is enabled All system functions are halted when the clock freezes but data stored in the internal register file is retained Stop mode can be released by an nRESET signal or an external interrupt NOTE Before executing the STOP instruction set the STPCON register as 10100101b 8 2 1 1 Using RESET to Release Stop Mode Stop mode is released when nRESET signal is released and returned to High level All system and peripheral control registers are then reset to their default values and the contents of all data registers are retained A Reset operation automatically selects a slow clock fOSC 16 because CLKCON 3 and CLKCON 4 are cleared to 00B After the oscillation stabilization interval has elapsed the CPU executes the system initialization routine by fetching the 16 bit address stored in ROM locations 0100H and 0101H 8 2 1 2 Using an External Interrupt to Release Stop Mode External interrupts with an RC delay noise filter circuit can be used to release Stop mode Clock related external interrupts cannot be used External interrupts INTO INT1 in S3F94C8 F94C4 interrupt structure meets this criterion NOTE When Stop mode is released by an external in
74. 8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 1 1 1 Tool Program Mode This mode is applied at the time of erasing and programming full area of flash memory by using external programming tools The five pins of SSF94C8 F94C4 are connected to a programming tool The internal flash memory of S3F94C8 F94C4 be programmed by using Serial OTP MTP tools SPW2 plus single programmer or GW PRO2 gang programmer and so on Other modules except flash memory module operate at reset state This mode does not support sector erase However it supports chip erase all flash memory is erased at a time and two protection modes Hard lock protection Read protection The read protection mode is only available in tool program mode To read protect a chip select read protection option while writing program code to a chip in tool program mode by using a programming tool After read protect all data of flash memory read becomes 00 This protection is released by chip erase execution in tool program mode Table 13 1 Descriptions of Pins Used to Read Write the Flash in Tool Program Mode Main Chip During Programming M Serial data pin Output when reading Input 1 SDAT t when writing Input and push pull output port can be assigned d un SCLK EE Serial clock pin input only pin Power supply pin for Tool mode entering indicates that MTP enters into the Tool Rese Pie mode When 11 V is applied MTP is in Tool mode 3 20 pin
75. 8 S3F94C8 F94C4 Interrupt Structure The S3F94C8 F94C4 microcontroller has four peripheral interrupt sources e PWM overflow e Timer 0 match PO0 0 external interrupt PO 1 external interrupt Vector Enable Disable Pending Bits Source TOCON 0 Timer 0 Match TOCON 1 PWMCON 0 PWM Overflow PWMCON 1 0000H 0001H POPND 0 P0 0 External Interrupt POPND 1 SYM 3 El DI POPND 2 P0 1 External Interrupt POPND 3 Figure 5 3 S3F94C8 F94C4 Interrupt Structure SAMSUNG ELECTRONICS 5 4 er S3F94C8 F94C4 UM REV 1 00 5 INTERRUPT STRUCTURE 5 1 9 Peripheral Interrupt Control Registers For each interrupt source there is one or more corresponding peripheral control registers that lets you control the interrupt generated by the related peripheral see Table 5 1 Table 5 1 Interrupt Source Control and Data Registers Interrupt Source Register s Register Location s P0 0 external interrupt POCONL E7H 1 external interrupt POPND E8H D2H PWMCON F3H PWM overflow interrupt PWMDATA F2H PWMDATA1 FOH SAMSUNG ELECTRONICS 55 x S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET SAM88RCRI INSTRUCTION SET 6 1 Overview of SAM88RCRI Instruction Set The SAM88RCRI instruction set is designed to support large register file It includes full complement of 8 bit arithmetic and logic operations There are 41 instructions No special I O instructions are neces
76. 9 Programming Tip Sample S3F94C8 F94C4 Initialization Routine 8 9 Programming Tip Configuring the Basic Timer 10 6 Programming Tip Configuring Timer 0 Interval 10 11 Programming Tip Programming the PWM Module to Sample Specifications 11 13 Programming Tip Configuring A D Converter sse 12 6 Programming Tip Sector 13 7 Programming Tip Programming sess enne 13 11 Programming Tip Reading 13 14 Programming Tip Hard Lock Protection sess 13 15 S3F94C8 F94C4_UM_REV 1 00 1 OVERVIEW OF S3F94C8 94C4 OVERVIEW OF S3F94C8 94C4 1 1 SAM88RCRI Microcontrollers Samsung s SAM88RCRI series of 8 bit single chip CMOS microcontrollers offer a fast and efficient CPU along with a wide range of integrated peripherals and programmable ROM with various sizes The key features of CPU include e Efficient register oriented architecture e Selectable CPU clock sources e Idle and Stop power down modes released by the interrupt e Built in basic timer with watchdog function To render a flexible programming environment for applications with varied memory and I O requirements a
77. A D Converter lt lt Interrupt Vector Address gt gt ECTOR 00H INT TIMERO S3F94C8 F94C4 has only one interrupt vector lt lt Smart Option gt gt ORG 3CH DB OH 003CH DB OH 003DH DB FH DB 3H 100H DI Disable Interrupt LD BTCON 10100011B Disable Watchdog must be initialized to 0 must be initialized to 0 enable LVR internal RC oscillator 0 0 0 0 0 0 POCONH 11111111B POCONL 11111111B P2CONH 00100000B Configure P0 4 P0 Configure P0 0 P0 Configure P2 6 AD 7 AD input 3 AD input input Enable interrupt lt lt Main loop gt gt CALL AD CONV Subroutine for AD conversion e e JR t MAIN AD_CONV ADCON 00000001B Select analog input channel gt P0 0 Select conversion speed fOSC 16 Set conversion start bit If you select conversion speed to fOSC 16 at least one NOP must be included CONV LOOP ADCON 00001000B Check EOC flag Z CONV LOOP EOC flag 0 1 High 8 bits of conversion result are stored in ADDATAH register jump to CONV_LOOP until EOC flag RO ADDATAH R1 ADDATAL Low 2 bits of conversion result are stored in ADDATAL register Select analog input channel gt P0 1 ADCON 00010011B Select conversion speed fOSC 8 Set conversion start bit SAMSUNG ELECTRONICS 12 6 S3F94C8 F94C4 UM REV 1 00 12 A D CONVERTER CONV_LOOP2 ADCON 00001000B EOC
78. A1 e Extension data registers PWMEX PWM output pins P0 6 PWM 11 1 1 2 PWM Counter The PWM counter is an incrementing counter comprised of a lower base counter and an upper extension counter To determine the PWM module s base operating frequency the lower base counter is compared to the PWM base data register value In order to achieve higher resolutions the extension bits of upper counter can be used to modulate the stretch cycle To control the stretching of PWM output duty cycle at specific intervals the extended counter value is compared to the value you write to the module s extension bits SAMSUNG ELECTRONICS 11 1 er S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION 11 1 1 3 PWM Data and Extension Registers PWM duty data consist of base data bits and extension data bits Determine the output value generated by the PWM circuit For each PWM resolution the location of base data bits and extension data bits are different combinations of register PWMDATA F2H PWMDATA1 FOH and PWMEX F1H e 8 bit resolution 6 bit base 2 bit extension Base 6 data bits PWMDATA 7 2 Extension 2 bits PWMDATA 1 0 12 bit resolution 6 bit base 6 bit extension Base 6 data bits PWMDATA1 5 0 Extension 6 bits PWMEX 7 2 14 bit resolution 8 bit base 6 bit extension Base 8 data bits PWMDATA1 7 0 Extension 6 bits PWMEX 7 2 Base 1 for 12 bit PWM PWMDATA 1
79. B94C8 94C4 Target Board The TB94C8 94C4 target board is used for S3F94C8 F94C4 microcontrollers This board is operated as target CPU with Emulator OPENIce 1 500 2000 SK 1200 ae rT1B94C8 94C4 ELECTRONICS To User_Vcc Off Idle Stop 128 S3E94C0 EVA Chip 20 Q c c ks Target System Interface Emulator Interfalce Main Mode 0 Board Clock EVA Mode SMDS2 SMDS2 JP4 Disable Figure 17 2 94 8 94 4 Target Board Configuration NOTE Since TB94C8 94C4 should be supplied with 5V the power supply from Emulator should be 5V for the target board operation SAMSUNG ELECTRONICS 17 3 xu S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS Table 17 1 Components of TB94C8 94C4 us 2o pin connector Connection between target board and user application sytem wa epnswien SmatOplonsetplrS FMCSMOREVAGND MACC fo Selection of SMDS2 SMDS2 internal external clock JP2 MODE Selection Selection of Eva Main chip mode of S3F94C8 94C4 EVA chip Enables disables the selection of PWM Selection of SMDS2 SMDS2 Selection of power to user Table 17 2 Power Selection Settings for TB94C8 94C4 To User Vcc Settings Operating Mode Faser Vec The SMDS2 SMDS2 main BEEF board supplies to the off o on target board evaluation chip and target system TB94
80. C8 94C4 The SMDS2 SMDS2 main To user_Vcc ss board supplies only to eg the target board evaluation chip The target system must have its own power supply NOTE The symbol in the To User Vcc setting column indicates the electrical short off configuration SAMSUNG ELECTRONICS 17 4 xu S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS 17 1 5 SMDS2 Selection SAM8 To write data into program memory available in SMDS2 the target board should be selected for SMDS2 through switch as shown in Table 17 3 Otherwise the program memory writing function is not available Table 17 3 The SMDS2 Tool Selection Setting JP4 Setting Operating Mode R W R W Target SMDS 2 eo SMDS 2 SMDS2 System SAMSUNG ELECTRONICS 17 5 er S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS Table 17 4 Using Single Header Pins to Select Clock Source PWM Operation Mode Board CLK amp o da s internal clock source as the system clock Default setting Inner CLK Board CLK JP1 Use external crystal or ceramic oscillator as the system clock Clock Source Inner CLK PWM Enable JP3 PWM function is disabled PWM Disable PWM Enable H JP3 PWM function is enabled Default setting PWM Disable Main Mode 53 94 0 runs in the Main mode similar to S3F94C8 F94C4 The debug interface is not available Main Mode JP2 SSE94CO runs in the EVA mode While debugging a program set the
81. DF Example The statement SCF Sets the carry flag to logic one SAMSUNG ELECTRONICS 6 45 xu S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 33 SRA Shift Right Arithmetic SRA dst Operation dst 7 lt dst 7 dst 0 dst lt dst 1 n 0 6 An arithmetic shift right of one bit position is performed on the destination operand Bit zero LSB replaces the carry flag The value of bit 7 sign bit remains unchanged and is shifted to bit position 6 Flags C Set if the bit shifted from the LSB position bit zero was 1 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Always cleared to 0 Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 4 DO R D1 IR Examples Given Register 00H 9AH register 02H 03H register 03H OBCH and 1 SRA 00H Register 00H OCD C 0 SRA 02 Register 02H 03H register 03H EH C 0 In the first example if general register 00H contains the value 9AH 10011010B the statement SRA shifts the bit values in register to right one bit position Bit zero 0 clears the C flag and bit 7 1 is then shifted to the bit 6 position bit 7 remains unchanged This leaves the value 11001101B in destination register SAMSUNG ELECTRONICS 6 46 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET
82. Disable NOTE TOCON 3 is not auto cleared you must pay attention when clear pending bit refer to P10 12 Figure 10 5 Simplified Timer 0 Function Diagram Interval Timer Mode SAMSUNG ELECTRONICS 10 8 im S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 Compare Value Match Match Match TODATA Match Match Match Match Up Counter Value TOCNT 00H Clear Clear Count start i TOCON 3 1 Value change Counter Clear TOCON 3 Interrupt Request TOCON 0 TO Match Output P2 0 Figure 10 6 Timer 0 Timing Diagram SAMSUNG ELECTRONICS 10 9 im S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 RESET or STOP Bits 3 2 v Basic Timer Control Register Data Bus Write 1010xxxxB to disable 8 Bit Up Counter 11084 MUX Read Only 1 128 When BTCNT7 is set after releasing from RESET or STOP mode CPU clock starts Data Bus TOCNT DOH Clear Read Only P2 CONL 1 0 Match Signal TODATA D1H Read Write Basic Timer Control Register Data Bus m TimerO Control Register NOTE During a power on Reset operation the CPU is idle during the required oscillation stabilization interval until bit 7 the basic timer counter is set Figure 10 7 Basic Timer and Timer 0 Block Diagram SAMSUNG ELECTRONICS 10 10 en S3F94C8 F94C4_UM_REV 1 00 10 BASIC TIMER AND TIMER 0 Example 10 2 Programming Tip Configuring Timer 0 Interval Mode The followi
83. FH Bitidentifer 7 6 5 4 3 2 a1 o Resetvaue o o 0 0 ew am aw T 3 Global Interrupt Enable Bit Disables all interrupts Enables all interrupt 2 0 Page Select Bits 0 Pageo 1 t Not used for S3F94C8 F94C4 0 Page 2 Not used for S3F94C8 F94C4 Page 3 Not used for S3F94C8 F94C4 ofa ofa SAMSUNG ELECTRONICS 4 19 IP S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 19 TOCON TIMER 0 Control Register D2H Bit Identifier LIL SIL ei Ie e e me o o 9 9 ew aw ww aw RW 7 6 Timer 0 Input Clock Selection Bits fOSC 4096 fOSC 256 fOSC 8 5 4 Not used for S3F94C8 F94C4 3 Timer 0 Counter Clear Bit No effect Clears the timer 0 counter when write 2 Not used for S3F94C8 F94C4 Timer 0 Interrupt Enable Bit EN Disables interrupt Enables interrupt 0 Timer 0 Interrupt Pending Bit Match interrupt No interrupt is pending when read Clears pending bit when write i i Interrupt is pending when read No effect when write NOTE 1 TOCON 3 is not auto cleared You must pay attention while clearing pending bit Refer to pages 10 12 for more information 2 Touse TO match output set TOCON 3 to 1 Refer to pages 10 7 for more information SAMSUNG ELECTRONICS 4 20 IP S3F94C8 F94C4_UM_
84. G MODES 3 1 Overview of Addressing Modes Instructions indicate the operation to be performed and the data to be operated upon Instructions stored in program memory are fetched for execution using the program counter To determine the location of data operand Addressing mode is used The operands specified in SAM88RCRI instructions can include condition codes and immediate data or a location in the register file program memory or data memory The SAM88RCRI instruction set supports six explicit addressing modes Not all of these addressing modes are available for each instruction The addressing modes and their symbols are as follows e Register R e Indirect Register IR Indexed X e Direct Address DA e Relative Address RA e Immediate IM SAMSUNG ELECTRONICS 3 1 I S3F94C8 F94C4_UM_REV 1 00 3 1 1 Register Addressing Mode 3 ADDRESSING MODES In Register Addressing mode the operand specifies the content of a specified register see Figure 3 1 Working register addressing differs from Register Addressing because it uses a 16 byte working register space in the register file and a 4 bit register within that space see Figure 3 2 Program Memory OPCODE 8 Bit Register File Address One Operand Instruction Example Point to one register in register Register File pum Value used in Instruction Execution Sample Instruction DEC CNTR Where CNTR is the label of an 8 bit register addr
85. H and register 08H 8AH OR RO R1 RO 3FH 1 2 OR RO R2 RO 37H R2 01H register 01H 37H gt gt OR 00H 01H Register register 01H 37H OR O1H Q00H Register 00H 08H register 01H OBFH OR 02H gt Register OOH OAH In the first example if working register RO contains the value 15H and register R1 contains the value 2AH the statement OR RO R1 logical ORs both RO and 1 register contents and stores the result in destination register RO The other examples show the use of logical OR instruction with the various addressing modes and formats SAMSUNG ELECTRONICS 6 35 en S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 23 POP Pop From Stack POP dst Operation dst lt SP SP SP 1 The contents of location addressed by stack pointer are loaded into the destination The stack pointer is then incremented by one Flags No flags affected Format Bytes Cycles Opcode Addr Mode Hex dst dst 2 8 50 R 51 IR Examples Given Register 00 01H register 01H 1BH SP OD9H OBBH and stack register OBBH 55H POP OOH gt Register 55H SP OBCH POP 00H gt Register 00H 01H register 01H 55H SP OBCH In the first example general register 00H contains the value 01H The statement POP 00H loads the contents of location OBBH 55H into destination register OOH and then increments the stack pointer by one
86. NICS 13 8 xu S3F94C8 F94C4_UM_REV 1 00 FMSECH High Address of Sector FMSECL Low Address of Sector High Address to Write Low Address to Write 8 bit Data lt 0A5H FMCON 01010000B LDC 4 RR n R data FMUSR 00 Finish 1 BYTE Writing 13 EMBEDDED FLASH MEMORY INTERFACE Set Secotr Base Address Set Address and Data User Program Mode Enable Mode Select Write data at flash User Program Mode Disable Figure 13 7 Byte Program Flowchart in a User Program Mode SAMSUNG ELECTRONICS 13 9 S3F94C8 F94C4_UM_REV 1 00 FMSECH High Address of Sector FMSECL lt lt Low Address of Sector High Address to Write Low Address to Write 8 bit Data lt 0A5H FMCON 01010000B LDC 4 RR R data YES NO NO FMUSR lt 00 TES Finish Writing Continuous address YES Different YES Data R data New 8 data 13 EMBEDDED FLASH MEMORY INTERFACE Set Secotr Base Address Set Address and Data User Program Mode Enable Mode Select Write data at flash User Program Mode Disable User Program Mode Disable Check Sector Check Address Increse Address Update Data to Write Figure 13 8 Program Flowchart in a User Program Mode SAMSUNG ELECTRONICS 13 10 S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE Example 13 2 Programming Tip Programming Case1 1 Byte Progr
87. REV 1 00 5 INTERRUPT STRUCTURE INTERRUPT STRUCTURE 5 1 Overview of Interrupt Structure The SAM88RCRI interrupt structure has two basic components namely vector and sources The number of interrupt Sources can be serviced through an interrupt vector that is assigned in ROM address OOOOH VECTOR SOURCES 1 S2 NOTES 1 The SAM88 RCRI interrupt has only one vector address 0000H 0001H 2 The number of Sn value is expandable Figure 5 1 S3F9 Series Interrupt Type 5 1 1 Interrupt Processing Control Points Interrupt processing can be controlled in two ways that is either globally or by specific interrupt source The system level control points in the interrupt structure are as follows Global interrupt enable and disable by El and DI instructions Interrupt source enable and disable settings in the corresponding peripheral control register s SAMSUNG ELECTRONICS 5 1 uu S3F94C8 F94C4 UM REV 1 00 5 INTERRUPT STRUCTURE 5 1 2 Enable Disable Interrupt Instructions El DI The system mode register SYM DFH is used to enable and disable interrupt processing SYM 3 is the enable and disable bit for global interrupt processing The system initialization routine executed after a reset must always contain an instruction to globally enable the interrupt structure Although you can manipulate SYM 3 directly to enable and disable interrupts during normal operation it is recommended that you use the and DI ins
88. S3F94C8 F94C4 8 Bit CMOS MICROCONTROLLERS Revision 1 00 July 2010 USER S MANUAL SAMSUNG ELECTRONICS RESERVES THE RIGHT TO CHANGE PRODUCTS INFORMATION AND SPECIFICATIONS WITHOUT NOTICE Products and specifications discussed herein are for reference purposes only All informa tion discussed herein is provided an AS IS basis without warranties of any kind This document and all information discussed herein remain the sole and exclusive property of Samsung Electronics No license of any patent copyright mask work trademark or any other intellectual property right is granted by one party to the other party under this document by implication estoppel or otherwise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply For updates or additional information about Samsung products contact your nearest Samsung office All brand names trademarks and registered trademarks belong to their respective owners 2010 Samsung Electronics Co Ltd All rights reserved SAMSUNG ELECTRONICS IT Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication Samsung assu
89. SAMSUNG ELECTRONICS 4 4 en S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 1 ADCON A D Converter Control Register F7H Bitidentifier 7 6 5 4 3 2 3 o Preserves o o o o 9 od 7 4 A D Converter Input Pin Selection Bits ADCO POO o ofofpo ajaneeon o 10 0 1 abes Pod 0 1 0 0 op1ifo 1j AnespePosg o 0 1 1 0 o 1 4 1 0 7 0 lances 1 0 0 1 Connected with GND internally 1 0 1 0 Connected with GND internally 1 o 1 1 Connected with GND internally O 1 1 0 0 Connected with GND internally 1 1 0 4 Connected with GND internally 1 1 1 0 Connected with GND internally 3 End of Conversion Status Bit m A D conversion is in progress A D conversion is complete 2 1 Clock Source Selection Bit NOTE o foSc 16 OSC lt 10 MHz 0 1 fOSC 8 fOSC lt 10 MHz 0 103 4 fOSC lt 10 MHz fOSC 1 fOSC lt 4 MHz 0 Conversion Start Bit No effect A D conversion start NOTE Maximum ADC Clock Input 4 MHz SAMSUNG ELECTRONICS 4 5 S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 2 BTCON Basic Timer Control Register DCH Bit Identifier IL edt cdl eI dha io o o o 9 9 9 9 9 7 4 Watchdog Timer Function Enable Bit fi
90. Timer 0 interrupt pending bit 00 fosc 4096 0 interrupt pending when read 01 fosc 256 0 Clear TO pending bit when write 10 fosc 8 1 Interrupt is pending when read 11 fosc 1 No effect when write Timer 0 interrupt enable bit Not used for S3F94C8 F94C4 0 Disable TO interrupt 1 Enable TO interrupt Not used for S3F94C8 F94C4 Timer 0 counter clear bit 0 No effect 1 Clear the Timer 0 counter when write NOTE To use TO match output P2 0 TOCON3 must be set to 1 In this case there can be same delay in the timer operation In case time interval is very important make TOCON 3 0 Figure 10 4 Timer 0 Control Registers SAMSUNG ELECTRONICS 10 7 er S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 10 3 2 Timer 0 Function Description 10 3 2 1 Interval Timer Mode In interval timer mode match signal is generated when the counter value is identical to the value written to Timer 0 reference data register TODATA The match signal generates Timer 0 match interrupt TOINT vector and then clears the counter For example if you write the value 10H to TODATA the counter will increment until it reaches 10H At this point the Timer 0 interrupt request is generated the counter value is reset and counting is resumed TOCON 3 Counter TOCNT Timer 0 counter clear Comparator Data Register TODATA TOCON 1 Interrupt Enable
91. VR 2 3 V DB DB DB DB DI LD LD LD LD LD LD LD LD ORG 0100H lt lt Interrupt Vector Address gt gt RG 0000H ECTOR 94C4 S3F94C8 F94C4 has only one interrupt vector lt lt Smart Option gt gt 8 RESET AND POWER DOWN Programming Tip Sample S3F94C8 F94C4 Initialization Routine 03H 003FH internal RC 3 2 MHz in VDD lt lt Initialize System and Peripherals gt gt Disable Interrupt BTCON 10100011B Disable Watchdog CLKCON 0011000B Select non divided CPU clock SP 0COH Stack pointer must be set 01 01 POCONH 10101 POCONL 10101 P1CON 000010 P2CONH 0100101 H L P0 0 P0 7 PI 0 Pi 1 B B P2 0 P2 6 Cy c c Timer settings P2CONL 010101 0 A TODATA 50H CPU 3 2 TOCON 01001010B 08C 256 CP JP RO 0 RAM clear RO RO P ULE RAM CLR lt lt Initialize other registers gt gt SAMSUNG ELECTRONICS 8 9 push pull output push pull output push pull output MHz interrupt interval 6 4 msec Timer 0 interrupt enable lear all data registers from 00h to 5FH gt gt Enable interrupt S3F94C8 F94C4 UM REV 1 00 8 RESET AND POWER DOWN lt lt Main loop gt gt NOP Start Main Loop BTCON 02 Enable Watchdog Clear Basic Counter BTCNT ED DISPLAY
92. YM 3 to 1 This allows interrupts to be serviced as they occur If an interrupt s pending bit was set while interrupt processing was disabled by executing a DI instruction it will be serviced when you execute the El instruction No flags are affected Bytes Cycles Opcode Hex opc 1 4 If the SYM register contains the value 00H that is if interrupts are currently disabled the statement El sets the SYM register to 08H enabling all interrupts SYM 3 is the enable bit for global interrupt processing SAMSUNG ELECTRONICS 6 21 er S3F94C8 F94C4_UM_REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 12 IDLE Idle Operation IDLE Operation The IDLE instruction stops the CPU clock while allowing system clock oscillation to continue Idle mode can be released by an interrupt request IRQ or an external reset operation Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src opc 1 4 6F Example The instructions IDLE NOP NOP NOP Stop the CPU clock but not the system clock SAMSUNG ELECTRONICS 6 22 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 13 INC Increment INC dst Operation dst lt dst 1 The contents of the destination operand are incremented by one Flags C Unaffected 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is dst value is
93. a Memory with Long Offset S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES 3 1 9 Direct Address Mode In Direct Address DA mode the instruction provides the 5 16 bit memory address Jump JP and Call CALL instructions use this addressing mode to specify the 16 bit destination address loaded in the Program Counter PC whenever a JP or CALL instruction is executed The LDC and LDE instructions can use Direct Address mode to specify the source or destination address for Load operations to program memory LDC or external data memory LDE if implemented Program or Data Memory Program Memory Upper Address Byte Lower Address Byte LSB Selects Program 0 or 1 4 Memory or Data Memory OPCODE 0 Program Memory Data Memory Sample Instructions LDC R5 1234H The values in the program address 1234H are loaded into register R5 LDE R5 1234H Identical operation to LDC example except that external program memory is accessed Figure 3 10 Direct Addressing for Load Instructions SAMSUNG ELECTRONICS 3 10 er S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES 3 1 10 Direct Address Mode 1 Program Memory Next OPCODE Program Memory Address Used Lower Address Byte Upper Address Byte OPCODE Sample Instructions JP C JOB1 Where JOB1 is a 16 bit immediate address CALL DISPLAY Where DISPLAY is a 16 bit immediate address Figure 3 11 Direct Addressing for Call and Jump Instruction
94. ain P2CONH L CLO TO PO Data Output Disable input mode Input Data Circuit Type A NOTE pins have protection diodes through Vss Figure 9 8 Port 2 Circuit Diagram SAMSUNG ELECTRONICS 9 9 im S3F94C8 F94C4_UM_REV 1 00 9 PORTS Port 2 Control Register High Byte EAH R W 7 Not sued for S3F94C8 F94C4 6 4 Port 2 P2 6 ADC8 CLO Configuration Bits 000 Schmitt trigger input pull up enable 0 0 1 Schmitt trigger input 0 1 x ADC input 100 Push pull output 101 Open drain output pull up enable 110 Open drain output 1 1 1 Alternative function CLO output 3 2 Port 2 P2 5 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 P2 4 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output NOTE When noise problem is important issue you had better not use CLO output Figure 9 9 Port 2 Control Register P2CONH High Byte SAMSUNG ELECTRONICS 9 10 er S3F94C8 F94C4_UM_REV 1 00 11 0 PORTS Port 2 Control Register Low Byte EBH R W 7 6 Port 2 P2 3 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 5 4 Port 2 P2 2 Configuration Bits 0 0 Schmitt trigger input pull up enabl
95. amming WR_BYTE LD LD LD LD LD LD FMUSR 0A5H FMCON 01010000B FMS FMS R10 R11 ECH 03H ECL 00H R9 03 10 RR10 R9 FMUSR 00H Case2 Programming in the same sector WR_INSECTOR LD LD LD LD LD LD LD RO 40H 5 FMS R10 R11 USR 0A5H CON 01010000B ECH 06H ECL 00H R9 33H 06H GRR10 R9 R11 RO NZ FMUSR 00H WR BYT SAMSUNG ELECTRONICS Write data AAH to destination address 0310H Enable User program mode Select Programming mode Set the base address of sector 0300H Load data AA to write Load flash memory upper address into upper register of pair working register Load flash memory lower address into lower register of pair working register Write data AAH at flash memory location 0310H Disable User program mode RR10 Address copy R10 high address R1l1l low address Enable User program mode Select Programming mode and start programming Set the base address of sector located in target to write data The sector 12 s base address is 0600H Load data 33H to write Load flash memory upper address into upper register pair working register Load flash memory lower address into lower register of pair working register Write data 33H at flash memory location Reset address in the same sector by INC instruct
96. andalone Samsung OTP MTP FLASH Programmer for after service Small size and light for portable use Supports all Samsung OTP MTP FLASH devices Supports HEX file download via USB port from PC Fast program and verify time OTP 2Kbytes per second MTP 10Kbytes per second Internal large buffer memory 118M Bytes Driver software runs on various operating systems Windows 95 98 2000 XP Supports full functions of OTP MTP programmer Read Program Verify Blank and Protection Supplies two kinds of Power User system power or USB power adapter Supports Firmware upgrade SEMINIX Telephone 82 2 539 7891 Fax 82 2 539 7819 E mail sales seminix com URL http Awww seminix com Flash writing adapter board Special flash writing socket for S3F94C8 F94C4 Supports 20DIP 20SOP 20SSOP 16DIP 16SOP and 16TSSOP C amp A technology Telephone 82 2 2612 9027 Fax 82 2 2612 9044 E mail wisdom cnatech com URL http Awww cnatech com SAMSUNG ELECTRONICS 17 12
97. apped ADCom Register moon rm RW AD Convener Data Register High ADDATAH re x x x x x x x AID Converter Data Register Low ADDATAL m Locations FAH FFH Are Not Mapped NOTE 1 Not mapped or not used x Undefined 2 Theregister FTSTCON is not used Its value should always be 00H during normal operation SAMSUNG ELECTRONICS 4 3 xu S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS Bit number s that is are appended to the register name for bit addressing Name of individual Register Register address bit or related bits ID Register name hexadecimal FLAGS System Flags Register D5H Bit Identifier 7 RESET Value x x x x x x 0 0 Read Write R W R W R W R W R W R W R W R W Carry Flag C EN Operation does not generate a carry or borrow cdndition Operation generates carry out or borrow into high order bit 7 Zero Flag EN Operation result is a non zero value Operation result is zero Sign Flag EN Operation generates positive number MSB Operation generates negative number MSB Jr R Read only Description of the RESET value notation W Write only effect of specific 2 Not used R W Read write bit settings Undetermind value Not used 0 Logic zero ne Bit number MSB Bit 7 LSB Bit 0 Figure 4 1 Register Description Format
98. ata Register Format SAMSUNG ELECTRONICS 9 2 xu S3F94C8 F94C4_UM_REV 1 00 9 PORTS 9 1 2 Port 0 Port 0 is a bit programmable general purpose port You can select normal input or push pull output mode In addition you can configure a pull up resistor to individual pins using control register settings It is designed for high current functions such as LED direct drive Port O pins can also be used for alternative functions ADC input external interrupt input and PWM output Two control resisters are used to control Port 0 namely POCONH E6H and POCONL E7H You access port 0 directly by writing or reading the corresponding port data register PO EOH Pull up Pull up register Enable 50 kQ typical PWM PO Data Output Disable input mode Input Data External Interrupt Input To ADC NOTE pins have protection diodes Input Data through Vss Output Do Figure 9 2 Port 0 Circuit Diagram SAMSUNG ELECTRONICS 9 3 im S3F94C8 F94C4_UM_REV 1 00 9 PORTS Port 0 Control Register High Byte E6H R W 7 6 Port P0 7 ADC7 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 11 2 A D converter input ADC7 schmitt trigger input off 5 4 Port 0 PO 6 ADC6 PWM Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Alternative function PWM output 10 Push pull output 1
99. ations Chapter 3 Addressing Modes contains detailed descriptions of the addressing modes that are supported by the SSF8 series CPU Chapter 4 Control Registers contains overview tables for all mapped system and peripheral control register values as well as detailed one page descriptions in a standardized format You can use these easy to read alphabetically organized register descriptions as a quick reference source when writing programs Chapter 5 Interrupt Structure describes the S3F94C8 94CA interrupt structure in detail and further prepares you for additional information presented in the individual hardware module descriptions in Part Il Chapter 6 Instruction Set describes the features and conventions of the instruction set used for all S3F8 series microcontrollers Several summary tables are presented for orientation and reference Detailed descriptions of each instruction are presented in a standard format Each instruction description includes one or more practical examples of how to use the instruction when writing an application program SAMSUNG ELECTRONICS ex A basic familiarity with the information in Part will help you to understand the hardware module descriptions Part Il If you are not yet familiar with the S3F8 series microcontroller family and are reading this manual for the first time we recommend that you first read Chapters 1 3 carefully Then briefly look over the detailed information in Chapters
100. bit PWM 6 2 resolution 10 12 bit PWM 6 6 resolution 11 14 bit PWM 8 6 resolution Note Only one resolution mode can work at any time Figure 11 9 PWM Extension Register PWMEX PWMDATA MSB Base data 6 2 resolution Extension data for 6 2 resolution Base data for 6 6 resolution Base data for 8 6 resolution Figure 11 10 PWM Data Register PWMDATA SAMSUNG ELECTRONICS 11 11 uu S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION fOSC 8 fOSC fOSC 64 PWMCON 6 7 gt gt From extension bit up From base bit up counter counter extension bit base bit PWMCON O PWMCON 1 1 When base data gt Counter PWMCON 2 0 When data lt Counter bas bit Comparator P0 6 PWM 1 When data Counter base bit Data Extension Buffer Control Logic base bit PWM Data Register F2H FOH F2H FOH PWM Extension Data Register PWMCON 3 clear base or extension up counter overflow DATA BUS 7 0 Figure 11 11 PWM Module Functional Block Diagram SAMSUNG ELECTRONICS IP S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION Example 11 1 Programming Tip Programming the PWM Module to Sample Specifications lt lt Interrupt Vector Address gt gt ECTOR OOH INT_94C4 S3F94C8 F94C4 interrupt vector lt lt Smart Option gt gt RG 3CH OH OO3CH must be initialized to 1 OH 003DH must be initialized to
101. ce values remain unaffected LDC and LDE refer to program memory and data memory respectively The assembler changes or rr values to an even number for program memory and to an odd number for data memory No flags are affected dst o O opc opc opc src dst dst src src dst dst src src dst XS XS XLL XLL DAL x a I gt lt I gt T gt I src 0000 dst 0001 src 0001 DAL DAL DAL gt I DAH Cycles 10 10 12 12 14 14 14 14 14 14 Opcode Hex C3 D3 E7 F7 A7 7 A7 B7 A7 B7 The source src or working register pair rr for formats 5 and 6 cannot use register pair 0 1 For formats 3 and 4 the destination address XS rr and source address XS rr are one byte each Addr Mode dst src r Irr Irr r r XS rr XS rr r r XL rr XL rr r r DA DA r r DA DA r For formats 5 and 6 the destination address XL rr and the source address XL rr are two bytes each The DA and r source values for formats 7 and 8 address program memory the second set of values for formats 9 and 10 address data memory SAMSUNG ELECTRONICS 6 29 HIP S3F94C8 F94C4 UM REV 1 00 Examples 6 SAM88RCRI INSTRUCTION SET Given RO 11H R1 34H R2 01H R3 04H R4 00H R5 60H Program memory locations
102. chmitt trigger input pull up enable falling edge interrupt input 1 0 Push pull output 1 1 A D converter input ADCO schmitt trigger input off Figure 9 4 0 Control Register POCONL Low Byte S3F94C8 F94C4_UM_REV 1 00 9 PORTS Port 0 Interrupt Pending Register E8H R W 7 4 Not used for S3F94C8 F94CC 3 Port 0 1 ADC1 INT1 Interrupt Enable Bit 0 falling edge interrupt disable 1 falling edge interrupt enable 2 Port 0 1 ADC1 INT1 Interrupt Pending Bit 0 No interrupt pending when read Pending bit clear when write nterrupt is pending when read No effect when write 1 Port 0 0 ADCO INTO Interrupt Enable Bit 0 INTO falling edge interrupt disable 1 INTO falling edge interrupt enable 0 Port 0 0 ADCO INTO Interrupt Pending Bit 0 No interrupt pending when read 0 Pending bit clear when write 1 Interrupt is pending when read 1 No effect when write Figure 9 5 Port 0 Interrupt Pending Registers POPND SAMSUNG ELECTRONICS 9 6 im S3F94C8 F94C4_UM_REV 1 00 9 PORTS 9 1 3 Port 1 Port 1 is a 3 bit I O port with individually configurable pins It can be used for general I O port Schmitt trigger input mode push pull output mode or n channel open drain output mode In addition you can configure a pull up and pull down resistor to individual pin using control register settings It is designed for high current functions such as LED
103. cur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages expenses and reasonable attorney fees arising out of either directly or indirectly any claim of personal injury or death that may be associated with such unintended or unauthorized use even if such claim alleges that Samsung was negligent regarding the design or manufacture of said product All rights reserved No part of this publication may be reproduced stored in a retrieval system or transmitted in any form or by any means electric or mechanical by photocopying recording or otherwise without the prior written consent of Samsung Electronics Samsung Electronics Co Ltd San 24 Nongseo Dong Giheung Gu Yongin City Gyeonggi Do Korea 446 711 Contact Us younghee46 won samsung com TEL 82 31 209 3865 FAX 82 31 209 6494 Home Page http www samsungsemi com SAMSUNG ELECTRONICS Revision History Revision No Date Description Remark V0 0 Nov 2008 SAM8RC modified 8K Full flash ROM 208 Bytes RAM e Interrupt 1 vector 4 sources e 18 max PWM 1 channel resolution e Timer Basic timer and 8 bit timer 0 e ADC 10 bit x 9 channel e Operating voltage 1 8 2 7V 1 4MHz 2 7 5 5V 1
104. d Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 Format Bytes Cycles Opcode Addr Mode Hex dst src 6 53 r Ir src dst 3 6 54 R R 55 R IR dst src 3 6 56 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH AND R1 R2 gt Rl 02H R2 03H AND R2 gt 02H R2 03H AND 01H 02H gt Register 01 01H register 02H 03H AND 01H 02H gt Register 01 00H register 02H 03H AND 01H 25H gt Register 01H 21H In the first example destination working register R1 contains the value 12H and the source working register R2 contains 03H The statement AND R1 R2 logically ANDs the source operand 03H with the destination operand value 12H leaving the value 02H in register R1 SAMSUNG ELECTRONICS 6 13 en S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 4 CALL Call Procedure CALL dst Operation SP lt SP 1 SP lt PCL SP lt SP 1 SP lt lt dst The current contents of the program counter are pushed onto the top of the stack The program counter value used is the address of the first instruction following the CALL instruction The specified destination address is then loaded into the program counter and points to the first instruction of a procedure At the end of the procedure the return instruction RET can be used to return to th
105. d This will help you familiarize with the mapped locations in register file You can also use this description for quick reference while writing application programs Table 4 1 summarizes the system and peripheral registers In addition Figure 4 1 illustrates the important features of standard register description format Control register descriptions are arranged in alphabetical order according to register mnemonic For more information about control registers refer to the context of various peripheral hardware description in Part II of this manual SAMSUNG ELECTRONICS 4 1 xu S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS Table 4 1 System and Peripheral Control Registers RESET value Bit Register Name Location Address Rw 7 65 4 312 10 Timer 0 Control Register RW 00 0 00 Location Is Not Mapped Clock Control Register cikcon RW o olo System Flags Register osa aw x x x v Locations DGH D8H Are Not Mapped Location DAH Is Not Mapped MDS Special Register MDSREG DBH RW 0 Basic Timer Control Register BTCON RW Basic Timer Counter Test Mode Control Register FTSTCON DEH w 0 System Mode Register RW O 0
106. dexed addressing mode reg Rn reg 0 255 n 0 15 addr RRp addr range 128 to 127 where 0 2 14 addr RRp addr range 0 8191 where 0 2 14 da Direct addressing mode addr range 0 8191 addr addr number in the range 127 to 128 Relative addressing mode that is an offset relative to the address of the next instruction Immediate addressing mode data data 0 255 Indexed short offset addressing mode Indexed long offset addressing mode SAMSUNG ELECTRONICS 6 6 im S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET Table 6 5 Opcode Quick Reference OPCODE MAP md NIBBLE BORNE EM mu NEM Nm NM EM R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM 1 RLC RLC ADC ADC ADC ADC ADC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM 2 INC INC SUB SUB SUB SUB SUB R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM 3 JP SBC SBC SBC SBC SBC IRR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM 4 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM 5 POP POP AND AND AND AND AND R1 IR1 r1 r2 ri lr2 R2 R1 IR2 R1 R1 IM COM COM TCM TCM TCM TCM TCM R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM PUSH PUSH TM TM TM R2 IR2 r1 r2 j R2 R1 IR2 R1 Bd iid LD x r2 RL RL LD R1 IR1 PN A CP CP CP CP CP LDC r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r1 Irr2 xL CLR CLR XOR XOR XOR XOR XOR LDC R1 IR1 r1 r2 r1 Ir2 R2 R1 IR2 R1 R1 IM r2 Irr2 xL C RRC RRC LDC LD R1 IR1 r1 lrr2 r1 Ir2 SRA SRA LDC LD LD R1 IR1 Irri
107. ding Input pi when writing 1 S i E Input and push pull output port can be assigned 19 20 pin S Poo Sex 15 16 EN dk Power supply for entering Tool mode V indicates that MTP enters into the Tool pe mode When 11 V is applied MTP is in the Tool mode 20 ps 16 pin Vpp V Vpp V 20 5 16 20 EN NOTE Parentheses indicate pin number for 20 DIP 300A package Table 16 2 Comparison of S3F94C8 F94C4 Features Program memory memory 8K 4K byte Flash ROM Operating voltage Vpp 2 0 V to 5 5 V Flash MCU programming mode Vpp 5 0 V Vpp nRESET 11 V 20 DIP 20 SOP 20 SSOP 16SOP 16TSSOP Programmability User program multi time SAMSUNG ELECTRONICS 16 3 im S3F94C8 F94C4_UM_REV 1 00 16 S3F94C8 F94C4 FLASH 16 2 On Board Writing S3F94C8 F94C4 needs only five signal lines including VDD and GND pins for writing internal flash memory with serial protocol Therefore on board writing is possible if the writing signal lines are considered during design of the PCB of application board 16 2 1 Circuit Design Guide At the flash writing the writing tool needs five signal lines including GND VDD VPP SDAT and SCLK When you design the PCB circuit consider the usage of these signal lines for on board writing In case of VPP nRESET pin a capacitor should be inserted between the VPP pin and GND to increase the noise effect
108. ds Flags C Set if a borrow occurred src gt dst cleared otherwise 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurs that is if the operands were of opposite sign and the sign of result is the same as the sign of source cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 2 4 32 root 6 33 r Ir src dst 3 6 34 R R 35 R IR opc dst src 3 6 36 R IM Examples Given R1 10H R2 03H 1 register 01H 20H register 02H 03H and register 03H OAH SBC R1 R2 gt Rl OCH R2 03H SBC R2 05H R2 03H register 03H OAH SBC 01H 02H Register 01H 1CH register 02H 03H SBC 01H 02H gt Register 01H 15H register 02H 03H register 03H SBC 01H 8AH gt Register 01H 95H C S and V 1 In the first example if working register R1 contains the value 10H and register R2 the value 03H the statement SBC R1 R2 subtracts the source value 03H and C flag value 1 from the destination 10H and then stores the result OCH in register R1 SAMSUNG ELECTRONICS 6 44 en S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 32 SCF Set Carry Flag SCF Operation 1 The is set to logic one regardless of its previous value Flags C Set to 1 No other flags are affected Format Bytes Cycles Opcode Hex opc 1 4
109. e 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 3 2 Port 2 P2 1 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 1 1 Open drain output 1 0 Port 2 P2 0 Configuration Bits 0 0 Schmitt trigger input pull up enable 0 1 Schmitt trigger input 1 0 Push pull output 11 TO match output Figure 9 10 Port 2 Control Register P2CONL Low Byte SAMSUNG ELECTRONICS 9 1 uu S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 BASIC TIMER AND TIMER 0 10 1 Overview of Basic Timer and Timer 0 S3F94C8 F94C4 has two default timers 8 bit basic timer An 8 bit general purpose timer counter called timer 0 10 1 1 Basic Timer You can use the basic timer BT in two different ways e Asa watchdog timer To provide an automatic Reset mechanism in the event of system malfunction e To signal the end of required oscillation stabilization interval after a Reset or Stop mode release The functional components of basic timer block are e Clock frequency divider fOSC divided by 4096 1024 or 128 with multiplexer 8 bit basic timer counter DDH read only Basic timer control register BTCON DCH read write 10 1 2 Timer 0 Timer 0 has the following functional components e Clock frequency divider fOSC divided by 4096 256 8 or fOSC with multiplexer 8 bit counter TOCNT 8 bit comparat
110. e Addr Mode Hex dst dst 2 4 00 R 01 IR Examples Given R1 03H and register 03H 10H DEC R1 gt 02H DEC R1 gt Register 03H OFH In the first example if working register R1 contains the value 03H the statement DEC R1 decrements the hexadecimal value by one leaving the value 02H In the second example the statement DEC R1 decrements the value 10H contained in the destination register 03H by one leaving the value OFH SAMSUNG ELECTRONICS 6 19 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 10 DI Disable Interrupts DI Operation Flags Format Example Given SYM 08H DI SYM 3 lt 0 Bit zero of the system mode register SYM 3 is cleared to 0 globally disabling all interrupt processing Interrupt requests will continue to set their respective interrupt pending bits but the CPU will not service them while interrupt processing is disabled No flags are affected Bytes Cycles Opcode Hex opc 1 4 8F If the value of the SYM register is 08H the statement DI leaves the new value 00H in the register and clears SYM 3 to 0 disabling interrupt processing SAMSUNG ELECTRONICS 6 20 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 11 El Enable Interrupts Operation Flags Format Example Given SYM OOH SYM 3 lt 1 An instruction sets bit 2 of the system mode register S
111. e input pins in ADC module are alternatively used as digital input in port 0 and P2 6 12 1 2 A D Converter Control Register ADCON The A D converter control register ADCON is located at address F7H It has four functions Bits 7 4 select an analog input pin ADCO ADCS Bit 3 indicates the status of A D conversion Bits 2 1 select the conversion speed Bit 0 starts the A D conversion Only one analog input channel can be selected at a time You can dynamically select any one of the nine analog input pins ADCO ADC8 by manipulating the 4 bit value for ADCON 7 ADCON 4 A D Converter Control Register ADCON F7H R W A D Conversion input pin selection bits Conversion start bit 0 No effect 1 A D conversion start 0000 ADC 0 0001 ADC 1 0010 ADC 2 0011 3 P0 0 1 P0 2 P0 3 Conversion speed selection bits Mote 00 foso 16 fosc lt 10 MHz 01 fog 8 fasc lt 10 MHz 10 fosc 4 fosc lt 10 MHz 11 foso 1 foso lt 4MHz 0101 ADC 5 0110 ADC 6 0111 ADC 7 P0 7 1000 ADC 8 P2 6 1001 ig Connect to GND internally 1111 P0 5 P0 6 P0 0 P0 1 P0 2 P0 3 0100 4 P0 4 5 P0 6 P0 7 P2 6 End of conversion EOC status bit 0 A D conversion is in progress 1 A D conversion complete NOTE 1 Maximum ADC clock input 4MHz Figure 12 1 A D Converter Control Register ADCON SAMSUNG ELECTRONICS 12 2 xu S3F94C8 F94C4 UM REV 1 00
112. e original program flow RET pops the top of the stack back into the program counter Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 3 14 F6 DA opc dst 2 12 F4 IRR Examples Given RO 15H R1 21H 1A47H and SP 0B2H CALL 1521H gt 0BOH Memory locations 00H 01H 4AH where is the address that follows the instruction CALL RRO gt SP 0BOH 00H 1AH 01H 49H In the first example if the program counter s value is 1A47H and the stack pointer contains the value 0B2H the statement CALL 1521 pushes the current program counter s value onto the top of the stack The stack pointer now points to the memory location 00H The program counter is then loaded with the value 1521H which specifies the address of the first instruction in the program sequence to be executed If the contents of the program counter and stack pointer are the same as in the first example the statement CALL RRO produces the same result except that 49H is stored in stack location 01H because two byte instruction format was used The program counter is then loaded with the value 1521H which specifies the address of the first instruction in the program sequence to be executed SAMSUNG ELECTRONICS 6 14 xu S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 5 CCF Complement Carry Flag CCF Operation Flags Format Example C lt NOT C T
113. e register pair OOH and 01H leaving the value 0120H SAMSUNG ELECTRONICS 6 25 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 16 JR Jump Relative JR cc dst Operation If true PC lt PC dst If the condition specified by the condition code cc is true the relative address is added to the program counter and control passes to the statement whose address is now in the program counter otherwise the instruction following the JR instruction is executed See the list of condition codes The range of relative address is 127 to 128 The original value of the program counter specifies the address of first instruction byte following the JR statement Flags No flags are affected Format Bytes Cycles Opcode Addr Mode NOTE Hex dst cc dst 2 6 ccB RA cc 0to F NOTE In the first byte of the two byte instruction format the condition code and op code are four bits each Example Given The carry flag 1 and LABEL_X 1FF7H JR C LABEL_X gt 1FF7H If the carry is set that is if the condition code is true the statement JR C LABEL X will pass control to the statement whose address is now in the PC Otherwise the program instruction following the JR will be executed SAMSUNG ELECTRONICS 6 26 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 17 LD Load LD dst src Operation dst lt SIC The contents of source are loaded into t
114. e the current status of CPU operations Four of these eight bits FLAGS 4 FLAGS 7 can be tested and used with conditional jump instructions FLAGS register can be set or reset by instructions as long as its outcome does not affect the flags such as Load instruction Logical and Arithmetic instructions such as AND OR XOR ADD and SUB can affect the FLAGS register For example the AND instruction updates the Zero Sign and Overflow flags based on the outcome of the AND instruction If the AND instruction uses the FLAGS register as the destination then two write will occur simultaneously to the FLAGS register producing an unpredictable result System Flags Register FLAGS D5H R W Carry flag C 4 Not mapped Zero 7 Sign flag S Overflow flag V Figure 6 1 System Flags Register FLAGS 6 1 4 Flag Descriptions 6 1 4 1 Overflow Flag FLAGS 4 The V flag is set to 1 when the result of a two s complement operation is greater than 127 or less than 128 This flag is cleared to 0 following logic operations 6 1 4 2 Sign Flag FLAGS 5 S The sign bit identifies the state of MSB of the result following arithmetic logic rotate or shift operations A logic zero indicates a positive number and a logic one indicates a negative number 6 1 4 3 Zero Flag FLAGS 6 Z For arithmetic and logic operations the Z flag is set to 1 if the result of the operation is zero For operations that test register
115. ential linearity error Offset error of top Offset error of bottom Conversion time 1 Analog input voltage Analog input impedance NOTE 1 Conversion time is the time required from the moment a conversion operation starts until it ends 2 lapc specifies the operating current during A D conversion 3 fosc specifies the main oscillator clock SAMSUNG ELECTRONICS 14 8 xu S3F94C8 F94C4 UM REV 1 00 14 MECHANICAL DATA Table 14 10 LVR Circuit Characteristics 40 C to 85 C Vpp 1 8V to 5 5V 1 9 2 0 V Low voltage reset 1 8 V LVR MAX V LVR MIN Figure 14 5 LVR Reset Timing Table 14 11 Flash Memory AC Electrical characteristics TA 40 to 85 at Vpp 1 8 V to 5 5 V Parameter Symbol Conditions Min Typ Max Unit NOTE 1 The programming time specifies the time during which one byte 8 bit is programmed 2 The Chip erasing time specifies the time during which the entire program memory is erased 3 The Sector erasing time specifies the time during which all the 128 byte blocks are erased 4 The chip erasing is available in Tool Program Mode only SAMSUNG ELECTRONICS 14 9 er S3F94C8 F94C4 UM REV 1 00 14 MECHANICAL DATA S3F94C8 F94C4 Figure 14 6 Circuit Diagram to Improve EFT Characteristics NOTE To improve the EFT characteristics it is recommended to use the power capacitor near S3F94C8 F94C4 as shown in Fiqure 14 6 Table 14 12 ESD Characteristics
116. erflow occurs that is if the sign of destination changes during rotation cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 CO R 4 C1 IR Examples Given Register 55H register 01H 02H register 02H 17H and 0 RRC gt Register 2AH 1 RRC 01 gt Register 01 02H register 02H OBH 1 In the first example if general register OOH contains the value 55H 01010101B the statement RRC rotates this value one bit position to the right The initial value of bit zero 1 replaces the carry flag and the initial value of C flag 1 replaces bit 7 This leaves the new value 2AH 00101010B in destination register 00H Both sign flag and overflow flag are cleared to 0 SAMSUNG ELECTRONICS 6 43 en S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 31 SBC Subtract With Carry SBC dst src Operation dst lt dst src c The source operand along with the current value of carry flag is subtracted from the destination operand and the result is stored in the destination The contents of source remain unaffected Subtraction is performed by adding the two s complement of source operand to the destination operand In multiple precision arithmetic this instruction permits the carry borrow from the subtraction of the low order operands to be subtracted from the subtraction of high order operan
117. errupt 1 Enables interrupt PWM Overflow Interrupt Pending Bit No interrupt is pending when read E Clears pending bit when write Interrupt is pending when read No effect when write 1 PWMCON 3 is not auto cleared You must pay attention when clearing pending bit Refer to pages 11 12 for more information 2 PWMCON 5 should always be set to 0 SAMSUNG ELECTRONICS 4 17 IP S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 16 PWMEX PWM Extension Register F1H 7 6 5 4 3 2 a o REETVle o o o o o o o o RW RW RW RW RW RW RW RW 7 2 PWM Extension Bits PWM extension bits for 6 6 resolution and 8 6 resolution not used in 6 2 resolution 1 0 PWM Base extension Control bits ENES 1 Base 6 bit PWMDATA1 5 0 Extension 6 bit PWMEX 7 2 1 Base 8 bit PWMDATAt 7 0 Extension 6 bit PWMEX 7 2 SAMSUNG ELECTRONICS 4 18 er S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 17 STOPCON STOP Mode Control Register E4H Bit Identifier La ot oe I So Preset vaue o o o o o 9 9 7 0 Watchdog Timer Function Enable Bit 10100101 Enables STOP instruction Other value Disables STOP instruction NOTE When STOPCON register does not have 0A5H value and you use STOP instruction program counter PC is changed to reset address 4 1 18 SYM System Mode Register D
118. es Title Page Number Block Diagram of 3794 8 94 8 sse 1 3 Pin Assignment Diagram 20 Pin DIP SOP SSOP Package 1 4 Pin Assignment Diagram 16 Pin SOP TSSOP 1 5 Pin Circuit E M n 1 8 Piri Circuit Type de NER 1 8 Pin Circuit Type ds 1 8 PIn Gireult a 1 9 Pin Circuit Type E 1 9 Pin Circuit Type E 1 nep rea 1 10 Pin Circuit Type E 2 P1 0 P1 1 1 10 Program Memory Address 2 2 Smart Option argeste 2 3 Internal Register File Organization 2 6 16 Register m 2 7 Stack Operations mee SEEE 2 8 Register Addressing Siriei ten 3 2 Working Register Addressing 3 2 Indirect Register Addressing to Register File 3 3 Indirect Register Addressing to Program
119. ess Figure 3 1 Program Memory joe Working Register dst src OPCODE a Point to the working register Two Operand 1 of 16 Instruction Example Sample Instruction ADD R1 R2 working register area Figure 3 2 SAMSUNG ELECTRONICS 3 2 Register Addressing Register File OPERAND Where R1 and R2 are registers in the currently selected Working Register Addressing S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES 3 1 2 Indirect Register Addressing Mode In Indirect Register IR Addressing mode the contents of specified register or register pair include the address of the operand Depending on the instruction used the actual address may point to a register in the register file to program memory ROM or to an external memory space see Figure 3 3 Figure 3 6 You can use any 8 bit register to indirectly address another register Any 16 bit register pair can be used to indirectly address another memory location Program Memory Register File 8 bit Register File Address dst gt ADDRESS Point to One SPEDE Register in Register One Operand File Instruction Example Address of Operand used by Instruction Value used in OPERAND Instruction Execution Sample Instruction RL SHIFT Where SHIFT is the label of an 8 bit register address Figure 3 3 Indirect Register Addressing to Register File SAMSUNG ELECTRONICS 3 3 im S3F94C8 F94C4_UM_REV 1 00 3 1 3 Indirect
120. ged to Os and vice versa Flags C Unaffected 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 60 R 4 61 IR Examples Given R1 07H and register 07H OF 1H COM 1 gt R1 OF8H COM R1 gt 07H register 07H In the first example destination working register R1 contains the value 07H 00000111B The statement COM R1 complements all the bits in R1 All logic ones are changed to logic zeros and vice versa leaving the value OF8H 11111000B In the second example Indirect Register IR addressing mode is used to complement the value of destination register 07H 11110001B leaving the new value OEH 00001 110B SAMSUNG ELECTRONICS 6 17 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 8 CP Compare dst src Operation dst src The source operand is compared to subtracted from the destination operand and the appropriate flags are set accordingly The contents of both operands are unaffected by the comparison Flags C Set if a borrow occurred src dst cleared otherwise 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and the sign of the result is the same as the sign of
121. get board Marketing layout required e Delete 16 pin DIP package type Chap 1 15 e Change minimum operating frequency to 0 4MHz e Before 1 10MHz Now 0 4 10MHz e Add contents about external reset circuit e Add Notes about the unused bits of FLAGs register SAMSUNG ELECTRONICS eq Revision No Date Description Remark e ADC example contents refine e Electrical parameter ADC operating current 3 0V confirmed Typ 0 15mA max 0 45mA e Change Flash Endurance to 100 000 times YFH CHT Original 10 000 times V0 7 Sep 29 2009 P1 2 Pull down resistor related contents changed e P1 2 is VPP pin it added has intrinsic Electrical data ILIH1 ILIH2 changed internal pull down ILIH1 condition All input ports except ILIH2 resistor about and P1 2 300Kohm ILIH2 Xin delete Xout because it s output e It s different with ILIL2 Xin delete Xout because it s output 9454 And note below the table to describe the pull The pull down down resistor of P1 2 resistor has been Add note in chapter 09 notice customer to pay changed from attention to the pull down resistor of P1 2 100Kohm to Add note in chapter 01 notice that P1 2 have 300Kohm in Main intrinsic pull down resistor chip e Spec will be updated and confirmed after test main chip Oct 19 2009 e Change Flash Endurance to 10 000 times CHT Chapter 1 13 14 Original 100 000 times Reason Accordi
122. gure 13 4 Flash Memory Sector Address Register FMSECL SAMSUNG ELECTRONICS 13 4 er S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 3 Sector Erase You can erase a flash memory partially by using sector erase function only in user program mode The unit of flash memory that can be erased in the user program mode is a sector The program memory of S3F94C8 F94C4 8K AKbytes flash memory is divided into 64 32 sectors Every sector has 128 bytes size in all Therefore the sector to be located in destination address should be erased first to program a new data one byte into flash memory Minimum 4ms delay time for the erase is required after setting the sector address and triggering erase start bit FMCON 0 Sector erase is not supported in tool program modes MDS mode tool or programming tool 1FFFH S3F94C8 Sector 63 128 byte 1F7FH OFFFH S3F94C4 0F7FH Sector 0 128 byte Figure 13 5 Sector configurations in User Program Mode SAMSUNG ELECTRONICS 13 5 im S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 3 1 The Sector Erase Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Sector Address Register FMSECH and FMSECL 3 Set Flash Memory Control Register FMCON to 10100001B 4 Set Flash Memory User Programming Enable Register FMUSR to 00000000B FMUSR lt 0A5H User Programimg Mode Enable
123. he bit is then cleared automatically to 0 Figure 10 1 Basic Timer Control Register BTCON SAMSUNG ELECTRONICS 10 2 S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 10 2 2 Basic Timer Function 10 2 2 1 Watchdog Timer Function You can program the basic timer overflow signal BTOVF to generate Reset by setting BTCON 7 BTCON 4 to any value other than 1010B The 1010B value disables the watchdog function Reset clears BTCON to enabling the watchdog timer function automatically A Reset also selects the oscillator clock divided by 4096 as the BT clock A Reset is generated whenever a basic timer counter overflow occurs During normal operation the application program must prevent the overflow and accompanying reset operation from occurring To do this the value must be cleared by writing a 1 to BTCON 1 at regular intervals If a system malfunction occurs due to circuit noise or some other error condition the BT counter clear operation will not be executed and a basic timer overflow will occur initiating a Reset In other words during normal operation the basic timer overflow loop a bit 7 overflow of the 8 bit basic timer counter is always broken by a BTCNT clear instruction If a malfunction occurs a Reset is triggered automatically 10 2 2 2 Oscillation Stabilization Interval Timer Function You can use the basic timer to program a specific oscillation stabi
124. he carry flag C is complemented If C 1 the value of the carry flag is changed to logic zero On the other hand if 0 the value of the carry flag is changed to logic one C Complemented No other flags are affected Bytes Cycles Opcode Hex opc 1 4 EF Given the carry flag 0 CCF If the carry flag 0 the CCF instruction complements it in the FLAGS register OD5H changing its value from logic zero to logic one SAMSUNG ELECTRONICS 6 15 er S3F94C8 F94C4 UM REV 1 00 6 1 7 6 CLR Clear CLR dst Operation dst 0 The destination location is cleared to 0 Flags No flags are affected Format Bytes dst 2 Examples Given Register 4FH register 01H 02H and register 02H Register OOH CLR 00H CLR O1H gt Register 01H 02H register 02H 6 SAM88RCRI INSTRUCTION SET Cycles Opcode Addr Mode Hex dst 4 BO R 4 B1 IR 00H In Register R addressing mode the statement CLR 00H clears the destination register 00H value to 00H In the second example the statement CLR 901H uses Indirect Register IR addressing mode to clear the 02H register value to OOH SAMSUNG ELECTRONICS 6 16 S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 7 COM Complement COM dst Operation dst lt NOT dst The contents of the destination location are complemented one s complement all 1s are chan
125. he destination The source contents remain unaffected Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src dst opc src 2 4 rC r IM 4 r8 r R src opc dst 2 4 r9 R r r OtoF dst src 2 4 C7 Ir 4 D7 Ir r src dst 3 E4 R R E5 R IR opc dst src 3 6 E6 R IM D6 IR IM opc src dst 3 6 F5 IR R opc dst src 3 6 87 r x r opc 5 dst 3 6 97 x r r SAMSUNG ELECTRONICS 6 27 I S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET Examples Given RO 01H 1 OAH register OOH 01H register 01H 20H register 02 02H LOOP 30H and register 3AH OFFH LD LD LD LD LD LD LD LD LD 0 10H 0 01H 1H RO 1 RO RO RI O1H 2H G00H 0AH OOH 10H LD 00H 02H LD 0 LOOP R1 LD LOOP 80 R1 RO 10H RO 20H register 01H ter 01H RO R1 20H RO 01H ter 00 ter 02 ter 00 ter 00 ter 00 OFFH ter 31 H regis H regis regis regis regis register 02H 02H U Gc ooo c3 ost vri ii LLI iL POO PH RO SAMSUNG ELECTRONICS 6 28 er S3F94C8 F94C4 UM REV 1 00 6 1 7 18 LDC LDE Load Memory LDC LDE Operation Flags Format NOTE 1 2 3 4 10 dst src dst lt sic 6 SAM88RCRI INSTRUCTION SET This instruction loads a byte from program or data memory into a working register or vice versa The sour
126. ime interval modes A D Converter e Nine analog input pins MAX e 10 bit conversion resolution Oscillation Frequency e 0 4 MHz to 10 MHz external crystal oscillator Typical 4MHz external RC oscillator e Internal RC 3 2 MHz typ 0 5 MHz typ in VDD 5V Built in RESET Circuit LVR e Low Voltage check to make system reset 1 9 2 3 3 0 3 6 3 9 V by smart option Smart Option e LVR enable disable e Oscillator selection Operating Temperature Range 40 to 85 C Operating Voltage Range e 1 8V to 5 5 V 0 4 AM Hz LVR disable LVR to 5 5V 0 4 AM Hz LVR enable e 2 7V to 5 5V 0 4 10M Hz Package Types S3F94C8 F94C4 20 DIP 300A 20 SOP 375 20 SSOP 225 16 SOP 225 e 16 TSSOP 0044 Internal RC Operating Temp Range Internal RC Temp Range S3F94C8EZZ F94C4EZZ S3F94C8XZZ F94C4XZZ 40 C to 85 C 25 C to 85 C 3 5 25 4 1 5 25 SAMSUNG ELECTRONICS 40 C to 85 C 40 C to 85 C 1 2 S3F94C8 F94C4_UM_REV 1 00 1 OVERVIEW OF S3F94C8 94C4 1 3 Block Diagram of S3F94C8 94C8 P0 0 ADCO INTO P0 1 ADC1 INT1 P0 2 ADC2 Port and P0 3 ADC3 Interrupt Control P0 7 ADC7 Timer 0 SAM88RCRI CPU ADCO ADC8 gt P2 0 TO P2 1 208 Byte 4 8 KB ROM Regi Fil eg
127. in functions Figure 16 1 and Figure 16 2 show the pin assignments of S3F94C8 F94C4 package types NOTE 1 This chapter is about the Tool Program Mode of Flash MCU If you want to know about User Program Mode refer to the Chapter 13 Embedded Flash Memory Interface 2 In S3F94C8 F94C4 only five pins are used as flash operation pins The nRESET pin is used as VPP input and without TEST pin that different with other Samsung MCU products SAMSUNG ELECTRONICS 16 1 er S3F94C8 F94C4_UM_REV 1 00 16 S3F94C8 F94C4 FLASH Vss Voo 1 0 P0 0 ADCO INTO SCLK Xour P1 1 P0 1 ADC1 INT1 SDAT Vpp NRESET P1 2 P0 2 ADC2 S3F94C8 F94C4 TO P2 0 P0 3 ADC3 P2 1 20 DIP 300A P0 4 ADC4 20 SOP 37 P2 2 5 5 P0 6 ADC6 PWM P0 7 ADC7 P2 6 ADC8 CLO NOTE The bolds indicate MTP pin name Figure 16 1 S3F94C8 F94C4 Pin Assignments 20 DIP 20SOP Ves 16 I V X P1 0 4 15 PO 0 ADCO INTO SCLK Xg P1 1 C3 S3F94C8 F94C4 P0 1 ADC1 INT1 SDAT Vap NRESET P1 2 16 SOP 225 P0 2 ADC2 TO P2 0 O P0 3 ADC3 P2 1 EI P0 4 ADC4 P2 2 BL P0 5 ADC5 P2 3 Cj P0 6 ADC6 PWM NOTE bolds indicate MTP pin name Figure 16 2 S3F94C8 F94C4 Pin Assignments 16SOP SAMSUNG ELECTRONICS 16 2 er S3F94C8 F94C4_UM_REV 1 00 16 S3F94C8 F94C4 FLASH MCU Table 16 1 Descriptions of Pins Used to Read Write the EPROM Main Chip During Programming Serial data pin output when rea
128. into R8 and RR6 is decremented by one R8 OCDH R6 10H R7 32H RR6 lt RR6 1 R8 RR6 ODDH contents of data memory location 1033H is loaded into R8 and RR6 is decremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 32H SAMSUNG ELECTRONICS 6 32 en S3F94C8 F94C4_UM_REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 20 LDCI LDEI Load Memory and Increment LDCI LDEI dst src Operation dst rr lt src r These instructions are used for user stacks or block transfers of data from program or data memory to the register file A working register pair specifies the address of the memory location The contents of the source location are loaded into the destination location The memory address is then incremented automatically The contents of source remain unaffected LDCI and LDEI refer to program memory and external data memory respectively The assembler changes to even for program memory and to odd for data memory Flags No flags are affected Format Bytes Cycles Opcode Addr Mode Hex dst src Examples Given R6 10H R7 33H R8 12H program memory locations 1033H OCDH and 1034 0C5H external data memory locations 1033H ODDH and 1034H OD5H LDCI R8 RR6 OCDH contents of program memory location 1033H is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 OCDH R6 10H R7 34H R8 RR6 ODDH contents of data memory location 1033H
129. ion Check whether th nd address for programming reaches 0640H Disable User Program mode 13 11 er S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE Case3 Programming to the flash memory space located in other sectors ECTOR2 0 40H 1 40H USR 0A5H Enable User program mode CON 01010000B Select programming mode and start programming SECH 01H Set the base address of sector located in target address to write data FMSECL 4 00H The sector 2 s base address is 100H 9 0 Load data CCH to write R10 01H Load flash memory upper address into upper register of pair working register R11 40H Load flash memory lower address into lower register of pair working register WR BYT LD RO 40 ECTORS LD FMSECH Set the base address of sector located in target address to write data LD ECL The sector 5 s base address is 0280H LD 55 Load data 55H to write LD R10 02 Load flash memory upper address into upper register of pair working register R11 90 Load flash memory lower address into lower register of pair working register CALL WR_BYT WR INSECTOR12 LD FMSECH Set the base address of sector located target address to write data LD FMSECL The sector 12 s base address is 0600H LD R9 043 Load data A3H to write LD R10 06 Load flash memory upper address into upper register of
130. ion If cc is true PC lt dst The conditional JUMP instruction transfers program control to the destination address if the condition specified by the condition code cc is true otherwise the instruction following the JP instruction is executed The unconditional JP replaces the contents of the PC with the contents of the specified register pair Then the control passes to the statement addressed by the PC Flags No flags are affected Format 1 Bytes Cycles Opcode Addr Mode 2 Hex dst cc dst 3 8 ccD DA cc Oto F opc dst 2 8 30 IRR NOTE 1 3 byte format is used for a conditional jump and 2 byte format for an unconditional jump 2 Inthe first byte of the three byte instruction format conditional jump the condition code and the op code are both four bits Examples Given The carry flag C 1 register 00 01H and register 01 20H JP C LABEL W gt LABEL_W 1000H 1000H JP 00H gt PC 0120H The first example shows a conditional JP Assuming that the carry flag is set to 1 the statement UP C LABEL_W replaces the contents of the program counter with the value 1000H and transfers control to that location If the carry flag had not been set then the control would have passed to the statement immediately following the JP instruction The second example shows an unconditional JP The statement JP 00 replaces the contents of the program counter with the contents of th
131. is loaded into R8 and RR6 is incremented by one RR6 lt RR6 1 R8 ODDH R6 10H R7 34H SAMSUNG ELECTRONICS 6 33 ux S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 21 NOP No Operation NOP Operation When the CPU executes this instruction no action is performed Typically one or more NOPs are executed in sequence to affect a timing delay of variable duration Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 4 FF Example When the instruction NOP is encountered in a program no operation occurs Instead there is a delay in instruction execution time SAMSUNG ELECTRONICS 6 34 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 22 OR Logical OR OR dst src Operation dst lt dst OR src The source operand is logically ORed with destination operand Its result is stored in destination The contents of source remain unaffected The OR operation results in a 1 being stored whenever either of the corresponding bits in the two operands is a 1 otherwise 0 is stored Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always cleared to 0 Format Bytes Cycles Opcode Addr Mode Hex dst src 6 43 r Ir src dst 3 6 44 R R 45 R IR dst src 3 6 46 R IM Examples Given RO 15H R1 2AH R2 01H register OOH 08H register 01H 37
132. is set cleared otherwise V Set if arithmetic overflow occurs that is if the sign of destination changed during rotation cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 EO 1 IR Examples Given Register 00H 31H register 01H 02H and register 02H 17H RR 00H Register 00H 98H C I RR Q01H gt Register 01 02H register 02H 8BH 1 In the first example if general register contains the value 31H 00110001B the statement RR rotates this value one bit position to the right The initial value of bit zero is moved to bit 7 leaving the new value 98H 10011000B in the destination register The initial bit zero also resets the C flag to 1 and the sign flag and overflow flag are set to 1 SAMSUNG ELECTRONICS 6 42 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 30 RRC Rotate Right Through Carry RRC dst Operation dst 7 lt dst 0 dst lt dst 1 n 0 6 The contents of destination operand and carry flag are rotated right one bit position The initial value of bit zero LSB replaces the carry flag the initial value of carry flag replaces bit 7 MSB 7 0 Flags C Set if the bit rotated from the least significant bit position bit zero was 1 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic ov
133. ister File gt P2 6 ADC8 CLO P0 6 PWM NOTE 1 P1 2 is used as input only 2 IVC Internal Voltage Converte is not configurable Figure 1 1 Block Diagram of S3F94C8 94C8 SAMSUNG ELECTRONICS 1 3 xu S3F94C8 F94C4 UM REV 1 00 1 OVERVIEW OF S3F94C8 94C4 1 4 Pin Assignments Vss VDD XIN P1 0 P0 0 ADCO INTO SCLK XouT P1 1 PO 1 ADC1 INT1 SDAT VPP nRESET P1 2 P0 2 ADC2 TO P2 0 S3F94C8 F94C4 P0 3 ADC3 P2 1 20 DIP 300A P0 4 ADC4 20 SOP 375 P2 2 20 SSOP 225 P0 5 ADC5 P2 3 P0 6 ADC6 PWM P2 4 P0 7 ADC7 P2 5 P2 6 ADC8 CLO Figure 1 2 Pin Assignment Diagram 20 Pin DIP SOP SSOP Package SAMSUNG ELECTRONICS 1 4 er S3F94C8 F94C4_UM_REV 1 00 Vss XIN P1 0 XOUT P1 1 VPP nRESET P1 2 TO P2 0 P2 1 P2 2 P2 3 Figure 1 3 SAMSUNG ELECTRONICS S3F94C8 F94C4 16 SOP 225 16 TSSOP 0044 1 OVERVIEW OF S3F94C8 94C4 VDD P0 0 ADCO INTO SCLK P0 1 ADC1 INT1 SDAT P0 2 ADC2 P0 3 ADC3 P0 4 ADC4 P0 5 ADC5 P0 6 ADC6 PWM Pin Assignment Diagram 16 Pin SOP TSSOP Package 1 5 S3F94C8 F94C4_UM_REV 1 00 1 OVERVIEW OF S3F94C8 94C4 1 5 Pin Descriptions Table 1 1 S3F94C8 F94C4 Pin Descriptions Input P0 0 P0 7 I O Bit programmable port for Schmitt trigger input or ADCO ADC7 push pull output Pull up resistors are assigned by INTO INT 1 software PortO pins can also be used as A D
134. lator Characteristics 40 C to 85 C Osaer Test conaton Tm wx ws ceramic Vpp 1 8 to 2 7V 0 4 Ex MHz EH Main System Vop 18 to 27V NOTE For more information refer to Figure 14 2 Table 14 5 Oscillation Stabilization Time TA 40 C to 85 C VDD 1 8 V to 5 5 V Test Condition Main crystal fosc gt 1 0 MHz Main ceramic Oscillation stabilization occurs when Vpp is equal to the minimum oscillator voltage range External clock input high and low width 500 main system Oscillator twarr When released by a reset 1 ee stabilization NOTE 1 fOSC specifies the oscillator frequency 2 The duration of the oscillator stabilization wait time tWAIT when it is released by an interrupt is determined by the settings in the basic timer control register BTCON SAMSUNG ELECTRONICS 14 5 er S3F94C8 F94C4 UM REV 1 00 14 MECHANICAL DATA Table 14 6 RC Oscillator Characteristics S3F94C8EZZ F94C4EZZ 25 C to 85 C Vpp 1 8V to 5 5 Vpp 9 MHz MHz KHz External RC oscillator Internal RC oscillator Tolerance of Internal RC Vpp 5 0 V TA 25 C Vpp 5 0 25 to 85 C Vpp 2 0 to 5 5 V 25 to 85 C Table 14 7 RC Oscillator Characteristics S3F94C8XZZ F94C4XZZ 40 C to 85G Vpp 1 8V to 5 5 Clock Circuit Test Condition
135. lization interval following a Reset or when the Stop mode is released by an external interrupt In Stop mode whenever a Reset or an external interrupt occurs the oscillator will start The BTCNT value then starts increasing at the rate of fOSC 4096 for Reset or at the rate of preset clock source for an external interrupt When BTCNT 7 is set a signal is generated to indicate that the stabilization interval has elapsed and to gate the clock signal off to the CPU so that it can resume normal operation The following events occur when Stop mode is released 1 During Stop mode an external power on Reset or an external interrupt occurs to release the Stop mode and start oscillation 2 external power on Reset occurs the basic timer counter will increase at the rate of fOSC 4096 If an external interrupt is used to release the Stop mode the BTCNT value increases at the rate of preset clock source 3 Clock oscillation stabilization interval begins and continues until the bit 7 of basic timer counter is set 4 When a 7 is set normal CPU operation can resume SAMSUNG ELECTRONICS 10 3 im S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 Figure 10 2 and Figure 10 3 show the oscillation stabilization time RESET and STOP mode release Oscillation Stabilization Time Normal Operating mode Reset Release Voltage Internal Reset Release Oscillator Oscillator Stabilization Time 100
136. lopment 15 17 1 17 11 Target Boards EE 17 1 17 1 2 Programming Socket Adapter 17 1 17 1 3 Development System enne 17 2 17 1 4 TB94C8 94C4 Target 17 3 17 1 5 SMDS2 Selection 8 17 5 17 1 6 Third parties for Development Tools 2 222 17 9 17 1 6 1 In Circuit Emulator for SAM8 enne 17 9 17 1 6 2 OTP MTP 17 9 17 1 6 3 Development Tools Suppliers sse 17 9 17 1 6 4 8 bit In Circuit Emulator enemies nennen na 17 10 SAMSUNG ELECTRONICS Figure Number Figure 1 1 Figure 1 2 Figure 1 3 Figure 1 4 Figure 1 5 Figure 1 6 Figure 1 7 Figure 1 8 Figure 1 9 Figure 1 10 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 4 1 Figure 5 1 Figure 5 2 Figure 5 3 Figure 6 1 Figure 7 1 Figure 7 2 Figure 7 3 Figure 7 4 List of Figur
137. low is reached the internal reset will be activated The on chip Low Voltage Reset allows Static Reset when supply voltage is below a reference value Typical 1 9 2 3 3 0 3 6 and 3 9 V Owing to this feature external reset circuit can be removed As long as the supply voltage is below the reference value there is an internal and static RESET The MCU can only start when the supply voltage rises above the reference value While calculating the power consumption remember that static current of LVR circuit should be added to CPU operating current in any operating mode such as Stop Idle and Normal Run when LVR enable in Smart option SAMSUNG ELECTRONICS 8 1 en S3F94C8 F94C4 UM REV 1 00 8 RESET AND POWER DOWN Watchdog RESET RESET E Internal System RESETB When the level is lower than V Smart Option 3EH 7 NOTES 1 The target of voltage detection level is the one you selected at smart option 3EH 2 BGR is Band Gap voltage Reference Figure 8 1 Low Voltage Reset Circuit NOTE To program the duration of oscillation stabilization interval configure the appropriate settings in basic timer control register BTCON before entering Stop mode Also if you do not want to use the basic timer watchdog function which causes a system reset if a basic timer counter overflow occurs you can disable it by writing 1010B to the upper nibble of BTCON SAMSUNG ELECTRONICS 8 2 xu S3F94C8 F94C4_UM_REV 1 00 8 RESET
138. lues for Extension Data bits Ext1 PWMEX 7 2 11 6 PWM output stretch Values for Extension Data bits Ext1 PWMEX 7 2 11 8 Descriptions of Pins Used to Read Write the Flash in Tool Program Mode 13 2 Absolute Maximum er rrt 14 2 DC Electrical Characteristics cui en nannte nnn tnn dn MER pa aan Tapa an 14 8 AC Electrical Ch racteristiCs 2 eise rte beet ede P tet 14 4 Oscillator Characteristics n ere e 14 5 Oscillation Stabilization 14 5 RC Oscillator Characteristics SSF94C8EZZ 946 4 471 14 6 RC Oscillator Characteristics SSF94C8XZZ 4 2 2 14 6 Data Retention Supply Voltage in Stop Mode 14 7 A D Converter Electrical 5 5 14 8 LVR Circuit ChiaracterisliCs 4 iaa ceperint on nnno rta one aa oo deed 14 9 Flash Memory AC Electrical characteristics 14 9 ESD Sene 14 10 SAMSUNG ELECTRONICS er Table 16 1 Table 16 2 Table 16 3 Table 16 4 Table 17 1 Table 17 2 Table 17 3 Table 17 4 Table 17 5 Descriptions of Pins Used to Read Write the EPROM
139. mes no responsibility however for possible errors or omissions or for any consequences resulting from the use of the information contained herein Samsung reserves the right to make changes in its products or product specifications with the intent to improve function or design at any time and without notice and is not required to update this documentation to reflect such changes This publication does not convey to a purchaser of semiconductor devices described herein any license under the patent rights of Samsung or others Samsung makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Samsung assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation any consequential or incidental damages Copyright 2010 Samsung Electronics Co Lid Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by the customer s technical experts Samsung products are not designed intended or authorized for use as components in systems intended for surgical implant into the body for other applications intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may oc
140. n address data bus architecture and a large number of bit configurable ports have been provided To support real time operation s timer counters with selectable operating modes are also included 1 1 1 S3F94C8 F94C4 Microcontroller The S3F94C8 F94C4 single chip 8 bit CMOS microcontroller is designed for A D converter application field This microcontroller which is based on Samsung s SAM88RCRI CPU architecture is fabricated using an advanced CMOS process To reduce power consumption Stop and Idle Power down modes are implemented The S3F94C8 microcontroller contains an embedded 8Kbyte multi time programmable Full Flash ROM On the other hand the S3F94C4 microcontroller contains an 4Kbyte multi time programmable Full Flash ROM Both S3C94C8 and S3F94C4 are general purpose microcontrollers that are ideal for use in a wide range of electronics applications requiring simple timer counter and Pulse width Modulation PWM In addition the advanced CMOS technology in S3F94C8 F94C4 accounts for low power consumption and wide operating voltage range Using the SAM88RCRI design approach the following peripherals are integrated with the SAM8RCRI core e Three configurable I O ports 18 pins e Four interrupt sources with one vector and one interrupt level e One 8 bit timer counter with time interval modes e Analog to digital converter with nine input channels maximum and 10 bit resolution e One PWM output with three optional modes 8
141. nerates positive number MSB 0 Operation generates negative number MSB 1 4 Overflow Flag V 0 Operation resultis lt 127 or gt 128 1 Operation resultis gt 127 or lt 128 3 0 Not used for S3F94C8 F94C4 NOTE The unused bits 3 0 should always be kept as 0 in normal operation otherwise it may cause error SAMSUNG ELECTRONICS 4 8 S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 5 FMCON Flash Memory Control Register Bitldentifer 7 6 5 4 3 2 4 o ReetVae o o o o C reame aw aw nw aw Rw 7 4 Flash Memory Mode Selection Bits fo Programmingmode Pi 1 sectorerase mods Prof Hardiockmode 3 1 Not used for the S8F94C8 F94C4 0 Flash Operation Start Bit Operation stops 1 Operation starts This bit will be cleared automatically just after the corresponding operation is completed SAMSUNG ELECTRONICS 4 9 er S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 6 FMSECH Flash Memory Sector Address Register High Byte EEH Bitldentifer 7 6 5 4 3 2 3 o o o o of 9 9 9 9 RW RW RW RW RW RW RW RW 7 0 Flash Memory Sector Address Bits High Byte The 15th 8th bits select a sector of flash ROM NOTE The high byte flash memory sector address poi
142. ng sample program sets Timer 0 to interval timer mode ORG 000H VECTOR OOH INT 94C4 S3F94C8 F94C4 has only one interrupt vector ORG 03CH D OH 003C must be initialized to 0 D OH 003D must be initialized to 0 D D D E7H 003E enable LVR 2 3 V 03H 003F internal RC 3 2MHz in VDD 5V RG 0100 I Disable interrupt LD BTCON 1 0 Disable watchdog LD CLKCON Select non divided CPU clock LD SP 0 0 Set stack pointer LD POCON 0 LD POCONL 10 LD P1CON 000 LD P2CONH 01 LD P2CONL 0 0 A H L P0 0 0 7 push pull output P1 0 P1 1 push pull output 1 1 0 0 1 CO lt lt gt P2 0 P2 6 push pull output lt lt Timer setti TODATA CPU 3 2MHz interrupt interval 4 msec TOCON fOSC 256 Enable Timer 0 interrupt Enable interrupt lt lt Main loop gt gt Start main loop ED DISPLAY Sub block module JOB Sub block module ED DISPLAY SAMSUNG ELECTRONICS 10 11 uu S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 lt lt Interrupt Service Routines gt gt INT 94C4 OCON 00000010B Check Interrupt enabl Z NEXT CHK1 OCON 00000001B If timer 0 interrupt occurs NZ INT TIMERO TOCON O bit will be set EXT_CHK1 Interrupt enable bit and pending bit check INT TIM Timer 0 inte
143. ng to Mr Chung s information 250 C 100 000 40 85 10 000 So Spec 10 000 Nov 24 2009 Add Note for PWMCON 5 should always be set e Chapter 12 to 0 Because EVA chip not revision So need to note in Spec Dec 01 2009 PWM extended waveform of 6 6 and 8 6 e Chapter 11 modified Error correction Correct error PWMEX value in the figure SAMSUNG ELECTRONICS IT Preface The S3F94C8 94C4 Microcontroller User s Manual is designed for application designers and programmers who are using the S8F94C8 94C4 microcontroller for application development It is organized in two main parts Part Programming Model Part Hardware Descriptions Part contains software related information to familiarize you with the microcontroller s architecture programming model instruction set and interrupt structure It has six chapters Chapter 1 Product Overview Chapter 4 Control Registers Chapter 2 Address Spaces Chapter 5 Interrupt Structure Chapter 3 Addressing Modes Chapter 6 Instruction Set Chapter 1 Product Overview is a high level introduction to S3F94C8 940C4 with general product descriptions as well as detailed information about individual pin characteristics and pin circuit types Chapter 2 Address Spaces describes program and data memory spaces the internal register file and register addressing Chapter 2 also describes working register addressing as well as system stack and user defined stack oper
144. nter value specifies the higher eight bits of 16 bit pointer address 4 1 7 FMSECL Flash Memory Sector Address Register Low Byte EFH Bitldentifer 7 6 5 4 3 2 34 o o o 9 od 7 Flash Memory Sector Address Bit Low Byte The 7t bit selects a sector of flash ROM 6 0 Bits 6 0 Don t care NOTE The low byte flash memory sector address pointer value specifies the lower eight bits of 16 bit pointer address 4 1 8 FMUSR Flash Memory User Programming Enable Register EDH Bit Identifier 7 Reset Value EE TN 4n Read Write R W 7 0 Flash Memory User Programming Enable Bits 10100101 Enables user programming mode Other values Disables user programming mode d SAMSUNG ELECTRONICS 4 10 S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 9 POCONH Port 0 Control Register High Byte E6H Bitldentifer 7 6 5 4 3 2 a o Preserves o o o e 9 9 9 7 6 Port 0 PO 7 ADC7 Configuration Bits Schmitt trigger input pull up enable FEN Schmitt trigger input Push pull output A D converter input ADC7 Schmitt trigger input off 5 4 Port 0 P0 6 ADC6 PWM Configuration Bits Schmitt trigger input pull up enable rake Alternative function PWM output PES Push pull output A D converter input ADC6 Schmitt trigger input off 3 2 Port 0 P0 5 ADC5 Configuration Bits
145. o this value replaces the carry flag 7 0 cee Flags C Set if the bit rotated from the most significant bit position bit 7 was 1 2 Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurs that is if the sign of the destination changed during rotation cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 90 R 91 IR Examples Given Register 00H OAAH register 01H 02H and register 02H 17H RL 00H Register 00H 55H C 1 RL Q01H gt Register 01 02H register 02H 2EH 0 In the first example if general register contains the value 10101010B the statement RL rotates the OAAH value left one bit position leaving the new value 55H 01010101B and setting the carry and overflow flags SAMSUNG ELECTRONICS 6 40 en S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 28 Rotate Left Through Carry RLC dst Operation dst 0 lt dst 7 dst n 1 lt dst 0 6 The contents of the destination operand with the carry flag are rotated left one bit position The initial value of bit 7 replaces the carry flag C the initial value of carry flag replaces bit zero Ee Flags Set if the bit rotated from the most significant bit position bit 7 was 1 Z Set if the result is 0 clea
146. ol Register 7 2 8 RESET AND POWER DOWN peor oan annona ranas nnnm nn naar nn ara 8 1 8 1 System Dea 8 1 8 1 1 Overview of System 8 1 8 11 External Reset PIn inui ipee oe 8 3 8 1 1 2 MCU Initialization 8 4 8 2 Power DowN E 8 5 8 2 1 Stop Mode 8 5 8 2 1 1 Using RESET to Release Stop Mode 8 5 8 2 1 2 Using an External Interrupt to Release Stop Mode 8 5 8 2 2 Id EUER 8 6 8 3 Hardware Reset Values datei tete ated sardi Ege Rad dece dig geb kn ka e 8 7 9 VO POM gute 9 1 9 1 Overview of I O 9 1 9 1 1 Port Data Registers ica aie dee ni anaes 9 2 QV 2 POM MEE 9 3 meu 9 7 AM dvd M 9 9 10 BASIC TIMER AND TIMER O aaaassssssnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnnn nnmnnn 10 1 10 1 Overview of Basic Timer and Timer 0 10 1 10 1 Basie TIME m 10 1 SAMSUNG ELECTRONICS en 10 1
147. only way to release Idle mode 2 Activate any enabled interrupt causing Idle mode to be released When you use an interrupt to release Idle mode the CLKCON 3 and CLKCON 4 register values remain unchanged and the currently selected clock value is used The interrupt is then serviced Following IRET from service routine the instruction immediately following the one that initiated Idle mode is executed NOTE 1 Only external interrupts that are not clock related can be used to release the Stop mode To release Idle mode however any type of interrupt internal or external can be used 2 Before entering the STOP or IDLE mode the ADC must be disabled Otherwise the STOP or IDLE current can increase significantly SAMSUNG ELECTRONICS 86 im S3F94C8 F94C4 UM REV 1 00 8 3 Hardware Reset Values 8 RESET AND POWER DOWN Table 8 1 lists the values for CPU and system registers peripheral control registers and peripheral data registers following Reset operation in normal operating mode 1 0 shows the Reset bit value as logic one or logic zero respectively e x means that the bit value is undefined following a reset e dash means that the bit is either not used or not mapped Table 8 1 R Register Values after Reset RESET Value Bit Register N Address and Location Ge RW 7 65 2110 0 Location Is Not Mapped Locations DGH D8H Are Not Mapped
148. open drain output Not used for S3F94C8 F94C4 T 3 2 Port 1 P1 1 Interrupt Pending Bits Schmitt trigger input Schmitt trigger input pull up enable 1 9 Schmitt trigger input pull down enable 1 0 Port 1 P1 0 Configuration Bits Schmitt trigger input Schmitt trigger input pull up enable 1 output Schmitt trigger input pull down enable NOTE When you use external oscillator P1 0 and P1 1 must be set to output port to prevent current consumption SAMSUNG ELECTRONICS 4 14 en S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS 4 1 13 P2CONH Port 2 Control Register High Byte EAH Bitidentifer 7 6 5 4 3 2 a o Preserves o o o 9 9 Reaaiwite aw aw aw aw aw aw RW 7 Not used for the S3F94C8 F94C4 6 4 Port 2 P2 6 ADC8 CLO Configuration Bits 4 if o oupa purper 3 2 Port 2 2 5 Configuration Bits o Semmttinggerinpuipuispene 1 0 Port 2 2 4 Configuration Bits Schmitt trigger input pull up enable fo i Schmitt trigger input 1 Push putloutput __ NOTE To avoid problems resulting from noise do not use CLO output SAMSUNG ELECTRONICS 4 15 IP S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS
149. or 8 bit data register TODATA e Timer 0 control register SAMSUNG ELECTRONICS 10 1 er S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 10 2 Basic Timer BT 10 2 1 Basic Timer Control Register BTCON The basic timer control register BTCON selects the input clock frequency to clear the basic timer counter and frequency dividers and to enable or disable the watchdog timer function Reset clears BTCON to This enables the watchdog function and selects basic timer clock frequency of fOSC 4096 To disable the watchdog function you must write the signature code 1010 to the basic timer register control bits BTCON 7 BTCON 4 The 8 bit basic timer counter BTCNT can be cleared during normal operation by writing a 1 to BTCON 1 clear the frequency dividers for both the basic timer input clock and timer 0 clock write 1 to BTCON O Basic Timer Control Register BTCON DCH R W ao Divider clear bit for basic Watchdog timer enable bits timerand timer 1010B Disable watchdog function 0 No effect Other value Enable watchdog 1 Clear both dividers function Basic timer counter clear bits 0 No effect 1 Clear basic timer counter Basic timer input clock selection bits 00 fosc 4096 01 fosc 1024 10 fosc 128 11 Invalid selection NOTE When you write 1 to BTCON 0 or BTCON 1 the basic timer divider or basic timer counter is cleared T
150. pcode Hex opc 1 4 CF Example Given C2 1 or 0 The instruction RCF clears the carry flag C to logic zero SAMSUNG ELECTRONICS 6 38 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 26 RET Return RET Operation PC SP SP lt 2 The RET instruction is normally used return to the previously executing procedure at the end of a procedure entered by a CALL instruction The contents of the location addressed by the stack pointer are popped into the program counter The next statement to be executed is addressed by the new program counter value Flags No flags are affected Format Bytes Cycles Opcode Hex ope 1 8 AF 10 Example Given SP OBCH SP 101AH and PC 1234 RET gt PC 101AH SP OBEH The statement RET pops the contents of stack pointer location OBCH 10H into the high byte of program counter The stack pointer then pops the value in location OBDH 1 into the program counter s low byte following which the instruction at location 101AH is executed The stack pointer now points to memory location OBEH SAMSUNG ELECTRONICS 6 39 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 27 RL Rotate Left RL dst Operation dst 7 dst 0 lt dst 7 dst n 1 lt dst n 0 6 The contents of destination operand are rotated left one bit position The initial value of bit 7 is moved to the bit zero LSB position Als
151. prevents change of data in flash memory area If this function is enabled you cannot write or erase the data in a flash memory area This protection can be released by executing chip erase in the tool program mode In user program mode the procedure of setting Hard Lock Protection is described below In tool mode the manufacturer of serial tool writer could support Hardware Protection Refer to the manual of serial program writer tool provided by the manufacturer 13 6 1 Program Procedure in User Program Mode 1 Set Flash Memory User Programming Enable Register FMUSR to 10100101B 2 Set Flash Memory Control Register FMCON to 01100001B 3 Set Flash Memory User Programming Enable Register FMUSR to 00000000B Example 13 4 Programming Tip Hard Lock Protection FMUSR 0A5H Enable User program mode FMCON 01100001B Select Hard Lock Mode and start protection FMUSR 00 Disable User program mode SAMSUNG ELECTRONICS 13 15 ex S3F94C8 F94C4 UM REV 1 00 14 1 Overview of Electrical Data ELECTRICAL DATA 14 MECHANICAL DATA In this section the following S3F94C8 F94C4 electrical characteristics have been presented in the form of tables and graphs SAMSUNG ELECTRONICS Absolute maximum ratings DC electrical characteristics AC electrical characteristics Input timing measurement points Oscillator characteristics Oscillation stabilization time Operating voltage range Schmitt trigger
152. py 16 pin V 8 Vpp V DD 8 VSS 20 pin EY Logic power supply pin 13 1 1 2 User Program Mode This mode supports sector erase byte programming byte read and protection mode Hard Lock Protection The S3F94C8 F94C4 contains an internal pumping circuit to generate high voltage To program a flash memory in this mode several control registers should be used There are four kinds of functions in user program mode programming reading sector erase and protection mode Hard lock protection SAMSUNG ELECTRONICS 13 2 en S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 2 Flash Memory Control Registers User Program Mode 13 2 1 Flash Memory Control Register FMCOn FMCON register is only available in the user program mode to select the flash memory operation mode sector erase byte programming or making the flash memory into a hard lock protection Flash Memory Control Register FMCON ECH R W Flash Erase or Hard Lock Protectior Flash Memory Mode Selection Bits Operation Start Bit 0101 Programming mode 1010 Erase mode 0 Operation stop 0110 Hard lock mode 1 Operation start others Not used for 3 94 8 94 4 This bit will be cleared automatically just after erase operation Not used for S3F94C8 F94C4 Figure 13 1 Flash Memory Control Register FMCON The bit 0 of FMCON register FMCON 0 is used for enabling the Erase and Hard Lock Protection Therefore Era
153. red otherwise Set if the result bit 7 is set cleared otherwise V Set if arithmetic overflow occurs that is if the sign of the destination changes during rotation cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst opc dst 2 4 10 R 4 11 IR Examples Given Register 00H OAAH register 01H 02H and register 02H 17H 0 RLC OOH gt Register 00H 54H 1 RIC 601H gt Register 01H 02H register 02H 2EH 0 In the first example if general register has the value 101010108 the statement RLC rotates one bit position to the left The initial value of bit 7 sets the carry flag and the initial value of C flag replaces bit zero of register 00H leaving the value 55H 01010101B The MSB of register OOH resets the carry flag to 1 and sets the overflow flag SAMSUNG ELECTRONICS 6 41 xu S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 29 RR Rotate Right RR dst Operation lt dst 0 dst 7 lt dst 0 dst lt dst 1 n 0 6 The contents of destination operand are rotated right one bit position The initial value of bit zero LSB is moved to bit 7 MSB Also this value replaces the carry flag C 7 0 eis Flags C Set if the bit rotated from the least significant bit position bit zero was 1 2 Set if the result is 0 cleared otherwise S Set if the result bit 7
154. rnal RESET LVR normal I O pin can use the nRESET pin P1 2 S3F94C8 F94C4 can be RESET in four different ways using e External power on reset e External nRESET input pin pulled low e Digital watchdog peripheral timing out e Low Voltage Reset LVR During an external power on reset the voltage VDD is at High level and the nRESET pin is forced to Low level The nRESET signal is inputted through a Schmitt trigger circuit where it is synchronized with the CPU clock This brings the S3F94C8 F94C4 into a known operating status To ensure correct start up you should not release the nRESET signal before the VDD level is sufficient This allows MCU to operate at the chosen frequency To allow time for internal CPU clock oscillation so it can stabilize the nRESET pin must be held to Low level for a minimum time interval after the power supply comes within tolerance The minimum required oscillation stabilization time for a reset is approximately 52 4 ms 219 fOSC fOSC 10 MHz When a reset occurs during normal operation with both VDD and nRESET at High level the signal at the nRESET pin is forced to Low level and the Reset operation starts All system and peripheral control registers are then set to their default hardware Reset values see Table 8 1 for more information The MCU provides a watchdog timer function to ensure recovery from software malfunction If watchdog timer is not refreshed before an end of counter condition overf
155. rogram or Data Memory SAMSUNG ELECTRONICS 3 6 im S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES 3 1 6 Indexed Addressing Mode To calculate the effective operand address Indexed X Addressing mode adds an offset value to a base address during instruction execution see Figure 3 7 You can use Indexed Addressing mode to access locations in the internal register file or external memory In Short Offset Indexed Addressing mode the 8 bit displacement is treated as a signed integer in the range of 128 to 127 This applies to external memory accesses only see Figure 3 8 For register file addressing an 8 bit base address provided by the instruction is added to an 8 bit offset contained in a working register For external memory accesses the base address is stored in the working register pair designated in the instruction The 8 bit or 16 bit offset given in the instruction is then added to the base address see Figure 3 9 The only instruction that supports Indexed Addressing mode for the internal register file is Load instruction LD The LDC and LDE instructions support Indexed Addressing mode for internal program memory external program memory and for external data memory when implemented Register File Do instruction Ne OPERAND Program Memory Two Operand Point to one of the Instruction working register Example 1 of 16 Sample Instruction LD BASE R1 Where BASE is 8 bit immediate value
156. rogrammer Writer d SPW uni SEMINIX Single OTP MTP FLASH Programmer Telephone 82 2 539 7891 Supports Download Upload and Data Edit functions Fax 82 2 539 7819 Supports PC based operation with USB port E mail sales seminix com Supports full functions of OTP MTP FLASH MCU URL programmer Read Program Verify Blank and http Awww seminix com Protection Fast programming speed 4Kbyte sec Supports all Samsung OTP MTP FLASH MCU devices Low cost NOR Flash memory SST Samsung NAND Flash memory SLC Supports new devices by adding device files or upgrading the software GW uni SEMINIX Gang Programmer for OTP MTP FLASH MCU Telephone 82 2 539 7891 Supports eight devices programming at one time Fax 82 2 539 7819 Fast programming speed OTP 2Kbps MTP E mail sales seminix com 10Kbps URL Maximum buffer memory 100Mbyte http Awww seminix com Operation mode PC based Stand alone no PC Supports full functions of OTP MTP Read Program Checksum Verify Erase Read protection and Smart option Simple Graphical User Interface GUI Sets device information using device part number Supports LCD display and touch key Stand alone mode operation System upgradable Simple firmware upgrade SAMSUNG ELECTRONICS 17 11 xu S3F94C8 F94C4 UM REV 1 00 OTP MTP Programmer Writer Continued 17 DEVELOPMENT TOOLS AS pro On board programmer for Samsung Flash MCU Portable and St
157. rrupt service routine 11110110B Pending bit SAMSUNG ELECTRONICS 10 12 er S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION PULSE WIDTH MODULATION 11 1 Overview of Pulse Width Modulation The S3F94C8 F94C4 microcontroller consists of the Pulse Width Modulation PWM circuit This circuit can be configured in one of the three resolutions e 8 bit resolution 6 bit base 2 bit extension e 12 bit resolution 6 bit base 6 bit extension e 14 bit resolution 8 bit base 6 bit extension These three resolutions are mutually exclusive that is only one resolution can work at any time PWMEX 1 0 selects the resolution to be used The operation of all PWM circuits is controlled by a single control register PWMCON The PWM counter is an incrementing counter used by the PWM circuits To start the counter and enable the PWM circuits set PWMCON 2 to 1 If the counter is stopped it retains the current count value When the counter is re started it resumes counting from the retained count value To clear the counter set PWMCON 3 to 1 You can select a clock for the PWM counter by setting PWMCON 6 7 The clocks that you can select are fOSC 64 fOSC 8 OSC 2 and fOSC 11 1 1 Function Description 11 1 1 1 PWM The PWM circuits have the following components e PWM mode selection PWMEX 1 0 e Base comparator and extension cycle circuit e Base reference data registers PWMDATA PWMDAT
158. rs including 16 bit common working register area 208 Total Addressable Bytes 240 SAMSUNG ELECTRONICS 2 5 er S3F94C8 F94C4_UM_REV 1 00 SAMSUNG ELECTRONICS 2 ADDRESS SPACES Peripheral Control Registers 64 Bytes of Common Area System Control Registers Working Registers General Purpose 192 Bytes Register File and Stack Area Figure 2 3 Internal Register File Organization S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES 2 4 Common Working Register Area COH CFH The SAM88RCRI register architecture provides an efficient method for working register addressing mode This method takes full advantage of shorter instruction formats to reduce the execution time The 16 byte address range is called common area It can be used as working register to address any location on any page in the register file Typically these working registers serve as temporary buffers for data operations in different pages However since the S3F94C8 F94C4 uses only page 0 you can use the common area for any internal data operation The working register addressing mode and indirect register addressing mode can be used to access this area Registers are addressed as either single 8 bit register or paired 16 bit register In 16 bit register pairs the address of the first 8 bit register is always an even number and the address of the next register is an odd number The most significant byte of the 16 bit data is always stored in the even numbered
159. rsion With a 10 MHz CPU clock frequency one clock cycle is 400 ns 4 fxx If each bit conversion requires 4 clocks the conversion rate is calculated as follows 4 clocks bit x 10 bit step up time 10 clock 50 clocks 50 clock x 400 ns 20 us at 10 MHz 1 clock time 4 fxx assuming ADCON 2 1 10 SAMSUNG ELECTRONICS 12 4 er S3F94C8 F94C4 UM REV 1 00 12 A D CONVERTER 12 1 5 Internal A D Conversion Procedure 1 2 Analog input must remain between the voltage range of VSS and VDD Configure the analog input pins for input mode by making the appropriate settings in POCONH POCONL and P2CONH registers Before the conversion operation starts you must first select one of the nine input pins ADCO ADC8 by writing the appropriate value to the ADCON register When conversion has been completed 50 clocks have elapsed the EOC flag is set to 1 that a check can be made to verify that the conversion was successful The converted digital value is loaded to the output register ADDATAH 8 bit and ADDATAL 2 bit and then the ADC module enters into an idle state The digital conversion result can now be read from the ADDATAH and ADDATAL register Analog ADCO ADC8 Input Pin X S3F94C8 F94C4 Vss Figure 12 5 Recommended A D Converter Circuit for Highest Absolute Accuracy SAMSUNG ELECTRONICS 12 5 xu S3F94C8 F94C4 UM REV 1 00 12 A D CONVERTER Example 12 1 Programming Tip Configuring
160. s In Stop mode the main oscillator freezes that is it halts the CPU and peripherals The contents of the register file and current system register values are retained as is To release the Stop mode and start the oscillator reset operation must be performed or an external interrupt with RC delay noise filter for S3F94C8 F94C4 INTO INT1 must be applied In Idle mode the internal clock signal is gated off to the CPU but not to the interrupt control and timer The current CPU status is preserved including stack pointer program counter and flags Data in the register file is retained as is To release the Idle mode reset operation must be performed or an interrupt external or internally generated must be applied 7 1 3 System Clock Control Register CLKCON The System Clock Control Register is located in location 4 This register is read write addressable and has the following functions Oscillator IRQ wake up function enable disable CLKCON 7 Oscillator frequency divide by value non divided 2 8 or 16 CLKCON 4 and CLKCON 3 The CLKCON register decides whether an external interrupt can be used to release the Stop mode This is called the IRQ wake up function The IRQ wake up enable bit is CLKCON 7 After the reset operation is performed the external interrupt oscillator wake up function is enabled and the fOSC 16 slowest clock speed is selected as the CPU clock If necessary you can increase
161. s SAMSUNG ELECTRONICS 3 11 er S3F94C8 F94C4_UM_REV 1 00 3 ADDRESSING MODES 3 1 11 Relative Address Mode In Relative Address RA mode a two s complement signed displacement between 128 and 127 is specified in the instruction The displacement value is then added to the current PC value The result specifies the address of next instruction to be executed Before this addition occurs the PC contains the address of instruction immediately following the current instruction The instruction that supports RA addressing is JR Program Memory Next OPCODE Program Memory Address Used Current PC Value amp Displacement Current Instruction OPCODE Signed PF Displacement Value Sample Instructions JR ULT OFFSET Where OFFSET is a value in the range 127 to 128 Figure 3 12 Relative Addressing 3 1 12 Immediate Mode In Immediate IM Addressing mode the operand value used in instruction is the value supplied in operand field itself Immediate addressing mode is useful for loading constant values into registers Program Memory OPERAND OPCODE The Operand value is in the instruction Sample Instruction LD 0 Figure 3 13 Immediate Addressing SAMSUNG ELECTRONICS 3 12 er S3F94C8 F94C4_UM_REV 1 00 4 ADDRESSING REGISTERS ADDRESSING REGISTERS 4 1 Overview of Control Registers In this section detailed description of the S3F94C8 F94C4 control registers has been provide
162. s The S3F94C8 F94C4 has three I O ports with 18 pins in total You can access these ports directly by writing or reading port data register addresses All ports can be configured as LED drive High current output typical 10 mA Table 9 1 Overview of S3F94C8 F94C4 Port Configuration Function Description Programmability Bit programmable port for Schmitt trigger input or push pull output Pull up resistors are assigned by software Port 0 pins can also be used for alternative function ADC input external interrupt input Bit programmable port for Schmitt trigger input or push pull open drain output Pull up resistor are assignable by software Port 2 can also be used as alternative function ADC input CLO TO clock output Bit programmable I O port for Schmitt trigger input or push pull open drain output Pull up or pull down resistors are assignable by software Port 1 pins Bit can also be used as oscillator input output or reset input by smart option P1 2 is input only SAMSUNG ELECTRONICS 9 1 xu S3F94C8 F94C4_UM_REV 1 00 9 PORTS 9 1 1 Port Data Registers Table 9 2 provides an overview of the port data register names locations and addressing characteristics Figure 9 1 shows the structure of data registers for ports 0 2 Table 9 2 Port Data Register Summary NOTE reset operation clears the PO P2 data register to OOH I O Port n Data Register 0 2 Figure 9 1 Port D
163. s composed of a host system debugging tools and supporting software For a host system any standard computer that employs Win95 98 2000 XP as its operating system can be used A sophisticated debugging tool is provided in both the hardware and software This tool includes an in circuit emulator OPENice 1500 2000 and SK 1200 for the S3F7 S3F9 and S3F8 microcontroller families Samsung also offers supporting software that includes debugger assembler and program for setting options 17 1 1 Target Boards Target boards are available for all the S3C9 S3F9 series microcontrollers All the required target system cables and adapters are included in the device specific target board TB94C8 94C4 is a specific target board for the development of application systems using S3F94C8 F94C4 17 1 2 Programming Socket Adapter When you program S3F94C8 F94C4 s flash memory by using an emulator or OTP MTP writer you need a specific programming socket adapter for S3F94C8 F94C4 SAMSUNG ELECTRONICS 17 1 er S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS 17 1 3 Development System Configuration IBM PC or Compatible Emulator SK 1200 RS 232 USB OPEN Ice 1 500 RS 232 or OPENIce 1 2000 RS 232 USB RS 232C USB Target Application System Probe Adapter TB94C8 94C4 Target Board EVA Chip Figure 17 1 Development System Configuration SAMSUNG ELECTRONICS 17 2 er S3F94C8 F94C4 UM REV 1 00 17 DEVELOPMENT TOOLS 17 1 4 T
164. sary because control and data registers are mapped directly into the register file Flexible instructions for bit addressing rotate and shift operations complete the powerful data manipulation capabilities of the SAM88RCRI instruction set 6 1 1 Register Addressing To access an individual register an 8 bit address in the range 0 255 or the 4 bit address of a working register is specified Paired registers can be used to construct 16 bit program memory or data memory addresses For detailed information about register addressing refer to Chapter2 Address spaces 6 1 2 Addressing Modes There are six addressing modes namely Register R Indirect Register IR Indexed X Direct DA Relative RA and Immediate IM For detailed description of these addressing modes refer to Chapter 3 Addressing Modes SAMSUNG ELECTRONICS 6 1 xu S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET Table 6 1 Instruction Group Summary Wwmon Operands O feen femen umet SAMSUNG ELECTRONICS 6 2 er r m o gt 2 vs Q D v U 4 S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET SAMSUNG ELECTRONICS 63 im S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 3 Flags Register FLAGS The flags register FLAGS contains eight bits that describ
165. scillator If you are using internal oscillator then normal I O pins can use XIN P1 0 and XOUT P1 1 An internal RC oscillator source provides a typical 3 2 MHz or 0 5 MHz in VDD 5 V depending on the smart option On the other hand an external RC oscillator source provides a typical 4MHz clock for S3F94C8 F94C4 The RC oscillator circuit is supported by an internal capacitor An external crystal or ceramic oscillator source provides a 10 MHz maximum clock The XIN and XOUT pins connect the oscillator source to the on chip clock circuit Figure 7 1 and Figure 7 2 show a simplified external RC oscillator and crystal ceramic oscillator circuit respectively When you use an external oscillator P1 0 and P1 1 must be set to output port to prevent current consumption S3F94C8 F94C4 Figure 7 1 Main Oscillator Circuit RC Oscillator with Internal Capacitor S3F94C8 F94C4 Figure 7 2 Main Oscillator Circuit Crystal Ceramic Oscillator SAMSUNG ELECTRONICS 7 1 er S3F94C8 F94C4_UM_REV 1 00 7 CLOCK CIRCUIT 7 1 1 Oscillator Logic To increase the processing speed and reduce the clock noise non divided logic must be implemented for the main oscillator circuit For the same reasons high resolution waveforms Square signal edges must be generated so that the CPU can process logic operations efficiently 7 1 2 Clock Status During Power Down Modes The two power down modes Stop and Idle affect the clock oscillation as follow
166. se and Hard Lock Protection is activated when you set FMCON O to 1 If you write FMCON O to 1 for erasing CPU is stopped automatically for erasing time minimum 4ms After erasing time finishes CPU is restarted automatically When you read or program a byte data from or into flash memory this bit is not changed 13 2 2 Flash Memory User Programming Enable Register FMUSR The FMUSR register is used for safe operation of the flash memory This register will protect undesired erase or malfunctioning of CPU caused by an electrical noise After reset the user program mode is disabled since the value of FMUSR is 00000000 by reset operation If it is necessary to operate the flash memory you can use the user program mode by setting the value of FMUSR to 10100101B User program mode is disabled for the other value of 10100101B Flash Memory User Programming Enable Register FMUSR EDH R W Flash Memory User Programming Enable Bits 10100101 Enable user programming mode Other values Disable user programming mode Figure 13 2 Flash Memory User Programming Enable Register FMUSR SAMSUNG ELECTRONICS 13 3 im S3F94C8 F94C4_UM_REV 1 00 13 EMBEDDED FLASH MEMORY INTERFACE 13 2 3 Flash Memory Sector Address Registers There are two sector address registers for erase or programming flash memory The Flash Memory Sector Address Register Low Byte FMSECL indicates the low byte of sector address and Flash Memory Address Sector
167. src The source operand is logically exclusive ORed with the destination operand and the result is stored in the destination The exclusive OR operation results in a 1 bit being stored whenever the corresponding bits in the operands are different otherwise a 0 bit is stored Flags C Unaffected Z Set if the result is 0 cleared otherwise S Set if the result bit 7 is set cleared otherwise V Always reset to 0 Format Bytes Cycles Opcode Addr Mode Hex dst src 6 r Ir src dst 3 6 B4 R R B5 R IR dst src 3 6 B6 R IM Examples Given RO 0C7H R1 02H R2 18H register OOH 2BH register 01H 02H and register 02H 23H XOR RO RI gt RO 0C5H RI 02H XOR RO GR1 R1 02H Register 02H 23H XOR 01H Register 00H 29H Register 01H 02H XOR OOH 01H gt Register 00H 08H Register 01H 02H Register 02H 23H XOR 54 gt Register 00H In the first example if working register RO contains the value 0C7H and if register R1 contains the value 02H the statement XOR R1 logically exclusive ORs the R1 value with the RO value and stores the result 0C5H in the destination register RO SAMSUNG ELECTRONICS 6 51 en S3F94C8 F94C4 UM REV 1 00 7 CLOCK CIRCUIT CLOCK CIRCUIT 7 1 Overview of Clock Circuit Using smart option 3FH 1 0 in ROM you can select internal RC oscillator external RC oscillator or other external o
168. st be initialized to 0 DB OO3EH enable LVR 2 3 V DB 003FH internal RC 3 2 MHz in VDD 5 V lt lt Initialize System and Peripherals gt gt ORG 0100H DI Disable interrupt LD CLKCON 00011000B Select non divided CPU clock LD SP 0COH Stack pointer must be set e LD BTCON 02H Enable watchdog function Basic timer clock fOSC 4096 Clear Basic counter BTCNT Enable interrupt lt lt Main loop gt gt BTCON 02H Enable watchdog function Clear Basic counter BTCNT T MAIN lt lt Interrupt Service Routines gt gt INT 94 4 Check Interrupt enable bit and Pending bit Clear Pending bit SAMSUNG ELECTRONICS 10 6 er S3F94C8 F94C4 UM REV 1 00 10 BASIC TIMER AND TIMER 0 10 3 Timer 0 10 3 1 Timer 0 Control Registers TOCON The timer 0 control register TOCON selects the timer 0 operating mode interval timer and input clock frequency to clear the timer 0 counter and to enable the TO match interrupt It also contains pending bit for TO match interrupts Reset clears TOCON to This operation sets timer 0 to normal interval timer mode selects an input clock frequency of fOSC 4096 and disables the TO match interrupts The TO counter can be cleared at any time during normal operation by writing a 1 to TOCON 3 Timer 0 Control Register TOCON D2H R W Timer O input clock selection bits
169. st be used N ll uou alo SAMSUNG ELECTRONICS 6 9 im S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 Instruction Descriptions This section contains detailed information and programming examples for each instruction in the SAM87RI instruction set Information is arranged in a consistent format for improved readability and for fast referencing The following information is included in each instruction description Instruction name mnemonic Full instruction name Source destination format of the instruction operand Shorthand notation of the instruction s operation Textual description of the instruction s effect Specific flag settings affected by the instruction Detailed description of the instruction s format execution time and addressing mode s Programming example s explaining how to use the instruction SAMSUNG ELECTRONICS 6 10 er S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 1 ADC Add with Carry ADC dst src Operation dst lt dst src c The source operand along with the setting of the carry flag is added to the destination operand Their sum is stored in the destination The contents of the source remain unaffected Also two s complement addition is performed In multiple precision arithmetic this instruction permits the carry from the addition of low order operands to be carried onto the addition of high order operands Flags C Set if there is a
170. tended PWM Waveform 6 bit base 6 bit extension SAMSUNG ELECTRONICS 11 7 S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION 8 bit base 6 bit extension mode Table 11 4 PWM output stretch Values for Extension Data bits PWMEX 7 2 1 3 5 7 9 55 57 59 61 63 PWM Clock 4MHz OH PWMDATA1 Register 4g Values 250ns Figure 11 6 PWM Basic Waveform 8 bit base SAMSUNG ELECTRONICS 11 8 im S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION PWM Clock PWMDATA1 Register Values 02H PWMEX 64th 151 Extended Value is 04H Register Values 000100 11B J Figure 11 7 PWM Basic Waveform 8 bit base 6 bit extension SAMSUNG ELECTRONICS 11 9 er S3F94C8 F94C4_UM_REV 1 00 11 PULSE WIDTH MODULATION 11 1 2 PWM Control Register PWMCON The control register for the PWM module PWMCON is located at register address PWMCON is used for all three PWM resolutions Bit settings in the PWMCON register control the following functions e PWM counter clock selection PWM data reload interval selection e PWM counter clear e PWM counter stop start or resume operation e PWM counter overflow upper counter overflow interrupt control A reset clears all PWMCON bits to logic zero and disables the entire PWM module PWM Control Registers PWMCON F3H R W Reset 00H PWM extension counter OVF PWM input clock Interrupt pending
171. terrupt the current values in system and peripheral control registers are not changed When you use an interrupt to release Stop mode the CLKCON 3 and CLKCON 4 register values remain unchanged and the currently selected clock value is used If you use an external interrupt for Stop mode release you can also program the duration of oscillation stabilization interval To do this you must put the appropriate value to BTCON register before entering Stop mode The external interrupt is serviced when the Stop mode release occurs Following the IRET from the service routine the instruction immediately following the one that initiated Stop mode is executed SAMSUNG ELECTRONICS 85 im S3F94C8 F94C4_UM_REV 1 00 8 RESET AND POWER DOWN 8 2 2 Idle Mode Idle mode is invoked by the instruction IDLE opcode 6FH In Idle mode CPU operations are halted while some peripherals remain active During this mode the internal clock signal is gated off to the CPU but not to the interrupt logic and timer counters Port pins retain the same mode input or output that they had at the time of entering the Idle mode There are two ways to release Idle mode namely 1 Execute a Reset All system and peripheral control registers are reset to their default values and the contents of all data registers are retained The Reset automatically selects slow clock FOSC 16 because CLKCON 3 and CLKCON 4 are cleared to 00B If interrupts are masked Reset is the
172. ters nennen nnns 9 6 uio gu 1 Circuit Diagram ananasen 9 7 Port 1 Control Register P1CON 9 8 Port 2 Circuit Dig Grain 9 9 Port 2 Control Register P2CONH High Byte 9 10 Port 2 Control Register P2CONL Low Byte 9 1 Basic Timer Control Register BTCON sssssssssssssseseseeeeee ener enne nennen nenas 10 2 Oscillation Stabilization Time on RESET arenennvrnnnnvnnnnnvnnerrennnnrnnennnnrerresssrrnsnnrnnsnrensssrrssnnrensrnesennne 10 4 Oscillation Stabilization Time on STOP Mode Release 10 5 Timer 0 Control Registers nennen sensns nennen 10 7 Simplified Timer 0 Function Diagram Interval Timer Mode 10 8 BESSER Em 10 9 Basic Timer and Timer 0 Block Diagram eene 10 10 PWM Data and Extension 1 2 2 11 2 PWM Basic Waveform 6 bit 2 2 11 4 Extended PWM Waveform 6 51 base 2 bit extension 11 5 PWM Basic Waveform 6 bit base
173. the source operand cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 A3 r Ir src dst 3 6 A4 R R A5 R IR dst src 3 6 IM Examples Given R1 02H and R2 03H CP R1 R2 gt Set the C and S flags Destination working register R1 contains the value 02H and source register R2 contains the value 03H The statement CP R1 R2 subtracts the R2 value source subtrahend from the R1 value destination minuend Since borrow occurs and the difference is negative C and S are 1 Given R1 05H and R2 OAH CP R1 R2 JP UGE SKIP INC R1 SKIP LD R3 R1 In this example destination working register R1 contains the value 05H which is less than the contents of the source working register R2 OAH The statement R1 R2 generates 1 and the JP instruction does not jump to the SKIP location After the statement LD R3 R1 executes the value 06H remains in working register R3 SAMSUNG ELECTRONICS 6 18 er S3F94C8 F94C4_UM_REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 9 DEC Decrement DEC dst Operation dst lt dst 1 The contents of the destination operand are decremented by one Flags C Unaffected 2 Set if the result is 0 cleared otherwise S Set if result is negative cleared otherwise V Set if arithmetic overflow occurred that is dst value is 128 80H and result value is 127 7FH cleared otherwise Format Bytes Cycles Opcod
174. tialized to 0 DB must be initialized to 0 DB enable LVR 2 3 V DB Internal RC 3 2 MHz in VDD 5 V lt lt Reset gt gt ORG RE SAMSUNG ELECTRONICS 2 4 er S3F94C8 F94C4_UM_REV 1 00 2 ADDRESS SPACES 2 3 Register Architecture The upper 64 bytes of internal register file in S3F94C8 F94C4 consist of working registers system control registers and peripheral control registers The lower 192 bytes of internal register file OOH BFH are called general purpose register space You can access 240 registers in this space 208 registers are reserved for general purpose use case of S3F94C8 F94C4 the total number of addressable 8 bit registers is 240 Out of these 240 registers 32 bytes are used for CPU and system control registers and peripheral control and data registers 16 bytes are used as shared working registers and 192 registers are used for general purpose For many SAM88RCRI microcontrollers the addressable area of internal register file is further expanded by additional register pages in general purpose register space 00H BFH However this register file expansion is not implemented in S3F94C8 F94C4 Table 2 1 shows the specific register types and area in bytes they occupy in internal register file Table 2 1 Register Type Summary Register Type Number of Bytes CPU and system control registers Peripheral I O and clock control and data registers General purpose registe
175. tructions for this purpose 5 1 3 Interrupt Pending Function Types When the interrupt service routine ISR has executed the application program s service routine must clear the appropriate pending bit before return from interrupt subroutine IRET occurs 5 1 4 Interrupt Priority Since there is no interrupt priority register in SAM88RCRI the order of service is determined by a sequence of source executed in interrupt service routine El Instruction Interrupt Pending Execution Register RESET Source Interrupts Source Interrupts Enable Interrpt priority is determind by software polling method Vector Interrupt Cycle Global Interrupt Control El DI instruction Figure 5 2 Interrupt Function Diagram SAMSUNG ELECTRONICS 5 2 er S3F94C8 F94C4_UM_REV 1 00 5 INTERRUPT STRUCTURE 5 1 5 Interrupt Source Service Sequence The interrupt request polling and servicing sequence is as follows 1 Set the interrupt request pending bit to 1 The source generates an interrupt 2 The CPU generates an interrupt acknowledge signal The service routine starts Clear the pending flag of source to 0 using the software 5 Determine the interrupt priority by using software polling method 5 1 6 Interrupt Service Routines Before an interrupt request can be serviced the following conditions must be met Interrupt processing must be enabled El SYM 3 1 Interrupt must be enabled at the interrupt s
176. tt 5 3 5 1 7 Generating interrupt Vector 5 3 5 1 8 S3F94C8 F94C4 Interrupt nennen nnne nennen sterne nnne nen 5 4 5 1 9 Peripheral Interrupt Control eene nennen nennen 5 5 6 SAM88RCRI INSTRUCTION 6 1 6 1 Overview of SAM88RCRI Instruction 6 1 6 Tl Register Addressing Lua dere 6 1 6 1 2 Addressing eed de ra 6 1 6 1 3 Flags Register FLAGS esie rei te rei n Lern Fer Eee 6 4 6 1 4 Flag BI edem 6 4 6 1 4 1 Overflow Flag FLAGS 4 V 6 4 61 42 Sign Flag FEAGS 5 S ius iiie aec eroe 6 4 6 1 4 3 Zero Flag FELAGS 6 Z idet dnd eibi eec tet up lade Eie rase eod dede oc B Ene ed 6 4 6 1 4 4 Carry Flag FEAGS 7 ER rnnt RR Ee Ee XR ehe RN HY 6 4 6 1 5 Instruction Set Notation 6 5 6 1 6 Condition G d s eic eR niece idee a ERUNT HER REL 6 9 6 1 7 Instruction Descriptions sesssesssssssssseesseeen eene eene nnne nnns enn nnn nnns nnns ens 6 10 64 7 1 ADG Addwith Garry a ra ed Ded re gaben aee raid 6 11 6 1 7 2 ADD ETE 6 12 5 1 7 3
177. ut 5 4 Not used for S 3F94C8 F94C4 3 2 Port 1 P1 1 Configuration Bits 0 0 Schmitt trigger input 0 1 Schmitt trigger input pull up enable 1 0 Push pull output 11 Schmitt trigger input pull down enable 1 0 Port 1 P1 0 Configuration Bits 0 0 Schmitt trigger input 01 Schmitt trigger input pull up enable 1 0 Push pull output 11 Schmitt trigger input pull down enable 1 When you use external oscillator P1 0 P1 1 must be set to output port to prevent current consumption 2 When you enable LVR in smart option P1 2 nRESET VPP can be and can only be used as input port Figure 9 7 Port 1 Control Register P1CON SAMSUNG ELECTRONICS 9 8 im S3F94C8 F94C4_UM_REV 1 00 9 PORTS 9 1 4 Port 2 Port 2 is a 7 bit I O port with individually configurable pins It can be used for general I O port Schmitt trigger input mode push pull output mode or N channel open drain output mode You can also use some pins of port 2 ADC input CLO output and TO clock output In addition you can configure a pull up resistor to individual pins using control register settings It is designed for high current functions such as LED direct drive You can address port 2 bits directly by writing or reading the port 2 data register P2 E2H The port 2 control register 2 and P2CONL is located at addresses EAH and respectively Pull up Pull up register Enable 50 typical Open Dr
178. y from the most significant bit MSB of the result cleared therwise 2 Set if the result is 0 cleared otherwise S Set if the result is negative cleared otherwise V Set if arithmetic overflow occurred that is if both operands are of the same sign and the result is of the opposite sign cleared otherwise Format Bytes Cycles Opcode Addr Mode Hex dst src 6 03 r Ir src dst 3 6 04 R R 05 R IR dst src 3 6 06 R IM Examples Given R1 12H R2 03H register 01H 21H register 02H 03H register OAH ADD R1 R2 gt Rl 15H R2 03H ADD R1 R2 gt 1CH R2 03H ADD 01H 02H gt Register 01 24H register 02H 03H ADD 01H 02H gt Register 01 2BH register 02H 03H ADD 01H 25H gt Register 01H 46H In the first example destination working register R1 contains 12H and the source working register R2 contains 03H The statement ADD R1 R2 adds 03H to 12H leaving the value 15H in register R1 SAMSUNG ELECTRONICS 6 12 en S3F94C8 F94C4 UM REV 1 00 6 SAM88RCRI INSTRUCTION SET 6 1 7 3 AND Logical AND AND dst src Operation dst lt dst AND src The source operand is logically ANDed with the destination operand The result is stored in the destination The AND operation results in a 1 bit being stored whenever the corresponding bits in the two operands are both logic ones otherwise a 0 bit value is stored The contents of the source remain unaffected Flags C Unaffecte

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