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CL-PS7111 Evaluation Kit User Manual v1.0, April 1997 (Application
Contents
1. A 2 2 a Reference R81 R82 R83 R84 R85 R93 R99 R105 R104 s2 St TP1 TRI TR2 TR3 TRA TR5 U1 U2 U5 U11 U8 U9 U12 U13 U14 U18 U19 U31 U20 U21 U22 U23 U24 U26 U27 CL PS7111 Evaluation Kit User Manual Revised Januarv 8 1997 January 14 1997 Part 100 KQ x 8 100 KQ x 8 100 KQ x 8 010 0 05 Q 150 Q 9 kQ 9 ka 4 7 KQ SWSPST SWSPST NTP FMMT4124 FMMT4124 FMMT4124 FMMT4124 FMMT4124 MAX756CSA HM51W16160ALTT 7 29LV800BE 29LV800BE MSM7702 01MS MAX148BCAP MSC1192MS K LM339MX 29LV800BF 29LV800BF CL PS7111 CL PS7111 MAX3212CAI S14412DV S14431DV MAX1651CSA MAX608ESA 16426DQ CL PS6700 PC Card PCMCIA Interface APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC CL PS7111 EVAL Board Revised January 8 1997 DEB7111 SCH Revision B Bill of Materials cont January 14 1997 Item Quantity Reference Part 99 1 U28 SI9712DV 100 1 U29 13 MHz 101 1 U30 LM324 102 4 U32 AT29LV040 U33 AT29LV040 U34 AT29LV040 U35 AT29LV040 103 4 WI JMP3 W2 JMP3 W4 JMP3 W6 JMP3 104 2 X1 3 6864 MHz X6 3 6864 MHz 105 2 X2 32 768 kHz X5 32 768 kHz APPLICATION NOTE v1 0 PC Card PCMCIA Interface CL PS7111 Evaluation Kit User Manual CIRRUS LOGIC M Appendix C Schematics Please contact Cirrus Logic for the latest CL PS7111 schematic diagrams 46 PC Card PCMCIA Interface APPLICATION NOTE v1 0 CL PS
2. 9 5 Power Down Whenever the CL PS7111 enters Standby mode the CL PS6700 enters Power Down mode This is because the RUN signal is connected to the PSLEEP L input Ensure that there are no pending transac tions before the CL PS7111 enters Standby mode and that the transaction queue in the CL PS6700 is empty Use any of the GPIO ports instead of RUN PC Card PCMCIA Interface APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 9 6 Clocks When the CL PS7111 is operating at 18 MHz EXPCLK is driven out as the clock for the CL PS6700 The clock can be disabled through the Memory Configuration register If the CL PS7111 is operating at 13 MHz an external oscillator provides the clock on EXPCLK to the CL PS6700 Since the 13 MHz clock can be disabled through the RUN CLKEN output during standby mode ensure that there are no pending transactions April 1997 EY 35 APPLICATION NOTE v1 0 PC Card PCMCIA Interface gt CIRRUS LOGIC CL PS7111 Evaluation Kit User Manual Appendix A Source Address Locator Data sheets and application notes can be downloaded from your board supplier web site Abracon Corporation www abracon com Accelerated Technology Inc www atinucleus com Alps Electric www alps com AMD www amd com AMP www amp com ARM Ltd www arm com Cygnus www cygnus com Maxim www maxim ic com Molex www molex com Oki America I
3. a Selectthe ARMSD setup and the little endian serial port at 9600 baud b Exit and save this configuration Set the BOOTEN jumper W15 Connect the PC from which to download the boot code to the serial port 1 Select 9600 baud Run a terminal program such as Winterm Power down Power up 0 ON DPO JB Press the WAKEUP button S1 At this point the lt character will have been received from serial port 1 10 Send the file BOOTAMDO after receiving lt After 2 Kbytes are sent gt appears on screen The downloaded program begins executing at address 0000 0000 from the on chip SRAM The program also prompts that it is ready to receive data Send the code to download such as ROMU2L or any other program for example the operating system The binary file must contain a header the length the binary file and the destination start address to be loaded See Section 3 4 2 on page 11 APPLICATION NOTE v1 0 EVALUATION BOARD SS CL PS7111 Evaluation Kit User Manual CIRRUS LOGIC 11 Switch W15 to N normal boot 12 Power down 13 Power up 14 Press the WAKEUP button S1 At this point a banner message appears followed by the ARMSD prompt 3 4 4 Start Up Sequence Using Preinstalled Debug Monitor DEMON Use the following procedure to load the start up sequence using the preinstalled debug monitor DEMON ma Install the ARM software development toolkit 2 DOS only Run RECON
4. An inverted RUN signal powers up the MAX608 Note that the reference voltage is also off in Standby mode This is because the debug UART add on mod ule and the associated RS 232 driver MAX212 are still running during that time Since the RUN signal starts just prior to the execution of the first instruction in 18 MHz operation it is important that no accesses to memory or I O devices occur until full power is restored To do this execute out of cache and set up a secondary wakeup source after which the CPU can make memory references In 13 MHz operation with the PLL bypassed the wakeup time is reduced from 10 ms instead of the 250 ms required for 18 MHz operation This allows toggling at a fast rate in and out of the Standby state 6 2 Step Down Converter Connector J9 1 3 mm Circular Connector Pins 1 and 3 Sleeve VEXT Power from AC DC converter 6 to 12 V Pin 2 Center GND The step down converter LM1651 operates from anywhere from Vpp to 16 V and is also referred to as the External power source If VEXT power is on the input EXTPWR is active to the CL PS7111 This protects the CPU from exiting the Standby state if the NPWRFL signal is active The following sections provide a detailed description of the four pins on the CL PS7111 that are dedicated to battery power management MEDCHG BOOTEN This input detects to a switch that signals that a PC Card or other I O card is being removed This input is deglitched so t
5. R53 100 kQ R56 100 kQ R59 100 kQ R60 100 kQ R62 100 kQ R67 100 kQ R68 100 kQ R71 100 kQ 53 16 R4 10 kQ R7 10 kQ R21 10 kQ R24 10 kQ R27 10 kQ R29 10 kQ R43 10 kQ R44 10 kQ R45 10 kQ R69 10 kQ R73 10 kQ R75 10 kQ R89 10 kQ R90 10 kQ R91 10 kQ R95 10 kQ 54 2 R57 47 KQ R6 47 KQ 55 4 R8 100 R33 100 42 A EEE o P__ gt e o o PC Card PCMCIA Interface APPLICATION NOTE v1 0 April 1997 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC CL PS7111 EVAL Board Revised January 8 1997 DEB7111 SCH Revision B Bill of Materials cont January 14 1997 Item Quantity Reference Part R87 100 R92 10 Q 56 1 R10 140kQ 1 R70 120 kQ 57 4 R15 2 2 KQ R28 2 2 KQ R30 2 2 KQ R31 2 2 KQ 58 2 R17 1440 R19 144 Q 59 1 R18 18 KQ 60 1 R20 33 Q 61 2 R22 15 KQ R72 15kQ 62 1 R23 75kQ 63 5 R26 390 kQ R32 390 kQ R40 390 kQ R42 390 kQ R49 390 kQ 64 4 R37 100 2 R61 100 2 R74 100 Q R94 100 Q 65 1 R38 470 kQ 66 1 R47 500 kQ 67 1 R54 270 kQ 68 1 R55 22 kQ 69 1 R58 240 kQ 70 1 R63 200 kQ 71 1 R64 392 kQ 72 1 R65 806 kQ 73 7 R76 100 kQ x 8 R77 100 kO x8 R78 100 kQ x 8 R80 100 kQ x 8 APPLICATION NOTE v1 0 PC Card PCMCIA Interface gt CIRRUS LOGIC CL PS7111 EVAL Board DEB7111 SCH Revision B Bill of Materials cont ltem 74 75 76 77 78 79 85 86 87 88 89 90 92 93 94 95 96 97 98 Quantity Mi A 51 Mi No oak ek es
6. 9 8 1 CL PS7111 DC DC Converter for Positive Ver 29 8 2 CL PS7111 DC DC Converter for Negative Vee 31 9 1 CL PS7111 to CL PS6700 Interconnect Diagram 34 List of Tables Table Page 3 1 Assembly INSTRUCTION iii ata 8 3 2 Boot Software Programs l nanna ann nr nanna nn 10 3 3 Port Allocation Pin Configuration nn 20 3 4 JA CAMEO dE 21 3 5 Compatible Panels nanna 22 3 6 Ji Gonnector PINS iieii iia 22 3 7 J24 Pin CONNECTIONS L ix l ja Fa a a d Raia 23 7 1 Typical Current Values at Various Conditiona sena 27 8 1 Vee Control Circuitry vicario b d dee 28 8 2 Duty Ratio EB ii ai a stigaccecnavin is acre at che T ac ee 29 8 3 Duty Ratio 2 ivi aet EN AEAEE anes eden E ENE neers 30 8 4 Negative Veg Control Circuitry ooo eee nenneennnnnnnnn anna nanna nanna 31 8 5 DC DC Pump Ratio bh 32 9 1 Switch Settings irei tiene b ged 33 APPLICATION NOTE v1 0 List of Figures CL PS7111 Evaluation Kit User Manual Se CIRRUS LOGIC l 1 INTRODUCTION The CL PS7111 evaluation kit is targeted for system designers who are developing CL PS7111 based platforms This kit is also for software developers who plan to port operating systems and applications to the CL PS7111 To use the CL PS7111 evaluation kit the ARM toolkit containing the C compiler linker and assembler debugger and ARM instruction set emulators is required The CL PS7111 evaluation kit is intended to be used with the ARM toolkit running on a PC
7. 9 22 18 6 20 0 20 32 7 18 3 18 56 April EE a yyIyIgeIeIii A 29 ADDI IPATINN NOTE 11 N Dec DC CONVERTER gt CIRRUS LOGIC Table 8 2 Duty Ratio 5 cont Pump Ratio 5 Port PD 7 4 V V 8 16 2 16 45 9 145 14 68 A 12 7 12 85 B 10 98 11 1 C 9 27 9 33 D 7 53 7 57 E 5 7 5 79 F 4 06 4 06 Measured Vee values for a duty ratio of 2 are shown in Table 8 3 Table 8 3 Duty Ratio 2 Port PD 7 4 2 Pump Ratio VEE V CL PS7111 Evaluation Kit User Manual 0 1 2 3 4 5 6 7 8 9 A B c D 27 54 E 27 58 F 27 59 An EE APPLICATION NOTE v1 0 CL PS7111 ii Evaluation Kit User Manual xxT gt CIRRUS LOGIC 8 1 1 Negative Veg Table 8 4 shows the resistors required for the control circuitry on negative Ver Figure 8 2 is a sample schematic for a DC DC converter on negative Ver Table 8 4 Negative Ver Control Circuitry Resistor Function R73 Pull up resistor for negative Ver R53 Pull up resistor for the LM339 open drain output R54 Selects a voltage at the terminal of the comparator where the feedback output switches off high and turns off the Drive output R56 Selects the voltage level on the input of comparator to apply to VREF 1 5 V This resistor network allows Veg to be programmed under software control All outputs low indicate that R62 65 Veg is at max
8. CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 3 1 Main Feature Set The evaluation board has the following features Processing speed 18 432 MHz 13 MHz when using an optional oscillator Flash memory 1or2 banks of 512K x 32 bits 2 Mbyte reprogrammable at 3 V DRAM 1 bank of 1 Mbit x 16 bit 2 Mbyte JEIDA connector DRAM expansion to two banks of 32 bit DRAMs are possible with this connector Power Step up converter from 1 8 to 4 0 to 3 3 V Step down converter from 6 0 to 14 to 3 3 V PC card 3 3 or 5 V from Von LCD bias Vpp to 35 V from 3 3 V positive or negative bias selectable Vpp for PC card from Von Asynchronous serial port two Ports programmable up to 115 kbaud Infrared IrDA compliant 115 kbaud port multiplexed with asynchronous serial port 1 Keyboard Keyboard matrix on daughter card optional PC Card 68 pin card connector fully isolated 3 3 V or 5 V cards are supported Supported by single chip controller CL PS6700 A D 10 bit A D converter 8 channels MAX 148 Codec Telephone codec OKI MSM7702 Speaker With amplifier OKI MSC1192 LCD Three optional LCD connectors Expansion Connector 50 pin expansion connector for add on peripherals 8 bits wide such as UART and SPl compatible peripherals Boot from serial port with 32 bit wide flash APPLICATION NOTE v1 0 EVALUATION BOARD CL P
9. EVAL7111 DSN Orcad Capture for Windows Format schematic EVAL7111 LIB Orcad Library file schematic EVAL7111 BOM Bill of Materials Layout EVAL7111 ASC PADS PERFORM v 6 ASC file layout BATCHL DAT PADS Batch file to generate gerber files 4 2 Key Board The following are the absolute paths of the schematic files available through the Cirrus Logic BBS Path and Filename File Type and Contents schematic KEYB SCH Orcad 386 format use library REFDEBUG LIB schematic KEYB DSN Orcad Capture for Windows Format schematic KEYB LIB Orcad Library file layout KEYB ASC PADS PERFORM v 6 ASC file al BOOT CODE AND DEMON FILES For a complete listing of files see the README file on the BOOT floppy disk DESIGN FILES APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 6 POWER SUPPLY DESIGN The power supply design consists of a number of individual units that provide power from two AA batter ies as well as an AC DC adapter that ranges from 6 to 12 V Backup during sleep mode can be provided from a gold capacitor C33 that keeps the 32 kHz oscillator active or from a lithium battery with some minor rework required NOTE All power rails must be supplied with power It is not recommended to simply provide power to the realtime clock oscillator while core and I O are turned off The power supply is divided into following units Step up converter Step down conv
10. board l AN LCD TOUCH SCREEN D Bus pene 240 100 16 32Bit 320 240 l IEIET 480320 L NOOO CL PS7111 SERIAL FLASH TQFP 208 AWIRE MAX148 4xAT29LVO40A TA SPI A D DIP FLASH 4xAm29LV800B 4MByte E SPEAKER NZ SERIAL JL IXHMSIIGIGOALTT 4WIRE CODEC CODEC OKI lt lt MSM7702 P MICRO JEIDA 88pin DRAM MODULE 32Biv 2Banks CL PS6700 SE MODEM V 34 2 WAY PAGER PCMCIA 10 MODULE SERIAL PORT TYPE Vum ANALOG DIG 1 0 RADIO VF MAX3212 SERIALI RS232 SWITCH SERIAL 2 RS232 1 810 3V EA POWER SUPPLV IR MODULE CS8130M 610 12V Figure 3 1 CL PS7111 Evaluation Board Block Diagram i April 1997 EVALUATION BOARD APPLICATION NOTE v1 0
11. circuits No warranty is given for the suitability of the circuitry or program code described herein for any purpose other than demonstrating functional operation The information contained in this document is subject to change without notice Version 1 0 AN146REV1 APR 97 CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC Table of Contents List OF UE 3 LIST OF Tables aiir i e sa oc 3 1 INTRODUCTION i beka ki abi A ib to saba 4 1 1 Ordering Information ia aiaia da 4 2 EVALUATION KIT CONTENTS ssennnnnnnnnnnnnnnnnnnnnnnnznnnnnnnnnnnnmmmnnzzmzzznnnz 5 2 lt QOPUONS o tt 5 3 EVALUATION BOARD ia anti anka dida pa aa ia ab 6 31 MallEcature Set is ia ai A en A See EE EE 7 3 2 Board RevISIONS 200 8 3 2 1 Software ReViSION caia di 8 3 2 2 Selten Le 8 3 2 3 Stuffing Options a E 8 Sis Board SU a 9 3 3 1 O EEN ENEE EA dee 9 3 3 2 Be RE 9 3 4 SA 9 3 4 1 Boot Program Resize to 2 KDVtES L nn n nn 10 3 4 2 Boot Program File Format s nn E EER 11 3 4 3 Booting with Start Up Sequence from the Serial Port 11 3 4 4 Start Up Sequence Using Preinstalled Debug Monitor DEMON 12 3 4 5 Configure the ARM Debugger for Windows Tool v 2 13 3 0 Board Layout tia ti cea 14 3 6 Memory Architecture 0 snanar cc cnn rra 18 3 6 1 Memory Map in Operating Mode 2 near nn 19 3 6 2 Memory Map in Boot Mode AA 19 3 7 VO Port Allocation sse a A a ete eee
12. 20 3 8 Analog to Digital Converter nanna 21 CC Ne Be 21 3 10 J1 Connector Pinout nanna anna nm n mann nm 22 3 11 J24 Connector RIDE rc s ere Ae raed 23 EE tee ee Eegen 23 d DESIGN FILES eegen 24 4 1 System Board uta i A a 24 4 2 A e ii ira ii a ai LK Br Seared a a ae a ean ct fa ra 24 5 BOOT CODE AND DEMON FILES sssennnnzznnznnznnznnzznnnnnnnnnnnnnnnnnnznzzzz 24 6 POWER SUPPLY DESIGN iii ina nnan nin iEtasnaa aa 25 CH MEET CEET 25 6 2 Step Down Converter 26 7 MEASURING CL PS7111 POWER CONSUMPTION c ccseeessteeeeeees 27 April 1997 Table of Contents APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual 8 DC DC CONVERTER i iii ik e at 28 8 1 Setup Procedure snanar Anna a SAAn A AnnnAnnAnmnznmnnn za 28 8 1 1 Negative AT 31 8 1 2 ON 32 9 PC Card PCMCIA Interface sssrennnnnnnnnnnnnnnnnnnnnnnnnznnnnnnnnnmmnmmmnnnnznnnn 33 9 1 PC Card Power Switches at Multiple Points 33 9 1 1 PG Card PO aia taa ii tii 33 9 2 CL PS7111 to CL PS6700 Interconnect Diagram nn 34 E o e 34 9 4 DMA SUPOT EE 34 95 IN 34 9 85 GIOCKS xads A AT AAA T 35 A Source Address Locator ssssenezznnnnnnannnznnnnnnnnnnnzznnznnnnzznnzzzzznznnznz 36 B Bill Of Materials cono aiii Nee ee ENEE 37 C SCHEMAS sissa en ns i dwa 46 List of Figures Figure Page 3 1 CL PS7111 Evaluation Board Block Diagram sen 6 3 2 Null Modem Cable nn nn nn artna nanna nn nmnn nat n nanna
13. 20 5V 28 V Sharp minor cable adjustment required Ge SE PN CS Ver can be selected and the voltage can be adjusted under software control as described in Section 3 8 3 10 JI Connector Pinout A second interface connector J1 is provided for a custom panel from Cirrus Logic This panel is 240 x 100 pixels and operates on a single 3 3 V supply This panel uses the M signal AC modulation Connect the Cirrus Logic LCD panel 240 x 100 on J1 as shown in Table 3 6 Table 3 6 J1 Connector Pins Pin Number Signal Name 1 3 3V 2 DO Data 0 3 D1 Data 1 4 D2 Data 2 5 D3 Data 3 6 GND Ground 7 FRM Frame 8 GND Ground 9 CL Line Clock 10 GND Ground 11 CL2 Shift Clock 12 GND Ground 13 M Modulation 14 PEO LCD On 15 n ca 16 n c 17 n c e a n c indicates a pin that is a no connect 22 __ _ _ __ _______________________________ o o o _ r pq rirn trn_ April 1997 EVALUATION BOARD APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual 3 11 J24 Connector Pinout The J24 connector is compatible with following Alps panels KHABAAQ02A 320 x 240 KHABAA9O1A 320 x 240 KHABFC901A 160 x 240 KHABFA901A 240 x 160 KHABBB904A 480 x 320 i i Table 3 7 J24 Pin Connections Pin Number Symbol Signal Name 1 V5 Bias Supply Voltage 2 v2 Bias Supply Voltage 3 VEE LCD Driver Supply Volt
14. 5818 25 1 D16 BAT54C 26 2 J1 ZIF17 J15 ZIF17 27 1 J2 ZIF11 28 1 J3 HDR2 29 1 J4 HDR25 30 8 W3 JMP2 J5 JMP2 W7 JMP2 J7 JMP2 W8 JMP2 W11 JMP2 W12 JMP2 W15 JMP2 31 1 J6 PHONOSW 32 1 J8 TFDS3000 33 1 J9 CONAC 34 1 J10 HDR25X2 35 1 J11 PCMCIA68 36 2 J12 AMP557908 1 J25 AMP557908 1 37 1 J13 SM30 PC Card PCMCIA Interface APPLICATION NOTE v1 0 CL PS7111 ii Evaluation Kit User Manual a gt CIRRUS LOGIC CL PS7111 EVAL Board Revised January 8 1997 DEB7111 SCH Revision B Bill of Materials cont January 14 1997 Item Quantity Reference Part 38 1 J14 HDR3 39 1 J16 4HEADER 40 1 J17 JEIDA88 41 1 J18 HDR2x2 42 5 J19 HPPOD20 J20 HPPOD20 J21 HPPOD20 J22 HPPOD20 J23 HPPOD20 43 1 J24 HDR17 44 1 LS1 SPEAKER 45 1 LS2 BUZZER 46 4 L1 FERRITE L4 FERRITE L5 FERRITE L10 FERRITE 47 3 L2 47 uH L3 47 uH L7 47 uH 48 2 L8 22 uH L6 22 uH 49 1 L9 15 uH 50 5 R1 1 kQ R36 1 kQ R96 1 kQ R97 1 kQ R98 1 kQ 51 1 R2 PO 52 24 R3 100 kQ R9 100 kQ R11 100 kQ R12 100 kQ R13 100 kQ R14 100 kQ R16 100 kQ R25 100 kQ APPLICATION NOTE v1 0 PC Card PCMCIA Interface a EE EE gt CIRRUS LOGIC CL PS7111 EVAL Board DEB7111 SCH Revision B Bill of Materials cont CL PS7111 Evaluation Kit User Manual Revised January 8 1997 January 14 1997 Item Quantity Reference Part R34 100 kQ R35 100 kQ R39 100 kQ R41 100 kQ 52 cont R48 100 kQ R50 100 kQ R51 100 kQ R52 100 kQ
15. 7111 Evaluation Kit User Manual i gt CIRRUS LOGIC Notes April 1997 Tee APPLICATION NOTE v1 0 47 PC Card PCMCIA Interface l gt CIRRUS LOGIC Direct Sales Offices Domestic N CALIFORNIA Fremont TEL 510 623 8300 FAX 510 252 6020 S CALIFORNIA Westlake Village TEL 805 371 5860 FAX 805 371 5861 NORTHWESTERN AREA Portland OR TEL 503 620 5547 FAX 503 620 5665 SOUTH CENTRAL AREA Austin TX TEL 512 255 0080 FAX 512 255 0733 Houston TX TEL 281 257 2525 FAX 281 257 2555 NORTHEASTERN AREA Andover MA TEL 978 794 9992 FAX 978 794 9998 SOUTHEASTERN AREA Raleigh NC TEL 919 859 5210 FAX 919 859 5334 Boca Raton FL TEL 561 395 1613 FAX 561 395 1373 CL PS7111 Application Note AN PS1 v1 0 International CHINA Beijing TEL 86 10 6428 0783 FAX 86 10 6428 0786 FRANCE Paris TEL 33 1 48 12 2812 FAX 33 1 48 12 2810 GERMANY Herrsching TEL 49 81 52 92460 FAX 49 8 1 52 924699 HONG KONG Tsimshatsui TEL 852 2376 0801 FAX 852 2375 1202 JAPAN Tokyo TEL 81 3 3340 9111 FAX 81 3 3340 9120 KOREA Seoul TEL 82 2 565 8561 FAX 82 2 565 8565 SINGAPORE TEL 65 743 4111 FAX 65 742 4111 TAIWAN Taipei TEL 886 2 2718 4533 FAX 886 2 2718 4526 UNITED KINGDOM London England TEL 44 01628 472211 FAX 44 01628 486114 High Value Svstems in Silicon Cirrus Logic is a premier supplier of advanced int
16. CL PS7111 Ti CIRRUS LOGIC j Application Note AN PS1 l CL PS7111 Evaluation Kit User Manual Portable Svstems Cirrus Logic Inc Scope and Applicabilitv The CL PS7111 evaluation kit Order no CL PSK7111DMO1 is offered bv Cirrus Logic to assist svstem designers in building CL PS7111 based systems and developing and debugging drivers and application programs for this highly integrated microcontroller The evaluation kit provides software and hardware support to evalu ate performance and measure power consumption under various conditions This kit contains a reference board to be used as the starting point for new designs A system designer can elect to use the board as the motherboard and simply add application specific I O modules to the board For example the designer of a two way pager can incorporate the pager functionality as an I O module attached to the basic board All engineering design collateral is provided in this kit System Requirements The preloaded debug monitor requires a PC running the symbolic debug monitor PC DOS or Windows 95 Contact ARM at www arm com or Cirrus Logic to order the ARM toolkit containing a C compiler linker and assembler Familiarity with the ARM tools such as ARMSD and or Tool 200 is required to use the evaluation board Copyright 1997 Cirrus Logic Inc All rights reserved This document describes a potential application of Cirrus Logic Inc integrated
17. FIG from the ARM PC386 directory a Select ARMSD setup and the little endian serial port at 9600 baud A higher baud rate can be used but ARMSD is not reliable above 9600 baud on certain host systems b Exit and save the configuration 3 Connect the serial port labeled SERIAL 2 with the supplied null modem cable to one of the PCs serial ports 4 Connect the power supply 5 Launch ARMSD on the PC a If connected to Port 1 COM1 type ARMSD b If connected to Port 2 COM2 type ARMSD p 2 6 Press the RESET button S2 7 Press the WAKEUP button S1 If system does not wake up press the RESET button followed by WAKEUP Wait a few moments for the debug monitor to complete memory test and initialization Then the initial message reporting the DRAM size 0x20 0000 and the debug monitor version appears Ensure that the memory size is correct If the sign on message does not appear but instead there is an lt ARMSD gt prompt the parameters in RECONFIG to the serial port are not properly set EVALUATION BOARD APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 3 4 5 Configure the ARM Debugger for Windows Tool v2 1 The ARM debugger for Windows ADW must be configured for remote target Use the following proce dure 1 O AREN Choose Configure Debugger from the Option menu The Configurre Debugger Option menu opens Click the Target button to move to the Remote Debug Interface win
18. S7111 Evaluation Kit User Manual l gt CIRRUS LOGIC The debug monitor that is preprogrammed into the flash memory requires that a PC be connected through a serial cable on serial port 2 and that the PC run the ARM symbolic debugger Other operating systems are downloadable as described in Section 3 4 on page 9 3 2 Board Revisions The board described in Rev 0 2 of the Evaluation Kit User s Manual is Revision A The CL PS7111 is on a socket and can be replaced with the current revision A separate errata sheet is also available Please contact Cirrus Logic for the latest silicon status 3 2 1 Software Revision There has been a change in the ARM compiler in Toolkit v2 0 and later Please note that assembly instruc tion ADR is no longer supported when addresses are defined using equates Use the LDR instruction as shown in Table 3 1 Table 3 1 Assembly Instruction Old New ADR R4 LCD address LDR R4 LCD address 3 2 2 Endian Operation The CL PS7111 is a bi endian processor however all supplied programs operate in Little Endian mode No hardware change is required for Big Endian mode The byte lane switch is performed inside the mem ory controller 3 2 3 Stuffing Options A number of stuffing options are available e Clock source 18 MHz from 3 6864 MHz crystal 13 MHz from oscillator e Vee control Positive or negative e LCD panel 3 3 V panel 240 x 100 Other panels can
19. S7111 device provides dedicated support for DC DC conversion through two dutv cvcle programmable 96 kHz clocks One set of clocks can be used for keeping a constituent Ves supply voltage for the LCD panel the second set can be used to generate the programming voltage Vpp These clocks can also be used for the voltage of the backlight The schematic in Figure 8 1 is for positive and negative Ver control circuitry Vee must be closely con trolled over a relativelv wide range to adjust for voltage and temperature variations The reference board is designed to select positive or negative Ve through the proper setting of solder joints W1 W2 W7 and w8 The four output ports PD 7 4 can change Vee with software control The pump ratio duty cycle is selected so that sufficient current is provided and the inductor is not going into saturation In the example in Table 8 1 a pump ratio of four was sufficient Table 8 1 Ver Control Circuitry Resistor Function R75 Pull down resistor for positive Vee R53 Pull up resistor for LM339 open drain output R54 Selects a voltage at the 4 terminal of the comparator where the feedback output switches off high and turns off the Drive output Selects the voltage level on input of comparator to apply to Vger 1 5 V for 28 volts R55 22 kO Adjust SS this resistor to icrease decrease the voltage range a lower value increases the voltage range This resistor network enables Veg to be prog
20. age 4 Vop Logic Supply 3 3 V 5 FRM Frame Signal 6 GND Ground 7 CL1 Line Clock 8 GND Ground 9 M AC Signal 10 PEO Display on Signal 1 on 11 CL2 Shift Clock 12 V4 Bias Supply Voltage 13 V3 Bias Supply Voltage 14 D3 Data 3 15 D2 Data 2 16 D1 Data 1 17 DO Data 0 3 12 Codec CIRRUS LOGIC The schematics and bill of materials in this document shows the part number of the codec MSM7702 The codec interface is directly compatible without interface logic The power amplifier MSC 1192MS must be turned off at the end of every transmission to silence the speaker and conserve power The gain of the microphone can be adjusted by the R6 100 ka resistor A buzzer is optional Since the buzzer output goes into the digital input of the power amplifier it is not required if a speaker is present To enable the digital input the STDY input of the MSC1192MS must be high April 1997 ER 2 APPLICATION NOTE v1 0 EVALUATION BOARD CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC 4 DESIGN FILES 4 1 System Board The schematics can be found in one of two OrCAD formats The design database file is provided as an ASC file that can if necessary be converted into other formats The following are the absolute paths of the zipped schematic files provided in this kit Path and Filename File Type and Contents schematic EVAL7111 SCH Orcad 386 format use library REF7110D LIB schematic
21. be connected on jumpers J2 and J15 e Buzzer Use loud speaker instead of buzzer e DRAM Use 32 bit wide banks as supported on the JEIDA connector Though the board could also be stuffed with one bank of 16 bit flash memory in Bank 0 the reprogram ming of AMD flash must be unlocked by a proper address data sequence cannot be performed Use 32 or 8 bit wide banks of AMD flash memory If 16 bit wide flash must be used then use devices that require a programming voltage Vpp EVALUATION BOARD APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 3 3 Board Setup This serial port connection is through the supplied null modem cable to the port marked SERIAL 2 and to the PC host port COM1 or COM2 AMP 5577715 1 SUB D FEMALE 9 PIN RxD 2 13 TxD 3 0 2 DTR A l 6 GND 5 5 DSR 6 l4 RTS 7 0 8 CTS 8 17 Figure 3 2 Null Modem Cable 3 3 1 Power Two AA batteries connected to J3 or a 9 V AC DC adapter connected to J9 can provide power through a 1 3 mm circular connector GND is on the center pin When using a battery connected to J3 ensure the polarity is correct 3 3 2 LCD Connect the provided LCD module to the 17 pin flat cable on J1 Other panels can be connected to the 11 pin connector J3 and the 17 pin connector J15 The pinout of these connectors are compatible with some Sharp and Alps panels respectively Ensure that the polar
22. dow Click Add Select remote_d from the Target Environment window Click Configure Select the desired baud rate in the Configure window APPLICATION NOTE v1 0 EVALUATION BOARD CL PS7111 Evaluation Kit User Manual CIRRUS LOGIC l 3 5 Board Lavout The following two schematic diagrams present board lavout recommendations Please contact Cirrus Logic for the latest schematic diagrams EVWAI HATION RNADN ADDIIPATIDN NOTE 11 N CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC April 1997 p nn APPLICATION NOTE v1 0 EVALUATION BOARD 16 l CL PS7111 Evaluation Kit User Manual CIRRUS LOGIC M i April 1997 EVALUATION BOARD APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC The following lists the reference designators used in the schematics Designator Part W Permanent selectors normally the solder bridges J Jumper or connectors S Switches TP Test points The following lists the reference designators for jumpers and solder bridges Designator Function Wi Vee voltage selection W2 Vee voltage selection W3 aLAW uLAW selection W4 PC Card data bus power selector W6 Bank 0 select 16 32 bit W7 Vee voltage selection W Vee voltage selection W11 Boot ROM enable for 32 pin DIP option W12 Interrupt selection for PC Card W13 CASO W14 CAS1 W15 Boot select The following lists the r
23. eference designators for connectors Designator Function JI 17 pin LCD connector J2 11 pin LCD connector J3 Batterv connector J4 Keyboard connector J5 Optional speaker J6 Ear phone connector J7 Microphone connector J8 IR module J9 1 3 mm external supplv connector J10 Expansion connector J11 68 pin PC Card connector J12 Serial Port 1 RS 232 levels J13 Expansion ROM connector not populated J14 Serial Port 2 TTL J15 LCD ZIF connector for Alps panels J16 Touch panel J17 88 pin JEIDA DRAM module APPLICATION NOTE v1 0 EVALUATION BOARD CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC Designator cont Function J19 L A control signals J20 L A Data 15 0 J21 L A Address 15 0 J22 LIA Address 27 16 J23 LIA Data 31 16 J24 LCD signals header J25 Serial Port 2 RS 232 levels The following lists the reference designators for the switches Designator Function S1 Manual wake up 2 User reset 3 6 Memory Architecture The memory consists of two banks of flash and one bank of 16 bit wide DRAM each 2 Mbytes Addi tional DRAM can be added on a JEIDA memory module The boot flash can be 16 bits wide however 16 bit flash memory cannot be written to because of the way the AMD flash is reprogrammed by applying a sequence of memory addresses and data An optimal con figuration uses 8 bit wide memory If 16 bit wide memory is required use memory with Vpp enabled pro gramming The standby curr
24. egrated circuits that combine mixed signal processing precision analog techniques embedded processors and application specific algorithms into svstem on a chip solutions for existing and emerging growth markets Enhanced bv strong svstems expertise in selected markets the companv s products add high value to major brands worldwide in magnetic and optical storage networking communications consumer professional audio video and imaging and ultra precision data acquisition Cirrus Logic s manufacturing strategv ensures maximum product qualitv and availabilitv as well as access to world class processing technologies through joint ventures with IBM and Lucent Technologies Contact one of our systems and applications specialists to see how your company can benefit from the high value Cirrus Logic adds to its customers products Copyright 1997 Cirrus Logic Inc All rights reserved Cirrus Logic Inc has made best efforts to ensure that the information contained in this document is accurate and reliable However the information is subject to change without notice No responsibility is assumed by Cirrus Logic Inc for the use of this information nor for infringements of patents or other rights of third parties This document is the property of Cirrus Logic Inc and implies no license under patents copyrights or trade secrets Cirrus Logic and Crystal are trademarks of Cirrus Logic Inc which may be registered in some jurisdictions Ot
25. ent of the complete system is determined by the DRAM current in self refresh mode This is why a low refresh current is important Additional RAM can be placed on the add on debug module using a serial EEPROM EVALUATION BOARD APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 3 6 1 Memory Map in Operating Mode Physical Address Space 0000 0000 0000 0000 001F FFFF 1000 0000 101F FFFF 0000 3000 0000 4000 3000 0000 300F FFFF 4000 0000 43FF FFFF 4400 0000 47FF FFFF 4800 0000 4BFF FFFF 6000 0000 6000 07FF 7000 0000 6000 007F 8000 0000 8000 1800 C000 0000 C001F FFFF C000 0000 C001 FFFF C002 0000 C002 7FFF C002 8008 C002 8000 C01F FFFF o go Description Starting address of debug monitor 2 Mbyte flash 3 V Bank 0 2 Mbyte flash 3 V Bank 1 Location of the character set Page tables External serial port expansion space PC Card attribute space 8 bits wide PC Card memory space 8 16 bits byte word addressable PC Card I O space 8 16 bits On chip SRAM 2 Kbytes On chip boot code 128 bytes CL PS7111 registersa 2 Mbyte DRAM LCD buffer default addressb Work area for debug monitor Applications program start address DRAM used by software Refer to the CL PS7111 Data Book for complete register descriptions The DRAM is a 16 Mbit DRAM organized as 12 row addresses and 8 column addresses In this non square configuration the memory controller split
26. erter Backup supply gold capacitor or lithium battery PC Card supply Ver for LCD Vpp for PC Card There is also a bias generator for the Alps LCD panels This bias generator divides Ves appropriately to supply V2 V5 for the panel The CL PS7111 is in any of three modes 1 Boot mode Internal boot ROM at location 0x0000 0000 loads 2 Kbytes of data from UART1 at 9600 baud The memory is remapped 2 3 Operating modes a Run mode CPU on LCD on b Idle mode CPU off LCD refresh on c Standbv mode CPU off LCD refresh off and DRAM in the self refresh state Test modes NOTE There are several test modes that are described in detail in the CL PS7111 Data Book 6 1 Step up Converter Connector J3 Pin Header Pin 1 VBATT Battery voltage between 2 3 V target Use FET U26 with low UGS such as Si6426 Pin 2 GND The main power should be provided from two alkaline AA batteries The supply is in the range of 2 3 V depending on the remaining charge The step up converter U24 MAX608 can be turned off during power down only when the CL PS7111 is in the Idle mode APPLICATION NOTE v1 0 POWER SUPPLY DESIGN CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC In Idle mode the power required for the entire system is largely determined by the power down current of the DRAMs which can be put into the self refresh state Typically the leakage current of the entire system is between 50 300 UA
27. hat a mechanical switch can be used When this input is low at power up the CL PS7111 boots up from the on chip ROM and loads 2 Kbytes of data from UART 1 at 9600 baud BATOK This signal is derived from a comparator that is set to switch when the main batterv dies A transition to low generates a FIQ interrupt The O S must ensure that the svstem powers down into Standbv mode so as to not entirelv drain the batterv Logic integrated in the CL PS7111 prevents the svstem from starting up unless the power fail condition NPWRFL not active is removed NEXTPWR This input must be driven when an external power supply other than the main battery is powering the system Only when this input is high and NPWAFL is not active will the system exit Standby mode This prevents the system from attempting to wake up when the main battery is dead or fatally drained BATCHG This input when asserted will not generate an interrupt It signals that there is no battery present lt can be generated by an external comparator that senses battery voltage NPWRFL This input immediately places the system in Standby mode It will first sense that the DRAM access is complete and placed in self refresh mode and reset the CPU 26 5 lt ___RQRRQRQRQR o 2 Q P__ a _ o o oo o r r zz April 1997 POWER SUPPLY DESIGN APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual j gt CIRRUS LOGIC 7 MEASURING CL PS7111 POWER CONSUMPTION The c
28. her trademarks in this document belong to their respective companies CRUS and Cirrus Logic International Ltd are trade names of Cirrus Logic Inc Cirrus Logic Inc 3100 West Warren Ave Fremont CA 94538 TEL 510 623 8300 FAX 510 252 6020 Publications Ordering 800 359 6414 USA or 510 249 4200 Worldwide Web http www cirrus com 456700 001
29. ides a fully v2 1 com pliant PC Card interface including software controlled DMA and mixed voltage operation on a small foot print package During Sleep mode this controller is not drawing any measurable current while still signaling a card change condition Two interrupts could be used going to the CL PS7111 but for all exam ples in this application only PIRQ_L is connected to EINTI 9 1 PC Card Power Switches at Multiple Points First turn the power on for converter U1 and set for 5 V operation see PB4 and PD1 Next Vpp must be set to 5 V as controlled by the on chip DC DC converter Finally to turn on the appropriate switch or switches the MOSFET switch U28 must be controlled by writing the Power Management register of the CL PS6700 Table 9 1 Switch Settings Vpp Vpc S4 S3 S2 S1 5V 5V 0 1 Mos 0 5V 3V 1 0 Vpc 0 12V 5V 0 1 TA 1 12V 3V 1 0 Vpc 1 The CL PS6700 operates on split power planes to isolate the PC Card slot from the system There are a number of internal pull up resistors and logic that must operate if power to the CL PS6700 is off This also requires that the applied VDD HI signal is higher than the card voltage or Vpp respectively A Schottkv diode D16 in the power path assures that the VDD HI signal selects the higher of either the card voltage 3 3 or 5 V or Vpp 9 1 1 PC Card Power In most applications a 200 mA power source is sufficient to drive a PC Card To optim
30. imum Turning on the outputs increases the voltage and therefore decreases Ver GND VDD L3 R53 UD 47uH 100k D12 VEE H D 1N5818 TRI R74 PNP de DRIVEO C18 d 100 DRIVEL 15 B ER 10uF R54 DRIVEL 330k 82 FBO VREF o VDD Ul3D FBI 80 FBI 11 13 GND GND 10 eeh RB LM339 10k R56 o e CH R65 806k VDD 56 Mi R63 200k 54 R62 100k 53 100n R64 392k 55 CL PS7111 Figure 8 2 CL PS7111 DC DC Converter for Negative Ver ADDI IPATIDN NOTE 11 N Dec DC CONVERTER CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC 8 1 2 Vpp Control Vpp is controlled by DRIVEO The circuitry is designed to turn on with 5 or 12 V If PD6 is high the tran sistor TRA turns on This determines Vpp for 12 V by switching R57 in parallel to R59 If TR4 is turned off Vpp is set to 5 V Turning the pump ratio to 0 turns off the U21 switch and Vpp is effectively turned off The DC to DC pump ratio PR if set to 5 yields adequate power Table 8 5 DC DC Pump Ratio 5 Von PR PB3 0 PB3 1 Load Resistor 3 6 V 4 5 6V 12 78 V 1 2 KQ 3 6 V 5 78 V 12 98 V 1 2 KQ 3 6 V A 6 8 V 14 22 V 1 2 KQ DC DC CONVERTER APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 9 PC Card PCMCIA Interface The PC Card interface consists of the single chip controller CL PS6700 that prov
31. ity for Veg is properly set for panels that require Ver for contrast control Solder bridges W1 W2 W7 and W8 must be properly set and some resistors must be properly stuffed refer to legend included in the schmematics in Section 3 5 on page 14 3 4 Boot Sequence The on chip boot program can be activated by pulling MEDCHG BOOTEN low at power up This allows code to be easily loaded into the flash memory Use UART Port 1 of the CL PS7111 to boot up The stan dard setting is 9600 baud 1 start bit 1 stop bit and no parity The evaluation kit includes a modified ver sion of the ARM debug monitor ROMU2L preloaded into the flash memory The debug monitor operates from UART2 An optional add on board can be connected to the 50 pin con nector J10 If it is necessary to operate the debug monitor from the serial port on this module to free UART2 then the program ROMDBL must be loaded into the flash memory The on chip boot code executes at power up when the boot is enabled The MEDCHG BOOTEN pin must be low at the rising edge of POR An on chip boot program code is executed as discussed in the CL PS7111 Data Book This code loads a 2 Kbyte file into the on chip SRAM of the CL PS7111 jumps to APPLICATION NOTE v1 0 EVALUATION BOARD CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC the beginning of the 2k block and executes the loaded program that in turn loads a debug monitor Such as DEMONU2L or an operating
32. ize the requirement the following exchangeable converters can be used e MAX858 upto 50mAat5V e MAX856 upto 100 mA at 5 V e MAX756 up to 200 mA at 5 V April 1997 _ A _ __ _ _ _ _ __ _ _ __Q_ _ __ _ _______zro_aa AS 33 APPLICATION NOTE v1 0 PC Card PCMCIA Interface CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC 9 2 CL PS7111 to CL PS6700 Interconnect Diagram SYS_RES_L RESET_L EXPCLK PCLK NCSIAJ PCE L WRITE PTVPE Q Q D PB 0 PRDY 3 3 FS gt 8 gt D E ll Hi NEINT2 PIRQ L 77 P D o a o r fe o a a RUN PSLEEP_L o o O _ Drt5 0 MD 15 0 Figure 9 1 CL PS7111 to CL PS6700 Interconnect Diagram 9 3 Interrupts The two interrupt outputs of the CL PS6700 are open drain and must to be pulled up An interrupt in the CL PS6700 can be promoted to FIQ status that is the status change may cause a fast interrupt or one separated out for fast interrupt response Connect W12 to wire the FIQ output on the board to the external EXFIQ interrupt Since EXFIQ can also be used by the expansion board ensure it is being driven by an open drain output to make the wire OR connection 9 4 DMA Support The PDREQ L output of the CL PS6700 is pulled high on the board open drain output If DMA is required connect this output to an interrupt on the CL PS7111 Then DMA can be supported by software emulation use EXFIQ PDREQ_L can also be used as a GPIO
33. nF C22 100 nF C23 100 nF C24 100 nF C30 100 nF C38 100 nF C39 100 nF C43 100 nF C44 100 nF C45 100 nF C48 100 nF C63 100 nF C66 100 nF C68 100 nF C73 100 nF C79 100 nF 5 4 C18 47 pF C60 47 pF C93 47 pF C94 47 pF 6 13 C25 1 nF C26 1 nF C27 1 nF PC Card PCMCIA Interface APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC CL PS7111 EVAL Board Revised January 8 1997 DEB7111 SCH Revision B Bill of Materials cont January 14 1997 Item Quantity Reference Part C28 1 nF C36 1 nF C50 1 nF C51 1 nF 6 cont C52 1 nF C53 1 nF C54 1 nF C55 1 nF C56 1 nF C57 1 nF 7 1 C33 0 22 F 8 2 C34 1 uF C87 1 uF 9 4 C37 47 uF C41 47 uF C74 47 uF C75 47 uF 10 1 C59 15 pF 11 2 C72 0 33 uF C71 0 33 uF 12 3 C76 33 UF C77 33 uF C81 33 uF 13 2 C80 4 7 uF C78 4 7 UF 14 2 C86 0 47 UF C85 0 47 uF 15 2 C88 0 1 uF C89 0 1 uF 16 2 C90 3 3 UF C91 3 3 UF 17 1 C92 1 uF 16V 18 4 C97 4 7 uF 35 V C98 4 7 uF 35 V C99 4 7 uF 35 V C100 4 7 uF 35 V APPLICATION NOTE v1 0 PC Card PCMCIA Interface CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC CL PS7111 EVAL Board Revised January 8 1997 DEB7111 SCH Revision B Bill of Materials cont January 14 1997 Item Quantity Reference Part 19 1 D2 MAX809R 20 4 D3 BAV70 D4 BAV70 D5 BAV70 D7 BAV70 21 5 D6 1N5817 D10 1N5817 D13 1N5817 D14 1N5817 D15 1N5817 22 2 D8 1N4148 D9 1N4148 23 1 D11 14V 24 1 D12 1N
34. nc www oki com Temic www temic com Supplier of crystals and oscillators Supplier of the Nucleus O S Supplier of LCD panels and keyboards Supplier of flash memory Supplier of connectors Supplier of CPU support tools Suppler of development software tools Supplier of power ICs Supplier of connectors Supplier of codecs Supplier of Power MOSFET PC Card PCMCIA Interface APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC Appendix B Bill of Materials The bill of materials is in the DEB7111 BOM file CL PS7111 EVAL Board Revised January 8 1997 DEB7111 SCH Revision B Bill of Materials January 14 1997 Item Quantity Reference Part 1 1 CH1 100 pF 2 26 C1 10 nF C10 10 nF C15 10 nF C16 10 nF C17 10 nF C19 10 nF C20 10 nF C21 10 nF C29 10 nF C31 10 nF C32 10 nF C35 10 nF C40 10 nF C42 10 nF C47 10 nF C49 10 nF C58 10 nF C62 10 nF C64 10 nF C65 10 nF C67 10 nF C69 10 nF C70 10 nF C83 10 nF C84 10 nF C96 10 nF APPLICATION NOTE v1 0 PC Card PCMCIA Interface CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC CL PS7111 EVAL Board Revised January 8 1997 DEB7111 SCH Revision B Bill of Materials cont January 14 1997 Item Quantity Reference Part 3 4 ca 2 2 uF C3 2 2 UF C61 2 2 UF C82 2 2 UF 4 25 C4 100 nF C5 100 nF C6 100 nF C7 100 nF C8 100 nF C9 100 nF C11 100 nF C12 100 nF C13 100 nF C14 100
35. power shutdown converter PB4 Input Standard O PB4 0 turn off PC Card power 1 turn on PC Card power Power telephone codec MSM7702 PB5 Input Standard O PB5 0 turn off codec 1 turn on codec Power speaker amplifier PB6 Input Standard O PB6 0 turn off amplifier digital input on 1 turn on amplifier digital input off Power A D converter PB7 Input Standard O PB7 0 turn off A D converter 1 turn on A D converter PDO Output low Standard O RTS Request to send output active high PC Card voltage select PD1 Output low Standard O DTR 0 enable 5 V 1 enable 3 3 V Serial port off active low PD2a Output low Standard O PD2 0 disable RS 232 driver 1 enable RS 232 driver PD3 Output low Standard O PD3 Expansion connector ae Output low Standard O PD4 7 LCD contrast control LCD Display Signal PEO Input Standard O PEO 0 disable LCD off 1 enable LCD on EVALUATION BOARD APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC Table 3 3 Port Allocation Pin Configuration cont Port Reset Sate Drive Direction Signal Description IR transmit enable PE1 Input Standard O PE1 0 enable 1 disable PE2 Input Standard O PE2 TSPX drive panel a Since the on chip boot program expects data on serial Port 1 the RS 232 driver must be enabled U20 is enabled by port PD2 which is an output after power up The optimal solution is
36. rammed under software control All outputs low indicate that R62 to R65 Veg is at maximum Turning on the outputs increases the voltage at the comparator decreasing Veg 8 1 Setup Procedure Assuming that the nominal Veg voltage for a given LCD is 28 V and the range is from 27 29 V do the following to ensure sufficient contrast control range wh Connect a load resistor at C2 to force application of a 2 5 mA current or whatever the typical value for the panel is Program the Pump Control register to 5 Set PD 7 4 to high Set R55 so that minimum Veg is 27 V 9 2 0 n Set PD 7 4 to 1111 Ver should exceed 29 V 28 E el April 1997 DC DC CONVERTER APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC VDD VDD L3 R53 suy ATUH 100k D12 VEE E H 3 1NS818 R74 i 16 DRIVEO TRI qa NPN 100 DRIVEL 15 cn R54 DRIVE 10uF 330k 8 ad ki FBO VREF 1 GND UBA FBI a0 FBI 4 GND GND 5 g eet Pa RIS E 100k R55 3 b Cu R65 806k GND 6 R64 302K 5 Ven 100n 3 R63 200k 7 PD R62 100k 3 PDS GND GND P TL PSTITI Figure 8 1 CL PS7111 DC DC Converter for Positive Ver Measured Ver values for a dutv ratio of 5 are shown in Table 8 2 Table 8 2 Duty Ratio 5 Pump Ratio 5 Port PD 7 4 V V 0 30 8 31 12 1 29 04 29 34 2 27 2 27 48 3 25 4 25 70 4 23 6 24 0 5 21
37. s the memory into eight 256 Kbyte segments with equal size gaps between the segments To get a contiguous memory segment use the MMU to map pages of physical mem ory into the virtual address space of the CPU The page tables starting at location 0x4000 describe page addresses protection status and cacheability of individual pages 3 6 2 Memory Map in Boot Mode The memory map is different if the system is booted when the MEDCHG signal is low All memory spaces are selected through CSO CS5 the on chip memory space in address space CS7 and the SRAM at CS6 are reversed Therefore the boot code appears at location 0x0000 0000 while the on chip SRAM appears at 0x1000 0000 The DRAM and on chip registers are not remapped April 1997 APPLICATION NOTE v1 0 EVALUATION BOARD 3 7 I O Port Allocation CIRRUS LOGIC CL PS7111 Evaluation Kit User Manual Table 3 3 shows allocation pin configuration and function for the I O port Table 3 3 Port Allocation Pin Configuration Port Reset Sate Drive Direction Signal Description PA 7 0 Input Standard ROWT 7 0 Keyboard row input pulled down by R81 resistor network PBO Input Standard 1 0 PBO PRDY of PC Card controller CL PS6700 PB1 Input Standard 1 0 PB1 TSMY drive Volume control PB2 Input Standard O PB2 0 high volume 1 low volume PC Card Vpp PB3 Input Standard O PB3 0 enable 12 V 1 enable 5 V PC Card
38. system The loaded code is referred to as the secondary boot code This code actually boots the operating system and programs the flash The file size of BOOTAMDO is exactly 2048 bytes and it always uses UART1 This program can be customized if another interface is selected such as the IrDA port or a PCMCIA flash card The code is stored into the on board flash memory beginning at memory address space 0 Once the code is successfully loaded the system mustbe powered down and the boot switch jumper removed the MEDCHG BOOTEN signal must be high On the next power up the program executes from mem ory address space 0 out of Flash Bank 0 Two separate programs are provided for Bank 0 and Bank 1 The operating system normally provides the flashing other than the mandatory boot block If the DEMON is running use the supplied program FLASH to erase and program individual sectors Table 3 2 Boot Software Programs Program Function BOOTAMDO Initial program that downloads to SRAM must be exactly 2 Kbytes downloads code into Bank 0 BOOTAMD1 Initial program that downloads to SRAM must be exactly 2 Kbytes downloads code into Bank 1 ROMU2L DEMON uses UART2 little endian ROMDBL DEMON uses add on module little endian FLASH Program executes under DEMON erases and programs flash memory 3 4 1 Boot Program Resize to 2 Kbytes The initial boot program that is loaded into the on chip SRAM must be exac
39. tly 2 Kbytes If the BOOTAMDO program is compiled and linked the size must be adjusted to meet this parameter To do this simply load the program with DEBUG into memory adjust CRX to 800 and write back the file The following example code shows this sequence DEBUG BOOTAMDO RCX lt 800 W NOTE The memory map of all memory selected by CSO through CS5 and internal CS6 and CS7 areas is reversed Bank 0 CS0 is located at 0x7000 0000 during boot EVALUATION BOARD APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual i gt CIRRUS LOGIC 3 4 2 Boot Program File Format Once BOOTAMDO has been loaded into SRAM and given control by the boot loader The program prompts for the dile name containing the binary The format for this file is e 4 bytes first address Little Endian e 4 bytes length of data in bytes Little Endian The following example code is a script for adding header and length information to the top of the file using DOS debug commands e 8 00 00 00 00 00 cO 00 00 rex c008 nroml bin wcs f8 q 3 4 3 Booting with Start Up Sequence from the Serial Port In this mode the on chip boot program loads the boot code into the on chip SRAM from serial port 1 then loads a program such as the debug monitor into flash The following is a procedure to load the boot pro gram 1 Install the ARM software development toolkit 2 DOS only Run RECONFIG from the ARM PC386 directory
40. to use PB2 with a pull up resistor so that the RS 232 driver is enabled and use PD2 as volume control port 3 8 Analog to Digital Converter A 10 bit A D converter MAX148 is used in the board design This is actually a 12 bit converter and must be set up for 128 kHz ADCCLK a frame length of 24 and unipolar input Connect a potentiometer or a waveform generator on R47 with a maximum amplitude of 1 5 V For further information refer to the MAX148 data sheet 3 9 LCD Interface There is no industry standard for an LCD panel pinout Operating voltages as well as interface connec tors vary from supplier to supplier One of the more common pinouts is J2 with pin assignments as shown in Table 3 4 Table 3 4 J2 Connector Pins Pink Svmbol Signal Name 1 FRM Frame Signal 2 CL1 Line Clock 3 CL2 Shift Clock 4 PEO LCD on signal if high 5 Von 3 3 V 6 GND Frame Signal 7 VEE Selectable from approximately 30 V to 30 V 8 DO Data 0 9 D1 Data 1 10 D2 Data 2 11 D3 Data 3 APPLICATION NOTE v1 0 EVALUATION BOARD CL PS7111 Evaluation Kit User Manual l gt CIRRUS LOGIC The panels shown in Table 3 5 can be connected and are available from Cirrus Logic upon request These two panels are 5 V and are for evaluation only Contact your supplier for availability of 3 3 V panels Table 3 5 Compatible Panels Supplier Type Size Vpp VEE Sharp LM48014F 480 x 3
41. urrent supply of the CL PS7111 is separated into I O pad core 32 kHz oscillator and 3 6864 MHz PLL oscillator nodes The current drawn by the CL PS7111 can be observed by a mA meter connected to L1 L4 and L5 These are usually bridged by solder bumps No filters are required in the supply Use the POWER program to cycle through the different power states The mA meter can be connected to solder pads L4 and L5 to measure the oscillator and core currents respectively To measure the 32 kHz oscillator current a mA meter is required in place of D6 C33 must be removed so as not to measure the leakage current Ensure that the meter switch is uninterrupted when changing range The current can change by three orders of magnitude The current drawn depends on how individual modules are activated Some typical values are shown in Table 7 1 The values may change depending on the programming conditions Table 7 1 Typical Current Values at Various Conditiona Node Name Name Run Idle Standby UO VDDE lt 15 mA lt 1 mA lt 5 pA Core VcoRE lt 3 mA lt 2 mA lt 1 pA 32 kHz oscillator V30K lt 10 pA lt 10 pA lt 10 pA 3 6864 MHz PLL oscillator Vosc lt 1 2 mA lt 1 2 mA lt 1 pA Total approximate lt 30 mA lt 15 mA lt 17 pA April 1997 ny ig AA 2 APPLICATION NOTE v1 0 MEASURING CL PS7111 POWER CONSUMPTION ECH CL PS7111 EE CIRRUS LOGIC Evaluation Kit User Manual 8 DC DC CONVERTER The CL P
42. with DOS Windows 3 1 or Windows 95 installed 1 1 Ordering Information The following presents part numbering ordering information e CL PS7111 Evaluation Kit CL PS7111 DMBDO1 e ARM toolkit PSKARMTOOL 01 INTRODUCTION APPLICATION NOTE v1 0 CL PS7111 Evaluation Kit User Manual 2 EVALUATION KIT CONTENTS The evaluation kit contains CL PS7111 evaluation board Kevboard XN key matrices LCD Panel 240 x 100 pixels 3 3 V Cirrus Logic or 320 x 240 pixels 3 3 V Alpen Maxim data sheets Step up down converter A D converter Oki America Inc data sheets Telephone codec MSM7702 Speaker amplifier MSC1192 ARM710 core data book 9 V AC DC adapter CL PS7111 demonstration program disk Schematic layout disk CL PS7111 data book 2 null modem cables ARM debug monitor preloaded in flash memory 2 1 Options One of the following panels can be made available upon request April 1997 Sharp LM4801 4F 480 x 320 pixels 28 V VEE Alps KHABAA902A 320 x 240 pixels 20 V Veg APPLICATION NOTE v1 0 i gt CIRRUS LOGIC EVALUATION KIT CONTENTS gt CIRRUS LOGIC 3 EVALUATION BOARD CL PS7111 Evaluation Kit User Manual The evaluation board is designed as a prototype with some debugging capabilities such as test headers for logic analyzer trace optional memory and I O configurations Figure 3 1 shows the block diagram of the evaluation
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