QPLL User Manual - CMS-ECAL Monitoring system
Contents
1. Voltage Controlled Crystal Oscillator VCXO different crystals are required for operation in each one of the two frequency multiplication modes The required crystals are provided by CERN for the specified operation frequency 160 MHz 120 MHz LVDS IN 80 MHz 60 MHz CMOS IN Mode Enable External Control 40 MHz f Select Enable Auto Restart Reset Locked Vdd gt Error Figure 1 QPLL block diagram The use of a VCXO in the QPLL allows to achieve low jitter figures but imposes the limitation of a small frequency lock range To cope with crystal cutting accuracy process temperature and power supply variations upon reset or loss of lock the ASIC goes through a frequency calibration procedure In principle this is an automatic procedure that in most applications should be transparent to the user However in some situations like for example hardware or system testing the user might want to have control over it The signals that are relevant to this function are externalControl autoRestart and f Select 3 02 If the externalControl signal is set to 1 then the automatic calibration procedure is disabled and the VCXO centre frequency is set by the signals fjSelect 3 0 otherwise the free running frequency is automatically determined The QPLL contains a lock detection circuit that monitors at every instant the lock state of the phase locked loop If the PLL is detected to be unlock2. set by the automatic frequency calibration procedure externalControl 1 The VCXO free running frequency is set by the input signals f Select lt 3 0 gt f Select lt 3 0 gt 5V compatible CMOS inputs with internal pull down pull up resistors foSelect 3 lt pull up f Select lt 2 gt lt pull down fjSelect 1 pull down f Select 0 lt pull down These signals control the VCXO free running oscillation frequency when the signal externalControf is set to 1 If externalControf is set to 0 these signals have no influence on the IC operation inCMOS 5V compatible CMOS input with internal pull down resistor This is the CMOS reference clock input When in use inLVDS and inLVDS must be set to logic levels 0 and 1 respectively inLVDS and inLVDS LVDS inputs These signals are the LVDS reference clock inputs When in use inCMOS must be held at logic level 0 locked 2 5V CMOS output Reports the PLL locked status Lvds40MHz Ivds40MHz LVDS output 40MHz clock output Ivds80MHz Ilvds80MHz LVDS output mode 0 60 MHz clock signal with 120 MHz quartz crystal mode 1 80 MHz clock signal with 160 MHz quartz crystal Ivds160MHz lvds160MHz LVDS output mode 0 120 MHz clock signal with 120 MHz quartz crystal mode 1 160 MHz clock with 160 MHz quartz crystal mode 5V compatible CMOS input with internal pull up
3. 80 MHz and 160 MHz o 40 MHz 60 MHz and 120 MHz Reference clock input levels o LVDS o CMOS single ended 2 5 V to 5 V compatible Output jitter lt 50 ps peak to peak for input signal jitter less than 120 ps RMS Package LPCC 28 5 mm x 5 mm 0 5 mm pitch Power supply voltage 2 5V Radiation tolerant 0 25 um CMOS technology Crystal The QPLL quartz crystal will be provided with the QPLL for operation in the specified frequency multiplication mode 1 Please note that frequency numbers in this document are often rounded to the nearest integer This is just a simplification to facilitate reading and writing In fact these numbers should be interpreted to be the exact multiples of the LHC bunch crossing clock frequency VERSION 0 0 3 QPLL USER MANUAL PRELIMINARY OPERATION The QPLL uses the LHC bunch crossing clock as the reference frequency This signal can be feed to the ASIC either in CMOS or LVDS levels please refer to Figure 1 Selection of which input to use is simply done by forcing the unused clock input to logic level 0 notice the use of the OR function in the reference clock signal path in the block diagram The three clock outputs are LVDS signals and their frequency depends on the mode input When mode is set to 0 the output clock frequencies are 40 MHz 60 MHz and 120 MHz otherwise the frequencies are 40 MHz 80 MHz and 160 MHz Since the highest clock frequency is obtained directly from the
4. Output 2 5 V compatible 9 locked Output CMOS 2 5 V 10 gnd Power 11 vdd Power VERSION 0 0 7 QPLL USER MANUAL 12 Ivds80MHz Output LVDS 13 lvds80MHz Output LVDS 14 foSelect 2 Input CMOS 5V compatible 15 lvds160MHz Output LVDS 16 Ivds160MHz Output LVDS 17 gnd Power 18 vdd Power 19 Ivds40MHz Output LVDS 20 lvds40MHz Output LVDS 21 foSelect lt 1 gt Input CMOS 5V compatible 22 vdd Power 23 cap Power 24 xtal1 Analogue Quartz crystal 25 gnd power 26 xtal2 Analogue Quartz crystal 27 mode Input CMOS 5V compatible 28 foSelect 1 Input CMOS 5V compatible VERSION 0 0 PRELIMINARY
5. QPLL USER MANUAL PRELIMINARY QPLL User Manual Quartz Crystal Based Phase Locked Loop for Jitter Filtering Application in LHC Paulo Moreira CERN EP MIC Geneva Switzerland 2002 12 10 Version 0 0 Technical inquires Paulo Moreira cern ch VERSION 0 0 1 QPLL USER MANUAL PRELIMINARY Introduction 3 FQ Atle ox oic EE N E rueda Ad AE E RAME AE orsi 3 OPERATION 4 QPLL Signals 5 QPLL pinout 7 Pin assignment ese Ee ese Ee Ee GED Ee een Ge Ee ee Ee be Ke GED anaa Ee ee bee Ee ee de Ee Ke ee 7 VERSION 0 0 2 QPLL USER MANUAL PRELIMINARY INTRODUCTION The QPLL is a Quartz crystal based Phase Locked Loop Its function is to act as a jitter filter for clock signals operating synchronously with the LHC bunch crossing clock frequency Two frequency multiplication modes are implemented 120 MHz and 160 MHz modes In the 160 MHz mode the ASIC generates three clock signals synchronous with the reference clock at 40 MHz 80 MHz and 160 MHz while in the 120 MHz mode the synthesized frequencies are 40 MHz 60 MHz and 120 MHz In both cases the highest frequency is generated directly from a Voltage Controlled Crystal Oscillator VCXO and the lower frequencies are obtained by synchronous division The two frequency multiplication modes require Quartz crystals cut to the appropriate frequencies Features Quartz crystal based Phase Locked Loop Three LVDS clock outputs Two frequency multiplication modes o 40 MHz
6. ed a frequency calibration cycle is initiated to lock the PLL This feature can be disabled by forcing the signal autoRestart to 0 In this case a frequency calibration cycle is only started if a reset is applied to the IC In any case the Jocked signal reports the locked status of the PLL The logic circuits controlling the PLL use redundant logic techniques to cope with Single Event Upsets SEU The error flag indicates momentarily that one SEU has occurred These errors are dealt with automatic requiring no action from the user VERSION 0 0 4 QPLL USER MANUAL PRELIMINARY QPLL SIGNALS autoRestart 5V compatible CMOS input with internal pull up resistor autoRestart 0 Automatic restart of the PLL is disabled A frequency calibration cycle will only occur after a reset autoRestart 1 Automatic restart is enabled A frequency calibration cycle will occur each time the PLL is detected to be unlocked cap VCXO decoupling node A 100 nF capacitor must be connected between this pin and ground error 2 5V CMOS output This signal indicates that an SEU has occurred Since SEU events are dealt with automatically by the ASIC logic this signal will be active only during period in which the error condition persists A SEU should not affect the operation of the PLL externalControl 5V compatible CMOS input with internal pull down resistor externalControl 0 The VCXO centre frequency is
7. resistor VERSION 0 0 5 QPLL USER MANUAL PRELIMINARY mode 0 120 MHz frequency multiplication mode 120 MHz quartz crystal required mode 1 160 MHz frequency multiplication mode 160 MHz quartz crystal required reset 5V compatible CMOS input Active low reset signal xtal1 xtal2 Quartz crystal connections VERSION 0 0 6 QPLL USER MANUAL PRELIMINARY QPLL PINOUT The QPLL is packaged in a 28 pin LPCC 28 with 0 5 mm pin pitch 5mm x 5mm Leadless Plastic Chip Carrier POUW Z GIOK 9c pub gc LIOR vc doo ez DPA c 0219etes ec 1 inl VDS 121 f Select 1 2 inLVDS 120 Ivds40MHz 3 INCMOS QPLL H 19 Ivds40MHz Package LPCC 28 Size 5 mm x 5 mm 5 autoRestart 6 reset 7 f Select lt 3 gt Pitch 0 5 mm _ 18 vad 17 gna 116 Ivds160MHz 115 lvds160MHz TIL TL 3E 3 4 5 OO NO HA i a O N WO h O So aa lm onmes Ede eu 3 9 4 00072727 o Cx CO O oo Qo lt lt F A OY KN Figure 2 QPLL pinout Pin assignments Pin Number Signal Name Signal type 1 inLVDS Input LVDS 2 inLVDS Input LVDS 3 inCMOS Input CMOS 5V compatible 4 externalControl Input CMOS 5V compatible 5 autoRestart Input CMOS 5V compatible 6 reset Input CMOS 5V compatible 7 foSelect lt 3 gt Input CMOS 5V compatible 8 error
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