Technical Information on ARM-related JTAG / SWD / SWV / ETM
Contents
1. Output CPU A 10 43 i7 GND _ 18 TraceD2 Output son re 19 GND 20 TraceD3 Output MP L Key 5 Input output is based on the target system 9 e Connect the signal dedicated to SWO The pin can be left N C if you x NG are using Pin No 14 as SWO See 4 12 3 SRST signal is an open collector output 14 Establish wired OR connection to power on reset or system reset 16 on the target system or if wired OR circuit is not available connect 18 with OR circuit 20 4 In some CPUs SWO and TraceDO are multiplexed In the case of such pin connect SWO signal not to Pin No 6 but to Pin 3 9 9 11 19 19 1 7 19 No 14 even when you intend to use Pin No 14 as SWO not as L TraceDO 5 Key is intended for protection against wrong insertion 2 TraceClk E TraceDO SWO e TraceDi TraceD2 TraceD3 This interface does not use TRST If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction Technical Information on JTAG SWD SWV ARM related Target Interface Sep 18 2015 Fourth Edition 6 JTAG interface Trace Signals Na Stone output No 999 output Output Output 3 GD 4 ICK Input 15 GND 6 TDO Output 07 Ky 82. Do not install the product in locations subject to excessive amounts of water humidity dust oily vapor etc as it may result in the outbreak of fire malfunctions or electric shock Make sure that the correct power supply and voltage as listed is used m All copyrights pertaining to CSIDE are the sole property of Computex Co Ltd CSIDE PALMICE and COMPUTEX are registered trademarks of Computex Co Ltd in Japan All other company names product names etc listed within the product manual are trademarks and registered trademarks of each individual manufacturer Computex Table of Contents Chapter 1 Getting Started 1 ISLAM Tm 2 1 2 Product COMPOSITION C ntentS ikattar 3 1 3 Connection Stl eU kA AA 4 Chapter 2 PALMICE3 JTAG200 Hardware Specifications 5 2 1 PALMiCE3 JTAG200 model hardware specifications 6 2 2 JTAG200 model specificatioNS Xa 6 2 3 Name and function of each part Aa 7 2 3 1 Hardware revision icsnesinantearixasienctisnotedeieaukeiststeknintenstnandsardoneteauinaisiaantennesadomes 8 How revision sticker reads iii 8 Chapter Target Interface Specifications 9 OFO UCO PTT MM 10 o Target niter d AA 10 3 2 1 Shape of the connector for debugger nn 10 3 2 2
3. 16 TRST Input 17 GND 18 NC 01 Input output is based on the target system ta SRST signal is an open collector output Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR circuit 3 Key is intended for protection against wrong insertion 4 If the CPU does not present the pin or if you do not use RTCK leave itas N C 5 For some CPUs such as Renesas Electronics RZ A1L pull down may be required Check the data sheet of the CPU to be used and use either pull up or pull down Target connection reference diagram 2 connector 10K V Tref pull up EE f CPU a 6 TDI Other 9 Such as RZ A1 l mma ww mm ow 8 mm mm mm ww 5 l VCC rn 1 LI 10K LI B 10K LI LI LI pull up pull down 16 O TRST LI LI LI LI El LI 1 I i a mma mm p m Um ww a O TDO OC 49 Ce 105 SRST 19k pull up LO Key NM 14 grok 12 18 20 FO NO 3591113151719 GND B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction Technical Information on JTAG SWD SWV ARM related Target Interface Sep 18 2015 Fourth Edition E 10 pin 1 27mm pitch connector Target connector specificat
4. Corrected the Product purchase chart Technical Information and correspond to PALMiCE3 CM3 ETM200 only However PALMICE3 CM3 ETM200 is a product to be released in the future Added the note on SRST signal in respective signal tables SRST signal is an open collector output Third Edition Mar 04 2011 PALMiCE3 CM3 ETM200 has already been released Dec 2009 Deleted the following description To be released in the future Supported connectors Added graphic images of the connectors Product purchase chart Added graphic images of the optional products Added the note on SRST signal in respective signal tables Changed the note on TRST signal in respective signal tables Deleted CPU core options from Technical Information reference chart and Product purchase chart For supported CPUS refer to Product Summary of respective products up on our website Deleted the description of the case where ETM is not used and half pitch 1 27mm connector is used When you use them please contact us Fourth Edition Sep 18 2015 Added an item to Applicable products PALMiCE2H ARM ETM383 Following addition of an item to Applicable products mentioned above added the description on PALMiCE2H to Technical Information reference chart and Product purchase chart Following addition of an item to Applicable products mentioned above added X8X940 to pages on target interface details Placed specifications
5. Technical Information ARM related JTAG SWD SWV ETM Target Interfaces Sep 18 2015 Fourth Edition Go through the required procedures as stated under Foreign Exchange and Foreign Trade Control Law in exporting including the case where travellers directly carry this product or providing this product for residents outside Japan No part of this manual whether in whole or in part may be adapted copied or reproduced without prior permission The content of and the specifications of this product are subject to change without prior notice Computex Co Ltd shall not be held liable for any loss or damage arising from the use of this product although all possible measures have been taken by Computex Co Ltd in good faith to ensure the quality of the product Contact us for any questions feedback comments requests or anything of concern to you or in the event of malfunction regarding this product or misprinting or missing information within this manual Other names of CPUs etc mentioned in this manual are trademarks or registered trademarks of their respective manufacturers gt PALMICE J STICK and COMPUTEX are registered trademarks of Computex Co Ltd in Japan Copyright C 2009 Computex Co Ltd Document change history Second Edition Nov 13 2009 Added the descriptions on CPU core ARM and PALMiCE3 ARM JTAG200 to Technical Information reference chart and Product purchase chart
6. CPUs that do not present this signal leave the pin unconnected in open state SRST signal is an open collector output Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR circuit The signal is not used by Computex made debugger If the CPU does not present the pin or if you do not use RTCK leave it as N C The signal is not used by Computex made debugger it can be left unconnected If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value For the names of signals corresponding to respective pin No see the table of Signals Sep 18 2015 Fourth Edition Target connection reference diagram JSP Mictor connector 14 yrvpp VEC Ho vec Lg JV Tref if 10K pullup 3 l 2l TRet 195 TDI p LL M n LA pparot2 10K pull down Na 15 8 pgaacK 135 gro 16 18 20 22 23 24 25 28 27 28 29 31 33 35 37 38 TEST POINT VCC 8 O TRACEDATALO 15 36 O TRACECTL 6 TRACECLK EXTTRIG 4 12341 Z 7 NC YCC E GND 30 32 KO LogicO 10K pull up Tomte gal B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction 11 PALMICE3 JTAG200 model Hardware Manual Fifth Edition Copyright C 2009 Computex Co Ltd Precaut
7. L DV K Recommended connector Manufacturer AMP Model Mictor connector Top view on the target board 2 5767004 2 5767054 1 5767061 1 Please look at the pin configuration diagram and make sure that the connector is in the right direction before connecting Moreover please check the pin number in the corresponding signal table and make sure the signal and the pin numbers match Applicable products This manual is applicable for the following products PALMICE3 ARM JTAG200 PALMICE3 CMS ETM200 PALMICE2H ARM ETM383 Technical Information on JTAG SWD SWV ARM related Target Interface Sep 18 2015 Fourth Edition Technical Information reference chart 1 Depending on the target interface you use Technical Information you should refer to will be different Based on the chart below consult the applicable Technical Information Debugging ETM Choose a connector to be Technical interface SWV implemented on the target system Information No To Technical Information reference chart 2 Only those combinations available for selection are given For other combinations please contact us Technical Information reference chart 2 Choose a connector to Debugging ETM interface SWV E USE ETM 38 pin Mictor connector Technical Information CPU core Mode No _ Only those combinations available for selection are given Technical Info
8. flashes in some cases to notify errors mai For details refer to the user s manual Computex i cf ra 4 TARGET connector PALMICE 20 pin connector for connecting PALMiCE3 to the target system 5 EXT Connect an optional cable It 1s normally not used 6 Power switch Turns ON OFF the PALMiCE3 s power Power input state can be checked with 1 POWER LED 7 USB connector Connect USB cable mini B type PALMICE3 JTAG200 model Hardware Manual Chapter 2 PALMiCE3 JTAG200 Hardware Specifications 7 Computex 2 3 1 Hardware revision The sticker with PALMiCE3 information is placed at the back of PALMiCE3 main unit PALMICE ho n JTAG EMULATOA Computex Back side of PALMiCE3 main unit How revision sticker reads Read the number given on the upper side and the last alphabet shaded with black Example 1 Hardware revision 1 B In Example 1 PALMiCE3 hardware revision reads as 1 B In Example 2 where alphabets are not shaded PALMiCE3 hardware revision reads as 2 0 PALMICE3 JTAG200 model Hardware Manual Chapter 2 PALMiCE3 JTAG200 Hardware Specifications 8 Computex Chapter 3 Target Interface Specifications PALMiCE3 JTAG200 model Hardware Manual Chapter 3 Target Interface Specifications 9 Computex 3 1 Introduction This Chapter spells out target interface specifications for connecting PALMiCE3 JTAG200 to the target system 3 2 Target interface The interface for connecti
9. is not used by Computex made debugger f the CPU does not present the pin or if you do not use RTCK leave it as N C The signal is not used by Computex made debugger it can be left unconnected If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value For the names of signals corresponding to respective pin No see the table of Signals Sep 18 2015 Fourth Edition Target connection reference diagram 38P Mictor connector 14 vp0 6 o E V Tref YCC VCC 10K pull up 9 3 SRST 21 Tae 195 TDI 174 pM an TEST POINT e BO TCK 15 ppano 10K pull down 15 8 5 DBGACK 2 13 RTOK 20 2 8 8 34 kaiba TRACEPKT 1 2 PIPESTAT 11 2 38 4 TRACESYNG PIPESTATIO 8 TRACECLK OO 105 pRa 1 2 3 4 16 18 23 25 27 29 31 33 35 37 NC E GND B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction 10 Technical Information on JTAG SWD SWV ARM related Target Interface AD JTAG interface ETM Signals Output Output a H 3 NO oo 4 15 GND 6 TRACECLK Output 7 DBGRO Input 8 DBGACK Output 19 SRST Input 10 EXTTRIG Input 1 2 3 4 5 6 T 8 Input output is based on the target system In the
10. is to serve for potential detection and pull up signal of 1K will do 2 Each of these signals has been pulled up to the voltage level detected from VTref pin 3 Itis an output signal with open collector specification from PALMiCE3 Pull it up at a few 10KQ recommended on the target side 4 Names of signals in are those for the time of Serial Wire Debugging N C indicates that the pin is not used Each name of the signal varies depending on the CPU you use For Target connection reference diagram refer to PALMiCE3 Technical Information up on Computex website http www computex co jp eg PALMICE3 JTAG200 model Hardware Manual Chapter 3 Target Interface Specifications 11 Computex Computex Co Ltd Head Office Tairanbo Bldg aoc Higashiyama ku KYOTO 6050846 Japan PALMiCE3 JTAG200 model Hardware Manual Ohmori Plaza Bldg 5F May 2012 Fifth Edition CM951 E 1205 3 28 3 Minami Oi Shinagawa ku TOKYO 1400013 Japan Our Tokyo Sales Office has been relocated to the following address since October 2013 JK Ohmori Bldg 7F 3 28 10 Minami Oi Shinagawa ku TOKYO 1400013 Japan
11. make sure the signal and the pin numbers match 3 SWD interface Signals Target connection reference diagram Output Output wet T LO Vief 3 GND SWCLK Input 5 GND 6 swo Output 7 Key 8 NC 9 GND to SRST Input p GND i2 NG mm _5 GND 16 NC i7 GND 18 NC uS poo Io NG 1 Input output is based on the target system 2 SRST signal is an open collector output Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR circuit 8 Key is intended for protection against wrong insertion 10K pull up gt d Key 3 81214161820 NC 3591113151719 GND This interface does not use TRST If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction SWD interface Trace Signals Target connection reference diagram Input Input 20P connector no ione output Mo 98781 output T _ 38 GND 4 SWCIK Input mlu 15 GND 06 swo Output a keys NG input VT 9 GND 10 SRST Input eee 111 12 TraeCk Output DO swo 115 GND __ 16
12. of the target interface on the debugger side PALMiCE3 PALMiCE3 JTAG200 model Hardware Manual PALMiCE2H Extracted from PALMiCE2H ARM User s Manual Supported connectors 38 pin Mictor connector Changed the recommended connectors Before change 2 767004 2 767054 1 767061 RoHS non compliant products After change 2 5767004 2 5767054 1 5767061 1 RoHS compliant products Supported connectors Added the note Product purchase chart Added PALMiCE3 ARM 200 to to 10 Added notes on the TRST signal described in 2 Using 20 pin 2 54 mm pitch connector JTAG interface Added Using 20 pin 1 27 mm pitch connector JTAG interface According to the above addition incremented the heading number and subsequent numbers by one In accordance with J STICK sales termination deleted J STICK descriptions from the applicable products and the product purchase chart Technical Information on JTAG SWD SWV ETM ARM related Target Interface Sep 18 2015 Fourth Edition Supported connectors For detailed dimensions of the connectors refer to the documentations by respective manufacturers of the connectors 20 pin 2 54mm pitch connector OOOOO00090 QOO 000000 Recommended connector Manufacturer OMRON Corporation Model XG4C 2031 Recommended connector Manufacturer Samtec Inc Model FTSH 110 01 L DV K Recommended connector Manufacturer Samtec Inc Model FTSH 105 01
13. on chip debugging feature to provide the following functionalities a E B Ej E This chapter spells out specifications of PALMiCE3 hardware 2 2 JTAG200 model specifications _ Item JTAG200 model specifications Execution and break of the user program Break by matching any address and data Force break of the user program Trace and step executions Viewing and editing of memory register and I O 2 2 JTAG200 model specifications Target interface JTAG SWD SWV Specification of the connector 20 pin MIL connector Cable length Approx 20cm Interface on the e target system side Target interface voltage LED Outside dimensions Operating temperature 5 C to 40 C Operating humidity 35 to 85 RH No condensation USB host interface AC adapter Current consumption Weight 1 Hardware revision 0 0 supports 1 0V 3 6V For hardware revision see 2 3 1 Hardware revision Operating environment PALMICE3 JTAG200 model Hardware Manual Chapter 2 PALMiCE3 JTAG200 Hardware Specifications 6 Computex 2 3 and function of each part Appearance drawing of PALMiCE3 JTAG200 model is given to the following 1 PWRLED Comes on when the power is supplied to PALMiCE3 Power is supplied from the host computer through USB cable Front Left side 2 BSY LED Flickers during communication between PALMiCE3 and the target CPU 3 STS LED Lit normally during user program execution Front Right side Also
14. value AE eee NO 8 For the names of signals corresponding to respective pin No see the table of Signals me GND B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction Technical Information on JTAG SWD SWV ARM related Target Interface JTAG interface ETM Multiplex mode Signals Input Input Output Output A 1 NC 2T NO p ee 15 GND f 6 TRACECLK Output 7 DBGRQ Input 8 DBGACK Output 9 SRST3 Input 10 EXTTRIG Input 17 TMS Input 8 Ne J O 23 NC 24 TRACEPKI I 11 Output 25 NC 26 JTRACEPKT89 Output 27 NC 28 TRACEPKT 67 Output 29 NC 30 TRACEPKT45 Output 31 NC 32 TRACEPKT 0 3 Output 1 33 NC 234 PIPESTAT2 TRACEPKT2 Output 35 NC 36 PIPESTAT1 TRACEPKT1 Output 1 37 NC L 38 PIPESTATO TRACESYNC Output Input output is based on the target system In the CPUs that do not present this signal leave the pin unconnected in open 4 15 6 7 8 state SRST signal is an open collector output Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR circuit The signal
15. Dimension of the target cable i 10 3 2 3 Specifications of target interface signals 11 3 2 4 The target interface on PALMICES side 11 Computex Chapter 1 Getting Started PALMICE3 JTAG200 model Hardware Manual Chapter 1 Getting Started 1 Computex 1 1 Introduction PALMiCE3 JTAG200 model is an on chip debugger that supports ARM made core CPUs Its main features are as follows Provides multi core support No power supply to PALMICE3 is required with VBus support Allows downloading to external flash memory and its debugging Supports on chip flash memory Versatile Supports USB Standard Revision2 0 high speed and full speed Allows downloading of the latest CSIDE from the Internet Designed with palm sized light and compact body PALMICE3 JTAG200 model Hardware Manual Chapter 1 Getting Started 2 Computex 1 2 Product Composition Contents Product composition of PALMiCE3 JTAG200 model is as follows IPALMiCE3 JTAG200 model LILLIE ET EE x 1 Target cable Specifically for PALMiCE3 0 x 1 Product name sticker HHHH ix 1 Software CD ROM gi 1 Its name varies depending on CSIDE the debugger software you purchased PALMICE3 JTAG200 model Hardware Manual Chapter 1 Getting Started 3 Computex 1 3 Connection structure PALMiCE3 is to be connected to the host computer with the USB cable inc
16. NC pa GND 15 NC 6 GND 7 SWDIO Input Output 8 GND 9 SWOLK Input f 10 GND ti NC Cl 12 O 113 SWO Output 14 GND 15 SRST f 16 GND __ i7 NC Co GND i9 NC 120 GND __ 1 Input output is based on the target system 2 SRST signal is an open collector output Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR circuit 3 The signal is not used by Computex made debugger it can be left unconnected 3 9 11 17 19 NC 4681012 141618 20 LO GND his interface does notuse TRST If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction 2 JTAG interface Signals Target connection reference diagram Input Input 20P JTAG connector Output Output 2h 1v00 8 Output Output I i 3 TRST Input 4 GND FP el 5 TDI Input 6 GND ied ii Jot com FI A HG 7 TMS Input 8 GND Tok Input 10 GND _ Rr Output 12 cnn HQ 3f 15 SRST Input 16 GND 13 Ls psoack ew iP Input output is based the t
17. TD Input 9 GND to SRST Input GND 12 Traceck Output 13 GND 14 TraeDO Output 15 GND 16 TraeDi Output 17 GND J 18 TraceD2 Output 19 GND 20 TraceD3 Output Input output is based on the target system H SRST signal is an open collector output Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR circuit 8 Key is intended for protection against wrong insertion B This interface does notuse TRST Target connection reference diagram 20P connector ri Ee i 5v f 10K is la up TMS NY 2 __ 43 LM e CPU 8 6 O TDO VCC Le LO SET 2 i ola pull up 1 E Key 3 nE TraceClk in TraceDO T TraceDi TraceD2 20 TraceD3 3591113151719 GND If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction 6 JTAG interface Signals Sianal output No output Output Output 13 4 Input 5 GND 6 TDO Output 7 Key f 8 TD Input 9 GND to SRST Input j t2 NC O q 13 GND 14 RICK Output 15 GND
18. arget system CE su O SRST For some CPUs such as Renesas Electronics RZ A1L pull down pull up may be required Check the data sheet of the CPU to be used and 11 DBGRO use either pull up or pull down a 3 If the CPU does not present the pin or if you do not use RTCK l leave it as N C 5 4 SRST signalis an open collector output O DBGAOK Establish wired OR connection to power on reset or system 11 i 3 reset on the target system or if wired OR circuit is not available O RTCK connect with OR circuit 5 In the CPUs that do not present this signal leave the pin ees unconnected in open state TY GND 6 The signal is not used by Computex made debugger it can be left unconnected B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction Technical Information on JTAG SWD SWV ARM related Target Interface Sep 18 2015 Fourth Edition E 20 pin 1 27mm pitch connector Target connector specifications Recommended connector Manufacturer Samtec Inc Model FTSH 110 01 L DV K For detailed dimensions of the connector refer to the documentation by manufacturer of the connector Please look at the pin configuration diagram above and make sure that the connector is in Top view on the target board the right direction before connecting Please check the pin number in the signal table above and
19. ce Demultiplex mode Signals Target connection reference diagram 38P Mictor connector put 4 Output Output _1 NC E 2b 3 NC CU ANC vec isi 15 GND 6 TRACECLK Output DE 7 DBGRO Input 8 DBGACK Output O SRST 5 input 10 _EXTTRIG Input POC sla 195 TDI 15 TCK Input 16 NG tata 17 TMS Input f 18 NO J o CPU Loo bi cx 19 TDI O Input 20 NG _ 17 2 Cor TED 2 NO ie 0 s 15 8 2 13 5 23 24 25 26 1 Input output is based the target system UE O TRACEPKTA Blo 3 2 In the CPUs that do not present this signal leave the pin unconnected in 3 33 34 35 open state 36 37 38 8 SRST signal is an open collector output PIPESTATA BIO 2 9 Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR 31 32 circuit TRACESYNCA B 4 The signal is not used by Computex made debugger 5 f the CPU does not present the pin or if you do not use RTCK leave it as 6 N C O TRACECLK 6 The signal is not used by Computex made debugger it can be left TEST POINT unconnected PO poene so ExTTRIG 4 7 ifi h 10K 7 If the target CPU presents a pin specifically for TRST pull it up with 10 123416 18 20 22 ohmic
20. et Interface 38 pin Mictor connector Target connector specifications Top view on the target board Recommended connector Manufacturer AMP Model Mictor connector 2 767004 2 767054 1 767061 Sep 18 2015 Fourth Edition In mounting ETM connector place it to the position as close as possible to CPU so that wiring pattern length will be minimized Also in mounting JTAG connector place it to the position close to ETM connector In addition you will need to a connect e Grand Bus QOQ0UU0000000000000 Leads of ETM connector to Connectto GND D the GND DOOO0O0000000000000 38 2 For detailed dimensions of the connector refer to the documentation by manufacturer of the connector Please look at the pin configuration diagram above and make sure that the connector is in the right direction before connecting Please check the pin number in the signal table above and make sure the signal and the pin numbers match 8 JTAG interface ETM Normal mode Signals sen Output Output ilo NC NC 3 NC NC I 5 GND 6 TRACECLK Output 7 DBGRQ Input 8 DBGACK Output 9 58572 Input 10 EXTTRIGS Input 1 2 3 8 6 7 8 9 Input output is based on the target system In the CPUs that do not present this signal leave the pin unconnected in open state SRST signal is an open collector outp
21. ions Recommended connector Manufacturer Samtec Inc Model FTSH 105 01 L DV K For detailed dimensions of the connector refer to the documentation by manufacturer of the connector Please look at the pin configuration diagram above and make sure that the connector is in the right direction before connecting Please check the pin number in the signal table above and make sure the signal and the pin numbers match Top view on the target board 7 SWD interface Signals Target connection reference diagram Emm e so Output Output 3 GND 4 SWCIK Input 10P connector VCC lols VTref VCC SWDIO 5 GND 6 swo Output ower x 7 Key 8 NC Input BENE M NN EN SRST 1 Input output is based on the target system 2 SRST signal is an open collector output 2 Establish wired OR connection to power on reset or system SRST reset on the target system or if wired OR circuit is not available LC ke 3 connect with OR circuit y 3 Key is intended for protection against wrong insertion CE NC This interface does not use TRST If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction Technical Information on JTAG SWD SWV ARM related Targ
22. ions For Use Read the following thoroughly before attempting to use the product In the event of exporting the product including taking it outside of Japan or supplying the software to third parties not resident in Japan make sure that all procedures as stipulated by the Foreign Exchange and Foreign Trade Act are strictly observed m The product the product manual and the software may not be used or reproduced in whole or in part without prior permission m Product details and specifications are subject to modification without prior notice for the purpose of improving reliability functionality and design m Note that although a great deal of care has been taken in manufacturing the product the company does not guarantee the results of its use m The product has been manufactured with no intention of it being used for any purpose that requires extremely high levels of reliability and safety in functions and performance such as in military equipment nuclear power equipment aerodynamic or space exploration equipment traffic equipment incinerator control equipment medical equipment power generation control equipment equipment installed on the seabed safety devices or similar equipment in which malfunctions or incorrect operations may result in direct threats or damage to human lives or that may result in serious threats to society in general Note that the company refutes all responsibility for damages incurred through these uses
23. luded with the product PALMiCE3 is to be connected to the target system with the target cable included with the product For details on the target interface see the next chapter To use PALMICE3 the interface connector for PALMiCE3 use needs to be mounted on the target system beforehand 20 pin connector Computex PALMiCE2 USB cable Target system PALMiCE3 JTAG200 Host computer PALMiCE3 JTAG200 model Connection structure When connecting the hardware if you put too much pressure stress or strain on the connector doing so may cause damage Be careful not to put too much pressure or try not to strain or put stress on the connector About target cable specifically for PALMICE3 Make sure to use PALMiCE3 specific target cable made by Computex When establishing connections connect the connector with a tag 1 in the illustration to the target system 4 2 1 For connection to the target system optional products such as conversion adapter are available PALMICE3 JTAG200 model Hardware Manual Chapter 1 Getting Started 4 Computex Chapter 2 PALMICE3 JTAG200 Hardware Specifications PALMiCE3 JTAG200 model Hardware Manual Chapter 2 PALMiCE3 JTAG200 Hardware Specifications 5 Computex 2 1 PALMiCE3 JTAG200 model hardware specifications PALMiCE8 is a purpose built debugger for utilizing on chip debugging feature incorporated in ARM made cores PALMiCE3 incorporates
24. ng PALMiCE3 JTAG200 to the target system is described Target interface varies from CPU to CPU 3 2 1 Shape of the connector for debugger The shape of connector 20 pin MIL connector for debugger to be mounted on the target system side is as follows Top view on the target system O O O O O O O O O Recommended connector Manufacturer Omron Corporation Model XG4C 2031 For detailed dimensions of the connector refer to the documentations provided by manufacturers 3 2 2 Dimension of the target cable The dimension of target cable for connecting PALMiCE3 JTAG200 to the target system is as follows Approx 200mm For detailed dimensions of the connector refer to the documentations provided by manufacturers PALMICE3 JTAG200 model Hardware Manual Chapter 3 Target Interface Specifications 10 Computex 3 2 3 Specifications of target interface signals Input voltage level Target voltage 2 0 35 Target voltage 2 0 35 Output voltage level Under 0 2V 3 2 4 The target interface on PALMiCE3 side The target interface on PALMiCE3 side is described e SS Pao Net used 4 GND PIE CU RENE NUR prre C6 ow tf Input meos Mi 0 ow Naga 330Seies 0 GND 12 GD J 14 GD _6 GD 18 GND e 20 GND For Ve pin connect the signal to the power at the same level as the target interface VTref pin
25. rmation on JTAG SWD SWV ARM related Target Interface Sep 18 2015 Fourth Edition Product purchase chart Depending on the target interface you use the composition of product and optional product you should purchase will differ Based on the Technical Information No See Technical Information reference chart on the previous page choose the product Only those products available for selection are given Technical Information Product name 1 Required optional No product 1 For the CPUs supported by respective products refer to Product Summary of respective products up on Computex website Technical Information on JTAG SWD SWV ARM related Target Interface Sep 18 2015 Fourth Edition E 20 pin 2 54mm pitch connector Target connector specifications 2 54mm Recommended connector Manufacturer OMRON Corporation Model XG4C 2031 For detailed dimensions of the connector refer to the documentation by manufacturer of the connector 2 54mm 60000000006 1 QOOOOOOOO i Please look at the pin configuration diagram above and make sure that the connector is in the right direction before connecting Top view on the target board Please check the pin number in the signal table above and make sure the signal and the pin numbers match D SWD interface Signals Target connection reference diagram Input Input Output Output 20P JTAG connector 20 rvoo _
26. ut Establish wired OR connection to power on reset or system reset on the target system or if wired OR circuit is not available connect with OR circuit If the CPU does not present the pin or if you do not use RTCK leave it as N C The signal is not used by Computex made debugger The signal is not used by Computex made debugger it can be left unconnected If the target CPU presents a pin specifically for TRST pull it up with 10K ohmic value If the trace data is of 4 bit connect signals TRACEPKT4 15 or if of 8 bit connect signals TRACEPKTS8 15 to GND For the names of signals corresponding to respective pin No see the table of Signals Target connection reference diagram 38P Mictor connector O rvop 8 E vier OC 10K pullup ZO SRST 3 21d mer 7 Ly 20701 I D B sli BO TCK LO 2 10K pull down lt 2O DBGACK 13 RTCK 4 16 18 20 22 23 24 25 26 27 28 29 30 31 33 35 37 8 9 O TRACEPKTIO 15 34 36 38 9 meme PIPESTATIOL 2 32 TRACESYNC l TRACECLK TEST POINT VCC 10K pull up 19 ExTTRIG 9 1 2 3 4 NC p GND B Keep the length of wirings from CPU to the target connector as short as possible If the length gets long it could possibly be a factor contributing to malfunction Technical Information on JTAG SWD SWV ARM related Target Interface Sep 18 2015 Fourth Edition JTAG interfa
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