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ADV7183B Video Decoder manual

1. Bits Subaddress Register Bit Description 7 6 5 4 3 2 Comments Notes 0x01 Video Reserved 0 Set to default Selection ENVSPROC 0 Disable VSync processor 1 Enable VSync processor Reserved 0 Set to default BETACAM 0 Standard video input 1 Betacam input enable ENHSPLL 0 Disable HSync processor 1 Enable HSync processor Reserved 1 Set to default 0x03 Output SD_DUP_AV Duplicates the AV AV codes to suit 8 bit Control codes from the luma into the interleaved data output chroma path AV codes duplicated for 16 bit interfaces Reserved Set as default OF_SEL 3 0 Allows the user to 01010 Reserved choose from a set of output formats Reserved Oo 1 1 0 16 bit LLC1 4 2 2 0 0 1 1 8 bit LLC1 4 2 2 ITU R BT 656 0 1 0 ot used 0 1 1 ot used 0111110 ot used 0111111 ot used 1 0 0 0 ot used 1 0 0 1 ot used 0 1 0 ot used 1 0 1 1 ot used 1 1 0 0 ot used 1 1 01 ot used 1 1 1 0 ot used 111111 ot used TOD Three State Output Drivers 0 Output pins enabled See also TIM_OE and This bit allows the user to three TRI_LLC state the output drivers P 19 0 HS 1 Drivers three stated VS FIELD and SFL Allows VBI data Lines 1 to 0 All lines filtered and scaled 21 to be passed through with onlya 4 Only active video region minimum amount of filtering filtered performed 0x04 Extended RANGE Allo
2. eren 4 RU cie E RH ER te dette PER a 5 Electrical Characteristics eese 5 Video Specifications cete ertt terere 6 Timing Specifications seen 7 Analog Specifications eerte 7 Thermal Specifications eene 8 Timing Diagrams sicot pit RE ete pte 8 Absolute Maximum Ratings seen 9 EST Caution ciere EEG US 9 Pin Configuration and Function Descriptions 10 Analog FPronttiEnd u eee er 12 Analog Input Muxing 12 Global Control Registers 15 Power Save Modes asua iu usai 15 R set Contfol a SSS Sas 15 Global Pin Control i oe ER 16 Global Status Registers 18 Identificati OD oett RENE 18 Status Tz usse neenon PE 18 Autodetection Result 18 MIEM II 18 StatuS 3 19 Standard Definition Processor SDP 20 SD Luma Pathu a ene ens uene anu ua ua 20 SD Chroma 20 Sync ProcessIDQu 21 Data Recovery 21 General Setup 21 Color 23 Clamp Operation u een Otra 25 REVISION HISTORY 9 04 Revision 0 Initial Version L ma Eilter au 26 Chroma Filter cdd ec C deett 29 Gain Operation
3. Bits Subaddress Register Bit Description 716 5 4 3 Comments Notes OxE7 NTSC F Bit NFTOG 4 0 How many lines after NTSC default Toggle rollover to toggle F signal NFTOGSIGN 0 Set to low when manual programming 1 Not suitable for user programming NFTOGDELE Delay F transition by 0 No delay one line relative to NFTOG even 1 Additional delay by 1 line field NFTOGDELO Delay F transition by 0 No delay one line relative to NFTOG odd 1 Additional delay by 1 line field OxE8 PAL V Bit PVBEG 4 0 How many lines after 0 0 PAL default BT 656 Begin Icount rollover to set high PVBEGSIGN 0 Set to low when manual programming 1 Not suitable for user programming PVBEGDELE Delay V bit going 0 No delay high by one line relative to PVBEG 1 Additional delay by 1 line even field PVBEGDELO Delay V bit going 0 No delay high by one line relative to PVBEG 4 Additional delay by 1 line odd field OxE9 PALV Bit PVEND 4 0 How many lines after 1 0 PAL default BT 656 End Icount rollover to set V low PVENDSIGN 0 Set to low when manual programming 1 Not suitable for user programming PVENDDELE Delay V bit going low 0 No delay by one line relative to PVEND 1 Additional delay by 1 line even field PVENDDELO Delay V bit going 0 No delay low by one line relativeto PVEND 1 Additional delay by 1 line odd field OxEA PALF Bit PFTOG 4 0 How many lines after 0 0 PAL default BT 656 Toggle Icount rol
4. LELTLELFLTUELTLTLELTLTUELTUTEELTLELTLTUTUTLTUTELTLTTT T LLC1 0 i PRUS CICE FY 00 KK GH KY KEK ED EAV a H BLANK SAV OP ACTIVE VIDEO HS I HSE 10 0 HSB 10 0 i lt 4LLC1 0 0 D E E M E p Figure 20 HS Timing Rev 0 Page 39 of 96 ADV7183B VS and FIELD Configuration The following controls allow the user to configure the behavior of the VS and FIELD output pins as well to generate embedded AV codes ADV encoder compatible signals via NEWAVMODE PVS PF e HVSTIM e VSBHO VSBHE e VSEHO VSEHE e For NTSC control NVBEGDELO NVBEGDELE NVBEGSIGN NVBEG 4 0 NVENDDELO NVENDDELE NVENDSIGN NVEND 4 0 o NFTOGDELO NFTOGDELE NFTOGSIGN NFTOG 4 0 e For PAL control o PVBEGDELO PVBEGDELE PVBEGSIGN PVBEG 4 0 PVENDDELO PVENDDELE PVENDSIGN PVEND 4 0 PFTOGDELO PFTOGDELE PFTOGSIGN PFTOG 4 0 NEWAVMODE New AV Mode Address 0x31 4 When NEWAVMODE is 0 EAV SAV codes are generated to suit ADI encoders No adjustments are possible Setting NEWAVMODE to 1 default enables the manual position of the VSYNC Field and AV codes using Registers 0x34 to 0x37 and OxE5 to OxEA Default register settings CCIR656 compliant see Figure 21 for
5. m RR HOHER 30 Chroma Transient Improvement CTI 33 Digital Noise Reduction DNR sss 34 Comb Filters en ne eS 35 AV Code Insertion and Controls 37 Synchronization Output 5 39 Sync Processirig eene iei tier etna 46 Data Decode 47 Pixel Port Configuration seen 59 MPU Port 60 Register Accesses eed IRURE SE EH eet ed 61 Register Program mins suce REUS 61 PG Sequeneez Cuy EE Re et sedia 61 EC Register Maps orae RARE REUS 62 Register Map Details 66 Programming Examples eerte 88 Mode 1 CVBS Input Composite Video AIN5 88 Mode 2 S Video Input Y AINI and C on AINA 88 Mode 3 525i 625i YPrPb Input Y on AIN2 Pr on AIN3 and Phon AIN6 eee Qa EX ERE ESSERE 89 Mode 4 CVBS Tuner Input PAL Only on AINA 89 PCB Layout 90 Analog Interface 90 Power Supply Decoupling 90 PLE xen e DEED eh eee 90 Digital Outputs Both Data and Clocks 90 Digital Inputs eterne tae de itas 91 Anti
6. Table 39 Betacam Levels Name Betacam mV Betacam Variant mV SMPTE mV MII mV Y Range 0 to 714 incl 7 5 pedestal 010 714 to 700 0 to 700 incl 7 5 pedestal Pb and Pr Range 467 to 467 505 to 505 350 to 350 324 to 324 Sync Depth 286 286 300 300 Rev 0 Page 32 of 96 CG 11 0 Chroma Gain Address 0x2D 3 0 Address Ox2E 7 0 CMG 11 0 Chroma Manual Gain Address 0x2D 3 0 Address 0x2E 7 0 Chroma gain 11 0 is a dual function register If written to a desired manual chroma gain can be programmed This gain becomes active if the CAGC 1 0 mode is switched to manual fixed gain Refer to Equation 2 for calculating a desired gain If read back this register returns the current gain value Depending on the setting in the CAGC 1 0 bits this is one of the following values e Chroma manual gain value CAGC 1 0 set to chroma manual gain mode e Chroma automatic gain value CAGC 1 0 set to any of the automatic modes Table 40 CG CMG Function ADV7183B CKILLTHR 2 0 Color Kill Threshold Address 0x3D 6 4 The CKILLTHR 2 0 bits allow the user to select a threshold for the color kill function The threshold applies only to QAM based NTSC and PAL or FM modulated SECAM video standards To enable the color kill function the CKE bit must be set For settings 000 001 010 and 011 chroma demodulation inside the ADV7183B may not work satisfactorily for poor input video
7. 0 0 Gemstar word2 7 4 0 0 User data words 9 0 0 Gemstar word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 cs css CS 3 CS 2 CS 1 5 0 Checksum Rev 0 Page 53 of 96 ADV7183B Table 68 Gemstar 1x Data Full Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar word1 7 0 0 0 User data words 7 Gemstar word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 5 4 CS 3 CS 2 CS 1 CS 0 Checksum Table 69 NTSC CCAP Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 EP EP 0 0 CCAP word1 7 4 0 0 User data words 7 IEP EP 0 0 CCAP word1 3 0 0 0 User data words 8 0 0 CCAP word2 7 4 0 0 User d
8. 2 lt 8 3 Figure 5 80 Lead LQFP Pin Configuration Pin No Mnemonic Type Function 3 9 14 31 71 DGND G Digital Ground 39 40 47 53 56 AGND G Analog Ground 4 15 DVDDIO P Digital I O Supply Voltage 3 3 10 30 72 DVDD P Digital Core Supply Voltage 1 8 V 50 AVDD P Analog Supply Voltage 3 3 V 38 PVDD P PLL Supply Voltage 1 8 V 42 44 46 58 60 AIN1 AIN12 Analog Video Input Channels 62 41 43 45 57 59 61 11 INTRQ Interrupt Request Output Interrupt occurs when certain signals are detected on the input video See the interrupt register map in Table 82 13 16 18 25 34 NC No Connect Pins 35 63 65 69 70 77 78 33 32 24 23 22 15 Video Pixel Output Port 21 20 19 8 7 6 5 76 75 74 73 2 HS Horizontal Synchronization Output Signal 1 VS Vertical Synchronization Output Signal 80 FIELD Field Synchronization Output Signal 67 SDA 1 0 Port Serial Data Input Output Pin 68 SCLK Port Serial Clock Input Max Clock Rate of 400 kHz 66 ALSB This pin selects the address for the ADV7183B ALSB set to Logic 0 sets the address for a write as 0x40 for ALSB set to logic high the address selected is 0x42 Rev 0 Page 10 of 96 ADV7183B Pin No 64 27 26 29 28 36 79 37 12 51 52 48 49 54 55 RESET LLC1 LLC2 XTAL XTAL1 PWRDN OE ELPF S
9. Pvpp 1 65 V to 2 0 V operating temperature range unless otherwise noted Table 3 Parameter Symbol Test Conditions Min Typ Unit SYSTEM CLOCK AND CRYSTAL Nominal Frequency 27 00 MHz Frequency Stability 50 ppm PORT SCLK Frequency 400 kHz SCLK Min Pulse Width High ti 0 6 us SCLK Min Pulse Width Low t 1 3 us Hold Time Start Condition 0 6 us Setup Time Start Condition ta 0 6 us SDA Setup Time ts 100 ns SCLK and SDA Rise Time te 300 ns SCLK and SDA Fall Time t 300 ns Setup Time for Stop Condition 0 6 us RESET FEATURE Reset Pulse Width 5 ms CLOCK OUTPUTS LLC1 Mark Space Ratio to tio 45 55 55 45 Duty Cycle LLC1 Rising to LLC2 Rising tu 0 5 ns LLC1 Rising to LLC2 Falling t 0 5 ns DATA AND CONTROL OUTPUTS Data Output Transitional Time tis Negative clock edge to start of valid 3 4 ns data taccess tio t13 Data Output Transitional Time tu End of valid data to negative clock 2 4 ns edge tuoip to t14 Propagation Delay to Hi Z tis 6 ns Max Output Enable Access Time tie 7 ns Min Output Enable Access Time t 4 ns ANALOG SPECIFICATIONS Guaranteed by characterization At 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V 3 0 V to 3 6 V Pvpp 1 65 V to 2 0 V operating temperature range unless otherwise noted Table 4 Parameter Symbol Test Conditions Min Typ Max Unit CLAMP CIRCUITRY External Clamp Capacitor 0 1 uF Input Impedance Clamp
10. x x x CGMS3 7 4 are Read Only CGMS data register undetermined Rev 0 Page 82 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 Comments Notes 0x99 CCAP1 CCAP 17 01 x x x CCAP1 7 contains parity Read Only Closed caption data register bit for byte 0 Ox9A CCAP2 CCAP2 7 0 CCAP2 7 contains parity Read Only Closed caption data register bit for byte 0 Ox9B Letterbox 1 LB LCT 7 0 x x Reports the number of This feature Read Only Letterbox data register black lines detected at the examines the active top of active video video at the start and Ox9C Letterbox 2 LB_LCM 7 0 x x x Reports the number of at the end of each Read Only Letterbox data register black lines detected in the bottom half of active video if subtitles are d d not accompanied by a CGMS or WSS Ox9D Letterbox LB LCB 7 0 x x x Reports the number of sequence Read Only Letterbox data register black lines detected at the bottom of active video 0 2 CRC Reserved Set as default Enable CRC_ENABLE Enable CRC checksum Turn off CRC check Write decoded from CGMS packet to Register validate CGMSD CGMSD goes high with valid checksum Reserved Set as default Rev 0 Page 83 of 96 ADV7183B Subaddress Register Bit Desc
11. 011 default 100 101 110 111 No delay Chroma 1 chroma pixel late Chroma 2 chroma pixel late Chroma 3 chroma pixel late Not used Rev 0 Page 38 of 96 ADV7183B SYNCHRONIZATION OUTPUT SIGNALS HSE 10 0 HS End Address 0x34 2 0 Address 0x36 7 0 HS Configuration The position of this edge is controlled by placing a binary The following controls allow the user to configure the behavior number into HSE 10 0 The number applied offsets the edge of the HS output pin only with respect to an internal counter that is reset to 0 immediately after EAV code FE00 00 XY see Figure 20 HSE is set to Beginning of HS signal via HSB 10 0 00000000000b which is 0 LLC1 clock cycles from count 0 End of HS signal via HSE 10 0 The default value of HSE 9 0 is 000 indicating that the HS Polarity of HS using PHS pulse ends 0 pixels after falling edge of HS F le The HS Begin and HS End registers allow the user to freely position the HS output pin within the video line The values 1 To shift the HS toward active video by 20 LLC1s add in HSB 10 0 and HSE 10 0 are measured in pixel units from 20 LLC1s to both HSB and HSE that is HSB 10 0 the falling edge of HS Using both values the user can program 00000010110 HSE 10 0 00000010100 both the position and length of the HS output signal 2 shift the HS away from active video by 20 LLC1s add HSB 10 0 HS
12. Previous revisions of the ADV7183B had controls FACL FICL fast and fine clamp length to allow configuration of the length for which the coarse fast and fine current sources are switched on These controls were removed on the ADV7183B FT and replaced by an adaptive scheme CCLEN Current Clamp Enable Address 0x14 4 The current clamp enable bit allows the user to switch off the current sources in the analog front end altogether This may be useful if the incoming analog video signal is clamped externally When CCLEN is 0 the current sources are switched off When CCLEN is 1 default the current sources are enabled DCT 1 0 Digital Clamp Timing Address 0x15 6 5 The Clamp Timing register determines the time constant of the digital fine clamp circuitry It is important to realize that the digital fine clamp reacts very quickly since it is supposed to immediately correct any residual dc level error for the active line The time constant of the digital fine clamp must be much quicker than the one from the analog blocks By default the time constant of the digital fine clamp is adjusted dynamically to suit the currently connected input signal Table 28 DCT Function DCT 1 0 Description 00 Slow 1 sec 01 Medium TC 0 5 sec 10 default Fast TC 0 1 sec 11 Determined by the ADV7183B depending on the I P video parameters DCFE Digital Clamp Freeze Enable Address 0x15 4 This register
13. the ADV7183B powered down by default When PDBD is 0 default the digital core power is controlled by the PWRDN pin the bit is disregarded When PDBD is 1 the bit has priority the pin is disregarded PWRDN Address 0x0F 5 Setting the PWRDN bit switches the ADV7183B into a chip wide power down mode The power down stops the clock from entering the digital section of the chip thereby freezing its operation No I C bits are lost during power down The PWRDN bit also affects the analog blocks and switches them into low current modes The interface itself is unaffected and remains operational in power down mode The ADV7183B leaves the power down state if the PWRDN bit is set to 0 via PC or if the overall part is reset using RESET pin Note that PDBP must be set to 1 for the PWRDN bit to power down the ADV7183B When PWRDN is 0 default the chip is operational When PWRDN is 1 the ADV7183B is in chip wide power down ADC Power Down Control The ADV7183B contains three 10 bit ADCs ADC 0 ADC 1 and ADC 2 If required it is possible to power down each ADC individually When should the ADCs be powered down e CVBS mode ADC 1 and ADC 2 should be powered down to save on power consumption e S Video mode ADC 2 should be powered down to save on power consumption PWRDN ADC 0 Address 0x3A 3 When PWRDN 0 is 0 default the ADC is in normal operation When PWRDN_ADC_0 is 1 ADC 0 is powe
14. Reserved ya Set to 1 CAGT 1 0 Chroma automatic gain Slow TC 2 s Has an effect only if timing allows adjustment of the 0l 1 Medium TC 1 s CAGC 1 0 is set to chroma AGC tracking speed 170 Fast TC 025 auto gain 10 1 1 Adaptive Ox2E Chroma CMG 7 0 Chroma manual gain 1 1 0 750d gain is Min value is Od Gain lower 8 bits See CMG 11 8 for 1 in NTSC G 60 dB Control 2 description CMG 11 0 7414 gain is Max value is 3750 PAL G 5 Ox2F Luma Gain LMG 11 8 Luma manual gain can x LAGC 1 0 settings decide Control 1 be used program a desired manual in which mode LMG 1 1 0 chroma gain or to read back the Operates actual gain value used Reserved 1 1 Set to 1 LAGT 1 0 Luma automatic gain Slow 2 5 Only has an effect if timing allows adjustment of the 0l 1 Medium TC 1 s LAGC 1 0 is set to luma AGC tracking speed auto gain 001 010 110 Fast TC 0 2 5 011 0r 100 1 1 Adaptive 0x30 Luma Gain LMG 7 0 Luma manual gain canbe x x x x x LMG 11 0 1234dec gain Min value Control 2 used to program a desired manual is 1 in NTSC LMG 11 0 NTSC 1024 0 85 chroma gain or read back the actual 1266d gain is 1 in PAL PAL G 0 81 used gain value Max value NTSC 2468 G 2 PAL 2532 2 0x31 VS and Reserved Set to default Urna 1 HVSTIM Selects where within line 0 Start of line relative to HSE HSE Hsync end of video the VS signal
15. The resolution of HUE 7 0 is 1 bit 0 77 The hue adjustment value is fed into the AM color demodulation block Therefore it only applies to video signals that contain chroma information in the form of an AM modulated carrier CVBS or Y C in PAL or NTSC It does not affect SECAM and does not work on component video inputs YPrPb Table 27 HUE Function HUE 7 0 Description 0x00 default Phase of the chroma signal 0 Ox7F Phase of the chroma signal 90 0x80 Phase of the chroma signal 90 SD_OFF_Cb 7 0 0x80 default 0x00 OxFF Description 0 offset applied to the Cb channel 312 mV offset applied to the Cb channel 312 mV offset applied to the Cb channel SD OFF Cr 7 0 SD Offset Cr Channel Address 0xE2 7 0 This register allows the user to select an offset for data on the Cr channel only and adjust the hue of the picture There is a func tional overlap with the Hue 7 0 register Table 25 SD OFF Cr Function SD OFF Cti 7 0 Description 0x80 default 0 offset applied to the Cr channel 0x00 312 mV offset applied to the Cr channel OxFF 312 mV offset applied to the Cr channel BRI 7 0 Brightness Adjust Address 0x0A 7 0 This register controls the brightness of the video signal It allows the user to adjust the brightness of the picture Table 26 BRI Function BRI 7 0 Description 0x00 default Offset of the luma channel OIRE Ox7F O
16. 0 Page 66 of 96 Table 84 Interrupt Register Map Details ADV7183B Bit Subaddress Register Bit Description 71615 43 1 0 Comments Notes 0x40 Interrupt INTRQ_OP_SEL 1 0 010 Open drain Config 1 Interrupt Drive Level Select ola Drive low when active 110 Drive high when active Register 111 Reserved Access n 2 MPU_STIM_INTRQ 1 0 Manual interrupt mode disabled Manual Interrupt Set Mode Manual interrupt mode enabled Reserved x Not used MV_INTRQ_SEL 1 0 010 Reserved Macrovision Interrupt Select 011 Pseudo sync only 1 0 Color stripe only 111 Pseudo sync or color stripe INTRQ_DUR_SEL 1 0 010 3 Xtal periods Interrupt duration Select 011 15 Xtal periods 110 63 Xtal periods 1 1 Active until cleared 0x41 Reserved X X Xxx x x 0x42 Interrupt SD_LOCK_Q 0 No change Status 1 1 SD input has caused the These bits decoder to go from an unlocked be Read Only state to a locked state cleared or SD_UNLOCK_Q 0 No change masked in Resisters Register 1 SD input has caused the 0x43 and Access decoder to go from a locked 0x44 Page 2 state to an unlocked state respectively Reserved Reserved x Reserved x SD_FR_CHNG_Q 0 No Change 1 Denotes a change in the free run status MV_PS_CS_Q 0 No Change 1 Pseudo sync color striping detected See Reg 0x40 MV_INTRQ_SEL 1 0 for selection Reserved x 0x43 Interrupt SD_LOCK_CLR 0 Do not clear Clear
17. 1 1 1 PALWN1 1 1 0 0 0 PALWN2 111 010 1 NTSCNN1 111 O 1 0 NTSCNN2 1 1 O 1 1 NTSC NN3 111 1 0 0 NTSCWN1 111 1 0 1 NTSCWN2 1 1 1 1 0 NTSC WN3 1 1 141 1 Reserved CSFM 2 0 0 0 0 Auto selection 15 MHz Automatically selects C Shaping Filter mode allows the olo 1 Auto selection 2 17 MHz a C filter based on selection from a range of low pass video standard and chrominance filters quality If either auto mode is selected the 0 1 0 SH1 Selects a C filter for decoder selects the optimum C filter o 1 1 SH2 all video standards depending on the CVBS video llo lo SH3 and for good and source quality good vs bad Non bad video auto settings force a C filter for all 110 1 SH4 standards and quality of CVBS video 1 1 0 SH5 1 1 1 Wideband mode Rev 0 Page 75 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 2 1 0 Comments Notes 0x18 Shaping WYSFM 4 0 Wideband Y Shaping 0 0 0 0 0 Reserved Do not use Filter Filter mode allows the user to select olo 1 Reserved Do not use opo o ses input signals it is also used when a 0 1 1 SVHS2 good quality input CVBS signal is SVHS3 alte eva ty ofo by
18. Gemstar 4 14 GDECOL 4 Gemstar 5 15 GDECOL 5 Gemstar 6 16 GDECOL 6 Gemstar 7 17 GDECOL 7 Gemstar 8 18 GDECOL 8 Gemstar 9 19 GDECOL 9 Gemstar 10 20 GDECOL 10 Gemstar 11 21 GDECOL 11 Gemstar or closed caption 12 22 GDECOL 12 Gemstar 13 23 GDECOL 13 Gemstar 14 24 GDECOL 14 Gemstar 15 25 GDECOL 15 Gemstar 0 273 10 GDECEL 0 Gemstar 1 274 11 GDECEL 1 Gemstar 2 275 12 GDECEL 2 Gemstar 3 276 13 GDECEL 3 Gemstar 4 277 14 GDECEL 4 Gemstar 5 278 15 GDECEL 5 Gemstar 6 279 16 GDECEL 6 Gemstar 7 280 17 GDECEL 7 Gemstar 8 281 18 GDECEL 8 Gemstar 9 282 19 GDECEL 9 Gemstar 10 283 20 GDECEL 10 Gemstar 11 284 21 GDECEL 11 Gemstar or closed caption 12 285 22 GDECEL 12 Gemstar 13 286 23 GDECEL 13 Gemstar 14 287 24 GDECEL 14 Gemstar 15 288 25 GDECEL 15 Gemstar Rev 0 Page 56 of 96 ADV7183B Table 74 PAL Line Enable Bits and Corresponding Line Numbering Line Number line 3 0 ITU RBT 470 Enable Bit Comment 12 8 GDECOL 0 Not valid a 13 9 GDECOL 1 Not valid 14 10 GDECOL 2 Not valid 15 11 GDECOL 3 Not valid 0 12 Not valid 1 13 GDECOL 5 Not valid 2 14 GDECOL 6 Not valid 2 3 15 GDECOL 7 Not valid 4 16 GDECOL 8 Not valid 2 0 2 5 3 0 3 5 4 0 45 50 5 17 GDECOL 9 Not valid FREQUENCY MHz 6 18 GDECOL 10 Not valid Figure 36 NTSC IF Compensation Filter Responses 7 19 GDECOL 11
19. INTRQ_OP_ INTRQ_OP_ Config 0 x000 _SEL 1 _SEL O SEL 1 SEL O INTRQ SEL 1 SEL O Reserved 65 0x41 Interrupt r 66 0x42 MV_PS_CS_ SD_FR_CHN SD_UNLOCK SD_LOCK_Q Status 1 Q G_Q 0 Interrupt 000 w 67 0x43 MV_PS_CS_ SD_FR_CHN SD_UNLOCK SD_LOCK_ Clear 1 0000 CLR G_CLR _CLR CLR Interrupt x000 rw 68 0x44 MV_PS_CS_ SD_FR_CHN SD_UNLOCK SD_LOCK_ Maskb 1 0000 MSKB G_MSKB _MSKB MSKB Reserved 69 0x45 Interrupt 70 0x46 MPU_STIM_ WSS_ CGMS_ GEMD_Q CCAPD_Q Status 2 INTRQ_Q CHNGD_Q CHNGD_Q Interrupt w 71 0x47 MPU_STIM_ WSS CGMS CHN GEMD CLR CCAPD CLR Clear 2 0000 INTRO CLR CHNGD CLR GD CLR Interrupt Oxxx rw 72 0x48 MPU_STIM_ WSS_ CGMS_ GEMD_ CCAPD_ Maskb 2 0000 INTRQ_ CHNGD_ CHNGD_ MSKB MSKB MSKB MSKB MSKB Raw r 73 0x49 SCM_LOCK SD_H_LOCK SD_V_LOCK 50 Status 3 50HZ Interrupt 74 0 4 PAL SW SCM_LOCK_ SD AD SD 50 50 Status _CHNG_Q CHNG_Q CHNG_Q CHNG CHNG CHNG Interrupt 00 w 75 Ox4B PAL SW LK SCM LOCK SD AD CH SD_H_LOCK SD_V_LOCK 50 Clear 3 0000 CHNG CLR CHNG CLR NG CLR CHNG CLR CHNG CLR CHNG CLR Interrupt xx00 rw 76 Ox4C PAL SW LK SCM_LOCK_ SD AD SD SD_V_LOCK 50 Maskb 3 0000 _CHNG_ CHNG_ CHNG_ _CHNG_ _CHNG_ CHNG_ MSKB MSKB MSKB MSKB MSKB MSKB 1 access the Interrupt Register the Register Access page 1 0 in Register Address must be programmed to 01b Rev
20. Not valid 8 20 GDECOL 12 Not valid 9 21 GDECOL 13 Not valid 10 22 GDECOL 14 Closed caption 11 23 GDECOL 15 Not valid 12 321 8 GDECEL 0 Not valid 13 322 9 GDECEL 1 Not valid 14 323 10 GDECEL 2 Not valid 8 15 324 11 GDECEL 3 Not valid 5 0 325 12 GDECEL 4 Not valid 2 1 326 13 GDECEL 5 Not valid 2 327 14 GDECEL 6 Not valid 3 328 15 GDECEL 7 Not valid 4 329 16 GDECEL 8 Not valid 2 5 330 17 GDECEL 9 Not valid 3 0 35 40 T5 50 5 5 5 0 6 331 18 GDECEL 10 Not valid 7 332 19 GDECEL 11 Not valid Figure 37 PAL IF Compensation Filter Responses 8 333 20 GDECEL 12 Not valid See Table 85 for programming details 9 334 21 GDECEL 13 Not valid 2 5 10 335 22 GDECEL 14 Closed caption I C Interrupt System 11 336 23 GDECEL 15 Not valid The ADV7183B has a comprehensive interrupt register set This map is located in Register Access Page 2 See Table 83 for details of the interrupt register map IF Compensation Filter How to access this map is described in Figure 38 IFFILTSEL 2 0 IF Filter Select Address OxF8 2 0 The IFFILTSEL 2 0 register allows the user to compensate for SAW filter characteristics on a Composite input as would be observed on tuner outputs Figure 36 and Figure 37 show IF filter compensation for NTSC and PAL COMMON 2 SPACE ADDRESS 0x00 gt 0x3F ADDRESS 6 5 00b ADDRESS 6 5 01b
21. The following section describes each register in terms of its configuration The Communications register is an 8 bit write only register After the part has been accessed over the bus and a read write operation is selected the subaddress is set up The Subaddress register determines to from which register the operation takes place Table 81 lists the various operations under the control of the Subaddress register for the control port Register Select SR7 SRO These bits are set up to point to the required starting address ADV7183B SEQUENCER An sequencer is used when a parameter exceeds eight bits and is therefore distributed over two or more registers for example HSB 11 0 When such a parameter is changed using two or more I C write operations the parameter may hold an invalid value for the time between the first PC being completed and the last PC being completed In other words the top bits of the parameter may already hold the new value while the remaining bits of the parameter still hold the previous value To avoid this problem the sequencer holds the already updated bits of the parameter in local memory all bits of the parameter are updated together once the last register write operation has completed The correct operation of the sequencer relies on the following registers for the parameter in question must be written to in order of ascending addresses For example
22. The options for this feature are as follows 12C SPACE REGISTER ACCESS PAGE 1 12C SPACE REGISTER ACCESS PAGE 2 ADDRESS 0x40 gt OxFF ADDRESS 0x40 gt 0x4C NORMAL REGISTER SPACE INTERRUPT REGISTER SPACE Figure 38 Register Access Page 1 and Page 2 e Bypass mode default 04997 0 044 e NTSC consists of three filter characteristics e PAL consists of three filter characteristics Rev 0 Page 57 of 96 ADV7183B Interrupt Request Output Operation When an interrupt event occurs the interrupt pin INTRQ goes low with a programmable duration given by INTRQ_DUR_SEL 1 0 INTRQ DURSEL 1 0 Interrupt Duration Select Address 0x40 Interrupt Space 7 6 Table 75 INTRQ_DUR_SEL INTRQ_OP_SEL 1 0 Interrupt Duration Select Address 0x40 Interrupt Space 1 0 Table 76 INTRQ_OP_SEL INTRQ_OP_SEL 1 0 Description 00 default Open drain 01 Drive low when active 10 Drive high when active 11 Reserved INTRQ_DURSEL 1 0 Description 00 default 3 Xtal periods 01 15 Xtal Periods 10 63 Xtal Periods 11 Active until Cleared When Active until Cleared interrupt duration is selected and the event that caused the interrupt is no longer in force the interrupt persists until it is masked or cleared For example if the ADV7183B loses lock an interrupt is generated and INTRQ pin goes low If the ADV7183B returns to the locked state INTRQ continues to drive low until
23. signals Table 41 CKILLTHR Function CG 11 0 CMG 11 0 Read Write Description CMG 11 0 Write Manual gain for chroma path CG 11 0 Read Currently active gain 0 4095 Chroma _ Gain 0 4 2 1024 For example freezing the automatic gain loop and reading back the CG 11 0 register results in a value of 0x47A 1 Convert the readback value to decimal 0x47A 1146d 2 Apply Equation 2 to convert the readback value 1146 1024 1 12 CKE Color Kill Enable Address 0x2B 6 The Color Kill Enable bit allows the optional color kill function to be switched on or off For QAM based video standards PAL and NTSC as well as FM based systems SECAM the threshold for the color kill decision is selectable via the CKILLTHR 2 0 bits If color kill is enabled and if the color carrier of the incoming video signal is less than the threshold for 128 consecutive video lines color processing is switched off black and white output To switch the color processing back on another 128 consecutive lines with a color burst greater than the threshold are required The color kill option only works for input signals with a modu lated chroma part For component input YPrPb there is no color kill Setting CKE to 0 disables color kill Setting CKE to 1 default enables color kill Description CKILLTHR 2 0 SECAM NTSC PAL 000 No color kill Kill at 0 596 001 Kill at 596 Kill a
24. the data word D 8 0 Even parity means there will always be an even number of 1s within the D 8 0 bit arrangement This includes the EP bit describes the logic inverse of EP and is output on D 9 The EP is output to ensure that the reserved codes of 00 and FF cannot happen EF Even field identifier EF 1 indicates that the data was recovered from a video line on an even field 2X This bit indicates whether the data sliced was in Gemstar 1x or 2x format A high indicates 2x format e line 3 0 This entry provides a code that is unique for each of the possible 16 source lines of video from which Gemstar data may have been retrieved Refer to Table 73 and Table 74 DC I 0 Data count value The number of user data words in the packet divided by 4 The number of user data words UDW in any packet must be an integral number of 4 Padding is required at the end if necessary as set in ITU R BT 1364 See Table 64 The 2X bit determines whether the raw information retrieved from the video line was 2 or 4 bytes The state of the GDECAD bit affects whether the bytes are transmitted straight i e two bytes transmitted as two bytes or whether they are split into nibbles 1 two bytes added where necessary e CS 82 The checksum is provided to determine the integrity of the ancillary data packet It is calculated by summing up D 8 2 of DID SDID the Data Count byte and all UDWs and ignoring any overfl
25. 0 TVA 0 1 2 3 4 5 6 7 o 1 2 s a T5 e 50 A R R T T T Y Y BYTE 0 BYTE 1 40 IRE REFERENCE COLOR BURST 9 CYCLES FREQUENCY Fac 3 579545MHz AMPLITUDE 40 IRE 10 003 5 27 382us 33 764us 5 Table 60 CCAP Access Information Figure 34 Closed Caption Data Extraction Signal Name Register Location Address Register Default Value CCAP 1 7 0 CCAP1 7 0 153d 0x99 Readback Only CCAP2 7 0 CCAP2 7 0 154d Ox9A Readback Only Rev 0 Page 49 of 96 ADV7183B Letterbox Detection Incoming video signals may conform to different aspect ratios 16 9 wide screen of 4 3 standard For certain transmissions in the wide screen format a digital sequence WSS is transmitted with the video signal If a WSS sequence is provided the aspect ratio of the video can be derived from the digitally decoded bits WSS contains In the absence of a WSS sequence letterbox detection may be used to find wide screen signals The detection algorithm examines the active video content of lines at the start and end of a field If black lines are detected this may indicate that the currently shown picture is in wide screen format The active video content luminance magnitude over a line of video is summed together At the end of a line this accumulated value is compared with a threshold and a decision is made as to whether or not a particular line is black The threshold value needed may depend on the type of
26. 0 bits default to an autodetection mode that supports PAL NTSC SECAM and variants thereof The following section describes the autodetec tion system Autodetection of SD Modes In order to guide the autodetect system individual enable bits are provided for each of the supported video standards Setting the relevant bit to 0 inhibits the standard from being detected automatically Instead the system picks the closest of the remaining enabled standards The results of the autodetection can be read back via the status registers See the Global Status Registers section for more information VID SEL 3 0 Address 0x00 7 4 Table 18 VID SEL Function VID SEL Description 0000 default Autodetect PAL BGHID NTSC J no pedestal SECAM 0001 Autodetect PAL BGHID lt gt NTSC M pedestal SECAM 0010 Autodetect PAL pedestal lt gt NTSC J no pedestal SECAM 0011 Autodetect PAL N pedestal NTSC M pedestal SECAM 0100 NTSC J 1 0101 NTSC M 1 0110 PAL 60 0111 NTSC 4 43 1 1000 PAL BGHID 1001 PAL PAL BGHID with pedestal 1010 PAL M without pedestal 1011 PAL M 1100 PAL combination N 1101 PAL combination N with pedestal 1110 SECAM 1111 SECAM with pedestal AD 5 525 EN Enable Autodetection of SECAM 525 Line Video Address 0x07 7 Setting AD SEC525 EN to 0 default disables the autodetection of a 525 line system with SECAM style FM mo
27. 0 Gemstar word2 7 4 0 0 User data words 9 IEP EP 0 0 Gemstar word2 3 0 0 0 User data words 10 IEP EP 0 0 Gemstar word3 7 4 0 0 User data words 11 0 0 Gemstar word3 3 0 0 0 User data words 12 IEP EP 0 0 Gemstar word4 7 4 0 0 User data words 13 IEP EP 0 0 Gemstar word4 3 0 0 0 User data words 14 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Checksum Table 66 Gemstar 2x Data Full Byte Mode Byte DI9 DI8 DI7 DI6 D 5 0 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 Gemstar word1 7 0 0 0 User data words 7 Gemstar word2 7 0 0 0 User data words 8 Gemstar word3 7 0 0 0 User data words 9 Gemstar word4 7 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 5 4 CS 3 CS 2 CS 1 5 0 Checksum Table 67 Gemstar 1x Data Half Byte Mode Byte DI9 DI8 DI7 DI6 D 5 D 4 0121 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 line 3 0 0 0 SDID 5 0 0 0 0 0 1 0 0 Data count 6 0 0 Gemstar word1 7 4 0 0 User data words 7 IEP EP 0 0 Gemstar word1 3 0 0 0 User data words 8
28. 10 dB 5 dB 1 0 Reserved 3 MHz 6 MHz PAL Filters 1 1 2 dB 2 dB 1 0 5 dB 3 dB 1 1 7 dB 5 dB Reserved 0 0 0 OxF9 VS Mode EXTEND_VS_MAX_FREQ 0 Limit maximum Vsync Control frequency to 66 25 Hz 475 lines frame 1 Limit maximum Vsync frequency to 70 09 Hz 449 lines frame EXTEND VS MIN FREQ Limit minimum Vsync frequency to 42 75 Hz 731 lines frame Limit minimum Vsync frequency to 39 51 Hz 791 lines frame VS COAST 1 0 010 Auto Coast mode This value sets up 0 1 50 Hz Coast mode is output coast 110 60 Hz Coast mode 1 1 Reserved Reserved 0 87 96 ADV7183B 2 PROGRAMMING EXAMPLES MODE 1 CVBS INPUT COMPOSITE VIDEO ON 5 All standards are supported through autodetect 8 bit 4 2 2 ITU R BT 656 output P15 P8 Table 86 Mode 1 CVBS Input Register Address Register Value Notes 0x00 0x04 CVBS input on AIN5 0x15 0x00 Slow down digital clamps 0x17 0x41 Set CSFM to SH1 0x3A 0x16 Power down ADC 1 and ADC 2 0x50 0x04 Set DNR threshold to 4 for flat response OxOE 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x50 0x20 Recommended setting 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 5 Recommended setting 0 7 0x93 Recommended setting 0x7D 0x00 Recommended setting 0xD0 0x48 R
29. 4 OR 8 WORDS Figure 35 Gemstar and CCAP Embedded Data Packet Generic Table 63 Generic Data Output Packet Byte D 9 DI8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 2X line 3 0 0 0 SDID 5 IEP EP 0 0 0 0 DC 1 DC 0 0 0 Data count DC 6 IEP EP 0 0 word1 7 4 0 0 User data words 7 IEP EP 0 0 word1 3 0 0 0 User data words 8 IEP EP 0 0 word2 7 4 0 0 User data words 9 IEP EP 0 0 word2 3 0 0 0 User data words 10 IEP EP 0 0 word3 7 4 0 0 User data words 11 IEP EP 0 0 word3 3 0 0 0 User data words 12 IEP EP 0 0 word4 7 4 0 0 User data words 13 IEP EP 0 0 word4 3 0 0 0 User data words 14 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 0 0 Checksum Rev 0 Page 51 of 96 ADV7183B Table 64 Data Byte Allocation Raw Information Bytes User Data Words 2x Retrieved from the Video Line GDECAD Including Padding Padding Bytes DC 1 0 1 4 0 8 0 10 1 4 1 4 0 01 0 2 0 4 0 01 0 2 1 4 2 01 Gemstar Bit Names transmitted as four half bytes Padding bytes are then e DID The data identification value is 0x140 10 bit value Care has been taken that in 8 bit systems the 2 LSBs do not carry vital information EPand EP The EP bit is set to ensure even parity
30. 5 4 01 11100 SVHS5 11111 SVHS6 0 1 0 0 0 SVHS7 0 1 010 1 SVHS8 Oo 1 01110 SVHS9 0 1 011 1 SVHS10 0 1 1100 SVHS 11 0 1 110 1 SVHS 12 Oo 1 1 11 0 SVHS 13 0 1 1 11 1 SVHS 14 1 0 010 0 SVHS15 1 0 010 1 SVHS 16 1 0 14 0 SVHS 17 110 0 1 1 SVHS 18 CCIR 601 110 1 0 0 Reserved Do not use Reserved Do not use 111 1 1 1 Reserved Do use Reserved 0 Set default WYSFMOVR Enables the use of 0 Manual select filter using automatic WYSFN filter WYSFMI A 0 1 Auto selection of best filter 0x19 Comb PSFSEL 1 0 Controls the signal 0 0 Narrow Filter bandwidth that is fed to the comb 0 1 Medium Control filters PAL 110 Wide 1 1 Widest NSFSEL 1 0 Controls the signal Narrow bandwidth that is fed to the comb 11 Medium filters NTSC 110 Medium 1 1 Wide Reserved Set as default 0x1D ADI Reserved 0 0 x x Set to default Control2 vs COMP EN 0 Enabled 1 Disabled EN28XTAL 0 Use 27 MHz crystal 1 Use 28 MHz crystal TRI LLC 0 LLC pin active 1 LLC pin three stated Rev 0 Page 76 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 1 0 Comments Notes 0x27 Pixel Delay LTA 1 0 Luma timin
31. 76 0x4C CTI DNR Ctrl 1 11101111 rw 77 0x4D CTI DNR Ctrl 2 0000 1000 rw 78 0x4E Reserved XXXX XXXX rw 79 0x4F CTI DNR Ctrl 4 0000 1000 rw 80 0x50 Lock Count 0010 0100 rw 81 0x51 Reserved XXXX XXXX rw 82 142 0x52 0x8E Free Run Line Length 1 0000 0000 w 143 0x8F Reserved 0000 0000 w 144 0x90 VBI Info XXXX XXXX r 144 0x90 WSS 1 XXXX XXXX r 145 0x91 WSS 2 XXXX XXXX r 146 0x92 EDTV 1 XXXX XXXX r 147 0x93 EDTV 2 XXXX XXXX r 148 0x94 EDTV 3 XXXX XXXX r 149 0x95 CGMS 1 XXXX XXXX r 150 0x96 CGMS 2 XXXX XXXX r 151 0x97 CGMS 3 XXXX XXXX r 152 0x98 CCAP1 XXXX XXXX r 153 0x99 CCAP2 XXXX XXXX r 154 9 Letterbox 1 XXXX XXXX r 155 0x9B Letterbox 2 XXXX XXXX r 156 0x9C Letterbox 3 XXXX XXXX r 157 0x9D Reserved XXXX XXXX rw 158 177 0x9E 0xB1 CRC Enable 0001 1100 178 OxB2 Reserved XXXX XXXX rw 179 194 2 0 2 ADC Switch 1 XXXX XXXX rw 195 0xC3 ADC Switch 2 rw 196 0xC4 Reserved XXXX XXXX rw 197 219 0xC5 0xDB Letterbox Control 1 1010 1100 rw 220 0xDC Letterbox Control 2 0100 1100 rw 221 0xDD Reserved 0000 0000 rw 222 OxDE Reserved 0000 0000 rw 223 OxDF Reserved 0001 0100 rw 224 0 0 SD Offset Cb 1000 0000 rw 225 OxE1 SD Offset Cr 1000 0000 rw 226 OxE2 SD Saturation Cb 1000 0000 rw 227 OxE3 SD Saturation Cr 1000 0000 rw 228 OxE4 NTSC V Bit Begin 0010 0101 rw 229 0 5 NTSC V Bit End 0000 0100 rw 230 OxE6 NTSC F Bit Toggle 01100011 rw 231 OxE7 PAL V Bit Begin 01100101 rw 232 OxE8 PAL V Bit End 0001 0100 rw 233 OxE9 PAL F
32. Bit Toggle 01100011 rw 234 OxEA Rev 0 Page 63 of 96 ADV7183B Subaddress Register Name Reset Value rw Dec Hex Reserved XXXX XXXX rw 235 243 OxEB OxF3 Drive Strength xx01 0101 rw 244 OxF4 Reserved XXXX XXXX rw 245 247 OxF5 OxF7 IF Comp Control 0000 0000 rw 248 OxF8 VS Mode Control 0000 0000 rw 249 OxF9 Table 82 Common and Normal Page 1 Register Map Bit Names Register Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input Control VID_SEL 3 VID_SEL 2 VID_SEL 1 VID_SEL O INSEL 3 INSEL 2 INSEL 1 INSEL O Video Selection ENHSPLL BETACAM ENVSPROC Reserved Output Control EN TOD SEL 3 OF SEL 2 OF SEL 1 OF SEL O SD DUP AV Extended Output Control BT656 4 TIM OE BL C VBI EN SFL PI RANGE Reserved Reserved Autodetect Enable AD SEC525 EN AD SECAM EN AD 443 EN AD P60 EN AD PALN EN AD PALM EN AD NTSC EN AD PAL EN Contrast CON 7 CON 6 5 CON 4 CON 3 CON 2 CON 1 CON O Reserved Brightness BRI 7 BRI 6 BRI 5 BRI 4 BRI 3 BRI 2 BRI 1 BRI O Hue HUE 7 HUE 6 HUE 5 HUEA HUE 3 HUE 2 HUE 1 HUE O Default Value Y DEF Y 5 DEF YA DEF DEF 2 DEF Y 1 DEF 0 DEF VAL DEF VAL EN AUTO EN Default Value C DEF C7 DEF 6 DEF C 5 DEF DEF C 3 DEF C2 DEF C 1 DEF 0 ADI Control SUB USR 0 Power Management RES PWRDN PDBP Status 1 COL KILL AD RESULT 2 AD RESULT 1
33. CR2 SD OFF SD OFF CRO SD Saturation Cb SD SAT 7 SD SAT 6 SD SAT CB 5 SD SAT SD SAT CB 3 SD SAT CB2 SD SAT CB 1 SD SAT 0 SD Saturation Cr SD SAT 7 SD SAT 6 SD SAT 5 SD SAT SD SAT CR3 SD SAT CR2 SD SAT CR 1 SD SAT CRO NTSC V Bit Begin NVBEGDEL O NVBEGDEL E NVBEGSIGN NVBEG 4 NVBEG 3 NVBEG 2 NVBEG 1 NVBEG O NTSC V Bit End NVENDDEL O NVENDDEL E NVENDSIGN NVEND 4 NVEND 3 NVEND 2 NVEND 1 NVEND O NTSC F Bit Toggle NFTOGDEL O NFTOGDEL E NFTOGSIGN NFTOG 4 NFTOG 3 NFTOG 2 NFTOG 1 NFTOG O PAL V Bit Begin PVBEGDEL O PVBEGDEL E PVBEGSIGN PVBEG 4 PVBEG 3 PVBEG 2 PVBEG 1 PVBEG O PAL V Bit End PVENDDEL O PVENDDEL E PVENDSIGN PVEND 4 PVEND 3 PVEND 2 PVEND 1 PVEND O PAL F Bit Toggle PFTOGDEL O PFTOGDEL E PFTOGSIGN PFTOG 4 PFTOG 3 PFTOG 2 PFTOG 1 0 Reserved Drive Strength DR_STR 1 DR_STR O DR_STR_C 1 DR STR COO DR STR 5 1 DR STR S 0 Reserved IF Comp Control IFFILTSEL 2 IFFILTSEL 1 IFFILTSEL O VS Mode Control VS COAST VS COAST EXTEND VS EXTEND VS MODE 1 MODE O MIN_FREQ MAX_FREQ Rev 0 Page 65 of 96 ADV7183B PC REGISTER MAP DETAILS The following registers are located in the Common map and Register Access Page 2 Table 83 Interrupt Register Map Details Register Reset Subaddress Name Value rw Dec Hex Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Interrupt 0001 rw 64 0x40 INTRQ_DUR INTRQ_DUR MV_INTRQ_ MV_INTRQ_ MPU_STIM_
34. FSCLE to 0 default makes the overall lock status dependent on only horizontal sync lock Setting FSCLE to 1 makes the overall lock status dependent on horizontal sync lock and Fsc lock CIL 2 0 Count Into Lock Address 0x51 2 0 CIL 2 0 determines the number of consecutive lines for which the into lock condition must be true before the system switches into the locked state and reports this via Status 0 1 0 It counts the value in lines of video Table 19 CIL Function ADV7183B COL 2 0 Count Out of Lock Address 0x51 5 3 COL 2 0 determines the number of consecutive lines for which the out of lock condition must be true before the system switches into unlocked state and reports this via Status 0 1 0 It counts the value in lines of video Table 20 COL Function COL 2 0 Description 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100000 COLOR CONTROLS These registers allow the user to control the picture appearance including control of the active data in the event of video being lost These controls are independent of any other controls For instance brightness control is independent from picture clamping although both controls affect the signals dc level CON 7 0 Contrast Adjust Address 0x08 7 0 This allows the user to adjust the contrast of the picture Table 21 CON Function CON 7 0 Description 0x80 default Gain on luma channel 1 0x00 Gain on
35. Hz It is essential that the cutoff of this filter be less than 1 Hz to ensure correct operation of the internal clamps within the part These clamps ensure that the video stays within the 5 V range of the op amp used 0 40 80 100 04997 0 040 120 100k 300k 1M 3M 10M 30M 100M 300M 1G FREQUENCY Hz Figure 43 Third Order Butterworth Filter Response Rev 0 Page 91 of 96 ADV7183B TYPICAL CIRCUIT CONNECTION Examples of how to connect the ADV7183B video decoder are shown in Figure 44 and Figure 45 For a detailed schematic diagram for the ADV7183B refer to the ADV7183B evaluation note AVDD_5V FILTER 110 12uH o z 04997 0 041 Figure 44 ADI Recommended Antialiasing Circuit for All Input Channels Rev 0 Page 92 of 96 DVDDIO 3 3V 9 PVDD o 1 8V AVDD o 3 3V DVDD 1 8 9 AGND DGND AGND T 1ouF d CAPY2 ua AGND CAPC1 FERRITE BEAD 33uF Q 10uF Ven FERRITE BEAD 97 33uF 10uF FERRITE BEAD Q 33uF 10uF FERRITE BEAD 07 33uF 10uF Voenp 100nF 100nF 100nF 100nF 100nF E e e 5 V AGND CAPY1 O 1uF 1nF 10uF 0 1uF 1 AGND CAPC2 CML 10pF 0 1pF REFOUT Y 10uF 0 1uF AGND DVDDIO ae 27MHz eit DGND 15pF ADDRESS 5 DGND DVSS DVDDIO DVDDIO O O 2kQ MPU IN
36. Rev 0 Page 24 of 96 DEF_VAL_EN Default Value Enable Address 0x0C 0 This bit forces the use of the default values for Y Cr and Cb Refer to the descriptions for DEF_Y and DEF_C for additional information In this mode the decoder also outputs a stable 27 MHz clock HS and VS Setting DEF_VAL_EN to 0 default outputs a colored screen determined by user programmable Y Cr and Cb values when the decoder free runs Free run mode is turned on and off by the DEF_VAL_AUTO_EN bit Setting DEF_VAL_EN to 1 forces a colored screen output determined by user programmable Y Cr and Cb values This overrides picture data even if the decoder is locked DEF VAL AUTO EN Default Value Automatic Enable Address 0x0C 1 This bit enables the automatic usage of the default values for Y Cr and Cb when the ADV7183B cannot lock to the video signal Setting DEF VAL AUTO EN to 0 disables free run mode If the decoder is unlocked it outputs noise Setting DEF VAL EN to 1 default enables free run mode A colored screen set by the user programmable Y Cr and Cb values is displayed when the decoder loses lock CLAMP OPERATION The input video is ac coupled into the ADV7183B Therefore its dc value needs to be restored This process is referred to as clamping the video This section explains the general process of camping on the ADV7183B and shows the different ways in which a user can configure its behavior The ADV7183B uses a combinat
37. and 40 C to 85 80 lead LQFP Pb free package APPLICATIONS DVD recorders Video projectors HDD based PVRs DVDRs LCD TVs Set top boxes Security systems Digital televisions AVR receiver combinations AGC and clamp restore circuitry allow an input video signal peak to peak range of 0 5 V up to 1 6 V Alternatively these can be bypassed for manual settings The fixed 54 MHz clocking of the ADCs and datapath for all modes allows very precise accurate sampling and digital filtering The line locked clock output allows the output data rate timing signals and output clock signals to be synchronous asynchronous or line locked even with 5 line length variation The output control signals allow glueless interface connections in almost any application The ADV7183B modes are set up over a 2 wire serial bidirectional port PC compatible The ADV7183B is fabricated in a 3 3 V CMOS process Its monolithic CMOS construction ensures greater functionality with lower power dissipation The ADV7183B is packaged a small 80 lead LOFP Pb free package One Technology Way P O Box 9106 Norwood MA 02062 9106 U S A Tel 781 329 4700 www analog com Fax 781 326 8703 2004 Analog Devices Inc All rights reserved ADV7183B TABLE OF CONTENTS 3 Analog Front 3 Standard Definition Processor SDP 3 Functional Block Diagram
38. bit allows the user to freeze the digital clamp loop at any time It is intended for users who would like to do their own clamping Users should disable the current sources for analog clamping via the appropriate register bits wait until the digital clamp loop settles and then freeze it via the DCFE bit When DCFE to 0 default the digital clamp is operational When is 1 the digital clamp loop is frozen LUMA FILTER Data from the digital fine clamp block is processed by three sets of filters The data format at this point is CVBS for CVBS input or luma only for Y C and YPrPb input formats e Luma antialias filter YAA The ADV7183B receives video at a rate of 27 MHz In the case of 4x oversampled video the ADCs sample at 54 MHz and the first decimation is performed inside the DPP filters Therefore the data rate into the SDP core is always 27 MHz The ITU R BT 601 recommends a sampling frequency of 13 5 MHz The luma antialias filter decimates the oversampled video using a high quality linear phase low pass filter that preserves the luma signal while at the same time attenuating out of band components The luma antialias filter YAA has a fixed response e Luma shaping filters YSH The shaping filter block is a programmable low pass filter with a wide variety of responses It can be used to selectively reduce the luma video signal bandwidth needed prior to scaling for example For some video sources that conta
39. connection AIN11 AIN12 1 2 olo l i iol loi i oioi i olo O o 2jo 2 o oj3 o 3 o 3 o No connection SETADC sw man en 1 ADC_SW_MAN_EN Enable manual setting of the input signal muxing Disable Enable Rev 0 Page 84 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 2 1 0 Comments Notes OxDC Letterbox LB TH 4 0 Sets the threshold 0 1 1 0 0 Default threshold for the Control 1 value that determines if a line is detection of black lines black Reserved 110 1 Set as default OxDD Letterbox LB EL 3 0 Programs the end line 1 1 0 0 ends with Control2 of the activity window for LB the last line of active detection end of field video on a field 1100b 262 525 LB_SL 3 0 Program the start line 0 1 Letterbox detection of the activity window for LB aligned with the start of detection start of field active video 0100b 23 286 NTSC OxDE Reserved OxDF Reserved OxEO Reserved 001 0 11 10 1 0 0 OxE1 SD Offset SD_OFF_CB 7 0 Adjuststhe hue 1 0 0 0 Cb by selecting the offset for the Cb channel OxE2 SD Offset SD_OFF_C
40. is asserted 1 Start of line relative to HSB HSB begin NEWAVMODE Sets the EAV SAV 0 EAV SAV codes generated mode to suit ADI encoders 1 Manual VS Field position controlled by Registers 0x32 0x33 and OxE5 OxEA Reserved 0 0 0 Set to default 0x32 VSync Reserved NEWAVMODE bit Field ololo Set to default must be set high contol VSBHE 0 VS goes high in the middle of the line even field 1 VS changes state at the start of the line even field VSBHO 0 VS goes high in the middle of the line odd field 1 VS changes state at the start of the line odd field 0x33 VSync Reserved 0 0 0 Set to default Field VSEHE 0 VS goes low in the middle NEWAVMODE bit Control 3 of the line even field must be set high 1 VS changes state at the start of the line even field VSEHO 0 VS goes low in the middle of the line odd field 1 VS changes state at the start of the line odd field Rev 0 Page 78 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 2 1 0 Comments Notes 0x34 HS Position HSE 10 8 HS end allows the 0 O 0 HS output ends HSE 10 0 Using HSB and HSE Control 1 positioning of the HS output within pixels after the falling edge the user can program the video line of HSync the position and Reserved 0 Set to 0 length of the output HSB 10 8 H
41. letterbox detection window ends with the last active video line For an NTSC signal this window is from Line 262 to Line 525 Changing the bits to 1100 the detection window starts on Line 261 and ends on Line 254 Gemstar Data Recovery The Gemstar compatible data recovery block GSCD supports 1x and 2x data transmissions In addition it can serve asa closed caption decoder Gemstar compatible data transmissions can occur only in NTSC Closed caption data can be decoded in both PAL and NTSC The block is configured via in the following ways e GDECEL 15 0 allow data recovery on selected video lines on even fields to be enabled and disabled e GDECOL 15 0 enable the data recovery on selected lines for odd fields GDECAD configures the way in which data is embedded in the video data stream Rev 0 Page 50 of 96 The recovered data is not available through but is inserted into the horizontal blanking period of an ITU R BT656 com patible data stream The data format is intended to comply with the recommendation by the International Telecommunications Union ITU R BT 1364 For more information see the ITU website at www itu ch See Figure 35 The format of the data packet depends on the following criteria e Transmission is 1x or 2x e Data is output in 8 bit or 4 bit format see the description of the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 bit e Data is closed caption CCAP or Ge
42. no CCAP signals are detected and confidence in the decoded data is low When CCAPD is 1 the CCAP sequence detected and confidence in the decoded data is high EDTVD EDTV Sequence Detected Address 0x90 2 A Logic 1 for this bit indicates that the data in the EDT V1 2 3 registers is valid The EDTVD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted When EDTVD is 0 no EDTV sequence detected Confidence in decoded data is low When EDTVD is 1 an EDTV sequence detected Confidence in decoded data is high CGMSD CGMS A Sequence Detected Address 0x90 3 Logic 1 for this bit indicates that the data in the CGMSI 2 3 registers is valid The CGMSD bit goes high if a valid CRC checksum has been calculated from a received CGMS packet When CGMSD is 0 no CGMS transmission is detected and confidence in the decoded data is low When CGMSD is 1 the CGMS sequence is decoded and confidence in the decoded data is high ENABLE CRC Address 0 2 2 For certain video sources the CRC data bits may have an invalid format In such circumstances the CRC checksum validation procedure can be disabled The CGMSD bit goes high if the rising edge of the start bit is detected within a time window When CRC ENABLE is 0 no CRC check is performed The CGMSD bit goes high if the rising edge of the start bit is detected within a ti
43. only by horizontal lock 1 Lock status set by horizontal lock and subcarrier lock Ox8F Free Run Reserved 0 0 0 0 Set to default Line LLC_PAD_SEL 2 0 Enables manual LLC1 nominal 27 MHz Length 1 selection of clock for pin selected out on LLC1 pin 1 0 1 LLC2 nominally 13 5 MHz For 16 bit 4 2 2 out selected out on LLC1 pin OF_SEL 3 0 0010 Reserved 0 Set to default 0x90 VBI Info WSSD Screen signaling detected 0 o WSS detected Read only status bits Read Only 1 WSS detected CCAPD Closed caption data 0 CCAP signals detected 1 CCAP sequence detected EDTVD EDTV sequence 0 EDTV sequence detected 1 EDTV sequence detected CGMSD CGMS sequence 0 CGMS transition detected 1 CGMS sequence decoded Reserved x x x x 0x91 WSS1 WSS1 7 0 Read Only wide screen signaling data 0x92 WSS2 WSS2 7 0 X X x x x WSS2 7 6 are Read Only Wide screen signaling data undetermined 0x93 WSS2 WSS2 7 0 X X X x x Read Only Wide screen signaling data 0x94 EDTV2 EDTV2 7 0 X x x Read Only EDTV data register 0x95 EDTV3 EDTV3 7 0 x x x x x EDTV3 7 6 are EDTV3 5 is reserved Read Only EDTV data register undetermined for future use 0x96 CGMS1 CGMS1 7 0 X x x Read Only CGMS data register 0x97 CGMS2 CGMS2 7 0 x x x Read Only CGMS data register 0x98 CGMS3 CGMS3 7 0
44. programmed to steepen the chroma edges in an attempt to artificially restore lost color bandwidth The CTI block however operates only on edges above a certain threshold to ensure that noise is not emphasized Care has also been taken to ensure that edge ringing and undesirable saturation or hue distortion are avoided Chroma transient improvements are needed primarily for signals that experienced severe chroma bandwidth limitations For those types of signals it is strongly recommended to enable the CTI block via CTI_EN CTI_EN Chroma Transient Improvement Enable Address 0x4D 0 The CTI_EN bit enables the CTI function If set to 0 the CTI block is inactive and the chroma transients are left untouched Setting CTI_EN to 0 disables the CTI block Setting CTI_EN to 1 default enables the CTI block CTI_AB_EN Chroma Transient Improvement Alpha Blend Enable Address 0x4D 1 The CTI_AB_EN bit enables an alpha blend function within the CTI block If set to 1 the alpha blender mixes the transient improved chroma with the original signal The sharpness of the alpha blending can be configured via the CTI_AB 1 0 bits For the alpha blender to be active the CTI block must be enabled via the CTI_EN bit Setting CTI_AB_EN to 0 disables the CTI alpha blender Setting CTI_AB_EN to 1 default enables the CTI alpha blend mixing function 1 0 Chroma Transient Improvement Alpha Blend Address 0x4D 3 2 The CTI_AB
45. regulation filtering and decoupling It is highly desirable to provide separate regulated supplies for each of the analog circuitry groups AVDD DVDD DVDDIO and PVDD Some graphic controllers use substantially different levels of power when active during active picture time and when idle during horizontal and vertical sync periods This can result in a measurable change in the voltage supplied to the analog supply regulator which can in turn produce changes in the regulated analog supply voltage This can be mitigated by regulating the analog supply or at least PVDD from a different cleaner power source for example from a 12 V supply It is also recommended to use a single ground plane for the entire board This ground plane should have a space between the analog and digital sections of the PCB see Figure 42 ADV7183B ANALOG DIGITAL SECTION SECTION 04997 0 039 Figure 42 PCB Ground Layout Experience has repeatedly shown that the noise performance is the same or better with a single ground plane Using multiple ground planes can be detrimental because each separate ground plane is smaller and long ground loops can result In some cases using separate ground planes is unavoidable For those cases it is recommended to place a single ground plane under the ADV7183B The location of the split should be under the ADV7183B For this case it is even more important to place components wisely because the current loops
46. specifications are guaranteed over this range ELECTRICAL CHARACTERISTICS At Avpp 3 15 V to 3 45 V 1 65 V to 2 0 3 0 V to 3 6 V 1 65 V to 2 0 V operating temperature range unless otherwise noted Table 1 Parameter Symbol Test Conditions Min Typ Max Unit STATIC PERFORMANCE Resolution Each ADC N 10 Bits Integral Nonlinearity INL BSL at 54 MHz 0 475 40 6 3 LSB Differential Nonlinearity DNL BSL at 54 MHz 0 25 0 5 0 7 2 LSB DIGITAL INPUTS Input High Voltage Vin 2 Input Low Voltage Vit 0 8 Input Current lin Pins listed in Note 1 50 50 HA All other pins 10 10 HA Input Capacitance CiN 10 pF DIGITAL OUTPUTS Output High Voltage Isource 0 4 mA 2 4 Output Low Voltage VoL Isink 3 2 MA 0 4 High Impedance Leakage Current lLeak Pins listed in Note 2 50 All other pins 10 HA Output Capacitance Cour 20 pF POWER REQUIREMENTS Digital Core Power Supply Dvop 1 65 1 8 2 V Digital I O Power Supply 3 0 33 3 6 PLL Power Supply Pvop 1 65 1 8 2 0 V Analog Power Supply 3 15 33 3 45 Digital Core Supply Current 82 mA Digital I O Supply Current 2 mA PLL Supply Current 10 5 Analog Supply Current CVBS input 85 mA YPrPb input 180 mA Power Down Current PwRDN 1 5 mA Power Up Time tewrup 20 ms 1 Pins 36 and 79 Pins 1 2 5 6 8 12 17 18 24 32 35 74 76 80 3 Guarantee
47. strength 4x Rev 0 Page 16 of 96 ADV7183B Drive Strength Selection Clock DR_STR_C 1 0 Address OxF4 3 2 The DR_STR_C 1 0 bits can be used to select the strength of the clock signal output driver LLC pin For more information refer to the Drive Strength Selection Sync and the Drive Strength Selection Data sections Table 12 DR_STR_C Function DR_STR_C 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Drive Strength Selection Sync DR_STR_S 1 0 Address 0 4 1 0 The DR_STR_S 1 0 bits allow the user to select the strength of the synchronization signals with which HS VS and F are driven For more information refer to the Drive Strength Selection Clock and the Drive Strength Selection Data sections Table 13 DR_STR_S Function DR_STR_S 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive strength 4x Enable Subcarrier Frequency Lock Pin EN_SFL_PIN Address 0x04 1 The EN_SFL_PIN bit enables the output of subcarrier lock information also known as GenLock from the ADV7183B to an encoder in a decoder encoder back to back arrangement When EN_SFL_PIN is 0 default the subcarrier frequency lock output is disabled When EN_SFL_PIN is 1 the subcarrier frequency lock in
48. taken 1 Inread mode the highest Subaddress register contents continue to be output until the master device issues a no acknowledge This indicates the end of a read A no acknowledge condition is where the SDA line is not pulled low on the ninth pulse 2 Inwrite mode the data for the invalid byte is not loaded into any Subaddress register a no acknowledge is issued by the ADV7183B and the part returns to the idle condition 9 1 7 04997 0 036 DATA ACK STOP Figure 39 Bus Data Transfer WRITE SEQUENCE READ SEQUENCE S START P STOP A S ACKNOWLEDGE SLAVE A M ACKNOWLEDGE BY MASTER save sus apos A9 Stave anon x s SLAVE ADDR AS oara A S NO ACKNOWLEDGE SLAVE NO ACKNOWLEDGE BY MASTER 04997 0 037 Figure 40 Read and Write Sequence Rev 0 Page 60 of 96 REGISTER ACCESSES The MPU can write to or read from most of the ADV7183B s registers excepting the registers that are read only or write only The Subaddress register determines which register the next read or write operation accesses All communications with the part through the bus start with an access to the subaddress register Then a read write operation is performed from to the target address which then increments to the next address until a stop command on the bus is performed REGISTER PROGRAMMING
49. the automatic mode is disabled via setting the AUTO_PDC_EN bit to 0 the values programmed into LTA 1 0 and CTA 2 0 registers become active When AUTO_PDC_EN is 0 the ADV7183 uses the LTA 1 0 and CTA 2 0 values for delaying luma and chroma samples Refer to the LTA 1 0 Luma Timing Adjust Address 0x27 1 0 and the CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 sections When AUTO_PDC_EN is 1 default the ADV7183B auto matically determines the LTA and CTA values to have luma and chroma aligned at the output CTA 2 0 Chroma Timing Adjust Address 0x27 5 3 The Chroma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples This may be used to compensate for external filter group delay differences in the luma versus chroma path and to allow a different number of pipeline delays while processing the video downstream Review this functionality together with the LTA 1 0 register The chroma can only be delayed advanced in chroma pixel steps One chroma pixel step is equal to two luma pixels The programmable delay occurs after demodulation where one can no longer delay by luma pixel steps For manual programming use the following defaults CVBS input CTA 2 0 011 e YCinput CTA 2 0 101 YPrPb input CTA 2 0 110 Table 53 CTA Function CTA 2 0 Description 000 Not used 001 Chroma 2 chroma pixel early 010 Chroma 1 chroma pixel early
50. timing info or on the horizontal timing and lock status of the color subcarrier See the FSCLE Fsc Lock Enable Address 0x51 7 section AUTODETECTION RESULT AD RESULT 2 0 Address 0x10 6 4 The RESULT 2 0 bits report back on the findings from the autodetection block For more information on enabling the autodetection block see the General Setup section For information on configuring it see the Autodetection of SD Modes section Table 14 AD RESULT Function AD RESULT 2 0 Description 000 NTSM MJ 001 NTSC 443 010 PAL M 011 PAL 60 100 PAL BGHID 101 SECAM 110 PAL Combination N 111 SECAM 525 STATUS 1 7 0 Bit Name Description 0 IN LOCK In lock right now 1 LOST LOCK Lost lock since last read of this register 2 FSC LOCK Fsc locked right now 3 FOLLOW PW AGC follows peak white algorithm 4 AD RESULT O Result of autodetection 5 AD RESULT 1 Result of autodetection 6 AD RESULT 2 Result of autodetection 7 COL KILL Color kill active STATUS 2 STATUS 2 7 0 Address 0x12 7 0 Table 16 STATUS 2 Function STATUS 2 7 0 Bit Name Description 0 MVCS DET Detected Macrovision color striping 1 MVCS T3 Macrovision color striping protection Conforms to Type 3 if high and to Type 2 if low 2 MV PS DET Detected Macrovision pseudo Sync pulses 3 AGC DET Detected Macrovision AGC pulses 4 LL NSTD Line length is nonstandard 5 FSC NSTD Fsc frequency is nonst
51. to Dvuppio 0 3 V AGND 0 3 V to 0 3 150 C 65 C to 150 C 260 C ESD CAUTION ESD electrostatic discharge sensitive device Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection Although this product features proprietary ESD protection circuitry permanent damage may occur on devices subjected to high energy electrostatic discharges Therefore proper ESD precautions are recommended to avoid performance degradation or loss of functionality ADV7183B Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device This is a stress rating only functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied Exposure to absolute maximum rating conditions for extended periods may affect device reliability Ewa ESD SENSITIVE DEVICE Rev 0 Page 9 of 96 ADV7183B PIN CONFIGURATION AND F Table 7 Pin Function Descriptions 5 FIELD OE NC NO CONNECT UNCTION DESCRIPTIONS x a az or eoXt2 te FS Food 480 fh o 2 z z k kR R G 0 Z Z 00 0 lt Z lt Z lt lt 69 68 66 65 63 62 61 ADV7183B TOP VIEW Not to Scale 26 27 28 29 30 31 32 33 35 36 37 40 05548842983 84888 336 kS r gt 2 x
52. will be much longer current takes the path of least resistance An example of a current loop power plane to ADV7183B to digital output trace to digital data receiver to digital ground plane to analog ground plane PLL Place the PLL loop filter components as close as possible to the ELPF pin Do not place any digital or other high frequency traces near these components Use the values suggested in the data sheet with tolerances of 10 or less DIGITAL OUTPUTS BOTH DATA AND CLOCKS Try to minimize the trace length that the digital outputs have to drive Longer traces have higher capacitance which requires more current which causes more internal digital noise Shorter traces reduce the possibility of reflections Adding a 30 to 50 series resistor can suppress reflections reduce EMI and reduce the current spikes inside the ADV7183B If series resistors are used place them as close as possible to the ADV7183B pins However try not to add vias or extra length to the output trace to make the resistors closer If possible limit the capacitance that each of the digital outputs drive to less than 15 pF This can easily be accomplished by keeping traces short and by connecting the outputs to only one device Loading the outputs with excessive capacitance increases the current transients inside the ADV7183B creating more digital noise on its power supplies Rev 0 Page 90 of 96 DIGITAL INPUTS The digital inputs on the ADV
53. 0 See above select the lines of video Default Do not Control 2 even field Lines 10 25 check for Gemstar that the decoder checks compatible data on for Gemstar compatible any lines 10 25 in data even fields Ox4A Gemstar GDECOL 15 8 See the Comments GDECOL 15 0 16 LSB Line 10 Control 3 column individual enable bits that MSB Line 25 select the lines of video Default Do not 0x4B Gemstar GDECOL 7 0 See above olo 0 odd field Lines 10 25 check for Gemstar that the decoder checks compatible data on Control 4 f ibl Gemstar compatible any lines 10 25 in data odd fields 0x4C Gemstar GDECAD Controls the manner in Split data into half byte To avoid 00 FF code Control 5 which decoded Gemstar data is inserted into the horizontal blanking period Output straight 8 bit format Reserved x x Undefined Ox4D CTI DNR CTI EN CTI enable Disable CTI Control 1 Enable CTI CTI AB EN Enables the mixing of Disable CTI alpha blender the transient improved chroma with Enable CTI alpha blender the original signal AB 1 0 Controls the behavior Sharpest mixing of the alpha blend circuitry 011 Sharp mixing 110 Smooth 1 1 Smoothest Reserved 0 Set to default DNR_EN Enable or bypass the DNR 0 Bypass the DNR block block 1 Enable the DNR block Reserved 1 Set to default Ox4E DNR CTI_CTH 7 0 Specifies how big the 0 0 0 0 1 0 Set to 0x04 for A V i
54. 0 Do not use 01 PAL chroma comb adapts 5 lines 3 taps to 3 lines 2 taps cancels cross luma only 10 PAL chroma comb adapts 5 lines 5 taps to 3 lines 3 taps cancels cross luma and hue error less well 11 default PAL chroma comb adapts 5 lines 5 taps to 4 lines 4 taps cancels cross luma and hue error well CCMP 2 0 Chroma Comb Mode PAL Address 0x39 5 3 Table 49 CCMP Function CCMP 2 0 Description Configuration Oxx default Adaptive comb mode 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory 110 Fixed chroma comb all lines of line memory 111 Fixed chroma comb bottom lines of line memory Adaptive 3 line chroma comb for CTAPSP 01 Adaptive 4 line chroma comb for CTAPSP 10 Adaptive 5 line chroma comb for CTAPSP 11 Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 Fixed 3 line chroma comb for CTAPSP 01 Fixed 4 line chroma comb for CTAPSP 10 Fixed 5 line chroma comb for CTAPSP 11 Fixed 2 line chroma comb for CTAPSP 01 Fixed 3 line chroma comb for CTAPSP 10 Fixed 4 line chroma comb for CTAPSP 11 YCMP 2 0 Luma Comb Mode PAL Address 0x39 2 0 Table 50 YCMP Function YCMP 2 0 Description Configuration Oxx default Adaptive comb mode Adaptive 5 lines 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filt
55. 01 in Table 31 Table 31 CSFM Function CSFM 2 0 Description 000 default Autoselect 1 5 MHz bandwidth 001 Autoselect 2 17 MHz bandwidth 010 SH1 011 SH2 100 SH3 101 SH4 110 SH5 111 Wideband Mode v740a COMBINED C ANTIALIAS C SHAPING FILTER C RESAMPLER B ATTENUATION dB FREGUERCY 04997 0 016 Figure 16 Chroma Shaping Filter Responses Figure 16 shows the responses of SH1 narrowest to SH5 widest in addition to the wideband mode in red GAIN OPERATION The gain control within the ADV7183B is done on a purely digital basis The input ADCs support a 10 bit range mapped into a 1 6 V analog voltage range Gain correction takes place after the digitization in the form of a digital multiplier Advantages of this architecture over the commonly used PGA programmable gain amplifier before the ADCs include the fact that the gain is now completely independent of supply temperature and process variations As shown in Figure 17 the ADV7183B can decode a video signal as long as it fits into the ADC window Two components to this are the amplitude of the input signal and the dc level it resides on The level is set by the clamping circuitry see the Clamp Operation section If the amplitude of the analog video signal is too high clipping may occur resulting in visual artifacts The analog input range of the ADC together with the clamp
56. 1 Fixed 3 line chroma comb for CTAPSN 01 Fixed 4 line chroma comb for CTAPSN 10 Fixed 5 line chroma comb for CTAPSN 11 Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 11 2 0 Luma Comb Mode NTSC Address 0x38 2 0 Table 46 YCMN Function YCMN 2 0 Description Oxx default Adaptive comb mode Adaptive 3 line 3 taps luma comb 100 Disable luma comb Use low pass notch filter see the Y Shaping Filter section 101 Fixed luma comb top lines of line memory Fixed 2 line 2 taps luma comb 110 Fixed luma comb all lines of line memory Fixed 3 line 3 taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 2 line 2 taps luma comb Rev 0 Page 35 of 96 ADV7183B PAL Comb Filter Settings Table 47 PSFSEL Function Used for PAL B G H I D PAL M PAL Combinational N PSFSEL 1 0 Description PAL 60 and NTSC443 CVBS inputs 00 Narrow 01 default Medium PSFSEL 1 0 Split Filter Selection PAL 10 Wide Address 0x19 1 0 11 Widest The NSFSEL 1 0 control selects how much of the overall signal bandwidth is fed to the combs A wide split filter selection eliminates dot crawl but shows imperfections on diagonal lines The opposite is true for selecting a narrow bandwidth split filter CTAPSP 1 0 Chroma Comb Taps PAL Address 0x39 7 6 Table 48 CTAPSP Function CTAPSP 1 0 Description 0
57. 1 0 controls the behavior of alpha blend circuitry that mixes the sharpened chroma signal with the original one It thereby controls the visual impact of CTI on the output data For CTI_AB 1 0 to become active the CTI block must be enabled via the CTI_EN bit and the alpha blender must be switched on via CTI_AB_EN Sharp blending maximizes the effect of CTI on the picture but may also increase the visual impact of small amplitude high frequency chroma noise Table 42 CTI_AB Function CTI_AB 1 0 Description 00 Sharpest mixing between sharpened and original chroma signal 01 Sharp mixing 10 Smooth mixing 11 default Smoothest alpha blend function CTI_C_TH 7 0 CTI Chroma Threshold Address 0x4E 7 0 The CTI C TH 7 0 value is an unsigned 8 bit number speci fying how big the amplitude step in a chroma transition has to be in order to be steepened by the CTI block Programming a small value into this register causes even smaller edges to be steepened by the CTI block Making CTI C TH 7 0 a large value causes the block to improve large transitions only The default value for TH 7 0 is 0x08 indicating the threshold for the chroma edges prior to CTI DIGITAL NOISE REDUCTION DNR Digital noise reduction is based on the assumption that high frequency signals with low amplitude are probably noise and that their removal therefore improves picture quality DNR EN Digital Noise Reduction Enable A
58. 1 1 Clears SD_LOCK_Q bit SD_UNLOCK_CLR 0 Do not clear Write Only 1 Clears SD UNLOCK Q bit Reserved Not used Register Reserved 0 Not used Access Page 2 Reserved 0 Not used SD_FR_CHNG_CLR 0 Do not clear 1 Clears SD_FR_CHNG_Q bit MV_PS_CS_CLR 0 Do not clear 1 Clears MV_PS_CS_Q bit Reserved x Not used Rev 0 Page 67 of 96 ADV7183B Bit Subaddress Register Bit Description 3 Comments Notes 0x44 Interrupt SD_LOCK_MSKB Masks SD_LOCK_Q bit Mask 1 Do not mask SD_UNLOCK_MSKB Masks SD_UNLOCK_Q bit Read Write Do not mask Register Reserved Not used Reserved 0 Not used Register Access Reserved Not used Page2 SD FR CHNG MSKB Masks SD FR CHNG Obit Do not mask MV PS CS MSKB Masks MV PS CS bit Do not mask Reserved Not used 0x45 Reserved x 0x46 Interrupt CCAPD_Q Closed captioning not detected These bits Status 2 in the input video signal can be Closed captioning data detected cleared or Read Only in the video input signal masked by Register GEMD_Q Gemstar data not detected in 5 the input video signal ortan 0x48 Register Gemstar data detected in the respectively Access input video signal Page 2 CGMS_CHNGD_Q No change detected in CGMS data in the input video signal A change is detected in the CGMS data in the input video signal WSS_CHNGD_Q 0 No change detected WSS data
59. 16 OOTO SVHS 9 722 01011 SVHS 10 10011 SVHS 18 CCIR 601 HMM SUE 1 10100 01101 SVHS 12 19101 PACAN 0 1110 SVHS 13 Torg PALNA 01111 SVHS 14 10000 SVHS 15 11099 PANE 10001 SVHS 16 71001 NTSC NN 1 SVHS 17 NEE NN 10011 default SVHS 18 CCIR 601 10100 11111 Do not use 111100 NTSC WN 1 111101 NTSC WN 2 1 1110 NTSC WN 3 111111 Reserved Rev 0 Page 28 of 96 ADV7183B v740a COMBINED Y ANTIALIAS S VHS LOW PASS FILTERS Y RESAMPLE AMPLITUDE dB 04997 0 012 FREQUENCY ME Figure 12 Y S VHS Combined Responses The filter plots in Figure 12 show the S VHS 1 narrowest to S VHS 18 widest shaping filter settings Figure 14 shows the PAL notch filter responses The NTSC compatible notches are shown in Figure 15 v740a COMBINED Y ANTIALIAS CCIR MODE SHAPING FILTER Y RESAMPLE AMPLITUDE dB 04997 0 013 FREQUENCY Figure 13 S VHS 18 Extra Wideband Filter 601 Compliant v740a COMBINED Y ANTIALIAS PAL NOTCH FILTERS Y RESAMPLE AMPLITUDE dB 04997 0 014 FREQUENCY MHz Figure 14 S VHS 18 Extra Wideband Filter 601 Compliant v740a COMBINED Y A ESAME NTSC NOTCH FILTERS AMPLE AMPLITUDE dB 04997 0 015 10 12 EBEQUENGY ui Figure 15 Y
60. 7183B are designed to work with 3 3 V signals and are not tolerant of 5 V signals Extra compo nents are needed if 5 V logic signals are required to be applied to the decoder ANTIALIASING FILTERS For inputs from some video sources that are not bandwidth limited signals outside the video band can alias back into the video band during A D conversion and appear as noise on the output video The ADV7183B oversamples the analog inputs by a factor of 4 This 54 MHz sampling frequency reduces the requirement for an input filter for optimal performance it is recommended that an antialiasing filter be employed The recommended low cost circuit for implementing this buffer and filter circuit for all analog input signals is shown in Figure 44 The buffer is a simple emitter follower using a single npn transistor The antialiasing filter is implemented using passive components The passive filter is a third order Butterworth filter with a 3 dB point of 9 MHz The frequency response of the passive filter is shown in Figure 43 The flat pass band up to 6 MHz is essential The attenuation of the signal at the output of the filter due to the voltage divider of R24 and R63 is compen sated for in the ADV7183B part by using the automatic gain ADV7183B control The ac coupling capacitor at the input to the buffer creates a high pass filter with the biasing resistors for the transistor This filter has a cut off of 2 x x R39 R89 x C93 0 62
61. AD RESULT O FOLLOW PW FSC LOCK LOST LOCK IN LOCK Ident IDENT 7 IDENT 6 IDENT 5 IDENT 4 IDENT 3 IDENT 2 IDENT 1 IDENT O Status 2 FSC NSTD LL NSTD MV AGC DET MV PS DET MVCS T3 MVCS DET Status 3 PAL SW LOCK INTERLACE STD FLD LEN FREE RUN ACT SD OP 50HZ GEMD INST HLOCK Analog Clamp Control CCLEN Digital Clamp Control 1 DCT 1 DCT O Reserved Shaping Filter Control CSFM 2 CSFM 1 5 0 YSFM 4 YSFM 3 YSFM 2 YSFM 1 5 0 Shaping Filter Control 2 WYSFMOVR WYSFM 4 WYSFM 3 WYSFM 2 WYSFM 1 WYSFM O Comb Filter Control NSFSEL 1 NSFSEL O PSFSEL 1 PSFSEL O Reserved ADI Control 2 TRI_LLC EN28XTAL VS_JIT_ COMP_EN Reserved Pixel Delay Control SWPC AUTO_PDC_EN CTA 2 CTA 1 CTA O LTA 1 LTA O Reserved Misc Gain Control CKE PW UPD AGC Mode Control LAGC 2 LAGC 1 LAGC O CAGC 1 0 Chroma Gain Control 1 CAGT 1 0 CMG 11 CMG 10 CMG 9 CMG 8 Chroma Gain Control 2 CMG 7 CMG 6 CMG 5 CMG 4 CMG 3 CMG 2 CMG 1 CMG 0 Luma Gain Control 1 LAGT 1 LGAT O LMG 11 LMG 10 LMG 9 LMG 8 Luma Gain Control 2 LMG 7 LMG 6 LMG 5 LMG 4 LMG 3 LMG 2 LMG 1 LMG O VSync Field Control 1 NEWAVMODE HVSTIM VSync Field Control 2 VSBHO VSBHE VSync Field Control 3 VSEHO VSEHE HSync Position Control 1 HSB 10 HSB 9 HSB 8 HSE 10 HSE 9 HSE 8 HSync Position Control 2 HSB 7 HSB 6 HSB 5 HSB 4 HSB 3 HSB 2 HSB 1 5 0 HSync Position Control 3 HSE 7 HSE 6 HSE 5 HSE 4 HSE 3 HSE 2 HSE 1 5 0 Polarity PHS PVS PF PCLK NTSC Comb Control CTAPSN 1 CTAPSN O CCMN 2 CCMN 1 CCMN O YCMN 2 YCMN 1 YCMN O PAL
62. ANALOG DEVICES Multiformat SDTV Video Decoder ADV7183B FEATURES Multiformat video decoder supports NTSC J M 4 43 PAL B D G H I M N SECAM Integrates three 54 MHz 10 bit ADCs Clocked from a single 27 MHz crystal Line locked clock compatible LLC Adaptive Digital Line Length Tracking ADLLT signal processing and enhanced FIFO management give mini TBC functionality 5 line adaptive comb filters Proprietary architecture for locking to weak noisy and unstable video sources such as VCRs and tuners Subcarrier frequency lock and status information output Integrated AGC with adaptive peak white mode Macrovision copy protection detection CTI chroma transient improvement DNR digital noise reduction Multiple programmable analog input formats CVBS composite video S Video Y C YPrPb component VESA MII SMPTE and BetaCam 12 analog video input channels Automatic NTSC PAL SECAM identification Digital output formats 8 bit or16 bit ITU R 656 YCrCb 4 2 2 output HS VS and FIELD GENERAL DESCRIPTION The ADV7183B integrated video decoder automatically detects and converts a standard analog baseband television signal compatible with worldwide standards NTSC PAL and SECAM into 4 2 2 component video data compatible with 16 8 bit CCIR601 CCIR656 The advanced and highly flexible digital output interface enables performance video decoding and conversion in line locked clock based systems This makes the device i
63. BKSTZ 25 C to 70 C Low Profile Quad Flat Package LOFP ST 80 2 ADV7183BBSTZ 40 C to 85 C Low Profile Quad Flat Package LOFP ST 80 2 EVAL ADV7183BEBM Evaluation Board 17 Pb free part The ADV7183B is a Pb free environmentally friendly product It is manufactured using the most up to date materials and processes The coating on the leads of each device is 10096 pure Sn electroplate The device is suitable for Pb free applications and can withstand surface mount soldering at up to 255 C 5 In addition it is backward compatible with conventional SnPb soldering processes This means the electroplated Sn coating can be soldered with Sn Pb solder pastes at conventional reflow temperatures of 220 C to 235 C Rev 0 Page 94 of 96 ADV7183B NOTES Rev 0 Page 95 of 96 ADV7183B NOTES Purchase of licensed PC components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips Patent Rights to use these components in system provided that the system conforms to the lC Standard Specification as defined by Philips 2004 Analog Devices Inc All rights reserved Trademarks and ANALOG registered trademarks are the property of their respective owners Lal DEVICES Rev 0 Page 96 of 96 www analog com
64. Begin Address 0x34 6 4 Address 0x35 7 0 1696 LLC1s to both HSB and HSE for NTSC that is HSB 10 0 11010100010 HSE 10 0 11010100000 1696 is derived from the NTSC total number of pixels 1716 The position of this edge is controlled by placing a binary number into HSB 10 0 The number applied offsets the edge with respect to an internal counter that is reset to 0 immediately after EAV code FE00 00 XY see Figure 20 HSB is set to To move 20 LLC1s away from active video is equal to 00000000010b which is 2 LLC1 clock cycles from count 0 subtracting 20 from 1716 and adding the result in binary to The default value of HSB 10 0 is 0x002 indicating that the HS both HSB 10 0 and HSE 10 0 pulse starts 2 pixels after the falling edge of HS PHS Polarity HS Address 0x37 7 The polarity of the HS pin can be inverted using the PHS bit When PHS is 0 default HS is active high When PHS is 1 HS is active low Table 54 HS Timing Parameters see Figure 20 Characteristic HS to Active Video Active Video Total LLC1 HS Begin Adjust HS End Adjust LLC1 Clock Cycles Samples Line Clock Cycles Standard HSB 10 0 default HSE 10 0 default Cin Figure 20 default D in Figure 20 E in Figure 20 NTSC 00000000010b 00000000000b 272 720Y 720C 1440 1716 NTSC Square 00000000010b 00000000000b 276 640Y 640C 1280 1560 Pixel PAL 00000000010b 00000000000b 284 720Y 720C 1440 1728
65. Comb Control CTAPSP 1 CTAPSP O CCMP 2 CCMP 1 0 2 YCMP 1 0 ADC Control PWRDN_AD C_0 PWRDN_AD C_1 PWRDN_ADC_2 Reserved Rev 0 Page 64 of 96 ADV7183B Register Name Bit 7 Bit 6 Bit5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Manual Window Control CKILLTHR 2 CKILLTHR 1 CKILLTHR O Reserved Resample Control SFL_INV Reserved Gemstar Ctrl 1 GDECEL 15 GDECEL 14 GDECEL 13 GDECEL 12 GDECEL 11 GDECEL 10 GDECEL 9 GDECEL 8 Gemstar Ctrl 2 GDECEL 7 GDECEL 6 GDECEL 5 GDECEL 4 GDECEL 3 GDECEL 2 GDECEL 1 GDECEL O Gemstar Ctrl 3 GDECOL 15 GDECOL 14 GDECOL 13 GDECOL 12 GDECOL 11 GDECOL 10 GDECOL 9 GDECOL 8 Gemstar Ctrl 4 GDECOL 7 GDECOL 6 GDECOL 5 GDECOL 4 GDECOL 3 GDECOL 2 GDECOL 1 GDECOL O Gemstar Ctrl 5 GDECAD CTI DNR Ctrl 1 DNR_EN CTI_AB 1 CTI_AB O CTI_AB_EN CTI DNR Ctrl 2 CTI_C_TH 7 CTI_C_TH 6 5 CTI_C_TH 4 CTI C TH 3 CTI C TH2 CTI C TH 1 CTI C TH O Reserved CTI DNR Ctrl 4 DNR TH 7 DNR TH 6 DNR TH 5 4 DNR_TH 3 DNR_TH 2 DNR_TH 1 DNR_TH O Lock Count FSCLE SRLS COL 2 COL 1 COL O CIL 2 CIL 1 CIL O Reserved Free run Line Length 1 LLC PAD SEL 2 LLC PAD SEL 1 PAD SEL O Reserved VBI Info CGMSD EDTVD CCAPD WSSD WSS 1 WSS1 7 WSS1 6 WSS1 5 WSS1 4 WSS1 3 WSS1 2 WSS1 1 WSS1 0 WSS 2 WSS2 7 WSS2 6 W
66. Digital clamp timing 010 Slow 1 s Control 1 determines the time constant of the 1 Medium 0 5 5 digital fine clamp circuitry Fast TC 0 13 1 1 TC dependent on video Reserved 0 Set to default 0x17 Shaping YSFM 4 0 Selects Y Shaping Filter 010 0 0 0 Auto wide notch for poor Decoder selects Filter mode when in CVBS only mode quality sources or wide optimum Y shaping Control band filter with Comb for filter depending on Allows the user to select a wide good quality input CVBS quality range of low pass and notch filters 0 0 0 0 1 Auto narrow notch for poor quality sources or If either auto mode is selected the decoder selects the optimum filter depending on the CVBS video 0 0 14 0 SVHS1 If one of these modes source quality good vs bad 0 1 1 SVHS2 is selected the olo 5 53 decoder does olo change filter modes Depending on video 5 55 quality a fixed filter ojo 1 1 1 SVHS6 response the one 0 1 0 0 0 SVHS7 selected is used for ol1lolol1 svHs8 good and bad quality 5 59 video 0 1 O 1 1 SVHS10 0 1 1 0 0 SVHS11 0 1 110 1 SVHS 12 0 1 1 1 0 SVHS 13 0 1 1 14 1 SVHS 14 110 00 0 0 SVHS15 110 100 0 1 SVHS 16 110 0 1 0 SVHS17 110 1 1 SVHS 18 CCIR601 110 110 0 PALNN1 110 110 1 PALNN2 110 1 1 0 PALNN3 110
67. ENDDELE is set to 0 default there is no delay Setting NVENDDELE to 1 delays VSync from going low on an even field by a line relative to NVEND NVENDSIGN NTSC VSync End Sign Address OxE6 5 Setting NVENDSIGN to 0 default delays the end of VSync default Set for user manual programming Setting NVENDSIGN to 1 advances the end of VSync Not recommended for user programming NVEND NTSC 4 0 VSync End Address OxE6 4 0 The default value of NVEND is 00100 indicating the NTSC VSync end position For all NTSC PAL VSync timing controls both the V bit in the AV code and the VSync on the VS pin are modified NFTOGDELO NTSC Field Toggle Delay on Odd Field Address OxE7 7 When NFTOGDELO is 0 default there is no delay Setting NFTOGDELO to 1 delays the field toggle transition on an odd field by a line relative to NFTOG NFTOGDELE NTSC Field Toggle Delay on Even Field Address OxE7 6 When NFTOGDELE is 0 there is no delay Setting NFTOGDELE to 1 default delays the field toggle transition on an even field by a line relative to NFTOG eS ADVANCE TOGGLE OF FIELD BY NFTOG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 1 0 0 1 ADDITIONAL DELAY BY 1LINE FIELD TOGGLE Figure 25 NTSC FIELD Toggle DELAY TOGGLE OF FIELD BY NFTOG 4 0 ADDITIONAL DELAY BY 1LINE 04997 0 025 NFTOGSIGN NTSC Field Toggle Sign Address OxE7 5 Setting NFTOGSIGN to 0 delays the field tran
68. FL REFOUT CML CAPY1 CAPY2 CAPC1 CAPC2 Type Function System Reset Input Active Low A minimum low reset pulse width of 5 ms is required to reset the ADV7183B circuitry This is a line locked output clock for the pixel data output by the ADV7183B Nominally 27 MHz but varies up or down according to video line length This is a divide by 2 version of the LLC1 output clock for the pixel data output by the ADV7183B Nominally 13 5 MHz but varies up or down according to video line length This is the input pin for the 27 MHz crystal or can be overdriven by an external 3 3 V 27 MHz clock oscillator source In crystal mode the crystal must be a fundamental crystal This pin should be connected to the 27 MHz crystal or left as a no connect if an external 3 3 V 27 MHz clock oscillator source is used to clock the ADV7183B In crystal mode the crystal must be a fundamental crystal A logic low on this pin places the ADV7183B in a power down mode Refer to the Register Maps section for more options power down modes for the ADV7183B When set to a logic low OE enables the pixel output bus 15 of the ADV7183B A logic high on the OE pin places Pins 15 HS VS SFL SYNC_OUT into a high impedance state The recommended external loop filter must be connected to this ELPF pin as shown in Figure 45 Subcarrier Frequency Lock This pin contains a serial output stream that can be used to lock the subcarrier frequen
69. Filter Settings Used for NTSC M J CVBS inputs NSFSEL 1 0 Split Filter Selection NTSC Address 0x19 3 2 The NSFSEL 1 0 control selects how much of the overall signal bandwidth is fed to the combs A narrow split filter selection gives better performance on diagonal lines but leaves more dot crawl in the final output image The opposite is true for selecting a wide bandwidth split filter CCMN 2 0 Chroma Comb Mode NTSC Address 0x38 5 3 Table 45 CCMN Function CCMN 2 0 Description ADV7183B Table 43 NSFSEL Function NSFSEL 1 0 Description 00 default Narrow 01 Medium 10 Medium 11 Wide CTAPSN 1 0 Chroma Comb Taps NTSC Address 0x38 7 6 Table 44 CTAPSN Function CTAPSN 1 0 Description 00 Do not use 01 NTSC chroma comb adapts 3 lines 3 taps to 2 lines 2 taps 10 default NTSC chroma comb adapts 5 lines 5 taps to 3 lines 3 taps 11 NTSC chroma comb adapts 5 lines 5 taps to 4 lines 4 taps Oxx default Adaptive comb mode 100 Disable chroma comb 101 Fixed chroma comb top lines of line memory 110 Fixed chroma comb all lines of line memory 111 Fixed chroma comb bottom lines of line memory Adaptive 3 line chroma comb for CTAPSN 01 Adaptive 4 line chroma comb for CTAPSN 10 Adaptive 5 line chroma comb for CTAPSN 11 Fixed 2 line chroma comb for CTAPSN 01 Fixed 3 line chroma comb for CTAPSN 10 Fixed 4 line chroma comb for CTAPSN 1
70. G_CLR Do not clear Clear 3 Clears SD_OP_CHNG_Q bit SD_V_LOCK_CHNG_CLR Do not clear Write Only Clears SD_V_LOCK_CHNG_Qbit register SD_H_LOCK_CHNG_CLR Do not clear Clears SD_H_LOCK_CHNG_Q bit Register Access SD_AD_CHNG_CLR 0 Do not clear Page 2 1 Clears SD_AD_CHNG_Q bit SCM_LOCK_CHNG_CLR 0 Do not clear 1 Clears SCM_LOCK_CHNG_Q bit PAL_SW_LK_CHNG_CLR 0 Do not clear 1 Clears PAL_SW_LK_CHNG_Q bit Reserved x Not used Reserved Not used 0x4C Interrupt SD_OP_CHNG_MSKB Do not mask Mask 2 Masks SD_OP_CHNG_Q bit SD V LOCK CHNG MSKB Do not mask Masks SD_V_LOCK_CHNG_Q bit Register SD H LOCK CHNG MSKB Do not mask Masks SD LOCK CHNG bit Register SD AD CHNG MSKB 0 Do not mask Access 1 Masks 50 CHNG Page2 5 LOCK CHNG 5 0 Do not mask 1 Masks SCM_LOCK_CHNG_Q bit PAL SW LK CHNG MSKB 0 Do not mask 1 Masks PAL SW LK CHNG Reserved x Not used Reserved Not used Rev 0 Page 70 of 96 The following registers are located in the Common Map and Register Access Page 1 Table 85 Interrupt Register Map Details ADV7183B Subaddress Register Bit Description Bits Comments Notes 0x00 Input Control INSEL 3 0 The INSEL bits allow the user to select an input channel as well as the input format CVBS 1 CVBS AIN2 CVBS AIN3 CVBS AIN4 CVBS on AI
71. HIFTED IF NEWAVMODE 1 04997 0 021 Figure 21 NTSC Default BT 656 The polarity of H V and F is embedded in the data FIELD 1 py de Pod win du dosis pos d a i OUTPUT 4 VIDEO us Er cup c OUTPUT I I OUTPUT FIELD NVBEG 4 0 0 0 NVENDI4 0 0x3 OUTPUT NFTOG 4 0 0x5 FIELD 2 OUTPUT VIDEO FF I T T I I I L I T T OUTPUT vs I po OUTPUT 4 0 0x0 NVENDI4 0 0x3 FIELD gt OUTPUT 4 0 0x5 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 T n 04997 0 022 Figure 22 NTSC Typical VSync Field Positions Using Register Writes Table 55 Rev 0 Page 41 of 96 ADV7183B Table 55 Recommended User Settings for NTSC See Figure 22 Register Register Name Write 0x31 VSync Field Control 1 0x12 0x32 VSync Field Control 2 0x81 0x33 VSync Field Control 3 0x84 0x37 Polarity 0x29 OxE5 NTSV_V_Bit_Beg 0x0 OxE6 NTSC_V_Bit_End 0x3 OxE7 NTSC_F_Bit_Tog 0x85 NVBEGDELO NTSC VSync Begin Delay on Odd Field Address 0xE5 7 A aN IGE BE IN OF NH AY BE oF When NVBEGDELO is 0 default there is no delay Setting NVBEGDELO to 1 delay VSync going high on an odd CORMIER field by a line relative to NVBEG PROGRAMMING ODD F
72. IELD YES NO 0 0 1 E 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE 04997 0 023 Figure 23 NTSC VSync Begin NVBEGDELE NTSC VSync Begin Delay on Even Field Address 0xE5 6 When NVBEGDELE is 0 default there is no delay Setting NVBEGDELE to 1 delays VSync going high on an even field by a line relative to NVBEG NVBEGSIGN NTSC VSync Begin Sign Address 0xE5 5 Setting NVBEGSIGN to 0 delays the start of VSync Set for user manual programming Setting NVBEGSIGN to 1 default advances the start of VSync Not recommended for user programming NVBEG 4 0 NTSC VSync Begin Address OxE5 4 0 The default value of NVBEG is 00101 indicating the NTSC VSync begin position For all NTSC PAL VSync timing controls both the V bit in the AV code and the VSync the VS pin are modified Rev 0 Page 42 of 96 ADV7183B ADVANCE END OF VSYNC BY NVEND 4 0 DELAY END OF VSYNC BY NVEND A 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 0 0 1 ADVANCE ADVANCE 0 5 LINE 0 5 LINE 04997 0 024 VSYNC END Figure 24 NTSC VSync End NVENDDELO NTSC VSync End Delay on Odd Field Address 0 6 7 When NVENDDELO is 0 default there is no delay Setting NVENDDELO to 1 delays VSync from going low on an odd field by a line relative to NVEND NVENDDELE NTSC VSync End Delay on Even Field Address OxE6 6 When NV
73. N5 CVBS AIN6 Composite 210 Y on AIN1 Con AIN4 on AIN2 5 on AIN3 AIN6 5 i o jojoj oj o ojo oj w S O S o Y on AIN1 Pr on AIN4 Pb on AIN5 Y on AIN2 Pr on AIN3 Pb on AIN6 YPbPr CVBSin on AIN7 CVBS in AIN8 CVBS on AIN9 CVBSin on AIN10 y CVBS AIN11 Composite VID_SEL 3 0 The VID_SEL bits allow the user to select the input video standard Auto detect PAL BGHID NTSC without pedestal SECAM Auto detect PAL BGHID NTSC M with pedestal SECAM Auto detect PAL N NTSC M without pedestal SECAM Auto detect PAL N NTSC M with pedestal SECAM 5 5 PAL 60 NTSC 4 43 o PAL BGHID PAL N BGHID without pedestal PAL without pedestal PALM PAL combination N PAL combination SECAM with pedestal 2 2 2 olo SECAM with pedestal Rev 0 Page 71 of 96 ADV7183B
74. NTSC and Figure 26 for PAL For recommended manual user settings see Table 55 and Figure 22 for NTSC see Table 56 and Figure 27 for PAL HVSTIM Horizontal VS Timing Address 0x31 3 The HVSTIM bit allows the user to select where the VS signal is being asserted within a line of video Some interface circuitry may require VS to go low while HS is low When HVSTIM is 0 default the start of the line is relative to HSE When HVSTIM is 1 the start of the line is relative to HSB VSBHO VS Begin Horizontal Position Odd Address 0x32 7 The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSBHO is 0 default the VS pin goes high at the middle of a line of video odd field When VSBHO is 1 the VS pin changes state at the start of a line odd field VSBHE VS Begin Horizontal Position Even Address 0x32 6 The VSBHO and VSBHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state when only HS is high low When VSBHE is 0 default the VS pin goes high at the middle of a line of video even field When VSBHE is 1 the VS pin changes state at the start of a line even field VSEHO VS End Horizontal Position Odd Address 0x33 7 The VSEHO and VSEHE bits selec
75. OL Three State Output Drivers TOD Address 0x03 6 This bit allows the user to three state the output drivers of the ADV7183B Upon setting the TOD bit the 15 0 HS VS FIELD and SFL pins are three stated The timing pins HS VS FIELD can be forced active via the OE bit For more information on three state control refer to the Three State LLC Driver and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR XX bits The ADV7183B supports three stating via a dedicated pin When set high the OE pin three states the output drivers for P15 PO HS VS FIELD and SFL The output drivers are three stated if the TOD bit or the OE pin is set high When TOD is 0 default the output drivers are enabled When TOD is 1 the output drivers are three stated Three State LLC Driver TRI LLC Address 0x1D 7 This bit allows the output drivers for the LLC1 and LLC2 pins of the ADV7183B to be three stated For more information on three state control refer to the Three State Output Drivers and the Timing Signals Output Enable sections Individual drive strength controls are provided via the DR STR XX bits When TRI LLC is 0 default the LLC pin drivers work according to the DR STR 1 0 setting pin enabled When TRI LLC is 1 the LLC pin drivers are three stated Timing Signals Output Enable OE Address 0x04 3 The OE bit should be regarded as a
76. OxED 0xC5 0x93 0x00 0x48 OxAO Ox3E 0x00 Notes Y2 AIN2 Pr2 AIN3 Pb2 AIN6 Set DNR threshold to 4 for flat response ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting MODE 4 CVBS TUNER INPUT PAL ONLY ON AIN4 8 bit ITU R BT 656 output 15 8 Table 89 Mode 4 Tuner Input CVBS PAL Only Register Address 0x00 0x07 0x15 0x17 0x19 0x3A 0x50 OxOE 0x50 0x52 0x58 0x77 0x7C 0x7D 0xD0 0xD5 0xD7 0xE4 OxEA OxOE Register Value 0x83 0x01 0x00 0x41 OxFA 0x16 0 80 0 20 0 18 OxED 0 5 0 93 0 00 0 48 OxAO OxEA Ox3E OxOF 0x00 Notes CVBS AIN4 Force PAL only mode Enable PAL autodetection only Slow down digital clamps Set CSFM to SH1 Stronger dot crawl reduction Power down ADC 1 and ADC 2 Set higher DNR threshold ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Recommended setting Rev 0 P
77. PFTOGDELO PAL Field Toggle Delay on Odd Field Address OxEA 7 When is 0 default there is no delay Setting PFTOGDELO to 1 delays the F toggle transition on an odd field by a line relative to PFTOG PFTOGDELE PAL Field Toggle Delay on Even Field Address OxEA 6 When PFTOGDELE is 0 there is no delay Setting PFTOGDELE to 1 default delays the F toggle transition on an even field by a line relative to PFTOG PFTOGSIGN PAL Field Toggle Sign Address OxEA 5 Setting PFTOGSIGN to 0 delays the Field transition Set for user manual programming Setting PFTOGSIGN to 1 default advances the Field transition Not recommended for user programming PFTOG PAL Field Toggle Address OxEA 4 0 The default value of PFTOG is 00011 indicating the PAL Field toggle position For all NTSC PAL Field timing controls the F bit in the AV code and the Field signal on the FIELD DE pin are modified ADVANCE TOGGLE OF FIELD BY PTOG 4 0 DELAY TOGGLE OF FIELD BY PFTOG 4 0 2 VALID FOR USER PROGRAMMING ODD FIELD YES NO lt gt 1 0 0 1 ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 LINE FIELD Figure 30 PAL F Toggle SYNC PROCESSING The ADV7183B has two additional sync processing blocks that postprocess the raw synchronization information extracted from the digitized input video If desired the blocks can be disabled via the following two bits 04997 0 030 ENHSPLL E
78. R 7 0 Adjuststhe hue 1 0 Cr by selecting the offset for the Cr channel OxE3 SD Satura SD SAT CB 7 0 Adjusts the 110 0 0 0 0 0 0 Chromagain OdB tion Cb saturation of the picture by affecting gain on the Cb channel OxE4 SD SD SAT CR 7 0 Adjusts the 110 0101 O 0 0 0 Chroma gain 0 dB Saturation saturation of the picture by Cr affecting gain on the Cr channel 0 5 NTSC V NVBEG 4 0 How many lines after 1 0 1 NTSC default BT 656 Icount rollover to set high NVBEGSIGN 0 Set to low when manual programming 1 Not suitable for user programming NVBEGDELE Delay V bit going 0 No delay high by one line relative to NVBEG 1 Additional delay by 1 line even field NVBEGDELO Delay V bit going 0 No delay high by one line relative to NVBEG 4 Additional delay by 1 line odd field OxE6 NTSC V NVEND 4 0 How many lines after 1 0 0 NTSC default BT 656 Bit End Icount rollover to set low NVENDSIGN 0 Set to low when manual programming 1 Not suitable for user programming NVENDDELE Delay V bit going 0 No delay low by one line relative to NVEND 1 Additional delay by 1 line even field NVENDDELO Delay V bit going 0 No delay low by one line relative to NVEND 1 Additional delay by 1 line odd field Rev 0 Page 85 of 96 ADV7183B
79. S VHS 18 Extra Wideband Filter 601 CHROMA FILTER Data from the digital fine clamp block is processed by three sets of filters The data format at this point is CVBS for CVBS inputs chroma only for Y C or U V interleaved for YPrPb input formats The Chroma Antialias Filter CAA The ADV7183B over samples the CVBS by a factor of 2 and the Chroma PrPb by a factor of 4 A decimating filter CAA is used to preserve the active video band and to remove any out of band components The CAA filter has a fixed response Chroma Shaping Filters CSH The shaping filter block CSH can be programmed to perform a variety of low pass responses It can be used to selectively reduce the bandwidth of the chroma signal for scaling or compression Digital Resampling Filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system without user intervention plots in Figure 16 show the overall response of all filters together Rev 0 Page 29 of 96 ADV7183B 2 0 C Shaping Filter Mode Address 0x17 7 The C shaping filter mode bits allow the user to select from a range of low pass filters for the chrominance signal When switched in automatic mode the widest filter is selected based on the video standard format and user choice see settings 000 and 0
80. S begin allows the HS output starts HSB 10 0 HSync positioning of the HS output within pixels after the falling edge the video line of HSync Reserved 0 Setto 0 0x35 HS HSB 7 0 See above using HSB 10 0 Position and HSE 10 0 the user can program Control 2 the position and length of HS output signal 0x36 HS Position HSE 7 0 See above Control 3 0x37 Polarity PCLK Sets the polarity of LLC1 0 Invert polarity 1 Normal polarity as per the timing diagrams Reserved 0 0 Set to 0 PF Sets the FIELD polarity 0 Active high 1 Active low Reserved 0 Set to 0 PVS Sets the VS Polarity 0 Active high 1 Active low Reserved 0 Set to 0 PHS Sets HS Polarity 0 Active high 1 Active low 0x38 NTSC YCMN 2 0 Luma 0 0 0 Adaptive 3 line 3 tap luma un i Comb Mode NTSC 1 0 0 Use low pass notch 9nuo 1 0 1 Fixedluma comb 2 line Top lines of memory 1 1 0 Fixed luma comb 3 Line All lines of memory 1 1 1 Fixed luma comb 2 line Bottom lines of memory CCMN 2 0 Chroma 3 line adaptive for Comb Mode NTSC CTAPSN 01 4 line adaptive for CTAPSN 10 5 line adaptive for CTAPSN 11 110 0 Disable chroma comb 1 0 1 Fixed 2 line for Top lines of memory CTAPSN 01 Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 1 110 Fixed 3 line for All lines of memory CTAPSN 01 Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 1 141 Fixed 2 line for Botto
81. SS2 5 WSS2 4 WSS2 3 WSS2 2 WSS2 1 WSS2 0 EDTV 1 EDTV1 7 EDTV1 6 EDTV1 5 EDTV1 4 EDTV1 3 EDTV1 2 EDTV1 1 EDTV1 0 EDTV 2 EDTV2 7 EDTV2 6 EDTV2 5 EDTV2 4 EDTV2 3 EDTV2 2 EDTV2 1 EDTV2 0 EDTV 3 EDTV3 7 EDTV3 6 EDTV3 5 EDTV3 4 EDTV3 3 EDTV3 2 EDTV3 1 EDTV3 0 CGMS 1 CGMS1 7 CGMS1 6 CGMS1 5 CGMS1 4 CGMS1 3 CGMS1 2 CGMS1 1 CGMS1 0 CGMS 2 CGMS2 7 CGMS2 6 CGMS2 5 CGMS2 4 CGMS2 3 CGMS2 2 CGMS2 1 CGMS2 0 CGMS 3 CGMS3 7 CGMS3 6 CGMS3 5 CGMS3 4 CGMS3 3 CGMS3 2 CGMS3 1 CGMS3 0 CCAP1 CCAP1 7 CCAP1 6 CCAP1 5 CCAP1 4 CCAP1 3 CCAP1 2 CCAP1 1 CCAP1 0 CCAP2 CCAP2 7 CCAP2 6 CCAP2 5 CCAP2 4 CCAP2 3 CCAP2 2 CCAP2 1 CCAP2 0 Letterbox 1 LB_LCT 7 LB_LCT 6 LB_LCT 5 LB_LCT 4 LB_LCT 3 LB_LCT 2 LB_LCT 1 LB LCT O Letterbox 2 LB LCM 7 LB LCM 6 LB LCM 5 LB_LCM 4 LB_LCM 3 LB_LCM 2 LB_LCM 1 LB_LCM O Letterbox 3 LB_LCB 7 LB_LCB 6 LB_LCB 5 LB_LCB 4 LB_LCB 3 LB_LCB 2 LB_LCB 1 LB_LCB O Reserved CRC Enable CRC_ENABLE Reserved ADC Switch 1 ADC1_SW 3 ADC1_SW 2 ADC1_SW 1 ADC1_SW 0 SW 3 ADCO SW 2 ADCO SW 1 SW 0 ADC Switch 2 ADC SW M ADC2 SW 3 ADC2 SW 2 ADC2 SW 1 ADC2 SW 0 AN Reserved Letterbox Control 1 LB 4 LB TH 3 LB TH 2 LB TH 1 0 Letterbox Control 2 LB 513 LB 51 2 LB_SL 1 LB_SL O LB EL 3 LB EL 2 LB EL 1 LB ELO Reserved Reserved Reserved SD Offset Cb SD OFF 7 SD OFF CB 6 SD OFF CB 5 SD OFF 4 SD OFF SD OFF 2 SD OFF CB 1 SD OFF 0 SD Offset Cr SD OFF 7 SD OFF CR 6 SD OFF CR 5 SD OFF SD OFF CR3 SD OFF
82. Setting WYSFMOVR to 1 enables manual override via WYSEM 4 0 default Rev 0 Page 27 of 96 ADV7183B SET YSFM YSFM IN AUTO MODE 00000 OR 00001 NO USE YSFM SELECTED FILTER REGARDLESS FOR GOOD AND BAD VIDEO AUTO SELECT LUMA SHAPING FILTER TO COMPLEMENT COMB 1 0 SELECT WIDEBAND MEA 2505 WYSFM 4 0 Figure 11 YSFM and WYSFM Control Flowchart 04997 0 011 Table 29 YSEM Function WYSFM 4 0 Wide Band Y Shaping Filter Mode YSFM 4 0 Description Address 0 18 4 0 0 0000 Automatic selection including a wide notch The 4 0 bits allow the user to manually select a shaping response PAL NTSC SECAM filter for good quality video signals for example CVBS with 0 0001 default Automatic selection including a narrow stable time base luma component of YPrPb luma component notch response PAL NTSC SECAM of YC The WYSPM bits are only active if the WYSFMOVR bit 00010 SVHS 1 is set to 1 See the general discussion of the shaping filter 0 0011 SVHS 2 settings in the Y Shaping Filter section 0 0100 SVHS 3 001 01 SVHS 4 Table 30 WYSFM Function 10 5 5 5 5 4 01 Description oot 24159 00000 Do not use on 000 0 0001 Do not use 01001 0 0010 SVHS 1 1010 NT 00011 SVHS 2 01011 SVHS 10 QOO SVHS 3 01100 SVHS 11 Sys 01101 SVHS 12 SVHS 5 01110 SVHS 13 ots sVus 6 01111 SVHS 14 0089 SVHS 7 1 0000 SVHS 15 0001 S VS 8 SVHS
83. TERFACE CONTROL LINES 1009 RESET 100nF 1009 DVDDIO 4 7KQ Y DGND ADV7183B _ 0 01uF POWER SUPPLY DECOUPLING FOR Foenn Loann EACH POWER PIN x 1 1 oiuF 0 01uF POWER SUPPLY DECOUPLING FOR 1 1 NT AGND EACH POWER PIN OF 0 01uF SUPPLY DECOUPLING FOR NT AGND EACH POWER PIN 0 01 POWER SUPPLY DECOUPLING FOR EACH POWER MULTI FORMAT PIXEL PORT 27MHz OUTPUT CLOCK 13 5MHz OUTPUT CLOCK 4 OUTPUT ENABLE I P INTERRUPT O P SFL O P HS O P VS O P FIELD O P 1 7KQ 10nF 82nF PVDD DGND DGND Figure 45 Typical Connection Diagram Rev 0 Page 93 of 96 P15 P8 8 ITU R BT 656 PIXEL DATA 27MHz 7 Cb AND Cr 16 ITU R 656 PIXEL DATA 13 5MHzi 15 8 Y 16 BIT ITU R BT 656 PIXEL DATA 13 5MHz ADV7183B 04997 0 042 ADV7183B OUTLINE DIMENSIONS M 500 max 45 SEATING PLANE 0 T 1 45 S 5 is N Tus 0 05 gan 0 10 MAX VIEW A ROTATED 90 CCW COPLANARITY TOP VIEW PINS DOWN VIEW A COMPLIANT TO JEDEC STANDARDS MS 026 BEC Figure 46 80 Lead Low Profile Quad Flat Package LOFP ST 80 2 Dimensions shown in millimeters ORDERING GUIDE Model Temperature Range Package Description Package Option ADV7183
84. TERFACE 16 BIT INTERFACE ADV7183B SD_DUP_AV Duplicate AV codes Address 0x03 0 Depending on the output interface width it may be necessary to duplicate the AV codes from the luma path into the chroma path In an 8 bit wide output interface Cb Y Cr Y interleaved data the AV codes are defined as FF 00 00 AV with AV being the transmitted word that contains information about In this output interface mode the following assignment takes place Cb FE Y 00 Cr 00 and Y AV In a 16 bit output interface where Y and Cr Cb are delivered via separate data buses the AV code is over the whole 16 bits The SD DUP AV bit allows the user to replicate the AV codes on both busses so the full AV sequence can be found on the Y bus as well as on the Cr Cb bus See Figure 19 When SD_DUP_AV is 0 default the AV codes are in single fashion to suit 8 bit interleaved data output When SD_DUP_AV is 1 the AV codes are duplicated for 16 bit interfaces VBI_EN Vertical Blanking Interval Data Enable Address 0x03 7 The VBI enable bit allows data such as intercast and closed caption data to be passed through the luma channel of the decoder with a minimal amount of filtering All data for Lines 1 to 21 is passed through and available at the output port The ADV7183B does not blank the luma data and automatically switches all filters along the luma data path into their widest bandwidth For active video the filter setting
85. UPD to 0 updates the gain once per video line Setting PW to 1 default updates the gain once per field Chroma Gain CAGC 1 0 Chroma Automatic Gain Control Address 0x2C 1 0 The two bits of Color Automatic Gain Control mode select the basic mode of operation for automatic gain control in the chroma path Table 37 CAGC Function CAGC 1 0 Description 00 Manual fixed gain use CMG 11 0 01 Use luma gain for chroma 10 default Automatic gain based on color burst 11 Freeze chroma gain 0 default Assuming YprPb is selected as input format Selecting PAL with pedestal selects MII Selecting PAL without pedestal selects SMPTE Selecting NTSC with pedestal selects MII Selecting NTSC without pedestal selects SMPTE 1 Assuming YprPb is selected as input format Selecting PAL with pedestal selects BETACAM Selecting PAL without pedestal selects BETACAM variant Selecting NTSC with pedestal selects BETACAM Selecting NTSC without pedestal selects BETACAM variant 1 0 Chroma Automatic Gain Timing Address 0x2D 7 6 The Chroma Automatic Gain Timing register allows the user to influence the tracking speed of the chroma automatic gain con trol This register has an effect only if the CAGC 1 0 register is set to 10 automatic gain Table 38 CAGT Function CAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive
86. UT i 1 vs OUTPUT PVBEG 4 0 0x1 PVEND 4 0 0x4 FIELD 2 OUTPUT PFTOG 4 0 0 6 FIELD 2 1310 H 311 312 313 314 315 316 317 318 319 320 321 322 323 1 1 1 benn 1 output VIDEO 1 1 l PVBEG 4 0 0 1 PVEND 4 0 0x4 FELD gt OUTPUT 7 PFTOG 4 0 0x6 04997 0 027 Figure 27 PAL Typical VSync Field Positions Using Register Writes in Table 56 Rev 0 Page 44 of 96 ADVANCE BEGIN OF VSYNC PVBEG 4 0 DELAY BEGIN OF VSYNC BY PVBEG 4 0 NOT VALID FOR USER PROGRAMMING ODD FIELD YES NO 1 0 0 a ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 0 0 1 ADVANCE BY ADVANCE BY 0 5 LINE 0 5 LINE 04997 0 028 Figure 28 PAL VSync Begin PVBEGDELO PAL VSync Begin Delay on Odd Field Address 0 8 7 When PVBEGDELO is 0 default there is no delay Setting PVBEGDELO to 1 delays VSync going high on an odd field by a line relative to PVBEG PVBEGDELE PAL VSync Begin Delay on Even Field Address 0 8 6 When PVBEGDELE is 0 there is no delay Setting PVBEGDELE to 1 default delays VSync going high on an even field by a line relative to PVBEG PVBEGSIGN PAL VSync Begin Sign Address 0 8 5 Setting PVBEGSIGN to 0 delays the beginning of VSync Set for user manual programming Setting PVBEGSIGN to 1 default advances the beginning of VSync Not recommended f
87. VBS1 1 Composite 0001 CVBS2 AIN2 Composite 0010 CVBS3 AIN3 Composite 0011 CVBS4 AIN4 Composite 0100 CVBS5 AIN5 Composite 0101 CVBS6 AIN6 Composite 0110 Y1 AIN1 YC C1 AIN4 YC 0111 Y2 AIN2 YC C2 AIN5 YC 1000 Y3 AIN3 YC C3 AIN6 YC 1001 Y1 AIN1 YPrPb PR1 AIN4 YPrPb PB1 5 YPrPb 1010 Y2 AIN2 YPrPb PR2 AIN3 YPrPb PB2 AIN6 YPrPb 1011 CVBS7 AIN7 Composite 1100 CVBS8 8 Composite 1101 CVBS9 AIN9 Composite 1110 CVBS10 AIN10 Composite 1111 CVBS11 AIN11 Composite Input Pin ADI Recommended Input Muxing Control Channel No INSEL 3 0 AIN7 41 CVBS7 AIN1 42 CVBS1 YC1 Y YPrPb1 Y AIN8 43 CVBS8 AIN2 44 CVBS2 YC2 Y YPrPb2 Y 9 45 CVBS9 46 CVBS3 YC3 Y YPrPb2 Pb 10 57 CVBS10 AINA 58 CVBS4 YC1 C YPrPb1 Pb AIN11 59 CVBS11 AIN5 60 CVBS5 YC2 C YPrPb1 Pr AIN12 61 Not Available AIN6 62 CVBS6 YC3 C YPrPb2 Pr ADI recommended input muxing is designed to minimize crosstalk between signal channels and to obtain the highest level of signal integrity Table 9 summarizes how PCB layout should connect analog video signals to the ADV7183B It is strongly recommended to connect any unused analog input pins to AGND to act as a shield Inputs AIN7 to AIN11 should be connected to AGND when only six input channels are used This improves the quality of the sampling due to better isolation between the channels AINI2 is not under the control o
88. age 89 of 96 ADV7183B PCB LAYOUT RECOMMENDATIONS The ADV7183B is a high precision high speed mixed signal device To achieve the maximum performance from the part it is important to have a well laid out PCB board The following is a guide for designing a board using the ADV7183B ANALOG INTERFACE INPUTS Care should be taken when routing the inputs on the PCB Track lengths should be kept to a minimum and 75 trace impedances should be used when possible Trace impedances other than 75 also increase the chance of reflections POWER SUPPLY DECOUPLING It is recommended to decouple each power supply pin with 0 1 and 10 nF capacitors The fundamental idea is to have a decoupling capacitor within about 0 5 cm of each power pin Also avoid placing the capacitor on the opposite side of the PC board from the ADV7183B as doing so interposes resistive vias in the path The decoupling capacitors should be located between the power plane and the power pin Current should flow from the power plane to the capacitor to the power pin Do not make the power connection between the capacitor and the power pin Placing a via underneath the 100 nF capacitor pads down to the power plane is generally the best approach see Figure 41 VIA TO SUPPLY VIA TO GND 04997 0 038 Figure 41 Recommended Power Supply Decoupling It is particularly important to maintain low noise and good stability of PVDD Careful attention must be paid to
89. aliasing Filters 2 91 Typical Circuit Connection eerte 92 Outline Dimensions entente tenentes 94 Ordering Guide 94 Rev 0 Page 2 of 96 ADV7183B INTRODUCTION The ADV7183B is a high quality single chip multiformat video decoder that automatically detects and converts PAL NTSC and SECAM standards in the form of composite S Video and component video into a digital ITU R BT 656 format The advanced and highly flexible digital output interface enables performance video decoding and conversion in line locked clock based systems This makes the device ideally suited for a broad range of applications with diverse analog video charac teristics including tape based sources broadcast sources security surveillance cameras and professional systems ANALOG FRONT END The ADV7183B analog front end comprises three 10 bit ADCs that digitize the analog video signal before applying it to the standard definition processor The analog front end employs differential channels to each ADC to ensure high performance in mixed signal applications The front end also includes a 12 channel input mux that enables multiple video signals to be applied to the ADV7183B Current and voltage clamps are positioned in front of each ADC to ensure that the video signal remains within the range of the converter Fine clamping of the video signals is performed downstream by digital fine clamping w
90. amble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 0 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data Count 6 CCAP word1 7 0 0 0 User data words 7 CCAP word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 200h 9 1 0 0 0 0 0 0 0 0 0 UDW padding 200h 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev 0 Page 55 of 96 ADV7183B GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 The 16 bits of the GDECEL 15 0 are interpreted as a collection of 16 individual line decode enable signals Each bit refers to a line of video in an even field Setting the bit enables the decoder block trying to find Gemstar or closed caption compatible data on that particular line Setting the bit to 0 prevents the decoder from trying to retrieve data See Table 73 and Table 74 To retrieve closed caption data services on NTSC Line 284 11 must be set To retrieve closed caption data services on PAL Line 335 14 must be set The default value of GDECEL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the even field GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 The 16 bits of the GDECOL 15 0 form a collection of 16 individual line decode enable signals See Table 73 and Table 74 To retrieve closed caption data service
91. andard 6 Reserved 7 Reserved Rev 0 Page 18 of 96 ADV7183B STATUS 3 STATUS_3 7 0 Address 0x13 7 0 Table 17 STATUS 3 Function STATUS 3 7 0 Bit Name Description 0 INST_HLOCK Horizontal lock indicator instantaneous 1 GEMD Gemstar detect 2 SD OP 50HZ Flags whether 50 Hz or 60 Hz is present at output 3 Reserved for future use 4 FREE RUN ACT Output a blue screen see the DEF VAL AUTO EN section 5 STD FLD LEN Field length is correct for currently selected video standard 6 INTERLACED Interlaced video detected field sequence found 7 PAL SW LOCK Reliable sequence of swinging bursts detected Rev 0 Page 19 of 96 ADV7183B STANDARD DEFINITION PROCESSOR SDP STANDARD DEFINITION PROCESSOR MACROVISION VBI DATA STANDARD DETECTION RECOVERY AUTODETECTION LUMA GAIN FILTER CONTROL DIGITIZED CVBS DIGITIZED Y YC SYNC EXTRACT CHROMA CHROMA CHROMA GAIN DEMOD FILTER CONTROL Fsc RECOVERY Figure 8 Block Diagram of the Standard Definition Processor SD CHROMA PATH The input signal is processed by the following blocks DIGITIZED CVBS DIGITIZED C YC block diagram of the ADV7183B s standard definition processor SDP is shown in Figure 8 The SDP block can handle standard definition video in CVBS YC and YPrPb formats It can be divided into a luminance and a chrominance path If the input video is of a composite type CVBS both processin
92. ata words 9 IEP EP 0 0 CCAP word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5101 Checksum Table 70 NTSC CCAP Data Full Byte Mode Byte DI9 DI8 DI7 DI6 D 5 0 4 0121 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 1 0 0 SDID 5 EP EP 0 0 0 0 0 1 0 0 Data count 6 CCAP word1 7 0 0 0 User data words 7 CCAP word2 7 0 0 0 User data words 8 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 9 1 0 0 0 0 0 0 0 0 0 UDW padding 0x200 10 ICS 8 CS 8 CS 7 CS 6 CS 5 5 4 CS 3 CS 2 CS 1 CS 0 Checksum Rev 0 Page 54 of 96 ADV7183B NTSC CCAP Data Half byte output mode is selected by setting CDECAD 0 the full byte mode is enabled by CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section The data packet formats are shown in Table 71 and Table 72 Only closed caption data can be embedded in the output data stream NTSC closed caption data is sliced on line 21d on even and odd fields The corresponding enable bit has to be set high See the GDECEL 15 0 Gemstar Decoding Even Lines Address 0x48 7 0 Address 0x49 7 0 and GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 sections Table 71 PAL CCAP Data Half Byte Mode PAL CCAP Data Half byt
93. cal sync lock established fortis Register SD_H_LOCK SD horizontal sync lock not purpose Access established Page 2 SD horizontal sync lock established Reserved x Not used SCM_LOCK 0 SECAM lock not established SECAM Lock 1 SECAM lock established Reserved x Not used Reserved x Not used Reserved Not used Ox4A Interrupt SD OP CHNG Q No Change in SD signal These bits Status 3 SD 60 50 Hz frame rate at standard detected at the input can be input A Change in SD signal standard cleared and Read Only is detected at the input masked by Register SD V LOCK CHNG Q No change in SD vertical sync PE lock status Ox4C Register SD vertical sync lock status has respectively Access changed Page 2 SD H LOCK CHNG 0 No change in SD horizontal sync lock status SD horizontal sync lock status has changed SD AD CHNG Q x No change in AD_RESULT 2 0 SD autodetect changed bits in Status Register 1 AD_RESULT 2 0 bits in Status Register 1 have changed SCM_LOCK_CHNG_Q 0 No change in SECAM Lock SECAM Lock status 1 SECAM lock status has changed PAL_SW_LK_CHNG_Q x No change in PAL swinging burst lock status PAL swinging burst lock status has changed Reserved x Not used Reserved Not used Rev 0 Page 69 of 96 ADV7183B Bit Subaddress Register Bit Description 6 15 4 3 Comments Notes 0x4B Interrupt SD_OP_CHN
94. cy when this decoder is connected to any Analog Devices Inc digital video encoder Internal Voltage Reference Output Refer to Figure 45 for a recommended capacitor network for this pin The CML pin is common mode level for the internal ADCs Refer to Figure 45 for a recommended capacitor network for this pin ADC s Capacitor Network Refer to Figure 45 for a recommended capacitor network for this pin ADC s Capacitor Network Refer to Figure 45 for a recommended capacitor network for this pin Rev 0 Page 11 of 96 ADV7183B ANALOG FRONT END ANALOG INPUT MUXING INTERNAL MAPPING FUNCTIONS 8 m 5 9 5 Figure 6 Internal Pin Connections The ADV7183B has an integrated analog muxing section that allows more than one source of video signal to be connected to the decoder Figure 6 outlines the overall structure of the input muxing provided in the ADV7183B As seen in Figure 6 the analog input muxes can be controlled by functional registers INSEL or manually Using INSEL 3 0 simplifies the setup of the muxes and minimizes crosstalk between channels by pre assigning the input channels This is referred to as ADI recommended input muxing Control via PC manual override ADC_sw_man_en ADCO sw ADC1_sw ADC2_sw is provided for applications with special requirements for example number combinations of signals that would not be served by the pre assigned input connections This is referred t
95. d XXXX XXXX rw 26 28 0x1A 0x1C ADI Control 2 0000 Oxxx rw 29 0x1D Reserved XXXX XXXX rw 30 38 0x1E 0x26 Pixel Delay Control 0101 1000 rw 39 0x27 Reserved XXXX XXXX rw 40 42 0x28 0x2A Misc Gain Control 1110 0001 rw 43 0x2B AGC Mode Control 1010 1110 rw 44 0 2 Chroma Gain Control 1 11110100 rw 45 0x2D Chroma Gain Control 2 0000 0000 rw 46 0 2 Luma Gain Control 1 1111 xxxx rw 47 Ox2F Luma Gain Control 2 XXXX XXXX rw 48 0x30 VSync Field Control 1 0001 0010 rw 49 0x31 VSync Field Control 2 0100 0001 rw 50 0x32 VSync Field Control 3 1000 0100 rw 51 0x33 HSync Position Control 1 0000 0000 rw 52 0x34 HSync Position Control 2 0000 0010 rw 53 0x35 HSync Position Control 3 0000 0000 rw 54 0x36 Polarity 0000 0001 rw 55 0x37 NTSC Comb Control 1000 0000 rw 56 0x38 PAL Comb Control 1100 0000 rw 57 0x39 ADC Control 0001 0000 rw 58 0x3A Reserved XXXX XXXX rw 59 60 Ox3B 0x3C Rev 0 Page 62 of 96 ADV7183B Subaddress Register Name Reset Value rw Dec Hex Manual Window Control 0100 0011 rw 61 0x3D Reserved XXXX XXXX rw 62 64 0x3E 0x40 Resample Control 0100 0001 rw 65 0x41 Reserved XXXX XXXX rw 66 71 0x42 0x47 Gemstar Ctrl 1 00000000 rw 72 0x48 Gemstar Ctrl 2 0000 0000 rw 73 0x49 Gemstar Ctrl 3 0000 0000 rw 74 Ox4A Gemstar Ctrl 4 0000 0000 rw 75 Ox4B GemStar Ctrl 5 XXXX xxxO rw
96. d by characterization ADC1 powered on 5 All three ADCs powered on Rev 0 Page 5 of 96 ADV7183B VIDEO SPECIFICATIONS Guaranteed by characterization At 3 15 V to 3 45 Dvpp 1 65 V to 2 0 3 0 V to 3 6 1 65 V to 2 0 V operating temperature range unless otherwise noted Table 2 Parameter Symbol Test Conditions Min Typ Max Unit NONLINEAR SPECIFICATIONS Differential Phase DP CVBS I P modulate 5 step 0 5 0 7 Differential Gain DG CVBS I P modulate 5 step 0 5 0 7 Luma Nonlinearity LNL CVBS I P 5 step 0 5 0 7 NOISE SPECIFICATIONS SNR Unweighted Luma ramp 54 56 dB Luma flat field 58 60 dB Analog Front End Crosstalk 60 dB LOCK TIME SPECIFICATIONS Horizontal Lock Range 5 5 Vertical Lock Range 40 70 Hz Fsc Subcarrier Lock Range 1 3 Hz Color Lock In Time 60 Lines Sync Depth Range 20 200 Color Burst Range 5 200 Vertical Lock Time 2 Fields Autodetection Switch Speed 100 Lines CHROMA SPECIFICATIONS Hue Accuracy HUE 1 B Color Saturation Accuracy CL AC 1 96 Color AGC Range 5 400 96 Chroma Amplitude Error 0 5 96 Chroma Phase Error 0 4 Chroma Luma Intermodulation 0 2 LUMA SPECIFICATIONS Luma Brightness Accuracy CVBS 1 V I P 1 Luma Contrast Accuracy CVBS 1 V I P 1 Rev 0 Page 6 of 96 ADV7183B TIMING SPECIFICATIONS Guaranteed by characterization At Avpp 3 15 V to 3 45 V Dvpp 1 65 V to 2 0 V Dvppio 3 0 V to 3 6
97. ddress 0x4D 5 The DNR EN bit enables the DNR block or bypasses it Setting DNR EN to 0 bypasses DNR disables it Setting DNR EN to 1 default enables digital noise reduction on the luma data DNR_TH 7 0 DNR Noise Threshold Address 0x50 7 0 The TH 7 0 value is an unsigned 8 bit number used to determine the maximum edge that will be interpreted as noise and therefore blanked from the luma data Programming a large value into TH 7 0 causes the DNR block to interpret even large transients as noise and remove them The effect on the video data is therefore more visible Programming a small value causes only small transients to be seen as noise and to be removed The recommended TH 7 0 setting for A V inputs is 0x04 and the recommended DNR TH 7 0 setting for tuner inputs is OxOA The default value for DNR_TH 7 0 is 0x08 indicating the threshold for maximum luma edges to be interpreted as noise Rev 0 Page 34 of 96 COMB FILTERS The comb filters of the ADV7183B have been greatly improved to automatically handle video of all types standards and levels of quality The NTSC and PAL configuration registers allow the user to customize comb filter operation depending on which video standard is detected by autodetection or selected by manual programming In addition to the bits listed in this section there are some further ADI internal controls contact ADI for more information NTSC Comb
98. deally suited for a broad range of applications with diverse analog video characteristics including tape based sources broadcast sources security surveillance cameras and professional systems The 10 bit accurate A D conversion provides professional quality video performance and is unmatched This allows true 8 bit resolution in the 8 bit output mode The 12 analog input channels accept standard Composite S Video YPrPb video signals in an extensive number of Rev 0 Information furnished by Analog Devices is believed to be accurate and reliable However no responsibility is assumed by Analog Devices for its use nor for any infringements of patents or other rights of third parties that may result from its use Specifications subject to change without notice No license is granted by implication or otherwise under any patent or patent rights of Analog Devices Trademarks and registered trademarks are the property of their respective owners 0 5 V to 1 6 V analog signal input range Differential gain 0 596 typ Differential phase 0 5 typ Programmable video controls Peak white hue brightness saturation contrast Integrated on chip video timing generator Free run mode generates stable video ouput with no I P decode support for close captioning WSS CGMS EDTV Gemstar 1x 2x Power down mode 2 wire serial MPU interface I C compatible 3 3 V analog 1 8 V digital core 3 3 V supply 2 temperature grades 25 C to 70 C
99. dulated color component Setting AD SEC525 EN to 1 enables the detection Rev 0 Page 21 of 96 ADV7183B AD SECAM EN Enable Autodetection of SECAM Address 0x07 6 Setting AD SECAM EN to 0 disables the autodetection of SECAM Setting AD SECAM EN to 1 default enables the detection AD NA443 EN Enable Autodetection of NTSC 443 Address 0x07 5 Setting AD N443 EN to 0 disables the autodetection of NTSC style systems with a 4 43 MHz color subcarrier Setting 443 EN to 1 default enables the detection AD P60 EN Enable Autodetection of PAL60 Address 0x07 4 Setting AD P60 EN to 0 disables the autodetection of PAL systems with a 60 Hz field rate Setting P60 EN to 1 default enables the detection AD PALN EN Enable Autodetection of PAL N Address 0x07 3 Setting AD PALN EN to 0 disables the detection of the PAL standard Setting AD PALN EN to 1 default enables the detection AD PALM EN Enable Autodetection of PAL M Address 0x07 2 Setting AD PALM EN to 0 disables the autodetection of PAL M Setting AD PALM EN to 1 default enables the detection AD NTSC EN Enable Autodetection of NTSC Address 0x07 1 Setting AD NTSC EN to 0 disables the detection of standard NTSC Setting AD NTSC EN to 1 default enables the detection AD PAL EN Enable Autodetection of PAL Address 0x07 0 Setting AD PAL EN to 0 disables the detection of standard PAL Setting AD PAL EN to 1 default
100. e output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Table 71 and Table 72 list the bytes of the data packet Only closed caption data can be embedded in the output data stream PAL closed caption data is sliced from Lines 22 and 335 The corresponding enable bits have to be set See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 and GDECOL 15 0 Gemstar Decoding Odd Lines Address 0x4A 7 0 Address 0x4B 7 0 sections Byte DI9 DI8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 0 1 0 1 0 0 0 SDID 5 IEP EP 0 0 0 0 0 1 0 0 Data count 6 IEP EP 0 0 CCAP word1 7 4 0 0 User data words 7 0 0 CCAP word1 3 0 0 0 User data words 8 0 0 CCAP word2 7 4 0 0 User data words 9 IEP EP 0 0 CCAP word2 3 0 0 0 User data words 10 ICS 8 CS 8 CS 7 CS 6 CS 5 CS 4 CS 3 CS 2 CS 1 5 0 Table 72 PAL CCAP Data Full Byte Mode Byte D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed pre
101. e polarity of the clock and therefore the Y C assignments to outputting the nominal 13 5 MHz clock on the LLC pin see the clock edges can be altered by using the Polarity LLC pin the LLC1 Output Selection LLC PAD SEL 2 0 Address Ox8F 6 4 section When PAD SEL 2 0 is 000 default the output is nominally 27 MHz LLC on the LLCI pin When LLC_PAD_SEL 2 0 is 101 the output is nominally 13 5 MHz LLC on the LLCI pin Table 78 15 0 Output Input Pin Mapping Data Port Pins P 15 0 Format and Mode 15 14 13 12 11 10 9 8 7 6 5 4131211 10 Video Out 8 Bit 4 2 2 YCrCb 7 0 OUT Video Out 16 Bit 4 2 2 Y 7 0 OUT CrCb 7 0 OUT Table 79 Standard Definition Pixel Port Modes P 15 0 OF_SEL 3 0 Format P 15 8 P 7 0 0010 16 Bit LLC2 4 2 2 Y 7 0 CrCb 7 0 0011 default 8 LLC1 4 2 2 default YCrCb 7 0 default Three State 0110 1111 Reserved Reserved Do not use Rev 0 Page 59 of 96 ADV7183B MPU PORT DESCRIPTION The ADV7183B supports 2 wire PC compatible serial inter face Two inputs serial data SDA and serial clock SCLK carry information between the ADV7183B and the system master controller Each slave device is recognized by a unique address The ADV7183B s port allows the user to set up and configure the decoder and to read back captured VBI data The ADV7183B has two possible slave address
102. ecommended setting 0xD5 0 0 Recommended setting 0 07 OxEA Recommended setting OxE4 Ox3E Recommended setting OxEA OxOF Recommended setting OxOE 0x00 Recommended setting MODE 2 S VIDEO INPUT Y ON AIN1 AND C ON AIN4 All standards are supported through autodetect 8 bit ITU R BT 656 output P15 P8 Table 87 Mode 2 S Video Input Register Address Register Value Notes 0x00 0x06 Y1 AINT C1 0x15 0x00 Slow down digital clamps 0x3A 0x12 Power down ADC 2 0x50 0x04 Set DNR threshold to 4 for flat response 0x0E 0x80 ADI recommended programming sequence This sequence must be followed exactly when setting up the decoder 0x50 0x20 Recommended setting 0x52 0x18 Recommended setting 0x58 OxED Recommended setting 0x77 5 Recommended setting 0 7 0x93 Recommended setting 0x7D 0x00 Recommended setting 0xD0 0x48 Recommended setting 0xD5 0 0 Recommended setting 0 07 OxEA Recommended setting OxE4 0x3E Recommended setting OxEA 0x0F Recommended setting 0x0E 0x00 Recommended setting Rev 0 Page 88 of 96 MODE 3 5251 6251 YPRPB INPUT ON AIN2 PR ON AIN3 AND PB AIN6 All standards are supported through autodetect 8 bit ITU R BT 656 output on 15 8 Table 88 Mode 3 YPrPb Input 5251 6251 ADV7183B Register Address 0x00 0x50 OxOE 0x52 0x58 0x77 0x7C 0x7D 0xD0 OxD5 OxE4 OxOE Register Value Ox0A 0x04 0x80 0x18
103. enables the detection SELECT THE RAW LOCK SIGNAL SRLS TIME WIN FREE RUN LOCK TAKE Fac LOCK INTO ACCOUNT FSCLE COUNTER INTO LOCK COUNTER OUT OF LOCK SFL INV Subcarrier Frequency Lock Inversion This bit controls the behavior of the PAL switch bit in the SFL GenLock Telegram data stream It was implemented to solve some compatibility issues with video encoders It solves two problems First the PAL switch bit is only meaningful in PAL Some encoders including Analog Devices encoders also look at the state of this bit in NTSC Second there was a design change in Analog Devices encoders from ADV717x to ADV719x The older versions used the SFL GenLock Telegram bit directly while the later ones invert the bit prior to using it The reason for this is that the inversion compensated for the 1 line delay of an SFL GenLock Telegram transmission As a result ADV717x encoders need the PAL switch bit in the SFL GenLock Telegram to be 1 for NTSC to work and ADV7190 ADV7191 ADV7194 encoders need the PAL switch bit in the SFL to be 0 to work in NTSC If the state of the PAL switch bit is wrong a 180 phase shift Occurs In a decoder encoder back to back system in which SFL is used this bit must be set up properly for the specific encoder used SFL INV Address 0x41 6 Setting SFL_INV to 0 makes the part SFL compatible with ADV7190 ADV7191 ADV7194 encoders Setting SFL INV to 1 default makes
104. ependent on color burst amplitude Taken from luma path Y C Dependent on horizontal sync depth Dependent on color burst amplitude Taken from path Peak White Dependent on color burst amplitude Taken from path YPrPb Dependent on horizontal sync depth Taken from path Luma Gain Table 34 LAGT Function LAGC 2 0 Luma Automatic Gain Control Address 0x30 7 0 The luma automatic gain control mode bits select the mode of operation for the gain control in the luma path There are ADI internal parameters to customize the peak white gain control Contact ADI for more information Table 33 LAGC Function LAGC 2 0 Description 000 Manual fixed gain use LMG 11 0 001 AGC blank level to sync tip No override through peak white 010 default AGC blank level to sync tip Automatic override through peak white 011 Reserved 100 Reserved 101 Reserved 110 Reserved 111 Freeze gain LAGT 1 0 Luma Automatic Gain Timing Address 0x2F 7 6 The luma automatic gain timing register allows the user to influence the tracking speed of the luminance automatic gain control Note that this register only has an effect if the LAGC 2 0 register is set to 001 010 011 100 automatic gain control modes If peak white AGC is enabled and active see the STATUS 1 7 0 Address 0x10 7 0 section the actual gain update speed is dictated by the peak white AGC loop and asa result the LAGT
105. er section 101 Fixed luma comb top lines of line memory Fixed 3 lines 2 taps luma comb 110 Fixed luma comb all lines of line memory Fixed 5 lines 3 taps luma comb 111 Fixed luma comb bottom lines of line memory Fixed 3 lines 2 taps luma comb Rev 0 Page 36 of 96 AV CODE INSERTION AND CONTROLS This section describes the C based controls that affect e Insertion of AV codes into the data stream e Data blanking during the vertical blank interval VBI The range of data values permitted in the output data stream e relative delay of luma versus chroma signals Note that some of the decoded VBI data is being inserted during the horizontal blanking interval See the Gemstar Data Recovery section for more information BT656 4 ITU Standard BT R 656 4 Enable Address 0x04 7 The ITU has changed the position for toggling of the V bit within the SAV EAV codes for NTSC between revisions 3 and 4 The BT656 4 standard bit allows the user to select an output mode that is compliant with either the previous or the new standard For further information review the standard at http www itu int Note that the standard change affects NTSC only and has no bearing on PAL When BT656 4 is 0 default the BT656 3 specification is used The V bit goes low at EAV of Lines 10 and 273 When 656 4 is 1 the 656 4 specification is used The bit goes low at EAV of Lines 20 and 283 SD DUP AV 1 16 BIT IN
106. es for both read and write operations depending on the logic level on the ALSB pin These four unique addresses are shown in Table 80 The ADV7183B s ALSB pin controls Bit 1 of the slave address By altering the ALSB it is possible to control two ADV7183Bs in an application without having a conflict with the same slave address The LSB Bit 0 sets either a read or write operation Logic 1 corresponds to a read operation Logic 0 corresponds to a write operation Table 80 PC Address for the ADV7183B ALSB R W Slave Address 0 0 0x40 0 1 0x41 1 0 0x42 1 1 0x43 To control the device on the bus a specific protocol must be followed First the master initiates a data transfer by establish ing a start condition which is defined by a high to low transition on SDA while SCLK remains high This indicates that an address data stream will follow All peripherals respond to the start condition and shift the next eight bits 7 bit address R W bit The bits are transferred from MSB down to LSB The peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse this is known as an acknowledge bit All other devices withdraw from the bus at this point and maintain an idle condition The idle condition is where the device monitors the SDA and SCLK lines SCLOCK 1 7 8 _ 9 1 7 8 START ADDR R W ACK SUBADDRESS ACK waiting for the start condition and the correct tran
107. ext field The user should start read sequence with VS by first examining the VBI Info register Then depending on what data was detected the appropriate data registers should be read Note that the data registers are filled with decoded VBI data even if their corresponding detection bits are low it is likely that bits within the decoded data stream are wrong The closed captioning data CCAP is available in the registers and is also inserted into the output video data stream during horizontal blanking Gemstar compatible data is not available in the registers and is inserted into the data stream only during horizontal blanking WSSD Wide Screen Signaling Detected Address 0x90 0 Logic 1 for this bit indicates that the data in the WSS1 and WSS2 registers is valid The WSSD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted When WSSD is 0 no WSS is detected and confidence in the decoded data is low When WSSD is 1 WSS is detected and confidence in the decoded data is high CCAPD Closed Caption Detected Address 0x90 1 A Logic 1 for this bit indicates that the data in the CCAP1 and 2 registers is valid The CCAPD bit goes high if the rising edge of the start bit is detected within a time window and if the polarity of the parity bit matches the data transmitted When CCAPD is 0
108. f INSEL 3 0 It can be routed to ADCO ADCI ADC2 only by manual muxing See Table 10 for details Rev 0 Page 13 of 96 ADV7183B Manual Input Muxing By accessing a set of manual override muxing registers the analog input muxes of the ADV7183B can be controlled directly This is referred to as manual input muxing Manual input muxing overrides other input muxing control bits for example INSEL The manual muxing is activated by setting the ADC_SW_MAN_EN bit It only affects the analog switches in front of the ADCs This means if the settings of INSEL and the manual input muxing registers ADCO ADCI ACD2 sw contradict each other the ADCO ADCI ADC2 sw settings Restrictions in the channel routing are imposed by the analog signal routing inside the IC every input pin cannot be routed to each ADC Refer to Figure 6 for an overview on the routing capabilities inside the chip The three mux sections can be controlled by the reserved control signal buses ADC0 ADC1 ADC2 sw 3 0 Table 10 explains the control words used SETADC sw man en Manual Input Muxing Enable Address 0xC4 7 ADC0_sw 3 0 ADCO mux configuration Address 0xC3 3 0 ADCI sw 3 0 ADC1 mux configuration Address 0xC3 7 4 ADC2 sw 3 0 ADC2 mux configuration Address 0xC4 3 0 apply and INSEL is ignored Manual input muxing only controls the analog input muxes INSEL 3 0 still has to be set so the follow on blocks process the video data in the correc
109. ffset of the luma channel 100IRE OxFF Offset of the luma channel 100IRE DEF_Y 5 0 Default Value Y Address 0x0C 7 2 If the ADV7183B loses lock on the incoming video signal or if there is no input signal the DEF_Y 5 0 bits allows the user to specify a default luma value to be output This value is used under the following conditions IfDEF_VAL_AUTO_EN bit is set to high and the ADV7183B lost lock to the input video signal This is the intended mode of operation automatic mode e The DEF_VAL_EN bit is set regardless of the lock status of the video decoder This is a forced mode that may be useful during configuration The DEF_Y 5 0 values define the 6 MSBs of the output video The remaining LSBs are padded with 0s For example in 8 bit mode the output is 7 0 DEF_Y 5 0 0 0 DEF Y 5 0 is 0x0D Blue is the default value for Y Register OxOC has a default value of 0x36 DEF C 7 0 Default Value C Address 0x0D 7 0 The DEF C 7 0 register complements the DEF Y 5 0 value It defines the 4 MSBs of Cr and Cb values to be output if e TheDEF VAL AUTO EN bit is set to high and the ADV7183B cant lock to the input video automatic mode DEF VAL EN bit is set to high forced output The data that is finally output from the ADV7183B for the chroma side is Cr 7 0 DEF C 7 4 0 0 0 0 Cb 7 0 DEF C 3 0 0 0 0 0 DEF C 7 0 is 0x7C blue is the default value for Cr and Cb
110. fication on x ADV7183B 0x13 Read Only the revision of the part 0x12 Status MVCS DET MV color striping detected 1 Detected Register 2 MVCS MV color striping type 0 2 Read Only 1 Type 3 MV PS DET MV pseudo Sync detected 1 Detected MV AGC DET x MV AGC pulses detected 1 Detected LL NSTD x Nonstandard line length 1 Detected FSC NSTD x Fsc frequency nonstandard 1 Detected Reserved x x 0x13 Status INST_HLOCK 1 horizontal lock Unfiltered Register 3 achieved Read Only GEMD 1 Gemstar Data detected SD 50HZ SD 60 Hz detected SDField rate detect Reserved x SD 50 Hz detected FREE_RUN_ACT x 1 Free run mode active Blue screen output STD FLD_LEN x 1 Field length standard Correct Field length found INTERLACED x 1 Interlaced video Field sequence found detected PAL_SW_LOCK 1 Swinging burst Reliable swinging detected burst sequence 0x14 Analog Reserved 0 Set to default Clamp CCLEN Current clamp enable allows 0 Current sources switched Control the user to switch off the current off sources in the analog front 1 Current sources enabled Reserved Set to default Rev 0 Page 74 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 2 1 Comments Notes 0x15 Digital Reserved ojx x Set to default Clamp DCT 1 0
111. for HSB 10 0 write to Address 0x34 first followed by 0x35 e No other taking place between the two or more IC writes for the sequence For example for HSB 10 0 write to Address 0x34 first immediately followed by 0x35 Rev 0 Page 61 of 96 ADV7183B REGISTER MAPS Table 81 Common and Normal Page 1 Register Map Details Subaddress Register Name Reset Value rw Dec Hex Input Control 0000 0000 rw 0 0x00 Video Selection 1100 1000 rw 1 0x01 Reserved 0000 0100 rw 2 0x02 Output Control 0000 1100 rw 3 0x03 Extended Output Control 01xx 0101 rw 4 0x04 Reserved 0000 0000 rw 5 0x05 Reserved 0000 0010 rw 6 0x06 Autodetect Enable 01111111 rw 7 0x07 Contrast 1000 0000 rw 8 0x08 Reserved 1000 0000 rw 9 0x09 Brightness 0000 0000 rw 10 Ox0A Hue 0000 0000 rw 11 0x0B Default Value Y 00110110 rw 12 0x0C Default Value C 01111100 rw 13 0x0D ADI Control 0000 0000 rw 14 0x0E Power Management 0000 0000 rw 15 0x0F Status 1 XXXX XXXX r 16 0x10 Ident XXXX XXXX r 17 0x11 Status 2 XXXX XXXX r 18 0x12 Status 3 XXXX XXXX r 19 0x13 Analog Clamp Control 0001 0010 rw 20 0x14 Digital Clamp Control 1 0100 xxxx rw 21 0x15 Reserved XXXX XXXX rw 22 0x16 Shaping Filter Control 0000 0001 rw 23 0x17 Shaping Filter Control 2 10010011 rw 24 0x18 Comb Filter Control 1111 0001 rw 25 0x19 Reserve
112. formation is presented on the SFL pin Polarity LLC Pin PCLK Address 0x37 0 The polarity of the clock that leaves the ADV7183B via the LLCI and 112 pins can be inverted using the PCLK bit Changing the polarity of the LLC clock output may be necessary to meet the setup and hold time expectations of follow on chips This bit also inverts the polarity of the LLC2 clock When PCLK is 0 the LLC output polarity is inverted When PCLK is 1 default the LLC output polarity is normal as per the timing diagrams Rev 0 Page 17 of 96 ADV7183B GLOBAL STATUS REGISTERS Four registers provide summary information about the video decoder The IDENT register allows the user to identify the revision code of the ADV7183B The other three registers contain status bits regarding IC operation IDENTIFICATION IDENT 7 0 Address 0x11 7 0 This register provides identification of the revision of the ADV7183B An identification value of 0x11 indicates the ADV7183 released silicon An identification value of 0x13 indicates the ADV7183B STATUS 1 STATUS 1 7 0 Address 0x10 7 0 This read only register provides information about the internal status of the ADV7183B See CIL 2 0 Count Into Lock Address 0x51 2 0 and COL 2 0 Count Out of Lock Address 0x51 5 3 for information on the timing Table 15 STATUS 1 Function Depending on the setting of the FSCLE bit the Status 0 and Status 1 bits are based solely on horizontal
113. g Map See Figure 38 Reserved Set as default Rev 0 Page 73 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 Comments Notes 0x0F Power Reserved Set to default Management PDBP Power down bit priority Chip power down selects between PWRDN bit or PIN controlled by pin Bit has priority pin disregarded Reserved 0 0 Set to default PWRDN Power down places the 0 System functional decoder in a full power down mode 1 Powered down See PDBP OxOF Bit 2 Reserved 0 Set to default RES Chip Reset will load all bits 0 Normal operation with default values 1 Start reset sequence Executing reset takes approx 2 ms This bit is self clearing 0x10 Status IN_LOCK In lock right now 1 Provides information Register 1 LOST_LOCK Lost lock since last read 1 about Read Only FSC LOCK Fsc lock right now 1 stats aU Ine FOLLOW_PW x Peak white AGC mode active 1 AD_RESULT 2 0 Autodetection 100 NTSM MJ Detected standard result reports the standard of the olo 1 NTSC 443 Input video CHE NE PALM 0 111 PAL 60 1 PAL BGHID 1 01 1 110 PAL combination 1 111 SECAM 525 COL x Color kill is active 1 Color Kill 0x11 IDENT IDENT 7 0 Provides identi
114. g adjust allows 0 O No Delay CVBS mode Control the user to specify a timing LTA 1 0 00b difference between chroma and uma l elk G7 nS delayed S Video mode luma samples 1 0 Luma 2 clk 74 nS early LTA 1 0 01b YPrPb mode 1 1 Luma 1 clk 37 nS early LTA 1 0 01b Reserved Set to Zero CTA 2 0 Chroma timing adjust Not valid setting CVBS mode allows a specified timing difference olold Chroma 2 pixels early CTA 2 0 011b between the luma and chroma 21110 Chroma 1 pixel early samples del y S Video mode 01111 delay CTA 2 0 1016 1100 Chroma 1 pixel late 1 0 1 Chroma 2 pixels late YPrPb mode 1 11 10 Chroma 3 pixels late CTA 2 0 110b 1 141 Not valid setting AUTO_PDC_EN Automatically 0 Use values in LTA 1 0 and programs the LTA CTA values so CTA 2 0 for delaying that luma and chroma are aligned at luma chroma the output for all modes of 1 LTA and CTA values operation determined automatically SWPC Allows the Cr and Cb samples 0 No Swapping See to be swapped Swap CR CB WB 1 Swap the Cr and Cb O P Addr 0x89 samples Ox2B Misc Gain PW Peak white update 0 Update once per video Peak white must be Control determines the rate of gain line enabled See 1 Update once per field LAGC 2 0 Reserved 2 19720 0 Set to default CKE Color kill enable allows the 0 Color kill disabled For SECAM color kill color kill function to be switched on 1 Color kill enabled threshold is set a
115. g paths are fed with the CVBS input SD LUMA PATH The input signal is processed by the following blocks e Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal e Filter Block This block contains luma decimation filter YAA with a fixed response and some shaping filters YSH that have selectable responses e Luma Gain Control The automatic gain control AGC can operate on a variety of different modes including gain based on the depth of the horizontal sync pulse peak white mode and fixed manual gain e Luma Resample To correct for line length errors as well as dynamic line length changes the data is digitally resampled Luma2D Comb The two dimensional comb filter provides YC separation e Code Insertion At this point the decoded luma Y signal is merged with the retrieved chroma values AV codes as per ITU R BT 656 can be inserted SLLC CONTROL LUMA LUMA RESAMPLE 2D COMB RESAMPLE con VIDEO DATA CONTROL OUTPUT CHROMA CHROMA MEASUREMENT VIDEO DATA J PROCESSING BLOCK 04997 0 008 e Digital Fine Clamp This block uses a high precision algorithm to clamp the video signal e Chroma Demodulation This block employs a color subcarrier Fsc recovery unit to regenerate the color subcarrier for any modulated chroma scheme The demodulation block then performs an AM demodulation for PAL and NTSC and an FM demodulat
116. gement system CGMS EDTV Gemstar 1x 2x and extended data service XDS The ADV7183B is fully Macrovision certified detection circuitry enables Type I II and III protection levels to be identified and reported to the user The decoder is also fully robust to all Macrovision signal inputs Rev 0 Page 3 of 96 ADV7183B FUNCTIONAL BLOCK DIAGRAM OUTPUT FORMATTER TOYLNOD LNdLNO 3384 JOYULNOD 011 daAZISAHLNAS Hb VWOHHO NOILYASNI AV XVI Ht az van VWOYHD VW NOILOSLAGOLNVY 15 1OYULNOD TV8019 AU3AO23HU V1VG ISA UM ARD ERE VLVGISA TOHLNOO TOHLNOD 3OV3d31NI 1VIH3S TOYULNOD H311l4 qoaa TWALISIG MOLOIGaYd HL NIT od 7TOH1NOO uaria VW YOSS390ud NOLLINIJ3Q 15 8 054 Josssie eee gt NOILVH3N39 19019 7OHLNOO 119 GNV ONAS SNISS39O0ti DNAS 5931715 NOILVIWIO3G uossabooudaud viva LNdNI 100 0 66 0 O3dIA S S8A9 47 C LNIV ENIV Figure 1 Rev 0 Page 4 96 ADV7183B SPECIFICATIONS Temperature range Tm to Tmax 409 to 85 The min max
117. in high frequency noise reducing the bandwidth of the luma signal improves visual picture quality A follow on video compression stage may work more efficiently if the video is low pass filtered The ADV7183B has two responses for the shaping filter one that is used for good quality CVBS component and S VHS type sources and a second for nonstandard CVBS signals The YSH filter responses also include a set of notches for PAL and NTSC However it is recommended to use the comb filters for YC separation e Digital resampling filter This block is used to allow dynamic resampling of the video signal to alter parameters such as the time base of a line of video Fundamentally the resampler is a set of low pass filters The actual response is chosen by the system with no requirement for user intervention Figure 12 through Figure 15 show the overall response of all filters together Unless otherwise noted the filters are set into a typical wideband mode Rev 0 Page 26 of 96 ADV7183B Y Shaping Filter For input signals in CVBS format the luma shaping filters play an essential role in removing the chroma component from a composite signal YC separation must aim for best possible crosstalk reduction while still retaining as much bandwidth especially on the luma component as possible High quality YC separation can be achieved by using the internal comb filters of the ADV7183B Comb filtering however relies on the frequency re
118. in the input video signal 1 A change is detected in the WSS data in the input video signal Reserved Not used Reserved Not used Reserved Not used MPU_STIM_INTRQ_Q Manual interrupt not Set Manual interrupt Set 0x47 Interrupt CCAPD_CLR Do not clear Clear 2 Clears CCAPD_Q bit GEMD_CLR Do not clear Write Only Clears GEMD_Q bit CGMS CHNGD CLR Do not clear Register Clears CGMS_CHNGD_Q bit Access Page 2 WSS_CHNGD_CLR 0 Do not clear Clears WSS_CHNGD_Q bit Reserved Not used Reserved Not used Reserved Not used MPU_STIM_INTRQ_CLR Do not clear Clears MPU_STIM_INTRQ_Q bit Rev 0 Page 68 of 96 ADV7183B Bit Subaddress Register Bit Description 615 43 Comments Notes 0x48 Interrupt CCAPD_MSKB Do not mask Mask 2 Masks CCAPD_Q bit GEMD_MSKB Do not mask Masks GEMD_Q bit rite i CGMS_CHNGD_MSKB Do not mask Masks CGMS_CHNGD_Q bit Register Access WSS_CHNGD_MSKB 0 Do not mask Page 2 1 Masks WSS_CHNGD_Q bit Reserved 0 Not used Reserved 0 Not used Reserved 0 used MPU_STIM_INTRQ_MSKB Do not mask Masks MPU_STIM_INTRQ_Q bit 0x49 Raw 50 50 2 SD 60 Hz signal output These bits Status 3 SD 60 50Hz frame rate at SD 50 Hz signal output cannot be output cleared or Read Only SD_V_LOCK SD vertical sync lock not masked Register established Register Ox4A is used SD verti
119. input signal some control is provided via 0 Detection at the Start of a Field The ADV7183B expects a section of at least six consecutive black lines of video at the top of a field Once those lines are detected Register LB LCT 7 0 reports back the number of black lines that were actually found By default the ADV7183B starts looking for those black lines in sync with the beginning of active video for example straight after the last VBI video line SL 3 0 allows the user to set the start of letterbox detection from the beginning of a frame on a line by line basis The detection window closes in the middle of the field Detection at the End of a Field The ADV7183B expects at least six continuous lines of black video at the bottom of a field before reporting back the number of lines actually found via the LB LCB 7 0 value The activity window for letterbox detection end of field starts in the mid dle of an active field Its end is programmable via LB EL 3 0 Detection at the Midrange Some transmissions of wide screen video include subtitles within the lower black box If the ADV7183B finds at least two black lines followed by some more nonblack video for example the subtitle and is then followed by the remainder of the bottom black block it reports back a midcount via LB LCM 7 0 If no subtitles are found LB LCM 7 0 reports the same number LB LCB 7 0 There is a 2 field delay in the rep
120. ion for SECAM e Chroma Filter Block This block contains a chroma decimation filter CAA with a fixed response and some shaping filters CSH that have selectable responses e Gain Control Automatic gain control AGC can operate on several different modes including gain based on the color subcarrier s amplitude gain based on the depth of the horizontal sync pulse on the luma channel or fixed manual gain e Chroma Resample The chroma data is digitally resampled to keep it perfectly aligned with the luma data The resampling is done to correct for static and dynamic line length errors of the incoming video signal e Chroma 2D Comb The two dimensional 5 line superadaptive comb filter provides high quality YC separation in case the input signal is CVBS AV Code Insertion At this point the demodulated chroma Cr and Cb signal is merged with the retrieved luma values AV codes as per ITU R BT 656 can be inserted Rev 0 Page 20 of 96 SYNC PROCESSING The ADV7183B extracts syncs embedded in the video data stream There is currently no support for external HS VS inputs The sync extraction has been optimized to support imperfect video sources such as videocassette recorders with head switches The actual algorithm used employs a coarse detection based on a threshold crossing followed by a more detailed detection using an adaptive interpolation algorithm The raw sync information is sent to a line length measurement a
121. ion of current sources and a digital processing block for clamping as shown in Figure 10 The analog processing channel shown is replicated three times inside the IC While only one single channel and only one ADC would be needed for a CVBS signal two independent channels are needed for YC S VHS type signals and three independent channels are needed to allow component signals YPrPb to be processed FINE COARSE CURRENT CURRENT SOURCES SOURCES ANALOG VIDEO INPUT 8 18 CLAMP CONTROL ADV7183B The clamping can be divided into two sections e Clamping before the ADC analog domain current sources e Clamping after the ADC digital domain digital processing block The ADCs can digitize an input signal only if it resides within the ADC s 1 6 V input voltage range An input signal with a dc level that is too large or too small is clipped at the top or bottom of the ADC range The primary task of the analog clamping circuits is to ensure that the video signal stays within the valid ADC input window so that the analog to digital conversion can take place It is not necessary to clamp the input signal with a very high accuracy in the analog domain as long as the video signal fits the ADC range After digitization the digital fine clamp block corrects for any remaining variations in dc level Since the dc level of an input video signal refers directly to the brightness of the picture t
122. ithin the ADV7183B The ADCs are configured to run in 4x oversampling mode STANDARD DEFINITION PROCESSOR SDP The ADV7183B is capable of decoding a large selection of baseband video signals in composite S Video and component formats The video standards supported include PAL B D I G H PAL60 PAL M PAL PAL Nc NTSC NTSC 4 43 and SECAM B D G K L The ADV7183B can automatically detect the video standard and process it accordingly The ADV7183B has a 5 line superadaptive 2D comb filter that gives superior chrominance and luminance separation when decoding a composite video signal This highly adaptive filter automatically adjusts its processing mode according to video standard and signal quality with no user intervention required Video user controls such as brightness contrast saturation and hue are also available within the ADV7183B The ADV7183B implements a patented adaptive digital line length tracking ADLLT algorithm to track varying video line lengths from sources ADLLT enables the ADV7183B to track and decode poor quality video sources such as VCRs noisy sources from tuner outputs VCD players and camcorders The ADV7183B contains a chroma transient improvement processor that sharpens the edge rate of chroma transitions resulting in sharper vertical transitions The ADV7183B can process a variety of VBI data services such as closed captioning CC wide screen signaling WSS copy generation mana
123. lationship of the luma component multiples of the video line rate and the color subcarrier Fsc For good quality CVBS signals this relationship is known the comb filter algorithms can be used to separate out luma and chroma with high accuracy In the case of nonstandard video signals the frequency relationship may be disturbed and the comb filters may not be able to remove all crosstalk artifacts in an optimum fashion without the assistance of the shaping filter block An automatic mode is provided Here the ADV7183B evaluates the quality of the incoming video signal and selects the filter responses in accordance with the signal quality and video standard YFSM WYSFMOVR and WYSFM allow the user to manually override the automatic decisions in part or in full The luma shaping filter has three control registers e YSFM 4 0 allows the user to manually select a shaping filter mode applied to all video signals or to enable an automatic selection dependent on video quality and video standard e WYSFMOVR allows the user to manually override the WYSFM decision e WYSFM 4 0 allows the user to select a different shaping filter mode for good quality CVBS component YPrPb and S VHS YC input signals In automatic mode the system preserves the maximum possible bandwidth for good CVBS sources since they can successfully be combed as well as for luma components of YPrPb and YC sources since they need not be combed For poor
124. level determines the maximum supported amplitude of the video signal The minimum supported amplitude of the input video is determined by the ADV7183B s ability to retrieve horizontal and vertical timing and to lock to the color burst if present There are two gain control units one each for luma and chroma data Both can operate independently of each other The chroma unit however can also take its gain value from the luma path The possible AGC modes are summarized in Table 32 It is possible to freeze the automatic gain control loops This causes the loops to stop updating and the AGC determined gain at the time of the to freeze stay active until the loop is either unfrozen or the gain mode of operation is changed The currently active gain from any of the modes can be read back Refer to the description of the dual function manual gain registers LG 11 0 Luma Gain and CG 11 0 Chroma Gain in the Luma Gain and Chroma Gain sections ANALOG VOLTAGE RANGE SUPPORTED BY ADC 1 6V RANGE FOR ADV7183B MAXIMUM VOLTAGE MINIMUM VOLTAGE LEVEL SDP DATA GAIN SELECTION ONLY PRE PROCESSOR DPP 04997 0 017 Figure 17 Gain Control Overview Rev 0 Page 30 of 96 Table 32 AGC Modes ADV7183B Input Video Type Luma Gain Chroma Gain Any Manual gain luma Manual gain chroma CVBS Dependent on horizontal sync depth Dependent on color burst amplitude Taken from luma path Peak White D
125. lover to toggle F signal PFTOGSIGN 0 Set to low when manual programming 1 Not suitable for user programming PFTOGDELE Delay F transition by 0 No delay one line relative to PFTOG even 1 Additional delay by 1 line field PFTOGDELO Delay F transition by 0 No delay one line relative to PFTOG odd 1 Additional delay by 1 line field Rev 0 Page 86 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 2 0 Comments Notes OxF4 Drive DR_STR_S 1 0 Select the drive 0 Low drive strength 1x Strength strength for the sync output 1 Medium low drive signals strength 2x 0 Medium high drive strength 3x 1 High drive strength DR STR C 1 0 Select the drive 010 Low drive strength 1x strength for the clock output 0 1 Medium low drive signal strength 2x 110 Medium high drive strength 3x 111 High drive strength 4x DR STR 1 0 Select the drive Low drive strength 1x strength for the data output 011 Medium low drive signals Can be increased or strength 2x for EMC or crosstalk 110 Medium high drive strength 3x 111 High drive strength 4x Reserved x x No delay OxF8 IF Comp IFFILTSEL 2 0 IF filter selection for 0 0 Bypass mode Control PAL and NTSC 2 MHz 5MHz NTSC Filters 0 1 3 2 dB 0 0 6 dB 3 5 dB 0 1
126. luma channel 0 OxFF Gain on luma channel 2 CIL 2 0 Description 000 1 001 2 010 5 011 10 100 default 100 101 500 110 1000 111 100000 SD SAT Cb 7 0 SD Saturation Cb Channel Address OxE3 7 0 This register allows the user to control the gain of the Cb channel only The user can adjust the saturation of the picture Table 22 SD SAT Cb Function SD SAT Cb 7 0 Description 0x80 default 0x00 OxFF Gain on Cb channel 0 Gain on Cb channel 42 dB Gain on Cb channel 6 dB Rev 0 Page 23 of 96 ADV7183B SD SAT Cr 7 0 SD Saturation Cr Channel Address OxEA 7 0 This register allows the user to control the gain of the Cr channel only The user can adjust the saturation of the picture Table 23 SD SAT Cr Function SD SAT Cr 7 0 Description 0x80 default Gain on Cr channel 0 dB 0x00 Gain Cb channel 42 dB OxFF Gain on Cb channel 6 dB SD OFF Cb 7 0 SD Offset Cb Channel Address 0xE1 7 0 This register allows the user to select an offset for data on the Cb channel only and adjust the hue of the picture There is a functional overlap with the Hue 7 0 register Table 24 50 OFF Cb Function HUE 7 0 Hue Adjust Address 0 0 7 0 This register contains the value for the color hue adjustment It allows the user to adjust the hue of the picture HUEQ 7 0 has a range of 90 with 0x00 equivalent to an adjustment of 0
127. m lines of CTAPSN 01 memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 CTAPSN 1 0 Chroma Adapts 3 lines 2 lines Comb Taps NTSC ol 1 Not used 1 0 Adapts 5 lines lines 1 1 Adapts 5 lines 4 lines Rev 0 Page 79 of 96 ADV7183B Subaddress Register Bit Description Bits Comments Notes 0x39 PAL Comb Control YCMP 2 0 Luma Comb mode PAL Adaptive 5 line 3 tap luma comb Use low pass notch Fixed luma comb Top lines of memory Fixed luma comb 5 line All lines of memory 2 2 2 o gt Fixed comb 3 line Bottom lines of memory CCMP 2 0 Chroma Comb mode PAL 3 line adaptive for CTAPSN 01 4 line adaptive for CTAPSN 10 5 line adaptive for CTAPSN 11 Disable chroma comb Fixed 2 line for CTAPSN 01 Top lines of memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 Fixed 3 line for CTAPSN 01 All lines of memory Fixed 4 line for CTAPSN 10 Fixed 5 line for CTAPSN 11 Fixed 2 line for CTAPSN 01 Bottom lines of memory Fixed 3 line for CTAPSN 10 Fixed 4 line for CTAPSN 11 CTAPSP 1 0 Chroma comb taps PAL Adapts 5 lines 2 lines 2 taps Not used Adapts 5 lines 3 lines taps Adapts 5 line
128. me window When CRC ENABLE is 1 default CRC checksum is used to validate the CGMS sequence The CGMSD bit goes high for a valid checksum ADI recommended setting Rev 0 Page 47 of 96 ADV7183B Wide Screen Signaling Data EDTV Data Registers WSS1 7 0 Address 0x91 7 0 WSS2 7 0 Address 0x92 7 0 EDTV1 7 0 Address 0x93 7 0 EDTV2 7 0 Address 0x94 7 0 Figure 31 shows the bit correspondence between the analog EDTV3 7 0 Address 0x95 7 0 video waveform and the WSS1 WSS2 registers WSS2 7 6 are undetermined and should be masked out by software Figure 32 shows the bit correspondence between the analog video waveform and the EDTV1 EDTV2 EDTV3 registers EDTV3 7 6 are undetermined and should be masked out by software EDTV3 5 is reserved for future use and for now contains 0 The three LSBs of the EDTV waveform are currently not supported WSS1 7 0 wssors o 7 RUN IN START ACTIVE SEQUENCE CODE VIDEO 11 0us D 38 4us 42 5us Figure 31 WSS Data Extraction 04997 0 031 Table 57 WSS Access Information Signal Name Register Location Address Register Default Value WSS1 7 0 WSS 1 7 0 145d 0x91 Readback Only 552 5 0 WSS 2 5 0 146d 0x92 Readback Only EDTV1 7 0 EDTV2 7 0 EDTV3 5 0 101112 NOT SUPPORTED 04997 0 032 Figure 32 EDTV Data Extraction Table 58 EDTV Access Information Signal Name Register Location Address Registe
129. mstar compatible Data packets are output if the corresponding enable bit is set see the GDECEL and GDECOL descriptions and if the decoder detects the presence of data This means that for video lines where no data has been decoded no data packet is output even if the corresponding line enable bit is set Each data packet starts immediately after the EAV code of the preceding line See Figure 35 and Table 63 which show the overall structure of the data packet DATA IDENTIFICATION l PREAMBLE FOR ANCILLARY DATA AAT DATA OPTIONAL PADDING CHECK ADV7183B Entries within the packet are as follows e Fixed preamble sequence of 0x00 OxFF 0xFF Data identification word DID The value for the DID marking a Gemstar or CCAP data packet is 0x140 10 bit value e Secondary data identification word SDID contains information about the video line from which data was retrieved whether the Gemstar transmission was of 1x or 2x format and whether it was retrieved from an even or odd field e Data count byte giving the number of user data words that follow User data section Optional padding to ensure that the length of the user data word section of a packet is a multiple of four bytes requirement as set in ITU R BT 1364 e Checksum byte Table 63 lists the values within a generic data packet that is output by the ADV7183B in 8 bit format SECONDARY DATA IDENTIFICATION 04997 0 035 USER DATA
130. n addition to the TOD bit Setting it high forces the output drivers for HS VS and FIELD into the active that is driving state even if the TOD bit is set If set to low the HS VS and FIELD pins are three stated dependent on the TOD bit This functionality is useful if the decoder is to be used as a timing generator only This may be the case if only the timing signals are to be extracted from an incoming signal or if the part is in free run mode where a separate chip can output for instance a company logo For more information on three state control refer to the Three State Output Drivers and the Three State LLC Driver sections Individual drive strength controls are provided via the DR STR XX bits When OE is 0 default HS VS and FIELD are three stated according to the TOD bit When OE is 1 HS VS and FIELD are forced active all the time Drive Strength Selection Data DR STR 1 0 Address OxFA 5 4 For EMC and crosstalk reasons it may be desirable to strengthen or weaken the drive strength of the output drivers The DR 5 1 0 bits affect the P 15 0 output drivers For more information on three state control refer to the Drive Strength Selection Clock and the Drive Strength Selection Sync sections Table 11 STR Function DR STR 1 0 Description 00 Low drive strength 1x 01 default Medium low drive strength 2x 10 Medium high drive strength 3x 11 High drive
131. nable HSync Processor Address 0x01 6 The HSYNC processor is designed to filter incoming HSyncs that have been corrupted by noise providing improved per formance for video signals with stable time bases but poor SNR Setting ENHSPLL to 0 disables the HSync processor Setting ENHSPLL to 1 default enables the HSync processor ENVSPROC Enable VSync Processor Address 0x01 3 This block provides extra filtering of the detected VSyncs to give improved vertical lock Setting ENVSPROC to 0 disables the VSync processor Setting ENVSPROC to 1 default enables the VSync processor Rev 0 Page 46 of 96 ADV7183B VBI DATA DECODE The following low data rate VBI signals can be decoded by the ADV7183B e Wide screen signaling WSS Copy generation management systems CGMS e Closed captioning CCAP EDTV Gemstar 1x and 2x compatible data recovery The presence of any of the above signals is detected and if applicable a parity check is performed The result of this testing is contained in a confidence bit in the VBI Info 7 0 register Users are encouraged to first examine the VBI Info register before reading the corresponding data registers All VBI data decode bits are read only All VBI data registers are double buffered with the field signals This means that data is extracted from the video lines and appears the appropriate registers with the next field transition They are then static until the n
132. ncate to integer value 1822 72 1822 3 Convert to hexadecimal 1822d 0x71E 4 Split into two registers and program Luma Gain Control 1 3 0 0x7 Luma Gain Control 2 7 0 0 1 5 Enable Manual Fixed Gain Mode Set LAGC 2 0 to 000 BETACAM Enable Betacam Levels Address 0x01 5 If YPrPb data is routed through the ADV7183B the automatic gain control modes can target different video input levels as outlined in Table 42 Note that the BETACAM bit is valid only if the input mode is YprPb component The BETACAM bit sets the target value for AGC operation A review of the following sections is useful INSEL 3 0 Input Selection Address 0x00 3 0 to find how component video YprPb can be routed through the ADV7183B e Video Standard Selection to select the various standards for example with and without pedestal The automatic gain control AGC algorithms adjust the levels based on the setting of the BETACAM bit see Table 36 Table 36 BETACAM Function BETACAM Description PW UPD Peak White Update Address 0x2B 0 The peak white and average video algorithms determine the gain based on measurements taken from the active video The PW UPD bit determines the rate of gain change The LAGC 2 0 must be set to the appropriate mode to enable the peak white or average video mode in the first place For more information refer to the LAGC 2 0 Luma Automatic Gain Control Address 0x30 7 0 section Setting PW_
133. nd prediction block The output of this is then used to drive the digital resampling section to ensure that the ADV7183B outputs 720 active pixels per line The sync processing on the ADV7183B also includes the following specialized postprocessing blocks that filter and condition the raw sync information retrieved from the digitized analog video e VSYNC Processor This block provides extra filtering of the detected VSYNCs to give improved vertical lock e HSYNC Processor The HSYNC processor is designed to filter incoming HSYNCs that have been corrupted by noise providing much improved performance for video signals with stable time base but poor SNR VBI DATA RECOVERY The ADV7183B can retrieve the following information from the input video e Wide screen signaling WSS Copy generation management system CGMS e Closed caption CC e Macrovision protection presence EDTV data Gemstar compatible data slicing The ADV7183B is also capable of automatically detecting the incoming video standard with respect to e Color subcarrier frequency e Field rate Line rate The SPD can configure itself to support PAL BGHID PAL M N PAL combination NTSC M NTSC J SECAM 50 Hz 60 Hz NTSC4 43 and PAL60 ADV7183B GENERAL SETUP Video Standard Selection The VID_SEL 3 0 bits allows the user to force the digital core into a specific video standard Under normal circumstances this should not be necessary The VID SEL 3
134. nput Control 2 amplitude step must be to be set to OxOA for tuner input steepened by the CTI block 0x50 CTI DNR TH 7 0 Specifies the Control 4 maximum edge that is interpreted as noise and is therefore blanked Rev 0 Page 81 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 2 1 0 Comments Notes 0x51 Lock CIL 2 0 Count into lock determines 0 0 O 1 line of video Count the number of lines the system must 0 1011 21 of video remain in lock before showing a o 1 5 lines locked status O 1 1 10 lines of video 11 0 0 100 lines of video 1 O 1 500 lines of video 1 1 O 1000 lines of video 1 1 1 100000 lines of video COL 2 0 Count out of lock 1 line of video determines the number of lines the olold 2 lines of video system must remain out of lock zii before showing lost locked status eT OSES 0 1 1 10 lines of video 1 ON 100 lines of video 1 0 1 500 lines of video 11110 1000 lines of video 1 1 1 100000 lines of video SRLS Select raw lock signal Selects 0 Over field with vertical the determination of the lock status info 1 Line to line evaluation FSCLE Fsc lock enable 0 Lock status set
135. o as manual input muxing Refer to Figure 7 for an overview of the two methods of controlling the ADV7183B s input muxing ADI Recommended Input Muxing maximum of 12 CVBS inputs can be connected and decoded by the ADV7183B As seen in Figure 5 this means the sources will have to be connected to adjacent pins on the IC This calls for a careful design of the PCB layout for example ground shielding between all signals routed through tracks that are physically close together INSEL 3 0 Input Selection Address 0x00 3 0 The INSEL bits allow the user to select an input channel as well as the input format Depending on the PCB connections only a subset of the INSEL modes are valid Note that the INSEL 3 0 does not only switch the analog input muxing it also configures the standard definition processor core to process CVBS Comp S Video Y C or component YPbPr format Rev 0 Page 12 of 96 YES SET INSEL 3 0 FOR REQUIRED MUXING CONFIGURATION ADI RECOMMENDED INPUT MUXING SEE TABLE 9 ADV7183B ANALOG SIGNALS NO SET INSEL 3 0 TO CONFIGURE ADV7183B TO DECODE VIDEO FORMAT CVBS 0000 0110 YPrPb 1001 USE MANUAL INPUT MUXING ADC SW MAN EN ADCO SW ADC1 SW ADC2 SW 04997 0 007 Figure 7 Input Muxing Overview Table 8 Input Channel Switching Using INSEL 3 0 Table 9 Input Channel Assignments Description INSEL 3 0 Analog Input Pins Video Format 0000 default C
136. or user programming ADV7183B 4 0 PAL VSync Begin Address 8 4 0 The default value of PVBEG is 00101 indicating the PAL VSync begin position For all NTSC PAL VSync timing controls both the V bit in the AV code and the VSync on the VS pin are modified 1 NOT VALID FOR USER PROGRAMMING YES 1 0 0 1 ADDITIONAL ADDITIONAL DELAY BY DELAY BY 1 LINE 1 LINE 0 0 1 ADVANCE 0 5 LINE ADVANCE 0 5 LINE 04997 0 029 VSYNC END Figure 29 PAL VSync End PVENDDELO PAL VSync End Delay on Odd Field Address 0xE9 7 When PVENDDELO is 0 default there is no delay Setting PVENDDELO to 1 delays VSync going low on an odd field by a line relative to PVEND PVENDDELE PAL VSync End Delay on Even Field Address 0 9 6 When PVENDDELE is 0 default there is no delay Setting PVENDDELE to 1 delays VSync going low on an even field by a line relative to PVEND Rev 0 Page 45 of 96 ADV7183B PVENDSIGN PAL VSync End Sign Address 0xE9 5 Setting PVENDSIGN to 0 default delays the end of VSync Set for user manual programming Setting PVENDSIGN to 1 advances the end of VSync Not recommended for user programming PVEND 4 0 PAL Vsync End Address OxE9 4 0 The default value of PVEND is 10100 indicating the PAL VSync end position For all NTSC PAL VSync timing controls both the V bit in the AV code and the VSync on the VS pin are modified
137. orting of any line count parameters There is no letterbox detected bit The user is asked to read the LCT 7 0 and LB LCB 7 0 register values and to conclude whether or not the letterbox type video is present in software LB LCT 7 0 Letterbox Line Count Top Address 0x9B 7 0 LB LCM 7 0 Letterbox Line Count Mid Address 0x9C 7 0 LB LCB 7 0 Letterbox Line Count Bottom Address 0x9D 7 0 Table 61 LB LCx Access Information Signal Name Address Register Default Value LB LCT 7 0 Ox9B Readback only LB LCM 7 0 9 Readback only LB_LCB 7 0 Ox9D Readback only LB TH 4 0 Letterbox Threshold Control Address 0xDC 4 0 Table 62 LB TH Function LB TH 4 0 Description 01100 Default threshold for detection of black lines default 01101 to Increase threshold need larger active video 10000 content before identifying nonblack lines 00000 to Decrease threshold even small noise levels can 01011 cause the detection of nonblack lines LB SL 3 0 Letterbox Start Line Address 0xDD 7 4 The LB SL 3 0 bits are set at 0100b by default This means that letterbox detection window starts after the EDTV data line For an NTSC signal this window is from Line 23 to Line 286 Changing the bits to 0101 the detection window starts on Line 24 and ends on Line 287 LB 3 0 Letterbox End Line Address 0xDD 3 0 The LB EL 3 0 bits are set at 1101b by default This means that
138. ow during the summation Since all data bytes that are used to calculate the checksum have their 2 LSBs set to 0 the CS 1 0 bits are also always 0 ICS 8 describes the logic inversion of CS 8 The value ICS 8 is included in the checksum entry of the data packet to ensure that the reserved values of 0x00 and OxFF do not occur Table 65 to Table 70 outline the possible data packages Gemstar 2x Format Half Byte Output Mode Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Gemstar 1x Format Half byte output mode is selected by setting CDECAD 0 full byte output mode is selected by setting CDECAD 1 See the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section Rev 0 Page 52 of 96 Table 65 Gemstar 2x Data Half Byte Mode ADV7183B Byte DI9 DI8 DI7 DI6 D 5 DI4 D 2 D 1 D 0 Description 0 0 0 0 0 0 0 0 0 0 0 Fixed preamble 1 1 1 1 1 1 1 1 1 1 1 Fixed preamble 2 1 1 1 1 1 1 1 1 1 1 Fixed preamble 3 0 1 0 1 0 0 0 0 0 0 DID 4 EP EP EF 1 line 3 0 0 0 SDID 5 EP EP 0 0 0 0 1 0 0 0 Data count 6 EP EP 0 0 Gemstar word1 7 4 0 0 User data words 7 EP EP 0 0 Gemstar word1 3 0 0 0 User data words 8 EP EP 0
139. quality signals the system selects from a set of proprietary shaping filter responses that complements comb filter operation in order to reduce visual artifacts The decisions of the control logic are shown in Figure 11 YSFM 4 0 Y Shaping Filter Mode Address 0x17 4 0 The Y shaping filter mode bits allow the user to select from a wide range of low pass and notch filters When switched in automatic mode the filter is selected based on other register selections for example detected video standard as well as properties extracted from the incoming video itself for example quality time base stability The automatic selection always picks the widest possible bandwidth for the video input encountered If the YSFM settings specify a filter that is YSFM is set to values other than 00000 or 00001 the chosen filter is applied to all video regardless of its quality In automatic selection mode the notch filters are only used for bad quality video signals For all other video signals wideband filters are used WYSFMOVR Wideband Y Shaping Filter Override Address 0x18 7 Setting the WYSFMOVR bit enables the use of the 0 settings for good quality video signals For more information refer to the general discussion of the luma shaping filters in the Y Shaping Filter section and the flowchart shown in Figure 11 When WYSFMOVR is 0 the shaping filter for good quality video signals is selected automatically
140. r Default Value EDTV1 7 0 EDTV 1 7 0 147d 0x93 Readback Only EDTV2 7 0 EDTV 2 7 0 148d 0x94 Readback Only EDTV3 7 0 EDTV 3 7 0 149d 0x95 Readback Only Rev 0 Page 48 of 96 CGMS Data Registers CGMS1 7 0 Address 0x96 7 0 CGMS2 7 0 Address 0x97 7 0 CGMS3 7 0 Address 0x98 7 0 Figure 33 shows the bit correspondence between the analog video waveform and the CGMS1 CGMS2 CGMSS registers CGMS3 7 4 are undetermined and should be masked out by software 100 IRE 70 IRE REF 11 2us lt gt CGMS1 7 0 2 235us 20ns Table 59 CGMS Access Information Closed Caption Data Registers CCAP1 7 0 Address 0x99 7 0 CCAP2 7 0 Address 0x9A 7 0 ADV7183B Figure 34 shows the bit correspondence between the analog video waveform and the CCAP1 CCAP2 registers 7 contains the parity bit from the first word CCAP2 7 contains the parity bit from the second word Refer to the GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 section CGMS2 7 0 49 1us 0 5us Figure 33 CGMS Data Extraction CRC SEQUENCE CGMS3 3 0 04997 0 033 Signal Name Register Location Address Register Default Value CGMS1 7 0 CGMS 1 7 0 150d 0x96 Readback Only CGMS2 7 0 CGMS 2 7 0 151d 0x97 Readback Only CGMS3 3 0 CGMS 3 3 0 152d 0x98 Readback Only 10 5 0 25us 12 91us OF lock RUN IN CCAP1 7 0 CCAP2 7
141. ransmitted it is important to perform a fine clamp with high accuracy otherwise brightness variations may occur Further more dynamic changes in the dc level almost certainly lead to visually objectionable artifacts and must therefore be prohibited The clamping scheme has to be able to acquire a newly connected video signal with a completely unknown dc level and it must maintain the dc level during normal operation For quickly acquiring an unknown video signal the large cur rent clamps may be activated It is assumed that the amplitude of the video signal at this point is of a nominal value Control of the coarse and fine current clamp parameters is performed automatically by the decoder Standard definition video signals may have excessive noise on them In particular CVBS signals transmitted by terrestrial broadcast and demodulated using a tuner usually show very large levels of noise gt 100 mV A voltage clamp would be unsuitable for this type of video signal Instead the ADV7183B employs a set of four current sources that can cause coarse gt 0 5 mA and fine lt 0 1 mA currents to flow into and away from the high impedance node that carries the video signal see Figure 10 DATA PRE SDP uz Ju DPP 04997 0 010 Figure 10 Clamping Overview Rev 0 Page 25 of 96 ADV7183B The following sections describe the I C signals that can be used to influence the behavior of the clamps on the ADV7183B
142. red down PWRDN_ADC_1 Address 0x3A 2 When PWRDN_ADC_1 is 0 default the ADC is in normal operation When PWRDN_ADC_1 is 1 ADC 1 is powered down PWRDN 2 Address 0x3A 1 When PWRDN_ADC_2 is 0 default the ADC is in normal operation When PWRDN_ADC_2 is 1 ADC 2 is powered down RESET CONTROL Chip Reset RES Address 0x0F 7 Setting this bit equivalent to controlling the RESET pin on the ADV7183B issues a full chip reset All registers are reset to their default values Some register bits do not have a reset value specified They keep their last written value Those bits are marked as having a reset value of x in the register table After the reset sequence the part immediately starts to acquire the incoming video signal After setting the RES bit or initiating a reset via the pin the part returns to the default mode of operation with respect to its primary mode of operation All bits are loaded with their default values making this bit self clearing Executing a software reset takes approximately 2 ms However it is recommended to wait 5 ms before any further writes are performed The master controller receives a no acknowledge condition on the ninth clock cycle when chip reset is implemented See the MPU Port Description section When RES is 0 default operation is normal When RES is 1 the reset sequence starts Rev 0 Page 15 of 96 ADV7183B GLOBAL PIN CONTR
143. ription Bits Comments Notes 0xC3 ADC SWITCH 1 ADCO SW 3 0 Manual muxing control for ADCO o No connection o AIN1 AIN Al Al Al Al No connection No connection AIN7 210 AIN8 AIN9 AIN10 AIN11 AIN12 2 2 2 y key SETADC sw man 1 ADCI SW 3 0 Manual muxing control for ADC1 a O No connection AIN3 AIN4 xO O AIN5 AIN6 ojo No connection o No connection AIN9 o AIN10 AIN11 ojo AIN12 i 2 2 2 2 o o oi jo joijoijo jo 0 01 SETADC_sw_man_ en 1 OxC4 ADC SWITCH 2 ADC2 SW 3 0 Manual muxing control for ADC2 Reserved No connection No connection AIN2 No connection No connection AIN5 AIN6 No connection No connection No connection AIN8 No connection No
144. s 4 lines 4 taps Ox3A Reserved Set as default PWRDN ADC 2 Enables power down of ADC2 ADC2 normal operation Power down ADC2 PWRDN_ADC_1 Enables power down of ADC1 ADC1 normal operation Power down ADC1 PWRDN_ADC_O Enables power down of ADCO ADCO normal operation Power down ADCO Reserved Set as default 0x3D Manual Window Control Reserved Set to default CKILLTHR 2 0 Kill at 0 5 Kill at 1 5 Kill at 2 5 Kill at 4 Kill at 8 5 Kill at 16 Kill at 32 o WA lolo o WS ol Reserved CKE 1 enables the color kill function and must be enabled for CKILLTHR 2 0 to take effect Reserved Set to default Rev 0 Page 80 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 2 Comments Notes 0x41 Resample Reserved 0 1 00 Set to default Control SFL INV Controls the behavior of 0 SFL compatible with the PAL switch bit ADV7190 ADV7191 ADV7194 encoders 1 SFL compatible with ADV717x ADV7173x encoders Reserved 0 Set to default 0x48 Gemstar GDECEL 15 8 See the Comments GDECEL 15 0 16 LSB Line 10 Control 1 column individual enable bits that MSB Line 25 0x49 Gemstar 7
145. s for YSH and YPK are restored Refer to the BL_C_BVI Blank Chroma during VBI section for information on the chroma path When VBI_EN is 0 default all video lines are filtered scaled When VBI_EN is 1 only the active video region is filtered scaled SD_DUP_AV 0 8 BIT INTERFACE 05 X 9 XY Cb Y Cr Y BUS FF Ko AV CODE SECTION SS AV CODE SECTION AV CODE SECTION fav 04997 0 019 Figure 19 AV Code Duplication Control Rev 0 Page 37 of 96 ADV7183B BL_C_VBI Blank Chroma during VBI Address 0x04 2 Setting BL_C_VBI high the Cr and Cb values of all VBI lines are blanked This is done so any data that may arrive during VBI is not decoded as color and output through Cr and Cb Asa result it should be possible to send VBI lines into the decoder then output them through an encoder again undistorted Without this blanking any wrongly decoded color is encoded by the video encoder therefore the VBI lines are distorted Setting BL_C_VBI to 0 decodes and outputs color during VBI Setting BL_C_VBI to 1 default blanks Cr and Cb values during VBI RANGE Range Selection Address 0x04 0 AV codes as per ITU R BT 656 formerly known as CCIR 656 consist of a fixed header made up of OxFF and 0x00 values These two values are reserved and therefore are not to be used for active video Additionally
146. s on NTSC Line 21 GDECOL 11 must be set To retrieve closed caption data services on PAL Line 22 GDECOL 14 must be set The default value of GDECOL 15 0 is 0x0000 This setting instructs the decoder not to attempt to decode Gemstar or CCAP data from any line in the odd field GDECAD Gemstar Decode Ancillary Data Format Address 0x4C 0 The decoded data from Gemstar compatible transmissions or closed caption is inserted into the horizontal blanking period of the respective line of video There is a potential problem if the retrieved data bytes have the value 0x00 or OxFE In an ITU R BT 656 compatible data stream those values are reserved and used only to form a fixed preamble The GDECAD bit allows the data to be inserted into the horizontal blanking period in two ways e Insert all data straight into the data stream even the reserved values of 0x00 and OxFE if they occur This may violate the output data format specification ITU R 1364 e Split all data into nibbles and insert the half bytes over double the number of cycles in a 4 bit format When GDECAD is 0 the data is split into half bytes and inserted default When GDECAD is 1 the data is output straight in 8 bit format Table 73 NTSC Line Enable Bits and Corresponding Line Numbering Line Number line 3 0 ITU R BT 470 Enable Bit Comment 0 10 GDECOL 0 Gemstar 1 11 GDECOL 1 Gemstar 2 12 GDECOL 2 Gemstar 3 13
147. s switched off 10 MQ Large Clamp Source Current 0 75 mA Large Clamp Sink Current 0 75 mA Fine Clamp Source Current 60 uA Fine Clamp Sink Current 60 uA Rev 0 Page 7 of 96 ADV7183B THERMAL SPECIFICATIONS Table 5 Parameter Symbol Test Conditions Min Max Unit Junction to Case Thermal Resistance 4 layer PCB with solid ground plane 7 6 C W Junction to Ambient Thermal Resistance Still Air BJA 4 layer PCB with solid ground plane 38 1 C W TIMING DIAGRAMS SDA SCLK 8 t4 ta gt OUTPUT LLC 1 OUTPUT LLC 2 OUTPUTS 0 15 VS HS FIELD SFL Figure 2 PC Timing 04997 0 004 Figure 3 Pixel Port and Control Output Timing OE 4 1 I 7 PO P15 HS VS FIELD SFL te 04997 0 005 Figure 4 OE Timing Rev 0 Page 8 of 96 ABSOLUTE MAXIMUM RATINGS Table 6 Parameter Rating Avop to GND AV Avov to AGND AV Dvpp to 2 2V to AGND 2 2V to 4V Dvopio to AVDD 0 3 to 40 3 V to 0 3 V to 0 3 V 0 3 to 2 V Dvppio Dvop 0 3 to 2 V Avpp 0 3V to 2 Dvop 0 3V to 2 V Digital Inputs Voltage to DGND Digital Output Voltage to DGND Analog Inputs to AGND Maximum Junction Temperature max Storage Temperature Range Infrared Reflow Soldering 20 s 0 3V to 0 3 V 0 3V
148. sable autodetect enable 1 Enable 0x08 Contrast CON 7 0 Contrast adjust This is the 10 10 0 10 Luma gain 1 0x00 Gain 0 Register user control for contrast adjustment 0x80 Gain 1 OxFF Gain 2 0x09 Reserved Reserved 1 0 Ox0A Brightness BRI 7 0 This register controls the 0 0 0x00 OIRE Register brightness of the video signal Ox7F 100IRE 0x80 100IRE OxOB Hue HUE 7 0 This register contains the Register value for the color hue adjustment 90 to 90 0x0C Default DEF_VAL_EN Default value enable Free run mode dependent Value Y on DEF_VAL_AUTO_EN Force Free run mode on and output blue screen DEF_VAL_AUTO_EN Default value Disable Free run mode When lock is lost Enable Automatic Free Free run mode can run mode blue screen be enabled to output stable timing clock and a set color DEF_Y 5 0 Default value Y This Y 7 0 DEF_Y 5 0 0 0 Default Y value register holds the Y default value output in Free run mode 0x0D Default DEF_C 7 0 Default value C The Cr 0 1 Cr 7 0 DEF_C 7 4 0 0 0 Default Cb Cr value Value C and Cb default values are defined in 0 output Free run this register Cb 7 0 DEF_C 3 0 0 0 mode Default values 0 O give blue screen output OxOE ADI Reserved Set as Default Control SUB_USR_EN Enables the user to access the interrupt map Access User Reg Map Access Interrupt Re
149. settings have no effect As soon as the part leaves peak white AGC LAGT becomes relevant again The update speed for the peak white algorithm can be custom ized by the use of internal parameters Contact ADI for more information LAGT 1 0 Description 00 Slow TC 2 sec 01 Medium TC 1 sec 10 Fast TC 0 2 sec 11 default Adaptive LG 11 0 Luma Gain Address 0x2F 3 0 Address 0x30 7 0 LMG 11 0 Luma Manual Gain Address Ox2F 3 0 Address 0x30 7 0 Luma gain 11 0 is a dual function register If written to a desired manual luma gain can be programmed This gain becomes active if the LAGC 2 0 mode is switched to manual fixed gain Equation 1 shows how to calculate a desired gain If read back this register returns the current gain value Depending on the setting in the LAGC 2 0 bits this is one of the following values e Luma manual gain value LAGC 2 0 set to luma manual gain mode e Luma automatic gain value LAGC 2 0 set to any of the automatic modes Table 35 LG LMG Function LG 11 0 LMG 11 0 Read Write Description LMG 11 0 2 X Write Manual gain for luma path LG 11 0 Read Actually used gain 0 lt LG 4095 _ 2048 Luma _Gain 0 2 1 0 31 96 ADV7183B For example program the ADV7183B into manual fixed gain mode with a desired gain of 0 89 1 Use Equation 1 to convert the gain 0 89 x 2048 1822 72 2 Tru
150. sition Set for user manual programming Setting NFTOGSIGN to 1 default advances the field transition Not recommended for user programming Rev 0 Page 43 of 96 ADV7183B NFTOG 4 0 NTSC Field Toggle Address OxE7 4 0 Table 56 Recommended User Settings for PAL see Figure 27 The default value of NFTOG is 00011 indicating the NTSC Register Register Name Write Field toggle position 0x31 VSync Field Control 1 0x12 0x32 VSync Field Control 2 0x81 For all NTSC PAL Field timing controls both the F bit in the 0x33 VSync Field Control 3 0x84 AV code and the Field signal on the FIELD DE pin are modified 0x37 Polarity 0x29 OxE8 PAL_V_Bit_Beg 0x1 OxE9 PAL_V_Bit_End 0x4 OxEA PAL_F_Bit_Tog 0x6 FIELD 1 ca EE 622 1623 624 625 1 2 3 4 5 6 7 8 9 10 22 Ai OUTPUT du 2 VIDEO it Ell PVBEG 4 0 0x5 PVEND 4 0 0x4 F 4 PFTOG 4 0 0x3 2232200 FIELD 2 1 310 i 311 312 313 315 316 317 318 319 320 321 322 335 gi ourPur e rM VIDEO PVBEG 4 0 0x5 PVEND 4 0 0x4 i _ 2 F 4 PFTOG 4 0 0x3 04997 0 026 Figure 26 PAL Default BT 656 The polarity of H V and F is embedded in the data FIELD 1 622 11 1623 624 65 1 2 3 4 5 7 9 10 119980 Bi a i d t 1 output ii VIDEO j HS OUTP
151. smitted address The R W bit determines the direction of the data Logic 0 on the LSB of the first byte means the master writes information to the peripheral Logic 1 on the LSB of the first byte means the master reads information from the peripheral The ADV7183B acts as a standard slave device on the bus The data on the SDA pin is eight bits long supporting the 7 bit addresses plus the R W bit The ADV7183B has 249 subad dresses to enable access to the internal registers It therefore interprets the first byte as the device address and the second byte as the starting subaddress The subaddresses auto increment allowing data to be written to or read from the starting sub address A data transfer is always terminated by a stop condition The user can also access any unique subaddress register on a one by one basis without updating all the registers Stop and start conditions can be detected at any stage during the data transfer If these conditions are asserted out of sequence with normal read and write operations they cause an immediate jump to the idle condition During a given SCLK high period the user should only issue one start condition one stop condition or a single stop condition followed by a single start condition If an invalid subaddress is issued by the user the ADV7183B does not issue an acknowledge and returns to the idle condition If in auto increment mode the user exceeds the highest subaddress the following action is
152. t 1 596 010 Kill at 796 Kill at 2 596 011 Kill at 896 Kill at 4 096 100 default Kill at 9 596 Kill at 8 596 101 Kill at 1596 Kill at 16 096 110 Kill at 3296 Kill at 32 096 111 Reserved for ADI internal use only Do not select CHROMA TRANSIENT IMPROVEMENT CTI The signal bandwidth allocated for chroma is typically much smaller than that of luminance In the past this was a valid way to fit a color video signal into a given overall bandwidth because the human eye is less sensitive to chrominance than to luminance The uneven bandwidth however may lead to visual artifacts in sharp color transitions At the border of two bars of color both components luma and chroma change at the same time see Figure 18 Due to the higher bandwidth the signal transition of the luma component is usually a lot sharper than that of the chroma component The color edge is not sharp but blurred in the worst case over several pixels LUMA SIGNAL WITH A TRANSITION ACCOMPANIED LUMA BY A CHROMA TRANSITION SIGNAL 7 fo ORIGINAL SLOW CHROMA DEMODULATED 2 TRANSITION PRIOR SIGNAL SHARPENED CHROMA T TRANSITION AT THE 5 OUTPUT OF CTI 3 Figure 18 Luma Chroma Transition Rev 0 Page 33 of 96 ADV7183B The chroma transient improvement block examines the input video data It detects transitions of chroma and can be
153. t 8 and off See CKILLTHR 2 0 Reserved 1 Set to default 0 2 AGC Mode CAGC 1 0 Chroma automatic gain 0 0 Manual fixed gain Use CMG 11 0 Control control selects the basic mode of 0 1 Use luma gain for chroma operation for the AGC in the chroma ta path 1 0 Automatic gain Based color burst 1 1 Freeze chroma gain Reserved 1 Set to 1 LAGC 2 0 Luma automatic gain 100 Manual fixed gain Use LMG 11 0 control selects the mode of 0 0 1 AGC no override through Blank level to sync tip operation for the gain control in the white peak Man IRE luma path control 1 1 AGC auto override Blank level to sync tip through peak white Man IRE control 1111 AGC no override through Blank level to sync tip peak white Auto IRE control auto override Blank level to sync tip through peak white Auto IRE control 110 1 AGC active video with peak white 1 110 AGC active video with average video 1 1 1 Freeze gain Reserved 1 Set to 1 Rev 0 Page 77 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 Comments Notes Ox2D Chroma CMG 11 8 Chroma manual gain can 0 CAGC 1 0 settings Gain be used to program a desired decide in which Control 1 manual chroma gain Reading back mode CMG 11 0 from this register in AGC mode gives operates the current gain
154. t format This means INSEL must still be used to tell the ADV7183B whether the input signal is of component YC or CVBS format Table 10 Manual Mux Settings All ADCs SETADC sw man en 1 ADCO sw 3 0 ADCO Connected To ADC1 sw 3 0 0000 No Connection 0000 0001 AIN1 0001 0010 AIN2 0010 0011 AIN3 0011 0100 AIN4 0100 0101 5 0101 0110 AING 0110 0111 No Connection 0111 1000 No Connection 1000 1001 AIN7 1001 1010 AIN8 1010 1011 AIN9 1011 1100 AIN10 1100 1101 AIN11 1101 1110 AIN12 1110 1111 No Connection 1111 ADC1 Connected To ADC2 sw 3 0 ADC2 Connected To No Connection 0000 No Connection No Connection 0001 No Connection No Connection 0010 AIN2 AIN3 0011 No Connection 0100 No Connection 5 0101 AIN5 AING 0110 AING No Connection 0111 No Connection No Connection 1000 No Connection No Connection 1001 No Connection No Connection 1010 AIN8 AIN9 1011 No Connection AIN10 1100 No Connection AIN11 1101 AIN11 AIN12 1110 AIN12 No Connection 1111 No Connection Rev 0 Page 14 of 96 ADV7183B GLOBAL CONTROL REGISTERS Register control bits listed in this section affect the whole chip POWER SAVE MODES Power Down PDBP Address 0x0F 2 The digital core of the ADV7183B can be shut down by using a pin PWRDN and a bit PWRDN see below The PDBP controls which of the two has the higher priority The default is to give the pin PWRDN priority This allows the user to have
155. t the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSEHO is 0 default the VS pin goes low inactive at the middle of a line of video odd field When VSEHO is 1 the VS pin changes state at the start of a line odd field VSEHE VS End Horizontal Position Even Address 0x33 6 The VSEHO and VSEHE bits select the position within a line at which the VS pin not the bit in the AV code becomes active Some follow on chips require the VS pin to change state only when HS is high low When VSEHE is 0 default the VS pin goes low inactive at the middle of a line of video even field When VSEHE is 1 the VS pin changes state at the start of a line even field PVS Polarity VS Address 0x37 5 The polarity of the VS pin can be inverted using the PVS bit When PVS is 0 default VS is active high When PVS is 1 VS is active low Rev 0 Page 40 of 96 ADV7183B PF Polarity FIELD Address 0x37 3 The polarity of the FIELD pin can be inverted using the PF bit When PF is 0 default FIELD is active high When PF is 1 FIELD is active low FIELD 1 OUTPUT VIDEO NVEND 4 0 0x4 BT 656 4 i REG 0x04 BIT 7 1 NFTOG 4 0 0x3 FIELD 2 2651 266 267 268 269 270 2711 2721 273 OUTPUT VIDEO 4 0 0x3 APPLIES IF NEMAVMODE 0 MUST BE MANUALLY S
156. the SD_LOCK bit is either masked or cleared Interrupt Drive Level The ADV7183B resets with open drain enabled and all interrupts masked off Therefore INTRQ will be in a high impedance state after reset 01 or 10 has to be written to INTRQ_OP_SEL 1 0 for a logic level to be driven out from the INTRQ pin It is also possible to write to a register in the ADV7183B that manually asserts the INTRQ pin This bitis MPU 5 INTRQ Multiple Interrupt Events If interrupt event 1 occurs and then interrupt event 2 occurs before the system controller has cleared or masked interrupt event 1 the ADV7183B will not generate a second interrupt signal The system controller should check all unmasked interrupt status bits as more than one may be active Macrovision Interrupt Selection Bits The user can select between pseudo sync pulse and color stripe detection as follows INTRQ SEL 1 0 Macrovision Interrupt Selection Bits Address 0x40 Interrupt Space 5 4 Table 77 MV INTRQ SEL MV INTRQ SEL 1 0 Description 00 Reserved 01 default Pseudo Sync Only 10 Colour Stripe Only 11 Either Pseudo Sync or Color Stripe Additional information relating to the interrupt system is detailed in Table 83 Rev 0 Page 58 of 96 ADV7183B PIXEL PORT CONFIGURATION The ADV7183B has a very flexible pixel port that can be SWPC Swap Pixel Cr Cb Address 0x27 7 configured in a variety of formats to accommodate downs
157. the ITU specifies that the nominal range for video should be restricted to values between 16 and 235 for luma and 16 to 240 for chroma The RANGE bit allows the user to limit the range of values output by the ADV7183B to the recommended value range In any case it ensures that the reserved values of 255d and 00d 0x00 are not presented on the output pins unless they are part of an AV code header Table 51 RANGE Function LTA 1 0 Luma Timing Adjust Address 0x27 1 0 The Luma Timing Adjust register allows the user to specify a timing difference between chroma and luma samples Note that there is a certain functionality overlap with the CTA 2 0 register For manual programming use the following defaults e CVBS input LTA 1 0 00 e YC input LTA 1 0 01 e input LTA 1 0 01 Table 52 LTA Function LTA 1 0 Description 00 default No delay 01 Luma 1 clk 37 ns delayed 10 Luma 2clk 74 ns early 11 Luma 1 clk 37 ns early RANGE Description 0 16 lt Y lt 235 16 lt 240 1 default 1 lt Y lt 254 1 lt lt 254 Automatic Programmed Delay Control Address 0x27 6 Enabling the AUTO_PDC_EN function activates a function within the ADV7183B that automatically programs the LTA 1 0 and CTA 2 0 to have the chroma and luma data match delays for all modes of operation If set manual registers LTA 1 0 and CTA 2 0 are not used If
158. the part SFL compatible with ADV717x ADV7173x encoders Lock Related Controls Lock information is presented to the user through Bits 1 0 of the Status 1 register See the STATUS 1 7 0 Address 0x10 7 0 section Figure 9 outlines the signal flow and the controls available to influence the way the lock status information is generated FILTER THE RAW LOCK SIGNAL CIL 2 0 COL 2 0 STATUS 1 0 STATUS 1 1 MEMORY 04997 0 009 Figure 9 Lock Related Signal Path Rev 0 Page 22 of 96 SRLS Select Raw Lock Signal Address 0x51 6 Using the SRLS bit the user can choose between two sources for determining the lock status per Bits 1 0 in the Status 1 register The time_win signal is based on a line to line evaluation of the horizontal synchronization pulse of the incoming video It reacts quite quickly The free_run signal evaluates the properties of the incoming video over several fields and takes vertical synchronization information into account Setting SRLS to 0 default selects the free_run signal Setting SRLS to 1 selects the time_win signal FSCLE Fsc Lock Enable Address 0x51 7 The FSCLE bit allows the user to choose whether the status of the color subcarrier loop is taken into account when the overall lock status is determined and presented via Bits 1 0 in Status Register 1 This bit must be set to 0 when operating in YPrPb component mode to generate a reliable HLOCK status bit Setting
159. tream ICs Table 78 and Table 79 summarize the various functions that This bit allows aque Gb samples to be swapped the ADV7183B s pins can have in different modes of operation When SWPC is 0 default no swapping is allowed The ordering of components for example Cr versus Cb When SWPC is 1 the Cr and values be swapped CHA B C can be changed Refer to the SWPC Swap Pixel Cr Cb Address 0x27 7 section Table 78 indicates the default Output Selection LLC_PAD_SEL 2 0 positions for the Cr Cb components Address 0 8 6 4 The following write allows the user to select between the OF_SEL 3 0 Output Format Selection Address 0x03 5 2 LLC1 nominally at 27 MHz and LLC2 nominally at 13 5 MHz The modes in which the ADV7183B pixel port can be configured are under the control of OF_SEL 3 0 See Table 79 The LLC2 signal is useful for LLC2 compatible wide bus for details 16 bit output modes See OF SEL 3 0 Output Format Selection Address 0x03 5 2 for additional information The The default LLC frequency output on the LLCI pin is approxi LLC2 signal and data on the data bus are synchronized By mately 27 MHz For modes that operate with a nominal data default the rising edge of LLC1 LLC2 is aligned with the Y rate of 13 5 MHz 0001 0010 the clock frequency on the LLC1 data the falling edge occurs when the data bus holds C data pin stays at the higher rate of 27 MHz For information on Th
160. ws the user to select the 16 lt Y lt 235 16 lt C lt 240 ITU R BT 656 Output range of output values Can be 1 lt lt 254 1 lt lt 254 Extended range Control BT656 compliant or can fill the whole accessible number range EN_SFL_PIN SFL output is disabled SFL output enables SFL information output on encoder and decoder the SFL pin to be connected directly BL_C_VBI Blank Chroma during VBI 0 Decode and output color During VBI If set enables data in the VBI region 1 Blank Cr and Cb to be passed through the decoder undistorted TIM OE Timing signals output 0 HS VS F three stated Controlled by TOD enable 1 HS VS F forced active Reserved x x Reserved 1 BT656 4 Allows the user to select 0 BT656 3 complatible an output mode compatible with 1 BT656 4 compatible ITU R BT656 3 4 Rev 0 Page 72 of 96 ADV7183B Bits Subaddress Register Bit Description 716 5 4 3 Comments Notes 0x07 Autodetect AD PAL EN PAL B G I H autodetect Disable Enable enable Enable AD NTSC EN NTSC autodetect Disable enable Enable AD PALM EN PAL M autodetect Disable enable Enable AD PALN EN PAL N autodetect 0 Disable enable 1 Enable AD P60 EN PAL 60 autodetect 0 Disable enable 1 Enable AD N443 EN NTSC443 autodetect 0 Disable enable 1 Enable AD SECAM EN SECAM autodetect 0 Disable enable 1 Enable SEC525 EN SECAM 525 0 Di

ADV7183B Video Decoder manual

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