TN1177 - LatticeECP3 sysIO Usage Guide
Contents
1. Dersting Users can assign for a bank using the Setting option in the Design Planner See the software online help for a more detailed description of this setting 9 22 s LATTICE SEMICONDUCTOR LatticeECP3 syslO Usage Guide Figure 9 5 Veer Assignment in Design Planner E SpreadSheet View cntbuf Ipf Fie Edit View Preference Tools Hep 46 3 cnibur Input Ports 6 Output Ports eg 36 Bidir Ports m KH Nets n cells FI PT4B ESR amp Hg BD C Box pericaiFrecuercy Vf wou cock 7 MuticycteMndeey Pm Vet 4 550 A 8 m Group ty ak w 10 TYPI LVCMOS25 0 LVCMOS25 55101 OF LVCMOS25 OF FIO PT amp A FIO PT136B FK PR34A FIO PRAE FK PRS2A FO PRSZB FIOPLS24 FIO PLS2B lojv m ojo Biz Undo Modity Port Attributes Clock Attributes Net Attributes Cel Attributes Global Elock Period Frequency vOut Cicck MutiCycleMaxDelay Dereting 9 23 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide Appendix C syslO Attributes Using the Diamond Spreadsheet View User Interface syslO buffer attributes can be2. Output Standard Drive Vecio Nominal Single Ended Interfaces LVTTL 4mA 8mA 12mA 16mA 20mA 3 3 LVCMOS33 4mA 8mA 12mA 16mA 20mA 3 3 LVCMOS25 4mA 8mA 12mA 16mA 20mA 2 5 LVCMOS18 4mA 8mA 12mA 16mA 20mA 1 8 LVCMOS15 4mA 8mA 12mA 16mA 20mA 1 5 LVCMOS12 2mA 4mA 6mA 8 12mA 16mA 20mA 1 2 PCI33 N A 3 3 HSTL18 Class 8mA 12mA 1 8 HSTL18 Class 11 N A 1 8 HSTL15 Class 4mA 8mA 1 5 SSTL33 Class II N A 3 3 SSTL25 Class 8mA 12mA 2 5 SSTL25 Class II 16mA 20mA 2 5 SSTL18 Class N A 1 8 SSTL18 Class II 8mA 12mA 1 8 SSTL15 10mA 1 5 Differential Interfaces Differential HSTL18 Class 8mA 12mA 1 8 Differential HSTL18 Class II N A 1 8 Differential HSTL15 Class 4mA 8mA 1 5 Differential SSTL33 Class 11 N A 3 3 Differential SSTL25 Class 8mA 12mA 2 5 Differential SSTL25 Class II 16mA 20mA 2 5 Differential SSTL18 Class N A 1 8 Differential SSTL18 Class II 8mA 12mA 1 8 Differential SSTL15 10mA 1 5 LVDS N A 2 5 Point to Point LVDS PPLVDS N A 2 5 3 3 RSDS RSDSE N A 2 5 Mini LVDS N A 2 5 MLVDS N A 2 5 BLVDS N A 2 5 LVPECL N A 3 3 1 Multiple Drive supported using DiffDrive and MultDrive 2 Emulated with LVCMOS drivers and external resistors 3 This drive strength is only available when the output is configured as open drain syslO Banking Scheme LatticeECP3 devices have six general purpose programmable syslO banks and a seventh configuration bank Each of the six gen
3. SEMICONDUCTOR Usage Guide August 2013 Technical Note TN1177 Introduction The LatticeECP3 syslIO buffers give the designer the ability to easily interface with other devices using advanced system I O standards This technical note describes the syslO standards available and how to imple ment them using Lattice s ispLEVER design software syslO Buffer Overview The LatticeECP3 syslO interface contains multiple Programmable I O Cell PIC blocks Each PIC contains two Programmable I Os PIO PIOA and PIOB that are connected to their respective syslO buffers Two adjacent can be joined to provide a differential I O pair labeled as T and C Each PIO includes a syslO buffer and I O logic IOLOGIC The LatticeECP3 syslO buffers support a variety of sin gle ended and differential signaling standards The syslO buffer also supports the DQS strobe signal that is required for interfacing with the DDR memory of every 12 PIOs in the LattiteECP3 contains a delay element to facilitate the generation of DQS signals The DQS signal from the bus is used to strobe the DDR data from the memory into input register blocks For more information on the architecture of the syslO buffer refer to the LatticeECP3 Family Data Sheet The IOLOGIC includes input output and tristate registers that implement both single data rate SDR and double data rate DDR applications along with the necessary clock and data selection logic Progr
4. TYPE attribute IO TYPE string _ attribute IO_TYPE of Pinname signal is IO_TYPE Value attribute OPENDRAIN string OPENORANY attribute OPENDRAIN of Pinname signal is OpenDrain Value DRIVE attribute DRIVE string attribute DRIVE of Pinname signal is Drive Value attribute DIFFDRIVE string DIFEDRIVE attribute DIFFDRIVE of Pinname signal is Diffdrive Value attribute MULTIDRIVE string MUE DRINE attribute MULTIDRIVE of Pinname signal is MULTIDRIVE Value EQ_CAL attribute EQ_CAL string attribute EQ_CAL of Pinname signal is EQ_CAL Value attribute TERMINATEVTT string attribute TERMINATEVTT of Pinname signal is TERMINATEVTT Value attribute DIFFRESISTOR string attribute DIFFRESISTOR of Pinname signal is DIFFRESISTOR Value attribute PULLMODE string TERMINATEVTT DIFFRESISTOR PULLMODE attribute PULLMODE of Pinname signal is Pullmode Value attribute PCICLAMP string attribute PCICLAMP of Pinname signal is PCIClamp Value attribute PULLMODE string SLEWRATE attribute PULLMODE of Pinname signal is Slewrate Value DIN attribute DIN string attribute DIN of Pinname signal is attribute DOUT string DOUT attribute DOUT of Pinname signal is LOC attribute LOC string attribute LOC of Pinname signal is pin_locations attribute FIXEDDELAY string FIXEDDELAY attribute FI
5. Single Ended I O Standard Programmable Drive mA HSTL15 HSTL15D 1 4 8 HSTL18 l HSTL18D 1 8 12 SSTL25_I SSTL25D 1 8 12 SSTL25_II SSTL25D Il 16 20 SSTL18 Il SSTL18D Il 8 12 LVCMOS 12 with PCI Clamp OFF 4 8 12 16 20 LVCMOS 12 with PCI Clamp ON 2 6 LVCMOS 15 with PCI Clamp OFF 4 8 12 16 20 LVCMOS 15 with PCI Clamp ON 4 8 LVCMOS 18 with PCI Clamp OFF 4 8 12 16 20 LVCMOS 18 with PCI Clamp ON 4 8 12 16 LVCMOS25 4 8 12 16 20 LVCMOS33 4 8 12 16 20 LVTTL 4 8 12 16 20 Programmable Slew Rate Each LVCMOS or LVTTL output buffer pin also has a programmable output slew rate control that can be configured for either low noise or high speed performance Each I O pin has an individual slew rate control This allows designers to specify slew rate control on a pin by pin basis This slew rate control affects both the rising edge and the falling edges Open Drain Control All LVCMOS and LVTTL output buffers can be configured to function as open drain outputs The user can imple ment an open drain output by turning on the OPENDRAIN attribute in the software 9 8 os LatticeECP3 syslO H L ATTICE Usage Guide Differential SSTL and HSTL Support The single ended driver associated with the complementary C pad can optionally be driven by the complement of the data that drives the single ended driver associated with the true pad This allows a pair of single end
6. lVCMOS25 OFF UP NA FAST OFF OFF OFF NA NA Ni 2 Clock input N A i LVCMOS25 OFF uP NA FAST OFF OFF OFF NA 0 Input Port Na seio NES vone FAST OFF OFF OFF NA 0 42 Output Port N A 2 LVCMOS33 OFF UP 12 OFF OFF OFF NA NA 52 Output Port NA E13 SSTLIB OFF NONE NA FAST OFF OFF OFF 6 OutputPort c N A 887181 OFF NONE NA OFF OFF OFF NA NA S Y a d lt Port Assignments Pin Assiqnments Clock Resource Route Priority Cell Mapping Global Preferences Timing Preferences Group Misc Preferences Architecture LatticeECP3 Device LFE3 95EA Package FPBGA484 9 z Mr Users can create a VREF pin using the Spreadsheet view as shown in Figure 9 7 and then assign VREF for a bank using the VREF Column in the Ports Assignment Tab of the Spreadsheet View as show in Figure 9 8 See the Dia mond online help for a more detailed description of this setting Figure 9 7 Creating a VREF in Spreadsheet View Create New VREF VREF Name Pad Name 348 PLS2A PLS2B PRS2B PRS2A PR34B PR34A PT136B 7 6 6 3 3 2 2 1 vv Ca Ce e 9 24 LatticeECP3 syslO LAT TICE Usage Guide EN SEMICONDUCTOR Figure 9 8 Assigning a VREF for an Input Port in Spreadsheet View Type Name Group by Pin Bank ref IO TYPE TERMINATEVTT 1 2 Al Ports N A A N A LVCMOS25 OFF 2 W Input Port Dir N A LVCMOS25 OFF LVCMOS25 OFF 3 B Clock Input Cik
7. string DIFFRESISTOR assignment for I O Pin ATTRIBUTE DIFFRESISTOR OF portB SIGNAL IS 80 9 18 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide PULLMODE Attribute Declaration ATTRIBUTE PULLMODE string PULLMODE assignment for I O Pin ATTRIBUTE PULLMODE OF portA SIGNAL IS DOWN ATTRIBUTE PULLMODE OF portB SIGNAL IS UP PCICLAMP kkk Attribute Declaration ATTRIBUTE PCICLAMP string PULLMODE assignment for I O Pin ATTRIBUTE PCICLAMP OF portA SIGNAL IS OFF SLEWRATE kkk Attribute Declaration ATTRIBUTE SLEWRATE string SLEWRATE assignment for I O Pin ATTRIBUTE SLEWRATE OF portB SIGNAL IS FAST DIN DOUT Attribute Declaration ATTRIBUTE din string ATTRIBUTE dout string assignment for I O Pin ATTRIBUTE din OF input vector SIGNAL IS ATTRIBUTE dout OF output vector SIGNAL IS kkk LOC Attribute Declaration ATTRIBUTE LOC string LOC assignment for I O Pin ATTRIBUTE LOC OF input_vector SIGNAL IS E3 B3 C3 FIXEDDELAY Attribute Declaration ATTRIBUTE FIXEDDELAY string FIXEDDELAY assignment for I O Pin ATTRIBUTE FIXEDDELAY OF portA SIGNAL IS True kkk 9 19 LAT TICE SEMICONDUCTOR Verilog Synplicity This section lists syntax and examples for all the syslO Attributes in Veril
8. 4 D Input Port Cir 5 Input Port OE lt Port Assignments Pin Assignments Clock Resource Route Priority Cell Mapping Global Preferences Timing Preferences Gr Vana SSTL18_ OFF UA LVCMOS25 OFF 9 25
9. 9 Verilog Synplicity Attribute Syntax table Corrected information in the Syntax column June 2012 02 0 Supported Input Standards table Updated VCCIO column and removed GTL 4 row Supported Output Standards table Updated VCCIO information for Point to Point LVDS Mixed Voltage Support in Top Banks table Updated footnote 2 Mixed Voltage Support in Left and Right Banks table Updated footnote 1 March 2013 02 1 Mixed Voltage Support in Top Banks table Updated footnote 2 August 2013 02 2 Updated DRIVE Settings table Updated Technical Support Assistance information 9 16 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide Appendix A HDL Attributes Using HDL attributes you can assign the syslO attributes directly in your source code You will need to use the attribute definition and syntax for the synthesis vendor you are planning to use Below is a list of the syslO attri butes syntax and examples for the Synplify Pro synthesis tool This section only lists the syslO buffer attributes for these devices You can refer to the Synplify Pro user manual for a complete list of synthesis attributes You can access these manuals through the ispLEVER software Help VHDL Synplify Pro This section lists syntax and examples for all the syslO attributes in VHDL when using Synplify Pro synthesis tools Syntax Table 9 20 VHDL Attribute Syntax for Synplify Pro Attribute Syntax
10. Termination can be dynamic for bidirectional pins enabled when output buffer is put in tristate or static always on Hot Socketing Support The I Os located on the top and bottom sides of the device are fully hot socketable The top side of the device simultaneously supports hot socketing mixed voltage support within a bank and programmable clamp diodes for supporting PCI The I Os located on the left and right sides of the device do not support hot socketing See the LatticeECP3 Family Data Sheet for hot socketing IDK requirements 9 5 LatticeECP3 syslO zs LAT TICE Usage Guide SEMICONDUCTOR Mixed Voltage Support in a Bank The LatticeECP3 syslO buffer is connected to three parallel ratioed input buffers These three parallel buffers are connected to Vccio Vecaux and to Vcc giving support for thresholds that track with Vccio as well as fixed thresh olds for 3 3V Vccaux and 1 2V Vcc inputs This allows the input threshold for ratioed buffers to be assigned on a pin by pin basis rather than have it track with Vccio This option is available for all 1 2V 2 5V and 3 3V ratioed inputs and is independent of the bank Vccio voltage on the top banks when PCICLAMP is OFF In the left and right banks the PCICLAMP is always enabled to clamp any currents when Vispur is higher than Vccio Hence only 1 2 inputs and 2 5 inputs are allowed independent of Vccio as long as the ViNpur is less than For example if the bank Vcc
11. 25E LVPECL LVPECL LVPECL LVPECL BLVDS BLVDS BLVDS BLVDS RSDSE RSDSE RSDSE RSDSE Inputs All Single ended and All Single ended All Single ended All Single ended Differential TRLVDS Differential Differential Differential Transition Reduced LVDS Clock Inputs All Single ended All Single ended All Single ended All Single ended Differential Differential Differential Differential Hot Socketing Yes No Yes No Equalization on Inputs No Yes No Yes ISI Correction For DDR3 memory For DDR3 memory For DDR3 memory For DDR3 memory On Chip Termination No On Chip Parallel Termina tion On Chip Differential Termination No On Chip Parallel Termi nation On Chip Differential Termination PCI Support with or without PCI33 with clamp with clamp with clamp clamp 1 These differential standards are implemented by using a complementary LVCMOS driver with the external resistor pack 2 Available on 50 of the I Os in the bank 3 I Os in Bank 8 are shared with sysCONFIG pins and do not support true LVDS and DDR registers 4 I Os in Bank 8 do not support equalization 5 I Os in Bank 8 do not have a programmable clamp setting PCI clamp is always on in Bank 8 9 7 os LatticeECP3 syslO SEMICONDUCTOR syslO Buffer Configurations This section describes the various syslO features available on the LatticeECP3 FPGAs Bus Maintenance Cir
12. DRIVE The DIFFDRIVE setting is used to set the differential drive setting for the Mini LVDS driver when the driver setting needs to be adjusted to support variation in external termination An I O bank can have differential outputs with the same DIFFDRIVE setting Differential outputs with different DIFFDRIVE settings cannot be placed in the same I O bank Table 9 11 DIFFDRIVE Values WO Standard MULTDRIVEValues Default MINILVDS 1 6 1 65 1 7 1 75 1 81 1 87 1 93 2 0 1 6 LVDS 1 75 1 75 RSDS 2 0 2 0 PPLVDS 2 0 2 0 MULTDRIVE DIFFDRIVE only partially supports variation of Mini LVDS driver current Therefore in addition to DIFFDRIVE MULTDRIVE settings must be used to adjust the output drive strength of Mini LVDS Table 9 12 MULTDRIVE Values I O Standard MULTDRIVE Values Default MINILVDS 1x 2x 3x 4x 1x WDS x T 2 RSDS 1x 1x PPLVDS 1x 1x 9 12 os LatticeECP3 syslO SEMICONDUCTOR TERMINATEVTT This attribute is used to set the on chip parallel termination to VTT for reference buffer inputs VTT pins in corre sponding banks should be connected externally to the correct level VTT of the bank should be left floating if this termination is not used Table 9 13 TERMINATEVTT Values Attribute Values Default TERMINATEVTT OFF 40 50 60 OFF DIFFRESISTOR This attribute is used to set the on chip differential terminat
13. FF 1 75 2 0 000 4 TrStatePot 0 3 VA 1 0825 OFF NONE 12 FAST ON OFF OFF NA 0000 5 Bidi Port WA LVCMOS25 OFF up 12 FAST ON OFF OFF NA NA 0 0 000 6 Port LVCMOS25 OFF up 12 FAST ON OFF OFF NA NA 0 0000 7 BidiPort VA SSTLISO OFF NONE 10 SLOW ON OFF OFF NA NA 0 0 000 8 BdPot Bi N A LVCMOS25 OFF UP 12 FAST ON OFF OFF NA NA 0 0000 91 AIPORTS UA NA WA LVCMOS25 OFF UP FAST OFF OFF OFF NA NA NIA WA I 10 Clockinput Cik w NONE NA FAST ON OFF OFF NA NA 0 N A 1i InputPort Cir VA LVCMOS28 OFF up NA FAST OFF OFF OFF NA NA 2 NA 0 12 Input Port Dir WA LVCMOS28 OFF up NA FAST OFF OFF OFF Port Attrixdos Clock Attrbufes Net Alfritutes Cel Global Block PeriodFrequency IvOul Clock Maticycle MexDesory Derating archiechee enfe Denies FERITE Dicke FPP 288 Figure 9 4 Cell Attributes Tab 22 SpreadSheet View cntbuf Ipf Fie Edt View Preference Tools Help il amp 8 amp B BO 02 Ferixirrequency BF Cock BS MuticycleMaxDelay Vref Z 550 a6 A W cntbuf amp t Input Ports 71 FlipFlops count 3 T g Output Ports 2 1 FlipFtops count 0 True RA Bidir Ports count_1 True H Nets 18 4 FlipFlops count 2 True Port Attrioutes Clock Attrioutes Net Attributes Cel attributes G obal Block PenodiFrequency Ir Out Clock
14. OS12 3 3V PCI PCI33 1 These differential standards are implemented by using the complementary LYCMOS driver and external resistor pack 2 Supported on 50 of the pairs on the left and right sides of the device 3 Only inputs supported Available only on the top side of the device LVCMOS and LVTTL IO standards can be set to Open Drain configuration by using the OPENDRAIN attribute When configuring I Os on the left and right banks to be Open Drain it is required that the external pull up be less than the bank Vecio Table 9 9 Open Drain Attribute Values Attribute OPENDRAIN Values Default ON OFF OFF 9 11 EI LatticeECP3 syslO SEMICONDUCTOR DRIVE The DRIVE attribute will set the programmable drive strength for the output standards that have programmable drive capability Table 9 10 DRIVE Settings Output Standard DRIVE mA Default mA HSTL15 1 HSTL15D 4 8 8 HSTL18_l HSTL18D 8 12 12 SSTL25_I SSTL25D 1 8 12 8 SSTL25_II SSTL25D 16 20 16 SSTL18 I SSTL18D 8 12 12 LVCMOS12 without OPENDRAIN 2 6 6 LVCMOS12 with OPENDRAIN 4 8 12 16 20 12 LVCMOS15 without OPENDRAIN 4 8 8 LVCMOS15 with OPENDRAIN 4 8 12 16 20 12 LVCMOS18 without OPENDRAIN 4 8 12 16 12 LVCMOS18 with OPENDRAIN 4 8 12 16 20 12 LVCMOS25 4 8 12 16 20 12 LVCMOS33 4 8 12 16 20 12 LVTTL 4 8 12 16 20 12 DIFF
15. Supported Per Bank Table 9 6 I O Standards Supported per Bank Description Top Side Right Side Bottom Side Left Side Types of I O Buffers Single ended Single ended and Single ended Single ended and Differential Differential Single Ended Stan LVTTL LVTTL LVTTL LVTTL dards Outputs LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS25 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS18 LVCMOS15 LVCMOS15 LVCMOS15 LVCMOS15 LVCMOS12 LVCMOS12 LVCMOS12 LVCMOS12 SSTL15 SSTL15 SSTL15 SSTL15 SSTL18 Class 11 SSTL18 Class II SSTL18 Class 11 SSTL18 Class 11 SSTL25 Class I 11 SSTL25 Class Il SSTL2 Class Il SSTL2 Class 11 SSTL33 Class 11 SSTL33 Class II SSTL3 Class II SSTL3 Class II HSTL15 Class HSTL15 Class HSTL15 Class HSTL15 Class HSTL18 Il HSTL18 Class Il HSTL18 Class Il HSTL18 Class Il Differential Standards LVCMOS33D LVCMOS33D LVCMOS33D LVCMOS33D Outputs SSTL15D SSTL15D SSTL15D SSTL15D SSTL18D Class II SSTL18D Class Il SSTL18D Class II SSTL18D Class II SSTL25D Class II SSTL25D Class Il SSTL25D Class Il SSTL25D Class Il SSTL33D Class II SSTL33D Class l II SSTL33D Class I SSTL33D_I Il HSTL15D Class HSTL15D Class HSTL15D Class HSTL15D Class HSTL18D Class Il HSTL18D Class II HSTL18D Class l HSTL18D Class II LVDS LVDS RSDS RSDS Mini LVDS Mini LVDS PPLVDS point to point PPLVDS point to point LVDS25E LVDS25E LVDS25E LVDS
16. XEDELAY of Pinname signal is FIXEDDELAY Value Examples lO TYPE kkk Attribute Declaration ATTRIBUTE IO_TYPE string O TYPE assignment for I O Pin 9 17 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide ATTRIBUTE IO TYPE OF portA SIGNAL IS ATTRIBUTE IO TYPE OF portB SIGNAL IS LVCMOS33 ATTRIBUTE IO TYPE OF portC SIGNAL IS LVDS25 OPENDRAIN Attribute Declaration ATTRIBUTE OPENDRAIN string Open Drain assignment for I O Pin ATTRIBUTE OPENDRAIN OF portB SIGNAL IS ON DRIVE Attribute Declaration ATTRIBUTE DRIVE string DRIVE assignment for I O Pin ATTRIBUTE DRIVE OF portB SIGNAL IS 20 DIFFDRIVE Attribute Declaration ATTRIBUTE DIFFDRIVE string DIFFDRIVE assignment for I O Pin ATTRIBUTE DIFFDRIVE OF portB SIGNAL IS 2 0 MULTDRIVE Attribute Declaration ATTRIBUTE MULTDRIVE string MULTDRIVE assignment for I O Pin ATTRIBUTE MULTDRIVE OF portB SIGNAL IS 2X EQ_CAL Attribute Declaration ATTRIBUTE EQ_CAL string EQ CAL assignment for I O Pin ATTRIBUTE EQ_CAL OF portB SIGNAL IS 1 TERMINATEVTT Attribute Declaration ATTRIBUTE TERMINATEVTT string TERMINATEVTT assignment for I O Pin ATTRIBUTE TERMINATEVTT OF portB SIGNAL IS 40 DIFFERESISTOR Attribute Declaration ATTRIBUTE DIFFRESISTOR
17. ammable delay lines and dedicated logic within the IOLOGIC are used to provide the required shift to incoming clock and data signals and the delay required by DQS inputs in DDR memory The DDR implementation in the IOLOGIC and the DDR memory interface support are discussed in more detail in TN1180 LatticeECP3 High Speed I O Interface Supported syslO Standards The LatticeECP3 syslO buffer supports both single ended and differential standards Single ended standards can be further subdivided into internally ratioed standard such as LVCMOS LVTTL and PCI and externally referenced standards such as HSTL and SSTL The buffers support the LVTTL LVCMOS 1 2 1 5 1 8 2 5 and 3 3V stan dards In the LVCMOS and LVTTL modes the buffer has individually configurable options for drive strength bus maintenance weak pull up weak pull down or a bus keeper latch Other single ended standards supported include SSTL and HSTL Differential standards supported include LVDS RSDS BLVDS LVPECL differential SSTL and differential HSTL LatticeECP3 also support mini LVDS PPLVDS Point to Point LVDS and TRLVDS Transition Reduced LVDS Table 1 lists the syslO standards supported the LatticeECP3 devices 2013 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The s
18. and a auxiliary supply that powers the differential and referenced input buffers VccAux is used to supply I O reference voltage requiring 3 3V to satisfy the common mode range of the drivers and input buffers Vecu 1 2V 1 5V 1 8V 2 5V 3 3V The JTAG pins have a separate power supply that is independent of the bank Vccio supplies deter mines the electrical characteristics of the LVCMOS JTAG pins both the output high level and the input threshold Table 9 3 contains a summary of the required power supplies Table 9 3 Power Supplies Power Supply Description Value Vcc Core power supply 1 2V Vccio Power supply for the I O and configuration banks 1 2V 1 5V 1 8V 2 5V 3 3V VCCAUX Auxiliary power supply 3 3V VccJ Power supply for JTAG pins 1 2V 1 5V 1 8V 2 5V 3 3V 1 Refer to the LatticeECP3 Family Data Sheet for recommended min and max values Input Reference Voltage VREF2 Each bank can support up to two separate input voltages and that are used to set the thresh old for the referenced input buffers The location of these pins is pre determined within the bank These pins can be used as regular I Os if the bank does not require a voltage VREF1 for DDR Memory Interface When interfacing to DDR memory the input must be used as the reference voltage for the DQS and DQ input from the memory A voltage
19. assigned using the Spreadsheet view in the Lattice Diamond design software The Port Assignments Sheet lists all the ports in a design and all the available syslO attributes in multiple columns Click on each of these cells for a list of all the valid I O preferences for that port Each column takes precedence over the next Therefore when you choose a particular IO TYPE the columns for the DRIVE PULLMODE SLE WRATE and other attributes will only list the valid entries for that IO TYPE Pin locations can be locked using the Pin column of the Port Assignments sheet or using the Pin Assignments sheet You can right click on a cell and go to Assign Pins to see a list of available pins The Spreadsheet View also has an option to run a DRC check to check for any incorrect pin assignments You can enter the DIN DOUT preferences using the Cell Mapping tab All the preferences assigned using the Spreadsheet view are written into the logical preference file Ipf Figure 9 5 shows the Port Assignments Sheet of the Spreadsheet view For further information on how to use the Spreadsheet view refer to the Diamond Help documentation available in the Help menu option of the software Figure 9 6 Port Attributes Tab of SpreadSheet View Y Spreadsheet View File Edit View Design Window Help en Type Name Group Pin 110 706 TERMINATEVTT PULLMODE DRIVE SLEWRATE PCICLAMP OPENDRAIN DIFFRESISTOR DIFFORIVE MULTDRIVE Ey CAL 95 All Ports N A i A
20. cuit Each of the LVCMOS LVTTL and PCI types of inputs has a weak pull up weak pull down and weak bus keeper capability The pull up and pull down settings offer a fixed characteristic which is useful in creating wired logic such as wired ORs However current can be slightly higher than other options depending on the signal state The bus keeper option latches the signal in the last driven state holding it at a valid level with minimal power dissipation You can also choose to turn off the bus maintenance circuitry minimizing power dissipation and input leakage Note that in this case it is important to ensure that inputs are driven to a known state to avoid unnecessary power dissipation in the input buffer On the outputs the weak pull ups are on at all times Users have the option to turn off the pull up setting in the soft ware Programmable Drive Each LVCMOS or LVTTL as well as some of the referenced SSTL and HSTL output buffers has a programmable drive strength option This option can be set for each I O independently The drive strength settings available are 2mA 4mA 6mA 8mA 12mA 16mA and 20 Actual options available vary by I O voltage The user must con sider the maximum allowable current per bank and the package thermal limit current when selecting the drive strength Table 9 7 shows the available drive settings for each of the output standards Table 9 7 Programmable Drive Values for Single Ended Buffers
21. divider between Vref and GND is used to generate an on chip reference volt age that is used by the DQS transition detector circuit This voltage divider is only present on it is not avail able on Vrero For further information on the DQS transition detect logic and its implementation refer to TN1180 LatticeECP3 High Speed I O Interface When not used as VREF these predefined voltage reference pins are avail able as user I O pins For DDR1 memory interfaces the VREF1 should be connected to 1 25V since only SSTL25 signaling is allowed For DDR2 memory interfaces VREF1 should be connected to 0 9V since only SSTL18 signaling is allowed For DDR3 memory interfaces VREF1 should be connected to 0 75V since only SSTL15 signaling is allowed VTT Termination Voltage The VTT termination voltage on LatticeECP3 device is used for the referenced standard termination and common mode differential termination These termination voltage pins are available on the left and right of the device only Use of VTT is optional these pins should be left floating if termination to VTT is not required The allowable range for VTT is from 0 5V to 1 25V independent of the value of VCCIO The user decides the best termination voltage to apply to VTT Many applications will choose VTT to be nominally equal to the switching threshold of the interface standard being used with a tolerance of 5 and this is usually equal to half of the driver supply voltage VTT
22. e ports in a design and all the available syslO attributes as preferences Click on each of these cells for a list of all the valid I O preferences for that port Each column takes precedence over the next Therefore when you choose a particular TYPE the columns for the DRIVE PULLMODE SLEW RATE and other attributes will only list the valid combinations for that IO TYPE Pin locations can be locked using the pin location column of the Pin Attribute sheet Right click on a cell to list all the available pin locations The Design Planner will also run a DRC check to check for any incorrect pin assignments You can enter the DIN DOUT preferences using the Cell Attributes Sheet of the Design Planner All the prefer ences assigned using the Design Planner are written into the logical preference file Figures 9 3 and 9 4 show the Port Attribute Sheet and the Cell Attribute Sheet views of the Design Planner For fur ther information on how to use the Design Planner refer to the ispLEVER Help documentation available in the Help menu option of the software Figure 9 3 Port Attributes Tab of Design Planner SpreadSheet View Bank Es lE e TYPE TENAR Hope werd pex pares Ie DIFFDRIVE UTP ls Ed aen Outioad TriState Port az we MOS25 OFF 0 000 TriState Port Q1 vA LVCMOS25 OFF NONE FAST ON OFF OFF NA NA 0 000 131 TristatePot 20 7 LvOS25 OFF NONE NA SLOW ON OFF O
23. ed drivers to be used to drive complementary outputs with the lowest possible skew between the signals This is used for driv ing complementary SSTL and HSTL signals as required by the differential SSTL and HSTL clock inputs on syn chronous DRAM and synchronous SRAM devices respectively This capability is also used in conjunction with off chip resistors to emulate LVPECL and BLVDS output drivers PCI Support with Programmable PCICLAMP Each syslO buffer can be configured to support PCI33 The buffers on the top of the device have an optional PCI clamp diode that may optionally be specified in the ispLEVER design tools The programmable PCICLAMP be turned ON or OFF This option is available on each I O independently only on the top side banks For the other three sides of the device the PCICLAMP is always ON Differential I O Support 50 of the syslO buffer pairs on the left and right edges contain a differential output driver that can optionally drive the pads in the pair The standards support on these differential output pairs is as follows LVDS Point to Point LVDS PPLVDS Mini LVDS e RSDS All the other pins on all the sides of the device can support Emulated Differential standards using complementary LVCMOS drivers with external resistors The standards supported using differential output pairs is as follows BLVDS LVDS25E RSDSE LVPECL The LatticeECP3 Family Data Sheet lists the LVCMOS drivers and e
24. eral purpose syslO banks has a VCCIO supply voltage and two reference voltages VREF1 and VREF2 Figure 9 1 shows the six general purpose banks and the configuration bank with associated supplies Bank 8 is a bank dedicated to configuration logic and has seven dedicated configuration I Os and 14 multiplexed configuration I Os Bank 8 has the power supply pads VCCIO and VCCAUX but does not have VREF pads 9 3 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide On the top and bottom banks the syslO buffer pair consists of two single ended output drivers and two sets of sin gle ended input buffers both ratioed and referenced The left and right syslO buffer pair consists of two single ended output drivers and two sets of single ended input buffers both ratioed and referenced The referenced input buffer can also be configured as a differential input In 50 of the pairs there is also one differential output driver The two pads in the pair are described as true and comp where the true pad is associated with the positive side of the differential input buffer and the comp complementary pad is associated with the negative side of the differ ential input buffer Figure 9 1 sysIO Banking TOP lt lt lt om lt D m Jj D m m om m S289 S289 9 90 oS 5220 g c cw w S m ee cn cam
25. f these attributes in detail lO TYPE This attribute is used to set the syslO standard for an I O The Vccio required to set these I O standards are embedded in the attribute name itself There is no separate attribute to set the VCCIO requirements Table 9 8 lists the available I O types 9 10 zs LAT TICE SEMICONDUCTOR Table 9 8 IO_TYPE Attribute Values OPENDRAIN LatticeECP3 syslO Usage Guide syslO Signaling Standard IO TYPE DEFAULT LVCMOS25 LVDS 2 5V LVDS25 Point to Point LVDS PPLVDS Mini LVDS MINILVDS RSDS RSDS Transition Reduced LVDS TRLVDS Emulated LVDS 2 5V LVDS25E Bus LVDS 2 5V BLVDS25 LVPECL 3 3V LVPECL33 Emulated RSDS RSDSE MLVDS MLVDS HSTL18 Class and II HSTL18 1 HTSL18 Il Differential HSTL 18 Class and Il HSTL18D HSTL18D II HSTL 15 Class HSTL15 I Differential HSTL 15 Class I HSTL15D 1 SSTL 33 Class and II SSTL33 I SSTL33 Il Differential SSTL 33 Class and II SSTL33D I SSTL3D II SSTL 25 Class and II SSTL25 1 SSTL25 Il Differential SSTL 25 Class and Il SSTL25D I SSTL25D II SSTL 18 Class and II SSTL18 1 SSTL18 Il Differential SSTL 18 Class and II SSTL18D I SSTL18D II SSTL 15 SSTL15 LVTTL LVTTL33 3 3V LVCMOS LVCMOS33 3 3V LVCMOS Differential LVCMOS33D 2 5V LVCMOS LVCMOS25 1 8V LVCMOS LVCMOS18 1 5V LVCMOS LVCMOS15 1 2V LVCMOS LVCM
26. he VTT pin On chip termination is available on the left and right sides of the device The VTT pin should be left to float when using common mode differential termination Termination can be set to be dynamic for bidirec tional buffers where the termination is active only when the output buffer is disabled through the tristate control External termination to VTT should be used when implementing the DDR2 and DDR3 memory interfaces Equalization Setting Equalization filtering is available for single ended inputs on both true and complementary I Os and for differential inputs on the true I Os Equalization is required to compensate for the difficulty of sampling alternating logic transi tions with a relatively slow slew rate It is useful for the input DDR modes used in DDR3 memory and fast SP14 2 mode signaling It is available on the left and right sides Equalization acts as a tunable filter with settings determining the level of correction There are four settings avail able Zero none One Two and Three The equalization logic resides in the I O buffers Each I O can have a unique equalization setting within a DQS 12 group for DDR3 memory Software syslO Attributes syslO attributes can be specified in the HDL using the Preference Editor GUI or in the ASCII Preference file prf directly The appendices of this document provide examples of how these can be assigned using each of the meth ods described above This section describes each o
27. hould be left floating Referenced inputs cannot be used in this bank when DIFFRESISTOR is enabled Technical Support Assistance e mail techsupport latticesemi com Internet www latticesemi com 9 15 zs LAT TICE SEMICONDUCTOR Revision History LatticeECP3 syslO Usage Guide Date Version Change Summary February 2009 01 0 Initial release May 2009 01 1 Updated Mixed Voltage Support in Top Banks table Updated Mixed Voltage Support in Left and Right Banks table Added FIXEDDELAY attribute support for SDR registers August 2009 01 2 Updated On Chip Termination text section Updated DIFFRESISTOR text section Updated Banking Rules bullets April 2010 01 3 Removed support for programmable PCICLAMP equalization and VREF pins in Bank 8 June 2010 01 4 Added Appendix C syslO Attributes Using the Diamond Spreadsheet View User Interface November 2010 01 5 Updated Supported Input Standards table Updated Hot Socketing Support text section Updated Hot Socketing row of the I O Standards Supported per Bank table Updated first footnote in the Mixed Voltage Support in Left and Right Banks table March 2011 01 6 Added support for GTL input standard using HSTL input buffer April 2011 01 7 Updated to clarify PCICLAMP programmability and DRIVE settings availably with and without OPENDRAIN February 2012 01 8 Updated document with new corporate logo March 2012 01
28. io is 1 8V and PCICLAMP is OFF it is possible to have 1 2V and 3 3V ratioed input buffers with fixed thresholds as well as 2 5V ratioed inputs with tracking thresholds on the top bank On the left and right banks when Vecio is 1 8V it is possible to have only 1 2V with fixed thresholds But if the Vccio on the left and right sides is 3 3V it is possible to have a 1 2V input with fixed thresholds as well as 2 5V with tracking thresholds Prior to device configuration the ratioed input thresholds track the bank Vecio This option only takes effect after configuration Output standards within a bank are always set by Vccio but can drive a lower output standard into a device that is tolerant up to that Vccio Tables 9 4 and 9 5 shows the syslO standards that can be mixed in the same bank Table 9 4 Mixed Voltage Support in Top Banks Input syslO Standards 3 5 Output syslO Standards Vecio 1 2V 1 5V 1 8V 2 5V 3 3V 1 2V 1 5V 1 8V 2 5V 3 3V 1 2V Yes Yes Yes Yes 1 5V Yes Yes Yes Yes Yes 1 8V Yes Yes Yes Yes Yes 2 5V Yes Yes Yes Yes 3 3V Yes Yes Yes Yes 1 Mixed voltage input support is available on the top banks only when PCICLAMP is OFF All differential input buffers except LVPECL33 and TRLVDS be supported in banks independent of Vccio LVPECL33 can be placed on top side independent of Vccio when PCICLAMP is OFF 1 5V and 1 8V HSTL and SSTL reference inputs can be supported o
29. ion using common mode termination to VTT This on chip termination is optimized to work primarily for the LVDS I O type When the DIFFRESISTOR attribute is set the VTT pin should be left floating Table 9 14 DIFFRESISTOR Values Attribute Values Default DIFFRESISTOR OFF 80 100 120 OFF EQ CAL This attribute is used to set the Equalization setting available on the input pins on the left and right sides of the device EQ CAL is not available in Bank 8 Table 9 15 EQ CAL Values Attribute Values Default EQ CAL 0 1 2 3 4 0 PULLMODE The PULLMODE attribute is available for all the LVTLL and LVCMOS inputs and outputs This attribute can be enabled for each I O independently Table 9 16 PULLMODE Values PULL Options PULLMODE Value Pull up Default UP Pull Down DOWN Bus Keeper KEEPER Pull Off NONE Table 9 17 PULLMODE Settings Buffer Values Default Input UP DOWN KEEPER NONE UP Output UP DOWN KEEPER NONE UP PCICLAMP PCICLAMP is available on all the pads of the device On the top of the device the PCICLAMP setting can be option ally turned OFF The rest of the banks only support the PCICLAMP value ON 9 13 EI LatticeECP3 syslO SEMICONDUCTOR Table 9 18 PCICLAMP Values Attribute Values Default OFF ON SLEWRATE SLEWRATE attribute is available for all LVTTL a
30. n banks with any Vccio 2 5V SSTL reference inputs can be supported on banks with Vccio set to 1 8V 2 5V or 3 3V 3 3V SSTL reference inputs be supported on banks with Vccio set to 2 5V or 3 3V When output is configured as open drain it can be placed in bank independent of Vecio N Table 9 5 Mixed Voltage Support in Left and Right Banks Input syslO Standards 34 Output syslO Standards VCCIO 1 2V 1 5V 1 8V 2 5V 3 3V 1 2V 1 5V 1 8V 2 5V 3 3V 1 2V Yes Yes 1 5V Yes Yes Yes 1 8V Yes Yes Yes 2 5V Yes Yes Yes 3 3V Yes Yes Yes Yes 1 All differential input buffers except LVPECL33 and TRLVDS can be supported on banks with Vccio set to 2 5V or 3 3V LVPECL and TRLVDS require VCCIO of 3 3V If the Vccio is set to 1 8V or 1 5V this reduces the max and max to approximately 1 7V as the PCICLAMP is always enabled on this side when the gt Vccio of the bank 1 5V and 1 8V HSTL and SSTL reference inputs can be supported on banks with any 2 5V SSTL reference inputs can be supported on banks with Vccio set to 1 8V 2 5V or 3 3V 3 3V SSTL reference inputs can be supported on banks with Vccio set to 2 5V or 3 3V When output is configured as open drain it can be placed in bank independent of Vecio ar G 9 6 sm LAT TICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide syslO Standards
31. nd LVCMOS output drivers Each I O pin has an individual slew rate control This allows designers to specify slew rate control on a pin by pin basis Table 9 19 Slew Rate Values Attribute Values Default SLEWRATE FAST SLOW SLOW INBUF By default all the unused input buffers are disabled The INBUF attribute is used to enable the unused input buffers when performing a boundary scan test This is a global attribute and can be globally set to ON and OFF e Values ON OFF Default OFF FIXEDDELAY This attribute can be used in HDL to enable the input Fixed Delay on the input of an SDR Input register When set to TRUE you can achieve a zero hold time on the input register Value TRUE FALSE Default FALSE DIN DOUT This attribute can be used when an I O register needs to be assigned Using DIN asserts an input register and using DOUT asserts an output register in the design By default the software will attempt to assign the I O regis ters if applicable Users can turn this OFF by using a synthesis attribute or the ispLEVER Preference Editor These attributes can only be applied on registers LOC This attribute can be used to make pin assignments to the I O ports in the design This attribute is only used when the pin assignments are made in HDL source Pins can also be assigned directly using the GUI in the Preference Editor of the software See the appendices for further information Design Considerati
32. og using Synplicity synthesis tool Syntax LatticeECP3 syslO Usage Guide Table 9 21 Verilog Synplicity Attribute Syntax Attribute Syntax lO PinName synthesis IO 4 Type Value OPENDRAIN PinName synthesis OPENDRAIN OpenDrain Value DRIVE PinName synthesis DRIVE Drive Value DIFFDRIVE PinType PinName synthesis DIFFDRIVE DIFFDRIVE Value MULTDRIVE PinName synthesis MULTDRIVE MULTDRIVE Value EQ CAL PinName synthesis EQ CAL EQ CAL Value TERMINATEVTT PinType PinName synthesis TERMINATEVTT TERMINATEVTT Value DIFFRESISTOR PinType PinName synthesis DIFFRESISTOR DIFFRESISTOR Value PULLMODE PinName synthesis PULLMODE Pullmode Value PCICLAMP PinName synthesis PCICLAMP PCIClamp Value SLEWRATE PinName synthesis SLEWRATE Slewrate Value DIN PinType PinName synthesis DIN DOUT PinType PinName synthesis DOUT LOC PinType PinName synthesis LOC pin_locations FIXEDDELAY PinType PinName synthesis FIXEDDELAY FIXEDDELAY value Examples NO_TYPE PULLMODE SLEWRATE and DRIVE assignment output portB synthesis O_TYPE LVCMOS33 PULLMODE UP SLEWRATE FAST DRIVE 20 output p
33. ons and Usage This section discusses some of design rules and considerations that need to be taken into account when designing with the LatticeECP3 syslO buffer Banking Rules If Vecio or Vcc for any bank is set to 3 3V it is recommended that it be connected to the same power supply as Vecaux thus minimizing leakage If Vccio or Vcc for any bank is set to 1 2V it is recommended that it be connected to the same power supply as Voc thus minimizing leakage When implementing DDR memory interfaces the Vref of the bank is used to provide reference to the interface pins and cannot be used to power any other referenced inputs 9 14 LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide Only the top bank supports programmable PCI clamps On the top banks all legal input buffers should be independent of bank Vccio except for 1 8V and 1 5V buffers which require a bank Vccio of 1 8V and 1 5V On the left and right banks 1 2V input buffers can be assigned to a bank independent of Vccio 2 5V input buffers can be assigned to banks with Vccio 2 5V and 3 3V All other input buffers depend on the to the bank When DIFFRESITOR is used the VTT pin for that bank should be left floating When TERMINATEVTT is used VTT should be connected to the correct voltage depending on the IO TYPE set For example for SSTL18 standards VTT should be connected to 0 9V Both TERMINATEVTT and DIFFRESISTOR use the VTT pin hence the
34. ortC synthesis IO TYPE LVDS25 DIFFRESISTOR input portB synthesis IO TYPE Z LVDS DIFFRESITOR 80 DIFFDRIVE MULTDRIVE output portB synthesis IO TYPEZ MINILVDS DIFFDRIVE 2 2 0 MULTDRIVE 2X TERMINATEVTT EQ CAL input portB synthesis IO 65 15 60 EQ CAL 2 OPENDRAIN output portA synthesis OPENDRAIN ON PCICLAMP output portA synthesis IO PCICLAMP OFF IFIXEDDELAY input portB synthesis FIXEDDELAY true 9 20 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide II Place the flip flops near the load input input load synthesis II Place the flip flops near the outload output output outload synthesis dout pin location input 3 0 DATAO synthesis loc E3 B1 F3 Register pin location reg data in ch1 buf reg3 synthesis loc R40C47 Nectored internal bus reg 3 0 data in 1 reg synthesis loc R40C47 R40C46 R40C45 R40C44 9 21 E LatticeECP3 syslO LAT TICE Usage Guide SEMICONDUCTOR Appendix B syslO Attributes Using the ispLEVER Design Planner User Interface syslO buffer attributes can be assigned using the Design Planner Spreadsheet View available in the ispLEVER design tool If you are using Lattice Diamond design software see Appendix C The Pin Attribute Sheet lists all th
35. pecifications and information herein are subject to change without notice www latticesemi com 9 1 tn1177_02 2 zs LATTICE SEMICONDUCTOR Table 9 1 Supported Input Standards LatticeECP3 syslO Usage Guide Input Standard Vrer Nominal Vecio Nominal Single Ended Interfaces LVTTL 3 3 LVCMOS33 3 3 LVCMOS25 2 5 LVCMOS18 1 8 LVCMOS15 1 5 LVCMOS12 PCI33 HSTL18 Class Il 0 9 HSTL15 Class I 0 75 SSTL33 Class II 1 5 3 3 2 5 SSTL25 Class Il 1 25 3 3 2 5 1 8 SSTL18 Class 11 0 9 SSTL15 0 75 Differential Interfaces Differential SSTL33 Class I 11 3 3 2 5 Differential SSTL18 Class I 11 See Note 2 Differential SSTL25 Class I 11 3 3 2 5 1 8 Differential HSTL15 Class Differential HSTL18 Class 11 Differential SSTL 15 See Note 2 LVDS Transition Reduced LVDS 3 3 LVPECL 3 3 Bus LVDS MLVDS 1 For LVTTL33 LYCMOS33 LVCMOS25 if PCICLAMP is OFF they can be used independently of Vccio in the top banks 2 VREF is required when using Differential SSTL to interface to DDR memory 9 2 zs LATTICE SEMICONDUCTOR Table 9 2 Supported Output Standards LatticeECP3 syslO Usage Guide
36. s ee Say d 1 i 144 aa 1 5 l arn eee Loa 4 F i BANKO BANK1 T vecios VCCJ lt gt i5 GND gt amp VCCIO7 I VCCIO2 VREF1 7 Ix re Lo 2 7 4 15 5 aa VREF2 2 gt ND GND 2 l_ L m rq l VCCIO6 H le p H VCCIOS VREF1 6 12 E VREF1 3 VREF2 6 4 12 e te i VREF2 3 GND SERDES GND pm m P t E ee L 3 Wrap from Left Wrap from Right BOTTOM Vecio 1 2V 1 5V 1 8V 2 5V 3 3V There are a total of six supplies Vccioo Veciog Each bank has a separate Vccio supply that powers the single ended output drivers and the ratioed input buffers such as LVTTL LVCMOS and PCI LVTTL LVCMOS3 3 LVCMOS2 5 and LVCMOS1 2 inputs also have fixed threshold options allowing them to be placed in any bank Tables 9 4 and 9 6 list the allowed mixed voltage support in a given bank The Vccio voltage applied to the bank determines the ratioed input standards that can be supported in that bank It is also used to power the differential output drivers In addition Vccios is used to supply power to the sysCONFIG signals 9 4 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide Vccaux 3 3V In addition to the bank Vccio supplies LatticeECP3 devices have a Vcc core logic power supply
37. se are mutually exclusive in a bank Equalization is only available on the left and right banks PCICLAMP is programmable on the top side banks 0 and 1 For all other banks PCICLAMP is always ON Differential I O Rules All banks can support LVDS input buffers Only the banks on the right and left sides Banks 2 3 6 and 7 will support True Differential output buffers The banks on the top and bottom will support the LVDS input buffers but will not support True LVDS outputs The user can use emulated LVDS output buffers on these banks All banks support emulated differential buffers using the external resistor pack and complementary LVCMOS drivers Only 50 of the I Os on the left and right sides can provide LVDS mini LVDS PPLVDS and RSDS output buffer capability See the LatticeECP3 Family Data Sheet for the pin listing for all the true differential pairs The IO TYPE attribute for a differential buffer can only be assigned to the TRUE pad The ispLEVER design tool will automatically assign the other I O of the differential pair to the complementary pad TRLVDS inputs are only supported on the top banks LVDS MINILVDS RSDS PPDS cannot co exist in one bank An I O bank can only have differential outputs with the same DIFFDRIVE setting Differential outputs with differ ent DIFFDRIVE settings cannot be placed in the same I O bank DIFFRESISTOR termination is only available on the left and right sides If enabled the VTT of the bank s
38. xternal resistor requirements to implement these emulated standards The data sheet also lists the electrical specifications supported for all differential stan dards Differential SSTL and HSTL All single ended syslO buffers pairs support differential SSTL and HSTL Refer to the LatticeECP3 Family Data Sheet for a detailed description of the Differential HSTL and SSTL implementations Differential LVCMOS33 All single ended syslO buffer pairs also support the LVCMOS33D Differential standard with configurable drive strength and slew settings This generic 3 3V differential buffer allows the user to implement any type of 3 3V differ ential buffer by configuring the drive strength and calculating the external resistor values as per the application requirements GTL Input Support GTL inputs can be supported using either the SSTL15 or HSTL15 input standard with VREF set to 1 0V and external VTT termination to 1 5V GTL inputs implemented using this method can support the maximum speed listed for the SSTL and HSTL standards in the LatticeECP3 Family Data Sheet GTL outputs are not supported in the LatticeECP3 device 9 9 E LATTICE LatticeECP3 syslO SEMICONDUCTOR Usage Guide Figure 9 2 GTL Input Buffer Emulation Using HSTL15 Input VTT 1 5V z0 VREF 1 0V 1 HSTL15 On Chip Termination LatticeECP3 devices support on chip Parallel Termination to VTT as well Common mode differential termination using t
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